From adff5e94b0bf9a6365fe305f2a0a47617e40019d Mon Sep 17 00:00:00 2001 From: BernardXiong Date: Sat, 3 Jul 2021 09:48:03 +0800 Subject: [PATCH] [BSP] Add ART-pi smart BSP --- bsp/imx6ull-artpi-smart/.config | 761 + bsp/imx6ull-artpi-smart/Kconfig | 44 + bsp/imx6ull-artpi-smart/README.md | 25 + bsp/imx6ull-artpi-smart/SConscript | 14 + bsp/imx6ull-artpi-smart/SConstruct | 34 + .../applications/SConscript | 11 + bsp/imx6ull-artpi-smart/applications/main.c | 91 + bsp/imx6ull-artpi-smart/applications/mnt.c | 36 + bsp/imx6ull-artpi-smart/drivers/Kconfig | 130 + bsp/imx6ull-artpi-smart/drivers/SConscript | 17 + bsp/imx6ull-artpi-smart/drivers/board.c | 112 + bsp/imx6ull-artpi-smart/drivers/board.h | 48 + bsp/imx6ull-artpi-smart/drivers/bsp_clock.c | 223 + bsp/imx6ull-artpi-smart/drivers/bsp_clock.h | 26 + bsp/imx6ull-artpi-smart/drivers/drv_common.c | 43 + bsp/imx6ull-artpi-smart/drivers/drv_common.h | 35 + bsp/imx6ull-artpi-smart/drivers/drv_eth.c | 380 + bsp/imx6ull-artpi-smart/drivers/drv_eth.h | 42 + bsp/imx6ull-artpi-smart/drivers/drv_i2c.c | 141 + bsp/imx6ull-artpi-smart/drivers/drv_i2c.h | 89 + bsp/imx6ull-artpi-smart/drivers/drv_lcd.c | 188 + bsp/imx6ull-artpi-smart/drivers/drv_lcd.h | 89 + bsp/imx6ull-artpi-smart/drivers/drv_log.h | 27 + bsp/imx6ull-artpi-smart/drivers/drv_pin.c | 568 + bsp/imx6ull-artpi-smart/drivers/drv_pin.h | 19 + bsp/imx6ull-artpi-smart/drivers/drv_rtc.c | 167 + bsp/imx6ull-artpi-smart/drivers/drv_sdhc.c | 322 + bsp/imx6ull-artpi-smart/drivers/drv_sdhc.h | 42 + bsp/imx6ull-artpi-smart/drivers/drv_spi.c | 207 + bsp/imx6ull-artpi-smart/drivers/drv_spi.h | 98 + bsp/imx6ull-artpi-smart/drivers/drv_timer.c | 172 + bsp/imx6ull-artpi-smart/drivers/drv_timer.h | 17 + bsp/imx6ull-artpi-smart/drivers/drv_uart.c | 350 + bsp/imx6ull-artpi-smart/drivers/drv_uart.h | 58 + bsp/imx6ull-artpi-smart/drivers/font.h | 406 + bsp/imx6ull-artpi-smart/drivers/imx6ull.h | 415 + bsp/imx6ull-artpi-smart/drivers/rt_lcd.h | 59 + .../figures/hw_resources.png | Bin 0 -> 181159 bytes bsp/imx6ull-artpi-smart/libraries/SConscript | 15 + .../libraries/sdk/CMSIS/Include/cmsis_gcc.h | 1373 + .../libraries/sdk/CMSIS/SConscript | 10 + .../libraries/sdk/CORTEXA/Include/core_ca.h | 50 + .../libraries/sdk/CORTEXA/Include/core_ca7.h | 1377 + .../sdk/CORTEXA/Include/cortexa_gcc.h | 85 + .../sdk/CORTEXA/Include/cortexa_iar.h | 54 + .../libraries/sdk/CORTEXA/SConscript | 10 + .../libraries/sdk/SConscript | 15 + .../libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.h | 42156 ++++ .../sdk/devices/MCIMX6Y2/MCIMX6Y2.xml | 162023 +++++++++++++++ .../sdk/devices/MCIMX6Y2/MCIMX6Y2_features.h | 801 + .../libraries/sdk/devices/MCIMX6Y2/SConscript | 13 + .../sdk/devices/MCIMX6Y2/drivers/fsl_cache.c | 59 + .../sdk/devices/MCIMX6Y2/drivers/fsl_cache.h | 253 + .../sdk/devices/MCIMX6Y2/drivers/fsl_clock.c | 915 + .../sdk/devices/MCIMX6Y2/drivers/fsl_clock.h | 1177 + .../sdk/devices/MCIMX6Y2/drivers/fsl_common.c | 207 + .../sdk/devices/MCIMX6Y2/drivers/fsl_common.h | 487 + .../sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.c | 778 + .../sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.h | 749 + .../sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.c | 250 + .../sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.h | 659 + .../sdk/devices/MCIMX6Y2/drivers/fsl_enet.c | 1243 + .../sdk/devices/MCIMX6Y2/drivers/fsl_enet.h | 1355 + .../sdk/devices/MCIMX6Y2/drivers/fsl_epit.c | 122 + .../sdk/devices/MCIMX6Y2/drivers/fsl_epit.h | 397 + .../sdk/devices/MCIMX6Y2/drivers/fsl_gpio.c | 156 + .../sdk/devices/MCIMX6Y2/drivers/fsl_gpio.h | 243 + .../sdk/devices/MCIMX6Y2/drivers/fsl_i2c.c | 1376 + .../sdk/devices/MCIMX6Y2/drivers/fsl_i2c.h | 671 + .../sdk/devices/MCIMX6Y2/drivers/fsl_iomuxc.h | 1151 + .../sdk/devices/MCIMX6Y2/drivers/fsl_phy.c | 366 + .../sdk/devices/MCIMX6Y2/drivers/fsl_phy.h | 233 + .../devices/MCIMX6Y2/drivers/fsl_snvs_hp.c | 532 + .../devices/MCIMX6Y2/drivers/fsl_snvs_hp.h | 324 + .../sdk/devices/MCIMX6Y2/drivers/fsl_uart.c | 1275 + .../sdk/devices/MCIMX6Y2/drivers/fsl_uart.h | 870 + .../sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.c | 1654 + .../sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.h | 1380 + .../sdk/devices/MCIMX6Y2/drivers/fsl_wdog.c | 141 + .../sdk/devices/MCIMX6Y2/drivers/fsl_wdog.h | 299 + .../devices/MCIMX6Y2/drivers/usdhc/event.c | 145 + .../devices/MCIMX6Y2/drivers/usdhc/event.h | 103 + .../devices/MCIMX6Y2/drivers/usdhc/fsl_card.h | 668 + .../devices/MCIMX6Y2/drivers/usdhc/fsl_host.c | 172 + .../devices/MCIMX6Y2/drivers/usdhc/fsl_host.h | 646 + .../devices/MCIMX6Y2/drivers/usdhc/fsl_sd.c | 1688 + .../devices/MCIMX6Y2/drivers/usdhc/fsl_sdio.c | 1041 + .../MCIMX6Y2/drivers/usdhc/fsl_sdmmc.c | 310 + .../MCIMX6Y2/drivers/usdhc/fsl_sdmmc.h | 150 + .../MCIMX6Y2/drivers/usdhc/fsl_sdspi.c | 1273 + .../MCIMX6Y2/drivers/usdhc/fsl_sdspi.h | 227 + .../drivers/usdhc/fsl_specification.h | 1080 + .../MCIMX6Y2/drivers/usdhc/usdhc_config.h | 49 + .../devices/MCIMX6Y2/fsl_device_registers.h | 59 + .../sdk/devices/MCIMX6Y2/system_MCIMX6Y2.c | 489 + .../sdk/devices/MCIMX6Y2/system_MCIMX6Y2.h | 176 + .../libraries/sdk/devices/SConscript | 15 + bsp/imx6ull-artpi-smart/link.lds | 104 + bsp/imx6ull-artpi-smart/link_smart.lds | 105 + bsp/imx6ull-artpi-smart/mkimage.py | 235 + bsp/imx6ull-artpi-smart/rtconfig.h | 321 + bsp/imx6ull-artpi-smart/rtconfig.py | 47 + 102 files changed, 241913 insertions(+) create mode 100644 bsp/imx6ull-artpi-smart/.config create mode 100644 bsp/imx6ull-artpi-smart/Kconfig create mode 100644 bsp/imx6ull-artpi-smart/README.md create mode 100644 bsp/imx6ull-artpi-smart/SConscript create mode 100644 bsp/imx6ull-artpi-smart/SConstruct create mode 100644 bsp/imx6ull-artpi-smart/applications/SConscript create mode 100644 bsp/imx6ull-artpi-smart/applications/main.c create mode 100644 bsp/imx6ull-artpi-smart/applications/mnt.c create mode 100644 bsp/imx6ull-artpi-smart/drivers/Kconfig create mode 100644 bsp/imx6ull-artpi-smart/drivers/SConscript create mode 100644 bsp/imx6ull-artpi-smart/drivers/board.c create mode 100644 bsp/imx6ull-artpi-smart/drivers/board.h create mode 100644 bsp/imx6ull-artpi-smart/drivers/bsp_clock.c create mode 100644 bsp/imx6ull-artpi-smart/drivers/bsp_clock.h create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_common.c create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_common.h create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_eth.c create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_eth.h create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_i2c.c create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_i2c.h create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_lcd.c create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_lcd.h create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_log.h create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_pin.c create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_pin.h create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_rtc.c create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_sdhc.c create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_sdhc.h create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_spi.c create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_spi.h create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_timer.c create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_timer.h create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_uart.c create mode 100644 bsp/imx6ull-artpi-smart/drivers/drv_uart.h create mode 100644 bsp/imx6ull-artpi-smart/drivers/font.h create mode 100644 bsp/imx6ull-artpi-smart/drivers/imx6ull.h create mode 100644 bsp/imx6ull-artpi-smart/drivers/rt_lcd.h create mode 100644 bsp/imx6ull-artpi-smart/figures/hw_resources.png create mode 100644 bsp/imx6ull-artpi-smart/libraries/SConscript create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/CMSIS/Include/cmsis_gcc.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/CMSIS/SConscript create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/core_ca.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/core_ca7.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/cortexa_gcc.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/cortexa_iar.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/SConscript create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/SConscript create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.xml create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2_features.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/SConscript create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_cache.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_cache.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_clock.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_clock.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_common.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_common.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_enet.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_enet.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_epit.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_epit.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_gpio.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_gpio.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_i2c.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_i2c.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_iomuxc.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_phy.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_phy.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_snvs_hp.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_snvs_hp.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_uart.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_uart.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_wdog.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_wdog.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/event.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/event.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_card.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_host.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_host.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sd.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdio.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdmmc.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdmmc.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdspi.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdspi.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_specification.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/usdhc_config.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/fsl_device_registers.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/system_MCIMX6Y2.c create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/system_MCIMX6Y2.h create mode 100644 bsp/imx6ull-artpi-smart/libraries/sdk/devices/SConscript create mode 100644 bsp/imx6ull-artpi-smart/link.lds create mode 100644 bsp/imx6ull-artpi-smart/link_smart.lds create mode 100644 bsp/imx6ull-artpi-smart/mkimage.py create mode 100644 bsp/imx6ull-artpi-smart/rtconfig.h create mode 100644 bsp/imx6ull-artpi-smart/rtconfig.py diff --git a/bsp/imx6ull-artpi-smart/.config b/bsp/imx6ull-artpi-smart/.config new file mode 100644 index 0000000000..1fb9ad579f --- /dev/null +++ b/bsp/imx6ull-artpi-smart/.config @@ -0,0 +1,761 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_SIGNALS=y + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_MEMTRACE=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +CONFIG_RT_USING_DEVICE_OPS=y +CONFIG_RT_USING_INTERRUPT_INFO=y +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50000 +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_RT_USING_USERSPACE=y +CONFIG_KERNEL_VADDR_START=0xc0000000 +CONFIG_PV_OFFSET=0xc0000000 +# CONFIG_RT_IOREMAP_LATE is not set +CONFIG_ARCH_ARM_CORTEX_A=y +CONFIG_ARCH_ARM_CORTEX_A7=y +CONFIG_RT_BACKTRACE_FUNCTION_NAME=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=8 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +# CONFIG_RT_USING_I2C_BITOPS is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_NEWLIB is not set +CONFIG_RT_USING_MUSL=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +CONFIG_RT_USING_POSIX_CLOCKTIME=y +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +CONFIG_RT_USING_SAL=y + +# +# protocol stack implement +# +CONFIG_SAL_USING_LWIP=y +CONFIG_SAL_USING_POSIX=y + +# +# Network interface device +# +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +CONFIG_NETDEV_USING_IPV6=y +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=1 +CONFIG_NETDEV_IPV6_SCOPES=y + +# +# light weight TCP/IP stack +# +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP202 is not set +CONFIG_RT_USING_LWIP212=y +CONFIG_RT_USING_LWIP_IPV6=y +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_RT_LWIP_DEBUG is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +CONFIG_RT_USING_ULOG=y +# CONFIG_ULOG_OUTPUT_LVL_A is not set +# CONFIG_ULOG_OUTPUT_LVL_E is not set +# CONFIG_ULOG_OUTPUT_LVL_W is not set +# CONFIG_ULOG_OUTPUT_LVL_I is not set +CONFIG_ULOG_OUTPUT_LVL_D=y +CONFIG_ULOG_OUTPUT_LVL=7 +# CONFIG_ULOG_USING_ISR_LOG is not set +CONFIG_ULOG_ASSERT_ENABLE=y +CONFIG_ULOG_LINE_BUF_SIZE=128 +# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set + +# +# log format +# +# CONFIG_ULOG_OUTPUT_FLOAT is not set +CONFIG_ULOG_USING_COLOR=y +CONFIG_ULOG_OUTPUT_TIME=y +# CONFIG_ULOG_TIME_USING_TIMESTAMP is not set +CONFIG_ULOG_OUTPUT_LEVEL=y +CONFIG_ULOG_OUTPUT_TAG=y +# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set +CONFIG_ULOG_BACKEND_USING_CONSOLE=y +# CONFIG_ULOG_USING_FILTER is not set +# CONFIG_ULOG_USING_SYSLOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set +CONFIG_RT_USING_LWP=y +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_RT_LWP_SHM_MAX_NR=64 +CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 +CONFIG_LWP_TID_MAX_NR=64 +# CONFIG_LWP_UNIX98_PTY is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +CONFIG_SOC_IMX6ULL=y +CONFIG_CPU_MCIMX6Y2CVM05=y +CONFIG_FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 +CONFIG_FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL=1 + +# +# Platform Driver Configuration +# + +# +# Select UART Driver +# +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_UART8 is not set + +# +# Select SPI Driver +# +CONFIG_BSP_USING_SPI=y +# CONFIG_BSP_USING_SPI1 is not set +# CONFIG_BSP_USING_SPI2 is not set +CONFIG_BSP_USING_SPI3=y +# CONFIG_BSP_USING_SPI4 is not set + +# +# Select I2C Driver +# +CONFIG_BSP_USING_I2C=y +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_I2C2 is not set +CONFIG_BSP_USING_I2C3=y +CONFIG_I2C3_BAUD_RATE=400000 +# CONFIG_BSP_USING_I2C4 is not set + +# +# Select LCD Driver +# +CONFIG_BSP_USING_LCD=y +CONFIG_BSP_LCD_WIDTH=1024 +CONFIG_BSP_LCD_HEIGHT=600 + +# +# Select SD Card Driver +# +CONFIG_BSP_USING_SDHC=y + +# +# Select RTC Driver +# +CONFIG_BSP_USING_ONCHIP_RTC=y diff --git a/bsp/imx6ull-artpi-smart/Kconfig b/bsp/imx6ull-artpi-smart/Kconfig new file mode 100644 index 0000000000..4d44db2995 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/Kconfig @@ -0,0 +1,44 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_IMX6ULL + bool + select ARCH_ARM_CORTEX_A7 + select RT_USING_CACHE + select ARCH_ARM_MMU + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select RT_USING_FPU + default y + + if SOC_IMX6ULL + config CPU_MCIMX6Y2CVM05 + bool + default y + config FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + depends on RT_USING_CACHE + int + default 1 + config FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL + int "Disable Clock control in fsl files" + default 1 + endif + +source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/imx6ull-artpi-smart/README.md b/bsp/imx6ull-artpi-smart/README.md new file mode 100644 index 0000000000..30825157f3 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/README.md @@ -0,0 +1,25 @@ +# RT-Thread Smart for i.MX6ULL + +这是一份ART-pi smart开发板的BSP，支持smart模式也支持传统的RTOS模式； + +ART-pi smart采用了米尔科技的imx6ull核心板，硬件由韦东山团队完成，由社区来完成整体的BSP。硬件规格情况如下： + +![硬件资源](figures/hw_resources.png) + +## 如何编译 + +如果使用smart的模式，请使用smart sdk环境，然后进入到这个bsp目录，执行 + +```bash +scons +``` + +进行编译； + +如果使用RTOS模式，请确保在menuconfig中不选择smart模式，然后执行 + +```bash +scons +``` + +进行编译。 diff --git a/bsp/imx6ull-artpi-smart/SConscript b/bsp/imx6ull-artpi-smart/SConscript new file mode 100644 index 0000000000..c7ef7659ec --- /dev/null +++ b/bsp/imx6ull-artpi-smart/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imx6ull-artpi-smart/SConstruct b/bsp/imx6ull-artpi-smart/SConstruct new file mode 100644 index 0000000000..15f69a4c5d --- /dev/null +++ b/bsp/imx6ull-artpi-smart/SConstruct @@ -0,0 +1,34 @@ +import os +import sys +import rtconfig + +RTT_ROOT = os.getenv('RTT_ROOT') or os.path.join('..', '..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] +env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +if GetDepend('RT_USING_SMART'): + # use smart link.lds + env['LINKFLAGS'] = env['LINKFLAGS'].replace('link.lds', 'link_smart.lds') + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/imx6ull-artpi-smart/applications/SConscript b/bsp/imx6ull-artpi-smart/applications/SConscript new file mode 100644 index 0000000000..89083a964a --- /dev/null +++ b/bsp/imx6ull-artpi-smart/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/imx6ull-artpi-smart/applications/main.c b/bsp/imx6ull-artpi-smart/applications/main.c new file mode 100644 index 0000000000..38b1c57010 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/applications/main.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/10/7 bernard the first version + */ +#include +#include +#include + +#include +#include "drv_pin.h" + +#define LED_PIN GET_PIN(5, 3) + +int main(void) +{ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + + printf("hello rt-smart\n"); + + for(;;) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + return 0; +} + +#ifdef BSP_USING_LCD +#include "drv_lcd.h" + +struct lcd_info info; + +int imx6ull_elcd_test() +{ + struct rt_device *lcd_dev = RT_NULL; + int buff_size = 0; + rt_uint8_t *red_buff, *green_buff, *blue_buff; + + lcd_dev = (struct rt_device *)rt_device_find("lcd"); + + RT_ASSERT(lcd_dev); + + rt_device_init(lcd_dev); + rt_device_control(lcd_dev, RTGRAPHIC_CTRL_GET_INFO, &info); + + buff_size = info.graphic.width * info.graphic.height * info.graphic.bits_per_pixel /8; + red_buff = (rt_uint8_t *)rt_malloc(buff_size); + green_buff = (rt_uint8_t *)rt_malloc(buff_size); + blue_buff = (rt_uint8_t *)rt_malloc(buff_size); + + for(int i = 0; i < buff_size / 2; i++) + { + red_buff[2 * i] = 0x00; + red_buff[2 * i + 1] = 0x7c; + + green_buff[2 * i] = 0xE0; + green_buff[2 * i + 1] = 0x07; + + blue_buff[2 * i] = 0x1F; + blue_buff[2 * i + 1] = 0x00; + } + + for(int i = 0; i < 50; i++) + { + rt_memcpy(info.graphic.framebuffer, red_buff, buff_size); + rt_device_control(lcd_dev, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); + rt_thread_delay(50); + + rt_memcpy(info.graphic.framebuffer, green_buff, buff_size); + rt_device_control(lcd_dev, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); + rt_thread_delay(50); + + rt_memcpy(info.graphic.framebuffer, blue_buff, buff_size); + rt_device_control(lcd_dev, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); + rt_thread_delay(50); + } + + rt_device_close(lcd_dev); + + return RT_EOK; +} +MSH_CMD_EXPORT(imx6ull_elcd_test, imx6ull_elcd_test); + +#endif diff --git a/bsp/imx6ull-artpi-smart/applications/mnt.c b/bsp/imx6ull-artpi-smart/applications/mnt.c new file mode 100644 index 0000000000..00d6d1dbfb --- /dev/null +++ b/bsp/imx6ull-artpi-smart/applications/mnt.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include + +#ifdef RT_USING_DFS + +#include +#include + +int mnt_init(void) +{ + if (dfs_mount("sd0", "/", "elm", 0, NULL) != 0) + { + rt_kprintf("Dir / mount failed!\n"); + return -1; + } + + rt_thread_mdelay(200); + if (dfs_mount(RT_NULL, "/mnt", "rom", 0, &romfs_root) != 0) + { + rt_kprintf("Dir /mnt mount failed!\n"); + return -1; + } + + rt_kprintf("file system initialization done!\n"); + return 0; +} +INIT_ENV_EXPORT(mnt_init); +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/Kconfig b/bsp/imx6ull-artpi-smart/drivers/Kconfig new file mode 100644 index 0000000000..cf719bcb7e --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/Kconfig @@ -0,0 +1,130 @@ +menu "Platform Driver Configuration" + +menu "Select UART Driver" + if RT_USING_SERIAL + config BSP_USING_UART1 + bool "Enable UART1" + default y + config BSP_USING_UART2 + bool "Enable UART2" + default n + config BSP_USING_UART3 + bool "Enable UART3" + default n + config BSP_USING_UART4 + bool "Enable UART4" + default n + config BSP_USING_UART5 + bool "Enable UART5" + default n + config BSP_USING_UART6 + bool "Enable UART6" + default n + config BSP_USING_UART7 + bool "Enable UART7" + default n + config BSP_USING_UART8 + bool "Enable UART8" + default n + endif +endmenu + +menu "Select SPI Driver" + config BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + default n + + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1" + default n + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + config BSP_USING_SPI3 + bool "Enable SPI3" + default y + config BSP_USING_SPI4 + bool "Enable SPI4" + default n + endif +endmenu + +menu "Select I2C Driver" + config BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default n + + if BSP_USING_I2C + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + if BSP_USING_I2C1 + config I2C1_BAUD_RATE + int "Set i2c1 baud rate (HZ)" + default 100000 + endif + + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + if BSP_USING_I2C2 + config I2C2_BAUD_RATE + int "Set i2c2 baud rate (HZ)" + default 100000 + endif + + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + if BSP_USING_I2C3 + config I2C3_BAUD_RATE + int "Set i2c3 baud rate (HZ)" + default 100000 + endif + + config BSP_USING_I2C4 + bool "Enable I2C4" + default n + if BSP_USING_I2C4 + config I2C4_BAUD_RATE + int "Set i2c4 baud rate (HZ)" + default 100000 + endif + endif +endmenu + +menu "Select LCD Driver" +config BSP_USING_LCD + bool "Enable LCD" + default y + + if BSP_USING_LCD + config BSP_LCD_WIDTH + int "Width of LCD panel" + default 1024 + config BSP_LCD_HEIGHT + int "Height of LCD panel" + default 600 + endif +endmenu + +menu "Select SD Card Driver" + if RT_USING_SDIO + config BSP_USING_SDHC + bool "Enable SDHC" + default n + endif +endmenu + +menu "Select RTC Driver" + if RT_USING_RTC + config BSP_USING_ONCHIP_RTC + bool "Enable On-Chip rtc" + default y + endif +endmenu + +endmenu diff --git a/bsp/imx6ull-artpi-smart/drivers/SConscript b/bsp/imx6ull-artpi-smart/drivers/SConscript new file mode 100644 index 0000000000..7decf58c13 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/SConscript @@ -0,0 +1,17 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('iomux/*.c') +list = os.listdir(cwd) +CPPPATH = [cwd, cwd + '/iomux'] +objs = [] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +objs = objs + group + +Return('objs') diff --git a/bsp/imx6ull-artpi-smart/drivers/board.c b/bsp/imx6ull-artpi-smart/drivers/board.c new file mode 100644 index 0000000000..d7590bc35c --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/board.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-11-20 Bernard the first version + * 2018-11-22 Jesven add rt_hw_spin_lock + * add rt_hw_spin_unlock + * add smp ipi init + */ + +#include +#include +#include + +#include "board.h" + +#include +#ifdef RT_USING_USERSPACE +#include +#include +#endif + +extern size_t MMUTable[]; +rt_mmu_info mmu_info; + +#ifdef RT_USING_USERSPACE +struct mem_desc platform_mem_desc[] = { /* 100ask_imx6ull ddr 512M */ + {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x1FFFFFFF, KERNEL_VADDR_START + PV_OFFSET, NORMAL_MEM} +}; +#else +struct mem_desc platform_mem_desc[] = { + {0x00000000, 0x80000000, 0x00000000, DEVICE_MEM}, + {0x80000000, 0xFFF00000, 0x80000000, NORMAL_MEM} +}; +#endif +const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]); + +void idle_wfi(void) +{ + asm volatile ("wfi"); +} + +/** + * This function will initialize board + */ + +#ifdef RT_USING_USERSPACE +rt_region_t init_page_region = { + (uint32_t)PAGE_START, + (uint32_t)PAGE_END, +}; +#endif + +int board_reboot(int argc, char **argv) +{ + wdog_config_t config; + SRC_Type *src = (SRC_Type*)g_src_vbase; + WDOG_Type *wdog = (WDOG_Type*)g_wdog1_vbase; + + LOG_E("resetting ...\n"); + + rt_hw_ms_delay(50); + + src->SCR &= ~SRC_SCR_WARM_RESET_ENABLE_MASK; + + CLOCK_EnableClock(kCLOCK_Wdog1); + + WDOG_GetDefaultConfig(&config); + config.timeoutValue = 0x00u; + + WDOG_Init(wdog, &config); + + while (1) + { + //waiting... + } + + return 0; +} +MSH_CMD_EXPORT_ALIAS(board_reboot, reboot, reboot system); + +void rt_hw_board_init(void) +{ +#ifdef RT_USING_USERSPACE + rt_hw_mmu_map_init(&mmu_info, (void*)0xf0000000, 0x10000000, MMUTable, PV_OFFSET); + + rt_page_init(init_page_region); + rt_hw_mmu_ioremap_init(&mmu_info, (void*)0xf0000000, 0x10000000); + + arch_kuser_init(&mmu_info, (void*)0xffff0000); +#else + rt_hw_mmu_map_init(&mmu_info, (void*)0x80000000, 0x10000000, MMUTable, 0); + rt_hw_mmu_ioremap_init(&mmu_info, (void*)0x80000000, 0x10000000); +#endif + + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); + + /* initialize system heap */ + rt_system_heap_init(HEAP_BEGIN, HEAP_END); + + SystemAddressMapping(); + SystemClockInit(); + + rt_components_board_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + + rt_thread_idle_sethook(idle_wfi); +} diff --git a/bsp/imx6ull-artpi-smart/drivers/board.h b/bsp/imx6ull-artpi-smart/drivers/board.h new file mode 100644 index 0000000000..03861915b4 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/board.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "imx6ull.h" + +#include "mmu.h" + +#if defined(__CC_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void*)&Image$$RW_IRAM1$$ZI$$Limit) +#elif defined(__GNUC__) +extern int __bss_end; +#define HEAP_BEGIN ((void*)&__bss_end) +#endif + +#ifdef RT_USING_USERSPACE +#define HEAP_END (void*)(KERNEL_VADDR_START + 16 * 1024 * 1024) +#define PAGE_START HEAP_END +#define PAGE_END (void*)(KERNEL_VADDR_START + 128 * 1024 * 1024) +#else +#define HEAP_END (void*)(0x80000000 + 64 * 1024 * 1024) +#endif + +/* + * memory map for peripherals + */ +/* + start addr - end addr , size + 0x0090_0000 - 0x0091_FFFF, 128KB, OCRAM + 0x0200_0000 - 0x020F_FFFF, 1MB, AIPS-1 + 0x0210_0000 - 0x021F_FFFF, 1MB, AIPS-2 + 0x0220_0000 - 0x022F_FFFF, 1MB, AIPS-3 + */ +void rt_hw_board_init(void); + +extern rt_mmu_info mmu_info; + +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/bsp_clock.c b/bsp/imx6ull-artpi-smart/drivers/bsp_clock.c new file mode 100644 index 0000000000..3f0ad3a915 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/bsp_clock.c @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-20 Lyons first version + * 2021-06-24 RiceChen add spi and lcd clock config + */ + +#include "board.h" +#include "fsl_clock.h" + +#define _K_GPT_LOAD_VALUE RT_UINT32_MAX + +/* only used by MCIMX6Y2.h */ +uint32_t *g_ccm_vbase = (uint32_t*)IMX6ULL_CCM_BASE; +uint32_t *g_ccm_analog_vbase = (uint32_t*)IMX6ULL_CCM_ANALOGY_BASE; +uint32_t *g_pmu_vbase = (uint32_t*)IMX6ULL_PMU_BASE; + +/* used by all files */ +uint32_t *g_iomuxc_vbase = (uint32_t*)IMX6ULL_IOMUXC_BASE; +uint32_t *g_iomuxc_snvs_vbase = (uint32_t*)IMX6ULL_IOMUXC_SNVS_BASE; +uint32_t *g_src_vbase = (uint32_t*)IMX6ULL_SRC_BASE; +uint32_t *g_wdog1_vbase = (uint32_t*)IMX6ULL_WATCHDOG1_BASE; +uint32_t *g_snvs_vbase = (uint32_t*)IMX6ULL_SNVS_BASE; + +_internal_rw uint32_t *_s_gpt1_vbase = (uint32_t*)IMX6ULL_GPT1_BASE; + +static void _clk_enable( CCM_Type *base ) +{ + base->CCGR0 = 0XFFFFFFFF; + base->CCGR1 = 0XFFFFFFFF; + base->CCGR2 = 0XFFFFFFFF; + base->CCGR3 = 0XFFFFFFFF; + base->CCGR4 = 0XFFFFFFFF; + base->CCGR5 = 0XFFFFFFFF; + base->CCGR6 = 0XFFFFFFFF; +} + +void BOARD_BootClockRUN(void) +{ + rt_uint32_t reg_value; + + /* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */ + CLOCK_SetXtalFreq(24000000U); + CLOCK_SetRtcXtalFreq(32768U); + + /* + * ARM_CLK from 'pll1_sw_clk', whitch from 'pll1_main_clk' or 'step_clk' + * if edit 'pll1_main_clk', switch to 'step_clk' first + */ + reg_value = CCM->CCSR; + if (0 == (reg_value & CCM_CCSR_PLL1_SW_CLK_SEL_MASK)) //if sel 'pll1_main_clk' + { + reg_value &= ~CCM_CCSR_STEP_SEL_MASK; + reg_value |= CCM_CCSR_STEP_SEL(0); //sel 'osc_clk(24M)' + reg_value |= CCM_CCSR_PLL1_SW_CLK_SEL(1); //sel 'step_clk' + CCM->CCSR = reg_value; + } + + /* + * set PLL1(ARM PLL) at 1056MHz + * set ARM_CLK at 528MHz + * PLL output frequency = Fref * DIV_SEL / 2 + * = 24M * DIV_SEL / 2 = 1056M + */ + CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_ENABLE(1) + | CCM_ANALOG_PLL_ARM_DIV_SELECT(88); + + reg_value = CCM->CCSR; + reg_value &= ~CCM_CCSR_PLL1_SW_CLK_SEL_MASK; + reg_value |= CCM_CCSR_PLL1_SW_CLK_SEL(0); //resel 'pll1_main_clk' + CCM->CCSR = reg_value; + + CCM->CACRR = CCM_CACRR_ARM_PODF(1); //'CACRR[ARM_PODF]=0b001' divide by 2 + + /* + * set PLL2(System PLL) at fixed 528MHz + * PLL2_PFD0: 528M * 18 / FRAC + * PLL2_PFD1: 528M * 18 / FRAC + * PLL2_PFD2: 528M * 18 / FRAC + * PLL2_PFD3: 528M * 18 / FRAC + */ + reg_value = CCM_ANALOG->PFD_528; + reg_value &= ~0x3F3F3F3F; + reg_value |= CCM_ANALOG_PFD_528_SET_PFD0_FRAC(27); //27: 352MHz + reg_value |= CCM_ANALOG_PFD_528_SET_PFD1_FRAC(16); //16: 594MHz + reg_value |= CCM_ANALOG_PFD_528_SET_PFD2_FRAC(24); //24: 396MHz + reg_value |= CCM_ANALOG_PFD_528_SET_PFD3_FRAC(32); //32: 297MHz + CCM_ANALOG->PFD_528 = reg_value; + + /* + * set PLL3(USB PLL) at fixed 480MHz + * PLL3_PFD0: 480M * 18 / FRAC + * PLL3_PFD1: 480M * 18 / FRAC + * PLL3_PFD2: 480M * 18 / FRAC + * PLL3_PFD3: 480M * 18 / FRAC + */ + reg_value = CCM_ANALOG->PFD_480; + reg_value &= ~0x3F3F3F3F; + reg_value |= CCM_ANALOG_PFD_480_SET_PFD0_FRAC(12); //12: 720MHz + reg_value |= CCM_ANALOG_PFD_480_SET_PFD1_FRAC(16); //16: 540MHz + reg_value |= CCM_ANALOG_PFD_480_SET_PFD2_FRAC(17); //17: 508.24MHz + reg_value |= CCM_ANALOG_PFD_480_SET_PFD3_FRAC(19); //19: 457.74MHz + CCM_ANALOG->PFD_480 = reg_value; + + /* + * set PERCLK_CLK at 66MHz from IPG_CLK + */ + reg_value = CCM->CSCMR1; + reg_value &= ~CCM_CSCMR1_PERCLK_CLK_SEL_MASK; + reg_value |= CCM_CSCMR1_PERCLK_CLK_SEL(0); //sel IPG_CLK + reg_value &= ~CCM_CSCMR1_PERCLK_PODF_MASK; + reg_value |= CCM_CSCMR1_PERCLK_PODF(0); //'CSCMR1[PERCLK_PODF]=0b000000' divide by 1 + CCM->CSCMR1 = reg_value; + + CLOCK_DeinitAudioPll(); + CLOCK_DeinitVideoPll(); + CLOCK_DeinitEnetPll(); + + /* Configure UART divider to default */ + CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */ + + /* Configure ECSPI divider to default */ + CLOCK_SetMux(kCLOCK_EcspiMux, 0); /* Set ECSPI source to PLL3 60M */ + CLOCK_SetDiv(kCLOCK_EcspiDiv, 0); /* Set ECSPI divider to 1 */ + + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_Lcdif1PreDiv, 2); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lcdif1Div, 4); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_Lcdif1PreMux, 2); + CLOCK_SetMux(kCLOCK_Lcdif1Mux, 0); +} + +void BOARD_DelayInit(void) +{ + GPT_Type *_GPT = (GPT_Type*)_s_gpt1_vbase; + + _GPT->CR = 0; + + _GPT->CR = GPT_CR_SWR(1); + while (_GPT->CR & GPT_CR_SWR_MASK); + + /* + * 000 No clock + * 001 derive clock from ipg_clk + * 010 derive clock from ipg_clk_highfreq + * 011 derive clock from External Clock + * 100 derive clock from ipg_clk_32k + * 101 derive clock from ipg_clk_24M + */ + _GPT->CR = GPT_CR_CLKSRC(0x1); + + _GPT->PR = GPT_PR_PRESCALER(65); //Set GPT1 Clock to 66MHz/66 = 1MHz + + _GPT->OCR[0] = GPT_OCR_COMP(_K_GPT_LOAD_VALUE); + + _GPT->CR |= GPT_CR_EN(1); +} + +//execution before SystemClockInit called +void SystemAddressMapping(void) +{ + g_ccm_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_ccm_vbase); + g_ccm_analog_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_ccm_analog_vbase); + g_pmu_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_pmu_vbase); + + g_iomuxc_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_iomuxc_vbase); + g_iomuxc_snvs_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_iomuxc_snvs_vbase); + g_src_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_src_vbase); + g_wdog1_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_wdog1_vbase); + g_snvs_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)g_snvs_vbase); + + _s_gpt1_vbase = (uint32_t*)platform_get_periph_vaddr((rt_uint32_t)_s_gpt1_vbase); +} + +void SystemClockInit(void) +{ + BOARD_BootClockRUN(); + BOARD_DelayInit(); + + _clk_enable(CCM); +} + +void rt_hw_us_delay(uint32_t us) +{ + GPT_Type *_GPT = (GPT_Type*)_s_gpt1_vbase; + + rt_uint64_t old_cnt, new_cnt; + rt_uint64_t total = 0; + + old_cnt = _GPT->CNT; + while (1) + { + new_cnt = _GPT->CNT; + if (old_cnt != new_cnt) + { + if (new_cnt > old_cnt) + { + total += (new_cnt - old_cnt); + } else { + total += (new_cnt + _K_GPT_LOAD_VALUE - old_cnt); + } + old_cnt = new_cnt; + + if (total >= us) + break; + } + } +} + +void rt_hw_ms_delay(uint32_t ms) +{ + while (ms--) + { + rt_hw_us_delay(1000); + } +} diff --git a/bsp/imx6ull-artpi-smart/drivers/bsp_clock.h b/bsp/imx6ull-artpi-smart/drivers/bsp_clock.h new file mode 100644 index 0000000000..e84208fb4d --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/bsp_clock.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-20 Lyons first version + */ + +#ifndef __BSP_CLOCK_H__ +#define __BSP_CLOCK_H__ + +extern uint32_t *g_iomuxc_vbase; +extern uint32_t *g_iomuxc_snvs_vbase; +extern uint32_t *g_src_vbase; +extern uint32_t *g_wdog1_vbase; +extern uint32_t *g_snvs_vbase; + +void SystemAddressMapping(void); +void SystemClockInit(void); + +void rt_hw_us_delay(uint32_t us); +void rt_hw_ms_delay(uint32_t ms); + +#endif //#ifndef __BSP_CLOCK_H__ diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_common.c b/bsp/imx6ull-artpi-smart/drivers/drv_common.c new file mode 100644 index 0000000000..ad4685a709 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_common.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-04-11 RiceChen the first version + * + */ + +#include +#include +#include "board.h" + +#include "mmu.h" +#include "ioremap.h" +#include "fsl_iomuxc.h" +#include "drv_common.h" + +void *imx6ull_get_periph_vaddr(rt_uint32_t paddr) +{ + return rt_ioremap((void *)paddr, sizeof(sizeof(rt_uint32_t))); +} + +void *imx6ull_get_periph_paddr(rt_uint32_t vaddr) +{ + return rt_hw_mmu_v2p(&mmu_info, (void *)vaddr); +} + +void imx6ull_gpio_init(const struct imx6ull_iomuxc *gpio) +{ + rt_uint32_t mux_reg_vaddr = 0; + rt_uint32_t input_reg_vaddr = 0; + rt_uint32_t config_reg_vaddr = 0; + + mux_reg_vaddr = (rt_uint32_t)(gpio->muxRegister ? (rt_uint32_t)imx6ull_get_periph_vaddr(gpio->muxRegister) : gpio->muxRegister); + input_reg_vaddr = (rt_uint32_t)(gpio->inputRegister ? (rt_uint32_t)imx6ull_get_periph_vaddr(gpio->inputRegister) : gpio->inputRegister); + config_reg_vaddr = (rt_uint32_t)(gpio->configRegister ? (rt_uint32_t)imx6ull_get_periph_vaddr(gpio->configRegister) : gpio->configRegister); + + IOMUXC_SetPinMux(mux_reg_vaddr, gpio->muxMode, input_reg_vaddr, gpio->inputDaisy, config_reg_vaddr, gpio->inputOnfield); + IOMUXC_SetPinConfig(mux_reg_vaddr, gpio->muxMode, input_reg_vaddr, gpio->inputDaisy, config_reg_vaddr, gpio->configValue); +} diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_common.h b/bsp/imx6ull-artpi-smart/drivers/drv_common.h new file mode 100644 index 0000000000..976beb22f3 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_common.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-04-11 RiceChen the first version + * + */ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include + +struct imx6ull_iomuxc +{ + rt_uint32_t muxRegister; + rt_uint32_t muxMode; + rt_uint32_t inputRegister; + rt_uint32_t inputDaisy; + rt_uint32_t configRegister; + + rt_uint32_t inputOnfield; + + rt_uint32_t configValue; +}; + +void *imx6ull_get_periph_vaddr(rt_uint32_t paddr); +void *imx6ull_get_periph_paddr(rt_uint32_t vaddr); + +void imx6ull_gpio_init(const struct imx6ull_iomuxc *gpio); + +#endif \ No newline at end of file diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_eth.c b/bsp/imx6ull-artpi-smart/drivers/drv_eth.c new file mode 100644 index 0000000000..5fff2f78c0 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_eth.c @@ -0,0 +1,380 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-16 songchao support emac driver + * 2021-06-29 songchao add phy link detect + */ + +#include "drv_eth.h" +#define DBG_TAG "drv.enet" +#define DBG_LVL DBG_LOG +#include + +static struct rt_imx6ul_ethps imx6ul_eth_device; +static status_t read_data_from_eth(void *read_data,uint16_t *read_length); +static enet_config_t config; +static enet_handle_t g_handle; +static ENET_Type *enet_base_addr; +static uint8_t rx_recv_buf[ENET_RX_MAX_BUFFER_SIZE]; + +void imx6ul_eth_link_change(rt_bool_t up) +{ + if(up) + { + LOG_D("enet link up\n"); + eth_device_linkchange(&imx6ul_eth_device.parent, RT_TRUE); + imx6ul_eth_device.phy_link_status = RT_TRUE; + } + else + { + LOG_D("enet link down\n"); + eth_device_linkchange(&imx6ul_eth_device.parent, RT_FALSE); + imx6ul_eth_device.phy_link_status = RT_FALSE; + } +} + +enet_buffer_config_t buffConfig = { + ENET_RXBD_NUM, + ENET_TXBD_NUM, + ENET_RXBUFF_ALIGN_SIZE, + ENET_TXBUFF_ALIGN_SIZE, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + ENET_RXBUFF_TOTAL_SIZE, + ENET_TXBUFF_TOTAL_SIZE, +}; + +void ENET_InitModuleClock(void) +{ + const clock_enet_pll_config_t config = {true, true, false, 1, 1}; + CLOCK_InitEnetPll(&config); +} + +rt_err_t enet_buffer_init(enet_buffer_config_t *buffConfig) +{ + void *tx_buff_addr = RT_NULL; + void *rx_buff_addr = RT_NULL; + void *tx_bd_addr = RT_NULL; + void *rx_bd_addr = RT_NULL; + + if(((SYS_PAGE_SIZE<rxBufferTotalSize)|| + ((SYS_PAGE_SIZE<txBufferTotalSize)) + { + LOG_E("ERROR: alloc mem not enough for enet driver\n"); + return RT_ERROR; + } + rx_buff_addr = rt_pages_alloc(RX_BUFFER_INDEX_NUM); + if(!rx_buff_addr) + { + LOG_E("ERROR: rx buff page alloc failed\n"); + return RT_ERROR; + } + buffConfig->rxBufferAlign = (void *)rt_ioremap_nocache(virtual_to_physical(rx_buff_addr), (SYS_PAGE_SIZE<rxPhyBufferAlign = (void *)virtual_to_physical(rx_buff_addr); + + tx_buff_addr = rt_pages_alloc(TX_BUFFER_INDEX_NUM); + if(!tx_buff_addr) + { + LOG_E("ERROR: tx buff page alloc failed\n"); + return RT_ERROR; + } + buffConfig->txBufferAlign = (void *)rt_ioremap_nocache(virtual_to_physical(tx_buff_addr), (SYS_PAGE_SIZE<txPhyBufferAlign = (void *)virtual_to_physical(tx_buff_addr); + + + rx_bd_addr = rt_pages_alloc(RX_BD_INDEX_NUM); + if(!rx_bd_addr) + { + LOG_E("ERROR: rx bd page alloc failed\n"); + return RT_ERROR; + } + buffConfig->rxBdStartAddrAlign = (void *)rt_ioremap_nocache(virtual_to_physical(rx_bd_addr), (SYS_PAGE_SIZE<rxPhyBdStartAddrAlign = virtual_to_physical(rx_bd_addr); + + tx_bd_addr = rt_pages_alloc(TX_BD_INDEX_NUM); + if(!tx_bd_addr) + { + LOG_E("ERROR: tx bd page alloc failed\n"); + return RT_ERROR; + } + buffConfig->txBdStartAddrAlign = (void *)rt_ioremap_nocache(virtual_to_physical(tx_bd_addr), (SYS_PAGE_SIZE<txPhyBdStartAddrAlign = virtual_to_physical(tx_bd_addr); + + return RT_EOK; +} + +/* EMAC initialization function */ +static rt_err_t rt_imx6ul_eth_init(rt_device_t dev) +{ + bool link = false; + rt_err_t state; + phy_speed_t speed; + phy_duplex_t duplex; + + enet_base_addr = (ENET_Type *)rt_ioremap((void *)IMX6UL_ENET,SYS_PAGE_SIZE); + + phy_reset(); + ENET_InitPins(); + ENET_InitModuleClock(); + ENET_GetDefaultConfig(&config); + config.interrupt |= (ENET_RX_INTERRUPT); + PHY_Init(enet_base_addr, ENET_PHY, SYS_CLOCK_HZ); + PHY_GetLinkStatus(enet_base_addr, ENET_PHY, &link); + if (link) + { + /* Get the actual PHY link speed. */ + PHY_GetLinkSpeedDuplex(enet_base_addr, ENET_PHY, &speed, &duplex); + /* Change the MII speed and duplex for actual link status. */ + config.miiSpeed = (enet_mii_speed_t)speed; + config.miiDuplex = (enet_mii_duplex_t)duplex; + } + else + { + LOG_E("\r\nPHY Link down, please check the cable connection and link partner setting.\r\n"); + } + + state = enet_buffer_init(&buffConfig); + if(state != RT_EOK) + { + return state; + } + ENET_Init(enet_base_addr, &g_handle, &config, &buffConfig, &imx6ul_eth_device.dev_addr[0], SYS_CLOCK_HZ); + ENET_ActiveRead(enet_base_addr); + rt_hw_interrupt_install(IMX_INT_ENET, (rt_isr_handler_t)ENET_DriverIRQHandler, (void *)enet_base_addr,ENET_IRQ_NAME); + rt_hw_interrupt_umask(IMX_INT_ENET); + + return RT_EOK; +} + +static rt_err_t rt_imx6ul_eth_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_imx6ul_eth_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_imx6ul_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + return 0; +} + +static rt_size_t rt_imx6ul_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + return 0; +} + +static rt_err_t rt_imx6ul_eth_control(rt_device_t dev, int cmd, void *args) +{ + switch (cmd) + { + case NIOCTL_GADDR: + /* get MAC address */ + if (args) + { + rt_memcpy(args, imx6ul_eth_device.dev_addr, MAX_ADDR_LEN); + } + else + { + return -RT_ERROR; + } + break; + + default : + break; + } + return RT_EOK; +} + +/* transmit data*/ +rt_err_t rt_imx6ul_eth_tx(rt_device_t dev, struct pbuf *p) +{ + rt_err_t ret = RT_ERROR; + struct pbuf *q = NULL; + uint16_t offset = 0; + uint32_t last_flag = 0; + status_t status; + RT_ASSERT(p); + + for(q = p;q != NULL;q=q->next) + { + if(q->next == NULL) + { + last_flag = 1; + } + else + { + last_flag = 0; + } + status = ENET_SendFrame(enet_base_addr, &g_handle, q->payload, q->len,last_flag); + offset = offset + q->len; + if(status == kStatus_Success) + { + } + else + { + return RT_ERROR; + } + } + if(offset > ENET_FRAME_MAX_FRAMELEN) + { + LOG_E("net error send length %d exceed max length\n",offset); + } + return ret; +} + +struct pbuf *rt_imx6ul_eth_rx(rt_device_t dev) +{ + struct pbuf *p = NULL; + status_t status; + uint16_t length =0; + status = read_data_from_eth(rx_recv_buf,&length); + if(status == kStatus_ENET_RxFrameEmpty) + { + return RT_NULL; + } + else if(status == kStatus_ENET_RxFrameError) + { + return RT_NULL; + } + if(length > ENET_FRAME_MAX_FRAMELEN) + { + LOG_E("net error recv length %d exceed max length\n",length); + return RT_NULL; + } + + p = pbuf_alloc(PBUF_RAW, ENET_FRAME_MAX_FRAMELEN, PBUF_POOL); + if(p == RT_NULL) + { + return RT_NULL; + } + else + { + pbuf_realloc(p, length); + memcpy(p->payload,rx_recv_buf,length); + p->len = length; + p->tot_len = length; + } + return p; +} + +void rx_enet_callback() +{ + eth_device_ready(&(imx6ul_eth_device.parent)); + ENET_DisableInterrupts(enet_base_addr,ENET_RX_INTERRUPT); +} + +void tx_enet_callback() +{ + ENET_DisableInterrupts(enet_base_addr,ENET_TX_INTERRUPT); +} + +static status_t read_data_from_eth(void *read_data,uint16_t *read_length) +{ + status_t status = 0; + uint16_t length = 0; + /* Get the Frame size */ + status = ENET_ReadFrame(enet_base_addr,&g_handle,&config,read_data,&length); + if((status == kStatus_ENET_RxFrameEmpty)||(status == kStatus_ENET_RxFrameError)) + { + ENET_EnableInterrupts(enet_base_addr,ENET_RX_INTERRUPT); + if(status == kStatus_ENET_RxFrameError) + { + /*recv error happend reinitialize mac*/ + ENET_Init(enet_base_addr, &g_handle, &config, &buffConfig, &imx6ul_eth_device.dev_addr[0], SYS_CLOCK_HZ); + ENET_ActiveRead(enet_base_addr); + return kStatus_ENET_RxFrameError; + } + else if(status == kStatus_ENET_RxFrameEmpty) + { + return kStatus_ENET_RxFrameEmpty; + } + } + *read_length = length; + return status; +} +/*phy link detect thread*/ +static void phy_detect_thread_entry(void *param) +{ + bool link = false; + while(1) + { + PHY_GetLinkStatus(enet_base_addr, ENET_PHY, &link); + if(link != imx6ul_eth_device.phy_link_status) + { + if(link == true) + { + PHY_StartNegotiation(enet_base_addr,ENET_PHY); + } + imx6ul_eth_link_change(link); + } + rt_thread_delay(DETECT_DELAY_ONE_SECOND); + } +} + +_internal_ro struct rt_device_ops _k_enet_ops = +{ + rt_imx6ul_eth_init, + rt_imx6ul_eth_open, + rt_imx6ul_eth_close, + rt_imx6ul_eth_read, + rt_imx6ul_eth_write, + rt_imx6ul_eth_control, +}; + +static int imx6ul_eth_init(void) +{ + rt_err_t state = RT_EOK; + + imx6ul_eth_device.dev_addr[0] = 0xa8; + imx6ul_eth_device.dev_addr[1] = 0x5e; + imx6ul_eth_device.dev_addr[2] = 0x45; + imx6ul_eth_device.dev_addr[3] = 0x31; + imx6ul_eth_device.dev_addr[4] = 0x32; + imx6ul_eth_device.dev_addr[5] = 0x33; + + imx6ul_eth_device.parent.parent.ops = &_k_enet_ops; + + imx6ul_eth_device.parent.eth_rx = rt_imx6ul_eth_rx; + imx6ul_eth_device.parent.eth_tx = rt_imx6ul_eth_tx; + imx6ul_eth_device.phy_link_status = RT_FALSE; + + /* register eth device */ + state = eth_device_init(&(imx6ul_eth_device.parent), ENET_NAME); + if (RT_EOK == state) + { + LOG_E("emac device init success\n"); + } + else + { + LOG_E("emac device init faild: %d", state); + state = -RT_ERROR; + } + + /* start phy link detect */ + rt_thread_t phy_link_tid; + phy_link_tid = rt_thread_create("link_detect", + phy_detect_thread_entry, + RT_NULL, + 512, + RT_THREAD_PRIORITY_MAX - 2, + 2); + if (phy_link_tid != RT_NULL) + { + rt_thread_startup(phy_link_tid); + } + return state; +} +INIT_DEVICE_EXPORT(imx6ul_eth_init); diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_eth.h b/bsp/imx6ull-artpi-smart/drivers/drv_eth.h new file mode 100644 index 0000000000..06370ed066 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_eth.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-16 songchao first version + */ + +#ifndef __DRV_ETH_H__ +#define __DRV_ETH_H__ + +#include +#include +#include "fsl_phy.h" +#include "imx6ull.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAX_ADDR_LEN 6 +struct rt_imx6ul_ethps +{ + /* inherit from ethernet device */ + struct eth_device parent; + /* interface address info, hw address */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; + /* ETH_Speed */ + uint32_t ETH_Speed; + /* ETH_Duplex_Mode */ + uint32_t ETH_Mode; + rt_bool_t phy_link_status; +}; + + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_ETH_H__ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_i2c.c b/bsp/imx6ull-artpi-smart/drivers/drv_i2c.c new file mode 100644 index 0000000000..9745672f89 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_i2c.c @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-13 Lyons first version + * 2021-06-23 RiceChen refactor + */ + +#include +#include + +#ifdef BSP_USING_I2C + +#define LOG_TAG "drv.i2c" +#include + +#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4) +#error "Please define at least one BSP_USING_I2Cx" +#endif + +#include "fsl_iomuxc.h" +#include "drv_i2c.h" + +static struct imx6ull_i2c_config i2c_config[] = +{ +#ifdef BSP_USING_I2C1 + I2C1_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C2 + I2C2_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C3 + I2C3_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C4 + I2C4_BUS_CONFIG, +#endif +}; + +static struct imx6ull_i2c_bus i2c_obj[sizeof(i2c_config) / sizeof(i2c_config[0])]; + +static rt_size_t imx6ull_i2c_mst_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + struct imx6ull_i2c_bus *i2c_bus = RT_NULL; + i2c_master_transfer_t xfer = {0}; + rt_size_t i = 0; + + RT_ASSERT(bus != RT_NULL); + + i2c_bus = (struct imx6ull_i2c_bus *)bus; + + for(i = 0 ;i < num; i++) + { + if(msgs[i].flags & RT_I2C_RD) + { + xfer.flags = kI2C_TransferNoStartFlag; + xfer.slaveAddress = msgs[i].addr; + xfer.direction = kI2C_Read; + xfer.subaddress = 0; + xfer.subaddressSize = 0; + xfer.data = msgs[i].buf; + xfer.dataSize = msgs[i].len; + I2C_MasterTransferBlocking(i2c_bus->config->I2C, &xfer); + } + else + { + xfer.flags = kI2C_TransferNoStartFlag; + xfer.slaveAddress = msgs[i].addr; + xfer.direction = kI2C_Write; + xfer.subaddress = 0; + xfer.subaddressSize = 0; + xfer.data = msgs[i].buf; + xfer.dataSize = msgs[i].len; + I2C_MasterTransferBlocking(i2c_bus->config->I2C, &xfer); + } + } + + return i; +} + +static rt_err_t imx6ull_i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t cmd, rt_uint32_t arg) +{ + return RT_EOK; +} + +static rt_err_t imx6ull_i2c_gpio_init(struct imx6ull_i2c_bus *bus) +{ + struct imx6ull_i2c_bus *i2c_bus = RT_NULL; + + i2c_bus = (struct imx6ull_i2c_bus *)bus; + + imx6ull_gpio_init(&i2c_bus->config->scl_gpio); + imx6ull_gpio_init(&i2c_bus->config->sda_gpio); + return RT_EOK; + +} + +#ifdef RT_USING_DEVICE_OPS +static const struct rt_i2c_bus_device_ops imx6ull_i2c_ops = +{ + .master_xfer = imx6ull_i2c_mst_xfer, + .slave_xfer = RT_NULL, + .i2c_bus_control = imx6ull_i2c_bus_control, +}; +#endif + +int rt_hw_i2c_init(void) +{ + rt_uint16_t obj_num = 0; + rt_uint32_t src_clock; + i2c_master_config_t masterConfig = {0}; + + obj_num = sizeof(i2c_config) / sizeof(i2c_config[0]); + + src_clock = (CLOCK_GetFreq(kCLOCK_IpgClk) / (CLOCK_GetDiv(kCLOCK_PerclkDiv) + 1U)); + + for(int i = 0; i < obj_num; i++) + { + i2c_obj[i].config = &i2c_config[i]; + i2c_obj[i].config->I2C = (I2C_Type *)imx6ull_get_periph_vaddr((rt_uint32_t)(i2c_obj[i].config->I2C)); + i2c_obj[i].parent.ops = &imx6ull_i2c_ops; + imx6ull_i2c_gpio_init(&i2c_obj[i]); + + I2C_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate_Bps = i2c_config[i].baud_rate; + + CLOCK_EnableClock(i2c_obj[i].config->clk_ip_name); + + I2C_MasterInit(i2c_obj[i].config->I2C, &masterConfig, src_clock); + + rt_i2c_bus_device_register(&i2c_obj[i].parent, i2c_obj[i].config->name); + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif \ No newline at end of file diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_i2c.h b/bsp/imx6ull-artpi-smart/drivers/drv_i2c.h new file mode 100644 index 0000000000..1e9cb8bbd6 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_i2c.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-13 Lyons first version + * 2021-06-23 RiceChen refactor + */ + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + +#include +#include "drv_common.h" + +#include "fsl_iomuxc.h" +#include "fsl_clock.h" +#include "fsl_i2c.h" + +struct imx6ull_i2c_config +{ + I2C_Type *I2C; + char *name; + + rt_uint32_t baud_rate; + + rt_uint32_t clk_ip_name; + + struct imx6ull_iomuxc scl_gpio; + struct imx6ull_iomuxc sda_gpio; +}; + +struct imx6ull_i2c_bus +{ + struct rt_i2c_bus_device parent; + struct imx6ull_i2c_config *config; +}; + +#ifdef BSP_USING_I2C1 +#define I2C1_BUS_CONFIG \ + { \ + .I2C = I2C1, \ + .name = "i2c1", \ + .clk_ip_name = kCLOCK_I2c1S, \ + .baud_rate = I2C1_BAUD_RATE, \ + .scl_gpio = {IOMUXC_UART4_TX_DATA_I2C1_SCL, 1, 0x70B0}, \ + .sda_gpio = {IOMUXC_UART4_RX_DATA_I2C1_SDA, 1, 0x70B0}, \ + } +#endif /* BSP_USING_I2C1 */ + +#ifdef BSP_USING_I2C2 +#define I2C2_BUS_CONFIG \ + { \ + .I2C = I2C2, \ + .name = "i2c2", \ + .clk_ip_name = kCLOCK_I2c2S, \ + .baud_rate = I2C2_BAUD_RATE, \ + .scl_gpio = {IOMUXC_UART5_TX_DATA_I2C2_SCL, 1, 0x70B0}, \ + .sda_gpio = {IOMUXC_UART5_RX_DATA_I2C2_SDA, 1, 0x70B0}, \ + } +#endif /* BSP_USING_I2C2 */ + +#ifdef BSP_USING_I2C3 +#define I2C3_BUS_CONFIG \ + { \ + .I2C = I2C3, \ + .name = "i2c3", \ + .clk_ip_name = kCLOCK_I2c3S, \ + .baud_rate = I2C3_BAUD_RATE, \ + .scl_gpio = {IOMUXC_ENET2_RX_DATA0_I2C3_SCL, 1, 0x70B0}, \ + .sda_gpio = {IOMUXC_ENET2_RX_DATA1_I2C3_SDA, 1, 0x70B0}, \ + } +#endif /* BSP_USING_I2C3 */ + +#ifdef BSP_USING_I2C4 +#define I2C4_BUS_CONFIG \ + { \ + .I2C = I2C4, \ + .name = "i2c4", \ + .clk_ip_name = kCLOCK_I2c4S, \ + .baud_rate = I2C4_BAUD_RATE, \ + .scl_gpio = {IOMUXC_ENET2_RX_EN_I2C4_SCL, 1, 0x70B0}, \ + .sda_gpio = {IOMUXC_ENET2_TX_DATA0_I2C4_SDA, 1, 0x70B0}, \ + } +#endif /* BSP_USING_I2C4 */ + +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_lcd.c b/bsp/imx6ull-artpi-smart/drivers/drv_lcd.c new file mode 100644 index 0000000000..6045cb5163 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_lcd.c @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-11 Lyons first version + * 2021-06-24 RiceChen refactor + */ + +#include +#include + +#ifdef BSP_USING_LCD + +#define LOG_TAG "drv.lcd" +#include + +#include "fsl_iomuxc.h" +#include "drv_lcd.h" +#include + +struct imx6ull_lcd_config lcd_config = LCD_BUS_CONFIG; +struct imx6ull_lcd_bus lcd_obj; + +static rt_err_t imx6ull_elcd_init(rt_device_t device) +{ + struct imx6ull_lcd_bus *elcd_dev = RT_NULL; + clock_video_pll_config_t pll_config; + elcdif_rgb_mode_config_t lcd_config; + + RT_ASSERT(device != RT_NULL); + + elcd_dev = (struct imx6ull_lcd_bus *)device; + + pll_config.loopDivider = 32; + pll_config.postDivider = 1; + pll_config.numerator = 0; + pll_config.denominator = 0; + + CLOCK_InitVideoPll(&pll_config); + + lcd_config.hfp = LCD_HFP; + lcd_config.vfp = LCD_VFP; + lcd_config.hbp = LCD_HBP; + lcd_config.vbp = LCD_VBP; + lcd_config.hsw = LCD_HSW; + lcd_config.vsw = LCD_VSW; + + lcd_config.polarityFlags = kELCDIF_DataEnableActiveHigh | + kELCDIF_VsyncActiveLow | + kELCDIF_HsyncActiveLow | + kELCDIF_DriveDataOnRisingClkEdge; + + lcd_config.panelWidth = LCD_WIDTH; + lcd_config.panelHeight = LCD_HEIGHT; + lcd_config.pixelFormat = kELCDIF_PixelFormatRGB565; + lcd_config.dataBus = kELCDIF_DataBus24Bit; + lcd_config.bufferAddr = (uint32_t)elcd_dev->fb_phy; + + ELCDIF_RgbModeInit(elcd_dev->config->ELCDIF, &lcd_config); + ELCDIF_RgbModeStart(elcd_dev->config->ELCDIF); + + return RT_EOK; +} + +static rt_err_t imx6ull_elcd_control(rt_device_t device, int cmd, void *args) +{ + struct imx6ull_lcd_bus *elcd_dev = RT_NULL; + + RT_ASSERT(device != RT_NULL); + + elcd_dev = (struct imx6ull_lcd_bus *)device; + + switch(cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + { + break; + } + case RTGRAPHIC_CTRL_POWERON: + { + rt_pin_write(IMX6ULL_LCD_BL_PIN, PIN_HIGH); + break; + } + case RTGRAPHIC_CTRL_POWEROFF: + { + rt_pin_write(IMX6ULL_LCD_BL_PIN, PIN_LOW); + break; + } + case RTGRAPHIC_CTRL_GET_INFO: + { + struct lcd_info *info = (struct lcd_info *)args; + RT_ASSERT(info != RT_NULL); + + rt_memcpy(&info->graphic, &elcd_dev->info, sizeof(struct rt_device_graphic_info)); + + info->screen.shamem_len = elcd_dev->info.width * elcd_dev->info.width * elcd_dev->info.bits_per_pixel/8; + info->screen.shamem_start = (rt_uint32_t)lwp_map_user_phy(lwp_self(), RT_NULL, + elcd_dev->fb_phy, + info->screen.shamem_len, 1); + break; + } + case RTGRAPHIC_CTRL_SET_MODE: + { + break; + } + } + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops elcd_ops = +{ + imx6ull_elcd_init, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + imx6ull_elcd_control, +}; +#endif + +int rt_hw_elcd_init(void) +{ + rt_err_t ret = 0; + + lcd_config.ELCDIF = (LCDIF_Type *)imx6ull_get_periph_vaddr((rt_uint32_t)(lcd_config.ELCDIF)); + lcd_config.lcd_mux_base = (rt_uint32_t)imx6ull_get_periph_vaddr((rt_uint32_t)(lcd_config.lcd_mux_base)); + lcd_config.lcd_cfg_base = (rt_uint32_t)imx6ull_get_periph_vaddr((rt_uint32_t)(lcd_config.lcd_cfg_base)); + + for(int i = 0; i < LCD_GPIO_MAX; i++) + { + IOMUXC_SetPinMux((lcd_config.lcd_mux_base + i * 4), 0x0U, 0x00000000U, 0x0U, (lcd_config.lcd_cfg_base + i * 4), 0); + IOMUXC_SetPinConfig((lcd_config.lcd_mux_base + i * 4), 0x0U, 0x00000000U, 0x0U, (lcd_config.lcd_cfg_base + i * 4), 0xB9); + } + + CLOCK_EnableClock(lcd_config.apd_clk_name); + CLOCK_EnableClock(lcd_config.pix_clk_name); + + lcd_obj.config = &lcd_config; + + lcd_obj.fb_virt = rt_pages_alloc(rt_page_bits(LCD_BUF_SIZE)); + lcd_obj.fb_phy = lcd_obj.fb_virt + PV_OFFSET; + + rt_kprintf("fb address => 0x%08x\n", lcd_obj.fb_phy); + if(lcd_obj.fb_phy == RT_NULL) + { + rt_kprintf("initialize frame buffer failed!\n"); + return -RT_ERROR; + } + + lcd_obj.info.width = LCD_WIDTH; + lcd_obj.info.height = LCD_HEIGHT; + lcd_obj.info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; + lcd_obj.info.bits_per_pixel = LCD_BITS_PER_PIXEL; + lcd_obj.info.framebuffer = (void *)lcd_obj.fb_virt; + + lcd_obj.parent.type = RT_Device_Class_Graphic; + +#ifdef RT_USING_DEVICE_OPS + lcd_obj.parent.ops = &elcd_ops; +#else + lcd_obj.parent.init = imx6ull_elcd_init; + lcd_obj.parent.open = RT_NULL; + lcd_obj.parent.close = RT_NULL; + lcd_obj.parent.read = RT_NULL; + lcd_obj.parent.write = RT_NULL; + lcd_obj.parent.control = imx6ull_elcd_control; +#endif + + lcd_obj.parent.user_data = (void *)&lcd_obj.info; + + ret = rt_device_register(&lcd_obj.parent, lcd_obj.config->name, RT_DEVICE_FLAG_RDWR); + + /* LCD_BL */ + rt_pin_mode (IMX6ULL_LCD_BL_PIN, PIN_MODE_OUTPUT); + rt_pin_write(IMX6ULL_LCD_BL_PIN, PIN_HIGH); + + rt_memset((rt_uint8_t *)lcd_obj.fb_virt, 0xff, LCD_BUF_SIZE); + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_elcd_init); + +#endif + diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_lcd.h b/bsp/imx6ull-artpi-smart/drivers/drv_lcd.h new file mode 100644 index 0000000000..165d160e3f --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_lcd.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-11 Lyons first version + * 2021-06-24 RiceChen refactor + */ + +#ifndef __DRV_LCD_H__ +#define __DRV_LCD_H__ + +#include +#include "drv_pin.h" +#include "drv_common.h" + +#include "fsl_iomuxc.h" +#include "fsl_clock.h" +#include "fsl_elcdif.h" + +#define LCD_GPIO_MAX 29 +#define LCD_MUX_BASE 0x020E0104U +#define LCD_CONFIG_BASE 0x020E0390U + +#define LCD_WIDTH BSP_LCD_WIDTH +#define LCD_HEIGHT BSP_LCD_HEIGHT +#define LCD_VSW 3 +#define LCD_VBP 20 +#define LCD_VFP 12 +#define LCD_HSW 20 +#define LCD_HBP 140 +#define LCD_HFP 160 + +#define LCD_BITS_PER_PIXEL 16 +#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8) + +#define IMX6ULL_LCD_BL_PIN GET_PIN(1, 8) + +struct fb_fix_screen_info +{ + rt_uint32_t shamem_start; + rt_uint32_t shamem_len; +}; + +struct lcd_info +{ + struct rt_device_graphic_info graphic; + struct fb_fix_screen_info screen; +}; + +struct imx6ull_lcd_config +{ + LCDIF_Type *ELCDIF; + char *name; + + rt_uint32_t apd_clk_name; + rt_uint32_t pix_clk_name; + + rt_uint32_t lcd_mux_base; + rt_uint32_t lcd_cfg_base; +}; + +struct imx6ull_lcd_bus +{ + struct rt_device parent; + struct rt_device_graphic_info info; + + struct imx6ull_lcd_config *config; + + rt_uint8_t *fb_phy; + rt_uint8_t *fb_virt; +}; + +#ifdef BSP_USING_LCD +#define LCD_BUS_CONFIG \ + { \ + .ELCDIF = LCDIF, \ + .name = "lcd", \ + .apd_clk_name = kCLOCK_Lcd, \ + .pix_clk_name = kCLOCK_Lcdif1, \ + .lcd_mux_base = LCD_MUX_BASE, \ + .lcd_cfg_base = LCD_CONFIG_BASE, \ + } +#endif /* BSP_USING_LCD */ + + +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_log.h b/bsp/imx6ull-artpi-smart/drivers/drv_log.h new file mode 100644 index 0000000000..f126da0de3 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_log.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-03 RiceChen first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include \ No newline at end of file diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_pin.c b/bsp/imx6ull-artpi-smart/drivers/drv_pin.c new file mode 100644 index 0000000000..a804d6b996 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_pin.c @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-13 Lyons edit and remove irq setting + * 2021-06-23 RiceChen refactor gpio driver and support gpio IRQ + */ + +#include +#include + +#include "drv_pin.h" +#include "drv_common.h" +#include "fsl_gpio.h" +#include "fsl_iomuxc.h" + +rt_uint32_t iomuxc_base = IOMUXC_BASE; +rt_uint32_t iomuxc_snvs_base = IOMUXC_SNVS_BASE; + +struct pin_mask +{ + GPIO_Type *gpio; + rt_int32_t valid_mask; + clock_ip_name_t gpio_clock; +}; + +struct pin_mask mask_tab[5] = +{ + {GPIO1, 0xffffffff, kCLOCK_Gpio1}, /* GPIO1 */ + {GPIO2, 0x003fffff, kCLOCK_Gpio2}, /* GPIO2 */ + {GPIO3, 0x1fffffff, kCLOCK_Gpio3}, /* GPIO3,29~31 not supported */ + {GPIO4, 0x1fffffff, kCLOCK_Gpio4}, /* GPIO4,29~31 not supported */ + {GPIO5, 0x00000fff, kCLOCK_Gpio5} /* GPIO5,12~31 not supported */ +}; + +const rt_int8_t gpio_reg_offset[5][32] = +{ + { 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,}, + {32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 94, 95, 96, 97, 98, 99, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,}, + {48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, -1, -1, -1,}, + {77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93,100,101,102,103,104,105,106,107,108,109,110,111, -1, -1, -1,}, + { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,}, +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + // GPIO1 + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + // GPIO2 + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + // GPIO3 + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + // GPIO4 + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + // GPIO5 + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +static void imx6ull_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode) +{ + GPIO_Type *gpio_base = RT_NULL; + gpio_pin_config_t config; + rt_uint32_t config_value = 0; + rt_int8_t port, pin_num, reg_offset; + rt_uint32_t mux_base_addr, config_base_addr; + + port = pin >> 5; + pin_num = pin & 31; + + config.outputLogic = PIN_LOW; + config.interruptMode = kGPIO_NoIntmode; + + switch (mode) + { + case PIN_MODE_OUTPUT: + { + config.direction = kGPIO_DigitalOutput; + config_value = 0x0030U; + } + break; + + case PIN_MODE_INPUT: + { + config.direction = kGPIO_DigitalInput; + config_value = 0x0830U; + } + break; + + case PIN_MODE_INPUT_PULLDOWN: + { + config.direction = kGPIO_DigitalInput; + config_value = 0x3030U; + } + break; + + case PIN_MODE_INPUT_PULLUP: + { + config.direction = kGPIO_DigitalInput; + config_value = 0xB030U; + } + break; + + case PIN_MODE_OUTPUT_OD: + { + config.direction = kGPIO_DigitalOutput; + config_value = 0x0830U; + } + break; + } + + reg_offset = gpio_reg_offset[port][pin_num]; + gpio_base = (GPIO_Type *)imx6ull_get_periph_paddr((rt_uint32_t)mask_tab[port].gpio); + + if(gpio_base != GPIO5) + { + IOMUXC_Type *periph = (IOMUXC_Type*)iomuxc_base; + + mux_base_addr = (rt_uint32_t)&periph->SW_MUX_CTL_PAD[reg_offset]; + config_base_addr = (rt_uint32_t)&periph->SW_PAD_CTL_PAD[reg_offset]; + } + else + { + IOMUXC_SNVS_Type *periph = (IOMUXC_SNVS_Type*)iomuxc_snvs_base; + + mux_base_addr = (rt_uint32_t)&periph->SW_MUX_CTL_PAD[reg_offset]; + config_base_addr = (rt_uint32_t)&periph->SW_PAD_CTL_PAD[reg_offset]; + } + IOMUXC_SetPinMux(mux_base_addr, 0x5U, 0x00000000U, 0x0U, config_base_addr, 1); + IOMUXC_SetPinConfig(mux_base_addr, 0x5U, 0x00000000U, 0x0U, config_base_addr, config_value); + + GPIO_PinInit(mask_tab[port].gpio, pin_num, &config); +} + +static void imx6ull_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value) +{ + rt_int8_t port = 0, pin_num = 0; + + port = pin >> 5; + pin_num = pin & 31; + + GPIO_WritePinOutput(mask_tab[port].gpio, pin_num, value); +} + +static int imx6ull_pin_read(struct rt_device *device, rt_base_t pin) +{ + int value = 0; + rt_int8_t port = 0, pin_num = 0; + + value = PIN_LOW; + port = pin >> 5; + pin_num = pin & 31; + + value = GPIO_ReadPadStatus(mask_tab[port].gpio, pin_num); + + return value; +} + +static rt_err_t imx6ull_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), + void *args) +{ + rt_base_t level = 0; + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[pin].pin == pin && + pin_irq_hdr_tab[pin].hdr == hdr && + pin_irq_hdr_tab[pin].mode == mode && + pin_irq_hdr_tab[pin].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + + pin_irq_hdr_tab[pin].pin = pin; + pin_irq_hdr_tab[pin].hdr = hdr; + pin_irq_hdr_tab[pin].mode = mode; + pin_irq_hdr_tab[pin].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t imx6ull_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level = 0; + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[pin].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[pin].pin = -1; + pin_irq_hdr_tab[pin].hdr = RT_NULL; + pin_irq_hdr_tab[pin].mode = 0; + pin_irq_hdr_tab[pin].args = RT_NULL; + + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t imx6ull_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + gpio_interrupt_mode_t int_mode; + rt_int8_t port = 0, pin_num = 0; + + port = pin >> 5; + pin_num = pin & 31; + + if (pin_irq_hdr_tab[pin].pin == -1) + { + rt_kprintf("rtt pin: %d callback function not initialized!\n", pin); + return RT_ENOSYS; + } + + if (enabled == PIN_IRQ_ENABLE) + { + switch (pin_irq_hdr_tab[pin].mode) + { + case PIN_IRQ_MODE_RISING: + int_mode = kGPIO_IntRisingEdge; + break; + case PIN_IRQ_MODE_FALLING: + int_mode = kGPIO_IntFallingEdge; + break; + case PIN_IRQ_MODE_RISING_FALLING: + int_mode = kGPIO_IntRisingOrFallingEdge; + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + int_mode = kGPIO_IntHighLevel; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + int_mode = kGPIO_IntLowLevel; + break; + default: + int_mode = kGPIO_IntRisingEdge; + break; + } + + GPIO_SetPinInterruptConfig(mask_tab[port].gpio, pin_num, int_mode); + GPIO_EnableInterrupts(mask_tab[port].gpio, 1U << pin_num); + } + else if (enabled == PIN_IRQ_DISABLE) + { + GPIO_DisableInterrupts(mask_tab[port].gpio, pin_num); + } + else + { + return RT_EINVAL; + } + + return RT_EOK; +} + +static void imx6ull_isr(rt_int16_t index_offset, rt_int8_t pin_start, GPIO_Type *base) +{ + rt_int32_t isr_status = 0, index = 0; + rt_int8_t i = 0, pin_end = 0; + + + pin_end = pin_start + 15; + isr_status = GPIO_GetPinsInterruptFlags(base) & base->IMR; + + for (i = pin_start; i <= pin_end ; i++) + { + if (isr_status & (1 << i)) + { + GPIO_ClearPinsInterruptFlags(base, (1 << i)); + index = index_offset + i; + if (pin_irq_hdr_tab[index].hdr != RT_NULL) + { + pin_irq_hdr_tab[index].hdr(pin_irq_hdr_tab[index].args); + } + } + } +} + +/* GPIO1 index offset is 0 */ +void GPIO1_Combined_0_15_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(0, 0, mask_tab[0].gpio); + + rt_interrupt_leave(); +} + +void GPIO1_Combined_16_31_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(0, 15, mask_tab[0].gpio); + + rt_interrupt_leave(); +} + +/* GPIO2 index offset is 32 */ +void GPIO2_Combined_0_15_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(32, 0, mask_tab[1].gpio); + + rt_interrupt_leave(); +} + +void GPIO2_Combined_16_31_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(32, 15, mask_tab[1].gpio); + + rt_interrupt_leave(); +} + +/* GPIO3 index offset is 64 */ +void GPIO3_Combined_0_15_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(64, 0, mask_tab[2].gpio); + + rt_interrupt_leave(); +} + +void GPIO3_Combined_16_31_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(64, 15, mask_tab[2].gpio); + + rt_interrupt_leave(); +} + +/* GPIO4 index offset is 96 */ +void GPIO4_Combined_0_15_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(96, 0, mask_tab[3].gpio); + + rt_interrupt_leave(); +} +void GPIO4_Combined_16_31_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(96, 15, mask_tab[3].gpio); + + rt_interrupt_leave(); +} + +/* GPIO5 index offset is 128 */ +void GPIO5_Combined_0_15_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(128, 0, mask_tab[4].gpio); + + rt_interrupt_leave(); +} + +/* GPIO5 index offset is 128 */ +void GPIO5_Combined_16_31_IRQHandler(int irqno, void *param) +{ + rt_interrupt_enter(); + + imx6ull_isr(128, 0, mask_tab[4].gpio); + + rt_interrupt_leave(); +} + +static const struct rt_pin_ops gpio_ops = +{ + imx6ull_pin_mode, + imx6ull_pin_write, + imx6ull_pin_read, + imx6ull_pin_attach_irq, + imx6ull_pin_detach_irq, + imx6ull_pin_irq_enable, + RT_NULL, +}; + +static void imx6ull_pin_interrupt_install(void) +{ + rt_hw_interrupt_install(IMX_INT_GPIO1_INT15_0, GPIO1_Combined_0_15_IRQHandler, RT_NULL, "GPIO1_0_15"); + rt_hw_interrupt_install(IMX_INT_GPIO1_INT31_16, GPIO1_Combined_16_31_IRQHandler, RT_NULL, "GPIO1_16_31"); + rt_hw_interrupt_install(IMX_INT_GPIO2_INT15_0, GPIO2_Combined_0_15_IRQHandler, RT_NULL, "GPIO2_0_15"); + rt_hw_interrupt_install(IMX_INT_GPIO2_INT31_16, GPIO2_Combined_16_31_IRQHandler, RT_NULL, "GPIO2_16_31"); + rt_hw_interrupt_install(IMX_INT_GPIO3_INT15_0, GPIO3_Combined_0_15_IRQHandler, RT_NULL, "GPIO3_0_15"); + rt_hw_interrupt_install(IMX_INT_GPIO3_INT31_16, GPIO3_Combined_16_31_IRQHandler, RT_NULL, "GPIO3_16_31"); + rt_hw_interrupt_install(IMX_INT_GPIO4_INT15_0, GPIO4_Combined_0_15_IRQHandler, RT_NULL, "GPIO4_0_15"); + rt_hw_interrupt_install(IMX_INT_GPIO4_INT31_16, GPIO4_Combined_16_31_IRQHandler, RT_NULL, "GPIO4_16_31"); + rt_hw_interrupt_install(IMX_INT_GPIO5_INT15_0, GPIO5_Combined_0_15_IRQHandler, RT_NULL, "GPIO5_0_15"); + rt_hw_interrupt_install(IMX_INT_GPIO5_INT31_16, GPIO5_Combined_16_31_IRQHandler, RT_NULL, "GPIO5_16_31"); + + rt_hw_interrupt_umask(IMX_INT_GPIO1_INT15_0); + rt_hw_interrupt_umask(IMX_INT_GPIO1_INT31_16); + rt_hw_interrupt_umask(IMX_INT_GPIO2_INT15_0); + rt_hw_interrupt_umask(IMX_INT_GPIO2_INT31_16); + rt_hw_interrupt_umask(IMX_INT_GPIO3_INT15_0); + rt_hw_interrupt_umask(IMX_INT_GPIO3_INT31_16); + rt_hw_interrupt_umask(IMX_INT_GPIO4_INT15_0); + rt_hw_interrupt_umask(IMX_INT_GPIO4_INT31_16); + rt_hw_interrupt_umask(IMX_INT_GPIO5_INT15_0); + rt_hw_interrupt_umask(IMX_INT_GPIO5_INT31_16); +} + +int imx6ull_hw_pin_init(void) +{ + iomuxc_base = (size_t)imx6ull_get_periph_vaddr(iomuxc_base); + iomuxc_snvs_base = (size_t)imx6ull_get_periph_vaddr(iomuxc_snvs_base); + + for(int port = 0; port < sizeof(mask_tab) / sizeof(mask_tab[0]); port++) + { + mask_tab[port].gpio = (GPIO_Type *)imx6ull_get_periph_vaddr((rt_uint32_t)mask_tab[port].gpio); + CLOCK_EnableClock(mask_tab[port].gpio_clock); + } + + imx6ull_pin_interrupt_install(); + + rt_device_pin_register("pin", &gpio_ops, RT_NULL); + + rt_kprintf("pin driver init success\n"); + return RT_EOK; +} +INIT_BOARD_EXPORT(imx6ull_hw_pin_init); diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_pin.h b/bsp/imx6ull-artpi-smart/drivers/drv_pin.h new file mode 100644 index 0000000000..98c388fe40 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_pin.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-13 Lyons first version + * 2021-06-23 RiceChen add get pin API + */ + +#ifndef __DRV_PIN_H__ +#define __DRV_PIN_H__ + +#include "board.h" + +#define GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31)) + +#endif //#ifndef __DRV_PIN_H__ diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_rtc.c b/bsp/imx6ull-artpi-smart/drivers/drv_rtc.c new file mode 100644 index 0000000000..576b952d75 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_rtc.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-04-25 Lyons first version + */ + +#include + +#ifdef BSP_USING_ONCHIP_RTC + +#include "board.h" + +#define DBG_TAG "drv.rtc" +#define DBG_LVL DBG_WARNING +#include + +#define _DEVICE_NAME "rtc" + +_internal_rw struct rt_device _s_rtc_device; + +static time_t _get_rtc_timestamp(void) +{ + snvs_hp_rtc_datetime_t rtcDate; + SNVS_Type *snvs = (SNVS_Type*)g_snvs_vbase; + struct tm tm_new; + + SNVS_HP_RTC_GetDatetime(snvs, &rtcDate); + + tm_new.tm_sec = rtcDate.second; + tm_new.tm_min = rtcDate.minute; + tm_new.tm_hour = rtcDate.hour; + tm_new.tm_mday = rtcDate.day; + tm_new.tm_mon = rtcDate.month - 1; + tm_new.tm_year = rtcDate.year - 1900; + + return mktime(&tm_new); +} + +static rt_err_t _set_rtc_time_stamp(time_t time_stamp) +{ + snvs_hp_rtc_datetime_t rtcDate; + SNVS_Type *snvs = (SNVS_Type*)g_snvs_vbase; + struct tm *p_tm; + + p_tm = localtime(&time_stamp); + + rtcDate.second = p_tm->tm_sec; + rtcDate.minute = p_tm->tm_min; + rtcDate.hour = p_tm->tm_hour; + rtcDate.day = p_tm->tm_mday; + rtcDate.month = p_tm->tm_mon + 1; + rtcDate.year = p_tm->tm_year + 1900; + + if (kStatus_Success != SNVS_HP_RTC_SetDatetime(snvs, &rtcDate)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static void _rtc_init(void) +{ + snvs_hp_rtc_config_t snvsRtcConfig; + SNVS_Type *snvs = (SNVS_Type*)g_snvs_vbase; + + SNVS_HP_RTC_GetDefaultConfig(&snvsRtcConfig); + SNVS_HP_RTC_Init(snvs, &snvsRtcConfig); + + SNVS_HP_RTC_StartTimer(snvs); +} + +static rt_err_t _rtc_config(struct rt_device *dev) +{ + return RT_EOK; +} + +static rt_err_t _rtc_ops_control( rt_device_t dev, int cmd, void *args ) +{ + rt_err_t result; + + RT_ASSERT(RT_NULL != dev); + + result = RT_EOK; + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + *(rt_uint32_t *)args = _get_rtc_timestamp(); + LOG_D("RTC: get rtc_time %x", *(rt_uint32_t *)args); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + if (_set_rtc_time_stamp(*(rt_uint32_t *)args)) + { + result = -RT_ERROR; + } + LOG_D("RTC: set rtc_time %x", *(rt_uint32_t *)args); + break; + } + + return result; +} + +#ifdef RT_USING_DEVICE_OPS +_internal_ro struct rt_device_ops _k_rtc_ops = +{ + RT_NULL, /* init */ + RT_NULL, /* open */ + RT_NULL, /* close */ + RT_NULL, /* read */ + RT_NULL, /* write */ + _rtc_ops_control, /* control */ +}; +#endif + +static rt_err_t _rt_rtc_register( rt_device_t device, const char *name, rt_uint32_t flag ) +{ + RT_ASSERT(RT_NULL != device); + + _rtc_init(); + if (RT_EOK != _rtc_config(device)) + { + return -RT_ERROR; + } + + device->type = RT_Device_Class_RTC; +#ifdef RT_USING_DEVICE_OPS + device->ops = &_k_rtc_ops; +#else + device->init = RT_NULL; + device->open = RT_NULL; + device->close = RT_NULL; + device->read = RT_NULL; + device->write = RT_NULL; + device->control = _rtc_ops_control; +#endif + device->user_data = RT_NULL; + + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + + /* register a character device */ + return rt_device_register(device, name, flag); +} + +int rt_hw_rtc_init(void) +{ + rt_err_t result; + + result = _rt_rtc_register(&_s_rtc_device, _DEVICE_NAME, RT_DEVICE_FLAG_RDWR); + if (RT_EOK != result) + { + LOG_E("rtc register err code: %d", result); + return result; + } + + LOG_D("rtc init success."); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif /* BSP_USING_ONCHIP_RTC */ diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_sdhc.c b/bsp/imx6ull-artpi-smart/drivers/drv_sdhc.c new file mode 100644 index 0000000000..b35d06ff39 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_sdhc.c @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-04-23 Lyons first version + */ + +#include + +#ifdef BSP_USING_SDHC + +#include "board.h" +#include "drv_pin.h" +#include "drv_sdhc.h" + +#define DBG_TAG "drv.sdhc" +#define DBG_LVL DBG_LOG +#include + +#define SDCARD_SHOW_CARD_INFO 0 + +/* + * There are 512M Bytes reserved for boot image. + * Modify these parameter manually. + */ +#define SDCARD_PART1_START_SECTOR 8192 //no fs! +#define SDCARD_PART2_START_SECTOR 1056768 //use fs. + +_internal_rw struct imx_sddev _s_sdcard_device = { + .name = "sd0", + .periph.paddr = BOARD_SD_HOST_BASEADDR, + .irqno = RT_NULL, //not use irq yet! + .gpio = { + {IOMUXC_SD1_CLK_USDHC1_CLK, 0U, 0x17049}, + {IOMUXC_SD1_CMD_USDHC1_CMD, 0U, 0x17089}, + + {IOMUXC_SD1_DATA0_USDHC1_DATA0, 0U, 0x17089}, + {IOMUXC_SD1_DATA1_USDHC1_DATA1, 0U, 0x17089}, + {IOMUXC_SD1_DATA2_USDHC1_DATA2, 0U, 0x17089}, + {IOMUXC_SD1_DATA3_USDHC1_DATA3, 0U, 0x17089}, + }, + .flag = 0, +}; + +_internal_rw sd_card_t _s_sd; + +#if defined(SDCARD_SHOW_CARD_INFO) && (SDCARD_SHOW_CARD_INFO) +static void _sdcard_show_info( sd_card_t *card ) +{ + LOG_RAW("------------------------------\n"); + LOG_RAW("sd card infomation\n"); + LOG_RAW("------------------------------\n"); + + LOG_RAW("Version:\n"); + LOG_RAW(" version: %d\n", card->version); + + LOG_RAW("Bus frequency:\n"); + LOG_RAW(" freq: %d Hz\n", card->busClock_Hz); + + LOG_RAW("Capacity information:\n"); + + LOG_RAW(" sector size: %d Bytes\n", card->blockSize); + LOG_RAW(" sector count: %d\n", card->blockCount); + LOG_RAW(" block size: %d\n", card->csd.eraseSectorSize); + + LOG_RAW("Working condition:\n"); + + LOG_RAW(" voltage: "); + if (card->operationVoltage == kCARD_OperationVoltage330V) { + LOG_RAW("3.3V"); + } else if (card->operationVoltage == kCARD_OperationVoltage180V) { + LOG_RAW("1.8V"); + } + LOG_RAW("\n"); + + LOG_RAW(" timing mode: "); + if (card->currentTiming == kSD_TimingSDR12DefaultMode) + { + if (card->operationVoltage == kCARD_OperationVoltage330V) { + LOG_RAW("Default"); + } else if (card->operationVoltage == kCARD_OperationVoltage180V) { + LOG_RAW("SDR12"); + } + } else if (card->currentTiming == kSD_TimingSDR25HighSpeedMode) { + if (card->operationVoltage == kCARD_OperationVoltage180V) { + LOG_RAW("SDR25"); + } else { + LOG_RAW("High Speed"); + } + } else if (card->currentTiming == kSD_TimingSDR50Mode) { + LOG_RAW("SDR50"); + } else if (card->currentTiming == kSD_TimingSDR104Mode) { + LOG_RAW("SDR104"); + } else if (card->currentTiming == kSD_TimingDDR50Mode) { + LOG_RAW("DDR50"); + } + LOG_RAW("\n"); +} +#endif //#if defined(SDCARD_SHOW_CARD_INFO) && (SDCARD_SHOW_CARD_INFO) + +static rt_err_t sdcard_init_clock( struct imx_sddev *sddev ) +{ + RT_ASSERT(RT_NULL != sddev); + + if (IMX6ULL_USDHC1_BASE == sddev->periph.paddr) + { + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 0U); + CLOCK_EnableClock(kCLOCK_Usdhc1); + } else if (IMX6ULL_USDHC2_BASE == sddev->periph.paddr) { + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 0U); + CLOCK_EnableClock(kCLOCK_Usdhc2); + } + + return RT_EOK; +} + +static void _sdcard_gpio_init( struct imx_sddev *sddev ) +{ + RT_ASSERT(RT_NULL != sddev); + + for (int i=0; igpio[i]); + } +} + +static rt_err_t _sdcard_device_init( struct imx_sddev *sddev ) +{ + sd_card_t *card = RT_NULL; + + RT_ASSERT(RT_NULL != sddev); + RT_ASSERT(0 != sddev->periph.vaddr); + + sdcard_init_clock(sddev); + + card = &_s_sd; + + card->host.base = (USDHC_Type*)(sddev->periph.vaddr); + if (IMX6ULL_USDHC1_BASE == sddev->periph.paddr) + { + card->host.sourceClock_Hz = BOARD_USDHC1_CLK_FREQ; + } else if (IMX6ULL_USDHC2_BASE == sddev->periph.paddr) { + card->host.sourceClock_Hz = BOARD_USDHC2_CLK_FREQ; + } + + if (kStatus_Success != SD_Init(card)) + { + SD_Deinit(card); + rt_memset(card, 0U, sizeof(_s_sd)); + + LOG_W("sd card init failed."); + return -RT_ERROR; + } + + sddev->flag = 1; + + LOG_D("sd card init finished."); + LOG_D("sd card has %d sector, sector size %d Bytes.", card->blockCount, card->blockSize); + +#if defined(SDCARD_SHOW_CARD_INFO) && (SDCARD_SHOW_CARD_INFO) + _sdcard_show_info(card); +#endif + + return RT_EOK; +} + +static rt_err_t _sdcard_ops_init( rt_device_t dev ) +{ + return RT_EOK; +} + +static rt_err_t _sdcard_ops_open( rt_device_t dev, + rt_uint16_t oflag ) +{ + RT_ASSERT(RT_NULL != dev); + + if (!(dev->flag & RT_DEVICE_FLAG_RDWR)) + { + LOG_W("only support rd/wr option!"); + return -RT_ERROR; + } + + dev->ref_count++; + + return RT_EOK; +} + +static rt_err_t _sdcard_ops_close( rt_device_t dev ) +{ + RT_ASSERT(RT_NULL != dev); + + dev->ref_count = (0 == dev->ref_count) ? 0 : (dev->ref_count - 1); + + return RT_EOK; +} + +static rt_size_t _sdcard_ops_read( rt_device_t dev, + rt_off_t pos, + void *buffer, + rt_size_t size ) +{ + RT_ASSERT(RT_NULL != dev); + + if (0 == dev->ref_count) + { + return 0; + } + + if (kStatus_Success != SD_ReadBlocks(&_s_sd, buffer, SDCARD_PART2_START_SECTOR+pos, size)) + { + return 0; + } + + return size; +} + +static rt_size_t _sdcard_ops_write( rt_device_t dev, + rt_off_t pos, + const void *buffer, + rt_size_t size ) +{ + RT_ASSERT(RT_NULL != dev); + + if (0 == dev->ref_count) + { + return 0; + } + + if (kStatus_Success != SD_WriteBlocks(&_s_sd, buffer, SDCARD_PART2_START_SECTOR+pos, size)) + { + return 0; + } + + return size; +} + +static rt_err_t _sdcard_ops_control( rt_device_t dev, + int cmd, + void *args ) +{ + struct rt_device_blk_geometry *pgeometry = RT_NULL; + rt_err_t result; + + switch (cmd) + { + case RT_DEVICE_CTRL_BLK_GETGEOME: + if (args) + { + pgeometry = (struct rt_device_blk_geometry*)args; + + pgeometry->sector_count = _s_sd.blockCount; + pgeometry->bytes_per_sector = _s_sd.blockSize; + pgeometry->block_size = _s_sd.csd.eraseSectorSize; + + result = RT_EOK; + } + else + { + result = -RT_EINVAL; + } + break; + + case RT_DEVICE_CTRL_BLK_SYNC: + result = RT_EOK; + break; + + default : + result = -RT_EINVAL; + break; + } + + return result; +} + +#ifdef RT_USING_DEVICE_OPS +_internal_ro struct rt_device_ops _k_sdcard_ops = +{ + _sdcard_ops_init, /* init */ + _sdcard_ops_open, /* open */ + _sdcard_ops_close, /* close */ + _sdcard_ops_read, /* read */ + _sdcard_ops_write, /* write */ + _sdcard_ops_control, /* control */ +}; +#endif + +int rt_hw_sdcard_init(void) +{ + struct rt_device *device = RT_NULL; + + device = &_s_sdcard_device.parent; + + device->type = RT_Device_Class_Block; +#ifdef RT_USING_DEVICE_OPS + device->ops = &_k_sdcard_ops; +#else + device->init = _sdcard_ops_init; + device->open = _sdcard_ops_open; + device->close = _sdcard_ops_close; + device->read = _sdcard_ops_read; + device->write = _sdcard_ops_write; + device->control = _sdcard_ops_control; +#endif + device->user_data = RT_NULL; + + rt_device_register(device, _s_sdcard_device.name, RT_DEVICE_FLAG_RDWR); + + _s_sdcard_device.periph.vaddr = platform_get_periph_vaddr(_s_sdcard_device.periph.paddr); + + _s_sdcard_device.flag = 0; //wait for sdhc init! + + _sdcard_gpio_init(&_s_sdcard_device); + _sdcard_device_init(&_s_sdcard_device); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_sdcard_init); + +#endif //#ifdef BSP_USING_SDHC diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_sdhc.h b/bsp/imx6ull-artpi-smart/drivers/drv_sdhc.h new file mode 100644 index 0000000000..431c07acac --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_sdhc.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-04-23 Lyons first version + */ + +#ifndef __DRV_SDHC_H__ +#define __DRV_SDHC_H__ + +#include "board.h" +#include "drv_common.h" + +#ifdef BSP_USING_SDHC + +/* Fixed value, not edit! */ +#define SDCARD_CONTROL_PIN_NUM (6) + +struct imx_periph +{ + rt_uint32_t paddr; + rt_uint32_t vaddr; +}; + +struct imx_sddev +{ + struct rt_device parent; + + const char *name; + struct imx_periph periph; + rt_uint32_t irqno; + + struct imx6ull_iomuxc gpio[SDCARD_CONTROL_PIN_NUM]; + + rt_uint32_t flag; +}; + +#endif //#ifdef BSP_USING_SDHC +#endif //#ifndef __DRV_SDHC_H__ diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_spi.c b/bsp/imx6ull-artpi-smart/drivers/drv_spi.c new file mode 100644 index 0000000000..a00d86d41a --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_spi.c @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-13 Lyons first version + * 2021-06-23 RiceChen refactor + */ + +#include +#include + +#ifdef BSP_USING_SPI + +#define LOG_TAG "drv.spi" +#include + +#include "fsl_iomuxc.h" +#include "drv_spi.h" + +static struct imx6ull_spi_config spi_config[] = +{ +#ifdef BSP_USING_SPI1 + SPI1_BUS_CONFIG, +#endif +#ifdef BSP_USING_SPI2 + SPI2_BUS_CONFIG, +#endif +#ifdef BSP_USING_SPI3 + SPI3_BUS_CONFIG, +#endif +#ifdef BSP_USING_SPI4 + SPI4_BUS_CONFIG, +#endif +}; + +static struct imx6ull_spi_bus spi_obj[sizeof(spi_config) / sizeof(spi_config[0])]; + +static rt_err_t imx6ull_ecspi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) +{ + struct imx6ull_spi_bus *spi_dev = RT_NULL; + ecspi_master_config_t config; + rt_uint32_t scr_clock = 0; + + spi_dev = (struct imx6ull_spi_bus *)(device->bus->parent.user_data); + + ECSPI_MasterGetDefaultConfig(&config); + + config.samplePeriod = 10; + config.txFifoThreshold = 0; + config.channelConfig.dataLineInactiveState = kECSPI_DataLineInactiveStateHigh; + + if (cfg->data_width == 8) + { + config.burstLength = 8; + } + else + { + return -RT_EINVAL; + } + + if (cfg->mode & RT_SPI_SLAVE) + { + config.channelConfig.channelMode = kECSPI_Slave; + } + else + { + config.channelConfig.channelMode = kECSPI_Master; + } + + if(cfg->mode & RT_SPI_CPHA) + { + config.channelConfig.phase = kECSPI_ClockPhaseSecondEdge; + } + else + { + config.channelConfig.phase = kECSPI_ClockPhaseFirstEdge; + } + + if(cfg->mode & RT_SPI_CPOL) + { + config.channelConfig.polarity = kECSPI_PolarityActiveLow; + } + else + { + config.channelConfig.polarity = kECSPI_PolarityActiveHigh; + } + + config.baudRate_Bps = cfg->max_hz; + + scr_clock = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 8U); + ECSPI_MasterInit(spi_dev->config->ECSPI, &config, scr_clock); + return RT_EOK; +} + +static rt_uint32_t imx6ull_ecspi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + struct imx6ull_spi_bus *spi_dev = RT_NULL; + struct imx6ull_spi_cs *cs = RT_NULL; + + const rt_uint8_t *send_ptr = RT_NULL; + rt_uint8_t *recv_ptr = RT_NULL; + rt_uint16_t size = 0; + rt_uint8_t temp_data; + + spi_dev = (struct imx6ull_spi_bus *)(device->bus->parent.user_data); + cs = (struct imx6ull_spi_cs *)device->parent.user_data; + + recv_ptr = (rt_uint8_t *)message->recv_buf; + send_ptr = (rt_uint8_t *)message->send_buf; + size = message->length; + + if(message->cs_take && cs) + { + rt_pin_write(cs->pin, PIN_LOW); + } + + ECSPI_SetChannelSelect(spi_dev->config->ECSPI, kECSPI_Channel0); + while (size--) + { + temp_data = (send_ptr != RT_NULL) ? (*send_ptr++) : 0xff; + + while (!(spi_dev->config->ECSPI->STATREG & ECSPI_STATREG_TE_MASK)); + ECSPI_WriteData(spi_dev->config->ECSPI, temp_data); + + while (!(spi_dev->config->ECSPI->STATREG & ECSPI_STATREG_RR_MASK)); + temp_data = ECSPI_ReadData(spi_dev->config->ECSPI); + + if (recv_ptr != RT_NULL) + { + *recv_ptr++ = temp_data; + } + } + + if(message->cs_release && cs) + { + rt_pin_write(cs->pin, PIN_HIGH); + } + + return message->length; +} + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin) +{ + rt_err_t ret = RT_EOK; + + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + struct imx6ull_spi_cs *cs_pin = (struct imx6ull_spi_cs *)rt_malloc(sizeof(struct imx6ull_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + + cs_pin->pin = pin; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, PIN_HIGH); + + ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + return ret; +} + +static rt_err_t imx6ull_spi_gpio_init(struct imx6ull_spi_bus *bus) +{ + struct imx6ull_spi_bus *spi_bus = RT_NULL; + + spi_bus = (struct imx6ull_spi_bus *)bus; + + imx6ull_gpio_init(&spi_bus->config->clk_gpio); + imx6ull_gpio_init(&spi_bus->config->miso_gpio); + imx6ull_gpio_init(&spi_bus->config->mosi_gpio); + + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +static const struct rt_spi_ops imxrt_spi_ops = +{ + .configure = imx6ull_ecspi_configure, + .xfer = imx6ull_ecspi_xfer, +}; +#endif + +int rt_hw_spi_init(void) +{ + rt_uint16_t obj_num = 0; + + obj_num = sizeof(spi_config) / sizeof(spi_config[0]); + + for(int i = 0; i < obj_num; i++) + { + spi_obj[i].config = &spi_config[i]; + spi_obj[i].config->ECSPI = (ECSPI_Type *)imx6ull_get_periph_vaddr((rt_uint32_t)(spi_obj[i].config->ECSPI)); + imx6ull_spi_gpio_init(&spi_obj[i]); + + CLOCK_EnableClock(spi_obj[i].config->clk_ip_name); + + spi_obj[i].parent.parent.user_data = &spi_obj[i]; + rt_spi_bus_register(&spi_obj[i].parent, spi_obj[i].config->name, &imxrt_spi_ops); + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_spi_init); + +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_spi.h b/bsp/imx6ull-artpi-smart/drivers/drv_spi.h new file mode 100644 index 0000000000..590e589974 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_spi.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-13 Lyons first version + * 2021-06-23 RiceChen refactor + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include "drv_common.h" + +#include "fsl_iomuxc.h" +#include "fsl_clock.h" +#include "fsl_ecspi.h" + +struct imx6ull_spi_cs +{ + rt_uint32_t pin; +}; + +struct imx6ull_spi_config +{ + ECSPI_Type *ECSPI; + char *name; + + rt_uint32_t clk_ip_name; + + struct imx6ull_iomuxc clk_gpio; + struct imx6ull_iomuxc miso_gpio; + struct imx6ull_iomuxc mosi_gpio; +}; + +struct imx6ull_spi_bus +{ + struct rt_spi_bus parent; + struct imx6ull_spi_config *config; +}; + +#ifdef BSP_USING_SPI1 +#define SPI1_BUS_CONFIG \ + { \ + .ECSPI = ECSPI1, \ + .name = "spi1", \ + .clk_ip_name = kCLOCK_Ecspi1, \ + .clk_gpio = {IOMUXC_CSI_DATA04_ECSPI1_SCLK, 0, 0X10B1}, \ + .miso_gpio = {IOMUXC_CSI_DATA07_ECSPI1_MISO, 0, 0X10B1}, \ + .mosi_gpio = {IOMUXC_CSI_DATA06_ECSPI1_MOSI, 0, 0X10B1}, \ + } +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_USING_SPI2 +#define SPI2_BUS_CONFIG \ + { \ + .ECSPI = ECSPI2, \ + .name = "spi2", \ + .clk_ip_name = kCLOCK_Ecspi2, \ + .clk_gpio = {IOMUXC_UART4_TX_DATA_ECSPI2_SCLK, 0, 0X10B1}, \ + .miso_gpio = {IOMUXC_UART5_RX_DATA_ECSPI2_MISO, 0, 0X10B1}, \ + .mosi_gpio = {IOMUXC_UART5_TX_DATA_ECSPI2_MOSI, 0, 0X10B1}, \ + } + +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_USING_SPI3 +#define SPI3_BUS_CONFIG \ + { \ + .ECSPI = ECSPI3, \ + .name = "spi3", \ + .clk_ip_name = kCLOCK_Ecspi3, \ + .clk_gpio = {IOMUXC_UART2_RX_DATA_ECSPI3_SCLK, 0, 0X10B1}, \ + .miso_gpio = {IOMUXC_UART2_RTS_B_ECSPI3_MISO, 0, 0X10B1}, \ + .mosi_gpio = {IOMUXC_UART2_CTS_B_ECSPI3_MOSI, 0, 0X10B1}, \ + } + +#endif /* BSP_USING_SPI3 */ + +#ifdef BSP_USING_SPI4 +#define SPI4_BUS_CONFIG \ + { \ + .ECSPI = ECSPI4, \ + .name = "spi4", \ + .clk_ip_name = kCLOCK_Ecspi4, \ + .clk_gpio = {IOMUXC_ENET2_TX_DATA1_ECSPI4_SCLK, 0, 0X10B1}, \ + .miso_gpio = {IOMUXC_ENET2_TX_CLK_ECSPI4_MISO, 0, 0X10B1}, \ + .mosi_gpio = {IOMUXC_ENET2_TX_EN_ECSPI4_MOSI, 0, 0X10B1}, \ + } + +#endif /* BSP_USING_SPI4 */ + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin); + +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_timer.c b/bsp/imx6ull-artpi-smart/drivers/drv_timer.c new file mode 100644 index 0000000000..9001ba65de --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_timer.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-22 Jesven first version + */ + +#include +#include +#include + +#include +#include "mmu.h" + +#define TICK_PERIOD (g_sys_freq / RT_TICK_PER_SECOND) +static int g_sys_freq; + +#define IRQ_SECURE_PHY_TIMER 29 /* Secure physical timer event */ +#define IRQ_NOSECURE_PHY_TIMER 30 /* No-Secure physical timer event */ + +#define IRQ_SYS_TICK IRQ_SECURE_PHY_TIMER + + +/* System Counter */ +struct sctr_regs { + rt_uint32_t cntcr; + rt_uint32_t cntsr; + rt_uint32_t cntcv1; + rt_uint32_t cntcv2; + rt_uint32_t resv1[4]; + rt_uint32_t cntfid0; + rt_uint32_t cntfid1; + rt_uint32_t cntfid2; + rt_uint32_t resv2[1001]; + rt_uint32_t counterid[1]; +}; + +#define SC_CNTCR_ENABLE (1 << 0) +#define SC_CNTCR_HDBG (1 << 1) +#define SC_CNTCR_FREQ0 (1 << 8) +#define SC_CNTCR_FREQ1 (1 << 9) + + +#define isb() __asm__ __volatile__ ("" : : : "memory") +#define dsb() __asm__ __volatile__ ("" : : : "memory") +#define dmb() __asm__ __volatile__ ("" : : : "memory") + + +static inline void enable_cntp(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 1; + asm volatile ("mcr p15, 0, %0, c14, c2, 1" :: "r"(cntv_ctl)); // write CNTP_CTL + isb(); +} + +static inline void disable_cntp(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 0; + asm volatile ("mcr p15, 0, %0, c14, c2, 1" :: "r"(cntv_ctl)); // write CNTP_CTL + isb(); +} + +static inline rt_uint32_t read_cntfrq(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val)); + return val; +} + +static inline void write_cntp_tval(rt_uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c14, c2, 0" :: "r"(val)); + isb(); + return; +} + +static inline void write_cntp_cval(rt_uint64_t val) +{ + asm volatile ("mcrr p15, 2, %Q0, %R0, c14" :: "r" (val)); + isb(); + return; +} + +static inline rt_uint64_t read_cntp_cval(void) +{ + rt_uint64_t val; + asm volatile ("mrrc p15, 2, %Q0, %R0, c14" : "=r" (val)); + return (val); +} + +volatile unsigned int *CCM_CLPCR; + +static void imx6ull_enable_clk_in_waitmode(void) +{ + CCM_CLPCR = rt_ioremap((void*)0x20C4054, 4); + *CCM_CLPCR &= ~((1 << 5) | 0x3); +} + +static void system_counter_clk_source_init(void) +{ + /* to do */ +} + +static void system_counter_init(void) +{ + /* enable system_counter */ +#define SCTR_BASE_ADDR 0x021DC000 +#define CONFIG_SC_TIMER_CLK 8000000 + + /* imx6ull, enable system counter */ + struct sctr_regs *sctr = (struct sctr_regs *)rt_ioremap((void*)SCTR_BASE_ADDR, sizeof(struct sctr_regs)); + unsigned long val, freq; + + freq = CONFIG_SC_TIMER_CLK; + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); + + sctr->cntfid0 = freq; + + /* Enable system counter */ + val = sctr->cntcr; + val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1); + val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG; + sctr->cntcr = val; + + imx6ull_enable_clk_in_waitmode(); +} + +static void arch_timer_init(void) +{ + g_sys_freq = read_cntfrq(); + + /* set timeout val */ + disable_cntp(); + write_cntp_tval(TICK_PERIOD); + + /* start timer */ + enable_cntp(); + + /* enable irq */ +} + +static void rt_hw_timer_isr(int vector, void *param) +{ + rt_tick_increase(); + + /* setup for next irq */ + /* clear interrupt */ + disable_cntp(); + write_cntp_cval(read_cntp_cval() + TICK_PERIOD); + enable_cntp(); +} + +int rt_hw_timer_init(void) +{ + /* Setup Timer for generating irq */ + /* enable timer */ + system_counter_clk_source_init(); + system_counter_init(); + arch_timer_init(); + + /* insall irq, enable irq */ + rt_hw_interrupt_install(IRQ_SYS_TICK, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(IRQ_SYS_TICK); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_timer_init); diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_timer.h b/bsp/imx6ull-artpi-smart/drivers/drv_timer.h new file mode 100644 index 0000000000..c50b073d36 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_timer.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-22 Jesven first version + */ + +#ifndef DRV_TIMER_H__ +#define DRV_TIMER_H__ + +void timer_init(int timer, unsigned int preload); +void timer_clear_pending(int timer); + +#endif diff --git a/bsp/imx6ull-artpi-smart/drivers/drv_uart.c b/bsp/imx6ull-artpi-smart/drivers/drv_uart.c new file mode 100644 index 0000000000..2a23cd6dbc --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/drv_uart.c @@ -0,0 +1,350 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-09 Lyons first version + */ + +#include + +#ifdef RT_USING_SERIAL + +#include "board.h" +#include "drv_uart.h" +#include "drv_common.h" + +enum +{ +#ifdef BSP_USING_UART1 + eDevUart_UART1, +#endif +#ifdef BSP_USING_UART2 + eDevUart_UART2, +#endif +#ifdef BSP_USING_UART3 + eDevUart_UART3, +#endif +#ifdef BSP_USING_UART4 + eDevUart_UART4, +#endif +#ifdef BSP_USING_UART5 + eDevUart_UART5, +#endif +#ifdef BSP_USING_UART6 + eDevUart_UART6, +#endif +#ifdef BSP_USING_UART7 + eDevUart_UART7, +#endif +#ifdef BSP_USING_UART8 + eDevUart_UART8, +#endif + + eDevUart_Max, +}; + +_internal_rw struct imx_uart _s_uart[eDevUart_Max] = { +#ifdef BSP_USING_UART1 +{ + .name = "uart0", + .periph.paddr = IMX6ULL_UART1_BASE, + .irqno = UART1_IRQn, + .gpio = { + {IOMUXC_UART1_TX_DATA_UART1_TX, 0, 0x10B0}, + {IOMUXC_UART1_RX_DATA_UART1_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_115200N81, +}, +#endif + +#ifdef BSP_USING_UART2 +{ + .name = "uart1", + .periph.paddr = IMX6ULL_UART2_BASE, + .irqno = UART2_IRQn, + .gpio = { + {IOMUXC_UART2_TX_DATA_UART2_TX, 0, 0x10B0}, + {IOMUXC_UART2_RX_DATA_UART2_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_DEFAULT, +}, +#endif + +#ifdef BSP_USING_UART3 +{ + .name = "uart2", + .periph.paddr = IMX6ULL_UART3_BASE, + .irqno = UART3_IRQn, + .gpio = { + {IOMUXC_UART3_TX_DATA_UART3_TX, 0, 0x10B0}, + {IOMUXC_UART3_RX_DATA_UART3_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_DEFAULT, +}, +#endif + +#ifdef BSP_USING_UART4 +{ + .name = "uart3", + .periph.paddr = IMX6ULL_UART4_BASE, + .irqno = UART4_IRQn, + .gpio = { + {IOMUXC_UART4_TX_DATA_UART4_TX, 0, 0x10B0}, + {IOMUXC_UART4_RX_DATA_UART4_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_DEFAULT, +}, +#endif + +#ifdef BSP_USING_UART5 +{ + .name = "uart4", + .periph.paddr = IMX6ULL_UART5_BASE, + .irqno = UART5_IRQn, + .gpio = { + {IOMUXC_UART5_TX_DATA_UART5_TX, 0, 0x10B0}, + {IOMUXC_UART5_RX_DATA_UART5_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_DEFAULT, +}, +#endif + +#ifdef BSP_USING_UART6 +{ + .name = "uart5", + .periph.paddr = IMX6ULL_UART6_BASE, + .irqno = UART6_IRQn, + .gpio = { + {IOMUXC_ENET2_RX_DATA1_UART6_TX, 0, 0x10B0}, + {IOMUXC_ENET2_RX_DATA0_UART6_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_DEFAULT, +}, +#endif + +#ifdef BSP_USING_UART7 +{ + .name = "uart6", + .periph.paddr = IMX6ULL_UART7_BASE, + .irqno = UART7_IRQn, + .gpio = { + {IOMUXC_ENET2_TX_DATA0_UART7_TX, 0, 0x10B0}, + {IOMUXC_ENET2_RX_EN_UART7_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_DEFAULT, +}, +#endif + +#ifdef BSP_USING_UART8 +{ + .name = "uart7", + .periph.paddr = IMX6ULL_UART8_BASE, + .irqno = UART8_IRQn, + .gpio = { + {IOMUXC_ENET2_TX_DATA1_UART8_TX, 0, 0x10B0}, + {IOMUXC_ENET2_TX_EN_UART8_RX, 0, 0x10B0}, + }, + .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX), + .param = RT_SERIAL_CONFIG_DEFAULT, +}, +#endif +}; + +static void _uart_gpio_init( struct imx_uart *device ) +{ + for (int i=0; igpio); i++) + { + imx6ull_gpio_init(&device->gpio[i]); + } +} + +static rt_err_t _uart_ops_configure( struct rt_serial_device *dev, + struct serial_configure *cfg ) +{ + struct imx_uart *uart = RT_NULL; + UART_Type *periph = RT_NULL; + rt_uint32_t reg_value; + + RT_ASSERT(RT_NULL != dev); + RT_ASSERT(RT_NULL != cfg); + + uart = (struct imx_uart*)dev; + periph = (UART_Type*)uart->periph.vaddr; + + _uart_gpio_init(uart); + + periph->UCR1 &= ~UART_UCR1_UARTEN_MASK; + + periph->UFCR &= ~UART_UFCR_RFDIV_MASK; + periph->UFCR |= UART_UFCR_RFDIV(5); + + RT_ASSERT(cfg->baud_rate <= BAUD_RATE_921600); + + periph->UBIR = UART_UBIR_INC(15); + periph->UBMR = UART_UBMR_MOD(HW_UART_BUS_CLOCK / cfg->baud_rate - 1); + + reg_value = 0; + + switch (cfg->data_bits) + { + case DATA_BITS_7: + reg_value |= UART_UCR2_WS(0); + break; + default: + reg_value |= UART_UCR2_WS(1); + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_2: + reg_value |= UART_UCR2_STPB(1); + break; + default: + reg_value |= UART_UCR2_STPB(0); + break; + } + + switch (cfg->parity) + { + case PARITY_ODD: + reg_value |= UART_UCR2_PREN(1); + reg_value |= UART_UCR2_PROE(1); + break; + case PARITY_EVEN: + reg_value |= UART_UCR2_PREN(1); + reg_value |= UART_UCR2_PROE(0); + break; + default: + reg_value |= UART_UCR2_PREN(0); + reg_value |= UART_UCR2_PROE(0); + break; + } + + periph->UCR3 |= UART_UCR3_RXDMUXSEL(1); //this bit should always be set! + periph->UCR2 |= reg_value | UART_UCR2_IRTS(1) | UART_UCR2_TXEN(1) | UART_UCR2_RXEN(1); + periph->UCR1 |= UART_UCR1_UARTEN(1); + + return RT_EOK; +} + +static rt_err_t _uart_ops_control( struct rt_serial_device *dev, + int cmd, + void *arg ) +{ + struct imx_uart *uart = RT_NULL; + UART_Type *periph = RT_NULL; + rt_err_t result; + + RT_ASSERT(RT_NULL != dev); + + uart = (struct imx_uart*)dev; + periph = (UART_Type*)uart->periph.vaddr; + + result = RT_EOK; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + periph->UCR4 &= ~UART_UCR4_DREN_MASK; + periph->UCR4 |= UART_UCR4_DREN(0); + break; + + case RT_DEVICE_CTRL_SET_INT: + periph->UCR4 |= UART_UCR4_DREN(1); + rt_hw_interrupt_umask(uart->irqno); + break; + + default: + result = -RT_EINVAL; + break; + } + + return result; +} + +static int _uart_ops_putc( struct rt_serial_device *dev, + char ch ) +{ + struct imx_uart *uart = RT_NULL; + UART_Type *periph = RT_NULL; + + RT_ASSERT(RT_NULL != dev); + + uart = (struct imx_uart*)dev; + periph = (UART_Type*)uart->periph.vaddr; + + while (0 == (periph->USR2 & UART_USR2_TXDC_MASK)); + periph->UTXD = ch; + + return 1; +} + +static int _uart_ops_getc( struct rt_serial_device *dev ) +{ + struct imx_uart *uart = RT_NULL; + UART_Type *periph = RT_NULL; + int ch; + + RT_ASSERT(RT_NULL != dev); + + uart = (struct imx_uart*)dev; + periph = (UART_Type*)uart->periph.vaddr; + + ch = (0 == (periph->USR2 & UART_USR2_RDR_MASK)) ? -1 : periph->URXD; + return ch; +} + +_internal_ro struct rt_uart_ops _k_uart_ops = +{ + _uart_ops_configure, /* configure */ + _uart_ops_control, /* control */ + _uart_ops_putc, /* putc */ + _uart_ops_getc, /* getc */ + RT_NULL, /* dma_transmit */ +}; + +static void _uart_isr( int irqno, void* parameter ) +{ + struct rt_serial_device *serial; + + rt_interrupt_enter(); + + serial = (struct rt_serial_device *)parameter; + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + + rt_interrupt_leave(); +} + +int rt_hw_uart_init(void) +{ + for (int idx=0; idx?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~ +//modulus mode : column type + +//12*12 ASCII +const unsigned char _k_ascii_1206_tbl[95][12] = { + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ + {0x00,0x00,0x00,0x00,0x3F,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/ + {0x00,0x00,0x30,0x00,0x40,0x00,0x30,0x00,0x40,0x00,0x00,0x00},/*""",2*/ + {0x09,0x00,0x0B,0xC0,0x3D,0x00,0x0B,0xC0,0x3D,0x00,0x09,0x00},/*"#",3*/ + {0x18,0xC0,0x24,0x40,0x7F,0xE0,0x22,0x40,0x31,0x80,0x00,0x00},/*"$",4*/ + {0x18,0x00,0x24,0xC0,0x1B,0x00,0x0D,0x80,0x32,0x40,0x01,0x80},/*"%",5*/ + {0x03,0x80,0x1C,0x40,0x27,0x40,0x1C,0x80,0x07,0x40,0x00,0x40},/*"&",6*/ + {0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x80,0x20,0x40,0x40,0x20},/*"(",8*/ + {0x00,0x00,0x40,0x20,0x20,0x40,0x1F,0x80,0x00,0x00,0x00,0x00},/*")",9*/ + {0x09,0x00,0x06,0x00,0x1F,0x80,0x06,0x00,0x09,0x00,0x00,0x00},/*"*",10*/ + {0x04,0x00,0x04,0x00,0x3F,0x80,0x04,0x00,0x04,0x00,0x00,0x00},/*"+",11*/ + {0x00,0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/ + {0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x00,0x00},/*"-",13*/ + {0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/ + {0x00,0x20,0x01,0xC0,0x06,0x00,0x38,0x00,0x40,0x00,0x00,0x00},/*"/",15*/ + {0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"0",16*/ + {0x00,0x00,0x10,0x40,0x3F,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*"1",17*/ + {0x18,0xC0,0x21,0x40,0x22,0x40,0x24,0x40,0x18,0x40,0x00,0x00},/*"2",18*/ + {0x10,0x80,0x20,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"3",19*/ + {0x02,0x00,0x0D,0x00,0x11,0x00,0x3F,0xC0,0x01,0x40,0x00,0x00},/*"4",20*/ + {0x3C,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x23,0x80,0x00,0x00},/*"5",21*/ + {0x1F,0x80,0x24,0x40,0x24,0x40,0x34,0x40,0x03,0x80,0x00,0x00},/*"6",22*/ + {0x30,0x00,0x20,0x00,0x27,0xC0,0x38,0x00,0x20,0x00,0x00,0x00},/*"7",23*/ + {0x1B,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"8",24*/ + {0x1C,0x00,0x22,0xC0,0x22,0x40,0x22,0x40,0x1F,0x80,0x00,0x00},/*"9",25*/ + {0x00,0x00,0x00,0x00,0x08,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ + {0x00,0x00,0x00,0x00,0x04,0x60,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ + {0x00,0x00,0x04,0x00,0x0A,0x00,0x11,0x00,0x20,0x80,0x40,0x40},/*"<",28*/ + {0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x00,0x00},/*"=",29*/ + {0x00,0x00,0x40,0x40,0x20,0x80,0x11,0x00,0x0A,0x00,0x04,0x00},/*">",30*/ + {0x18,0x00,0x20,0x00,0x23,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*"?",31*/ + {0x1F,0x80,0x20,0x40,0x27,0x40,0x29,0x40,0x1F,0x40,0x00,0x00},/*"@",32*/ + {0x00,0x40,0x07,0xC0,0x39,0x00,0x0F,0x00,0x01,0xC0,0x00,0x40},/*"A",33*/ + {0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"B",34*/ + {0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x30,0x80,0x00,0x00},/*"C",35*/ + {0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"D",36*/ + {0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x40,0x30,0xC0,0x00,0x00},/*"E",37*/ + {0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x00,0x30,0x00,0x00,0x00},/*"F",38*/ + {0x0F,0x00,0x10,0x80,0x20,0x40,0x22,0x40,0x33,0x80,0x02,0x00},/*"G",39*/ + {0x20,0x40,0x3F,0xC0,0x04,0x00,0x04,0x00,0x3F,0xC0,0x20,0x40},/*"H",40*/ + {0x20,0x40,0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x00,0x00},/*"I",41*/ + {0x00,0x60,0x20,0x20,0x20,0x20,0x3F,0xC0,0x20,0x00,0x20,0x00},/*"J",42*/ + {0x20,0x40,0x3F,0xC0,0x24,0x40,0x0B,0x00,0x30,0xC0,0x20,0x40},/*"K",43*/ + {0x20,0x40,0x3F,0xC0,0x20,0x40,0x00,0x40,0x00,0x40,0x00,0xC0},/*"L",44*/ + {0x3F,0xC0,0x3C,0x00,0x03,0xC0,0x3C,0x00,0x3F,0xC0,0x00,0x00},/*"M",45*/ + {0x20,0x40,0x3F,0xC0,0x0C,0x40,0x23,0x00,0x3F,0xC0,0x20,0x00},/*"N",46*/ + {0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"O",47*/ + {0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*"P",48*/ + {0x1F,0x80,0x21,0x40,0x21,0x40,0x20,0xE0,0x1F,0xA0,0x00,0x00},/*"Q",49*/ + {0x20,0x40,0x3F,0xC0,0x24,0x40,0x26,0x00,0x19,0xC0,0x00,0x40},/*"R",50*/ + {0x18,0xC0,0x24,0x40,0x24,0x40,0x22,0x40,0x31,0x80,0x00,0x00},/*"S",51*/ + {0x30,0x00,0x20,0x40,0x3F,0xC0,0x20,0x40,0x30,0x00,0x00,0x00},/*"T",52*/ + {0x20,0x00,0x3F,0x80,0x00,0x40,0x00,0x40,0x3F,0x80,0x20,0x00},/*"U",53*/ + {0x20,0x00,0x3E,0x00,0x01,0xC0,0x07,0x00,0x38,0x00,0x20,0x00},/*"V",54*/ + {0x38,0x00,0x07,0xC0,0x3C,0x00,0x07,0xC0,0x38,0x00,0x00,0x00},/*"W",55*/ + {0x20,0x40,0x39,0xC0,0x06,0x00,0x39,0xC0,0x20,0x40,0x00,0x00},/*"X",56*/ + {0x20,0x00,0x38,0x40,0x07,0xC0,0x38,0x40,0x20,0x00,0x00,0x00},/*"Y",57*/ + {0x30,0x40,0x21,0xC0,0x26,0x40,0x38,0x40,0x20,0xC0,0x00,0x00},/*"Z",58*/ + {0x00,0x00,0x00,0x00,0x7F,0xE0,0x40,0x20,0x40,0x20,0x00,0x00},/*"[",59*/ + {0x00,0x00,0x70,0x00,0x0C,0x00,0x03,0x80,0x00,0x40,0x00,0x00},/*"\",60*/ + {0x00,0x00,0x40,0x20,0x40,0x20,0x7F,0xE0,0x00,0x00,0x00,0x00},/*"]",61*/ + {0x00,0x00,0x20,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00},/*"^",62*/ + {0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10},/*"_",63*/ + {0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/ + {0x00,0x00,0x02,0x80,0x05,0x40,0x05,0x40,0x03,0xC0,0x00,0x40},/*"a",65*/ + {0x20,0x00,0x3F,0xC0,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*"b",66*/ + {0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x06,0x40,0x00,0x00},/*"c",67*/ + {0x00,0x00,0x03,0x80,0x04,0x40,0x24,0x40,0x3F,0xC0,0x00,0x40},/*"d",68*/ + {0x00,0x00,0x03,0x80,0x05,0x40,0x05,0x40,0x03,0x40,0x00,0x00},/*"e",69*/ + {0x00,0x00,0x04,0x40,0x1F,0xC0,0x24,0x40,0x24,0x40,0x20,0x00},/*"f",70*/ + {0x00,0x00,0x02,0xE0,0x05,0x50,0x05,0x50,0x06,0x50,0x04,0x20},/*"g",71*/ + {0x20,0x40,0x3F,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*"h",72*/ + {0x00,0x00,0x04,0x40,0x27,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*"i",73*/ + {0x00,0x10,0x00,0x10,0x04,0x10,0x27,0xE0,0x00,0x00,0x00,0x00},/*"j",74*/ + {0x20,0x40,0x3F,0xC0,0x01,0x40,0x07,0x00,0x04,0xC0,0x04,0x40},/*"k",75*/ + {0x20,0x40,0x20,0x40,0x3F,0xC0,0x00,0x40,0x00,0x40,0x00,0x00},/*"l",76*/ + {0x07,0xC0,0x04,0x00,0x07,0xC0,0x04,0x00,0x03,0xC0,0x00,0x00},/*"m",77*/ + {0x04,0x40,0x07,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*"n",78*/ + {0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*"o",79*/ + {0x04,0x10,0x07,0xF0,0x04,0x50,0x04,0x40,0x03,0x80,0x00,0x00},/*"p",80*/ + {0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x50,0x07,0xF0,0x00,0x10},/*"q",81*/ + {0x04,0x40,0x07,0xC0,0x02,0x40,0x04,0x00,0x04,0x00,0x00,0x00},/*"r",82*/ + {0x00,0x00,0x06,0x40,0x05,0x40,0x05,0x40,0x04,0xC0,0x00,0x00},/*"s",83*/ + {0x00,0x00,0x04,0x00,0x1F,0x80,0x04,0x40,0x00,0x40,0x00,0x00},/*"t",84*/ + {0x04,0x00,0x07,0x80,0x00,0x40,0x04,0x40,0x07,0xC0,0x00,0x40},/*"u",85*/ + {0x04,0x00,0x07,0x00,0x04,0xC0,0x01,0x80,0x06,0x00,0x04,0x00},/*"v",86*/ + {0x06,0x00,0x01,0xC0,0x07,0x00,0x01,0xC0,0x06,0x00,0x00,0x00},/*"w",87*/ + {0x04,0x40,0x06,0xC0,0x01,0x00,0x06,0xC0,0x04,0x40,0x00,0x00},/*"x",88*/ + {0x04,0x10,0x07,0x10,0x04,0xE0,0x01,0x80,0x06,0x00,0x04,0x00},/*"y",89*/ + {0x00,0x00,0x04,0x40,0x05,0xC0,0x06,0x40,0x04,0x40,0x00,0x00},/*"z",90*/ + {0x00,0x00,0x00,0x00,0x04,0x00,0x7B,0xE0,0x40,0x20,0x00,0x00},/*"{",91*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00},/*"|",92*/ + {0x00,0x00,0x40,0x20,0x7B,0xE0,0x04,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ + {0x40,0x00,0x80,0x00,0x40,0x00,0x20,0x00,0x20,0x00,0x40,0x00},/*"~",94*/ +}; + +//16*16 ASCII +const unsigned char _k_ascii_1608_tbl[95][16] = { + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xCC,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/ + {0x00,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x00,0x00},/*""",2*/ + {0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x00,0x00},/*"#",3*/ + {0x00,0x00,0x0E,0x18,0x11,0x04,0x3F,0xFF,0x10,0x84,0x0C,0x78,0x00,0x00,0x00,0x00},/*"$",4*/ + {0x0F,0x00,0x10,0x84,0x0F,0x38,0x00,0xC0,0x07,0x78,0x18,0x84,0x00,0x78,0x00,0x00},/*"%",5*/ + {0x00,0x78,0x0F,0x84,0x10,0xC4,0x11,0x24,0x0E,0x98,0x00,0xE4,0x00,0x84,0x00,0x08},/*"&",6*/ + {0x08,0x00,0x68,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xE0,0x18,0x18,0x20,0x04,0x40,0x02,0x00,0x00},/*"(",8*/ + {0x00,0x00,0x40,0x02,0x20,0x04,0x18,0x18,0x07,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/ + {0x02,0x40,0x02,0x40,0x01,0x80,0x0F,0xF0,0x01,0x80,0x02,0x40,0x02,0x40,0x00,0x00},/*"*",10*/ + {0x00,0x80,0x00,0x80,0x00,0x80,0x0F,0xF8,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x00},/*"+",11*/ + {0x00,0x01,0x00,0x0D,0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/ + {0x00,0x00,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80},/*"-",13*/ + {0x00,0x00,0x00,0x0C,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/ + {0x00,0x00,0x00,0x06,0x00,0x18,0x00,0x60,0x01,0x80,0x06,0x00,0x18,0x00,0x20,0x00},/*"/",15*/ + {0x00,0x00,0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"0",16*/ + {0x00,0x00,0x08,0x04,0x08,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"1",17*/ + {0x00,0x00,0x0E,0x0C,0x10,0x14,0x10,0x24,0x10,0x44,0x11,0x84,0x0E,0x0C,0x00,0x00},/*"2",18*/ + {0x00,0x00,0x0C,0x18,0x10,0x04,0x11,0x04,0x11,0x04,0x12,0x88,0x0C,0x70,0x00,0x00},/*"3",19*/ + {0x00,0x00,0x00,0xE0,0x03,0x20,0x04,0x24,0x08,0x24,0x1F,0xFC,0x00,0x24,0x00,0x00},/*"4",20*/ + {0x00,0x00,0x1F,0x98,0x10,0x84,0x11,0x04,0x11,0x04,0x10,0x88,0x10,0x70,0x00,0x00},/*"5",21*/ + {0x00,0x00,0x07,0xF0,0x08,0x88,0x11,0x04,0x11,0x04,0x18,0x88,0x00,0x70,0x00,0x00},/*"6",22*/ + {0x00,0x00,0x1C,0x00,0x10,0x00,0x10,0xFC,0x13,0x00,0x1C,0x00,0x10,0x00,0x00,0x00},/*"7",23*/ + {0x00,0x00,0x0E,0x38,0x11,0x44,0x10,0x84,0x10,0x84,0x11,0x44,0x0E,0x38,0x00,0x00},/*"8",24*/ + {0x00,0x00,0x07,0x00,0x08,0x8C,0x10,0x44,0x10,0x44,0x08,0x88,0x07,0xF0,0x00,0x00},/*"9",25*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x0C,0x03,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ + {0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ + {0x00,0x00,0x00,0x80,0x01,0x40,0x02,0x20,0x04,0x10,0x08,0x08,0x10,0x04,0x00,0x00},/*"<",28*/ + {0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x00,0x00},/*"=",29*/ + {0x00,0x00,0x10,0x04,0x08,0x08,0x04,0x10,0x02,0x20,0x01,0x40,0x00,0x80,0x00,0x00},/*">",30*/ + {0x00,0x00,0x0E,0x00,0x12,0x00,0x10,0x0C,0x10,0x6C,0x10,0x80,0x0F,0x00,0x00,0x00},/*"?",31*/ + {0x03,0xE0,0x0C,0x18,0x13,0xE4,0x14,0x24,0x17,0xC4,0x08,0x28,0x07,0xD0,0x00,0x00},/*"@",32*/ + {0x00,0x04,0x00,0x3C,0x03,0xC4,0x1C,0x40,0x07,0x40,0x00,0xE4,0x00,0x1C,0x00,0x04},/*"A",33*/ + {0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x11,0x04,0x0E,0x88,0x00,0x70,0x00,0x00},/*"B",34*/ + {0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x04,0x10,0x08,0x1C,0x10,0x00,0x00},/*"C",35*/ + {0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"D",36*/ + {0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x17,0xC4,0x10,0x04,0x08,0x18,0x00,0x00},/*"E",37*/ + {0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x17,0xC0,0x10,0x00,0x08,0x00,0x00,0x00},/*"F",38*/ + {0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x44,0x1C,0x78,0x00,0x40,0x00,0x00},/*"G",39*/ + {0x10,0x04,0x1F,0xFC,0x10,0x84,0x00,0x80,0x00,0x80,0x10,0x84,0x1F,0xFC,0x10,0x04},/*"H",40*/ + {0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x00,0x00,0x00,0x00},/*"I",41*/ + {0x00,0x03,0x00,0x01,0x10,0x01,0x10,0x01,0x1F,0xFE,0x10,0x00,0x10,0x00,0x00,0x00},/*"J",42*/ + {0x10,0x04,0x1F,0xFC,0x11,0x04,0x03,0x80,0x14,0x64,0x18,0x1C,0x10,0x04,0x00,0x00},/*"K",43*/ + {0x10,0x04,0x1F,0xFC,0x10,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x0C,0x00,0x00},/*"L",44*/ + {0x10,0x04,0x1F,0xFC,0x1F,0x00,0x00,0xFC,0x1F,0x00,0x1F,0xFC,0x10,0x04,0x00,0x00},/*"M",45*/ + {0x10,0x04,0x1F,0xFC,0x0C,0x04,0x03,0x00,0x00,0xE0,0x10,0x18,0x1F,0xFC,0x10,0x00},/*"N",46*/ + {0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"O",47*/ + {0x10,0x04,0x1F,0xFC,0x10,0x84,0x10,0x80,0x10,0x80,0x10,0x80,0x0F,0x00,0x00,0x00},/*"P",48*/ + {0x07,0xF0,0x08,0x18,0x10,0x24,0x10,0x24,0x10,0x1C,0x08,0x0A,0x07,0xF2,0x00,0x00},/*"Q",49*/ + {0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x11,0xC0,0x11,0x30,0x0E,0x0C,0x00,0x04},/*"R",50*/ + {0x00,0x00,0x0E,0x1C,0x11,0x04,0x10,0x84,0x10,0x84,0x10,0x44,0x1C,0x38,0x00,0x00},/*"S",51*/ + {0x18,0x00,0x10,0x00,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x00,0x18,0x00,0x00,0x00},/*"T",52*/ + {0x10,0x00,0x1F,0xF8,0x10,0x04,0x00,0x04,0x00,0x04,0x10,0x04,0x1F,0xF8,0x10,0x00},/*"U",53*/ + {0x10,0x00,0x1E,0x00,0x11,0xE0,0x00,0x1C,0x00,0x70,0x13,0x80,0x1C,0x00,0x10,0x00},/*"V",54*/ + {0x1F,0xC0,0x10,0x3C,0x00,0xE0,0x1F,0x00,0x00,0xE0,0x10,0x3C,0x1F,0xC0,0x00,0x00},/*"W",55*/ + {0x10,0x04,0x18,0x0C,0x16,0x34,0x01,0xC0,0x01,0xC0,0x16,0x34,0x18,0x0C,0x10,0x04},/*"X",56*/ + {0x10,0x00,0x1C,0x00,0x13,0x04,0x00,0xFC,0x13,0x04,0x1C,0x00,0x10,0x00,0x00,0x00},/*"Y",57*/ + {0x08,0x04,0x10,0x1C,0x10,0x64,0x10,0x84,0x13,0x04,0x1C,0x04,0x10,0x18,0x00,0x00},/*"Z",58*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x40,0x02,0x40,0x02,0x40,0x02,0x00,0x00},/*"[",59*/ + {0x00,0x00,0x30,0x00,0x0C,0x00,0x03,0x80,0x00,0x60,0x00,0x1C,0x00,0x03,0x00,0x00},/*"\",60*/ + {0x00,0x00,0x40,0x02,0x40,0x02,0x40,0x02,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00},/*"]",61*/ + {0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00},/*"^",62*/ + {0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01},/*"_",63*/ + {0x00,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/ + {0x00,0x00,0x00,0x98,0x01,0x24,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xFC,0x00,0x04},/*"a",65*/ + {0x10,0x00,0x1F,0xFC,0x00,0x88,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*"b",66*/ + {0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x00},/*"c",67*/ + {0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x11,0x08,0x1F,0xFC,0x00,0x04},/*"d",68*/ + {0x00,0x00,0x00,0xF8,0x01,0x44,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xC8,0x00,0x00},/*"e",69*/ + {0x00,0x00,0x01,0x04,0x01,0x04,0x0F,0xFC,0x11,0x04,0x11,0x04,0x11,0x00,0x18,0x00},/*"f",70*/ + {0x00,0x00,0x00,0xD6,0x01,0x29,0x01,0x29,0x01,0x29,0x01,0xC9,0x01,0x06,0x00,0x00},/*"g",71*/ + {0x10,0x04,0x1F,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*"h",72*/ + {0x00,0x00,0x01,0x04,0x19,0x04,0x19,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"i",73*/ + {0x00,0x00,0x00,0x03,0x00,0x01,0x01,0x01,0x19,0x01,0x19,0xFE,0x00,0x00,0x00,0x00},/*"j",74*/ + {0x10,0x04,0x1F,0xFC,0x00,0x24,0x00,0x40,0x01,0xB4,0x01,0x0C,0x01,0x04,0x00,0x00},/*"k",75*/ + {0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"l",76*/ + {0x01,0x04,0x01,0xFC,0x01,0x04,0x01,0x00,0x01,0xFC,0x01,0x04,0x01,0x00,0x00,0xFC},/*"m",77*/ + {0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*"n",78*/ + {0x00,0x00,0x00,0xF8,0x01,0x04,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0xF8,0x00,0x00},/*"o",79*/ + {0x01,0x01,0x01,0xFF,0x00,0x85,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*"p",80*/ + {0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x05,0x01,0xFF,0x00,0x01},/*"q",81*/ + {0x01,0x04,0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x04,0x01,0x00,0x01,0x80,0x00,0x00},/*"r",82*/ + {0x00,0x00,0x00,0xCC,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x98,0x00,0x00},/*"s",83*/ + {0x00,0x00,0x01,0x00,0x01,0x00,0x07,0xF8,0x01,0x04,0x01,0x04,0x00,0x00,0x00,0x00},/*"t",84*/ + {0x01,0x00,0x01,0xF8,0x00,0x04,0x00,0x04,0x00,0x04,0x01,0x08,0x01,0xFC,0x00,0x04},/*"u",85*/ + {0x01,0x00,0x01,0x80,0x01,0x70,0x00,0x0C,0x00,0x10,0x01,0x60,0x01,0x80,0x01,0x00},/*"v",86*/ + {0x01,0xF0,0x01,0x0C,0x00,0x30,0x01,0xC0,0x00,0x30,0x01,0x0C,0x01,0xF0,0x01,0x00},/*"w",87*/ + {0x00,0x00,0x01,0x04,0x01,0x8C,0x00,0x74,0x01,0x70,0x01,0x8C,0x01,0x04,0x00,0x00},/*"x",88*/ + {0x01,0x01,0x01,0x81,0x01,0x71,0x00,0x0E,0x00,0x18,0x01,0x60,0x01,0x80,0x01,0x00},/*"y",89*/ + {0x00,0x00,0x01,0x84,0x01,0x0C,0x01,0x34,0x01,0x44,0x01,0x84,0x01,0x0C,0x00,0x00},/*"z",90*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x3E,0xFC,0x40,0x02,0x40,0x02},/*"{",91*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/ + {0x00,0x00,0x40,0x02,0x40,0x02,0x3E,0xFC,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ + {0x00,0x00,0x60,0x00,0x80,0x00,0x80,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x20,0x00},/*"~",94*/ +}; + +//24*24 ASICII +const unsigned char _k_ascii_2412_tbl[95][36] = { + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x80,0x38,0x0F,0xFE,0x38,0x0F,0x80,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x06,0x00,0x00,0x0C,0x00,0x00,0x38,0x00,0x00,0x31,0x00,0x00,0x06,0x00,0x00,0x0C,0x00,0x00,0x38,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00},/*""",2*/ + {0x00,0x00,0x00,0x00,0x61,0x80,0x00,0x67,0xF8,0x07,0xF9,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x67,0xF8,0x07,0xF9,0x80,0x00,0x61,0x80,0x00,0x00,0x00},/*"#",3*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,0xE0,0x03,0xE0,0xF0,0x06,0x30,0x08,0x04,0x18,0x08,0x1F,0xFF,0xFE,0x04,0x0E,0x08,0x07,0x87,0xF0,0x03,0x81,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*"$",4*/ + {0x01,0xF0,0x00,0x06,0x0C,0x00,0x04,0x04,0x08,0x06,0x0C,0x70,0x01,0xF9,0xC0,0x00,0x0E,0x00,0x00,0x3B,0xE0,0x00,0xEC,0x18,0x07,0x08,0x08,0x04,0x0C,0x18,0x00,0x03,0xE0,0x00,0x00,0x00},/*"%",5*/ + {0x00,0x01,0xE0,0x00,0x07,0xF0,0x03,0xF8,0x18,0x04,0x1C,0x08,0x04,0x17,0x08,0x07,0xE1,0xD0,0x03,0xC0,0xE0,0x00,0x23,0xB0,0x00,0x3C,0x08,0x00,0x20,0x08,0x00,0x00,0x10,0x00,0x00,0x00},/*"&",6*/ + {0x00,0x00,0x00,0x01,0x00,0x00,0x31,0x00,0x00,0x32,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x01,0xFF,0xC0,0x07,0x80,0xF0,0x0C,0x00,0x18,0x10,0x00,0x04,0x20,0x00,0x02,0x00,0x00,0x00},/*"(",8*/ + {0x00,0x00,0x00,0x20,0x00,0x02,0x10,0x00,0x04,0x0C,0x00,0x18,0x07,0x80,0xF0,0x01,0xFF,0xC0,0x00,0x7F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/ + {0x00,0x00,0x00,0x00,0x42,0x00,0x00,0x66,0x00,0x00,0x66,0x00,0x00,0x3C,0x00,0x00,0x18,0x00,0x03,0xFF,0xC0,0x00,0x18,0x00,0x00,0x3C,0x00,0x00,0x66,0x00,0x00,0x66,0x00,0x00,0x42,0x00},/*"*",10*/ + {0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x01,0xFF,0xC0,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00},/*"+",11*/ + {0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x31,0x00,0x00,0x32,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/ + {0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00},/*"-",13*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x00,0x00,0x38,0x00,0x00,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/ + {0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x1C,0x00,0x00,0x70,0x00,0x01,0x80,0x00,0x0E,0x00,0x00,0x38,0x00,0x00,0xC0,0x00,0x07,0x00,0x00,0x1C,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00},/*"/",15*/ + {0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x03,0x80,0x70,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"0",16*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x08,0x01,0x00,0x08,0x01,0x00,0x08,0x03,0xFF,0xF8,0x07,0xFF,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"1",17*/ + {0x00,0x00,0x00,0x01,0xC0,0x38,0x02,0xC0,0x58,0x04,0x00,0x98,0x04,0x01,0x18,0x04,0x02,0x18,0x04,0x04,0x18,0x06,0x1C,0x18,0x03,0xF8,0x18,0x01,0xE0,0xF8,0x00,0x00,0x00,0x00,0x00,0x00},/*"2",18*/ + {0x00,0x00,0x00,0x01,0xC0,0xE0,0x03,0xC0,0xF0,0x04,0x00,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x06,0x18,0x08,0x03,0xF4,0x18,0x01,0xE7,0xF0,0x00,0x01,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*"3",19*/ + {0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x0D,0x00,0x00,0x11,0x00,0x00,0x61,0x00,0x00,0x81,0x08,0x03,0x01,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x01,0x08,0x00,0x01,0x08,0x00,0x00,0x00},/*"4",20*/ + {0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0xFC,0xD0,0x06,0x08,0x08,0x06,0x10,0x08,0x06,0x10,0x08,0x06,0x10,0x08,0x06,0x18,0x38,0x06,0x0F,0xF0,0x06,0x07,0xC0,0x00,0x00,0x00,0x00,0x00,0x00},/*"5",21*/ + {0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x84,0x30,0x02,0x08,0x18,0x04,0x10,0x08,0x04,0x10,0x08,0x04,0x10,0x08,0x07,0x18,0x10,0x03,0x0F,0xF0,0x00,0x07,0xC0,0x00,0x00,0x00},/*"6",22*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xC0,0x00,0x07,0x00,0x00,0x06,0x00,0x00,0x06,0x00,0xF8,0x06,0x07,0xF8,0x06,0x18,0x00,0x06,0xE0,0x00,0x07,0x00,0x00,0x06,0x00,0x00,0x00,0x00,0x00},/*"7",23*/ + {0x00,0x00,0x00,0x01,0xE1,0xE0,0x03,0xF7,0xF0,0x06,0x34,0x10,0x04,0x18,0x08,0x04,0x18,0x08,0x04,0x0C,0x08,0x04,0x0C,0x08,0x06,0x16,0x18,0x03,0xF3,0xF0,0x01,0xC1,0xE0,0x00,0x00,0x00},/*"8",24*/ + {0x00,0x00,0x00,0x00,0xF8,0x00,0x03,0xFC,0x30,0x03,0x06,0x38,0x04,0x02,0x08,0x04,0x02,0x08,0x04,0x02,0x08,0x04,0x04,0x10,0x03,0x08,0xF0,0x01,0xFF,0xC0,0x00,0x7F,0x00,0x00,0x00,0x00},/*"9",25*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x38,0x00,0x70,0x38,0x00,0x70,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x1A,0x00,0x30,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x14,0x00,0x00,0x22,0x00,0x00,0x41,0x00,0x00,0x80,0x80,0x01,0x00,0x40,0x02,0x00,0x20,0x04,0x00,0x10,0x08,0x00,0x08,0x00,0x00,0x00},/*"<",28*/ + {0x00,0x00,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x00,0x00},/*"=",29*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x08,0x04,0x00,0x10,0x02,0x00,0x20,0x01,0x00,0x40,0x00,0x80,0x80,0x00,0x41,0x00,0x00,0x22,0x00,0x00,0x14,0x00,0x00,0x08,0x00,0x00,0x00,0x00},/*">",30*/ + {0x00,0x00,0x00,0x03,0xC0,0x00,0x04,0xC0,0x00,0x04,0x00,0x00,0x08,0x00,0x38,0x08,0x0F,0x38,0x08,0x08,0x38,0x08,0x10,0x00,0x0C,0x30,0x00,0x07,0xE0,0x00,0x03,0xC0,0x00,0x00,0x00,0x00},/*"?",31*/ + {0x00,0x00,0x00,0x00,0x3F,0x80,0x00,0xFF,0xE0,0x03,0x80,0x70,0x02,0x0F,0x10,0x06,0x70,0x88,0x04,0xC0,0x88,0x04,0x83,0x08,0x04,0x7F,0x88,0x02,0xC0,0x90,0x03,0x01,0x20,0x00,0xFE,0x40},/*"@",32*/ + {0x00,0x00,0x08,0x00,0x00,0x18,0x00,0x01,0xF8,0x00,0x3E,0x08,0x01,0xC2,0x00,0x07,0x02,0x00,0x07,0xE2,0x00,0x00,0xFE,0x00,0x00,0x1F,0xC8,0x00,0x01,0xF8,0x00,0x00,0x38,0x00,0x00,0x08},/*"A",33*/ + {0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x06,0x18,0x08,0x03,0xF4,0x18,0x01,0xE7,0xF0,0x00,0x01,0xE0,0x00,0x00,0x00},/*"B",34*/ + {0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x02,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x10,0x06,0x00,0x20,0x07,0x80,0xC0,0x00,0x00,0x00},/*"C",35*/ + {0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x18,0x02,0x00,0x10,0x03,0x80,0x70,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"D",36*/ + {0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x3E,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x01,0x00,0x60,0x00,0x00,0x00},/*"E",37*/ + {0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x00,0x04,0x08,0x00,0x04,0x08,0x00,0x04,0x3E,0x00,0x06,0x00,0x00,0x06,0x00,0x00,0x01,0x80,0x00,0x00,0x00,0x00},/*"F",38*/ + {0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x02,0x08,0x04,0x02,0x08,0x02,0x03,0xF0,0x07,0x83,0xF0,0x00,0x02,0x00,0x00,0x02,0x00},/*"G",39*/ + {0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x04,0x08,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08},/*"H",40*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"I",41*/ + {0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x07,0x00,0x00,0x01,0x04,0x00,0x01,0x04,0x00,0x01,0x04,0x00,0x03,0x07,0xFF,0xFE,0x07,0xFF,0xFC,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00},/*"J",42*/ + {0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x0C,0x08,0x00,0x18,0x00,0x00,0x3E,0x00,0x04,0xC7,0x80,0x05,0x03,0xC8,0x06,0x00,0xF8,0x04,0x00,0x38,0x04,0x00,0x18,0x00,0x00,0x08},/*"K",43*/ + {0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x18,0x00,0x00,0x60,0x00,0x00,0x00},/*"L",44*/ + {0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0x80,0x08,0x07,0xFC,0x00,0x00,0x7F,0xC0,0x00,0x03,0xF8,0x00,0x07,0xC0,0x00,0x78,0x00,0x07,0x80,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08},/*"M",45*/ + {0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0x00,0x08,0x03,0xC0,0x00,0x00,0xE0,0x00,0x00,0x38,0x00,0x00,0x1E,0x00,0x00,0x07,0x00,0x00,0x01,0xC0,0x04,0x00,0xF0,0x07,0xFF,0xF8,0x04,0x00,0x00},/*"N",46*/ + {0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x03,0x00,0x30,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"O",47*/ + {0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x04,0x08,0x04,0x04,0x00,0x04,0x04,0x00,0x04,0x04,0x00,0x04,0x04,0x00,0x06,0x0C,0x00,0x03,0xF8,0x00,0x01,0xF0,0x00,0x00,0x00,0x00},/*"P",48*/ + {0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x88,0x04,0x00,0x88,0x04,0x00,0xC8,0x06,0x00,0x3C,0x03,0x00,0x3E,0x01,0xFF,0xE6,0x00,0x7F,0x84,0x00,0x00,0x00},/*"Q",49*/ + {0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x00,0x04,0x0C,0x00,0x04,0x0F,0x00,0x04,0x0B,0xC0,0x06,0x10,0xF0,0x03,0xF0,0x38,0x01,0xE0,0x08,0x00,0x00,0x08},/*"R",50*/ + {0x00,0x00,0x00,0x01,0xE0,0xF8,0x03,0xF0,0x30,0x06,0x30,0x10,0x04,0x18,0x08,0x04,0x18,0x08,0x04,0x0C,0x08,0x04,0x0C,0x08,0x02,0x06,0x18,0x02,0x07,0xF0,0x07,0x81,0xE0,0x00,0x00,0x00},/*"S",51*/ + {0x01,0x80,0x00,0x06,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x00,0x04,0x00,0x00,0x06,0x00,0x00,0x01,0x80,0x00},/*"T",52*/ + {0x04,0x00,0x00,0x07,0xFF,0xE0,0x07,0xFF,0xF0,0x04,0x00,0x18,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x04,0x00,0x10,0x07,0xFF,0xE0,0x04,0x00,0x00},/*"U",53*/ + {0x04,0x00,0x00,0x06,0x00,0x00,0x07,0xE0,0x00,0x07,0xFE,0x00,0x04,0x1F,0xE0,0x00,0x01,0xF8,0x00,0x00,0x38,0x00,0x01,0xE0,0x04,0x3E,0x00,0x07,0xC0,0x00,0x06,0x00,0x00,0x04,0x00,0x00},/*"V",54*/ + {0x04,0x00,0x00,0x07,0xE0,0x00,0x07,0xFF,0xC0,0x04,0x1F,0xF8,0x00,0x07,0xC0,0x07,0xF8,0x00,0x07,0xFF,0x80,0x04,0x3F,0xF8,0x00,0x07,0xC0,0x04,0xF8,0x00,0x07,0x00,0x00,0x04,0x00,0x00},/*"W",55*/ + {0x00,0x00,0x00,0x04,0x00,0x08,0x06,0x00,0x18,0x07,0xC0,0x78,0x05,0xF1,0xC8,0x00,0x3E,0x00,0x00,0x1F,0x80,0x04,0x63,0xE8,0x07,0x80,0xF8,0x06,0x00,0x18,0x04,0x00,0x08,0x00,0x00,0x00},/*"X",56*/ + {0x04,0x00,0x00,0x06,0x00,0x00,0x07,0x80,0x00,0x07,0xE0,0x08,0x04,0x7C,0x08,0x00,0x1F,0xF8,0x00,0x07,0xF8,0x00,0x18,0x08,0x04,0xE0,0x08,0x07,0x00,0x00,0x06,0x00,0x00,0x04,0x00,0x00},/*"Y",57*/ + {0x00,0x00,0x00,0x01,0x00,0x08,0x06,0x00,0x38,0x04,0x00,0xF8,0x04,0x03,0xE8,0x04,0x0F,0x08,0x04,0x7C,0x08,0x05,0xF0,0x08,0x07,0xC0,0x08,0x07,0x00,0x18,0x04,0x00,0x60,0x00,0x00,0x00},/*"Z",58*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFE,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x00,0x00,0x00},/*"[",59*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x07,0x00,0x00,0x00,0xC0,0x00,0x00,0x38,0x00,0x00,0x06,0x00,0x00,0x01,0xC0,0x00,0x00,0x30,0x00,0x00,0x0E,0x00,0x00,0x01,0x00,0x00,0x00},/*"\",60*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x3F,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"]",61*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x10,0x00,0x00,0x30,0x00,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x10,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"^",62*/ + {0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01},/*"_",63*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x10,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/ + {0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x19,0xF8,0x00,0x1B,0x18,0x00,0x22,0x08,0x00,0x26,0x08,0x00,0x24,0x08,0x00,0x24,0x10,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x18},/*"a",65*/ + {0x00,0x00,0x00,0x04,0x00,0x00,0x07,0xFF,0xF8,0x0F,0xFF,0xF0,0x00,0x18,0x18,0x00,0x10,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x18,0x00,0x1F,0xF0,0x00,0x0F,0xC0,0x00,0x00,0x00},/*"b",66*/ + {0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x18,0x30,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x3C,0x08,0x00,0x1C,0x10,0x00,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00},/*"c",67*/ + {0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x38,0x18,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x04,0x10,0x10,0x07,0xFF,0xF8,0x0F,0xFF,0xF0,0x00,0x00,0x10,0x00,0x00,0x00},/*"d",68*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x12,0x30,0x00,0x22,0x18,0x00,0x22,0x08,0x00,0x22,0x08,0x00,0x32,0x08,0x00,0x1E,0x10,0x00,0x0E,0x20,0x00,0x00,0x00},/*"e",69*/ + {0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x01,0xFF,0xF8,0x03,0xFF,0xF8,0x06,0x20,0x08,0x04,0x20,0x08,0x04,0x20,0x08,0x07,0x20,0x00,0x03,0x00,0x00,0x00,0x00,0x00},/*"f",70*/ + {0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x0E,0x6E,0x00,0x1F,0xF3,0x00,0x31,0xB1,0x00,0x20,0xB1,0x00,0x20,0xB1,0x00,0x31,0x91,0x00,0x1F,0x13,0x00,0x2E,0x1E,0x00,0x20,0x0E,0x00,0x30,0x00},/*"g",71*/ + {0x00,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x00},/*"h",72*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x06,0x3F,0xF8,0x06,0x3F,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"i",73*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x03,0x00,0x20,0x01,0x00,0x20,0x01,0x00,0x20,0x03,0x06,0x3F,0xFE,0x06,0x3F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"j",74*/ + {0x00,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x01,0x88,0x00,0x03,0x00,0x00,0x2F,0xC0,0x00,0x38,0xF8,0x00,0x20,0x38,0x00,0x20,0x08,0x00,0x00,0x08,0x00,0x00,0x00},/*"k",75*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"l",76*/ + {0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x00,0x08},/*"m",77*/ + {0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x10,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x00},/*"n",78*/ + {0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x0F,0xF0,0x00,0x18,0x30,0x00,0x30,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x08,0x00,0x18,0x30,0x00,0x0F,0xF0,0x00,0x07,0xC0,0x00,0x00,0x00},/*"o",79*/ + {0x00,0x00,0x00,0x00,0x20,0x01,0x00,0x3F,0xFF,0x00,0x3F,0xFF,0x00,0x10,0x11,0x00,0x20,0x09,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x38,0x00,0x1F,0xF0,0x00,0x0F,0xC0,0x00,0x00,0x00},/*"p",80*/ + {0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x38,0x18,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x09,0x00,0x10,0x11,0x00,0x1F,0xFF,0x00,0x3F,0xFF,0x00,0x00,0x01,0x00,0x00,0x00},/*"q",81*/ + {0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x08,0x08,0x00,0x10,0x08,0x00,0x20,0x08,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x30,0x00,0x00,0x00,0x00},/*"r",82*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x78,0x00,0x1E,0x18,0x00,0x33,0x08,0x00,0x23,0x08,0x00,0x21,0x08,0x00,0x21,0x88,0x00,0x21,0x98,0x00,0x30,0xF0,0x00,0x38,0x60,0x00,0x00,0x00},/*"s",83*/ + {0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0xFF,0xF0,0x03,0xFF,0xF8,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00,0x00},/*"t",84*/ + {0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x3F,0xF0,0x00,0x7F,0xF8,0x00,0x00,0x18,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x20,0x10,0x00,0x3F,0xF8,0x00,0x7F,0xF0,0x00,0x00,0x10,0x00,0x00,0x00},/*"u",85*/ + {0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x3C,0x00,0x00,0x3F,0x80,0x00,0x23,0xF0,0x00,0x00,0x78,0x00,0x00,0x70,0x00,0x23,0x80,0x00,0x3C,0x00,0x00,0x30,0x00,0x00,0x20,0x00},/*"v",86*/ + {0x00,0x20,0x00,0x00,0x3C,0x00,0x00,0x3F,0xE0,0x00,0x23,0xF8,0x00,0x00,0xE0,0x00,0x27,0x00,0x00,0x3E,0x00,0x00,0x3F,0xE0,0x00,0x21,0xF8,0x00,0x01,0xE0,0x00,0x3E,0x00,0x00,0x20,0x00},/*"w",87*/ + {0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x38,0x38,0x00,0x3E,0x68,0x00,0x27,0x80,0x00,0x03,0xC8,0x00,0x2C,0xF8,0x00,0x38,0x38,0x00,0x20,0x18,0x00,0x20,0x08,0x00,0x00,0x00},/*"x",88*/ + {0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x30,0x03,0x00,0x3C,0x01,0x00,0x3F,0x83,0x00,0x23,0xEC,0x00,0x00,0x70,0x00,0x23,0x80,0x00,0x3C,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"y",89*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x08,0x00,0x20,0x38,0x00,0x20,0xF8,0x00,0x23,0xE8,0x00,0x2F,0x88,0x00,0x3E,0x08,0x00,0x38,0x08,0x00,0x20,0x18,0x00,0x00,0x70,0x00,0x00,0x00},/*"z",90*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x14,0x00,0x1F,0xF7,0xFC,0x30,0x00,0x06,0x20,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00},/*"{",91*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x02,0x30,0x00,0x06,0x1F,0xF7,0xFC,0x00,0x14,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ + {0x00,0x00,0x00,0x18,0x00,0x00,0x60,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0x00,0x10,0x00,0x00,0x08,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x0C,0x00,0x00,0x10,0x00,0x00},/*"~",94*/ +}; + +//32*32 ASCII +const unsigned char _k_ascii_3216_tbl[95][128]={ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF0,0x00,0xC0,0x07,0xFF,0xE1,0xE0,0x07,0xF0,0x01,0xE0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x01,0xC0,0x00,0x00,0x07,0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x1C,0x20,0x00,0x00,0x01,0xC0,0x00,0x00,0x07,0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*""",2*/ + {0x00,0x00,0x00,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0F,0xE0,0x00,0x1F,0xFC,0x00,0x03,0xF8,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0F,0xE0,0x00,0x1F,0xFC,0x00,0x03,0xF8,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x00,0x00,0x00},/*"#",3*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x00,0x78,0x07,0xC0,0x00,0xFC,0x06,0x40,0x01,0x0E,0x00,0x20,0x03,0x07,0x00,0x20,0x02,0x03,0x80,0x20,0x0F,0xFF,0xFF,0xFC,0x02,0x01,0xC0,0x20,0x02,0x00,0xE0,0x60,0x01,0x30,0x70,0x40,0x01,0xF0,0x3F,0x80,0x00,0xF0,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"$",4*/ + {0x00,0xFE,0x00,0x00,0x01,0xFF,0x00,0x00,0x03,0x01,0x80,0x00,0x02,0x00,0x80,0x60,0x03,0x01,0x81,0xC0,0x01,0xFF,0x07,0x00,0x00,0xFE,0x18,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0xBF,0x00,0x00,0x0C,0xFF,0xC0,0x00,0x71,0x80,0x60,0x01,0xC1,0x00,0x20,0x03,0x01,0x80,0x60,0x00,0x00,0xFF,0xC0,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00},/*"%",5*/ + {0x00,0x00,0x1F,0x00,0x00,0x00,0x7F,0xC0,0x00,0xFC,0xC0,0xC0,0x01,0xFF,0x80,0x60,0x03,0x03,0xE0,0x20,0x02,0x02,0x78,0x20,0x02,0x06,0x1E,0x20,0x03,0xFC,0x07,0x40,0x01,0xF0,0x03,0x80,0x00,0x01,0x03,0xC0,0x00,0x01,0x1C,0x60,0x00,0x01,0xE0,0x20,0x00,0x01,0x00,0x20,0x00,0x01,0x00,0x40,0x00,0x00,0x01,0x80,0x00,0x00,0x00,0x00},/*"&",6*/ + {0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x1C,0x60,0x00,0x00,0x1C,0x40,0x00,0x00,0x1F,0x80,0x00,0x00,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF8,0x00,0x00,0x3F,0xFF,0x00,0x00,0x78,0x07,0xC0,0x01,0xC0,0x00,0xE0,0x03,0x00,0x00,0x30,0x04,0x00,0x00,0x08,0x08,0x00,0x00,0x04,0x10,0x00,0x00,0x02,0x00,0x00,0x00,0x00},/*"(",8*/ + {0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x02,0x08,0x00,0x00,0x04,0x04,0x00,0x00,0x08,0x03,0x00,0x00,0x30,0x01,0xC0,0x00,0xE0,0x00,0x78,0x07,0xC0,0x00,0x3F,0xFF,0x00,0x00,0x07,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x18,0x00,0x00,0x0E,0x38,0x00,0x00,0x0E,0x38,0x00,0x00,0x06,0x30,0x00,0x00,0x03,0x60,0x00,0x00,0x61,0x43,0x80,0x00,0xFF,0xFF,0x80,0x00,0x61,0x43,0x00,0x00,0x03,0x60,0x00,0x00,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x0E,0x38,0x00,0x00,0x0C,0x18,0x00,0x00,0x00,0x00,0x00},/*"*",10*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x7F,0xFF,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00},/*"+",11*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0xE3,0x00,0x00,0x00,0xE2,0x00,0x00,0x00,0xFC,0x00,0x00,0x00,0x78,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00},/*"-",13*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x00,0x00,0x01,0xE0,0x00,0x00,0x01,0xE0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x0E,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x0E,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x0E,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"/",15*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x7F,0xFF,0x00,0x00,0xF0,0x07,0x80,0x01,0x80,0x00,0xC0,0x03,0x00,0x00,0x60,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0x00,0x00,0x60,0x01,0x80,0x00,0xC0,0x00,0xE0,0x03,0x80,0x00,0x7F,0xFF,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x00,0x00},/*"0",16*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x20,0x00,0x80,0x00,0x20,0x00,0x80,0x00,0x20,0x00,0x80,0x00,0x60,0x01,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"1",17*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x00,0xE0,0x00,0x98,0x01,0x60,0x01,0x00,0x02,0x60,0x02,0x00,0x04,0x60,0x02,0x00,0x08,0x60,0x02,0x00,0x10,0x60,0x02,0x00,0x20,0x60,0x02,0x00,0x40,0x60,0x03,0x00,0x80,0x60,0x01,0x83,0x00,0x60,0x01,0xFE,0x00,0xE0,0x00,0x7C,0x07,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"2",18*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x80,0x01,0xF0,0x07,0xC0,0x01,0x00,0x00,0x40,0x02,0x00,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x03,0x03,0x80,0x20,0x01,0x86,0x80,0x40,0x01,0xFC,0xC0,0xC0,0x00,0x78,0x7F,0x80,0x00,0x00,0x1E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"3",19*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x48,0x00,0x00,0x01,0x88,0x00,0x00,0x06,0x08,0x00,0x00,0x0C,0x08,0x10,0x00,0x30,0x08,0x10,0x00,0x40,0x08,0x10,0x01,0xFF,0xFF,0xF0,0x03,0xFF,0xFF,0xF0,0x03,0xFF,0xFF,0xF0,0x00,0x00,0x08,0x10,0x00,0x00,0x08,0x10,0x00,0x00,0x08,0x10,0x00,0x00,0x00,0x00},/*"4",20*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x00,0x1F,0x86,0x40,0x03,0xE1,0x00,0x20,0x03,0x02,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x06,0x00,0x40,0x03,0x03,0x01,0xC0,0x03,0x01,0xFF,0x80,0x03,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"5",21*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFC,0x00,0x00,0x3F,0xFF,0x00,0x00,0x70,0xC3,0x80,0x00,0x81,0x80,0xC0,0x01,0x01,0x00,0x60,0x03,0x02,0x00,0x20,0x02,0x02,0x00,0x20,0x02,0x02,0x00,0x20,0x02,0x02,0x00,0x20,0x02,0x03,0x00,0x40,0x01,0xC1,0x80,0xC0,0x00,0xC0,0xFF,0x80,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00},/*"6",22*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x00,0x03,0xC0,0x00,0x00,0x03,0x80,0x00,0x00,0x03,0x00,0x00,0x00,0x03,0x00,0x07,0xE0,0x03,0x00,0x3F,0xE0,0x03,0x01,0xC0,0x00,0x03,0x06,0x00,0x00,0x03,0x18,0x00,0x00,0x03,0x60,0x00,0x00,0x03,0x80,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"7",23*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x00,0x00,0x78,0x3F,0x80,0x00,0xFC,0x60,0xC0,0x01,0x8E,0xC0,0x40,0x03,0x07,0x80,0x20,0x02,0x03,0x00,0x20,0x02,0x01,0x80,0x20,0x02,0x01,0x80,0x20,0x02,0x01,0xC0,0x20,0x03,0x01,0xE0,0x40,0x01,0x86,0x70,0xC0,0x00,0xFC,0x3F,0x80,0x00,0x78,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"8",24*/ + {0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0xFF,0x81,0xC0,0x01,0xC0,0xC1,0xC0,0x01,0x00,0x60,0x20,0x02,0x00,0x20,0x20,0x02,0x00,0x20,0x20,0x02,0x00,0x20,0x20,0x02,0x00,0x20,0x60,0x02,0x00,0x40,0xC0,0x01,0x00,0xC1,0x80,0x00,0xC1,0x8F,0x00,0x00,0x7F,0xFE,0x00,0x00,0x1F,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"9",25*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0xC0,0x00,0x07,0x81,0xE0,0x00,0x07,0x81,0xE0,0x00,0x03,0x00,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x66,0x00,0x06,0x00,0x78,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x01,0xC0,0x00,0x00,0x03,0x60,0x00,0x00,0x06,0x30,0x00,0x00,0x0C,0x18,0x00,0x00,0x18,0x0C,0x00,0x00,0x30,0x06,0x00,0x00,0x60,0x03,0x00,0x00,0xC0,0x01,0x80,0x01,0x00,0x00,0x40,0x02,0x00,0x00,0x20,0x04,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"<",28*/ + {0x00,0x00,0x00,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x00,0x00,0x00},/*"=",29*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x10,0x02,0x00,0x00,0x20,0x01,0x00,0x00,0x40,0x00,0xC0,0x01,0x80,0x00,0x60,0x03,0x00,0x00,0x30,0x06,0x00,0x00,0x18,0x0C,0x00,0x00,0x0C,0x18,0x00,0x00,0x06,0x30,0x00,0x00,0x03,0x60,0x00,0x00,0x01,0xC0,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*">",30*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x00,0x00,0x01,0xF8,0x00,0x00,0x02,0x38,0x00,0x00,0x02,0x00,0x00,0x00,0x04,0x00,0x00,0xC0,0x04,0x00,0x79,0xE0,0x04,0x00,0x81,0xE0,0x04,0x01,0x00,0xC0,0x04,0x03,0x00,0x00,0x02,0x02,0x00,0x00,0x03,0x06,0x00,0x00,0x01,0xFC,0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,0x00,0x00},/*"?",31*/ + {0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0x70,0x07,0x80,0x00,0xC0,0x00,0xC0,0x01,0x01,0xF8,0x40,0x03,0x07,0xFC,0x20,0x02,0x1E,0x04,0x20,0x02,0x30,0x08,0x20,0x02,0x20,0x30,0x20,0x02,0x3F,0xFC,0x20,0x01,0x3F,0x04,0x40,0x01,0x80,0x0C,0xC0,0x00,0xE0,0x31,0x80,0x00,0x1F,0xC2,0x00,0x00,0x00,0x00,0x00},/*"@",32*/ + {0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x60,0x00,0x00,0x03,0xE0,0x00,0x00,0x3E,0x20,0x00,0x03,0xE0,0x20,0x00,0x3E,0x20,0x00,0x03,0xE0,0x20,0x00,0x03,0x80,0x20,0x00,0x07,0xFC,0x20,0x00,0x00,0x3F,0xE0,0x00,0x00,0x03,0xFE,0x20,0x00,0x00,0x3F,0xE0,0x00,0x00,0x01,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"A",33*/ + {0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x03,0x03,0x00,0x20,0x01,0x86,0x80,0x60,0x01,0xFC,0xC0,0xC0,0x00,0xF8,0x7F,0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x00,0x00},/*"B",34*/ + {0x00,0x00,0x00,0x00,0x00,0x07,0xF8,0x00,0x00,0x3F,0xFF,0x00,0x00,0x70,0x07,0x80,0x00,0xC0,0x00,0xC0,0x01,0x00,0x00,0x40,0x03,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x01,0x00,0x00,0x40,0x01,0x80,0x00,0xC0,0x03,0xC0,0x01,0x80,0x00,0x30,0x06,0x00,0x00,0x00,0x00,0x00},/*"C",35*/ + {0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0x00,0x00,0x60,0x01,0x00,0x00,0x40,0x01,0x80,0x00,0xC0,0x00,0xF0,0x07,0x80,0x00,0x7F,0xFE,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x00,0x00},/*"D",36*/ + {0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x03,0x80,0x20,0x02,0x0F,0xE0,0x20,0x03,0x00,0x00,0x60,0x03,0xC0,0x00,0xE0,0x00,0x60,0x03,0x00,0x00,0x00,0x00,0x00},/*"E",37*/ + {0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x00,0x02,0x01,0x00,0x00,0x02,0x01,0x00,0x00,0x02,0x01,0x00,0x00,0x02,0x03,0x80,0x00,0x03,0x0F,0xE0,0x00,0x03,0x00,0x00,0x00,0x03,0xC0,0x00,0x00,0x00,0x60,0x00,0x00},/*"F",38*/ + {0x00,0x00,0x00,0x00,0x00,0x07,0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0x70,0x07,0x80,0x01,0xC0,0x01,0xC0,0x01,0x00,0x00,0x40,0x03,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x01,0x00,0x20,0x20,0x01,0x00,0x20,0x40,0x03,0xC0,0x3F,0x80,0x00,0x30,0x3F,0x80,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00},/*"G",39*/ + {0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x80,0x20,0x02,0x00,0x80,0x20,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x02,0x00,0x80,0x20,0x02,0x00,0x80,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"H",40*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"I",41*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x0F,0x00,0x00,0x00,0x0F,0x00,0x00,0x00,0x01,0x02,0x00,0x00,0x01,0x02,0x00,0x00,0x01,0x02,0x00,0x00,0x03,0x02,0x00,0x00,0x06,0x03,0xFF,0xFF,0xFC,0x03,0xFF,0xFF,0xF8,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"J",42*/ + {0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0xC0,0x20,0x02,0x01,0x00,0x20,0x00,0x07,0x80,0x00,0x00,0x0F,0xE0,0x00,0x00,0x30,0xF8,0x00,0x02,0x60,0x3E,0x20,0x03,0x80,0x0F,0x20,0x03,0x00,0x03,0xE0,0x02,0x00,0x00,0xE0,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x20},/*"K",43*/ + {0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00},/*"L",44*/ + {0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xE0,0x00,0x20,0x03,0xFF,0x00,0x20,0x00,0x1F,0xF0,0x00,0x00,0x01,0xFF,0x80,0x00,0x00,0x0F,0xE0,0x00,0x00,0x1E,0x00,0x00,0x03,0xE0,0x00,0x00,0x3E,0x00,0x20,0x03,0xE0,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20},/*"M",45*/ + {0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0x80,0x00,0x20,0x03,0xF0,0x00,0x20,0x00,0xFC,0x00,0x00,0x00,0x1F,0x00,0x00,0x00,0x07,0xC0,0x00,0x00,0x01,0xF0,0x00,0x00,0x00,0x7C,0x00,0x02,0x00,0x1F,0x80,0x02,0x00,0x07,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"N",46*/ + {0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0xF0,0x07,0x80,0x01,0x80,0x00,0xC0,0x01,0x00,0x00,0x40,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x01,0x00,0x00,0x40,0x01,0x80,0x00,0xC0,0x00,0xF0,0x03,0x80,0x00,0x3F,0xFE,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x00,0x00},/*"O",47*/ + {0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x80,0x20,0x02,0x00,0x80,0x20,0x02,0x00,0x80,0x00,0x02,0x00,0x80,0x00,0x02,0x00,0x80,0x00,0x02,0x00,0x80,0x00,0x03,0x01,0x80,0x00,0x01,0x83,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0x7C,0x00,0x00,0x00,0x00,0x00,0x00},/*"P",48*/ + {0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x7F,0xFF,0x00,0x00,0xF0,0x03,0x80,0x01,0x80,0x01,0xC0,0x01,0x00,0x06,0x40,0x02,0x00,0x04,0x20,0x02,0x00,0x04,0x20,0x02,0x00,0x06,0x20,0x02,0x00,0x03,0xE0,0x01,0x00,0x00,0xF8,0x01,0x80,0x00,0x5C,0x00,0xE0,0x03,0x8C,0x00,0x3F,0xFF,0x0C,0x00,0x0F,0xFC,0x18,0x00,0x00,0x00,0x00},/*"Q",49*/ + {0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x80,0x00,0x02,0x01,0xE0,0x00,0x02,0x01,0xFC,0x00,0x03,0x03,0x3F,0x80,0x01,0x86,0x07,0xE0,0x01,0xFC,0x00,0xE0,0x00,0xF8,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"R",50*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x06,0x00,0x00,0xFE,0x01,0xE0,0x01,0x86,0x00,0xC0,0x03,0x03,0x00,0x40,0x02,0x03,0x00,0x20,0x02,0x01,0x80,0x20,0x02,0x01,0x80,0x20,0x02,0x01,0xC0,0x20,0x02,0x00,0xC0,0x20,0x01,0x00,0xE0,0x60,0x01,0x80,0x70,0xC0,0x03,0xE0,0x3F,0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x00,0x00},/*"S",51*/ + {0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x03,0x80,0x00,0x00,0x03,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x80,0x00,0x00,0x00,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*"T",52*/ + {0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0xC0,0x02,0x00,0x00,0x40,0x02,0x00,0x00,0x60,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x02,0x00,0x00,0x40,0x02,0x00,0x00,0x80,0x03,0xFF,0xFF,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"U",53*/ + {0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0xC0,0x00,0x00,0x03,0xFC,0x00,0x00,0x02,0x3F,0xC0,0x00,0x00,0x03,0xF8,0x00,0x00,0x00,0x7F,0x80,0x00,0x00,0x07,0xE0,0x00,0x00,0x07,0x80,0x00,0x00,0x78,0x00,0x02,0x03,0xC0,0x00,0x02,0x3C,0x00,0x00,0x03,0xC0,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00},/*"V",54*/ + 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{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x00,0x01,0x8F,0xC0,0x00,0x03,0x8C,0x60,0x00,0x06,0x18,0x20,0x00,0x04,0x10,0x20,0x00,0x04,0x10,0x20,0x00,0x04,0x20,0x20,0x00,0x04,0x20,0x40,0x00,0x06,0x20,0x40,0x00,0x03,0xFF,0xC0,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00},/*"a",65*/ + {0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xC0,0x00,0x01,0x80,0xC0,0x00,0x02,0x00,0x60,0x00,0x02,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x40,0x00,0x03,0x00,0xC0,0x00,0x01,0xFF,0x80,0x00,0x00,0xFE,0x00,0x00,0x00,0x00,0x00},/*"b",66*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x01,0xFF,0x80,0x00,0x03,0x81,0xC0,0x00,0x02,0x00,0x40,0x00,0x06,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x03,0xC0,0x40,0x00,0x01,0xC0,0x80,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"c",67*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x01,0xFF,0x80,0x00,0x03,0x80,0xC0,0x00,0x06,0x00,0x60,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x02,0x04,0x00,0x40,0x02,0x02,0x00,0x80,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00},/*"d",68*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x01,0xFF,0x80,0x00,0x03,0x11,0xC0,0x00,0x02,0x10,0x40,0x00,0x04,0x10,0x60,0x00,0x04,0x10,0x20,0x00,0x04,0x10,0x20,0x00,0x04,0x10,0x20,0x00,0x06,0x10,0x20,0x00,0x03,0x10,0x40,0x00,0x01,0xF0,0xC0,0x00,0x00,0x71,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"e",69*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x7F,0xFF,0xE0,0x01,0xFF,0xFF,0xE0,0x01,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x02,0x04,0x00,0x20,0x02,0x04,0x00,0x20,0x02,0x04,0x00,0x00,0x02,0x00,0x00,0x00,0x01,0xC0,0x00,0x00,0x01,0xC0,0x00,0x00},/*"f",70*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x00,0xE3,0x3E,0x00,0x03,0xFF,0xC2,0x00,0x02,0x0C,0xC3,0x00,0x04,0x04,0xC1,0x00,0x04,0x04,0xC1,0x00,0x04,0x04,0xC1,0x00,0x04,0x04,0xC1,0x00,0x06,0x0C,0xC1,0x00,0x03,0xF8,0xC3,0x00,0x05,0xF0,0x62,0x00,0x06,0x00,0x7E,0x00,0x06,0x00,0x3C,0x00,0x00,0x00,0x00},/*"g",71*/ + {0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xE0,0x00,0x01,0x00,0x20,0x00,0x02,0x00,0x20,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x03,0xFF,0xE0,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20},/*"h",72*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x03,0x87,0xFF,0xE0,0x03,0x8F,0xFF,0xE0,0x03,0x80,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"i",73*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x03,0x00,0x04,0x00,0x06,0x03,0x87,0xFF,0xFC,0x03,0x8F,0xFF,0xF8,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"j",74*/ + {0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xE0,0x00,0x00,0x08,0x20,0x00,0x00,0x10,0x20,0x00,0x00,0x30,0x00,0x00,0x00,0xFC,0x00,0x00,0x05,0x8E,0x00,0x00,0x07,0x07,0xA0,0x00,0x06,0x01,0xE0,0x00,0x04,0x00,0xE0,0x00,0x04,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"k",75*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"l",76*/ + {0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x0F,0xFF,0xE0,0x00,0x02,0x00,0x20,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x03,0xFF,0xE0,0x00,0x02,0x00,0x20,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"m",77*/ + {0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x0F,0xFF,0xE0,0x00,0x01,0x00,0x20,0x00,0x02,0x00,0x20,0x00,0x02,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x03,0xFF,0xE0,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20},/*"n",78*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0xFF,0x80,0x00,0x03,0x81,0xC0,0x00,0x02,0x00,0x40,0x00,0x06,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x02,0x00,0x40,0x00,0x03,0x81,0xC0,0x00,0x01,0xFF,0x80,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00},/*"o",79*/ + {0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x07,0xFF,0xFF,0x00,0x0F,0xFF,0xFF,0x00,0x01,0x00,0xC1,0x00,0x02,0x00,0x41,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x40,0x00,0x03,0x01,0xC0,0x00,0x01,0xFF,0x80,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00},/*"p",80*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x01,0xFF,0x80,0x00,0x03,0x80,0xC0,0x00,0x02,0x00,0x60,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x02,0x00,0x41,0x00,0x03,0x00,0xC1,0x00,0x03,0xFF,0xFF,0x00,0x07,0xFF,0xFF,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01},/*"q",81*/ + {0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x0F,0xFF,0xE0,0x00,0x0F,0xFF,0xE0,0x00,0x00,0xC0,0x20,0x00,0x01,0x00,0x20,0x00,0x02,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00},/*"r",82*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x00,0x01,0xC0,0xE0,0x00,0x03,0xE0,0x40,0x00,0x06,0x30,0x20,0x00,0x04,0x30,0x20,0x00,0x04,0x18,0x20,0x00,0x04,0x18,0x20,0x00,0x04,0x18,0x20,0x00,0x04,0x0C,0x20,0x00,0x02,0x0C,0x60,0x00,0x03,0x07,0xC0,0x00,0x07,0x83,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"s",83*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x1F,0xFF,0x80,0x00,0xFF,0xFF,0xC0,0x00,0x04,0x00,0x60,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x40,0x00,0x00,0x01,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"t",84*/ + {0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x04,0x00,0x40,0x00,0x04,0x00,0x80,0x00,0x07,0xFF,0xE0,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40},/*"u",85*/ + {0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x07,0x80,0x00,0x00,0x07,0xF0,0x00,0x00,0x04,0xFE,0x00,0x00,0x04,0x1F,0xC0,0x00,0x00,0x03,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x1C,0x00,0x00,0x04,0x60,0x00,0x00,0x07,0x80,0x00,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"v",86*/ + {0x00,0x04,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x07,0xC0,0x00,0x00,0x07,0xFC,0x00,0x00,0x04,0x3F,0x80,0x00,0x00,0x03,0xE0,0x00,0x04,0x0F,0x80,0x00,0x06,0xF0,0x00,0x00,0x07,0xF0,0x00,0x00,0x07,0xFF,0x80,0x00,0x04,0x0F,0xE0,0x00,0x00,0x03,0x80,0x00,0x04,0x3C,0x00,0x00,0x07,0xC0,0x00,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00},/*"w",87*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x60,0x00,0x07,0x00,0xE0,0x00,0x07,0x83,0x20,0x00,0x07,0xE6,0x00,0x00,0x04,0xF8,0x00,0x00,0x00,0x3C,0x00,0x00,0x04,0x5E,0x20,0x00,0x05,0x87,0xA0,0x00,0x06,0x01,0xE0,0x00,0x04,0x00,0x60,0x00,0x04,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"x",88*/ + {0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x03,0x00,0x07,0x00,0x03,0x00,0x07,0xE0,0x01,0x00,0x04,0xF8,0x01,0x00,0x04,0x1F,0x02,0x00,0x00,0x07,0xFC,0x00,0x00,0x00,0xE0,0x00,0x00,0x07,0x00,0x00,0x04,0x38,0x00,0x00,0x07,0xC0,0x00,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00},/*"y",89*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x60,0x00,0x06,0x00,0xE0,0x00,0x04,0x03,0xE0,0x00,0x04,0x07,0xA0,0x00,0x04,0x0E,0x20,0x00,0x04,0x3C,0x20,0x00,0x04,0x70,0x20,0x00,0x05,0xE0,0x20,0x00,0x07,0x80,0x20,0x00,0x07,0x00,0x60,0x00,0x04,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"z",90*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x01,0x40,0x00,0x07,0xFE,0x3F,0xF8,0x08,0x00,0x00,0x04,0x10,0x00,0x00,0x02,0x10,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"{",91*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x02,0x10,0x00,0x00,0x02,0x08,0x00,0x00,0x04,0x07,0xFE,0x3F,0xF8,0x00,0x01,0x40,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ + {0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"~",94*/ +}; + +#endif //#ifndef __FONT_H__ + diff --git a/bsp/imx6ull-artpi-smart/drivers/imx6ull.h b/bsp/imx6ull-artpi-smart/drivers/imx6ull.h new file mode 100644 index 0000000000..a2e47226ef --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/imx6ull.h @@ -0,0 +1,415 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-22 quanzhao first version + */ + +#ifndef __IMX6UL_H__ +#define __IMX6UL_H__ + +#include +#include + +#ifdef RT_USING_LWP +#include +#include +#endif + +enum _gic_base_offsets +{ + kGICDBaseOffset = 0x1000, //!< GIC distributor offset. + kGICCBaseOffset = 0x2000 //!< GIC CPU interface offset. +}; + +/* SOC-relative definitions */ +enum _imx_interrupts +{ + SW_INTERRUPT_0 = 0, //!< Software interrupt 0. + SW_INTERRUPT_1 = 1, //!< Software interrupt 1. + SW_INTERRUPT_2 = 2, //!< Software interrupt 2. + SW_INTERRUPT_3 = 3, //!< Software interrupt 3. + SW_INTERRUPT_4 = 4, //!< Software interrupt 4. + SW_INTERRUPT_5 = 5, //!< Software interrupt 5. + SW_INTERRUPT_6 = 6, //!< Software interrupt 6. + SW_INTERRUPT_7 = 7, //!< Software interrupt 7. + SW_INTERRUPT_8 = 8, //!< Software interrupt 8. + SW_INTERRUPT_9 = 9, //!< Software interrupt 9. + SW_INTERRUPT_10 = 10, //!< Software interrupt 10. + SW_INTERRUPT_11 = 11, //!< Software interrupt 11. + SW_INTERRUPT_12 = 12, //!< Software interrupt 12. + SW_INTERRUPT_13 = 13, //!< Software interrupt 13. + SW_INTERRUPT_14 = 14, //!< Software interrupt 14. + SW_INTERRUPT_15 = 15, //!< Software interrupt 15. + RSVD_INTERRUPT_16 = 16, //!< Reserved. + RSVD_INTERRUPT_17 = 17, //!< Reserved. + RSVD_INTERRUPT_18 = 18, //!< Reserved. + RSVD_INTERRUPT_19 = 19, //!< Reserved. + RSVD_INTERRUPT_20 = 20, //!< Reserved. + RSVD_INTERRUPT_21 = 21, //!< Reserved. + RSVD_INTERRUPT_22 = 22, //!< Reserved. + RSVD_INTERRUPT_23 = 23, //!< Reserved. + RSVD_INTERRUPT_24 = 24, //!< Reserved. + RSVD_INTERRUPT_25 = 25, //!< Reserved. + RSVD_INTERRUPT_26 = 26, //!< Reserved. + RSVD_INTERRUPT_27 = 27, //!< Reserved. + RSVD_INTERRUPT_28 = 28, //!< Reserved. + RSVD_INTERRUPT_29 = 29, //!< Reserved. + RSVD_INTERRUPT_30 = 30, //!< Reserved. + RSVD_INTERRUPT_31 = 31, //!< Reserved. + IMX_INT_IOMUXC_GPR = 32, //!< General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot. + IMX_INT_CHEETAH_CSYSPWRUPREQ = 33, //!< @todo Listed as DAP in RM + IMX_INT_SDMA = 34, //!< Logical OR of all 48 SDMA interrupt requests/events from all channels. + IMX_INT_TSC = 35, //!< TSC + IMX_INT_SNVS_LP_SET_PWR_OFF = 36, //!< PMIC power off request. + IMX_INT_LCDIF = 37, //!< LCDIF interrupt request. + IMX_INT_BEE = 38, //!< BEE interrupt request. + IMX_INT_CSI = 39, //!< CMOS Sensor Interface interrupt request. + IMX_INT_PXP = 40, //!< PXP interrupt request. + IMX_INT_SCTR1 = 41, //!< SCTR1 + IMX_INT_SCTR2 = 42, //!< SCTR2 + IMX_INT_WDOG3 = 43, //!< WDOG3 timer reset interrupt request. + IMX_INT_INTERRUPT_44 = 44, //!< Reserved. + IMX_INT_APBH_DMA = 45, //!< APBH DMA + IMX_INT_EIM = 46, //!< EIM interrupt request. + IMX_INT_NAND_BCH = 47, //!< Reserved. + IMX_INT_NAND_GPMI = 48, //!< Reserved. + IMX_INT_UART6 = 49, //!< Logical OR of UART5 interrupt requests. + IMX_INT_INTERRUPT_50 = 50, //!< Reserved. + IMX_INT_SNVS = 51, //!< SNVS consolidated interrupt. + IMX_INT_SNVS_SEC = 52, //!< SNVS security interrupt. + IMX_INT_CSU = 53, //!< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted. + IMX_INT_USDHC1 = 54, //!< uSDHC1 (Enhanced SDHC) interrupt request. + IMX_INT_USDHC2 = 55, //!< uSDHC2 (Enhanced SDHC) interrupt request. + IMX_INT_SAI3 = 56, //!< uSDHC3 (Enhanced SDHC) interrupt request. + IMX_INT_SAI4 = 57, //!< uSDHC4 (Enhanced SDHC) interrupt request. + IMX_INT_UART1 = 58, //!< Logical OR of UART1 interrupt requests. + IMX_INT_UART2 = 59, //!< Logical OR of UART2 interrupt requests. + IMX_INT_UART3 = 60, //!< Logical OR of UART3 interrupt requests. + IMX_INT_UART4 = 61, //!< Logical OR of UART4 interrupt requests. + IMX_INT_UART5 = 62, //!< Logical OR of UART5 interrupt requests. + IMX_INT_ECSPI1 = 63, //!< eCSPI1 interrupt request. + IMX_INT_ECSPI2 = 64, //!< eCSPI2 interrupt request. + IMX_INT_ECSPI3 = 65, //!< eCSPI3 interrupt request. + IMX_INT_ECSPI4 = 66, //!< eCSPI4 interrupt request. + IMX_INT_I2C4 = 67, //!< Reserved. + IMX_INT_I2C1 = 68, //!< I2C1 interrupt request. + IMX_INT_I2C2 = 69, //!< I2C2 interrupt request. + IMX_INT_I2C3 = 70, //!< I2C3 interrupt request. + IMX_INT_UART7 = 71, //!< Logical OR of UART5 interrupt requests. + IMX_INT_UART8 = 72, //!< Logical OR of UART5 interrupt requests. + IMX_INT_INTERRUPT_73 = 73, //!< Reserved. + IMX_INT_USB_OTG2 = 74, //!< USB Host 1 interrupt request. + IMX_INT_USB_OTG1 = 75, //!< USB OTG1 interrupt request. + IMX_INT_USB_UTMI0 = 76, //!< UTMI0 interrupt request. + IMX_INT_USB_UTMI1 = 77, //!< UTMI1 interrupt request. + IMX_INT_CAAM_JQ2 = 78, //!< SSI1 interrupt request. + IMX_INT_CAAM_ERR = 79, //!< SSI2 interrupt request. + IMX_INT_CAAM_RTIC = 80, //!< SSI3 interrupt request. + IMX_INT_TEMPERATURE = 81, //!< Temperature Sensor (temp. greater than threshold) interrupt request. + IMX_INT_ASRC = 82, //!< Reserved. + IMX_INT_INTERRUPT_83 = 83, //!< Reserved. + IMX_INT_SPDIF = 84, //!< Logical OR of SPDIF TX and SPDIF RX interrupts. + IMX_INT_INTERRUPT_85 = 85, //!< Reserved. + IMX_INT_PMU_ANA_BO = 86, //!< PMU analog regulator brown-out interrupt request. + IMX_INT_GPT1 = 87, // + IMX_INT_EPIT1 = 88, //!< EPIT1 output compare interrupt. + IMX_INT_EPIT2 = 89, //!< EPIT2 output compare interrupt. + IMX_INT_GPIO1_INT7 = 90, //!< INT7 interrupt request. + IMX_INT_GPIO1_INT6 = 91, //!< INT6 interrupt request. + IMX_INT_GPIO1_INT5 = 92, //!< INT5 interrupt request. + IMX_INT_GPIO1_INT4 = 93, //!< INT4 interrupt request. + IMX_INT_GPIO1_INT3 = 94, //!< INT3 interrupt request. + IMX_INT_GPIO1_INT2 = 95, //!< INT2 interrupt request. + IMX_INT_GPIO1_INT1 = 96, //!< INT1 interrupt request. + IMX_INT_GPIO1_INT0 = 97, //!< INT0 interrupt request. + IMX_INT_GPIO1_INT15_0 = 98, //!< Combined interrupt indication for GPIO1 signals 0 - 15. + IMX_INT_GPIO1_INT31_16 = 99, //!< Combined interrupt indication for GPIO1 signals 16 - 31. + IMX_INT_GPIO2_INT15_0 = 100, //!< Combined interrupt indication for GPIO2 signals 0 - 15. + IMX_INT_GPIO2_INT31_16 = 101, //!< Combined interrupt indication for GPIO2 signals 16 - 31. + IMX_INT_GPIO3_INT15_0 = 102, //!< Combined interrupt indication for GPIO3 signals 0 - 15. + IMX_INT_GPIO3_INT31_16 = 103, //!< Combined interrupt indication for GPIO3 signals 16 - 31. + IMX_INT_GPIO4_INT15_0 = 104, //!< Combined interrupt indication for GPIO4 signals 0 - 15. + IMX_INT_GPIO4_INT31_16 = 105, //!< Combined interrupt indication for GPIO4 signals 16 - 31. + IMX_INT_GPIO5_INT15_0 = 106, //!< Combined interrupt indication for GPIO5 signals 0 - 15. + IMX_INT_GPIO5_INT31_16 = 107, //!< Combined interrupt indication for GPIO5 signals 16 - 31. + IMX_INT_INTERRUPT_108 = 108, //!< Reserved. + IMX_INT_INTERRUPT_109 = 109, //!< Reserved. + IMX_INT_INTERRUPT_110 = 110, //!< Reserved. + IMX_INT_INTERRUPT_111 = 111, //!< Reserved. + IMX_INT_WDOG1 = 112, //!< WDOG1 timer reset interrupt request. + IMX_INT_WDOG2 = 113, //!< WDOG2 timer reset interrupt request. + IMX_INT_KPP = 114, //!< Key Pad interrupt request. + IMX_INT_PWM1 = 115, //!< Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM2 = 116, //!< Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM3 = 117, //!< Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_PWM4 = 118, //!< Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. + IMX_INT_CCM_INT1 = 119, //!< CCM interrupt request 1. + IMX_INT_CCM_INT2 = 120, //!< CCM interrupt request 2. + IMX_INT_GPC_INT1 = 121, //!< GPC interrupt request 1. + IMX_INT_INTERRUPT_122 = 122, //!< Reserved. + IMX_INT_SRC = 123, //!< SRC interrupt request. + IMX_INT_INTERRUPT_124 = 124, //!< Logical OR of all L2 interrupt requests. + IMX_INT_INTERRUPT_125 = 125, //!< Parity Check error interrupt request. + IMX_INT_CHEETAH_PERFORM = 126, //!< Logical OR of Performance Unit interrupts. + IMX_INT_CHEETAH_TRIGGER = 127, //!< Logical OR of CTI trigger outputs. + IMX_INT_SRC_CPU_WDOG = 128, //!< Combined CPU wdog interrupts (4x) out of SRC. + IMX_INT_SAI1 = 129, //!< EPDC interrupt request. + IMX_INT_SAI2 = 130, //!< EPDC interrupt request. + IMX_INT_INTERRUPT_131 = 131, //!< DCP general interrupt request. + IMX_INT_ADC1 = 132, //!< DCP channel 0 interrupt request. + IMX_INT_ADC2 = 133, //!< DCP secure interrupt request. + IMX_INT_INTERRUPT_134 = 134, //!< Reserved. + IMX_INT_INTERRUPT_135 = 135, //!< Reserved. + IMX_INT_SJC = 136, //!< SJC interrupt from General Purpose register. + IMX_INT_CAAM_0 = 137, //!< Reserved. + IMX_INT_CAAM_1 = 138, //!< Reserved. + IMX_INT_QSPI = 139, //!< Reserved. + IMX_INT_TZASC1 = 140, //!< ASC1 interrupt request. + IMX_INT_GPT2 = 141, //!< Reserved. + IMX_INT_CAN1 = 142, //!< Reserved. + IMX_INT_CAN2 = 143, //!< Reserved. + IMX_INT_SIM1 = 144, //!< Reserved. + IMX_INT_SIM2 = 145, //!< Reserved. + IMX_INT_PWM5 = 146, //!< Fast Ethernet Controller interrupt request. + IMX_INT_PWM6 = 147, //!< Reserved. + IMX_INT_PWM7 = 148, //!< Reserved. + IMX_INT_PWM8 = 149, //!< Reserved. + IMX_INT_ENET1 = 150, //!< Reserved. + IMX_INT_ENET1_TIMER = 151, //!< Reserved. + IMX_INT_ENET2 = 152, //!< Reserved. + IMX_INT_ENET2_TIMER = 153, //!< Reserved. + IMX_INT_INTERRUPT_154 = 154, //!< Reserved. + IMX_INT_INTERRUPT_155 = 155, //!< Reserved. + IMX_INT_INTERRUPT_156 = 156, //!< Reserved. + IMX_INT_INTERRUPT_157 = 157, //!< Reserved. + IMX_INT_INTERRUPT_158 = 158, //!< Reserved. + IMX_INT_PMU_DIG_BO = 159, //!< //!< PMU digital regulator brown-out interrupt request. + IMX_INTERRUPT_COUNT = 160 //!< Total number of interrupts. +}; + +/* SOC-relative definitions */ +#include "MCIMX6Y2.h" + +#include "fsl_cache.h" +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "fsl_elcdif.h" +#include "fsl_usdhc.h" +#include "fsl_card.h" +#include "fsl_wdog.h" +#include "fsl_i2c.h" +#include "fsl_ecspi.h" +#include "fsl_snvs_hp.h" + +#define IMX6ULL_PERIPH_SIZE (16 * 1024) + +/* Interrupt Control Interface */ +#define ARM_GIC_CPU_BASE 0x00A00000 + +/* + * Peripheral addresses + */ +#define IMX6ULL_UART1_BASE UART1_BASE /* UART 1 */ +#define IMX6ULL_UART2_BASE UART2_BASE /* UART 2 */ +#define IMX6ULL_UART3_BASE UART3_BASE /* UART 3 */ +#define IMX6ULL_UART4_BASE UART4_BASE /* UART 4 */ +#define IMX6ULL_UART5_BASE UART5_BASE /* UART 5 */ +#define IMX6ULL_UART6_BASE UART6_BASE /* UART 6 */ +#define IMX6ULL_UART7_BASE UART7_BASE /* UART 7 */ +#define IMX6ULL_UART8_BASE UART8_BASE /* UART 8 */ + +#define IMX6ULL_WATCHDOG1_BASE WDOG1_BASE /* watchdog 1 */ +#define IMX6ULL_WATCHDOG2_BASE WDOG2_BASE /* watchdog 2 */ +#define IMX6ULL_WATCHDOG3_BASE WDOG3_BASE /* watchdog 3 */ + +#define IMX6ULL_GPIO1_BASE GPIO1_BASE /* GPIO port 0 */ +#define IMX6ULL_GPIO2_BASE GPIO2_BASE /* GPIO port 1 */ +#define IMX6ULL_GPIO3_BASE GPIO3_BASE /* GPIO port 2 */ +#define IMX6ULL_GPIO4_BASE GPIO4_BASE /* GPIO port 3 */ +#define IMX6ULL_GPIO5_BASE GPIO5_BASE /* GPIO port 4 */ + +#define IMX6ULL_SNVS_BASE SNVS_BASE /* Real Time Clock */ + +#define IMX6ULL_SCTL_BASE 0x021DC000u /* System Controller */ + +#define IMX6ULL_CLCD_BASE LCDIF_BASE /* CLCD */ + +#define IMX6ULL_GIC_DIST_BASE (ARM_GIC_CPU_BASE+kGICDBaseOffset) /* Generic interrupt controller distributor */ +#define IMX6ULL_GIC_CPU_BASE (ARM_GIC_CPU_BASE+kGICCBaseOffset) /* Generic interrupt controller CPU interface */ + +#define IMX6ULL_IOMUXC_BASE IOMUXC_BASE +#define IMX6ULL_IOMUXC_SNVS_BASE IOMUXC_SNVS_BASE +#define IMX6ULL_IOMUXC_GPR_BASE IOMUXC_GPR_BASE + +#define IMX6ULL_CCM_BASE 0x20C4000u +#define IMX6ULL_CCM_ANALOGY_BASE 0x20C8000u +#define IMX6ULL_PMU_BASE 0x20C8110u + +#define IMX6ULL_ENET1_BASE ENET1_BASE +#define IMX6ULL_ENET2_BASE ENET2_BASE + +#define IMX6ULL_GPT1_BASE GPT1_BASE +#define IMX6ULL_GPT2_BASE GPT2_BASE + +#define IMX6ULL_ECSPI1_BASE ECSPI1_BASE +#define IMX6ULL_ECSPI2_BASE ECSPI2_BASE +#define IMX6ULL_ECSPI3_BASE ECSPI3_BASE +#define IMX6ULL_ECSPI4_BASE ECSPI4_BASE + +#define IMX6ULL_I2C1_BASE I2C1_BASE +#define IMX6ULL_I2C2_BASE I2C2_BASE +#define IMX6ULL_I2C3_BASE I2C3_BASE +#define IMX6ULL_I2C4_BASE I2C4_BASE + +#define IMX6ULL_SDMA_BASE SDMAARM_BASE + +#define IMX6ULL_USDHC1_BASE USDHC1_BASE +#define IMX6ULL_USDHC2_BASE USDHC2_BASE + +#define IMX6ULL_SRC_BASE SRC_BASE + +#define IMX6ULL_GPMI_BASE GPMI_BASE +#define IMX6ULL_BCH_BASE BCH_BASE +#define IMX6ULL_APBH_BASE APBH_BASE + +#define IMX6ULL_CSI_BASE CSI_BASE + +#define IMX6ULL_CAN1_BASE CAN1_BASE +#define IMX6ULL_CAN2_BASE CAN2_BASE + +/* the maximum number of gic */ +#define ARM_GIC_MAX_NR 1 + +#define _internal_ro static const +#define _internal_rw static +#define _internal_zi static + +#define GET_ARRAY_NUM(ins) ((uint32_t)(sizeof(ins)/sizeof(ins[0]))) + +#include "bsp_clock.h" + +/* the maximum number of interrupts */ +#define ARM_GIC_NR_IRQS IMX_INTERRUPT_COUNT + +/* the maximum entries of the interrupt table */ +#define MAX_HANDLERS IMX_INTERRUPT_COUNT + +/* the basic constants needed by gic */ +rt_inline rt_uint32_t platform_get_gic_dist_base(void) +{ + rt_uint32_t gic_base; + asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base)); + return gic_base + kGICDBaseOffset; +} + +rt_inline rt_uint32_t platform_get_gic_cpu_base(void) +{ + rt_uint32_t gic_base; + asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base)); + return gic_base + kGICCBaseOffset; +} + +RT_WEAK void *rt_hw_kernel_virt_to_phys(void *v_addr) +{ + void *p_addr = 0; +#ifdef RT_USING_USERSPACE + rt_base_t level; + + extern rt_mmu_info mmu_info; + extern void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr); + + level = rt_hw_interrupt_disable(); + p_addr = _rt_hw_mmu_v2p(&mmu_info, v_addr); + rt_hw_interrupt_enable(level); +#else + p_addr = v_addr; +#endif + + return p_addr; +} + +rt_inline rt_uint32_t platform_get_periph_vaddr(rt_uint32_t paddr) +{ +#ifdef RT_USING_USERSPACE + rt_uint32_t mask = IMX6ULL_PERIPH_SIZE - 1; + return (rt_uint32_t)rt_ioremap((void*)(paddr&(~mask)), IMX6ULL_PERIPH_SIZE) + (paddr & mask); +#else + return paddr; +#endif +} + +rt_inline uint32_t mem_map_v2p(uint32_t virt) +{ +#ifdef RT_USING_USERSPACE + return virt + PV_OFFSET; +#else + return virt; +#endif +} + +rt_inline uint32_t mem_map_p2v(uint32_t phys) +{ +#ifdef RT_USING_USERSPACE + return phys - PV_OFFSET; +#else + return phys; +#endif +} + +#define GIC_IRQ_START 0 + +#define GIC_ACK_INTID_MASK 0x000003ff + +/* the definition needed by gic.c */ +#define __REG32(x) (*((volatile unsigned int *)(x))) + +/* keep compatible with platform SDK */ +typedef enum { + CPU_0, + CPU_1, + CPU_2, + CPU_3, +} cpuid_e; + +enum _gicd_sgi_filter +{ + //! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter. + kGicSgiFilter_UseTargetList = 0, + + //! Forward the interrupt to all CPU interfaces except that of the processor that requested + //! the interrupt. + kGicSgiFilter_AllOtherCPUs = 1, + + //! Forward the interrupt only to the CPU interface of the processor that requested the + //! interrupt. + kGicSgiFilter_OnlyThisCPU = 2 +}; + +typedef void (*irq_hdlr_t) (void); + +extern void rt_hw_interrupt_mask(int vector); +extern void rt_hw_interrupt_umask(int vector); +extern rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +rt_inline void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr) +{ + rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, RT_NULL, "unknown"); +} + +rt_inline void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority) +{ + rt_hw_interrupt_umask(irq_id); +} + +rt_inline void disable_interrupt(uint32_t irq_id, uint32_t cpu_id) +{ + rt_hw_interrupt_mask(irq_id); +} + +#endif /* __IMX6UL_H__ */ diff --git a/bsp/imx6ull-artpi-smart/drivers/rt_lcd.h b/bsp/imx6ull-artpi-smart/drivers/rt_lcd.h new file mode 100644 index 0000000000..c794008884 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/drivers/rt_lcd.h @@ -0,0 +1,59 @@ +#ifndef RT_LCD_H__ +#define RT_LCD_H__ + + +/* ioctls + 0x46 is 'F' */ +#define FBIOGET_VSCREENINFO 0x4600 +#define FBIOPUT_VSCREENINFO 0x4601 +#define FBIOGET_FSCREENINFO 0x4602 +#define FBIOGETCMAP 0x4604 +#define FBIOPUTCMAP 0x4605 +#define FBIOPAN_DISPLAY 0x4606 +#define FBIO_CURSOR 0x4608 +/* #define FBIOGET_MONITORSPEC 0x460C */ +/* #define FBIOPUT_MONITORSPEC 0x460D */ +/* #define FBIOSWITCH_MONIBIT 0x460E */ +#define FBIOGET_CON2FBMAP 0x460F +#define FBIOPUT_CON2FBMAP 0x4610 +#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */ +#define FBIOGET_VBLANK 0x4612 +#define FBIO_ALLOC 0x4613 +#define FBIO_FREE 0x4614 +#define FBIOGET_GLYPH 0x4615 +#define FBIOGET_HWCINFO 0x4616 +#define FBIOPUT_MODEINFO 0x4617 +#define FBIOGET_DISPINFO 0x4618 +#define FBIO_WAITFORVSYNC 0x4620 + +struct fb_bitfield +{ + uint32_t offset; /* beginning of bitfield */ + uint32_t length; /* length of bitfield */ + uint32_t msb_right; /* != 0 : Most significant bit is */ + /* right */ +}; + +struct fb_var_screeninfo +{ + uint32_t xres; + uint32_t yres; + + uint32_t bits_per_pixel; + + struct fb_bitfield red; /* bitfield in fb mem if true color, */ + struct fb_bitfield green; /* else only length is significant */ + struct fb_bitfield blue; + struct fb_bitfield transp; /* transparency */ +}; + +struct fb_fix_screeninfo +{ + char id[16]; + unsigned long smem_start; + uint32_t smem_len; + + uint32_t line_length; +}; + +#endif diff --git a/bsp/imx6ull-artpi-smart/figures/hw_resources.png b/bsp/imx6ull-artpi-smart/figures/hw_resources.png new file mode 100644 index 0000000000000000000000000000000000000000..d835bb588eda4860dadd011eb604400df4bf8072 GIT binary patch literal 181159 zcmb??Q+Q-;*Jje`sAJpi*iJf5$LiR&QE}3-opfy5wr$(CJ=O1g?>GM(%-I}NT~}$> z-s@Rw-B`~Kk&_XF`-c4u1Ox=`r?{{J2ncvO2ngr~6a?^{tC9R25Rh-|WABDX68+`}-Xo<7?E{;win@K+9~=>8q6-NMdj$e!39@BdTPukEB>E-!i^o#9 zWirYWMtci9;q&YFS^n^Dkk8EcW;J3)5V=3$hc{2lnphaa9K0%NWR0@Je;Qb%Cm19q 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+list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/CMSIS/Include/cmsis_gcc.h b/bsp/imx6ull-artpi-smart/libraries/sdk/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000..bb89fbba9e --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/CMSIS/SConscript b/bsp/imx6ull-artpi-smart/libraries/sdk/CMSIS/SConscript new file mode 100644 index 0000000000..8ca37048bf --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/CMSIS/SConscript @@ -0,0 +1,10 @@ +from building import * + +cwd = GetCurrentDir() +src = [] + +path = [cwd + '/Include'] + +group = DefineGroup('libraries', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/core_ca.h b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/core_ca.h new file mode 100644 index 0000000000..47d1e7fbbe --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/core_ca.h @@ -0,0 +1,50 @@ +/* Copyright (c) 2009 - 2015 ARM LIMITED + Copyright (c) 2016, Freescale Semiconductor, Inc. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CA_H +#define __CORE_CA_H + +/*------------------ GNU Compiler ----------------------*/ +#if defined ( __GNUC__ ) + #include "cortexa_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include "cortexa_iar.h" + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CA_H */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/core_ca7.h b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/core_ca7.h new file mode 100644 index 0000000000..4e3a347b96 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/core_ca7.h @@ -0,0 +1,1377 @@ +/* Copyright (c) 2009 - 2015 ARM LIMITED + Copyright (c) 2016, Freescale Semiconductor, Inc. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CA7_H_GENERIC +#define __CORE_CA7_H_GENERIC + +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(__GNUC__) + #define FORCEDINLINE __attribute__((always_inline)) +#else + #define FORCEDINLINE +#endif + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_ca.h" /* Core Instruction and Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA7_H_DEPENDANT +#define __CORE_CA7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - CPSR + - CP15 Registers + ******************************************************************************/ + +/* Core Register CPSR */ +typedef union +{ + struct + { + uint32_t M:5; /*!< bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved0:4; /*!< bit: 20..23 Reserved */ + uint32_t J:1; /*!< bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CPSR_Type; + +/* CPSR Register Definitions */ +#define CPSR_N_Pos 31U /*!< CPSR: N Position */ +#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< CPSR: N Mask */ + +#define CPSR_Z_Pos 30U /*!< CPSR: Z Position */ +#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< CPSR: Z Mask */ + +#define CPSR_C_Pos 29U /*!< CPSR: C Position */ +#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< CPSR: C Mask */ + +#define CPSR_V_Pos 28U /*!< CPSR: V Position */ +#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< CPSR: V Mask */ + +#define CPSR_Q_Pos 27U /*!< CPSR: Q Position */ +#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< CPSR: Q Mask */ + +#define CPSR_IT0_Pos 25U /*!< CPSR: IT0 Position */ +#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< CPSR: IT0 Mask */ + +#define CPSR_J_Pos 24U /*!< CPSR: J Position */ +#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< CPSR: J Mask */ + +#define CPSR_GE_Pos 16U /*!< CPSR: GE Position */ +#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< CPSR: GE Mask */ + +#define CPSR_IT1_Pos 10U /*!< CPSR: IT1 Position */ +#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< CPSR: IT1 Mask */ + +#define CPSR_E_Pos 9U /*!< CPSR: E Position */ +#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< CPSR: E Mask */ + +#define CPSR_A_Pos 8U /*!< CPSR: A Position */ +#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< CPSR: A Mask */ + +#define CPSR_I_Pos 7U /*!< CPSR: I Position */ +#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< CPSR: I Mask */ + +#define CPSR_F_Pos 6U /*!< CPSR: F Position */ +#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< CPSR: F Mask */ + +#define CPSR_T_Pos 5U /*!< CPSR: T Position */ +#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< CPSR: T Mask */ + +#define CPSR_M_Pos 0U /*!< CPSR: M Position */ +#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< CPSR: M Mask */ + + +/* CP15 Register SCTLR */ +typedef union +{ + struct + { + uint32_t M:1; /*!< bit: 0 MMU enable */ + uint32_t A:1; /*!< bit: 1 Alignment check enable */ + uint32_t C:1; /*!< bit: 2 Cache enable */ + uint32_t _reserved0:2; /*!< bit: 3.. 4 Reserved */ + uint32_t CP15BEN:1; /*!< bit: 5 CP15 barrier enable */ + uint32_t _reserved1:1; /*!< bit: 6 Reserved */ + uint32_t B:1; /*!< bit: 7 Endianness model */ + uint32_t _reserved2:2; /*!< bit: 8.. 9 Reserved */ + uint32_t SW:1; /*!< bit: 10 SWP and SWPB enable */ + uint32_t Z:1; /*!< bit: 11 Branch prediction enable */ + uint32_t I:1; /*!< bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< bit: 13 Vectors bit */ + uint32_t RR:1; /*!< bit: 14 Round Robin select */ + uint32_t _reserved3:2; /*!< bit:15..16 Reserved */ + uint32_t HA:1; /*!< bit: 17 Hardware Access flag enable */ + uint32_t _reserved4:1; /*!< bit: 18 Reserved */ + uint32_t WXN:1; /*!< bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< bit: 20 Unprivileged write permission implies PL1 XN */ + uint32_t FI:1; /*!< bit: 21 Fast interrupts configuration enable */ + uint32_t U:1; /*!< bit: 22 Alignment model */ + uint32_t _reserved5:1; /*!< bit: 23 Reserved */ + uint32_t VE:1; /*!< bit: 24 Interrupt Vectors Enable */ + uint32_t EE:1; /*!< bit: 25 Exception Endianness */ + uint32_t _reserved6:1; /*!< bit: 26 Reserved */ + uint32_t NMFI:1; /*!< bit: 27 Non-maskable FIQ (NMFI) support */ + uint32_t TRE:1; /*!< bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< bit: 29 Access flag enable */ + uint32_t TE:1; /*!< bit: 30 Thumb Exception enable */ + uint32_t _reserved7:1; /*!< bit: 31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} SCTLR_Type; + +#define SCTLR_TE_Pos 30U /*!< SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< SCTLR: TRE Mask */ + +#define SCTLR_NMFI_Pos 27U /*!< SCTLR: NMFI Position */ +#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< SCTLR: NMFI Mask */ + +#define SCTLR_EE_Pos 25U /*!< SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< SCTLR: EE Mask */ + +#define SCTLR_VE_Pos 24U /*!< SCTLR: VE Position */ +#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< SCTLR: VE Mask */ + +#define SCTLR_U_Pos 22U /*!< SCTLR: U Position */ +#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< SCTLR: U Mask */ + +#define SCTLR_FI_Pos 21U /*!< SCTLR: FI Position */ +#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< SCTLR: FI Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< SCTLR: WXN Mask */ + +#define SCTLR_HA_Pos 17U /*!< SCTLR: HA Position */ +#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< SCTLR: HA Mask */ + +#define SCTLR_RR_Pos 14U /*!< SCTLR: RR Position */ +#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< SCTLR: RR Mask */ + +#define SCTLR_V_Pos 13U /*!< SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< SCTLR: I Mask */ + +#define SCTLR_Z_Pos 11U /*!< SCTLR: Z Position */ +#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< SCTLR: Z Mask */ + +#define SCTLR_SW_Pos 10U /*!< SCTLR: SW Position */ +#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< SCTLR: SW Mask */ + +#define SCTLR_B_Pos 7U /*!< SCTLR: B Position */ +#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< SCTLR: B Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< SCTLR: M Mask */ + +/* CP15 Register ACTLR */ +typedef union +{ + struct + { + uint32_t _reserved0:6; /*!< bit: 0.. 5 Reserved */ + uint32_t SMP:1; /*!< bit: 6 Enables coherent requests to the processor */ + uint32_t _reserved1:3; /*!< bit: 7.. 9 Reserved */ + uint32_t DODMBS:1; /*!< bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + uint32_t _reserved3:12; /*!< bit:16..27 Reserved */ + uint32_t DDI:1; /*!< bit: 28 Disable dual issue */ + uint32_t _reserved7:3; /*!< bit:29..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< ACTLR: DDI Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< ACTLR: L1PCTL Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< ACTLR: L1RADIS Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< ACTLR: DODMBS Mask */ + +#define ACTLR_SMP_Pos 6U /*!< ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< ACTLR: SMP Mask */ + + +/* CP15 Register CPACR */ +typedef union +{ + struct + { + uint32_t _reserved0:20; /*!< bit: 0..19 Reserved */ + uint32_t cp10:2; /*!< bit:20..21 Access rights for coprocessor 10 */ + uint32_t cp11:2; /*!< bit:22..23 Access rights for coprocessor 11 */ + uint32_t _reserved1:6; /*!< bit:24..29 Reserved */ + uint32_t D32DIS:1; /*!< bit: 30 Disable use of registers D16-D31 of the VFP register file */ + uint32_t ASEDIS:1; /*!< bit: 31 Disable Advanced SIMD Functionality */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CPACR_Type; + +#define CPACR_ASEDIS_Pos 31U /*!< CPACR: ASEDIS Position */ +#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< CPACR: ASEDIS Mask */ + +#define CPACR_D32DIS_Pos 30U /*!< CPACR: D32DIS Position */ +#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< CPACR: D32DIS Mask */ + +#define CPACR_cp11_Pos 22U /*!< CPACR: cp11 Position */ +#define CPACR_cp11_Msk (3UL << CPACR_cp11_Pos) /*!< CPACR: cp11 Mask */ + +#define CPACR_cp10_Pos 20U /*!< CPACR: cp10 Position */ +#define CPACR_cp10_Msk (3UL << CPACR_cp10_Pos) /*!< CPACR: cp10 Mask */ + + +/* CP15 Register DFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t Domain:4; /*!< bit: 4.. 7 Fault on which domain */ + uint32_t _reserved0:2; /*!< bit: 8.. 9 Reserved */ + uint32_t FS1:1; /*!< bit: 10 Fault Status bits bit 4 */ + uint32_t WnR:1; /*!< bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< bit: 12 External abort type */ + uint32_t CM:1; /*!< bit: 13 Cache maintenance fault */ + uint32_t _reserved1:18; /*!< bit:14..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} DFSR_Type; + +#define DFSR_CM_Pos 13U /*!< DFSR: CM Position */ +#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< DFSR: CM Mask */ + +#define DFSR_Ext_Pos 12U /*!< DFSR: Ext Position */ +#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< DFSR: Ext Mask */ + +#define DFSR_WnR_Pos 11U /*!< DFSR: WnR Position */ +#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< DFSR: WnR Mask */ + +#define DFSR_FS1_Pos 10U /*!< DFSR: FS1 Position */ +#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< DFSR: FS1 Mask */ + +#define DFSR_Domain_Pos 4U /*!< DFSR: Domain Position */ +#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< DFSR: Domain Mask */ + +#define DFSR_FS0_Pos 0U /*!< DFSR: FS0 Position */ +#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< DFSR: FS0 Mask */ + + +/* CP15 Register IFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t _reserved0:6; /*!< bit: 4.. 9 Reserved */ + uint32_t FS1:1; /*!< bit: 10 Fault Status bits bit 4 */ + uint32_t _reserved1:1; /*!< bit: 11 Reserved */ + uint32_t ExT:1; /*!< bit: 12 External abort type */ + uint32_t _reserved2:19; /*!< bit:13..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IFSR_Type; + +#define IFSR_ExT_Pos 12U /*!< IFSR: ExT Position */ +#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< IFSR: ExT Mask */ + +#define IFSR_FS1_Pos 10U /*!< IFSR: FS1 Position */ +#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< IFSR: FS1 Mask */ + +#define IFSR_FS0_Pos 0U /*!< IFSR: FS0 Position */ +#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< IFSR: FS0 Mask */ + + +/* CP15 Register ISR */ +typedef union +{ + struct + { + uint32_t _reserved0:6; /*!< bit: 0.. 5 Reserved */ + uint32_t F:1; /*!< bit: 6 FIQ pending bit */ + uint32_t I:1; /*!< bit: 7 IRQ pending bit */ + uint32_t A:1; /*!< bit: 8 External abort pending bit */ + uint32_t _reserved1:23; /*!< bit:14..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} ISR_Type; + +#define ISR_A_Pos 13U /*!< ISR: A Position */ +#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< ISR: A Mask */ + +#define ISR_I_Pos 12U /*!< ISR: I Position */ +#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< ISR: I Mask */ + +#define ISR_F_Pos 11U /*!< ISR: F Position */ +#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< ISR: F Mask */ + + +/* Mask and shift a bit field value for use in a register bit range. */ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/* Mask and shift a register value to extract a bit filed value. */ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + + + +/******************************************************************************* + * CP15 Access Functions + ******************************************************************************/ +FORCEDINLINE __STATIC_INLINE uint32_t __get_SCTLR(void) +{ + return __MRC(15, 0, 1, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) +{ + __MCR(15, 0, sctlr, 1, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_ACTLR(void) +{ + return __MRC(15, 0, 1, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_ACTLR(uint32_t actlr) +{ + __MCR(15, 0, actlr, 1, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_CPACR(void) +{ + return __MRC(15, 0, 1, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE void __set_CPACR(uint32_t cpacr) +{ + __MCR(15, 0, cpacr, 1, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_TTBR0(void) +{ + return __MRC(15, 0, 2, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) +{ + __MCR(15, 0, ttbr0, 2, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_TTBR1(void) +{ + return __MRC(15, 0, 2, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_TTBR1(uint32_t ttbr1) +{ + __MCR(15, 0, ttbr1, 2, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_TTBCR(void) +{ + return __MRC(15, 0, 2, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE void __set_TTBCR(uint32_t ttbcr) +{ + __MCR(15, 0, ttbcr, 2, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_DACR(void) +{ + return __MRC(15, 0, 3, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_DACR(uint32_t dacr) +{ + __MCR(15, 0, dacr, 3, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_DFSR(void) +{ + return __MRC(15, 0, 5, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_DFSR(uint32_t dfsr) +{ + __MCR(15, 0, dfsr, 5, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_IFSR(void) +{ + return __MRC(15, 0, 5, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_IFSR(uint32_t ifsr) +{ + __MCR(15, 0, ifsr, 5, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_DFAR(void) +{ + return __MRC(15, 0, 6, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_DFAR(uint32_t dfar) +{ + __MCR(15, 0, dfar, 6, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_IFAR(void) +{ + return __MRC(15, 0, 6, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE void __set_IFAR(uint32_t ifar) +{ + __MCR(15, 0, ifar, 6, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_VBAR(void) +{ + return __MRC(15, 0, 12, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_VBAR(uint32_t vbar) +{ + __MCR(15, 0, vbar, 12, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_ISR(void) +{ + return __MRC(15, 0, 12, 1, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_ISR(uint32_t isr) +{ + __MCR(15, 0, isr, 12, 1, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_CONTEXTIDR(void) +{ + return __MRC(15, 0, 13, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_CONTEXTIDR(uint32_t contextidr) +{ + __MCR(15, 0, contextidr, 13, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_CBAR(void) +{ + return __MRC(15, 4, 15, 0, 0); +} + + +/******************************************************************************* + * L1 Cache Functions + ******************************************************************************/ +#define L1C_INSTRUCTION_CACHE_LINE_SIZE (32U) +#define L1C_DATA_CACHE_LINE_SIZE (64U) + +#define L1C_DATA_CACHE_OP_CLEAN (1U) +#define L1C_DATA_CACHE_OP_INVALIDATE (2U) +#define L1C_DATA_CACHE_OP_CLEAN_INVALIDATE (3U) + +/* Invalidate both intruction cache and branch predictor */ +FORCEDINLINE __STATIC_INLINE void L1C_InvalidateInstructionCacheAll(void) +{ + /* ICIALLU only affects self core. */ + __MCR(15, 0, 0, 7, 5, 0); + /* BPIALL only affects self core. */ + __MCR(15, 0, 0, 7, 5, 6); + /* Ensure completion of the invalidation */ + __DSB(); + __ISB(); +} + +FORCEDINLINE __STATIC_INLINE void L1C_InvalidateInstructionCacheLine(const void *VirtAddr) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_INSTRUCTION_CACHE_LINE_SIZE - 1); + /* ICIMVAU */ + __MCR(15, 0, base, 7, 5, 1); + /* BPIMVA */ + __MCR(15, 0, base, 7, 5, 7); + /* Ensure completion of the invalidation */ + __DSB(); + __ISB(); +} + +FORCEDINLINE __STATIC_INLINE void L1C_InvalidateInstructionCacheRange(const void *VirtAddr, uint32_t length) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_INSTRUCTION_CACHE_LINE_SIZE - 1); + uint32_t end = (uint32_t)VirtAddr + length; + + while (base < end) + { + /* ICIMVAU */ + __MCR(15, 0, base, 7, 5, 1); + /* BPIMVA */ + __MCR(15, 0, base, 7, 5, 7); + base += L1C_INSTRUCTION_CACHE_LINE_SIZE; + } + + /* Ensure completion of the invalidation */ + __DSB(); + __ISB(); +} + +FORCEDINLINE __STATIC_INLINE void L1C_EnableInstructionCache() +{ + uint32_t sctlr = __get_SCTLR(); + + if ((sctlr & (SCTLR_I_Msk | SCTLR_Z_Msk)) != (SCTLR_I_Msk | SCTLR_Z_Msk)) + { /* Enable cache and branch predictor */ + L1C_InvalidateInstructionCacheAll(); + sctlr |= SCTLR_I_Msk | SCTLR_Z_Msk; + __set_SCTLR(sctlr); + /* __ISB() is not needed as there's no instruction changes */ + } +} + +FORCEDINLINE __STATIC_INLINE void L1C_DisableInstructionCache() +{ + uint32_t sctlr = __get_SCTLR(); + + if ((sctlr & (SCTLR_I_Msk | SCTLR_Z_Msk)) != 0) + { /* Disable cache and branch predictor */ + sctlr &= ~(SCTLR_I_Msk | SCTLR_Z_Msk); + __set_SCTLR(sctlr); + /* __ISB() is not needed as there's no instruction changes */ + } +} + +FORCEDINLINE __STATIC_INLINE void L1C_OpDataCacheAll(uint32_t operation) +{ + uint32_t clidr, loc, ctype; + uint32_t level; + uint32_t ccsidr, set, ass, setshift, assshift; + uint32_t i, j, reg; + + clidr = __MRC(15, 1, 0, 0, 1); + loc = (clidr >> 24) & 0x7UL; + + for (level = 0; level < loc; level++) + { /* Clean each level */ + ctype = (clidr >> (level * 3)) & 0x7UL; + if (ctype == 2 || /* Data cache only */ + ctype == 3 || /* Separate instruction and data caches */ + ctype == 4) /* Unified cache */ + { + __MCR(15, 2, level << 1, 0, 0, 0); /* Select data cache */ + + ccsidr = __MRC(15, 1, 0, 0, 0); /* Get cache size ID */ + set = ((ccsidr >> 13) & 0x7FFFUL) + 1; + ass = ((ccsidr >> 3) & 0x3FFUL) + 1; + + setshift = (ccsidr & 0x7UL) + 2 + 2; + for (i = 1; i < 10 && ass > (1UL << i); i++) + { + } + assshift = 32 - i; + + for (i = 0; i < ass; i++) + { + for (j = 0; j < set; j++) + { + reg = (i << assshift) | (j << setshift) | (level << 1); + switch (operation) + { + case L1C_DATA_CACHE_OP_CLEAN: + /* DCCSW */ + __MCR(15, 0, reg, 7, 10, 2); + break; + case L1C_DATA_CACHE_OP_INVALIDATE: + /* DCISW */ + __MCR(15, 0, reg, 7, 6, 2); + break; + case L1C_DATA_CACHE_OP_CLEAN_INVALIDATE: + /* DCCISW */ + __MCR(15, 0, reg, 7, 14, 2); + break; + default: + break; + } + } + } + /* Ensure completion of the L1 cache operation */ + __DSB(); + } + } + + /* Ensure completion of the cache operation */ + __DSB(); +} + +/* Invalidate data cache */ +FORCEDINLINE __STATIC_INLINE void L1C_InvalidateDataCacheAll(void) +{ + L1C_OpDataCacheAll(L1C_DATA_CACHE_OP_INVALIDATE); +} + +FORCEDINLINE __STATIC_INLINE void L1C_InvalidateDataCacheLine(const void *VirtAddr) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_DATA_CACHE_LINE_SIZE - 1); + /* DCIMVAC */ + __MCR(15, 0, base, 7, 6, 1); + /* Ensure completion of the invalidation */ + __DSB(); +} + +FORCEDINLINE __STATIC_INLINE void L1C_InvalidateDataCacheRange(const void *VirtAddr, uint32_t length) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_DATA_CACHE_LINE_SIZE - 1); + uint32_t end = (uint32_t)VirtAddr + length; + + while (base < end) + { + /* DCIMVAC */ + __MCR(15, 0, base, 7, 6, 1); + base += L1C_DATA_CACHE_LINE_SIZE; + } + + /* Ensure completion of the invalidation */ + __DSB(); +} + +/* Clean data cache */ +FORCEDINLINE __STATIC_INLINE void L1C_CleanDataCacheAll(void) +{ + L1C_OpDataCacheAll(L1C_DATA_CACHE_OP_CLEAN); +} + +FORCEDINLINE __STATIC_INLINE void L1C_CleanDataCacheLine(const void *VirtAddr) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_DATA_CACHE_LINE_SIZE - 1); + /* DCCMVAC */ + __MCR(15, 0, base, 7, 10, 1); + /* Ensure completion of the clean */ + __DSB(); +} + +FORCEDINLINE __STATIC_INLINE void L1C_CleanDataCacheRange(const void *VirtAddr, uint32_t length) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_DATA_CACHE_LINE_SIZE - 1); + uint32_t end = (uint32_t)VirtAddr + length; + + while (base < end) + { + /* DCCMVAC */ + __MCR(15, 0, base, 7, 10, 1); + base += L1C_DATA_CACHE_LINE_SIZE; + } + + /* Ensure completion of the clean */ + __DSB(); +} + +/* Clean and invalidate data cache */ +FORCEDINLINE __STATIC_INLINE void L1C_CleanInvalidateDataCacheAll(void) +{ + L1C_OpDataCacheAll(L1C_DATA_CACHE_OP_CLEAN_INVALIDATE); +} + +FORCEDINLINE __STATIC_INLINE void L1C_CleanInvalidateDataCacheLine(const void *VirtAddr) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_DATA_CACHE_LINE_SIZE - 1); + /* DCCIMVAC */ + __MCR(15, 0, base, 7, 14, 1); + /* Ensure completion of the clean */ + __DSB(); +} + +FORCEDINLINE __STATIC_INLINE void L1C_CleanInvalidateDataCacheRange(const void *VirtAddr, uint32_t length) +{ + uint32_t base = (uint32_t)VirtAddr & ~(L1C_DATA_CACHE_LINE_SIZE - 1); + uint32_t end = (uint32_t)VirtAddr + length; + + while (base < end) + { + /* DCCIMVAC */ + __MCR(15, 0, base, 7, 14, 1); + base += L1C_DATA_CACHE_LINE_SIZE; + } + + /* Ensure completion of the clean */ + __DSB(); +} + +FORCEDINLINE __STATIC_INLINE void L1C_EnableDataCache() +{ + uint32_t sctlr = __get_SCTLR(); + + if ((sctlr & SCTLR_C_Msk) != SCTLR_C_Msk) + { /* Enable cache */ + L1C_InvalidateDataCacheAll(); + sctlr |= SCTLR_C_Msk; + __set_SCTLR(sctlr); + /* __ISB() is not needed as there's no instruction changes */ + } +} + +FORCEDINLINE __STATIC_INLINE void L1C_DisableDataCache() +{ + uint32_t sctlr = __get_SCTLR(); + + if ((sctlr & SCTLR_C_Msk) != 0) + { /* Disable cache */ + sctlr &= ~SCTLR_C_Msk; + __set_SCTLR(sctlr); + L1C_CleanInvalidateDataCacheAll(); + /* __ISB() is not needed as there's no instruction changes */ + } +} + +/******************************************************************************* + * MMU Functions + ******************************************************************************/ +enum _mmu_memory_type +{ + MMU_MemoryStronglyOrdered = 0U, /*!< TEX: 0, C: 0, B: 0 */ + MMU_MemoryDevice = 1U, /*!< TEX: 0, C: 0, B: 1 */ + MMU_MemoryWriteBackNoWriteAllocate = 3U, /*!< TEX: 0, C: 1, B: 1 */ + MMU_MemoryNonCacheable = 4U, /*!< TEX: 1, C: 0, B: 0 */ + MMU_MemoryWriteBackWriteAllocate = 7U, /*!< TEX: 1, C: 1, B: 1 */ +}; + +enum _mmu_domain_access +{ + MMU_DomainNA = 0U, /*!< No acces. Any access to the domain generates a Domain fault */ + MMU_DomainClient = 1U, /*!< Accesses are checked against the permission bits in the translation tables */ + MMU_DomainManager = 3U, /*!< Accesses are not checked against the permission bits in the translation tables */ +}; + +enum _mmu_access_permission +{ + MMU_AccessNANA = 0U, /*!< No access in both privileged and unprivileged modes */ + MMU_AccessRWNA = 1U, /*!< Read/Write in privileged mode, no access in unprivileged mode */ + MMU_AccessRWRO = 2U, /*!< Read/Write in privileged mode, Read Only in unprivileged mode */ + MMU_AccessRWRW = 3U, /*!< Read/Write in privileged mode, Read/Write in unprivileged mode */ + MMU_AccessRONA = 5U, /*!< Read Only in privileged mode, no access in unprivileged mode */ + MMU_AccessRORO = 7U, /*!< Read Only in privileged mode, Read Only in unprivileged mode */ +}; + +typedef struct _mmu_attribute_t +{ + uint8_t type; /*!< memory type, see _mmu_memory_type */ + uint8_t domain; /*!< memory domain assignment */ + uint8_t accessPerm; /*!< the memory region access permission, see _mmu_access_permission */ + uint8_t shareable:1; /*!< memory region is shareable among multiple cores or system master */ + uint8_t notSecure:1; /*!< translated physical address is in non-secure memory map */ + uint8_t notGlob:1; /*!< the region translation is process specific */ + uint8_t notExec:1; /*!< the memory region cannot execute code */ +} mmu_attribute_t; + +/* L1Table must be 16KB aligned (bit [13:0] all 0) with size 16KB */ +FORCEDINLINE __STATIC_INLINE void MMU_Init(uint32_t *L1Table) +{ + uint32_t L1Base = (uint32_t)L1Table; + + /* Use TTBR translation, with 16KB L1Table size (N=0) */ + __set_TTBCR(0); + + /* Set TTBR0 with inner/outer write back write allocate and not shareable, [4:3]=01, [1]=0, [6,0]=01 */ + __set_TTBR0((L1Base & 0xFFFFC000UL) | 0x9UL); + + /* Set all domains to client */ + __set_DACR(0x55555555UL); + + /* Set PROCID and ASID to 0 */ + __MCR(15, 0, 0, 13, 0, 1); + + /* Set all virtual space to invalid */ + memset(L1Table, 0, 4096*4); +} + +/* L1Table[4096], L2Table[256] */ +/* L2Table == NULL: use L1Table entry */ +FORCEDINLINE __STATIC_INLINE void MMU_ConfigPage(uint32_t *L1Table, uint32_t *L2Table, const void *VirtAddr, + uint32_t PhysAddr, const mmu_attribute_t *Attr) +{ + uint32_t index1 = (uint32_t)VirtAddr >> 20; + uint32_t index2 = ((uint32_t)VirtAddr >> 12) & 0xFFUL; + uint32_t descriptor1 = L1Table[index1]; + uint32_t descriptor2 = (PhysAddr & 0xFFFFF000UL) | /* Physical address */ + (Attr->notGlob ? (1UL << 11) : 0) | /* nG */ + (Attr->shareable ? (1UL << 10) : 0) | /* S */ + (Attr->notExec ? 1UL : 0) | /* XN */ + (((Attr->type >> 2) & 7UL) << 6) | /* TEX */ + ((Attr->type & 3UL) << 2) | /* C,B */ + ((Attr->accessPerm & 4UL) << 9) | /* AP[2] */ + ((Attr->accessPerm & 3UL) << 4) | /* AP[1:0] */ + 2UL; /* Small Page */ + + if ((descriptor1 & 3UL) == 1) /* Page table first level already exists */ + { + /* Ignore the parameter and use the descriptor */ + L2Table = (uint32_t *)(descriptor1 & 0xFFFFFC00UL); + L2Table[index2] = descriptor2; + } + else if ((descriptor1 & 3UL) == 0) /* No L2 table available */ + { + L1Table[index1] = ((uint32_t)L2Table & 0xFFFFFC00UL) | /* L2 Table address */ + ((Attr->domain & 15UL) << 5) | /* Domain */ + (Attr->notSecure ? (1UL << 3) : 0) | /* NS */ + 1UL; /* Page Table */ + /* Use L2Table in parameter */ + L2Table[index2] = descriptor2; + } +} + +/* L1Table[4096], L2Table[256] */ +FORCEDINLINE __STATIC_INLINE void MMU_ConfigLargePage(uint32_t *L1Table, uint32_t *L2Table, const void *VirtAddr, + uint32_t PhysAddr, const mmu_attribute_t *Attr) +{ + uint32_t i; + uint32_t index1 = (uint32_t)VirtAddr >> 20; + uint32_t index2 = ((uint32_t)VirtAddr >> 12) & 0xF0UL; + uint32_t descriptor1 = L1Table[index1]; + uint32_t descriptor2 = (PhysAddr & 0xFFFF0000UL) | /* Physical address */ + (Attr->notGlob ? (1UL << 11) : 0) | /* nG */ + (Attr->shareable ? (1UL << 10) : 0) | /* S */ + (Attr->notExec ? (1UL << 15) : 0) | /* XN */ + (((Attr->type >> 2) & 7UL) << 12) | /* TEX */ + ((Attr->type & 3UL) << 2) | /* C,B */ + ((Attr->accessPerm & 4UL) << 9) | /* AP[2] */ + ((Attr->accessPerm & 3UL) << 4) | /* AP[1:0] */ + 1UL; /* Large Page */ + + if ((descriptor1 & 3UL) == 1) /* Page table first level already exists */ + { + /* Ignore the parameter and use the descriptor */ + L2Table = (uint32_t *)(descriptor1 & 0xFFFFFC00UL); + for (i = 0; i < 16; i++) + L2Table[index2 + i] = descriptor2; + } + else if ((descriptor1 & 3UL) == 0) /* No L2 table available */ + { + L1Table[index1] = ((uint32_t)L2Table & 0xFFFFFC00UL) | /* L2 Table address */ + ((Attr->domain & 15UL) << 5) | /* Domain */ + (Attr->notSecure ? (1UL << 3) : 0) | /* NS */ + 1UL; /* Page Table */ + /* Use L2Table in parameter */ + for (i = 0; i < 16; i++) + L2Table[index2 + i] = descriptor2; + } +} + +/* L1Table[4096] */ +FORCEDINLINE __STATIC_INLINE void MMU_ConfigSection(uint32_t *L1Table, const void *VirtAddr, + uint32_t PhysAddr, const mmu_attribute_t *Attr) +{ + uint32_t index = (uint32_t)VirtAddr >> 20; + uint32_t descriptor = (PhysAddr & 0xFFF00000UL) | /* Physical address */ + (Attr->notSecure ? (1UL << 19) : 0) | /* NS */ + (Attr->notGlob ? (1UL << 17) : 0) | /* nG */ + (Attr->shareable ? (1UL << 16) : 0) | /* S */ + (Attr->notExec ? (1UL << 4) : 0) | /* XN */ + (((Attr->type >> 2) & 7UL) << 12) | /* TEX */ + ((Attr->type & 3UL) << 2) | /* C,B */ + ((Attr->domain & 15UL) << 5) | /* Domain */ + ((Attr->accessPerm & 4UL) << 15) | /* AP[2] */ + ((Attr->accessPerm & 3UL) << 10) | /* AP[1:0] */ + 2UL; /* Section */ + + L1Table[index] = descriptor; +} + +/* L1Table[4096] */ +FORCEDINLINE __STATIC_INLINE void MMU_ConfigSuperSection(uint32_t *L1Table, const void *VirtAddr, + uint32_t PhysAddr, const mmu_attribute_t *Attr) +{ + uint32_t i; + uint32_t index = ((uint32_t)VirtAddr >> 20) & 0xFF0UL; + uint32_t descriptor = (PhysAddr & 0xFF000000UL) | /* Physical address */ + (Attr->notSecure ? (1UL << 19) : 0) | /* NS */ + (Attr->notGlob ? (1UL << 17) : 0) | /* nG */ + (Attr->shareable ? (1UL << 16) : 0) | /* S */ + (Attr->notExec ? (1UL << 4) : 0) | /* XN */ + (((Attr->type >> 2) & 7UL) << 12) | /* TEX */ + ((Attr->type & 3UL) << 2) | /* C,B */ + /* Supersection has fixed domain 0 */ + ((Attr->accessPerm & 4UL) << 15) | /* AP[2] */ + ((Attr->accessPerm & 3UL) << 10) | /* AP[1:0] */ + 2; /* Section */ + + for (i = 0; i < 16; i++) + L1Table[index + i] = descriptor; +} + +FORCEDINLINE __STATIC_INLINE uint32_t * MMU_GetL1Table(void) +{ + return (uint32_t *)(__get_TTBR0() & 0xFFFFC000UL); +} + +FORCEDINLINE __STATIC_INLINE void MMU_SetL1Table(uint32_t *L1Table) +{ + /* update L1Table base address without changing other attributes */ + __set_TTBR0(((uint32_t)L1Table & 0xFFFFC000UL) | (__get_TTBR0() & 0x3FFFUL)); +} + +FORCEDINLINE __STATIC_INLINE uint32_t * MMU_GetL2Table(const void *VirtAddr) +{ + uint32_t index1 = (uint32_t)VirtAddr >> 20; + uint32_t descriptor1; + uint32_t *L1Table = MMU_GetL1Table(); + uint32_t *L2Table = NULL; + + descriptor1 = L1Table[index1]; + if ((descriptor1 & 3UL) == 1) /* Page */ + L2Table = (uint32_t *)(descriptor1 & 0xFFFFFC00UL); + + return L2Table; +} + +FORCEDINLINE __STATIC_INLINE void MMU_SetContext(uint32_t procid, uint32_t asid) +{ + uint32_t reg = (procid << 8) | (asid & 0xFFUL); + + __MCR(15, 0, reg, 13, 0, 1); +} + +/* access: _mmu_domain_access */ +FORCEDINLINE __STATIC_INLINE void MMU_ConfigDomain(uint32_t domain, uint32_t access) +{ + uint32_t dacr = __get_DACR(); + uint32_t mask = 3UL << ((domain & 0xFUL) * 2); + uint32_t reg = (dacr & ~mask) | ((access & 3) << ((domain & 0xFUL) * 2)); + + __set_DACR(reg); +} + +FORCEDINLINE __STATIC_INLINE void MMU_InvalidateTLB(void) +{ + /* TLBIALL only affects self core */ + __MCR(15, 0, 0, 8, 7, 0); + __DSB(); + __ISB(); +} + +FORCEDINLINE __STATIC_INLINE void MMU_Disable(void) +{ + uint32_t sctlr = __get_SCTLR(); + + sctlr &= ~SCTLR_M_Msk; + __set_SCTLR(sctlr); + __ISB(); +} + +FORCEDINLINE __STATIC_INLINE void MMU_Enable(void) +{ + uint32_t sctlr = __get_SCTLR(); + + MMU_InvalidateTLB(); + sctlr |= SCTLR_M_Msk; + __set_SCTLR(sctlr); + __ISB(); +} + +/******************************************************************************* + * GIC Functions + ******************************************************************************/ +typedef struct +{ + uint32_t RESERVED0[1024]; + __IOM uint32_t D_CTLR; /*!< Offset: 0x1000 (R/W) Distributor Control Register */ + __IM uint32_t D_TYPER; /*!< Offset: 0x1004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t D_IIDR; /*!< Offset: 0x1008 (R/ ) Distributor Implementer Identification Register */ + uint32_t RESERVED1[29]; + __IOM uint32_t D_IGROUPR[16]; /*!< Offset: 0x1080 - 0x0BC (R/W) Interrupt Group Registers */ + uint32_t RESERVED2[16]; + __IOM uint32_t D_ISENABLER[16]; /*!< Offset: 0x1100 - 0x13C (R/W) Interrupt Set-Enable Registers */ + uint32_t RESERVED3[16]; + __IOM uint32_t D_ICENABLER[16]; /*!< Offset: 0x1180 - 0x1BC (R/W) Interrupt Clear-Enable Registers */ + uint32_t RESERVED4[16]; + __IOM uint32_t D_ISPENDR[16]; /*!< Offset: 0x1200 - 0x23C (R/W) Interrupt Set-Pending Registers */ + uint32_t RESERVED5[16]; + __IOM uint32_t D_ICPENDR[16]; /*!< Offset: 0x1280 - 0x2BC (R/W) Interrupt Clear-Pending Registers */ + uint32_t RESERVED6[16]; + __IOM uint32_t D_ISACTIVER[16]; /*!< Offset: 0x1300 - 0x33C (R/W) Interrupt Set-Active Registers */ + uint32_t RESERVED7[16]; + __IOM uint32_t D_ICACTIVER[16]; /*!< Offset: 0x1380 - 0x3BC (R/W) Interrupt Clear-Active Registers */ + uint32_t RESERVED8[16]; + __IOM uint8_t D_IPRIORITYR[512]; /*!< Offset: 0x1400 - 0x5FC (R/W) Interrupt Priority Registers */ + uint32_t RESERVED9[128]; + __IOM uint8_t D_ITARGETSR[512]; /*!< Offset: 0x1800 - 0x9FC (R/W) Interrupt Targets Registers */ + uint32_t RESERVED10[128]; + __IOM uint32_t D_ICFGR[32]; /*!< Offset: 0x1C00 - 0xC7C (R/W) Interrupt configuration registers */ + uint32_t RESERVED11[32]; + __IM uint32_t D_PPISR; /*!< Offset: 0x1D00 (R/ ) Private Peripheral Interrupt Status Register */ + __IM uint32_t D_SPISR[15]; /*!< Offset: 0x1D04 - 0xD3C (R/ ) Shared Peripheral Interrupt Status Registers */ + uint32_t RESERVED12[112]; + __OM uint32_t D_SGIR; /*!< Offset: 0x1F00 ( /W) Software Generated Interrupt Register */ + uint32_t RESERVED13[3]; + __IOM uint8_t D_CPENDSGIR[16]; /*!< Offset: 0x1F10 - 0xF1C (R/W) SGI Clear-Pending Registers */ + __IOM uint8_t D_SPENDSGIR[16]; /*!< Offset: 0x1F20 - 0xF2C (R/W) SGI Set-Pending Registers */ + uint32_t RESERVED14[40]; + __IM uint32_t D_PIDR4; /*!< Offset: 0x1FD0 (R/ ) Peripheral ID4 Register */ + __IM uint32_t D_PIDR5; /*!< Offset: 0x1FD4 (R/ ) Peripheral ID5 Register */ + __IM uint32_t D_PIDR6; /*!< Offset: 0x1FD8 (R/ ) Peripheral ID6 Register */ + __IM uint32_t D_PIDR7; /*!< Offset: 0x1FDC (R/ ) Peripheral ID7 Register */ + __IM uint32_t D_PIDR0; /*!< Offset: 0x1FE0 (R/ ) Peripheral ID0 Register */ + __IM uint32_t D_PIDR1; /*!< Offset: 0x1FE4 (R/ ) Peripheral ID1 Register */ + __IM uint32_t D_PIDR2; /*!< Offset: 0x1FE8 (R/ ) Peripheral ID2 Register */ + __IM uint32_t D_PIDR3; /*!< Offset: 0x1FEC (R/ ) Peripheral ID3 Register */ + __IM uint32_t D_CIDR0; /*!< Offset: 0x1FF0 (R/ ) Component ID0 Register */ + __IM uint32_t D_CIDR1; /*!< Offset: 0x1FF4 (R/ ) Component ID1 Register */ + __IM uint32_t D_CIDR2; /*!< Offset: 0x1FF8 (R/ ) Component ID2 Register */ + __IM uint32_t D_CIDR3; /*!< Offset: 0x1FFC (R/ ) Component ID3 Register */ + + __IOM uint32_t C_CTLR; /*!< Offset: 0x2000 (R/W) CPU Interface Control Register */ + __IOM uint32_t C_PMR; /*!< Offset: 0x2004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t C_BPR; /*!< Offset: 0x2008 (R/W) Binary Point Register */ + __IM uint32_t C_IAR; /*!< Offset: 0x200C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t C_EOIR; /*!< Offset: 0x2010 ( /W) End Of Interrupt Register */ + __IM uint32_t C_RPR; /*!< Offset: 0x2014 (R/ ) Running Priority Register */ + __IM uint32_t C_HPPIR; /*!< Offset: 0x2018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t C_ABPR; /*!< Offset: 0x201C (R/W) Aliased Binary Point Register */ + __IM uint32_t C_AIAR; /*!< Offset: 0x2020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t C_AEOIR; /*!< Offset: 0x2024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t C_AHPPIR; /*!< Offset: 0x2028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + uint32_t RESERVED15[41]; + __IOM uint32_t C_APR0; /*!< Offset: 0x20D0 (R/W) Active Priority Register */ + uint32_t RESERVED16[3]; + __IOM uint32_t C_NSAPR0; /*!< Offset: 0x20E0 (R/W) Non-secure Active Priority Register */ + uint32_t RESERVED17[6]; + __IM uint32_t C_IIDR; /*!< Offset: 0x20FC (R/ ) CPU Interface Identification Register */ + uint32_t RESERVED18[960]; + __OM uint32_t C_DIR; /*!< Offset: 0x3000 ( /W) Deactivate Interrupt Register */ +} GIC_Type; + + +/* For simplicity, we only use group0 of GIC */ +FORCEDINLINE __STATIC_INLINE void GIC_Init(void) +{ + uint32_t i; + uint32_t irqRegs; + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + irqRegs = (gic->D_TYPER & 0x1FUL) + 1; + + /* On POR, all SPI is in group 0, level-sensitive and using 1-N model */ + + /* Disable all PPI, SGI and SPI */ + for (i = 0; i < irqRegs; i++) + gic->D_ICENABLER[i] = 0xFFFFFFFFUL; + + /* Make all interrupts have higher priority */ + gic->C_PMR = (0xFFUL << (8 - __GIC_PRIO_BITS)) & 0xFFUL; + + /* No subpriority, all priority level allows preemption */ + gic->C_BPR = 7 - __GIC_PRIO_BITS; + + /* Enable group0 distribution */ + gic->D_CTLR = 1UL; + + /* Enable group0 signaling */ + gic->C_CTLR = 1UL; +} + +FORCEDINLINE __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + gic->D_ISENABLER[((uint32_t)(int32_t)IRQn) >> 5] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + +FORCEDINLINE __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + gic->D_ICENABLER[((uint32_t)(int32_t)IRQn) >> 5] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + +/* Return IRQ number (and CPU source in SGI case) */ +FORCEDINLINE __STATIC_INLINE uint32_t GIC_AcknowledgeIRQ(void) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + return gic->C_IAR & 0x1FFFUL; +} + +/* value should be got from GIC_AcknowledgeIRQ() */ +FORCEDINLINE __STATIC_INLINE void GIC_DeactivateIRQ(uint32_t value) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + gic->C_EOIR = value; +} + +FORCEDINLINE __STATIC_INLINE uint32_t GIC_GetRunningPriority(void) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + return gic->C_RPR & 0xFFUL; +} + +FORCEDINLINE __STATIC_INLINE void GIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + gic->C_BPR = PriorityGroup & 0x7UL; +} + +FORCEDINLINE __STATIC_INLINE uint32_t GIC_GetPriorityGrouping(void) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + return gic->C_BPR & 0x7UL; +} + +FORCEDINLINE __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + gic->D_IPRIORITYR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8UL - __GIC_PRIO_BITS)) & (uint32_t)0xFFUL); +} + +FORCEDINLINE __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + return(((uint32_t)gic->D_IPRIORITYR[((uint32_t)(int32_t)IRQn)] >> (8UL - __GIC_PRIO_BITS))); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/cortexa_gcc.h b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/cortexa_gcc.h new file mode 100644 index 0000000000..408afbbf6e --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/cortexa_gcc.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CORTEXA_GCC_H +#define __CORTEXA_GCC_H + +#include "cmsis_gcc.h" + +#define __STRINGIFY(x) #x + +#define __MCR(coproc, opcode_1, src, CRn, CRm, opcode_2) \ + __ASM volatile ("MCR " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ + "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " \ + __STRINGIFY(opcode_2) \ + : : "r" (src) ) + +#define __MRC(coproc, opcode_1, CRn, CRm, opcode_2) \ + ({ \ + uint32_t __dst; \ + __ASM volatile ("MRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ + "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " \ + __STRINGIFY(opcode_2) \ + : "=r" (__dst) ); \ + __dst; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_APSR(uint32_t apsr) +{ + __ASM volatile ("MSR apsr, %0" : : "r" (apsr) : "cc"); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc"); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void) +{ + uint32_t result; + + __ASM volatile ("VMRS %0, fpexc" : "=r" (result) ); + return result; +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) +{ + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc)); +} + +#endif /* __CORTEXA_GCC_H */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/cortexa_iar.h b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/cortexa_iar.h new file mode 100644 index 0000000000..e9a70d8ea0 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/Include/cortexa_iar.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CORTEXA_IAR_H +#define __CORTEXA_IAR_H + +#ifdef __cplusplus +/* FIXME: work around the IAR CPP compiling issue in Cortex-A support */ +#define __get_PSR() 0 +#endif + +#include + +static inline uint32_t __get_FPEXC(void) +{ + uint32_t result; + + __ASM volatile ("VMRS %0, fpexc" : "=r" (result) ); + return result; +} + +static inline void __set_FPEXC(uint32_t fpexc) +{ + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc)); +} + +#endif /* __CORTEXA_IAR_H */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/SConscript b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/SConscript new file mode 100644 index 0000000000..8ca37048bf --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/CORTEXA/SConscript @@ -0,0 +1,10 @@ +from building import * + +cwd = GetCurrentDir() +src = [] + +path = [cwd + '/Include'] + +group = DefineGroup('libraries', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/SConscript b/bsp/imx6ull-artpi-smart/libraries/sdk/SConscript new file mode 100644 index 0000000000..4c815c49b8 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.h new file mode 100644 index 0000000000..f23cdfc0d1 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.h @@ -0,0 +1,42156 @@ +/* +** ################################################################### +** Processors: MCIMX6Y2CVM05 +** MCIMX6Y2CVM08 +** MCIMX6Y2DVM05 +** MCIMX6Y2DVM09 +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: IMX6ULLRM, Rev. 1, Feb. 2017 +** Version: rev. 3.0, 2017-02-28 +** Build: b170422 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCIMX6Y2 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-12-18) +** Initial version. +** - rev. 2.0 (2016-08-02) +** Rev.B Header GA +** - rev. 3.0 (2017-02-28) +** Rev.1 Header GA +** +** ################################################################### +*/ + +/*! + * @file MCIMX6Y2.h + * @version 3.0 + * @date 2017-02-28 + * @brief CMSIS Peripheral Access Layer for MCIMX6Y2 + * + * CMSIS Peripheral Access Layer for MCIMX6Y2 + */ + +#ifndef _MCIMX6Y2_H_ +#define _MCIMX6Y2_H_ /**< Symbol preventing repeated inclusion */ + +extern uint32_t *g_ccm_vbase; +extern uint32_t *g_ccm_analog_vbase; +extern uint32_t *g_pmu_vbase; + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 160 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + Software0_IRQn = 0, /**< Cortex-A7 Software Generated Interrupt 0 */ + Software1_IRQn = 1, /**< Cortex-A7 Software Generated Interrupt 1 */ + Software2_IRQn = 2, /**< Cortex-A7 Software Generated Interrupt 2 */ + Software3_IRQn = 3, /**< Cortex-A7 Software Generated Interrupt 3 */ + Software4_IRQn = 4, /**< Cortex-A7 Software Generated Interrupt 4 */ + Software5_IRQn = 5, /**< Cortex-A7 Software Generated Interrupt 5 */ + Software6_IRQn = 6, /**< Cortex-A7 Software Generated Interrupt 6 */ + Software7_IRQn = 7, /**< Cortex-A7 Software Generated Interrupt 7 */ + Software8_IRQn = 8, /**< Cortex-A7 Software Generated Interrupt 8 */ + Software9_IRQn = 9, /**< Cortex-A7 Software Generated Interrupt 9 */ + Software10_IRQn = 10, /**< Cortex-A7 Software Generated Interrupt 10 */ + Software11_IRQn = 11, /**< Cortex-A7 Software Generated Interrupt 11 */ + Software12_IRQn = 12, /**< Cortex-A7 Software Generated Interrupt 12 */ + Software13_IRQn = 13, /**< Cortex-A7 Software Generated Interrupt 13 */ + Software14_IRQn = 14, /**< Cortex-A7 Software Generated Interrupt 14 */ + Software15_IRQn = 15, /**< Cortex-A7 Software Generated Interrupt 15 */ + VirtualMaintenance_IRQn = 25, /**< Cortex-A7 Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /**< Cortex-A7 Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /**< Cortex-A7 Virtual Timer Interrupt */ + LegacyFastInt_IRQn = 28, /**< Cortex-A7 Legacy nFIQ signal Interrupt */ + SecurePhyTimer_IRQn = 29, /**< Cortex-A7 Secure Physical Timer Interrupt */ + NonSecurePhyTimer_IRQn = 30, /**< Cortex-A7 Non-secure Physical Timer Interrupt */ + LegacyIRQ_IRQn = 31, /**< Cortex-A7 Legacy nIRQ Interrupt */ + + /* Device specific interrupts */ + IOMUXC_IRQn = 32, /**< General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot. */ + DAP_IRQn = 33, /**< Debug Access Port interrupt request. */ + SDMA_IRQn = 34, /**< SDMA interrupt request from all channels. */ + TSC_IRQn = 35, /**< TSC interrupt. */ + SNVS_IRQn = 36, /**< Logic OR of SNVS_LP and SNVS_HP interrupts. */ + LCDIF_IRQn = 37, /**< LCDIF sync interrupt. */ + RNGB_IRQn = 38, /**< RNGB interrupt. */ + CSI_IRQn = 39, /**< CMOS Sensor Interface interrupt request. */ + PXP_IRQ0_IRQn = 40, /**< PXP interrupt pxp_irq_0. */ + SCTR_IRQ0_IRQn = 41, /**< SCTR compare interrupt ipi_int[0]. */ + SCTR_IRQ1_IRQn = 42, /**< SCTR compare interrupt ipi_int[1]. */ + WDOG3_IRQn = 43, /**< WDOG3 timer reset interrupt request. */ + Reserved44_IRQn = 44, /**< Reserved */ + APBH_IRQn = 45, /**< DMA Logical OR of APBH DMA channels 0-3 completion and error interrupts. */ + WEIM_IRQn = 46, /**< WEIM interrupt request. */ + RAWNAND_BCH_IRQn = 47, /**< BCH operation complete interrupt. */ + RAWNAND_GPMI_IRQn = 48, /**< GPMI operation timeout error interrupt. */ + UART6_IRQn = 49, /**< UART6 interrupt request. */ + PXP_IRQ1_IRQn = 50, /**< PXP interrupt pxp_irq_1. */ + SNVS_Consolidated_IRQn = 51, /**< SNVS consolidated interrupt. */ + SNVS_Security_IRQn = 52, /**< SNVS security interrupt. */ + CSU_IRQn = 53, /**< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted. */ + USDHC1_IRQn = 54, /**< USDHC1 (Enhanced SDHC) interrupt request. */ + USDHC2_IRQn = 55, /**< USDHC2 (Enhanced SDHC) interrupt request. */ + SAI3_RX_IRQn = 56, /**< SAI3 interrupt ipi_int_sai_rx. */ + SAI3_TX_IRQn = 57, /**< SAI3 interrupt ipi_int_sai_tx. */ + UART1_IRQn = 58, /**< UART1 interrupt request. */ + UART2_IRQn = 59, /**< UART2 interrupt request. */ + UART3_IRQn = 60, /**< UART3 interrupt request. */ + UART4_IRQn = 61, /**< UART4 interrupt request. */ + UART5_IRQn = 62, /**< UART5 interrupt request. */ + eCSPI1_IRQn = 63, /**< eCSPI1 interrupt request. */ + eCSPI2_IRQn = 64, /**< eCSPI2 interrupt request. */ + eCSPI3_IRQn = 65, /**< eCSPI3 interrupt request. */ + eCSPI4_IRQn = 66, /**< eCSPI4 interrupt request. */ + I2C4_IRQn = 67, /**< I2C4 interrupt request. */ + I2C1_IRQn = 68, /**< I2C1 interrupt request. */ + I2C2_IRQn = 69, /**< I2C2 interrupt request. */ + I2C3_IRQn = 70, /**< I2C3 interrupt request. */ + UART7_IRQn = 71, /**< UART-7 ORed interrupt. */ + UART8_IRQn = 72, /**< UART-8 ORed interrupt. */ + Reserved73_IRQn = 73, /**< Reserved */ + USB_OTG2_IRQn = 74, /**< USBO2 USB OTG2 */ + USB_OTG1_IRQn = 75, /**< USBO2 USB OTG1 */ + USB_PHY1_IRQn = 76, /**< UTMI0 interrupt request. */ + USB_PHY2_IRQn = 77, /**< UTMI1 interrupt request. */ + DCP_IRQ_IRQn = 78, /**< DCP interrupt request dcp_irq. */ + DCP_VMI_IRQ_IRQn = 79, /**< DCP interrupt request dcp_vmi_irq. */ + DCP_SEC_IRQ_IRQn = 80, /**< DCP interrupt request secure_irq. */ + TEMPMON_IRQn = 81, /**< Temperature Monitor Temperature Sensor (temperature greater than threshold) interrupt request. */ + ASRC_IRQn = 82, /**< ASRC interrupt request. */ + ESAI_IRQn = 83, /**< ESAI interrupt request. */ + SPDIF_IRQn = 84, /**< SPDIF interrupt. */ + Reserved85_IRQn = 85, /**< Reserved */ + PMU_IRQ1_IRQn = 86, /**< Brown-out event on either the 1.1, 2.5 or 3.0 regulators. */ + GPT1_IRQn = 87, /**< Logical OR of GPT1 rollover interrupt line, input capture 1 and 2 lines, output compare 1, 2, and 3 interrupt lines. */ + EPIT1_IRQn = 88, /**< EPIT1 output compare interrupt. */ + EPIT2_IRQn = 89, /**< EPIT2 output compare interrupt. */ + GPIO1_INT7_IRQn = 90, /**< INT7 interrupt request. */ + GPIO1_INT6_IRQn = 91, /**< INT6 interrupt request. */ + GPIO1_INT5_IRQn = 92, /**< INT5 interrupt request. */ + GPIO1_INT4_IRQn = 93, /**< INT4 interrupt request. */ + GPIO1_INT3_IRQn = 94, /**< INT3 interrupt request. */ + GPIO1_INT2_IRQn = 95, /**< INT2 interrupt request. */ + GPIO1_INT1_IRQn = 96, /**< INT1 interrupt request. */ + GPIO1_INT0_IRQn = 97, /**< INT0 interrupt request. */ + GPIO1_Combined_0_15_IRQn = 98, /**< Combined interrupt indication for GPIO1 signals 0 - 15. */ + GPIO1_Combined_16_31_IRQn = 99, /**< Combined interrupt indication for GPIO1 signals 16 - 31. */ + GPIO2_Combined_0_15_IRQn = 100, /**< Combined interrupt indication for GPIO2 signals 0 - 15. */ + GPIO2_Combined_16_31_IRQn = 101, /**< Combined interrupt indication for GPIO2 signals 16 - 31. */ + GPIO3_Combined_0_15_IRQn = 102, /**< Combined interrupt indication for GPIO3 signals 0 - 15. */ + GPIO3_Combined_16_31_IRQn = 103, /**< Combined interrupt indication for GPIO3 signals 16 - 31. */ + GPIO4_Combined_0_15_IRQn = 104, /**< Combined interrupt indication for GPIO4 signals 0 - 15. */ + GPIO4_Combined_16_31_IRQn = 105, /**< Combined interrupt indication for GPIO4 signals 16 - 31. */ + GPIO5_Combined_0_15_IRQn = 106, /**< Combined interrupt indication for GPIO5 signals 0 - 15. */ + GPIO5_Combined_16_31_IRQn = 107, /**< Combined interrupt indication for GPIO5 signals 16 - 31. */ + Reserved108_IRQn = 108, /**< Reserved */ + Reserved109_IRQn = 109, /**< Reserved */ + Reserved110_IRQn = 110, /**< Reserved */ + Reserved111_IRQn = 111, /**< Reserved */ + WDOG1_IRQn = 112, /**< WDOG1 timer reset interrupt request. */ + WDOG2_IRQn = 113, /**< WDOG2 timer reset interrupt request. */ + KPP_IRQn = 114, /**< Key Pad interrupt request. */ + PWM1_IRQn = 115, /**< hasRegInstance(`PWM1`)?`Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + PWM2_IRQn = 116, /**< hasRegInstance(`PWM2`)?`Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + PWM3_IRQn = 117, /**< hasRegInstance(`PWM3`)?`Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + PWM4_IRQn = 118, /**< hasRegInstance(`PWM4`)?`Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + CCM_IRQ1_IRQn = 119, /**< CCM interrupt request ipi_int_1. */ + CCM_IRQ2_IRQn = 120, /**< CCM interrupt request ipi_int_2. */ + GPC_IRQn = 121, /**< GPC interrupt request 1. */ + Reserved122_IRQn = 122, /**< Reserved */ + SRC_IRQn = 123, /**< SRC interrupt request src_ipi_int_1. */ + Reserved124_IRQn = 124, /**< Reserved */ + Reserved125_IRQn = 125, /**< Reserved */ + CPU_PerformanceUnit_IRQn = 126, /**< Performance Unit interrupt ~ipi_pmu_irq_b. */ + CPU_CTI_Trigger_IRQn = 127, /**< CTI trigger outputs interrupt ~ipi_cti_irq_b. */ + SRC_Combined_IRQn = 128, /**< Combined CPU wdog interrupts (4x) out of SRC. */ + SAI1_IRQn = 129, /**< SAI1 interrupt request. */ + SAI2_IRQn = 130, /**< SAI2 interrupt request. */ + Reserved131_IRQn = 131, /**< Reserved */ + ADC1_IRQn = 132, /**< ADC1 interrupt request. */ + ADC_5HC_IRQn = 133, /**< ADC_5HC interrupt request. */ + Reserved134_IRQn = 134, /**< Reserved */ + Reserved135_IRQn = 135, /**< Reserved */ + SJC_IRQn = 136, /**< SJC interrupt from General Purpose register. */ + CAAM_Job_Ring0_IRQn = 137, /**< CAAM job ring 0 interrupt ipi_caam_irq0. */ + CAAM_Job_Ring1_IRQn = 138, /**< CAAM job ring 1 interrupt ipi_caam_irq1. */ + QSPI_IRQn = 139, /**< QSPI1 interrupt request ipi_int_ored. */ + TZASC_IRQn = 140, /**< TZASC (PL380) interrupt request. */ + GPT2_IRQn = 141, /**< Logical OR of GPT2 rollover interrupt line, input capture 1 and 2 lines, output compare 1, 2 and 3 interrupt lines. */ + CAN1_IRQn = 142, /**< Combined interrupt of ini_int_busoff,ini_int_error,ipi_int_mbor,ipi_int_txwarning and ipi_int_waken */ + CAN2_IRQn = 143, /**< Combined interrupt of ini_int_busoff,ini_int_error,ipi_int_mbor,ipi_int_txwarning and ipi_int_waken */ + Reserved144_IRQn = 144, /**< Reserved */ + Reserved145_IRQn = 145, /**< Reserved */ + PWM5_IRQn = 146, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM6_IRQn = 147, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM7_IRQn = 148, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM8_IRQn = 149, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + ENET1_IRQn = 150, /**< ENET1 interrupt */ + ENET1_1588_IRQn = 151, /**< ENET1 1588 Timer interrupt [synchronous] request. */ + ENET2_IRQn = 152, /**< ENET2 interrupt */ + ENET2_1588_IRQn = 153, /**< MAC 0 1588 Timer interrupt [synchronous] request. */ + Reserved154_IRQn = 154, /**< Reserved */ + Reserved155_IRQn = 155, /**< Reserved */ + Reserved156_IRQn = 156, /**< Reserved */ + Reserved157_IRQn = 157, /**< Reserved */ + Reserved158_IRQn = 158, /**< Reserved */ + PMU_IRQ2_IRQn = 159 /**< Brown-out event on either core, gpu or soc regulators. */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Configuration of the Cortex-A7 Processor and Core Peripherals + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-A7 Processor and Core Peripherals + * @{ + */ + +#define __CA7_REV 0x0005 /**< Core revision r0p5 */ +#define __GIC_PRIO_BITS 5 /**< Number of Bits used for Priority Levels */ +#define __FPU_PRESENT 1 /**< FPU present or not */ + +#include "core_ca7.h" /* Core Peripheral Access Layer */ +#include "system_MCIMX6Y2.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_mux_ctl_pad +{ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_MOD = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TMS = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TDO = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TDI = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TCK = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TRST_B = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_CTS_B = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_RTS_B = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART4_TX_DATA = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART4_RX_DATA = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART5_TX_DATA = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART5_RX_DATA = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA0 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA1 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_EN = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA0 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA1 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_EN = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_ER = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA0 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA1 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_EN = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA0 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA1 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_EN = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_ER = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_CLK = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_RESET = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA00 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA01 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA02 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA03 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA04 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA05 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA06 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA07 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA08 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA09 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA10 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA11 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA12 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA13 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA14 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA15 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA16 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA17 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA18 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA19 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA20 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA21 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA22 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA23 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_MCLK = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA00 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA01 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA02 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA03 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA04 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA05 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA06 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA07 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */ +} iomuxc_sw_mux_ctl_pad_t; + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD_DDR + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD_DDR collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad_ddr +{ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 = 16U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 = 17U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B = 18U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B = 19U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B = 20U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B = 21U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B = 22U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 = 23U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 = 24U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 = 25U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 = 26U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 = 27U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 = 28U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 = 29U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P = 30U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P = 31U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P = 32U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_RESET = 33U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ +} iomuxc_sw_pad_ctl_pad_ddr_t; + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad +{ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_CTS_B = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_RTS_B = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART4_TX_DATA = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART4_RX_DATA = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART5_TX_DATA = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART5_RX_DATA = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA0 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA1 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_EN = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA0 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA1 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_EN = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_ER = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA0 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA1 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_EN = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA0 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA1 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_EN = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_ER = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_CLK = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_RESET = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA00 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA01 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA02 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA03 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA04 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA05 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA06 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA07 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA08 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA09 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA10 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA11 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA12 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA13 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA14 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA15 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA16 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA17 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA18 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA19 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA20 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA21 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA22 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA23 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_MCLK = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA00 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA01 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA02 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA03 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA04 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA05 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA06 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA07 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */ +} iomuxc_sw_pad_ctl_pad_t; + +/*! + * @brief Enumeration for the IOMUXC select input + * + * Defines the enumeration for the IOMUXC select input collections. + */ +typedef enum _iomuxc_select_input +{ + kIOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */ + kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA05_SELECT_INPUT = 5U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA00_SELECT_INPUT = 6U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA01_SELECT_INPUT = 7U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA04_SELECT_INPUT = 8U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA06_SELECT_INPUT = 9U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA07_SELECT_INPUT = 10U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA08_SELECT_INPUT = 11U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA09_SELECT_INPUT = 12U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA10_SELECT_INPUT = 13U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA11_SELECT_INPUT = 14U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA12_SELECT_INPUT = 15U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA13_SELECT_INPUT = 16U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA14_SELECT_INPUT = 17U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA15_SELECT_INPUT = 18U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA16_SELECT_INPUT = 19U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA17_SELECT_INPUT = 20U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA18_SELECT_INPUT = 21U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA19_SELECT_INPUT = 22U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA20_SELECT_INPUT = 23U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA21_SELECT_INPUT = 24U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA22_SELECT_INPUT = 25U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA23_SELECT_INPUT = 26U, /**< IOMUXC select input index */ + kIOMUXC_CSI_HSYNC_SELECT_INPUT = 27U, /**< IOMUXC select input index */ + kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 28U, /**< IOMUXC select input index */ + kIOMUXC_CSI_VSYNC_SELECT_INPUT = 29U, /**< IOMUXC select input index */ + kIOMUXC_CSI_FIELD_SELECT_INPUT = 30U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_SCLK_SELECT_INPUT = 31U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_MISO_SELECT_INPUT = 32U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_MOSI_SELECT_INPUT = 33U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_SS0_B_SELECT_INPUT = 34U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_SCLK_SELECT_INPUT = 35U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_MISO_SELECT_INPUT = 36U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_MOSI_SELECT_INPUT = 37U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_SS0_B_SELECT_INPUT = 38U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_SCLK_SELECT_INPUT = 39U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_MISO_SELECT_INPUT = 40U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_MOSI_SELECT_INPUT = 41U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_SS0_B_SELECT_INPUT = 42U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_SCLK_SELECT_INPUT = 43U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_MISO_SELECT_INPUT = 44U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_MOSI_SELECT_INPUT = 45U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_SS0_B_SELECT_INPUT = 46U, /**< IOMUXC select input index */ + kIOMUXC_ENET1_REF_CLK1_SELECT_INPUT = 47U, /**< IOMUXC select input index */ + kIOMUXC_ENET1_MAC0_MDIO_SELECT_INPUT = 48U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_REF_CLK2_SELECT_INPUT = 49U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_MAC0_MDIO_SELECT_INPUT = 50U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 51U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 52U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_CAPTURE1_SELECT_INPUT = 53U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_CAPTURE2_SELECT_INPUT = 54U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_CLK_SELECT_INPUT = 55U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_CAPTURE1_SELECT_INPUT = 56U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_CAPTURE2_SELECT_INPUT = 57U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_CLK_SELECT_INPUT = 58U, /**< IOMUXC select input index */ + kIOMUXC_I2C1_SCL_SELECT_INPUT = 59U, /**< IOMUXC select input index */ + kIOMUXC_I2C1_SDA_SELECT_INPUT = 60U, /**< IOMUXC select input index */ + kIOMUXC_I2C2_SCL_SELECT_INPUT = 61U, /**< IOMUXC select input index */ + kIOMUXC_I2C2_SDA_SELECT_INPUT = 62U, /**< IOMUXC select input index */ + kIOMUXC_I2C3_SCL_SELECT_INPUT = 63U, /**< IOMUXC select input index */ + kIOMUXC_I2C3_SDA_SELECT_INPUT = 64U, /**< IOMUXC select input index */ + kIOMUXC_I2C4_SCL_SELECT_INPUT = 65U, /**< IOMUXC select input index */ + kIOMUXC_I2C4_SDA_SELECT_INPUT = 66U, /**< IOMUXC select input index */ + kIOMUXC_KPP_COL0_SELECT_INPUT = 67U, /**< IOMUXC select input index */ + kIOMUXC_KPP_COL1_SELECT_INPUT = 68U, /**< IOMUXC select input index */ + kIOMUXC_KPP_COL2_SELECT_INPUT = 69U, /**< IOMUXC select input index */ + kIOMUXC_KPP_ROW0_SELECT_INPUT = 70U, /**< IOMUXC select input index */ + kIOMUXC_KPP_ROW1_SELECT_INPUT = 71U, /**< IOMUXC select input index */ + kIOMUXC_KPP_ROW2_SELECT_INPUT = 72U, /**< IOMUXC select input index */ + kIOMUXC_LCD_BUSY_SELECT_INPUT = 73U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_MCLK_SELECT_INPUT = 74U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA_SELECT_INPUT = 75U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 76U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 77U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_MCLK_SELECT_INPUT = 78U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_DATA_SELECT_INPUT = 79U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 80U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 81U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_MCLK_SELECT_INPUT = 82U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_RX_DATA_SELECT_INPUT = 83U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_TX_BCLK_SELECT_INPUT = 84U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_TX_SYNC_SELECT_INPUT = 85U, /**< IOMUXC select input index */ + kIOMUXC_SDMA_EVENTS0_SELECT_INPUT = 86U, /**< IOMUXC select input index */ + kIOMUXC_SDMA_EVENTS1_SELECT_INPUT = 87U, /**< IOMUXC select input index */ + kIOMUXC_SPDIF_IN_SELECT_INPUT = 88U, /**< IOMUXC select input index */ + kIOMUXC_SPDIF_EXT_CLK_SELECT_INPUT = 89U, /**< IOMUXC select input index */ + kIOMUXC_UART1_RTS_B_SELECT_INPUT = 90U, /**< IOMUXC select input index */ + kIOMUXC_UART1_RX_DATA_SELECT_INPUT = 91U, /**< IOMUXC select input index */ + kIOMUXC_UART2_RTS_B_SELECT_INPUT = 92U, /**< IOMUXC select input index */ + kIOMUXC_UART2_RX_DATA_SELECT_INPUT = 93U, /**< IOMUXC select input index */ + kIOMUXC_UART3_RTS_B_SELECT_INPUT = 94U, /**< IOMUXC select input index */ + kIOMUXC_UART3_RX_DATA_SELECT_INPUT = 95U, /**< IOMUXC select input index */ + kIOMUXC_UART4_RTS_B_SELECT_INPUT = 96U, /**< IOMUXC select input index */ + kIOMUXC_UART4_RX_DATA_SELECT_INPUT = 97U, /**< IOMUXC select input index */ + kIOMUXC_UART5_RTS_B_SELECT_INPUT = 98U, /**< IOMUXC select input index */ + kIOMUXC_UART5_RX_DATA_SELECT_INPUT = 99U, /**< IOMUXC select input index */ + kIOMUXC_UART6_RTS_B_SELECT_INPUT = 100U, /**< IOMUXC select input index */ + kIOMUXC_UART6_RX_DATA_SELECT_INPUT = 101U, /**< IOMUXC select input index */ + kIOMUXC_UART7_RTS_B_SELECT_INPUT = 102U, /**< IOMUXC select input index */ + kIOMUXC_UART7_RX_DATA_SELECT_INPUT = 103U, /**< IOMUXC select input index */ + kIOMUXC_UART8_RTS_B_SELECT_INPUT = 104U, /**< IOMUXC select input index */ + kIOMUXC_UART8_RX_DATA_SELECT_INPUT = 105U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 106U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG_OC_SELECT_INPUT = 107U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 108U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_WP_SELECT_INPUT = 109U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CLK_SELECT_INPUT = 110U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 111U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CMD_SELECT_INPUT = 112U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 114U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 115U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 116U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 117U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 118U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 119U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 120U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */ +} iomuxc_select_input_t; + +/* @} */ + +/*! + * @brief Enumeration for the IOMUXC group + * + * Defines the enumeration for the IOMUXC group collections. + */ +typedef enum _iomuxc_grp +{ + kIOMUXC_SW_PAD_CTL_GRP_ADDDS = 0U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL = 1U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_B0DS = 2U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRPK = 3U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_CTLDS = 4U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_B1DS = 5U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRHYS = 6U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRPKE = 7U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRMODE = 8U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDR_TYPE = 9U, /**< IOMUXC group index */ +} iomuxc_grp_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_snvs_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC_SNVS SW_MUX_CTL_PAD + * + * Defines the enumeration for the IOMUXC_SNVS SW_MUX_CTL_PAD collections. + */ +typedef enum _iomuxc_snvs_sw_mux_ctl_pad +{ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_BOOT_MODE0 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_BOOT_MODE1 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER0 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER1 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER2 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER3 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER4 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER5 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER6 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER7 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER8 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER9 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ +} iomuxc_snvs_sw_mux_ctl_pad_t; + +/*! + * @addtogroup iomuxc_snvs_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC_SNVS SW_PAD_CTL_PAD + * + * Defines the enumeration for the IOMUXC_SNVS SW_PAD_CTL_PAD collections. + */ +typedef enum _iomuxc_snvs_sw_pad_ctl_pad +{ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_PMIC_ON_REQ = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_CCM_PMIC_STBY_REQ = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_BOOT_MODE0 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_BOOT_MODE1 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER0 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER1 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER2 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER3 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER4 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER5 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER6 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER7 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER8 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER9 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ +} iomuxc_snvs_sw_pad_ctl_pad_t; + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC[1]; /**< Control register, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __I uint32_t HS; /**< Status register, offset: 0x8 */ + __I uint32_t R[1]; /**< Data result register, array offset: 0xC, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CFG; /**< Configuration register, offset: 0x14 */ + __IO uint32_t GC; /**< General control register, offset: 0x18 */ + __IO uint32_t GS; /**< General status register, offset: 0x1C */ + __IO uint32_t CV; /**< Compare value register, offset: 0x20 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x24 */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x28 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name HC - Control register */ +#define ADC_HC_ADCH_MASK (0x1FU) +#define ADC_HC_ADCH_SHIFT (0U) +#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) +#define ADC_HC_AIEN_MASK (0x80U) +#define ADC_HC_AIEN_SHIFT (7U) +#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) + +/* The count of ADC_HC */ +#define ADC_HC_COUNT (1U) + +/*! @name HS - Status register */ +#define ADC_HS_COCO0_MASK (0x1U) +#define ADC_HS_COCO0_SHIFT (0U) +#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) + +/*! @name R - Data result register */ +#define ADC_R_CDATA_MASK (0xFFFU) +#define ADC_R_CDATA_SHIFT (0U) +#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) + +/* The count of ADC_R */ +#define ADC_R_COUNT (1U) + +/*! @name CFG - Configuration register */ +#define ADC_CFG_ADICLK_MASK (0x3U) +#define ADC_CFG_ADICLK_SHIFT (0U) +#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) +#define ADC_CFG_MODE_MASK (0xCU) +#define ADC_CFG_MODE_SHIFT (2U) +#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) +#define ADC_CFG_ADLSMP_MASK (0x10U) +#define ADC_CFG_ADLSMP_SHIFT (4U) +#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) +#define ADC_CFG_ADIV_MASK (0x60U) +#define ADC_CFG_ADIV_SHIFT (5U) +#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) +#define ADC_CFG_ADLPC_MASK (0x80U) +#define ADC_CFG_ADLPC_SHIFT (7U) +#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) +#define ADC_CFG_ADSTS_MASK (0x300U) +#define ADC_CFG_ADSTS_SHIFT (8U) +#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) +#define ADC_CFG_ADHSC_MASK (0x400U) +#define ADC_CFG_ADHSC_SHIFT (10U) +#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) +#define ADC_CFG_REFSEL_MASK (0x1800U) +#define ADC_CFG_REFSEL_SHIFT (11U) +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) +#define ADC_CFG_ADTRG_MASK (0x2000U) +#define ADC_CFG_ADTRG_SHIFT (13U) +#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) +#define ADC_CFG_AVGS_MASK (0xC000U) +#define ADC_CFG_AVGS_SHIFT (14U) +#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) +#define ADC_CFG_OVWREN_MASK (0x10000U) +#define ADC_CFG_OVWREN_SHIFT (16U) +#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) + +/*! @name GC - General control register */ +#define ADC_GC_ADACKEN_MASK (0x1U) +#define ADC_GC_ADACKEN_SHIFT (0U) +#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) +#define ADC_GC_DMAEN_MASK (0x2U) +#define ADC_GC_DMAEN_SHIFT (1U) +#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) +#define ADC_GC_ACREN_MASK (0x4U) +#define ADC_GC_ACREN_SHIFT (2U) +#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) +#define ADC_GC_ACFGT_MASK (0x8U) +#define ADC_GC_ACFGT_SHIFT (3U) +#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) +#define ADC_GC_ACFE_MASK (0x10U) +#define ADC_GC_ACFE_SHIFT (4U) +#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) +#define ADC_GC_AVGE_MASK (0x20U) +#define ADC_GC_AVGE_SHIFT (5U) +#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) +#define ADC_GC_ADCO_MASK (0x40U) +#define ADC_GC_ADCO_SHIFT (6U) +#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) +#define ADC_GC_CAL_MASK (0x80U) +#define ADC_GC_CAL_SHIFT (7U) +#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) + +/*! @name GS - General status register */ +#define ADC_GS_ADACT_MASK (0x1U) +#define ADC_GS_ADACT_SHIFT (0U) +#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) +#define ADC_GS_CALF_MASK (0x2U) +#define ADC_GS_CALF_SHIFT (1U) +#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) +#define ADC_GS_AWKST_MASK (0x4U) +#define ADC_GS_AWKST_SHIFT (2U) +#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) + +/*! @name CV - Compare value register */ +#define ADC_CV_CV1_MASK (0xFFFU) +#define ADC_CV_CV1_SHIFT (0U) +#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) +#define ADC_CV_CV2_MASK (0xFFF0000U) +#define ADC_CV_CV2_SHIFT (16U) +#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) + +/*! @name OFS - Offset correction value register */ +#define ADC_OFS_OFS_MASK (0xFFFU) +#define ADC_OFS_OFS_SHIFT (0U) +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) +#define ADC_OFS_SIGN_MASK (0x1000U) +#define ADC_OFS_SIGN_SHIFT (12U) +#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) + +/*! @name CAL - Calibration value register */ +#define ADC_CAL_CAL_CODE_MASK (0xFU) +#define ADC_CAL_CAL_CODE_SHIFT (0U) +#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x2198000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { 0u, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ADC_5HC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_5HC_Peripheral_Access_Layer ADC_5HC Peripheral Access Layer + * @{ + */ + +/** ADC_5HC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC[5]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */ + __I uint32_t HS; /**< Status register for HW triggers, offset: 0x14 */ + __I uint32_t R[5]; /**< Data result register for HW triggers, array offset: 0x18, array step: 0x4 */ + __IO uint32_t CFG; /**< Configuration register, offset: 0x2C */ + __IO uint32_t GC; /**< General control register, offset: 0x30 */ + __IO uint32_t GS; /**< General status register, offset: 0x34 */ + __IO uint32_t CV; /**< Compare value register, offset: 0x38 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x3C */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x40 */ +} ADC_5HC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC_5HC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_5HC_Register_Masks ADC_5HC Register Masks + * @{ + */ + +/*! @name HC - Control register for hardware triggers */ +#define ADC_5HC_HC_ADCH_MASK (0x1FU) +#define ADC_5HC_HC_ADCH_SHIFT (0U) +#define ADC_5HC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HC_ADCH_SHIFT)) & ADC_5HC_HC_ADCH_MASK) +#define ADC_5HC_HC_AIEN_MASK (0x80U) +#define ADC_5HC_HC_AIEN_SHIFT (7U) +#define ADC_5HC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HC_AIEN_SHIFT)) & ADC_5HC_HC_AIEN_MASK) + +/* The count of ADC_5HC_HC */ +#define ADC_5HC_HC_COUNT (5U) + +/*! @name HS - Status register for HW triggers */ +#define ADC_5HC_HS_COCO0_MASK (0x1U) +#define ADC_5HC_HS_COCO0_SHIFT (0U) +#define ADC_5HC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO0_SHIFT)) & ADC_5HC_HS_COCO0_MASK) +#define ADC_5HC_HS_COCO1_MASK (0x2U) +#define ADC_5HC_HS_COCO1_SHIFT (1U) +#define ADC_5HC_HS_COCO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO1_SHIFT)) & ADC_5HC_HS_COCO1_MASK) +#define ADC_5HC_HS_COCO2_MASK (0x4U) +#define ADC_5HC_HS_COCO2_SHIFT (2U) +#define ADC_5HC_HS_COCO2(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO2_SHIFT)) & ADC_5HC_HS_COCO2_MASK) +#define ADC_5HC_HS_COCO3_MASK (0x8U) +#define ADC_5HC_HS_COCO3_SHIFT (3U) +#define ADC_5HC_HS_COCO3(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO3_SHIFT)) & ADC_5HC_HS_COCO3_MASK) +#define ADC_5HC_HS_COCO4_MASK (0x10U) +#define ADC_5HC_HS_COCO4_SHIFT (4U) +#define ADC_5HC_HS_COCO4(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO4_SHIFT)) & ADC_5HC_HS_COCO4_MASK) + +/*! @name R - Data result register for HW triggers */ +#define ADC_5HC_R_CDATA_MASK (0xFFFU) +#define ADC_5HC_R_CDATA_SHIFT (0U) +#define ADC_5HC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_R_CDATA_SHIFT)) & ADC_5HC_R_CDATA_MASK) + +/* The count of ADC_5HC_R */ +#define ADC_5HC_R_COUNT (5U) + +/*! @name CFG - Configuration register */ +#define ADC_5HC_CFG_ADICLK_MASK (0x3U) +#define ADC_5HC_CFG_ADICLK_SHIFT (0U) +#define ADC_5HC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADICLK_SHIFT)) & ADC_5HC_CFG_ADICLK_MASK) +#define ADC_5HC_CFG_MODE_MASK (0xCU) +#define ADC_5HC_CFG_MODE_SHIFT (2U) +#define ADC_5HC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_MODE_SHIFT)) & ADC_5HC_CFG_MODE_MASK) +#define ADC_5HC_CFG_ADLSMP_MASK (0x10U) +#define ADC_5HC_CFG_ADLSMP_SHIFT (4U) +#define ADC_5HC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADLSMP_SHIFT)) & ADC_5HC_CFG_ADLSMP_MASK) +#define ADC_5HC_CFG_ADIV_MASK (0x60U) +#define ADC_5HC_CFG_ADIV_SHIFT (5U) +#define ADC_5HC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADIV_SHIFT)) & ADC_5HC_CFG_ADIV_MASK) +#define ADC_5HC_CFG_ADLPC_MASK (0x80U) +#define ADC_5HC_CFG_ADLPC_SHIFT (7U) +#define ADC_5HC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADLPC_SHIFT)) & ADC_5HC_CFG_ADLPC_MASK) +#define ADC_5HC_CFG_ADSTS_MASK (0x300U) +#define ADC_5HC_CFG_ADSTS_SHIFT (8U) +#define ADC_5HC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADSTS_SHIFT)) & ADC_5HC_CFG_ADSTS_MASK) +#define ADC_5HC_CFG_ADHSC_MASK (0x400U) +#define ADC_5HC_CFG_ADHSC_SHIFT (10U) +#define ADC_5HC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADHSC_SHIFT)) & ADC_5HC_CFG_ADHSC_MASK) +#define ADC_5HC_CFG_REFSEL_MASK (0x1800U) +#define ADC_5HC_CFG_REFSEL_SHIFT (11U) +#define ADC_5HC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_REFSEL_SHIFT)) & ADC_5HC_CFG_REFSEL_MASK) +#define ADC_5HC_CFG_ADTRG_MASK (0x2000U) +#define ADC_5HC_CFG_ADTRG_SHIFT (13U) +#define ADC_5HC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADTRG_SHIFT)) & ADC_5HC_CFG_ADTRG_MASK) +#define ADC_5HC_CFG_AVGS_MASK (0xC000U) +#define ADC_5HC_CFG_AVGS_SHIFT (14U) +#define ADC_5HC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_AVGS_SHIFT)) & ADC_5HC_CFG_AVGS_MASK) +#define ADC_5HC_CFG_OVWREN_MASK (0x10000U) +#define ADC_5HC_CFG_OVWREN_SHIFT (16U) +#define ADC_5HC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_OVWREN_SHIFT)) & ADC_5HC_CFG_OVWREN_MASK) + +/*! @name GC - General control register */ +#define ADC_5HC_GC_ADACKEN_MASK (0x1U) +#define ADC_5HC_GC_ADACKEN_SHIFT (0U) +#define ADC_5HC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ADACKEN_SHIFT)) & ADC_5HC_GC_ADACKEN_MASK) +#define ADC_5HC_GC_DMAEN_MASK (0x2U) +#define ADC_5HC_GC_DMAEN_SHIFT (1U) +#define ADC_5HC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_DMAEN_SHIFT)) & ADC_5HC_GC_DMAEN_MASK) +#define ADC_5HC_GC_ACREN_MASK (0x4U) +#define ADC_5HC_GC_ACREN_SHIFT (2U) +#define ADC_5HC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ACREN_SHIFT)) & ADC_5HC_GC_ACREN_MASK) +#define ADC_5HC_GC_ACFGT_MASK (0x8U) +#define ADC_5HC_GC_ACFGT_SHIFT (3U) +#define ADC_5HC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ACFGT_SHIFT)) & ADC_5HC_GC_ACFGT_MASK) +#define ADC_5HC_GC_ACFE_MASK (0x10U) +#define ADC_5HC_GC_ACFE_SHIFT (4U) +#define ADC_5HC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ACFE_SHIFT)) & ADC_5HC_GC_ACFE_MASK) +#define ADC_5HC_GC_AVGE_MASK (0x20U) +#define ADC_5HC_GC_AVGE_SHIFT (5U) +#define ADC_5HC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_AVGE_SHIFT)) & ADC_5HC_GC_AVGE_MASK) +#define ADC_5HC_GC_ADCO_MASK (0x40U) +#define ADC_5HC_GC_ADCO_SHIFT (6U) +#define ADC_5HC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ADCO_SHIFT)) & ADC_5HC_GC_ADCO_MASK) +#define ADC_5HC_GC_CAL_MASK (0x80U) +#define ADC_5HC_GC_CAL_SHIFT (7U) +#define ADC_5HC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_CAL_SHIFT)) & ADC_5HC_GC_CAL_MASK) + +/*! @name GS - General status register */ +#define ADC_5HC_GS_ADACT_MASK (0x1U) +#define ADC_5HC_GS_ADACT_SHIFT (0U) +#define ADC_5HC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GS_ADACT_SHIFT)) & ADC_5HC_GS_ADACT_MASK) +#define ADC_5HC_GS_CALF_MASK (0x2U) +#define ADC_5HC_GS_CALF_SHIFT (1U) +#define ADC_5HC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GS_CALF_SHIFT)) & ADC_5HC_GS_CALF_MASK) +#define ADC_5HC_GS_AWKST_MASK (0x4U) +#define ADC_5HC_GS_AWKST_SHIFT (2U) +#define ADC_5HC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GS_AWKST_SHIFT)) & ADC_5HC_GS_AWKST_MASK) + +/*! @name CV - Compare value register */ +#define ADC_5HC_CV_CV1_MASK (0xFFFU) +#define ADC_5HC_CV_CV1_SHIFT (0U) +#define ADC_5HC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CV_CV1_SHIFT)) & ADC_5HC_CV_CV1_MASK) +#define ADC_5HC_CV_CV2_MASK (0xFFF0000U) +#define ADC_5HC_CV_CV2_SHIFT (16U) +#define ADC_5HC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CV_CV2_SHIFT)) & ADC_5HC_CV_CV2_MASK) + +/*! @name OFS - Offset correction value register */ +#define ADC_5HC_OFS_OFS_MASK (0xFFFU) +#define ADC_5HC_OFS_OFS_SHIFT (0U) +#define ADC_5HC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_OFS_OFS_SHIFT)) & ADC_5HC_OFS_OFS_MASK) +#define ADC_5HC_OFS_SIGN_MASK (0x1000U) +#define ADC_5HC_OFS_SIGN_SHIFT (12U) +#define ADC_5HC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_OFS_SIGN_SHIFT)) & ADC_5HC_OFS_SIGN_MASK) + +/*! @name CAL - Calibration value register */ +#define ADC_5HC_CAL_CAL_CODE_MASK (0xFU) +#define ADC_5HC_CAL_CAL_CODE_SHIFT (0U) +#define ADC_5HC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CAL_CAL_CODE_SHIFT)) & ADC_5HC_CAL_CAL_CODE_MASK) + + +/*! + * @} + */ /* end of group ADC_5HC_Register_Masks */ + + +/* ADC_5HC - Peripheral instance base addresses */ +/** Peripheral ADC_5HC base address */ +#define ADC_5HC_BASE (0x219C000u) +/** Peripheral ADC_5HC base pointer */ +#define ADC_5HC ((ADC_5HC_Type *)ADC_5HC_BASE) +/** Array initializer of ADC_5HC peripheral base addresses */ +#define ADC_5HC_BASE_ADDRS { ADC_5HC_BASE } +/** Array initializer of ADC_5HC peripheral base pointers */ +#define ADC_5HC_BASE_PTRS { ADC_5HC } +/** Interrupt vectors for the ADC_5HC peripheral type */ +#define ADC_5HC_IRQS { ADC_5HC_IRQn } + +/*! + * @} + */ /* end of group ADC_5HC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer + * @{ + */ + +/** AIPSTZ - Register Layout Typedef */ +typedef struct { + __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */ + __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */ + __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */ + __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */ + __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */ +} AIPSTZ_Type; + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks + * @{ + */ + +/*! @name MPR - Master Priviledge Registers */ +#define AIPSTZ_MPR_MPROT5_MASK (0xF00U) +#define AIPSTZ_MPR_MPROT5_SHIFT (8U) +#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) +#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) +#define AIPSTZ_MPR_MPROT3_SHIFT (16U) +#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) +#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) +#define AIPSTZ_MPR_MPROT2_SHIFT (20U) +#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) +#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) +#define AIPSTZ_MPR_MPROT1_SHIFT (24U) +#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) +#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) +#define AIPSTZ_MPR_MPROT0_SHIFT (28U) +#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) + +/*! @name OPACR - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR_OPAC7_MASK (0xFU) +#define AIPSTZ_OPACR_OPAC7_SHIFT (0U) +#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) +#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) +#define AIPSTZ_OPACR_OPAC6_SHIFT (4U) +#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) +#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) +#define AIPSTZ_OPACR_OPAC5_SHIFT (8U) +#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) +#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) +#define AIPSTZ_OPACR_OPAC4_SHIFT (12U) +#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) +#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) +#define AIPSTZ_OPACR_OPAC3_SHIFT (16U) +#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) +#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) +#define AIPSTZ_OPACR_OPAC2_SHIFT (20U) +#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) +#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) +#define AIPSTZ_OPACR_OPAC1_SHIFT (24U) +#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) +#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) +#define AIPSTZ_OPACR_OPAC0_SHIFT (28U) +#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) + +/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) +#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) +#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) +#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) +#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) +#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) +#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) +#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) +#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) +#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) +#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) +#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) +#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) +#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) +#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) +#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) +#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) +#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) +#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) +#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) +#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) +#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) +#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) +#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) + +/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) +#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) +#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) +#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) +#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) +#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) +#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) +#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) +#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) +#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) +#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) +#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) +#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) +#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) +#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) +#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) +#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) +#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) +#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) +#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) +#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) +#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) +#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) +#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) + +/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) +#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) +#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) +#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) +#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) +#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) +#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) +#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) +#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) +#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) +#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) +#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) +#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) +#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) +#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) +#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) +#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) +#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) +#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) +#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) +#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) +#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) +#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) +#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) + +/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) +#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) +#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) +#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) +#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) +#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) + + +/*! + * @} + */ /* end of group AIPSTZ_Register_Masks */ + + +/* AIPSTZ - Peripheral instance base addresses */ +/** Peripheral AIPSTZ1 base address */ +#define AIPSTZ1_BASE (0x207C000u) +/** Peripheral AIPSTZ1 base pointer */ +#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) +/** Peripheral AIPSTZ2 base address */ +#define AIPSTZ2_BASE (0x217C000u) +/** Peripheral AIPSTZ2 base pointer */ +#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) +/** Peripheral AIPSTZ3 base address */ +#define AIPSTZ3_BASE (0x227C000u) +/** Peripheral AIPSTZ3 base pointer */ +#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) +/** Array initializer of AIPSTZ peripheral base addresses */ +#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE } +/** Array initializer of AIPSTZ peripheral base pointers */ +#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3 } + +/*! + * @} + */ /* end of group AIPSTZ_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- APBH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer + * @{ + */ + +/** APBH - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */ + __IO uint32_t CTRL0_SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */ + __IO uint32_t CTRL0_CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */ + __IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */ + __IO uint32_t CTRL1; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */ + __IO uint32_t CTRL2; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */ + __IO uint32_t CHANNEL_CTRL; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */ + __IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */ + __IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */ + __IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */ + __I uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */ + uint8_t RESERVED_2[156]; + __I uint32_t CH0_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x100 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CH0_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x110 */ + uint8_t RESERVED_4[12]; + __I uint32_t CH0_CMD; /**< APBH DMA Channel n Command Register, offset: 0x120 */ + uint8_t RESERVED_5[12]; + __I uint32_t CH0_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x130 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CH0_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x140 */ + uint8_t RESERVED_7[12]; + __I uint32_t CH0_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x150 */ + uint8_t RESERVED_8[12]; + __I uint32_t CH0_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x160 */ + uint8_t RESERVED_9[12]; + __I uint32_t CH1_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x170 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CH1_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x180 */ + uint8_t RESERVED_11[12]; + __I uint32_t CH1_CMD; /**< APBH DMA Channel n Command Register, offset: 0x190 */ + uint8_t RESERVED_12[12]; + __I uint32_t CH1_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x1A0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CH1_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x1B0 */ + uint8_t RESERVED_14[12]; + __I uint32_t CH1_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1C0 */ + uint8_t RESERVED_15[12]; + __I uint32_t CH1_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1D0 */ + uint8_t RESERVED_16[12]; + __I uint32_t CH2_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x1E0 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CH2_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x1F0 */ + uint8_t RESERVED_18[12]; + __I uint32_t CH2_CMD; /**< APBH DMA Channel n Command Register, offset: 0x200 */ + uint8_t RESERVED_19[12]; + __I uint32_t CH2_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x210 */ + uint8_t RESERVED_20[12]; + __IO uint32_t CH2_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x220 */ + uint8_t RESERVED_21[12]; + __I uint32_t CH2_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x230 */ + uint8_t RESERVED_22[12]; + __I uint32_t CH2_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x240 */ + uint8_t RESERVED_23[12]; + __I uint32_t CH3_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x250 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CH3_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x260 */ + uint8_t RESERVED_25[12]; + __I uint32_t CH3_CMD; /**< APBH DMA Channel n Command Register, offset: 0x270 */ + uint8_t RESERVED_26[12]; + __I uint32_t CH3_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x280 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CH3_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x290 */ + uint8_t RESERVED_28[12]; + __I uint32_t CH3_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2A0 */ + uint8_t RESERVED_29[12]; + __I uint32_t CH3_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2B0 */ + uint8_t RESERVED_30[12]; + __I uint32_t CH4_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x2C0 */ + uint8_t RESERVED_31[12]; + __IO uint32_t CH4_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x2D0 */ + uint8_t RESERVED_32[12]; + __I uint32_t CH4_CMD; /**< APBH DMA Channel n Command Register, offset: 0x2E0 */ + uint8_t RESERVED_33[12]; + __I uint32_t CH4_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x2F0 */ + uint8_t RESERVED_34[12]; + __IO uint32_t CH4_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x300 */ + uint8_t RESERVED_35[12]; + __I uint32_t CH4_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x310 */ + uint8_t RESERVED_36[12]; + __I uint32_t CH4_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x320 */ + uint8_t RESERVED_37[12]; + __I uint32_t CH5_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x330 */ + uint8_t RESERVED_38[12]; + __IO uint32_t CH5_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x340 */ + uint8_t RESERVED_39[12]; + __I uint32_t CH5_CMD; /**< APBH DMA Channel n Command Register, offset: 0x350 */ + uint8_t RESERVED_40[12]; + __I uint32_t CH5_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x360 */ + uint8_t RESERVED_41[12]; + __IO uint32_t CH5_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x370 */ + uint8_t RESERVED_42[12]; + __I uint32_t CH5_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x380 */ + uint8_t RESERVED_43[12]; + __I uint32_t CH5_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x390 */ + uint8_t RESERVED_44[12]; + __I uint32_t CH6_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x3A0 */ + uint8_t RESERVED_45[12]; + __IO uint32_t CH6_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x3B0 */ + uint8_t RESERVED_46[12]; + __I uint32_t CH6_CMD; /**< APBH DMA Channel n Command Register, offset: 0x3C0 */ + uint8_t RESERVED_47[12]; + __I uint32_t CH6_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x3D0 */ + uint8_t RESERVED_48[12]; + __IO uint32_t CH6_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x3E0 */ + uint8_t RESERVED_49[12]; + __I uint32_t CH6_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x3F0 */ + uint8_t RESERVED_50[12]; + __I uint32_t CH6_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x400 */ + uint8_t RESERVED_51[12]; + __I uint32_t CH7_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x410 */ + uint8_t RESERVED_52[12]; + __IO uint32_t CH7_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x420 */ + uint8_t RESERVED_53[12]; + __I uint32_t CH7_CMD; /**< APBH DMA Channel n Command Register, offset: 0x430 */ + uint8_t RESERVED_54[12]; + __I uint32_t CH7_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x440 */ + uint8_t RESERVED_55[12]; + __IO uint32_t CH7_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x450 */ + uint8_t RESERVED_56[12]; + __I uint32_t CH7_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x460 */ + uint8_t RESERVED_57[12]; + __I uint32_t CH7_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x470 */ + uint8_t RESERVED_58[12]; + __I uint32_t CH8_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x480 */ + uint8_t RESERVED_59[12]; + __IO uint32_t CH8_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x490 */ + uint8_t RESERVED_60[12]; + __I uint32_t CH8_CMD; /**< APBH DMA Channel n Command Register, offset: 0x4A0 */ + uint8_t RESERVED_61[12]; + __I uint32_t CH8_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x4B0 */ + uint8_t RESERVED_62[12]; + __IO uint32_t CH8_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x4C0 */ + uint8_t RESERVED_63[12]; + __I uint32_t CH8_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4D0 */ + uint8_t RESERVED_64[12]; + __I uint32_t CH8_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4E0 */ + uint8_t RESERVED_65[12]; + __I uint32_t CH9_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x4F0 */ + uint8_t RESERVED_66[12]; + __IO uint32_t CH9_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x500 */ + uint8_t RESERVED_67[12]; + __I uint32_t CH9_CMD; /**< APBH DMA Channel n Command Register, offset: 0x510 */ + uint8_t RESERVED_68[12]; + __I uint32_t CH9_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x520 */ + uint8_t RESERVED_69[12]; + __IO uint32_t CH9_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x530 */ + uint8_t RESERVED_70[12]; + __I uint32_t CH9_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x540 */ + uint8_t RESERVED_71[12]; + __I uint32_t CH9_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x550 */ + uint8_t RESERVED_72[12]; + __I uint32_t CH10_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x560 */ + uint8_t RESERVED_73[12]; + __IO uint32_t CH10_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x570 */ + uint8_t RESERVED_74[12]; + __I uint32_t CH10_CMD; /**< APBH DMA Channel n Command Register, offset: 0x580 */ + uint8_t RESERVED_75[12]; + __I uint32_t CH10_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x590 */ + uint8_t RESERVED_76[12]; + __IO uint32_t CH10_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x5A0 */ + uint8_t RESERVED_77[12]; + __I uint32_t CH10_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5B0 */ + uint8_t RESERVED_78[12]; + __I uint32_t CH10_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5C0 */ + uint8_t RESERVED_79[12]; + __I uint32_t CH11_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x5D0 */ + uint8_t RESERVED_80[12]; + __IO uint32_t CH11_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x5E0 */ + uint8_t RESERVED_81[12]; + __I uint32_t CH11_CMD; /**< APBH DMA Channel n Command Register, offset: 0x5F0 */ + uint8_t RESERVED_82[12]; + __I uint32_t CH11_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x600 */ + uint8_t RESERVED_83[12]; + __IO uint32_t CH11_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x610 */ + uint8_t RESERVED_84[12]; + __I uint32_t CH11_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x620 */ + uint8_t RESERVED_85[12]; + __I uint32_t CH11_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x630 */ + uint8_t RESERVED_86[12]; + __I uint32_t CH12_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x640 */ + uint8_t RESERVED_87[12]; + __IO uint32_t CH12_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x650 */ + uint8_t RESERVED_88[12]; + __I uint32_t CH12_CMD; /**< APBH DMA Channel n Command Register, offset: 0x660 */ + uint8_t RESERVED_89[12]; + __I uint32_t CH12_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x670 */ + uint8_t RESERVED_90[12]; + __IO uint32_t CH12_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x680 */ + uint8_t RESERVED_91[12]; + __I uint32_t CH12_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x690 */ + uint8_t RESERVED_92[12]; + __I uint32_t CH12_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x6A0 */ + uint8_t RESERVED_93[12]; + __I uint32_t CH13_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x6B0 */ + uint8_t RESERVED_94[12]; + __IO uint32_t CH13_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x6C0 */ + uint8_t RESERVED_95[12]; + __I uint32_t CH13_CMD; /**< APBH DMA Channel n Command Register, offset: 0x6D0 */ + uint8_t RESERVED_96[12]; + __I uint32_t CH13_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x6E0 */ + uint8_t RESERVED_97[12]; + __IO uint32_t CH13_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x6F0 */ + uint8_t RESERVED_98[12]; + __I uint32_t CH13_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x700 */ + uint8_t RESERVED_99[12]; + __I uint32_t CH13_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x710 */ + uint8_t RESERVED_100[12]; + __I uint32_t CH14_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x720 */ + uint8_t RESERVED_101[12]; + __IO uint32_t CH14_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x730 */ + uint8_t RESERVED_102[12]; + __I uint32_t CH14_CMD; /**< APBH DMA Channel n Command Register, offset: 0x740 */ + uint8_t RESERVED_103[12]; + __I uint32_t CH14_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x750 */ + uint8_t RESERVED_104[12]; + __IO uint32_t CH14_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x760 */ + uint8_t RESERVED_105[12]; + __I uint32_t CH14_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x770 */ + uint8_t RESERVED_106[12]; + __I uint32_t CH14_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x780 */ + uint8_t RESERVED_107[12]; + __I uint32_t CH15_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x790 */ + uint8_t RESERVED_108[12]; + __IO uint32_t CH15_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x7A0 */ + uint8_t RESERVED_109[12]; + __I uint32_t CH15_CMD; /**< APBH DMA Channel n Command Register, offset: 0x7B0 */ + uint8_t RESERVED_110[12]; + __I uint32_t CH15_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x7C0 */ + uint8_t RESERVED_111[12]; + __IO uint32_t CH15_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x7D0 */ + uint8_t RESERVED_112[12]; + __I uint32_t CH15_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7E0 */ + uint8_t RESERVED_113[12]; + __I uint32_t CH15_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7F0 */ + uint8_t RESERVED_114[12]; + __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */ +} APBH_Type; + +/* ---------------------------------------------------------------------------- + -- APBH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Register_Masks APBH Register Masks + * @{ + */ + +/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_RSVD0_SHIFT (16U) +#define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK) +#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK) +#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK) +#define APBH_CTRL0_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_SFTRST_SHIFT (31U) +#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK) + +/*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_SET_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_SET_RSVD0_SHIFT (16U) +#define APBH_CTRL0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK) +#define APBH_CTRL0_SET_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_SET_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_SET_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK) +#define APBH_CTRL0_SET_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_SET_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_SET_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_SET_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK) +#define APBH_CTRL0_SET_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_SET_SFTRST_SHIFT (31U) +#define APBH_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK) + +/*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_CLR_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_CLR_RSVD0_SHIFT (16U) +#define APBH_CTRL0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK) +#define APBH_CTRL0_CLR_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_CLR_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK) +#define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_CLR_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_CLR_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_CLR_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK) +#define APBH_CTRL0_CLR_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_CLR_SFTRST_SHIFT (31U) +#define APBH_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK) + +/*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_TOG_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_TOG_RSVD0_SHIFT (16U) +#define APBH_CTRL0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK) +#define APBH_CTRL0_TOG_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_TOG_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK) +#define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_TOG_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_TOG_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_TOG_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK) +#define APBH_CTRL0_TOG_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_TOG_SFTRST_SHIFT (31U) +#define APBH_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK) + +/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK) + +/*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_SET_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_SET_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_SET_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_SET_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_SET_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_SET_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_SET_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_SET_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_SET_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_SET_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_SET_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_SET_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_SET_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_SET_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_SET_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_SET_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_SET_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_SET_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_SET_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_SET_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_SET_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_SET_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_SET_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_SET_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_SET_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_SET_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_SET_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_SET_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_SET_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_SET_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_SET_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_SET_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK) + +/*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK) + +/*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK) + +/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK) + +/*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK) + +/*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK) + +/*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK) + +/*! @name DEVSEL - AHB to APBH DMA Device Assignment Register */ +#define APBH_DEVSEL_CH0_MASK (0x3U) +#define APBH_DEVSEL_CH0_SHIFT (0U) +#define APBH_DEVSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH0_SHIFT)) & APBH_DEVSEL_CH0_MASK) +#define APBH_DEVSEL_CH1_MASK (0xCU) +#define APBH_DEVSEL_CH1_SHIFT (2U) +#define APBH_DEVSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH1_SHIFT)) & APBH_DEVSEL_CH1_MASK) +#define APBH_DEVSEL_CH2_MASK (0x30U) +#define APBH_DEVSEL_CH2_SHIFT (4U) +#define APBH_DEVSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH2_SHIFT)) & APBH_DEVSEL_CH2_MASK) +#define APBH_DEVSEL_CH3_MASK (0xC0U) +#define APBH_DEVSEL_CH3_SHIFT (6U) +#define APBH_DEVSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH3_SHIFT)) & APBH_DEVSEL_CH3_MASK) +#define APBH_DEVSEL_CH4_MASK (0x300U) +#define APBH_DEVSEL_CH4_SHIFT (8U) +#define APBH_DEVSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH4_SHIFT)) & APBH_DEVSEL_CH4_MASK) +#define APBH_DEVSEL_CH5_MASK (0xC00U) +#define APBH_DEVSEL_CH5_SHIFT (10U) +#define APBH_DEVSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH5_SHIFT)) & APBH_DEVSEL_CH5_MASK) +#define APBH_DEVSEL_CH6_MASK (0x3000U) +#define APBH_DEVSEL_CH6_SHIFT (12U) +#define APBH_DEVSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH6_SHIFT)) & APBH_DEVSEL_CH6_MASK) +#define APBH_DEVSEL_CH7_MASK (0xC000U) +#define APBH_DEVSEL_CH7_SHIFT (14U) +#define APBH_DEVSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH7_SHIFT)) & APBH_DEVSEL_CH7_MASK) +#define APBH_DEVSEL_CH8_MASK (0x30000U) +#define APBH_DEVSEL_CH8_SHIFT (16U) +#define APBH_DEVSEL_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH8_SHIFT)) & APBH_DEVSEL_CH8_MASK) +#define APBH_DEVSEL_CH9_MASK (0xC0000U) +#define APBH_DEVSEL_CH9_SHIFT (18U) +#define APBH_DEVSEL_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH9_SHIFT)) & APBH_DEVSEL_CH9_MASK) +#define APBH_DEVSEL_CH10_MASK (0x300000U) +#define APBH_DEVSEL_CH10_SHIFT (20U) +#define APBH_DEVSEL_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH10_SHIFT)) & APBH_DEVSEL_CH10_MASK) +#define APBH_DEVSEL_CH11_MASK (0xC00000U) +#define APBH_DEVSEL_CH11_SHIFT (22U) +#define APBH_DEVSEL_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH11_SHIFT)) & APBH_DEVSEL_CH11_MASK) +#define APBH_DEVSEL_CH12_MASK (0x3000000U) +#define APBH_DEVSEL_CH12_SHIFT (24U) +#define APBH_DEVSEL_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH12_SHIFT)) & APBH_DEVSEL_CH12_MASK) +#define APBH_DEVSEL_CH13_MASK (0xC000000U) +#define APBH_DEVSEL_CH13_SHIFT (26U) +#define APBH_DEVSEL_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH13_SHIFT)) & APBH_DEVSEL_CH13_MASK) +#define APBH_DEVSEL_CH14_MASK (0x30000000U) +#define APBH_DEVSEL_CH14_SHIFT (28U) +#define APBH_DEVSEL_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH14_SHIFT)) & APBH_DEVSEL_CH14_MASK) +#define APBH_DEVSEL_CH15_MASK (0xC0000000U) +#define APBH_DEVSEL_CH15_SHIFT (30U) +#define APBH_DEVSEL_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH15_SHIFT)) & APBH_DEVSEL_CH15_MASK) + +/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */ +#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U) +#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U) +#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK) +#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU) +#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U) +#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK) +#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U) +#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U) +#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK) +#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U) +#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U) +#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK) +#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U) +#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U) +#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK) +#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U) +#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U) +#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK) +#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U) +#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U) +#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK) +#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U) +#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U) +#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK) +#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U) +#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U) +#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK) +#define APBH_DMA_BURST_SIZE_CH9_MASK (0xC0000U) +#define APBH_DMA_BURST_SIZE_CH9_SHIFT (18U) +#define APBH_DMA_BURST_SIZE_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH9_SHIFT)) & APBH_DMA_BURST_SIZE_CH9_MASK) +#define APBH_DMA_BURST_SIZE_CH10_MASK (0x300000U) +#define APBH_DMA_BURST_SIZE_CH10_SHIFT (20U) +#define APBH_DMA_BURST_SIZE_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH10_SHIFT)) & APBH_DMA_BURST_SIZE_CH10_MASK) +#define APBH_DMA_BURST_SIZE_CH11_MASK (0xC00000U) +#define APBH_DMA_BURST_SIZE_CH11_SHIFT (22U) +#define APBH_DMA_BURST_SIZE_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH11_SHIFT)) & APBH_DMA_BURST_SIZE_CH11_MASK) +#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3000000U) +#define APBH_DMA_BURST_SIZE_CH12_SHIFT (24U) +#define APBH_DMA_BURST_SIZE_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH12_SHIFT)) & APBH_DMA_BURST_SIZE_CH12_MASK) +#define APBH_DMA_BURST_SIZE_CH13_MASK (0xC000000U) +#define APBH_DMA_BURST_SIZE_CH13_SHIFT (26U) +#define APBH_DMA_BURST_SIZE_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH13_SHIFT)) & APBH_DMA_BURST_SIZE_CH13_MASK) +#define APBH_DMA_BURST_SIZE_CH14_MASK (0x30000000U) +#define APBH_DMA_BURST_SIZE_CH14_SHIFT (28U) +#define APBH_DMA_BURST_SIZE_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH14_SHIFT)) & APBH_DMA_BURST_SIZE_CH14_MASK) +#define APBH_DMA_BURST_SIZE_CH15_MASK (0xC0000000U) +#define APBH_DMA_BURST_SIZE_CH15_SHIFT (30U) +#define APBH_DMA_BURST_SIZE_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH15_SHIFT)) & APBH_DMA_BURST_SIZE_CH15_MASK) + +/*! @name DEBUG - AHB to APBH DMA Debug Register */ +#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U) +#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U) +#define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK) + +/*! @name CH0_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH0_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH0_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH0_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH0_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH0_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH0_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH0_CMD_COMMAND_MASK (0x3U) +#define APBH_CH0_CMD_COMMAND_SHIFT (0U) +#define APBH_CH0_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_COMMAND_SHIFT)) & APBH_CH0_CMD_COMMAND_MASK) +#define APBH_CH0_CMD_CHAIN_MASK (0x4U) +#define APBH_CH0_CMD_CHAIN_SHIFT (2U) +#define APBH_CH0_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CHAIN_SHIFT)) & APBH_CH0_CMD_CHAIN_MASK) +#define APBH_CH0_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH0_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH0_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_IRQONCMPLT_SHIFT)) & APBH_CH0_CMD_IRQONCMPLT_MASK) +#define APBH_CH0_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH0_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH0_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDLOCK_SHIFT)) & APBH_CH0_CMD_NANDLOCK_MASK) +#define APBH_CH0_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH0_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH0_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH0_CMD_NANDWAIT4READY_MASK) +#define APBH_CH0_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH0_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH0_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_SEMAPHORE_SHIFT)) & APBH_CH0_CMD_SEMAPHORE_MASK) +#define APBH_CH0_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH0_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH0_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH0_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH0_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH0_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH0_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH0_CMD_HALTONTERMINATE_MASK) +#define APBH_CH0_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH0_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH0_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CMDWORDS_SHIFT)) & APBH_CH0_CMD_CMDWORDS_MASK) +#define APBH_CH0_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH0_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH0_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_XFER_COUNT_SHIFT)) & APBH_CH0_CMD_XFER_COUNT_MASK) + +/*! @name CH0_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH0_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH0_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH0_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_BAR_ADDRESS_SHIFT)) & APBH_CH0_BAR_ADDRESS_MASK) + +/*! @name CH0_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH0_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH0_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH0_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH0_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH0_SEMA_PHORE_SHIFT (16U) +#define APBH_CH0_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_PHORE_SHIFT)) & APBH_CH0_SEMA_PHORE_MASK) + +/*! @name CH0_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH0_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH0_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH0_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH0_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH0_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH0_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH0_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RSVD1_SHIFT)) & APBH_CH0_DEBUG1_RSVD1_MASK) +#define APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH0_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH0_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH0_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH0_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH0_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_LOCK_SHIFT)) & APBH_CH0_DEBUG1_LOCK_MASK) +#define APBH_CH0_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH0_DEBUG1_READY_SHIFT (26U) +#define APBH_CH0_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_READY_SHIFT)) & APBH_CH0_DEBUG1_READY_MASK) +#define APBH_CH0_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH0_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH0_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_SENSE_SHIFT)) & APBH_CH0_DEBUG1_SENSE_MASK) +#define APBH_CH0_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH0_DEBUG1_END_SHIFT (28U) +#define APBH_CH0_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_END_SHIFT)) & APBH_CH0_DEBUG1_END_MASK) +#define APBH_CH0_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH0_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH0_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_KICK_SHIFT)) & APBH_CH0_DEBUG1_KICK_MASK) +#define APBH_CH0_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH0_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH0_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_BURST_SHIFT)) & APBH_CH0_DEBUG1_BURST_MASK) +#define APBH_CH0_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH0_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH0_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_REQ_SHIFT)) & APBH_CH0_DEBUG1_REQ_MASK) + +/*! @name CH0_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH0_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH0_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH0_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH0_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH0_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH0_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_APB_BYTES_MASK) + +/*! @name CH1_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH1_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH1_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH1_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH1_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH1_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH1_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH1_CMD_COMMAND_MASK (0x3U) +#define APBH_CH1_CMD_COMMAND_SHIFT (0U) +#define APBH_CH1_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_COMMAND_SHIFT)) & APBH_CH1_CMD_COMMAND_MASK) +#define APBH_CH1_CMD_CHAIN_MASK (0x4U) +#define APBH_CH1_CMD_CHAIN_SHIFT (2U) +#define APBH_CH1_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CHAIN_SHIFT)) & APBH_CH1_CMD_CHAIN_MASK) +#define APBH_CH1_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH1_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH1_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_IRQONCMPLT_SHIFT)) & APBH_CH1_CMD_IRQONCMPLT_MASK) +#define APBH_CH1_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH1_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH1_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDLOCK_SHIFT)) & APBH_CH1_CMD_NANDLOCK_MASK) +#define APBH_CH1_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH1_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH1_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH1_CMD_NANDWAIT4READY_MASK) +#define APBH_CH1_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH1_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH1_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_SEMAPHORE_SHIFT)) & APBH_CH1_CMD_SEMAPHORE_MASK) +#define APBH_CH1_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH1_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH1_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH1_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH1_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH1_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH1_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH1_CMD_HALTONTERMINATE_MASK) +#define APBH_CH1_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH1_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH1_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CMDWORDS_SHIFT)) & APBH_CH1_CMD_CMDWORDS_MASK) +#define APBH_CH1_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH1_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH1_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_XFER_COUNT_SHIFT)) & APBH_CH1_CMD_XFER_COUNT_MASK) + +/*! @name CH1_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH1_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH1_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH1_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_BAR_ADDRESS_SHIFT)) & APBH_CH1_BAR_ADDRESS_MASK) + +/*! @name CH1_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH1_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH1_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH1_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH1_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH1_SEMA_PHORE_SHIFT (16U) +#define APBH_CH1_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_PHORE_SHIFT)) & APBH_CH1_SEMA_PHORE_MASK) + +/*! @name CH1_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH1_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH1_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH1_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH1_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH1_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH1_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH1_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RSVD1_SHIFT)) & APBH_CH1_DEBUG1_RSVD1_MASK) +#define APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH1_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH1_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH1_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH1_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH1_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_LOCK_SHIFT)) & APBH_CH1_DEBUG1_LOCK_MASK) +#define APBH_CH1_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH1_DEBUG1_READY_SHIFT (26U) +#define APBH_CH1_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_READY_SHIFT)) & APBH_CH1_DEBUG1_READY_MASK) +#define APBH_CH1_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH1_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH1_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_SENSE_SHIFT)) & APBH_CH1_DEBUG1_SENSE_MASK) +#define APBH_CH1_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH1_DEBUG1_END_SHIFT (28U) +#define APBH_CH1_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_END_SHIFT)) & APBH_CH1_DEBUG1_END_MASK) +#define APBH_CH1_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH1_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH1_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_KICK_SHIFT)) & APBH_CH1_DEBUG1_KICK_MASK) +#define APBH_CH1_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH1_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH1_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_BURST_SHIFT)) & APBH_CH1_DEBUG1_BURST_MASK) +#define APBH_CH1_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH1_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH1_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_REQ_SHIFT)) & APBH_CH1_DEBUG1_REQ_MASK) + +/*! @name CH1_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH1_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH1_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH1_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH1_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH1_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH1_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_APB_BYTES_MASK) + +/*! @name CH2_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH2_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH2_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH2_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH2_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH2_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH2_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH2_CMD_COMMAND_MASK (0x3U) +#define APBH_CH2_CMD_COMMAND_SHIFT (0U) +#define APBH_CH2_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_COMMAND_SHIFT)) & APBH_CH2_CMD_COMMAND_MASK) +#define APBH_CH2_CMD_CHAIN_MASK (0x4U) +#define APBH_CH2_CMD_CHAIN_SHIFT (2U) +#define APBH_CH2_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CHAIN_SHIFT)) & APBH_CH2_CMD_CHAIN_MASK) +#define APBH_CH2_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH2_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH2_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_IRQONCMPLT_SHIFT)) & APBH_CH2_CMD_IRQONCMPLT_MASK) +#define APBH_CH2_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH2_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH2_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDLOCK_SHIFT)) & APBH_CH2_CMD_NANDLOCK_MASK) +#define APBH_CH2_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH2_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH2_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH2_CMD_NANDWAIT4READY_MASK) +#define APBH_CH2_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH2_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH2_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_SEMAPHORE_SHIFT)) & APBH_CH2_CMD_SEMAPHORE_MASK) +#define APBH_CH2_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH2_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH2_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH2_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH2_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH2_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH2_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH2_CMD_HALTONTERMINATE_MASK) +#define APBH_CH2_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH2_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH2_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CMDWORDS_SHIFT)) & APBH_CH2_CMD_CMDWORDS_MASK) +#define APBH_CH2_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH2_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH2_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_XFER_COUNT_SHIFT)) & APBH_CH2_CMD_XFER_COUNT_MASK) + +/*! @name CH2_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH2_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH2_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH2_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_BAR_ADDRESS_SHIFT)) & APBH_CH2_BAR_ADDRESS_MASK) + +/*! @name CH2_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH2_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH2_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH2_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH2_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH2_SEMA_PHORE_SHIFT (16U) +#define APBH_CH2_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_PHORE_SHIFT)) & APBH_CH2_SEMA_PHORE_MASK) + +/*! @name CH2_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH2_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH2_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH2_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH2_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH2_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH2_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH2_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RSVD1_SHIFT)) & APBH_CH2_DEBUG1_RSVD1_MASK) +#define APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH2_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH2_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH2_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH2_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH2_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_LOCK_SHIFT)) & APBH_CH2_DEBUG1_LOCK_MASK) +#define APBH_CH2_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH2_DEBUG1_READY_SHIFT (26U) +#define APBH_CH2_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_READY_SHIFT)) & APBH_CH2_DEBUG1_READY_MASK) +#define APBH_CH2_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH2_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH2_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_SENSE_SHIFT)) & APBH_CH2_DEBUG1_SENSE_MASK) +#define APBH_CH2_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH2_DEBUG1_END_SHIFT (28U) +#define APBH_CH2_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_END_SHIFT)) & APBH_CH2_DEBUG1_END_MASK) +#define APBH_CH2_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH2_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH2_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_KICK_SHIFT)) & APBH_CH2_DEBUG1_KICK_MASK) +#define APBH_CH2_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH2_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH2_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_BURST_SHIFT)) & APBH_CH2_DEBUG1_BURST_MASK) +#define APBH_CH2_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH2_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH2_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_REQ_SHIFT)) & APBH_CH2_DEBUG1_REQ_MASK) + +/*! @name CH2_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH2_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH2_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH2_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH2_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH2_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH2_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_APB_BYTES_MASK) + +/*! @name CH3_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH3_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH3_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH3_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH3_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH3_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH3_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH3_CMD_COMMAND_MASK (0x3U) +#define APBH_CH3_CMD_COMMAND_SHIFT (0U) +#define APBH_CH3_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_COMMAND_SHIFT)) & APBH_CH3_CMD_COMMAND_MASK) +#define APBH_CH3_CMD_CHAIN_MASK (0x4U) +#define APBH_CH3_CMD_CHAIN_SHIFT (2U) +#define APBH_CH3_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CHAIN_SHIFT)) & APBH_CH3_CMD_CHAIN_MASK) +#define APBH_CH3_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH3_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH3_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_IRQONCMPLT_SHIFT)) & APBH_CH3_CMD_IRQONCMPLT_MASK) +#define APBH_CH3_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH3_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH3_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDLOCK_SHIFT)) & APBH_CH3_CMD_NANDLOCK_MASK) +#define APBH_CH3_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH3_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH3_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH3_CMD_NANDWAIT4READY_MASK) +#define APBH_CH3_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH3_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH3_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_SEMAPHORE_SHIFT)) & APBH_CH3_CMD_SEMAPHORE_MASK) +#define APBH_CH3_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH3_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH3_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH3_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH3_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH3_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH3_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH3_CMD_HALTONTERMINATE_MASK) +#define APBH_CH3_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH3_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH3_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CMDWORDS_SHIFT)) & APBH_CH3_CMD_CMDWORDS_MASK) +#define APBH_CH3_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH3_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH3_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_XFER_COUNT_SHIFT)) & APBH_CH3_CMD_XFER_COUNT_MASK) + +/*! @name CH3_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH3_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH3_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH3_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_BAR_ADDRESS_SHIFT)) & APBH_CH3_BAR_ADDRESS_MASK) + +/*! @name CH3_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH3_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH3_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH3_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH3_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH3_SEMA_PHORE_SHIFT (16U) +#define APBH_CH3_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_PHORE_SHIFT)) & APBH_CH3_SEMA_PHORE_MASK) + +/*! @name CH3_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH3_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH3_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH3_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH3_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH3_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH3_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH3_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RSVD1_SHIFT)) & APBH_CH3_DEBUG1_RSVD1_MASK) +#define APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH3_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH3_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH3_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH3_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH3_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_LOCK_SHIFT)) & APBH_CH3_DEBUG1_LOCK_MASK) +#define APBH_CH3_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH3_DEBUG1_READY_SHIFT (26U) +#define APBH_CH3_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_READY_SHIFT)) & APBH_CH3_DEBUG1_READY_MASK) +#define APBH_CH3_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH3_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH3_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_SENSE_SHIFT)) & APBH_CH3_DEBUG1_SENSE_MASK) +#define APBH_CH3_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH3_DEBUG1_END_SHIFT (28U) +#define APBH_CH3_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_END_SHIFT)) & APBH_CH3_DEBUG1_END_MASK) +#define APBH_CH3_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH3_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH3_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_KICK_SHIFT)) & APBH_CH3_DEBUG1_KICK_MASK) +#define APBH_CH3_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH3_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH3_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_BURST_SHIFT)) & APBH_CH3_DEBUG1_BURST_MASK) +#define APBH_CH3_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH3_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH3_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_REQ_SHIFT)) & APBH_CH3_DEBUG1_REQ_MASK) + +/*! @name CH3_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH3_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH3_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH3_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH3_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH3_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH3_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_APB_BYTES_MASK) + +/*! @name CH4_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH4_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH4_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH4_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH4_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH4_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH4_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH4_CMD_COMMAND_MASK (0x3U) +#define APBH_CH4_CMD_COMMAND_SHIFT (0U) +#define APBH_CH4_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_COMMAND_SHIFT)) & APBH_CH4_CMD_COMMAND_MASK) +#define APBH_CH4_CMD_CHAIN_MASK (0x4U) +#define APBH_CH4_CMD_CHAIN_SHIFT (2U) +#define APBH_CH4_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CHAIN_SHIFT)) & APBH_CH4_CMD_CHAIN_MASK) +#define APBH_CH4_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH4_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH4_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_IRQONCMPLT_SHIFT)) & APBH_CH4_CMD_IRQONCMPLT_MASK) +#define APBH_CH4_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH4_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH4_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDLOCK_SHIFT)) & APBH_CH4_CMD_NANDLOCK_MASK) +#define APBH_CH4_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH4_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH4_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH4_CMD_NANDWAIT4READY_MASK) +#define APBH_CH4_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH4_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH4_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_SEMAPHORE_SHIFT)) & APBH_CH4_CMD_SEMAPHORE_MASK) +#define APBH_CH4_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH4_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH4_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH4_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH4_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH4_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH4_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH4_CMD_HALTONTERMINATE_MASK) +#define APBH_CH4_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH4_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH4_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CMDWORDS_SHIFT)) & APBH_CH4_CMD_CMDWORDS_MASK) +#define APBH_CH4_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH4_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH4_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_XFER_COUNT_SHIFT)) & APBH_CH4_CMD_XFER_COUNT_MASK) + +/*! @name CH4_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH4_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH4_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH4_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_BAR_ADDRESS_SHIFT)) & APBH_CH4_BAR_ADDRESS_MASK) + +/*! @name CH4_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH4_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH4_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH4_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH4_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH4_SEMA_PHORE_SHIFT (16U) +#define APBH_CH4_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_PHORE_SHIFT)) & APBH_CH4_SEMA_PHORE_MASK) + +/*! @name CH4_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH4_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH4_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH4_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH4_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH4_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH4_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH4_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RSVD1_SHIFT)) & APBH_CH4_DEBUG1_RSVD1_MASK) +#define APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH4_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH4_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH4_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH4_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH4_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_LOCK_SHIFT)) & APBH_CH4_DEBUG1_LOCK_MASK) +#define APBH_CH4_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH4_DEBUG1_READY_SHIFT (26U) +#define APBH_CH4_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_READY_SHIFT)) & APBH_CH4_DEBUG1_READY_MASK) +#define APBH_CH4_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH4_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH4_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_SENSE_SHIFT)) & APBH_CH4_DEBUG1_SENSE_MASK) +#define APBH_CH4_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH4_DEBUG1_END_SHIFT (28U) +#define APBH_CH4_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_END_SHIFT)) & APBH_CH4_DEBUG1_END_MASK) +#define APBH_CH4_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH4_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH4_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_KICK_SHIFT)) & APBH_CH4_DEBUG1_KICK_MASK) +#define APBH_CH4_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH4_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH4_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_BURST_SHIFT)) & APBH_CH4_DEBUG1_BURST_MASK) +#define APBH_CH4_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH4_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH4_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_REQ_SHIFT)) & APBH_CH4_DEBUG1_REQ_MASK) + +/*! @name CH4_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH4_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH4_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH4_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH4_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH4_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH4_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_APB_BYTES_MASK) + +/*! @name CH5_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH5_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH5_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH5_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH5_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH5_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH5_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH5_CMD_COMMAND_MASK (0x3U) +#define APBH_CH5_CMD_COMMAND_SHIFT (0U) +#define APBH_CH5_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_COMMAND_SHIFT)) & APBH_CH5_CMD_COMMAND_MASK) +#define APBH_CH5_CMD_CHAIN_MASK (0x4U) +#define APBH_CH5_CMD_CHAIN_SHIFT (2U) +#define APBH_CH5_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CHAIN_SHIFT)) & APBH_CH5_CMD_CHAIN_MASK) +#define APBH_CH5_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH5_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH5_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_IRQONCMPLT_SHIFT)) & APBH_CH5_CMD_IRQONCMPLT_MASK) +#define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH5_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH5_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK) +#define APBH_CH5_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH5_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH5_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH5_CMD_NANDWAIT4READY_MASK) +#define APBH_CH5_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH5_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH5_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_SEMAPHORE_SHIFT)) & APBH_CH5_CMD_SEMAPHORE_MASK) +#define APBH_CH5_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH5_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH5_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH5_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH5_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH5_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH5_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH5_CMD_HALTONTERMINATE_MASK) +#define APBH_CH5_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH5_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH5_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CMDWORDS_SHIFT)) & APBH_CH5_CMD_CMDWORDS_MASK) +#define APBH_CH5_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH5_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH5_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_XFER_COUNT_SHIFT)) & APBH_CH5_CMD_XFER_COUNT_MASK) + +/*! @name CH5_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH5_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH5_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH5_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_BAR_ADDRESS_SHIFT)) & APBH_CH5_BAR_ADDRESS_MASK) + +/*! @name CH5_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH5_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH5_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH5_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH5_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH5_SEMA_PHORE_SHIFT (16U) +#define APBH_CH5_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_PHORE_SHIFT)) & APBH_CH5_SEMA_PHORE_MASK) + +/*! @name CH5_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH5_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH5_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH5_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH5_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH5_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH5_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH5_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RSVD1_SHIFT)) & APBH_CH5_DEBUG1_RSVD1_MASK) +#define APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH5_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH5_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH5_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH5_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH5_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_LOCK_SHIFT)) & APBH_CH5_DEBUG1_LOCK_MASK) +#define APBH_CH5_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH5_DEBUG1_READY_SHIFT (26U) +#define APBH_CH5_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_READY_SHIFT)) & APBH_CH5_DEBUG1_READY_MASK) +#define APBH_CH5_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH5_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH5_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_SENSE_SHIFT)) & APBH_CH5_DEBUG1_SENSE_MASK) +#define APBH_CH5_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH5_DEBUG1_END_SHIFT (28U) +#define APBH_CH5_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_END_SHIFT)) & APBH_CH5_DEBUG1_END_MASK) +#define APBH_CH5_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH5_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH5_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_KICK_SHIFT)) & APBH_CH5_DEBUG1_KICK_MASK) +#define APBH_CH5_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH5_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH5_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_BURST_SHIFT)) & APBH_CH5_DEBUG1_BURST_MASK) +#define APBH_CH5_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH5_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH5_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_REQ_SHIFT)) & APBH_CH5_DEBUG1_REQ_MASK) + +/*! @name CH5_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH5_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH5_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH5_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH5_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH5_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH5_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_APB_BYTES_MASK) + +/*! @name CH6_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH6_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH6_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH6_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH6_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH6_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH6_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH6_CMD_COMMAND_MASK (0x3U) +#define APBH_CH6_CMD_COMMAND_SHIFT (0U) +#define APBH_CH6_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_COMMAND_SHIFT)) & APBH_CH6_CMD_COMMAND_MASK) +#define APBH_CH6_CMD_CHAIN_MASK (0x4U) +#define APBH_CH6_CMD_CHAIN_SHIFT (2U) +#define APBH_CH6_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CHAIN_SHIFT)) & APBH_CH6_CMD_CHAIN_MASK) +#define APBH_CH6_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH6_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH6_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_IRQONCMPLT_SHIFT)) & APBH_CH6_CMD_IRQONCMPLT_MASK) +#define APBH_CH6_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH6_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH6_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDLOCK_SHIFT)) & APBH_CH6_CMD_NANDLOCK_MASK) +#define APBH_CH6_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH6_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH6_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH6_CMD_NANDWAIT4READY_MASK) +#define APBH_CH6_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH6_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH6_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_SEMAPHORE_SHIFT)) & APBH_CH6_CMD_SEMAPHORE_MASK) +#define APBH_CH6_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH6_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH6_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH6_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH6_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH6_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH6_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH6_CMD_HALTONTERMINATE_MASK) +#define APBH_CH6_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH6_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH6_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CMDWORDS_SHIFT)) & APBH_CH6_CMD_CMDWORDS_MASK) +#define APBH_CH6_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH6_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH6_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_XFER_COUNT_SHIFT)) & APBH_CH6_CMD_XFER_COUNT_MASK) + +/*! @name CH6_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH6_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH6_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH6_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_BAR_ADDRESS_SHIFT)) & APBH_CH6_BAR_ADDRESS_MASK) + +/*! @name CH6_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH6_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH6_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH6_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH6_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH6_SEMA_PHORE_SHIFT (16U) +#define APBH_CH6_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_PHORE_SHIFT)) & APBH_CH6_SEMA_PHORE_MASK) + +/*! @name CH6_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH6_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH6_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH6_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH6_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH6_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH6_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH6_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RSVD1_SHIFT)) & APBH_CH6_DEBUG1_RSVD1_MASK) +#define APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH6_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH6_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH6_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH6_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH6_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_LOCK_SHIFT)) & APBH_CH6_DEBUG1_LOCK_MASK) +#define APBH_CH6_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH6_DEBUG1_READY_SHIFT (26U) +#define APBH_CH6_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_READY_SHIFT)) & APBH_CH6_DEBUG1_READY_MASK) +#define APBH_CH6_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH6_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH6_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_SENSE_SHIFT)) & APBH_CH6_DEBUG1_SENSE_MASK) +#define APBH_CH6_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH6_DEBUG1_END_SHIFT (28U) +#define APBH_CH6_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_END_SHIFT)) & APBH_CH6_DEBUG1_END_MASK) +#define APBH_CH6_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH6_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH6_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_KICK_SHIFT)) & APBH_CH6_DEBUG1_KICK_MASK) +#define APBH_CH6_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH6_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH6_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_BURST_SHIFT)) & APBH_CH6_DEBUG1_BURST_MASK) +#define APBH_CH6_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH6_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH6_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_REQ_SHIFT)) & APBH_CH6_DEBUG1_REQ_MASK) + +/*! @name CH6_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH6_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH6_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH6_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH6_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH6_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH6_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_APB_BYTES_MASK) + +/*! @name CH7_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH7_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH7_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH7_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH7_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH7_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH7_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH7_CMD_COMMAND_MASK (0x3U) +#define APBH_CH7_CMD_COMMAND_SHIFT (0U) +#define APBH_CH7_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_COMMAND_SHIFT)) & APBH_CH7_CMD_COMMAND_MASK) +#define APBH_CH7_CMD_CHAIN_MASK (0x4U) +#define APBH_CH7_CMD_CHAIN_SHIFT (2U) +#define APBH_CH7_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CHAIN_SHIFT)) & APBH_CH7_CMD_CHAIN_MASK) +#define APBH_CH7_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH7_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH7_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_IRQONCMPLT_SHIFT)) & APBH_CH7_CMD_IRQONCMPLT_MASK) +#define APBH_CH7_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH7_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH7_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDLOCK_SHIFT)) & APBH_CH7_CMD_NANDLOCK_MASK) +#define APBH_CH7_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH7_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH7_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH7_CMD_NANDWAIT4READY_MASK) +#define APBH_CH7_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH7_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH7_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_SEMAPHORE_SHIFT)) & APBH_CH7_CMD_SEMAPHORE_MASK) +#define APBH_CH7_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH7_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH7_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH7_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH7_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH7_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH7_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH7_CMD_HALTONTERMINATE_MASK) +#define APBH_CH7_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH7_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH7_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CMDWORDS_SHIFT)) & APBH_CH7_CMD_CMDWORDS_MASK) +#define APBH_CH7_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH7_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH7_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_XFER_COUNT_SHIFT)) & APBH_CH7_CMD_XFER_COUNT_MASK) + +/*! @name CH7_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH7_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH7_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH7_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_BAR_ADDRESS_SHIFT)) & APBH_CH7_BAR_ADDRESS_MASK) + +/*! @name CH7_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH7_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH7_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH7_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH7_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH7_SEMA_PHORE_SHIFT (16U) +#define APBH_CH7_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_PHORE_SHIFT)) & APBH_CH7_SEMA_PHORE_MASK) + +/*! @name CH7_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH7_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH7_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH7_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH7_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH7_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH7_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH7_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RSVD1_SHIFT)) & APBH_CH7_DEBUG1_RSVD1_MASK) +#define APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH7_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH7_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH7_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH7_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH7_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_LOCK_SHIFT)) & APBH_CH7_DEBUG1_LOCK_MASK) +#define APBH_CH7_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH7_DEBUG1_READY_SHIFT (26U) +#define APBH_CH7_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_READY_SHIFT)) & APBH_CH7_DEBUG1_READY_MASK) +#define APBH_CH7_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH7_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH7_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_SENSE_SHIFT)) & APBH_CH7_DEBUG1_SENSE_MASK) +#define APBH_CH7_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH7_DEBUG1_END_SHIFT (28U) +#define APBH_CH7_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_END_SHIFT)) & APBH_CH7_DEBUG1_END_MASK) +#define APBH_CH7_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH7_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH7_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_KICK_SHIFT)) & APBH_CH7_DEBUG1_KICK_MASK) +#define APBH_CH7_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH7_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH7_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_BURST_SHIFT)) & APBH_CH7_DEBUG1_BURST_MASK) +#define APBH_CH7_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH7_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH7_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_REQ_SHIFT)) & APBH_CH7_DEBUG1_REQ_MASK) + +/*! @name CH7_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH7_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH7_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH7_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH7_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH7_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH7_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_APB_BYTES_MASK) + +/*! @name CH8_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH8_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH8_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH8_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH8_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH8_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH8_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH8_CMD_COMMAND_MASK (0x3U) +#define APBH_CH8_CMD_COMMAND_SHIFT (0U) +#define APBH_CH8_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_COMMAND_SHIFT)) & APBH_CH8_CMD_COMMAND_MASK) +#define APBH_CH8_CMD_CHAIN_MASK (0x4U) +#define APBH_CH8_CMD_CHAIN_SHIFT (2U) +#define APBH_CH8_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CHAIN_SHIFT)) & APBH_CH8_CMD_CHAIN_MASK) +#define APBH_CH8_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH8_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH8_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_IRQONCMPLT_SHIFT)) & APBH_CH8_CMD_IRQONCMPLT_MASK) +#define APBH_CH8_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH8_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH8_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDLOCK_SHIFT)) & APBH_CH8_CMD_NANDLOCK_MASK) +#define APBH_CH8_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH8_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH8_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH8_CMD_NANDWAIT4READY_MASK) +#define APBH_CH8_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH8_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH8_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_SEMAPHORE_SHIFT)) & APBH_CH8_CMD_SEMAPHORE_MASK) +#define APBH_CH8_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH8_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH8_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH8_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH8_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH8_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH8_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH8_CMD_HALTONTERMINATE_MASK) +#define APBH_CH8_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH8_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH8_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CMDWORDS_SHIFT)) & APBH_CH8_CMD_CMDWORDS_MASK) +#define APBH_CH8_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH8_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH8_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_XFER_COUNT_SHIFT)) & APBH_CH8_CMD_XFER_COUNT_MASK) + +/*! @name CH8_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH8_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH8_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH8_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_BAR_ADDRESS_SHIFT)) & APBH_CH8_BAR_ADDRESS_MASK) + +/*! @name CH8_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH8_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH8_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH8_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH8_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH8_SEMA_PHORE_SHIFT (16U) +#define APBH_CH8_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_PHORE_SHIFT)) & APBH_CH8_SEMA_PHORE_MASK) + +/*! @name CH8_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH8_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH8_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH8_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH8_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH8_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH8_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH8_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RSVD1_SHIFT)) & APBH_CH8_DEBUG1_RSVD1_MASK) +#define APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH8_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH8_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH8_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH8_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH8_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_LOCK_SHIFT)) & APBH_CH8_DEBUG1_LOCK_MASK) +#define APBH_CH8_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH8_DEBUG1_READY_SHIFT (26U) +#define APBH_CH8_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_READY_SHIFT)) & APBH_CH8_DEBUG1_READY_MASK) +#define APBH_CH8_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH8_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH8_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_SENSE_SHIFT)) & APBH_CH8_DEBUG1_SENSE_MASK) +#define APBH_CH8_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH8_DEBUG1_END_SHIFT (28U) +#define APBH_CH8_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_END_SHIFT)) & APBH_CH8_DEBUG1_END_MASK) +#define APBH_CH8_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH8_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH8_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_KICK_SHIFT)) & APBH_CH8_DEBUG1_KICK_MASK) +#define APBH_CH8_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH8_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH8_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_BURST_SHIFT)) & APBH_CH8_DEBUG1_BURST_MASK) +#define APBH_CH8_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH8_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH8_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_REQ_SHIFT)) & APBH_CH8_DEBUG1_REQ_MASK) + +/*! @name CH8_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH8_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH8_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH8_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH8_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH8_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH8_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_APB_BYTES_MASK) + +/*! @name CH9_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH9_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH9_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH9_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH9_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH9_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH9_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH9_CMD_COMMAND_MASK (0x3U) +#define APBH_CH9_CMD_COMMAND_SHIFT (0U) +#define APBH_CH9_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_COMMAND_SHIFT)) & APBH_CH9_CMD_COMMAND_MASK) +#define APBH_CH9_CMD_CHAIN_MASK (0x4U) +#define APBH_CH9_CMD_CHAIN_SHIFT (2U) +#define APBH_CH9_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CHAIN_SHIFT)) & APBH_CH9_CMD_CHAIN_MASK) +#define APBH_CH9_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH9_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH9_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_IRQONCMPLT_SHIFT)) & APBH_CH9_CMD_IRQONCMPLT_MASK) +#define APBH_CH9_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH9_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH9_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDLOCK_SHIFT)) & APBH_CH9_CMD_NANDLOCK_MASK) +#define APBH_CH9_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH9_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH9_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH9_CMD_NANDWAIT4READY_MASK) +#define APBH_CH9_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH9_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH9_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_SEMAPHORE_SHIFT)) & APBH_CH9_CMD_SEMAPHORE_MASK) +#define APBH_CH9_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH9_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH9_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH9_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH9_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH9_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH9_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH9_CMD_HALTONTERMINATE_MASK) +#define APBH_CH9_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH9_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH9_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CMDWORDS_SHIFT)) & APBH_CH9_CMD_CMDWORDS_MASK) +#define APBH_CH9_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH9_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH9_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_XFER_COUNT_SHIFT)) & APBH_CH9_CMD_XFER_COUNT_MASK) + +/*! @name CH9_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH9_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH9_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH9_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_BAR_ADDRESS_SHIFT)) & APBH_CH9_BAR_ADDRESS_MASK) + +/*! @name CH9_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH9_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH9_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH9_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH9_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH9_SEMA_PHORE_SHIFT (16U) +#define APBH_CH9_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_PHORE_SHIFT)) & APBH_CH9_SEMA_PHORE_MASK) + +/*! @name CH9_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH9_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH9_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH9_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH9_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH9_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH9_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH9_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RSVD1_SHIFT)) & APBH_CH9_DEBUG1_RSVD1_MASK) +#define APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH9_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH9_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH9_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH9_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH9_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_LOCK_SHIFT)) & APBH_CH9_DEBUG1_LOCK_MASK) +#define APBH_CH9_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH9_DEBUG1_READY_SHIFT (26U) +#define APBH_CH9_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_READY_SHIFT)) & APBH_CH9_DEBUG1_READY_MASK) +#define APBH_CH9_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH9_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH9_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_SENSE_SHIFT)) & APBH_CH9_DEBUG1_SENSE_MASK) +#define APBH_CH9_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH9_DEBUG1_END_SHIFT (28U) +#define APBH_CH9_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_END_SHIFT)) & APBH_CH9_DEBUG1_END_MASK) +#define APBH_CH9_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH9_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH9_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_KICK_SHIFT)) & APBH_CH9_DEBUG1_KICK_MASK) +#define APBH_CH9_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH9_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH9_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_BURST_SHIFT)) & APBH_CH9_DEBUG1_BURST_MASK) +#define APBH_CH9_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH9_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH9_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_REQ_SHIFT)) & APBH_CH9_DEBUG1_REQ_MASK) + +/*! @name CH9_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH9_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH9_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH9_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH9_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH9_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH9_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_APB_BYTES_MASK) + +/*! @name CH10_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH10_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH10_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH10_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH10_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH10_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH10_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH10_CMD_COMMAND_MASK (0x3U) +#define APBH_CH10_CMD_COMMAND_SHIFT (0U) +#define APBH_CH10_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_COMMAND_SHIFT)) & APBH_CH10_CMD_COMMAND_MASK) +#define APBH_CH10_CMD_CHAIN_MASK (0x4U) +#define APBH_CH10_CMD_CHAIN_SHIFT (2U) +#define APBH_CH10_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CHAIN_SHIFT)) & APBH_CH10_CMD_CHAIN_MASK) +#define APBH_CH10_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH10_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH10_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_IRQONCMPLT_SHIFT)) & APBH_CH10_CMD_IRQONCMPLT_MASK) +#define APBH_CH10_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH10_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH10_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDLOCK_SHIFT)) & APBH_CH10_CMD_NANDLOCK_MASK) +#define APBH_CH10_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH10_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH10_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH10_CMD_NANDWAIT4READY_MASK) +#define APBH_CH10_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH10_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH10_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_SEMAPHORE_SHIFT)) & APBH_CH10_CMD_SEMAPHORE_MASK) +#define APBH_CH10_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH10_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH10_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH10_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH10_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH10_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH10_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH10_CMD_HALTONTERMINATE_MASK) +#define APBH_CH10_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH10_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH10_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CMDWORDS_SHIFT)) & APBH_CH10_CMD_CMDWORDS_MASK) +#define APBH_CH10_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH10_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH10_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_XFER_COUNT_SHIFT)) & APBH_CH10_CMD_XFER_COUNT_MASK) + +/*! @name CH10_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH10_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH10_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH10_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_BAR_ADDRESS_SHIFT)) & APBH_CH10_BAR_ADDRESS_MASK) + +/*! @name CH10_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH10_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH10_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH10_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH10_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH10_SEMA_PHORE_SHIFT (16U) +#define APBH_CH10_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_PHORE_SHIFT)) & APBH_CH10_SEMA_PHORE_MASK) + +/*! @name CH10_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH10_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH10_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH10_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH10_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH10_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH10_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH10_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RSVD1_SHIFT)) & APBH_CH10_DEBUG1_RSVD1_MASK) +#define APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH10_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH10_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH10_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH10_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH10_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_LOCK_SHIFT)) & APBH_CH10_DEBUG1_LOCK_MASK) +#define APBH_CH10_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH10_DEBUG1_READY_SHIFT (26U) +#define APBH_CH10_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_READY_SHIFT)) & APBH_CH10_DEBUG1_READY_MASK) +#define APBH_CH10_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH10_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH10_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_SENSE_SHIFT)) & APBH_CH10_DEBUG1_SENSE_MASK) +#define APBH_CH10_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH10_DEBUG1_END_SHIFT (28U) +#define APBH_CH10_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_END_SHIFT)) & APBH_CH10_DEBUG1_END_MASK) +#define APBH_CH10_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH10_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH10_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_KICK_SHIFT)) & APBH_CH10_DEBUG1_KICK_MASK) +#define APBH_CH10_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH10_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH10_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_BURST_SHIFT)) & APBH_CH10_DEBUG1_BURST_MASK) +#define APBH_CH10_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH10_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH10_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_REQ_SHIFT)) & APBH_CH10_DEBUG1_REQ_MASK) + +/*! @name CH10_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH10_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH10_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH10_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH10_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH10_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH10_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_APB_BYTES_MASK) + +/*! @name CH11_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH11_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH11_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH11_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH11_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH11_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH11_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH11_CMD_COMMAND_MASK (0x3U) +#define APBH_CH11_CMD_COMMAND_SHIFT (0U) +#define APBH_CH11_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_COMMAND_SHIFT)) & APBH_CH11_CMD_COMMAND_MASK) +#define APBH_CH11_CMD_CHAIN_MASK (0x4U) +#define APBH_CH11_CMD_CHAIN_SHIFT (2U) +#define APBH_CH11_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CHAIN_SHIFT)) & APBH_CH11_CMD_CHAIN_MASK) +#define APBH_CH11_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH11_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH11_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_IRQONCMPLT_SHIFT)) & APBH_CH11_CMD_IRQONCMPLT_MASK) +#define APBH_CH11_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH11_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH11_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDLOCK_SHIFT)) & APBH_CH11_CMD_NANDLOCK_MASK) +#define APBH_CH11_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH11_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH11_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH11_CMD_NANDWAIT4READY_MASK) +#define APBH_CH11_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH11_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH11_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_SEMAPHORE_SHIFT)) & APBH_CH11_CMD_SEMAPHORE_MASK) +#define APBH_CH11_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH11_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH11_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH11_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH11_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH11_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH11_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH11_CMD_HALTONTERMINATE_MASK) +#define APBH_CH11_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH11_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH11_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CMDWORDS_SHIFT)) & APBH_CH11_CMD_CMDWORDS_MASK) +#define APBH_CH11_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH11_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH11_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_XFER_COUNT_SHIFT)) & APBH_CH11_CMD_XFER_COUNT_MASK) + +/*! @name CH11_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH11_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH11_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH11_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_BAR_ADDRESS_SHIFT)) & APBH_CH11_BAR_ADDRESS_MASK) + +/*! @name CH11_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH11_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH11_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH11_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH11_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH11_SEMA_PHORE_SHIFT (16U) +#define APBH_CH11_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_PHORE_SHIFT)) & APBH_CH11_SEMA_PHORE_MASK) + +/*! @name CH11_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH11_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH11_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH11_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH11_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH11_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH11_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH11_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RSVD1_SHIFT)) & APBH_CH11_DEBUG1_RSVD1_MASK) +#define APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH11_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH11_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH11_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH11_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH11_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_LOCK_SHIFT)) & APBH_CH11_DEBUG1_LOCK_MASK) +#define APBH_CH11_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH11_DEBUG1_READY_SHIFT (26U) +#define APBH_CH11_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_READY_SHIFT)) & APBH_CH11_DEBUG1_READY_MASK) +#define APBH_CH11_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH11_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH11_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_SENSE_SHIFT)) & APBH_CH11_DEBUG1_SENSE_MASK) +#define APBH_CH11_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH11_DEBUG1_END_SHIFT (28U) +#define APBH_CH11_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_END_SHIFT)) & APBH_CH11_DEBUG1_END_MASK) +#define APBH_CH11_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH11_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH11_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_KICK_SHIFT)) & APBH_CH11_DEBUG1_KICK_MASK) +#define APBH_CH11_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH11_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH11_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_BURST_SHIFT)) & APBH_CH11_DEBUG1_BURST_MASK) +#define APBH_CH11_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH11_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH11_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_REQ_SHIFT)) & APBH_CH11_DEBUG1_REQ_MASK) + +/*! @name CH11_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH11_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH11_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH11_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH11_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH11_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH11_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_APB_BYTES_MASK) + +/*! @name CH12_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH12_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH12_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH12_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH12_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH12_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH12_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH12_CMD_COMMAND_MASK (0x3U) +#define APBH_CH12_CMD_COMMAND_SHIFT (0U) +#define APBH_CH12_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_COMMAND_SHIFT)) & APBH_CH12_CMD_COMMAND_MASK) +#define APBH_CH12_CMD_CHAIN_MASK (0x4U) +#define APBH_CH12_CMD_CHAIN_SHIFT (2U) +#define APBH_CH12_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CHAIN_SHIFT)) & APBH_CH12_CMD_CHAIN_MASK) +#define APBH_CH12_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH12_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH12_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_IRQONCMPLT_SHIFT)) & APBH_CH12_CMD_IRQONCMPLT_MASK) +#define APBH_CH12_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH12_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH12_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDLOCK_SHIFT)) & APBH_CH12_CMD_NANDLOCK_MASK) +#define APBH_CH12_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH12_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH12_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH12_CMD_NANDWAIT4READY_MASK) +#define APBH_CH12_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH12_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH12_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_SEMAPHORE_SHIFT)) & APBH_CH12_CMD_SEMAPHORE_MASK) +#define APBH_CH12_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH12_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH12_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH12_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH12_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH12_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH12_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH12_CMD_HALTONTERMINATE_MASK) +#define APBH_CH12_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH12_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH12_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CMDWORDS_SHIFT)) & APBH_CH12_CMD_CMDWORDS_MASK) +#define APBH_CH12_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH12_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH12_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_XFER_COUNT_SHIFT)) & APBH_CH12_CMD_XFER_COUNT_MASK) + +/*! @name CH12_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH12_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH12_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH12_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_BAR_ADDRESS_SHIFT)) & APBH_CH12_BAR_ADDRESS_MASK) + +/*! @name CH12_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH12_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH12_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH12_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH12_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH12_SEMA_PHORE_SHIFT (16U) +#define APBH_CH12_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_PHORE_SHIFT)) & APBH_CH12_SEMA_PHORE_MASK) + +/*! @name CH12_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH12_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH12_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH12_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH12_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH12_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH12_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH12_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RSVD1_SHIFT)) & APBH_CH12_DEBUG1_RSVD1_MASK) +#define APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH12_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH12_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH12_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH12_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH12_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_LOCK_SHIFT)) & APBH_CH12_DEBUG1_LOCK_MASK) +#define APBH_CH12_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH12_DEBUG1_READY_SHIFT (26U) +#define APBH_CH12_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_READY_SHIFT)) & APBH_CH12_DEBUG1_READY_MASK) +#define APBH_CH12_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH12_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH12_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_SENSE_SHIFT)) & APBH_CH12_DEBUG1_SENSE_MASK) +#define APBH_CH12_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH12_DEBUG1_END_SHIFT (28U) +#define APBH_CH12_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_END_SHIFT)) & APBH_CH12_DEBUG1_END_MASK) +#define APBH_CH12_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH12_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH12_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_KICK_SHIFT)) & APBH_CH12_DEBUG1_KICK_MASK) +#define APBH_CH12_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH12_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH12_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_BURST_SHIFT)) & APBH_CH12_DEBUG1_BURST_MASK) +#define APBH_CH12_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH12_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH12_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_REQ_SHIFT)) & APBH_CH12_DEBUG1_REQ_MASK) + +/*! @name CH12_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH12_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH12_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH12_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH12_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH12_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH12_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_APB_BYTES_MASK) + +/*! @name CH13_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH13_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH13_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH13_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH13_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH13_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH13_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH13_CMD_COMMAND_MASK (0x3U) +#define APBH_CH13_CMD_COMMAND_SHIFT (0U) +#define APBH_CH13_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_COMMAND_SHIFT)) & APBH_CH13_CMD_COMMAND_MASK) +#define APBH_CH13_CMD_CHAIN_MASK (0x4U) +#define APBH_CH13_CMD_CHAIN_SHIFT (2U) +#define APBH_CH13_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CHAIN_SHIFT)) & APBH_CH13_CMD_CHAIN_MASK) +#define APBH_CH13_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH13_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH13_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_IRQONCMPLT_SHIFT)) & APBH_CH13_CMD_IRQONCMPLT_MASK) +#define APBH_CH13_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH13_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH13_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDLOCK_SHIFT)) & APBH_CH13_CMD_NANDLOCK_MASK) +#define APBH_CH13_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH13_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH13_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH13_CMD_NANDWAIT4READY_MASK) +#define APBH_CH13_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH13_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH13_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_SEMAPHORE_SHIFT)) & APBH_CH13_CMD_SEMAPHORE_MASK) +#define APBH_CH13_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH13_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH13_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH13_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH13_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH13_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH13_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH13_CMD_HALTONTERMINATE_MASK) +#define APBH_CH13_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH13_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH13_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CMDWORDS_SHIFT)) & APBH_CH13_CMD_CMDWORDS_MASK) +#define APBH_CH13_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH13_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH13_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_XFER_COUNT_SHIFT)) & APBH_CH13_CMD_XFER_COUNT_MASK) + +/*! @name CH13_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH13_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH13_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH13_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_BAR_ADDRESS_SHIFT)) & APBH_CH13_BAR_ADDRESS_MASK) + +/*! @name CH13_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH13_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH13_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH13_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH13_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH13_SEMA_PHORE_SHIFT (16U) +#define APBH_CH13_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_PHORE_SHIFT)) & APBH_CH13_SEMA_PHORE_MASK) + +/*! @name CH13_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH13_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH13_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH13_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH13_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH13_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH13_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH13_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RSVD1_SHIFT)) & APBH_CH13_DEBUG1_RSVD1_MASK) +#define APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH13_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH13_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH13_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH13_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH13_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_LOCK_SHIFT)) & APBH_CH13_DEBUG1_LOCK_MASK) +#define APBH_CH13_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH13_DEBUG1_READY_SHIFT (26U) +#define APBH_CH13_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_READY_SHIFT)) & APBH_CH13_DEBUG1_READY_MASK) +#define APBH_CH13_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH13_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH13_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_SENSE_SHIFT)) & APBH_CH13_DEBUG1_SENSE_MASK) +#define APBH_CH13_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH13_DEBUG1_END_SHIFT (28U) +#define APBH_CH13_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_END_SHIFT)) & APBH_CH13_DEBUG1_END_MASK) +#define APBH_CH13_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH13_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH13_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_KICK_SHIFT)) & APBH_CH13_DEBUG1_KICK_MASK) +#define APBH_CH13_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH13_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH13_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_BURST_SHIFT)) & APBH_CH13_DEBUG1_BURST_MASK) +#define APBH_CH13_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH13_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH13_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_REQ_SHIFT)) & APBH_CH13_DEBUG1_REQ_MASK) + +/*! @name CH13_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH13_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH13_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH13_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH13_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH13_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH13_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_APB_BYTES_MASK) + +/*! @name CH14_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH14_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH14_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH14_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH14_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH14_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH14_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH14_CMD_COMMAND_MASK (0x3U) +#define APBH_CH14_CMD_COMMAND_SHIFT (0U) +#define APBH_CH14_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_COMMAND_SHIFT)) & APBH_CH14_CMD_COMMAND_MASK) +#define APBH_CH14_CMD_CHAIN_MASK (0x4U) +#define APBH_CH14_CMD_CHAIN_SHIFT (2U) +#define APBH_CH14_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CHAIN_SHIFT)) & APBH_CH14_CMD_CHAIN_MASK) +#define APBH_CH14_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH14_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH14_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_IRQONCMPLT_SHIFT)) & APBH_CH14_CMD_IRQONCMPLT_MASK) +#define APBH_CH14_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH14_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH14_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDLOCK_SHIFT)) & APBH_CH14_CMD_NANDLOCK_MASK) +#define APBH_CH14_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH14_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH14_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH14_CMD_NANDWAIT4READY_MASK) +#define APBH_CH14_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH14_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH14_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_SEMAPHORE_SHIFT)) & APBH_CH14_CMD_SEMAPHORE_MASK) +#define APBH_CH14_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH14_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH14_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH14_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH14_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH14_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH14_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH14_CMD_HALTONTERMINATE_MASK) +#define APBH_CH14_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH14_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH14_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CMDWORDS_SHIFT)) & APBH_CH14_CMD_CMDWORDS_MASK) +#define APBH_CH14_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH14_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH14_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_XFER_COUNT_SHIFT)) & APBH_CH14_CMD_XFER_COUNT_MASK) + +/*! @name CH14_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH14_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH14_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH14_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_BAR_ADDRESS_SHIFT)) & APBH_CH14_BAR_ADDRESS_MASK) + +/*! @name CH14_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH14_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH14_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH14_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH14_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH14_SEMA_PHORE_SHIFT (16U) +#define APBH_CH14_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_PHORE_SHIFT)) & APBH_CH14_SEMA_PHORE_MASK) + +/*! @name CH14_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH14_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH14_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH14_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH14_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH14_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH14_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH14_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RSVD1_SHIFT)) & APBH_CH14_DEBUG1_RSVD1_MASK) +#define APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH14_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH14_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH14_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH14_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH14_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_LOCK_SHIFT)) & APBH_CH14_DEBUG1_LOCK_MASK) +#define APBH_CH14_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH14_DEBUG1_READY_SHIFT (26U) +#define APBH_CH14_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_READY_SHIFT)) & APBH_CH14_DEBUG1_READY_MASK) +#define APBH_CH14_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH14_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH14_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_SENSE_SHIFT)) & APBH_CH14_DEBUG1_SENSE_MASK) +#define APBH_CH14_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH14_DEBUG1_END_SHIFT (28U) +#define APBH_CH14_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_END_SHIFT)) & APBH_CH14_DEBUG1_END_MASK) +#define APBH_CH14_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH14_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH14_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_KICK_SHIFT)) & APBH_CH14_DEBUG1_KICK_MASK) +#define APBH_CH14_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH14_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH14_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_BURST_SHIFT)) & APBH_CH14_DEBUG1_BURST_MASK) +#define APBH_CH14_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH14_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH14_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_REQ_SHIFT)) & APBH_CH14_DEBUG1_REQ_MASK) + +/*! @name CH14_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH14_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH14_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH14_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH14_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH14_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH14_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_APB_BYTES_MASK) + +/*! @name CH15_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH15_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH15_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH15_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH15_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH15_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH15_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH15_CMD_COMMAND_MASK (0x3U) +#define APBH_CH15_CMD_COMMAND_SHIFT (0U) +#define APBH_CH15_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_COMMAND_SHIFT)) & APBH_CH15_CMD_COMMAND_MASK) +#define APBH_CH15_CMD_CHAIN_MASK (0x4U) +#define APBH_CH15_CMD_CHAIN_SHIFT (2U) +#define APBH_CH15_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CHAIN_SHIFT)) & APBH_CH15_CMD_CHAIN_MASK) +#define APBH_CH15_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH15_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH15_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_IRQONCMPLT_SHIFT)) & APBH_CH15_CMD_IRQONCMPLT_MASK) +#define APBH_CH15_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH15_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH15_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDLOCK_SHIFT)) & APBH_CH15_CMD_NANDLOCK_MASK) +#define APBH_CH15_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH15_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH15_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH15_CMD_NANDWAIT4READY_MASK) +#define APBH_CH15_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH15_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH15_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_SEMAPHORE_SHIFT)) & APBH_CH15_CMD_SEMAPHORE_MASK) +#define APBH_CH15_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH15_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH15_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH15_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH15_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH15_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH15_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH15_CMD_HALTONTERMINATE_MASK) +#define APBH_CH15_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH15_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH15_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CMDWORDS_SHIFT)) & APBH_CH15_CMD_CMDWORDS_MASK) +#define APBH_CH15_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH15_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH15_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_XFER_COUNT_SHIFT)) & APBH_CH15_CMD_XFER_COUNT_MASK) + +/*! @name CH15_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH15_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH15_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH15_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_BAR_ADDRESS_SHIFT)) & APBH_CH15_BAR_ADDRESS_MASK) + +/*! @name CH15_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH15_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH15_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH15_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH15_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH15_SEMA_PHORE_SHIFT (16U) +#define APBH_CH15_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_PHORE_SHIFT)) & APBH_CH15_SEMA_PHORE_MASK) + +/*! @name CH15_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH15_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH15_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH15_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH15_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH15_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH15_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH15_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RSVD1_SHIFT)) & APBH_CH15_DEBUG1_RSVD1_MASK) +#define APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH15_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH15_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH15_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH15_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH15_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_LOCK_SHIFT)) & APBH_CH15_DEBUG1_LOCK_MASK) +#define APBH_CH15_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH15_DEBUG1_READY_SHIFT (26U) +#define APBH_CH15_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_READY_SHIFT)) & APBH_CH15_DEBUG1_READY_MASK) +#define APBH_CH15_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH15_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH15_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_SENSE_SHIFT)) & APBH_CH15_DEBUG1_SENSE_MASK) +#define APBH_CH15_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH15_DEBUG1_END_SHIFT (28U) +#define APBH_CH15_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_END_SHIFT)) & APBH_CH15_DEBUG1_END_MASK) +#define APBH_CH15_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH15_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH15_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_KICK_SHIFT)) & APBH_CH15_DEBUG1_KICK_MASK) +#define APBH_CH15_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH15_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH15_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_BURST_SHIFT)) & APBH_CH15_DEBUG1_BURST_MASK) +#define APBH_CH15_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH15_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH15_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_REQ_SHIFT)) & APBH_CH15_DEBUG1_REQ_MASK) + +/*! @name CH15_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH15_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH15_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH15_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH15_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH15_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH15_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_APB_BYTES_MASK) + +/*! @name VERSION - APBH Bridge Version Register */ +#define APBH_VERSION_STEP_MASK (0xFFFFU) +#define APBH_VERSION_STEP_SHIFT (0U) +#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK) +#define APBH_VERSION_MINOR_MASK (0xFF0000U) +#define APBH_VERSION_MINOR_SHIFT (16U) +#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK) +#define APBH_VERSION_MAJOR_MASK (0xFF000000U) +#define APBH_VERSION_MAJOR_SHIFT (24U) +#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK) + + +/*! + * @} + */ /* end of group APBH_Register_Masks */ + + +/* APBH - Peripheral instance base addresses */ +/** Peripheral APBH base address */ +#define APBH_BASE (0x1804000u) +/** Peripheral APBH base pointer */ +#define APBH ((APBH_Type *)APBH_BASE) +/** Array initializer of APBH peripheral base addresses */ +#define APBH_BASE_ADDRS { APBH_BASE } +/** Array initializer of APBH peripheral base pointers */ +#define APBH_BASE_PTRS { APBH } +/** Interrupt vectors for the APBH peripheral type */ +#define APBH_IRQS { APBH_IRQn } + +/*! + * @} + */ /* end of group APBH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ASRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer + * @{ + */ + +/** ASRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t ASRCTR; /**< ASRC Control Register, offset: 0x0 */ + __IO uint32_t ASRIER; /**< ASRC Interrupt Enable Register, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ASRCNCR; /**< ASRC Channel Number Configuration Register, offset: 0xC */ + __IO uint32_t ASRCFG; /**< ASRC Filter Configuration Status Register, offset: 0x10 */ + __IO uint32_t ASRCSR; /**< ASRC Clock Source Register, offset: 0x14 */ + __IO uint32_t ASRCDR1; /**< ASRC Clock Divider Register 1, offset: 0x18 */ + __IO uint32_t ASRCDR2; /**< ASRC Clock Divider Register 2, offset: 0x1C */ + __I uint32_t ASRSTR; /**< ASRC Status Register, offset: 0x20 */ + uint8_t RESERVED_1[28]; + __IO uint32_t ASRPMn[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */ + __IO uint32_t ASRTFR1; /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */ + uint8_t RESERVED_2[4]; + __IO uint32_t ASRCCR; /**< ASRC Channel Counter Register, offset: 0x5C */ + __IO uint32_t ASRDIA; /**< ASRC Data Input Register for Pair x, offset: 0x60 */ + __I uint32_t ASRDOA; /**< ASRC Data Output Register for Pair x, offset: 0x64 */ + __IO uint32_t ASRDIB; /**< ASRC Data Input Register for Pair x, offset: 0x68 */ + __I uint32_t ASRDOB; /**< ASRC Data Output Register for Pair x, offset: 0x6C */ + __IO uint32_t ASRDIC; /**< ASRC Data Input Register for Pair x, offset: 0x70 */ + __I uint32_t ASRDOC; /**< ASRC Data Output Register for Pair x, offset: 0x74 */ + uint8_t RESERVED_3[8]; + __IO uint32_t ASRIDRHA; /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */ + __IO uint32_t ASRIDRLA; /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */ + __IO uint32_t ASRIDRHB; /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */ + __IO uint32_t ASRIDRLB; /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */ + __IO uint32_t ASRIDRHC; /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */ + __IO uint32_t ASRIDRLC; /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */ + __IO uint32_t ASR76K; /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */ + __IO uint32_t ASR56K; /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */ + __IO uint32_t ASRMCRA; /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */ + __I uint32_t ASRFSTA; /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */ + __IO uint32_t ASRMCRB; /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */ + __I uint32_t ASRFSTB; /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */ + __IO uint32_t ASRMCRC; /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */ + __I uint32_t ASRFSTC; /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */ + uint8_t RESERVED_4[8]; + __IO uint32_t ASRMCR1[3]; /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */ +} ASRC_Type; + +/* ---------------------------------------------------------------------------- + -- ASRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASRC_Register_Masks ASRC Register Masks + * @{ + */ + +/*! @name ASRCTR - ASRC Control Register */ +#define ASRC_ASRCTR_ASRCEN_MASK (0x1U) +#define ASRC_ASRCTR_ASRCEN_SHIFT (0U) +#define ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK) +#define ASRC_ASRCTR_ASREA_MASK (0x2U) +#define ASRC_ASRCTR_ASREA_SHIFT (1U) +#define ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK) +#define ASRC_ASRCTR_ASREB_MASK (0x4U) +#define ASRC_ASRCTR_ASREB_SHIFT (2U) +#define ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK) +#define ASRC_ASRCTR_ASREC_MASK (0x8U) +#define ASRC_ASRCTR_ASREC_SHIFT (3U) +#define ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK) +#define ASRC_ASRCTR_SRST_MASK (0x10U) +#define ASRC_ASRCTR_SRST_SHIFT (4U) +#define ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK) +#define ASRC_ASRCTR_IDRA_MASK (0x2000U) +#define ASRC_ASRCTR_IDRA_SHIFT (13U) +#define ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK) +#define ASRC_ASRCTR_USRA_MASK (0x4000U) +#define ASRC_ASRCTR_USRA_SHIFT (14U) +#define ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK) +#define ASRC_ASRCTR_IDRB_MASK (0x8000U) +#define ASRC_ASRCTR_IDRB_SHIFT (15U) +#define ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK) +#define ASRC_ASRCTR_USRB_MASK (0x10000U) +#define ASRC_ASRCTR_USRB_SHIFT (16U) +#define ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK) +#define ASRC_ASRCTR_IDRC_MASK (0x20000U) +#define ASRC_ASRCTR_IDRC_SHIFT (17U) +#define ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK) +#define ASRC_ASRCTR_USRC_MASK (0x40000U) +#define ASRC_ASRCTR_USRC_SHIFT (18U) +#define ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK) +#define ASRC_ASRCTR_ATSA_MASK (0x100000U) +#define ASRC_ASRCTR_ATSA_SHIFT (20U) +#define ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK) +#define ASRC_ASRCTR_ATSB_MASK (0x200000U) +#define ASRC_ASRCTR_ATSB_SHIFT (21U) +#define ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK) +#define ASRC_ASRCTR_ATSC_MASK (0x400000U) +#define ASRC_ASRCTR_ATSC_SHIFT (22U) +#define ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK) + +/*! @name ASRIER - ASRC Interrupt Enable Register */ +#define ASRC_ASRIER_ADIEA_MASK (0x1U) +#define ASRC_ASRIER_ADIEA_SHIFT (0U) +#define ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK) +#define ASRC_ASRIER_ADIEB_MASK (0x2U) +#define ASRC_ASRIER_ADIEB_SHIFT (1U) +#define ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK) +#define ASRC_ASRIER_ADIEC_MASK (0x4U) +#define ASRC_ASRIER_ADIEC_SHIFT (2U) +#define ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK) +#define ASRC_ASRIER_ADOEA_MASK (0x8U) +#define ASRC_ASRIER_ADOEA_SHIFT (3U) +#define ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK) +#define ASRC_ASRIER_ADOEB_MASK (0x10U) +#define ASRC_ASRIER_ADOEB_SHIFT (4U) +#define ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK) +#define ASRC_ASRIER_ADOEC_MASK (0x20U) +#define ASRC_ASRIER_ADOEC_SHIFT (5U) +#define ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK) +#define ASRC_ASRIER_AOLIE_MASK (0x40U) +#define ASRC_ASRIER_AOLIE_SHIFT (6U) +#define ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK) +#define ASRC_ASRIER_AFPWE_MASK (0x80U) +#define ASRC_ASRIER_AFPWE_SHIFT (7U) +#define ASRC_ASRIER_AFPWE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK) + +/*! @name ASRCNCR - ASRC Channel Number Configuration Register */ +#define ASRC_ASRCNCR_ANCA_MASK (0xFU) +#define ASRC_ASRCNCR_ANCA_SHIFT (0U) +#define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK) +#define ASRC_ASRCNCR_ANCB_MASK (0xF0U) +#define ASRC_ASRCNCR_ANCB_SHIFT (4U) +#define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK) +#define ASRC_ASRCNCR_ANCC_MASK (0xF00U) +#define ASRC_ASRCNCR_ANCC_SHIFT (8U) +#define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK) + +/*! @name ASRCFG - ASRC Filter Configuration Status Register */ +#define ASRC_ASRCFG_PREMODA_MASK (0xC0U) +#define ASRC_ASRCFG_PREMODA_SHIFT (6U) +#define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK) +#define ASRC_ASRCFG_POSTMODA_MASK (0x300U) +#define ASRC_ASRCFG_POSTMODA_SHIFT (8U) +#define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK) +#define ASRC_ASRCFG_PREMODB_MASK (0xC00U) +#define ASRC_ASRCFG_PREMODB_SHIFT (10U) +#define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK) +#define ASRC_ASRCFG_POSTMODB_MASK (0x3000U) +#define ASRC_ASRCFG_POSTMODB_SHIFT (12U) +#define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK) +#define ASRC_ASRCFG_PREMODC_MASK (0xC000U) +#define ASRC_ASRCFG_PREMODC_SHIFT (14U) +#define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK) +#define ASRC_ASRCFG_POSTMODC_MASK (0x30000U) +#define ASRC_ASRCFG_POSTMODC_SHIFT (16U) +#define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK) +#define ASRC_ASRCFG_NDPRA_MASK (0x40000U) +#define ASRC_ASRCFG_NDPRA_SHIFT (18U) +#define ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK) +#define ASRC_ASRCFG_NDPRB_MASK (0x80000U) +#define ASRC_ASRCFG_NDPRB_SHIFT (19U) +#define ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK) +#define ASRC_ASRCFG_NDPRC_MASK (0x100000U) +#define ASRC_ASRCFG_NDPRC_SHIFT (20U) +#define ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK) +#define ASRC_ASRCFG_INIRQA_MASK (0x200000U) +#define ASRC_ASRCFG_INIRQA_SHIFT (21U) +#define ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK) +#define ASRC_ASRCFG_INIRQB_MASK (0x400000U) +#define ASRC_ASRCFG_INIRQB_SHIFT (22U) +#define ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK) +#define ASRC_ASRCFG_INIRQC_MASK (0x800000U) +#define ASRC_ASRCFG_INIRQC_SHIFT (23U) +#define ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK) + +/*! @name ASRCSR - ASRC Clock Source Register */ +#define ASRC_ASRCSR_AICSA_MASK (0xFU) +#define ASRC_ASRCSR_AICSA_SHIFT (0U) +#define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK) +#define ASRC_ASRCSR_AICSB_MASK (0xF0U) +#define ASRC_ASRCSR_AICSB_SHIFT (4U) +#define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK) +#define ASRC_ASRCSR_AICSC_MASK (0xF00U) +#define ASRC_ASRCSR_AICSC_SHIFT (8U) +#define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK) +#define ASRC_ASRCSR_AOCSA_MASK (0xF000U) +#define ASRC_ASRCSR_AOCSA_SHIFT (12U) +#define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK) +#define ASRC_ASRCSR_AOCSB_MASK (0xF0000U) +#define ASRC_ASRCSR_AOCSB_SHIFT (16U) +#define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK) +#define ASRC_ASRCSR_AOCSC_MASK (0xF00000U) +#define ASRC_ASRCSR_AOCSC_SHIFT (20U) +#define ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK) + +/*! @name ASRCDR1 - ASRC Clock Divider Register 1 */ +#define ASRC_ASRCDR1_AICPA_MASK (0x7U) +#define ASRC_ASRCDR1_AICPA_SHIFT (0U) +#define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK) +#define ASRC_ASRCDR1_AICDA_MASK (0x38U) +#define ASRC_ASRCDR1_AICDA_SHIFT (3U) +#define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK) +#define ASRC_ASRCDR1_AICPB_MASK (0x1C0U) +#define ASRC_ASRCDR1_AICPB_SHIFT (6U) +#define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK) +#define ASRC_ASRCDR1_AICDB_MASK (0xE00U) +#define ASRC_ASRCDR1_AICDB_SHIFT (9U) +#define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK) +#define ASRC_ASRCDR1_AOCPA_MASK (0x7000U) +#define ASRC_ASRCDR1_AOCPA_SHIFT (12U) +#define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK) +#define ASRC_ASRCDR1_AOCDA_MASK (0x38000U) +#define ASRC_ASRCDR1_AOCDA_SHIFT (15U) +#define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK) +#define ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U) +#define ASRC_ASRCDR1_AOCPB_SHIFT (18U) +#define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK) +#define ASRC_ASRCDR1_AOCDB_MASK (0xE00000U) +#define ASRC_ASRCDR1_AOCDB_SHIFT (21U) +#define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK) + +/*! @name ASRCDR2 - ASRC Clock Divider Register 2 */ +#define ASRC_ASRCDR2_AICPC_MASK (0x7U) +#define ASRC_ASRCDR2_AICPC_SHIFT (0U) +#define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK) +#define ASRC_ASRCDR2_AICDC_MASK (0x38U) +#define ASRC_ASRCDR2_AICDC_SHIFT (3U) +#define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK) +#define ASRC_ASRCDR2_AOCPC_MASK (0x1C0U) +#define ASRC_ASRCDR2_AOCPC_SHIFT (6U) +#define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK) +#define ASRC_ASRCDR2_AOCDC_MASK (0xE00U) +#define ASRC_ASRCDR2_AOCDC_SHIFT (9U) +#define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK) + +/*! @name ASRSTR - ASRC Status Register */ +#define ASRC_ASRSTR_AIDEA_MASK (0x1U) +#define ASRC_ASRSTR_AIDEA_SHIFT (0U) +#define ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK) +#define ASRC_ASRSTR_AIDEB_MASK (0x2U) +#define ASRC_ASRSTR_AIDEB_SHIFT (1U) +#define ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK) +#define ASRC_ASRSTR_AIDEC_MASK (0x4U) +#define ASRC_ASRSTR_AIDEC_SHIFT (2U) +#define ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK) +#define ASRC_ASRSTR_AODFA_MASK (0x8U) +#define ASRC_ASRSTR_AODFA_SHIFT (3U) +#define ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK) +#define ASRC_ASRSTR_AODFB_MASK (0x10U) +#define ASRC_ASRSTR_AODFB_SHIFT (4U) +#define ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK) +#define ASRC_ASRSTR_AODFC_MASK (0x20U) +#define ASRC_ASRSTR_AODFC_SHIFT (5U) +#define ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK) +#define ASRC_ASRSTR_AOLE_MASK (0x40U) +#define ASRC_ASRSTR_AOLE_SHIFT (6U) +#define ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK) +#define ASRC_ASRSTR_FPWT_MASK (0x80U) +#define ASRC_ASRSTR_FPWT_SHIFT (7U) +#define ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK) +#define ASRC_ASRSTR_AIDUA_MASK (0x100U) +#define ASRC_ASRSTR_AIDUA_SHIFT (8U) +#define ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK) +#define ASRC_ASRSTR_AIDUB_MASK (0x200U) +#define ASRC_ASRSTR_AIDUB_SHIFT (9U) +#define ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK) +#define ASRC_ASRSTR_AIDUC_MASK (0x400U) +#define ASRC_ASRSTR_AIDUC_SHIFT (10U) +#define ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK) +#define ASRC_ASRSTR_AODOA_MASK (0x800U) +#define ASRC_ASRSTR_AODOA_SHIFT (11U) +#define ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK) +#define ASRC_ASRSTR_AODOB_MASK (0x1000U) +#define ASRC_ASRSTR_AODOB_SHIFT (12U) +#define ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK) +#define ASRC_ASRSTR_AODOC_MASK (0x2000U) +#define ASRC_ASRSTR_AODOC_SHIFT (13U) +#define ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK) +#define ASRC_ASRSTR_AIOLA_MASK (0x4000U) +#define ASRC_ASRSTR_AIOLA_SHIFT (14U) +#define ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK) +#define ASRC_ASRSTR_AIOLB_MASK (0x8000U) +#define ASRC_ASRSTR_AIOLB_SHIFT (15U) +#define ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK) +#define ASRC_ASRSTR_AIOLC_MASK (0x10000U) +#define ASRC_ASRSTR_AIOLC_SHIFT (16U) +#define ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK) +#define ASRC_ASRSTR_AOOLA_MASK (0x20000U) +#define ASRC_ASRSTR_AOOLA_SHIFT (17U) +#define ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK) +#define ASRC_ASRSTR_AOOLB_MASK (0x40000U) +#define ASRC_ASRSTR_AOOLB_SHIFT (18U) +#define ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK) +#define ASRC_ASRSTR_AOOLC_MASK (0x80000U) +#define ASRC_ASRSTR_AOOLC_SHIFT (19U) +#define ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK) +#define ASRC_ASRSTR_ATQOL_MASK (0x100000U) +#define ASRC_ASRSTR_ATQOL_SHIFT (20U) +#define ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK) +#define ASRC_ASRSTR_DSLCNT_MASK (0x200000U) +#define ASRC_ASRSTR_DSLCNT_SHIFT (21U) +#define ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK) + +/*! @name ASRPMn - ASRC Parameter Register n */ +#define ASRC_ASRPMn_PARAMETER_VALUE_MASK (0xFFFFFFU) +#define ASRC_ASRPMn_PARAMETER_VALUE_SHIFT (0U) +#define ASRC_ASRPMn_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPMn_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPMn_PARAMETER_VALUE_MASK) + +/* The count of ASRC_ASRPMn */ +#define ASRC_ASRPMn_COUNT (5U) + +/*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */ +#define ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U) +#define ASRC_ASRTFR1_TF_BASE_SHIFT (6U) +#define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK) +#define ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U) +#define ASRC_ASRTFR1_TF_FILL_SHIFT (13U) +#define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK) + +/*! @name ASRCCR - ASRC Channel Counter Register */ +#define ASRC_ASRCCR_ACIA_MASK (0xFU) +#define ASRC_ASRCCR_ACIA_SHIFT (0U) +#define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK) +#define ASRC_ASRCCR_ACIB_MASK (0xF0U) +#define ASRC_ASRCCR_ACIB_SHIFT (4U) +#define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK) +#define ASRC_ASRCCR_ACIC_MASK (0xF00U) +#define ASRC_ASRCCR_ACIC_SHIFT (8U) +#define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK) +#define ASRC_ASRCCR_ACOA_MASK (0xF000U) +#define ASRC_ASRCCR_ACOA_SHIFT (12U) +#define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK) +#define ASRC_ASRCCR_ACOB_MASK (0xF0000U) +#define ASRC_ASRCCR_ACOB_SHIFT (16U) +#define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK) +#define ASRC_ASRCCR_ACOC_MASK (0xF00000U) +#define ASRC_ASRCCR_ACOC_SHIFT (20U) +#define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK) + +/*! @name ASRDIA - ASRC Data Input Register for Pair x */ +#define ASRC_ASRDIA_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDIA_DATA_SHIFT (0U) +#define ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK) + +/*! @name ASRDOA - ASRC Data Output Register for Pair x */ +#define ASRC_ASRDOA_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDOA_DATA_SHIFT (0U) +#define ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK) + +/*! @name ASRDIB - ASRC Data Input Register for Pair x */ +#define ASRC_ASRDIB_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDIB_DATA_SHIFT (0U) +#define ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK) + +/*! @name ASRDOB - ASRC Data Output Register for Pair x */ +#define ASRC_ASRDOB_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDOB_DATA_SHIFT (0U) +#define ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK) + +/*! @name ASRDIC - ASRC Data Input Register for Pair x */ +#define ASRC_ASRDIC_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDIC_DATA_SHIFT (0U) +#define ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK) + +/*! @name ASRDOC - ASRC Data Output Register for Pair x */ +#define ASRC_ASRDOC_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDOC_DATA_SHIFT (0U) +#define ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK) + +/*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */ +#define ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU) +#define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U) +#define ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK) + +/*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */ +#define ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU) +#define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U) +#define ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK) + +/*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */ +#define ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU) +#define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U) +#define ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK) + +/*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */ +#define ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU) +#define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U) +#define ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK) + +/*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */ +#define ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU) +#define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U) +#define ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK) + +/*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */ +#define ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU) +#define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U) +#define ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK) + +/*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */ +#define ASRC_ASR76K_ASR76K_MASK (0x1FFFFU) +#define ASRC_ASR76K_ASR76K_SHIFT (0U) +#define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK) + +/*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */ +#define ASRC_ASR56K_ASR56K_MASK (0x1FFFFU) +#define ASRC_ASR56K_ASR56K_SHIFT (0U) +#define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK) + +/*! @name ASRMCRA - ASRC Misc Control Register for Pair A */ +#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU) +#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U) +#define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK) +#define ASRC_ASRMCRA_RSYNOFA_MASK (0x400U) +#define ASRC_ASRMCRA_RSYNOFA_SHIFT (10U) +#define ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK) +#define ASRC_ASRMCRA_RSYNIFA_MASK (0x800U) +#define ASRC_ASRMCRA_RSYNIFA_SHIFT (11U) +#define ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK) +#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U) +#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U) +#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK) +#define ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U) +#define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U) +#define ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK) +#define ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U) +#define ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U) +#define ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK) +#define ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U) +#define ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U) +#define ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK) +#define ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U) +#define ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U) +#define ASRC_ASRMCRA_ZEROBUFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK) + +/*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */ +#define ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU) +#define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U) +#define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK) +#define ASRC_ASRFSTA_IAEA_MASK (0x800U) +#define ASRC_ASRFSTA_IAEA_SHIFT (11U) +#define ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK) +#define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U) +#define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U) +#define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK) +#define ASRC_ASRFSTA_OAFA_MASK (0x800000U) +#define ASRC_ASRFSTA_OAFA_SHIFT (23U) +#define ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK) + +/*! @name ASRMCRB - ASRC Misc Control Register for Pair B */ +#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU) +#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U) +#define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK) +#define ASRC_ASRMCRB_RSYNOFB_MASK (0x400U) +#define ASRC_ASRMCRB_RSYNOFB_SHIFT (10U) +#define ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK) +#define ASRC_ASRMCRB_RSYNIFB_MASK (0x800U) +#define ASRC_ASRMCRB_RSYNIFB_SHIFT (11U) +#define ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK) +#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U) +#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U) +#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK) +#define ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U) +#define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U) +#define ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK) +#define ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U) +#define ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U) +#define ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK) +#define ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U) +#define ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U) +#define ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK) +#define ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U) +#define ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U) +#define ASRC_ASRMCRB_ZEROBUFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK) + +/*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */ +#define ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU) +#define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U) +#define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK) +#define ASRC_ASRFSTB_IAEB_MASK (0x800U) +#define ASRC_ASRFSTB_IAEB_SHIFT (11U) +#define ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK) +#define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U) +#define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U) +#define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK) +#define ASRC_ASRFSTB_OAFB_MASK (0x800000U) +#define ASRC_ASRFSTB_OAFB_SHIFT (23U) +#define ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK) + +/*! @name ASRMCRC - ASRC Misc Control Register for Pair C */ +#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU) +#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U) +#define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK) +#define ASRC_ASRMCRC_RSYNOFC_MASK (0x400U) +#define ASRC_ASRMCRC_RSYNOFC_SHIFT (10U) +#define ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK) +#define ASRC_ASRMCRC_RSYNIFC_MASK (0x800U) +#define ASRC_ASRMCRC_RSYNIFC_SHIFT (11U) +#define ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK) +#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U) +#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U) +#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK) +#define ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U) +#define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U) +#define ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK) +#define ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U) +#define ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U) +#define ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK) +#define ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U) +#define ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U) +#define ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK) +#define ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U) +#define ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U) +#define ASRC_ASRMCRC_ZEROBUFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK) + +/*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */ +#define ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU) +#define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U) +#define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK) +#define ASRC_ASRFSTC_IAEC_MASK (0x800U) +#define ASRC_ASRFSTC_IAEC_SHIFT (11U) +#define ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK) +#define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U) +#define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U) +#define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK) +#define ASRC_ASRFSTC_OAFC_MASK (0x800000U) +#define ASRC_ASRFSTC_OAFC_SHIFT (23U) +#define ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK) + +/*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */ +#define ASRC_ASRMCR1_OW16_MASK (0x1U) +#define ASRC_ASRMCR1_OW16_SHIFT (0U) +#define ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK) +#define ASRC_ASRMCR1_OSGN_MASK (0x2U) +#define ASRC_ASRMCR1_OSGN_SHIFT (1U) +#define ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK) +#define ASRC_ASRMCR1_OMSB_MASK (0x4U) +#define ASRC_ASRMCR1_OMSB_SHIFT (2U) +#define ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK) +#define ASRC_ASRMCR1_IMSB_MASK (0x100U) +#define ASRC_ASRMCR1_IMSB_SHIFT (8U) +#define ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK) +#define ASRC_ASRMCR1_IWD_MASK (0xE00U) +#define ASRC_ASRMCR1_IWD_SHIFT (9U) +#define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK) + +/* The count of ASRC_ASRMCR1 */ +#define ASRC_ASRMCR1_COUNT (3U) + + +/*! + * @} + */ /* end of group ASRC_Register_Masks */ + + +/* ASRC - Peripheral instance base addresses */ +/** Peripheral ASRC base address */ +#define ASRC_BASE (0x2034000u) +/** Peripheral ASRC base pointer */ +#define ASRC ((ASRC_Type *)ASRC_BASE) +/** Array initializer of ASRC peripheral base addresses */ +#define ASRC_BASE_ADDRS { ASRC_BASE } +/** Array initializer of ASRC peripheral base pointers */ +#define ASRC_BASE_PTRS { ASRC } +/** Interrupt vectors for the ASRC peripheral type */ +#define ASRC_IRQS { ASRC_IRQn } + +/*! + * @} + */ /* end of group ASRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BCH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer + * @{ + */ + +/** BCH - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */ + __I uint32_t STATUS0; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */ + __I uint32_t STATUS0_SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */ + __I uint32_t STATUS0_CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */ + __I uint32_t STATUS0_TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */ + __IO uint32_t MODE; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */ + __IO uint32_t MODE_SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */ + __IO uint32_t MODE_CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */ + __IO uint32_t MODE_TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */ + __IO uint32_t ENCODEPTR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */ + __IO uint32_t ENCODEPTR_SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */ + __IO uint32_t ENCODEPTR_CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */ + __IO uint32_t ENCODEPTR_TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */ + __IO uint32_t DATAPTR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */ + __IO uint32_t DATAPTR_SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */ + __IO uint32_t DATAPTR_CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */ + __IO uint32_t DATAPTR_TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */ + __IO uint32_t METAPTR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */ + __IO uint32_t METAPTR_SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */ + __IO uint32_t METAPTR_CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */ + __IO uint32_t METAPTR_TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */ + uint8_t RESERVED_0[16]; + __IO uint32_t LAYOUTSELECT; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */ + __IO uint32_t LAYOUTSELECT_SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */ + __IO uint32_t LAYOUTSELECT_CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */ + __IO uint32_t LAYOUTSELECT_TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */ + __IO uint32_t FLASH0LAYOUT0; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */ + __IO uint32_t FLASH0LAYOUT0_SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */ + __IO uint32_t FLASH0LAYOUT0_CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */ + __IO uint32_t FLASH0LAYOUT0_TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */ + __IO uint32_t FLASH0LAYOUT1; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */ + __IO uint32_t FLASH0LAYOUT1_SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */ + __IO uint32_t FLASH0LAYOUT1_CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */ + __IO uint32_t FLASH0LAYOUT1_TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */ + __IO uint32_t FLASH1LAYOUT0; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */ + __IO uint32_t FLASH1LAYOUT0_SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */ + __IO uint32_t FLASH1LAYOUT0_CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */ + __IO uint32_t FLASH1LAYOUT0_TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */ + __IO uint32_t FLASH1LAYOUT1; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */ + __IO uint32_t FLASH1LAYOUT1_SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */ + __IO uint32_t FLASH1LAYOUT1_CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */ + __IO uint32_t FLASH1LAYOUT1_TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */ + __IO uint32_t FLASH2LAYOUT0; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */ + __IO uint32_t FLASH2LAYOUT0_SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */ + __IO uint32_t FLASH2LAYOUT0_CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */ + __IO uint32_t FLASH2LAYOUT0_TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */ + __IO uint32_t FLASH2LAYOUT1; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */ + __IO uint32_t FLASH2LAYOUT1_SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */ + __IO uint32_t FLASH2LAYOUT1_CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */ + __IO uint32_t FLASH2LAYOUT1_TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */ + __IO uint32_t FLASH3LAYOUT0; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */ + __IO uint32_t FLASH3LAYOUT0_SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */ + __IO uint32_t FLASH3LAYOUT0_CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */ + __IO uint32_t FLASH3LAYOUT0_TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */ + __IO uint32_t FLASH3LAYOUT1; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */ + __IO uint32_t FLASH3LAYOUT1_SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */ + __IO uint32_t FLASH3LAYOUT1_CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */ + __IO uint32_t FLASH3LAYOUT1_TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */ + __IO uint32_t DEBUG0; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */ + __IO uint32_t DEBUG0_SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */ + __IO uint32_t DEBUG0_CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */ + __IO uint32_t DEBUG0_TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */ + __I uint32_t DBGKESREAD; /**< KES Debug Read Register, offset: 0x110 */ + __I uint32_t DBGKESREAD_SET; /**< KES Debug Read Register, offset: 0x114 */ + __I uint32_t DBGKESREAD_CLR; /**< KES Debug Read Register, offset: 0x118 */ + __I uint32_t DBGKESREAD_TOG; /**< KES Debug Read Register, offset: 0x11C */ + __I uint32_t DBGCSFEREAD; /**< Chien Search Debug Read Register, offset: 0x120 */ + __I uint32_t DBGCSFEREAD_SET; /**< Chien Search Debug Read Register, offset: 0x124 */ + __I uint32_t DBGCSFEREAD_CLR; /**< Chien Search Debug Read Register, offset: 0x128 */ + __I uint32_t DBGCSFEREAD_TOG; /**< Chien Search Debug Read Register, offset: 0x12C */ + __I uint32_t DBGSYNDGENREAD; /**< Syndrome Generator Debug Read Register, offset: 0x130 */ + __I uint32_t DBGSYNDGENREAD_SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */ + __I uint32_t DBGSYNDGENREAD_CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */ + __I uint32_t DBGSYNDGENREAD_TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */ + __I uint32_t DBGAHBMREAD; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */ + __I uint32_t DBGAHBMREAD_SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */ + __I uint32_t DBGAHBMREAD_CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */ + __I uint32_t DBGAHBMREAD_TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */ + __I uint32_t BLOCKNAME; /**< Block Name Register, offset: 0x150 */ + __I uint32_t BLOCKNAME_SET; /**< Block Name Register, offset: 0x154 */ + __I uint32_t BLOCKNAME_CLR; /**< Block Name Register, offset: 0x158 */ + __I uint32_t BLOCKNAME_TOG; /**< Block Name Register, offset: 0x15C */ + __I uint32_t VERSION; /**< BCH Version Register, offset: 0x160 */ + __I uint32_t VERSION_SET; /**< BCH Version Register, offset: 0x164 */ + __I uint32_t VERSION_CLR; /**< BCH Version Register, offset: 0x168 */ + __I uint32_t VERSION_TOG; /**< BCH Version Register, offset: 0x16C */ + __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */ + __IO uint32_t DEBUG1_SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */ + __IO uint32_t DEBUG1_CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */ + __IO uint32_t DEBUG1_TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */ +} BCH_Type; + +/* ---------------------------------------------------------------------------- + -- BCH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Register_Masks BCH Register Masks + * @{ + */ + +/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK) +#define BCH_CTRL_RSVD0_MASK (0x2U) +#define BCH_CTRL_RSVD0_SHIFT (1U) +#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK) +#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_RSVD1_MASK (0xF0U) +#define BCH_CTRL_RSVD1_SHIFT (4U) +#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK) +#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_RSVD2_MASK (0x200U) +#define BCH_CTRL_RSVD2_SHIFT (9U) +#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_RSVD3_MASK (0xF800U) +#define BCH_CTRL_RSVD3_SHIFT (11U) +#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK) +#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK) +#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK) +#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK) +#define BCH_CTRL_RSVD4_MASK (0x300000U) +#define BCH_CTRL_RSVD4_SHIFT (20U) +#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK) +#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK) +#define BCH_CTRL_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_RSVD5_SHIFT (23U) +#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK) +#define BCH_CTRL_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_CLKGATE_SHIFT (30U) +#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK) +#define BCH_CTRL_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_SFTRST_SHIFT (31U) +#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_SET_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_SET_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_MASK) +#define BCH_CTRL_SET_RSVD0_MASK (0x2U) +#define BCH_CTRL_SET_RSVD0_SHIFT (1U) +#define BCH_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD0_SHIFT)) & BCH_CTRL_SET_RSVD0_MASK) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_SET_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_SET_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_SET_RSVD1_MASK (0xF0U) +#define BCH_CTRL_SET_RSVD1_SHIFT (4U) +#define BCH_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD1_SHIFT)) & BCH_CTRL_SET_RSVD1_MASK) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_SET_RSVD2_MASK (0x200U) +#define BCH_CTRL_SET_RSVD2_SHIFT (9U) +#define BCH_CTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD2_SHIFT)) & BCH_CTRL_SET_RSVD2_MASK) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_SET_RSVD3_MASK (0xF800U) +#define BCH_CTRL_SET_RSVD3_SHIFT (11U) +#define BCH_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD3_SHIFT)) & BCH_CTRL_SET_RSVD3_MASK) +#define BCH_CTRL_SET_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_SET_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_SET_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENABLE_SHIFT)) & BCH_CTRL_SET_M2M_ENABLE_MASK) +#define BCH_CTRL_SET_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_SET_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_SET_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENCODE_SHIFT)) & BCH_CTRL_SET_M2M_ENCODE_MASK) +#define BCH_CTRL_SET_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_SET_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_SET_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_LAYOUT_SHIFT)) & BCH_CTRL_SET_M2M_LAYOUT_MASK) +#define BCH_CTRL_SET_RSVD4_MASK (0x300000U) +#define BCH_CTRL_SET_RSVD4_SHIFT (20U) +#define BCH_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD4_SHIFT)) & BCH_CTRL_SET_RSVD4_MASK) +#define BCH_CTRL_SET_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_SET_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_SET_DEBUGSYNDROME_MASK) +#define BCH_CTRL_SET_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_SET_RSVD5_SHIFT (23U) +#define BCH_CTRL_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD5_SHIFT)) & BCH_CTRL_SET_RSVD5_MASK) +#define BCH_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_SET_CLKGATE_SHIFT (30U) +#define BCH_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_CLKGATE_SHIFT)) & BCH_CTRL_SET_CLKGATE_MASK) +#define BCH_CTRL_SET_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_SET_SFTRST_SHIFT (31U) +#define BCH_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_SFTRST_SHIFT)) & BCH_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_CLR_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_CLR_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_MASK) +#define BCH_CTRL_CLR_RSVD0_MASK (0x2U) +#define BCH_CTRL_CLR_RSVD0_SHIFT (1U) +#define BCH_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD0_SHIFT)) & BCH_CTRL_CLR_RSVD0_MASK) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_CLR_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_CLR_RSVD1_MASK (0xF0U) +#define BCH_CTRL_CLR_RSVD1_SHIFT (4U) +#define BCH_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD1_SHIFT)) & BCH_CTRL_CLR_RSVD1_MASK) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_CLR_RSVD2_MASK (0x200U) +#define BCH_CTRL_CLR_RSVD2_SHIFT (9U) +#define BCH_CTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD2_SHIFT)) & BCH_CTRL_CLR_RSVD2_MASK) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_CLR_RSVD3_MASK (0xF800U) +#define BCH_CTRL_CLR_RSVD3_SHIFT (11U) +#define BCH_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD3_SHIFT)) & BCH_CTRL_CLR_RSVD3_MASK) +#define BCH_CTRL_CLR_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_CLR_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_CLR_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENABLE_SHIFT)) & BCH_CTRL_CLR_M2M_ENABLE_MASK) +#define BCH_CTRL_CLR_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_CLR_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_CLR_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENCODE_SHIFT)) & BCH_CTRL_CLR_M2M_ENCODE_MASK) +#define BCH_CTRL_CLR_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_CLR_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_LAYOUT_SHIFT)) & BCH_CTRL_CLR_M2M_LAYOUT_MASK) +#define BCH_CTRL_CLR_RSVD4_MASK (0x300000U) +#define BCH_CTRL_CLR_RSVD4_SHIFT (20U) +#define BCH_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD4_SHIFT)) & BCH_CTRL_CLR_RSVD4_MASK) +#define BCH_CTRL_CLR_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_CLR_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_CLR_DEBUGSYNDROME_MASK) +#define BCH_CTRL_CLR_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_CLR_RSVD5_SHIFT (23U) +#define BCH_CTRL_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD5_SHIFT)) & BCH_CTRL_CLR_RSVD5_MASK) +#define BCH_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_CLR_CLKGATE_SHIFT (30U) +#define BCH_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_CLKGATE_SHIFT)) & BCH_CTRL_CLR_CLKGATE_MASK) +#define BCH_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_CLR_SFTRST_SHIFT (31U) +#define BCH_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_SFTRST_SHIFT)) & BCH_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_TOG_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_TOG_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_MASK) +#define BCH_CTRL_TOG_RSVD0_MASK (0x2U) +#define BCH_CTRL_TOG_RSVD0_SHIFT (1U) +#define BCH_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD0_SHIFT)) & BCH_CTRL_TOG_RSVD0_MASK) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_TOG_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_TOG_RSVD1_MASK (0xF0U) +#define BCH_CTRL_TOG_RSVD1_SHIFT (4U) +#define BCH_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD1_SHIFT)) & BCH_CTRL_TOG_RSVD1_MASK) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_TOG_RSVD2_MASK (0x200U) +#define BCH_CTRL_TOG_RSVD2_SHIFT (9U) +#define BCH_CTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD2_SHIFT)) & BCH_CTRL_TOG_RSVD2_MASK) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_TOG_RSVD3_MASK (0xF800U) +#define BCH_CTRL_TOG_RSVD3_SHIFT (11U) +#define BCH_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD3_SHIFT)) & BCH_CTRL_TOG_RSVD3_MASK) +#define BCH_CTRL_TOG_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_TOG_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_TOG_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENABLE_SHIFT)) & BCH_CTRL_TOG_M2M_ENABLE_MASK) +#define BCH_CTRL_TOG_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_TOG_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_TOG_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENCODE_SHIFT)) & BCH_CTRL_TOG_M2M_ENCODE_MASK) +#define BCH_CTRL_TOG_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_TOG_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_LAYOUT_SHIFT)) & BCH_CTRL_TOG_M2M_LAYOUT_MASK) +#define BCH_CTRL_TOG_RSVD4_MASK (0x300000U) +#define BCH_CTRL_TOG_RSVD4_SHIFT (20U) +#define BCH_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD4_SHIFT)) & BCH_CTRL_TOG_RSVD4_MASK) +#define BCH_CTRL_TOG_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_TOG_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_TOG_DEBUGSYNDROME_MASK) +#define BCH_CTRL_TOG_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_TOG_RSVD5_SHIFT (23U) +#define BCH_CTRL_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD5_SHIFT)) & BCH_CTRL_TOG_RSVD5_MASK) +#define BCH_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_TOG_CLKGATE_SHIFT (30U) +#define BCH_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_CLKGATE_SHIFT)) & BCH_CTRL_TOG_CLKGATE_MASK) +#define BCH_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_TOG_SFTRST_SHIFT (31U) +#define BCH_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_SFTRST_SHIFT)) & BCH_CTRL_TOG_SFTRST_MASK) + +/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_RSVD0_MASK (0x3U) +#define BCH_STATUS0_RSVD0_SHIFT (0U) +#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK) +#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK) +#define BCH_STATUS0_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK) +#define BCH_STATUS0_ALLONES_MASK (0x10U) +#define BCH_STATUS0_ALLONES_SHIFT (4U) +#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK) +#define BCH_STATUS0_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_RSVD1_SHIFT (5U) +#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK) +#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK) +#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK) +#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_HANDLE_SHIFT (20U) +#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK) + +/*! @name STATUS0_SET - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_SET_RSVD0_MASK (0x3U) +#define BCH_STATUS0_SET_RSVD0_SHIFT (0U) +#define BCH_STATUS0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_RSVD0_SHIFT)) & BCH_STATUS0_SET_RSVD0_MASK) +#define BCH_STATUS0_SET_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_SET_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_SET_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_SET_UNCORRECTABLE_MASK) +#define BCH_STATUS0_SET_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_SET_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_SET_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_CORRECTED_SHIFT)) & BCH_STATUS0_SET_CORRECTED_MASK) +#define BCH_STATUS0_SET_ALLONES_MASK (0x10U) +#define BCH_STATUS0_SET_ALLONES_SHIFT (4U) +#define BCH_STATUS0_SET_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_ALLONES_SHIFT)) & BCH_STATUS0_SET_ALLONES_MASK) +#define BCH_STATUS0_SET_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_SET_RSVD1_SHIFT (5U) +#define BCH_STATUS0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_RSVD1_SHIFT)) & BCH_STATUS0_SET_RSVD1_MASK) +#define BCH_STATUS0_SET_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_SET_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_SET_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_STATUS_BLK0_SHIFT)) & BCH_STATUS0_SET_STATUS_BLK0_MASK) +#define BCH_STATUS0_SET_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_SET_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_SET_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_COMPLETED_CE_SHIFT)) & BCH_STATUS0_SET_COMPLETED_CE_MASK) +#define BCH_STATUS0_SET_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_SET_HANDLE_SHIFT (20U) +#define BCH_STATUS0_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_HANDLE_SHIFT)) & BCH_STATUS0_SET_HANDLE_MASK) + +/*! @name STATUS0_CLR - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_CLR_RSVD0_MASK (0x3U) +#define BCH_STATUS0_CLR_RSVD0_SHIFT (0U) +#define BCH_STATUS0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD0_SHIFT)) & BCH_STATUS0_CLR_RSVD0_MASK) +#define BCH_STATUS0_CLR_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_CLR_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_CLR_UNCORRECTABLE_MASK) +#define BCH_STATUS0_CLR_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_CLR_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_CLR_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_CORRECTED_SHIFT)) & BCH_STATUS0_CLR_CORRECTED_MASK) +#define BCH_STATUS0_CLR_ALLONES_MASK (0x10U) +#define BCH_STATUS0_CLR_ALLONES_SHIFT (4U) +#define BCH_STATUS0_CLR_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_ALLONES_SHIFT)) & BCH_STATUS0_CLR_ALLONES_MASK) +#define BCH_STATUS0_CLR_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_CLR_RSVD1_SHIFT (5U) +#define BCH_STATUS0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD1_SHIFT)) & BCH_STATUS0_CLR_RSVD1_MASK) +#define BCH_STATUS0_CLR_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_CLR_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_CLR_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_STATUS_BLK0_SHIFT)) & BCH_STATUS0_CLR_STATUS_BLK0_MASK) +#define BCH_STATUS0_CLR_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_CLR_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_CLR_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_COMPLETED_CE_SHIFT)) & BCH_STATUS0_CLR_COMPLETED_CE_MASK) +#define BCH_STATUS0_CLR_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_CLR_HANDLE_SHIFT (20U) +#define BCH_STATUS0_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_HANDLE_SHIFT)) & BCH_STATUS0_CLR_HANDLE_MASK) + +/*! @name STATUS0_TOG - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_TOG_RSVD0_MASK (0x3U) +#define BCH_STATUS0_TOG_RSVD0_SHIFT (0U) +#define BCH_STATUS0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_RSVD0_SHIFT)) & BCH_STATUS0_TOG_RSVD0_MASK) +#define BCH_STATUS0_TOG_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_TOG_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_TOG_UNCORRECTABLE_MASK) +#define BCH_STATUS0_TOG_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_TOG_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_TOG_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_CORRECTED_SHIFT)) & BCH_STATUS0_TOG_CORRECTED_MASK) +#define BCH_STATUS0_TOG_ALLONES_MASK (0x10U) +#define BCH_STATUS0_TOG_ALLONES_SHIFT (4U) +#define BCH_STATUS0_TOG_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_ALLONES_SHIFT)) & BCH_STATUS0_TOG_ALLONES_MASK) +#define BCH_STATUS0_TOG_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_TOG_RSVD1_SHIFT (5U) +#define BCH_STATUS0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_RSVD1_SHIFT)) & BCH_STATUS0_TOG_RSVD1_MASK) +#define BCH_STATUS0_TOG_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_TOG_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_TOG_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_STATUS_BLK0_SHIFT)) & BCH_STATUS0_TOG_STATUS_BLK0_MASK) +#define BCH_STATUS0_TOG_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_TOG_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_TOG_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_COMPLETED_CE_SHIFT)) & BCH_STATUS0_TOG_COMPLETED_CE_MASK) +#define BCH_STATUS0_TOG_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_TOG_HANDLE_SHIFT (20U) +#define BCH_STATUS0_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_HANDLE_SHIFT)) & BCH_STATUS0_TOG_HANDLE_MASK) + +/*! @name MODE - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK) +#define BCH_MODE_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_RSVD_SHIFT (8U) +#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK) + +/*! @name MODE_SET - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_SET_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_SET_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_SET_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_SET_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_SET_ERASE_THRESHOLD_MASK) +#define BCH_MODE_SET_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_SET_RSVD_SHIFT (8U) +#define BCH_MODE_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_SET_RSVD_SHIFT)) & BCH_MODE_SET_RSVD_MASK) + +/*! @name MODE_CLR - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_CLR_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_CLR_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_CLR_ERASE_THRESHOLD_MASK) +#define BCH_MODE_CLR_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_CLR_RSVD_SHIFT (8U) +#define BCH_MODE_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_CLR_RSVD_SHIFT)) & BCH_MODE_CLR_RSVD_MASK) + +/*! @name MODE_TOG - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_TOG_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_TOG_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_TOG_ERASE_THRESHOLD_MASK) +#define BCH_MODE_TOG_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_TOG_RSVD_SHIFT (8U) +#define BCH_MODE_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_TOG_RSVD_SHIFT)) & BCH_MODE_TOG_RSVD_MASK) + +/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK) + +/*! @name ENCODEPTR_SET - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_SET_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_SET_ADDR_SHIFT)) & BCH_ENCODEPTR_SET_ADDR_MASK) + +/*! @name ENCODEPTR_CLR - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_CLR_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_CLR_ADDR_SHIFT)) & BCH_ENCODEPTR_CLR_ADDR_MASK) + +/*! @name ENCODEPTR_TOG - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_TOG_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_TOG_ADDR_SHIFT)) & BCH_ENCODEPTR_TOG_ADDR_MASK) + +/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_ADDR_SHIFT (0U) +#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK) + +/*! @name DATAPTR_SET - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_SET_ADDR_SHIFT (0U) +#define BCH_DATAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_SET_ADDR_SHIFT)) & BCH_DATAPTR_SET_ADDR_MASK) + +/*! @name DATAPTR_CLR - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_CLR_ADDR_SHIFT (0U) +#define BCH_DATAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_CLR_ADDR_SHIFT)) & BCH_DATAPTR_CLR_ADDR_MASK) + +/*! @name DATAPTR_TOG - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_TOG_ADDR_SHIFT (0U) +#define BCH_DATAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_TOG_ADDR_SHIFT)) & BCH_DATAPTR_TOG_ADDR_MASK) + +/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_ADDR_SHIFT (0U) +#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK) + +/*! @name METAPTR_SET - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_SET_ADDR_SHIFT (0U) +#define BCH_METAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_SET_ADDR_SHIFT)) & BCH_METAPTR_SET_ADDR_MASK) + +/*! @name METAPTR_CLR - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_CLR_ADDR_SHIFT (0U) +#define BCH_METAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_CLR_ADDR_SHIFT)) & BCH_METAPTR_CLR_ADDR_MASK) + +/*! @name METAPTR_TOG - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_TOG_ADDR_SHIFT (0U) +#define BCH_METAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_TOG_ADDR_SHIFT)) & BCH_METAPTR_TOG_ADDR_MASK) + +/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK) + +/*! @name LAYOUTSELECT_SET - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_SET_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK) + +/*! @name LAYOUTSELECT_CLR - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK) + +/*! @name LAYOUTSELECT_TOG - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK) + +/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT0_SET - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT0_CLR - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT0_TOG - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH0LAYOUT1_SET - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH0LAYOUT1_CLR - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH0LAYOUT1_TOG - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT0_SET - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT0_CLR - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT0_TOG - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT1_SET - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT1_CLR - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT1_TOG - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT0_SET - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT0_CLR - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT0_TOG - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT1_SET - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT1_CLR - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT1_TOG - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT0_SET - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT0_CLR - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT0_TOG - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT1_SET - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT1_CLR - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT1_TOG - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK) +#define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK) + +/*! @name DEBUG0_SET - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_SET_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_SET_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD0_SHIFT)) & BCH_DEBUG0_SET_RSVD0_MASK) +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_SET_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_SET_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_SET_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_SET_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_SET_KES_STANDALONE_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_SET_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_SET_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_SET_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD1_SHIFT)) & BCH_DEBUG0_SET_RSVD1_MASK) + +/*! @name DEBUG0_CLR - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_CLR_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_CLR_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD0_SHIFT)) & BCH_DEBUG0_CLR_RSVD0_MASK) +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_CLR_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_CLR_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_CLR_KES_STANDALONE_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_CLR_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_CLR_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD1_SHIFT)) & BCH_DEBUG0_CLR_RSVD1_MASK) + +/*! @name DEBUG0_TOG - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_TOG_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_TOG_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD0_SHIFT)) & BCH_DEBUG0_TOG_RSVD0_MASK) +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_TOG_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_TOG_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_TOG_KES_STANDALONE_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_TOG_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_TOG_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD1_SHIFT)) & BCH_DEBUG0_TOG_RSVD1_MASK) + +/*! @name DBGKESREAD - KES Debug Read Register */ +#define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK) + +/*! @name DBGKESREAD_SET - KES Debug Read Register */ +#define BCH_DBGKESREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_SET_VALUES_SHIFT)) & BCH_DBGKESREAD_SET_VALUES_MASK) + +/*! @name DBGKESREAD_CLR - KES Debug Read Register */ +#define BCH_DBGKESREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_CLR_VALUES_SHIFT)) & BCH_DBGKESREAD_CLR_VALUES_MASK) + +/*! @name DBGKESREAD_TOG - KES Debug Read Register */ +#define BCH_DBGKESREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_TOG_VALUES_SHIFT)) & BCH_DBGKESREAD_TOG_VALUES_MASK) + +/*! @name DBGCSFEREAD - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK) + +/*! @name DBGCSFEREAD_SET - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_SET_VALUES_SHIFT)) & BCH_DBGCSFEREAD_SET_VALUES_MASK) + +/*! @name DBGCSFEREAD_CLR - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_CLR_VALUES_SHIFT)) & BCH_DBGCSFEREAD_CLR_VALUES_MASK) + +/*! @name DBGCSFEREAD_TOG - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_TOG_VALUES_SHIFT)) & BCH_DBGCSFEREAD_TOG_VALUES_MASK) + +/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK) + +/*! @name DBGSYNDGENREAD_SET - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_SET_VALUES_MASK) + +/*! @name DBGSYNDGENREAD_CLR - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_CLR_VALUES_MASK) + +/*! @name DBGSYNDGENREAD_TOG - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_TOG_VALUES_MASK) + +/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK) + +/*! @name DBGAHBMREAD_SET - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_SET_VALUES_SHIFT)) & BCH_DBGAHBMREAD_SET_VALUES_MASK) + +/*! @name DBGAHBMREAD_CLR - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_CLR_VALUES_SHIFT)) & BCH_DBGAHBMREAD_CLR_VALUES_MASK) + +/*! @name DBGAHBMREAD_TOG - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_TOG_VALUES_SHIFT)) & BCH_DBGAHBMREAD_TOG_VALUES_MASK) + +/*! @name BLOCKNAME - Block Name Register */ +#define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK) + +/*! @name BLOCKNAME_SET - Block Name Register */ +#define BCH_BLOCKNAME_SET_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_SET_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_SET_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_SET_NAME_SHIFT)) & BCH_BLOCKNAME_SET_NAME_MASK) + +/*! @name BLOCKNAME_CLR - Block Name Register */ +#define BCH_BLOCKNAME_CLR_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_CLR_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_CLR_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_CLR_NAME_SHIFT)) & BCH_BLOCKNAME_CLR_NAME_MASK) + +/*! @name BLOCKNAME_TOG - Block Name Register */ +#define BCH_BLOCKNAME_TOG_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_TOG_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_TOG_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_TOG_NAME_SHIFT)) & BCH_BLOCKNAME_TOG_NAME_MASK) + +/*! @name VERSION - BCH Version Register */ +#define BCH_VERSION_STEP_MASK (0xFFFFU) +#define BCH_VERSION_STEP_SHIFT (0U) +#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK) +#define BCH_VERSION_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_MINOR_SHIFT (16U) +#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK) +#define BCH_VERSION_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_MAJOR_SHIFT (24U) +#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK) + +/*! @name VERSION_SET - BCH Version Register */ +#define BCH_VERSION_SET_STEP_MASK (0xFFFFU) +#define BCH_VERSION_SET_STEP_SHIFT (0U) +#define BCH_VERSION_SET_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_STEP_SHIFT)) & BCH_VERSION_SET_STEP_MASK) +#define BCH_VERSION_SET_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_SET_MINOR_SHIFT (16U) +#define BCH_VERSION_SET_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_MINOR_SHIFT)) & BCH_VERSION_SET_MINOR_MASK) +#define BCH_VERSION_SET_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_SET_MAJOR_SHIFT (24U) +#define BCH_VERSION_SET_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_MAJOR_SHIFT)) & BCH_VERSION_SET_MAJOR_MASK) + +/*! @name VERSION_CLR - BCH Version Register */ +#define BCH_VERSION_CLR_STEP_MASK (0xFFFFU) +#define BCH_VERSION_CLR_STEP_SHIFT (0U) +#define BCH_VERSION_CLR_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_STEP_SHIFT)) & BCH_VERSION_CLR_STEP_MASK) +#define BCH_VERSION_CLR_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_CLR_MINOR_SHIFT (16U) +#define BCH_VERSION_CLR_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_MINOR_SHIFT)) & BCH_VERSION_CLR_MINOR_MASK) +#define BCH_VERSION_CLR_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_CLR_MAJOR_SHIFT (24U) +#define BCH_VERSION_CLR_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_MAJOR_SHIFT)) & BCH_VERSION_CLR_MAJOR_MASK) + +/*! @name VERSION_TOG - BCH Version Register */ +#define BCH_VERSION_TOG_STEP_MASK (0xFFFFU) +#define BCH_VERSION_TOG_STEP_SHIFT (0U) +#define BCH_VERSION_TOG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_STEP_SHIFT)) & BCH_VERSION_TOG_STEP_MASK) +#define BCH_VERSION_TOG_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_TOG_MINOR_SHIFT (16U) +#define BCH_VERSION_TOG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_MINOR_SHIFT)) & BCH_VERSION_TOG_MINOR_MASK) +#define BCH_VERSION_TOG_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_TOG_MAJOR_SHIFT (24U) +#define BCH_VERSION_TOG_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_MAJOR_SHIFT)) & BCH_VERSION_TOG_MAJOR_MASK) + +/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_RSVD_SHIFT (9U) +#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK) +#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK) + +/*! @name DEBUG1_SET - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_SET_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_SET_RSVD_SHIFT (9U) +#define BCH_DEBUG1_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_RSVD_SHIFT)) & BCH_DEBUG1_SET_RSVD_MASK) +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK) + +/*! @name DEBUG1_CLR - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_CLR_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_CLR_RSVD_SHIFT (9U) +#define BCH_DEBUG1_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_RSVD_SHIFT)) & BCH_DEBUG1_CLR_RSVD_MASK) +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK) + +/*! @name DEBUG1_TOG - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_TOG_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_TOG_RSVD_SHIFT (9U) +#define BCH_DEBUG1_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_RSVD_SHIFT)) & BCH_DEBUG1_TOG_RSVD_MASK) +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK) + + +/*! + * @} + */ /* end of group BCH_Register_Masks */ + + +/* BCH - Peripheral instance base addresses */ +/** Peripheral BCH base address */ +#define BCH_BASE (0x1808000u) +/** Peripheral BCH base pointer */ +#define BCH ((BCH_Type *)BCH_BASE) +/** Array initializer of BCH peripheral base addresses */ +#define BCH_BASE_ADDRS { BCH_BASE } +/** Array initializer of BCH peripheral base pointers */ +#define BCH_BASE_PTRS { BCH } +/** Interrupt vectors for the BCH peripheral type */ +#define BCH_IRQS { RAWNAND_BCH_IRQn } + +/*! + * @} + */ /* end of group BCH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ + __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ + __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ + __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ + __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ + uint8_t RESERVED_1[8]; + __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ + __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ + uint8_t RESERVED_2[48]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[64]; + uint8_t RESERVED_3[1024]; + __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_4[96]; + __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) +#define CAN_MCR_SUPV_MASK (0x800000U) +#define CAN_MCR_SUPV_SHIFT (23U) +#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) + +/*! @name CTRL1 - Control 1 Register */ +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) + +/*! @name TIMER - Free Running Timer Register */ +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) + +/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) + +/*! @name RX14MASK - Rx Buffer 14 Mask Register */ +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) + +/*! @name RX15MASK - Rx Buffer 15 Mask Register */ +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) + +/*! @name ECR - Error Counter Register */ +#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU) +#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U) +#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK) +#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U) +#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U) +#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK) + +/*! @name ESR1 - Error and Status 1 Register */ +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + +/*! @name IMASK2 - Interrupt Masks 2 Register */ +#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU) +#define CAN_IMASK2_BUFHM_SHIFT (0U) +#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK) + +/*! @name IMASK1 - Interrupt Masks 1 Register */ +#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUFLM_SHIFT (0U) +#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) + +/*! @name IFLAG2 - Interrupt Flags 2 Register */ +#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU) +#define CAN_IFLAG2_BUFHI_SHIFT (0U) +#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK) + +/*! @name IFLAG1 - Interrupt Flags 1 Register */ +#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU) +#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U) +#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK) +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) + +/*! @name CTRL2 - Control 2 Register */ +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) +#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) +#define CAN_CTRL2_WRMFRZ_SHIFT (28U) +#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) + +/*! @name ESR2 - Error and Status 2 Register */ +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) + +/*! @name CRCR - CRC Register */ +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) + +/*! @name RXFGMASK - Rx FIFO Global Mask Register */ +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) + +/*! @name RXFIR - Rx FIFO Information Register */ +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */ +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (64U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */ +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (64U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (64U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (64U) + +/*! @name RXIMR - Rx Individual Mask Registers */ +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (64U) + +/*! @name GFWR - Glitch Filter Width Registers */ +#define CAN_GFWR_GFWR_MASK (0xFFU) +#define CAN_GFWR_GFWR_SHIFT (0U) +#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x2090000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Peripheral CAN2 base address */ +#define CAN2_BASE (0x2094000u) +/** Peripheral CAN2 base pointer */ +#define CAN2 ((CAN_Type *)CAN2_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +/* Backward compatibility */ +#define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK +#define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT +#define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x) +#define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK +#define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT +#define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x) + + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer + * @{ + */ + +/** CCM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */ + __IO uint32_t CCDR; /**< CCM Control Divider Register, offset: 0x4 */ + __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */ + __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */ + __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */ + __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */ + __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */ + __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */ + __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */ + __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */ + __IO uint32_t CS1CDR; /**< CCM SAI1 Clock Divider Register, offset: 0x28 */ + __IO uint32_t CS2CDR; /**< CCM SAI2 Clock Divider Register, offset: 0x2C */ + __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */ + __IO uint32_t CHSCCDR; /**< CCM HSC Clock Divider Register, offset: 0x34 */ + __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */ + __IO uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */ + uint8_t RESERVED_0[8]; + __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */ + uint8_t RESERVED_1[8]; + __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */ + __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */ + __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ + __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */ + __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */ + __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */ + __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */ + __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */ + __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */ + __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */ + __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */ + __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */ + uint8_t RESERVED_2[4]; + __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */ +} CCM_Type; + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/*! @name CCR - CCM Control Register */ +#define CCM_CCR_OSCNT_MASK (0x7FU) +#define CCM_CCR_OSCNT_SHIFT (0U) +#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK) +#define CCM_CCR_COSC_EN_MASK (0x1000U) +#define CCM_CCR_COSC_EN_SHIFT (12U) +#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK) +#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U) +#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U) +#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK) +#define CCM_CCR_RBC_EN_MASK (0x8000000U) +#define CCM_CCR_RBC_EN_SHIFT (27U) +#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK) + +/*! @name CCDR - CCM Control Divider Register */ +#define CCM_CCDR_MMDC_CH1_MASK_MASK (0x10000U) +#define CCM_CCDR_MMDC_CH1_MASK_SHIFT (16U) +#define CCM_CCDR_MMDC_CH1_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCDR_MMDC_CH1_MASK_SHIFT)) & CCM_CCDR_MMDC_CH1_MASK_MASK) +#define CCM_CCDR_MMDC_CH0_MASK_MASK (0x20000U) +#define CCM_CCDR_MMDC_CH0_MASK_SHIFT (17U) +#define CCM_CCDR_MMDC_CH0_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCDR_MMDC_CH0_MASK_SHIFT)) & CCM_CCDR_MMDC_CH0_MASK_MASK) + +/*! @name CSR - CCM Status Register */ +#define CCM_CSR_REF_EN_B_MASK (0x1U) +#define CCM_CSR_REF_EN_B_SHIFT (0U) +#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK) +#define CCM_CSR_COSC_READY_MASK (0x20U) +#define CCM_CSR_COSC_READY_SHIFT (5U) +#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK) + +/*! @name CCSR - CCM Clock Switcher Register */ +#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U) +#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U) +#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) +#define CCM_CCSR_PLL1_SW_CLK_SEL_MASK (0x4U) +#define CCM_CCSR_PLL1_SW_CLK_SEL_SHIFT (2U) +#define CCM_CCSR_PLL1_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL1_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL1_SW_CLK_SEL_MASK) +#define CCM_CCSR_SECONDARY_CLK_SEL_MASK (0x8U) +#define CCM_CCSR_SECONDARY_CLK_SEL_SHIFT (3U) +#define CCM_CCSR_SECONDARY_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_SECONDARY_CLK_SEL_SHIFT)) & CCM_CCSR_SECONDARY_CLK_SEL_MASK) +#define CCM_CCSR_STEP_SEL_MASK (0x100U) +#define CCM_CCSR_STEP_SEL_SHIFT (8U) +#define CCM_CCSR_STEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_STEP_SEL_SHIFT)) & CCM_CCSR_STEP_SEL_MASK) + +/*! @name CACRR - CCM Arm Clock Root Register */ +#define CCM_CACRR_ARM_PODF_MASK (0x7U) +#define CCM_CACRR_ARM_PODF_SHIFT (0U) +#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK) + +/*! @name CBCDR - CCM Bus Clock Divider Register */ +#define CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7U) +#define CCM_CBCDR_PERIPH2_CLK2_PODF_SHIFT (0U) +#define CCM_CBCDR_PERIPH2_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH2_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) +#define CCM_CBCDR_FABRIC_MMDC_PODF_MASK (0x38U) +#define CCM_CBCDR_FABRIC_MMDC_PODF_SHIFT (3U) +#define CCM_CBCDR_FABRIC_MMDC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_FABRIC_MMDC_PODF_SHIFT)) & CCM_CBCDR_FABRIC_MMDC_PODF_MASK) +#define CCM_CBCDR_AXI_SEL_MASK (0x40U) +#define CCM_CBCDR_AXI_SEL_SHIFT (6U) +#define CCM_CBCDR_AXI_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AXI_SEL_SHIFT)) & CCM_CBCDR_AXI_SEL_MASK) +#define CCM_CBCDR_AXI_ALT_SEL_MASK (0x80U) +#define CCM_CBCDR_AXI_ALT_SEL_SHIFT (7U) +#define CCM_CBCDR_AXI_ALT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AXI_ALT_SEL_SHIFT)) & CCM_CBCDR_AXI_ALT_SEL_MASK) +#define CCM_CBCDR_IPG_PODF_MASK (0x300U) +#define CCM_CBCDR_IPG_PODF_SHIFT (8U) +#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK) +#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U) +#define CCM_CBCDR_AHB_PODF_SHIFT (10U) +#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK) +#define CCM_CBCDR_AXI_PODF_MASK (0x70000U) +#define CCM_CBCDR_AXI_PODF_SHIFT (16U) +#define CCM_CBCDR_AXI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AXI_PODF_SHIFT)) & CCM_CBCDR_AXI_PODF_MASK) +#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U) +#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U) +#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK) +#define CCM_CBCDR_PERIPH2_CLK_SEL_MASK (0x4000000U) +#define CCM_CBCDR_PERIPH2_CLK_SEL_SHIFT (26U) +#define CCM_CBCDR_PERIPH2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH2_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH2_CLK_SEL_MASK) +#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U) +#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U) +#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) + +/*! @name CBCMR - CCM Bus Clock Multiplexer Register */ +#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U) +#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U) +#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) +#define CCM_CBCMR_PERIPH2_CLK2_SEL_MASK (0x100000U) +#define CCM_CBCMR_PERIPH2_CLK2_SEL_SHIFT (20U) +#define CCM_CBCMR_PERIPH2_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH2_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH2_CLK2_SEL_MASK) +#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x600000U) +#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT (21U) +#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) +#define CCM_CBCMR_LCDIF1_PODF_MASK (0x3800000U) +#define CCM_CBCMR_LCDIF1_PODF_SHIFT (23U) +#define CCM_CBCMR_LCDIF1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF1_PODF_SHIFT)) & CCM_CBCMR_LCDIF1_PODF_MASK) + +/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */ +#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU) +#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U) +#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK) +#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U) +#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U) +#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) +#define CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x380U) +#define CCM_CSCMR1_QSPI1_CLK_SEL_SHIFT (7U) +#define CCM_CSCMR1_QSPI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_QSPI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_QSPI1_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U) +#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U) +#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U) +#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U) +#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U) +#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U) +#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U) +#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U) +#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U) +#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U) +#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK) +#define CCM_CSCMR1_BCH_CLK_SEL_MASK (0x40000U) +#define CCM_CSCMR1_BCH_CLK_SEL_SHIFT (18U) +#define CCM_CSCMR1_BCH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_BCH_CLK_SEL_SHIFT)) & CCM_CSCMR1_BCH_CLK_SEL_MASK) +#define CCM_CSCMR1_GPMI_CLK_SEL_MASK (0x80000U) +#define CCM_CSCMR1_GPMI_CLK_SEL_SHIFT (19U) +#define CCM_CSCMR1_GPMI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_GPMI_CLK_SEL_SHIFT)) & CCM_CSCMR1_GPMI_CLK_SEL_MASK) +#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF_MASK (0x3800000U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT (23U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT)) & CCM_CSCMR1_ACLK_EIM_SLOW_PODF_MASK) +#define CCM_CSCMR1_QSPI1_PODF_MASK (0x1C000000U) +#define CCM_CSCMR1_QSPI1_PODF_SHIFT (26U) +#define CCM_CSCMR1_QSPI1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_QSPI1_PODF_SHIFT)) & CCM_CSCMR1_QSPI1_PODF_MASK) +#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_MASK (0x60000000U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT (29U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT)) & CCM_CSCMR1_ACLK_EIM_SLOW_SEL_MASK) + +/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */ +#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU) +#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U) +#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK) +#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U) +#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U) +#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK) +#define CCM_CSCMR2_LDB_DI0_DIV_MASK (0x400U) +#define CCM_CSCMR2_LDB_DI0_DIV_SHIFT (10U) +#define CCM_CSCMR2_LDB_DI0_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_LDB_DI0_DIV_SHIFT)) & CCM_CSCMR2_LDB_DI0_DIV_MASK) +#define CCM_CSCMR2_LDB_DI1_DIV_MASK (0x800U) +#define CCM_CSCMR2_LDB_DI1_DIV_SHIFT (11U) +#define CCM_CSCMR2_LDB_DI1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_LDB_DI1_DIV_SHIFT)) & CCM_CSCMR2_LDB_DI1_DIV_MASK) +#define CCM_CSCMR2_ESAI_CLK_SEL_MASK (0x180000U) +#define CCM_CSCMR2_ESAI_CLK_SEL_SHIFT (19U) +#define CCM_CSCMR2_ESAI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_ESAI_CLK_SEL_SHIFT)) & CCM_CSCMR2_ESAI_CLK_SEL_MASK) +#define CCM_CSCMR2_VID_CLK_SEL_MASK (0xE00000U) +#define CCM_CSCMR2_VID_CLK_SEL_SHIFT (21U) +#define CCM_CSCMR2_VID_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_VID_CLK_SEL_SHIFT)) & CCM_CSCMR2_VID_CLK_SEL_MASK) +#define CCM_CSCMR2_VID_CLK_PRE_PODF_MASK (0x3000000U) +#define CCM_CSCMR2_VID_CLK_PRE_PODF_SHIFT (24U) +#define CCM_CSCMR2_VID_CLK_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_VID_CLK_PRE_PODF_SHIFT)) & CCM_CSCMR2_VID_CLK_PRE_PODF_MASK) +#define CCM_CSCMR2_VID_CLK_PODF_MASK (0x1C000000U) +#define CCM_CSCMR2_VID_CLK_PODF_SHIFT (26U) +#define CCM_CSCMR2_VID_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_VID_CLK_PODF_SHIFT)) & CCM_CSCMR2_VID_CLK_PODF_MASK) + +/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */ +#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU) +#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U) +#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK) +#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U) +#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U) +#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK) +#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U) +#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U) +#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK) +#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U) +#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U) +#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK) +#define CCM_CSCDR1_BCH_PODF_MASK (0x380000U) +#define CCM_CSCDR1_BCH_PODF_SHIFT (19U) +#define CCM_CSCDR1_BCH_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_BCH_PODF_SHIFT)) & CCM_CSCDR1_BCH_PODF_MASK) +#define CCM_CSCDR1_GPMI_PODF_MASK (0x1C00000U) +#define CCM_CSCDR1_GPMI_PODF_SHIFT (22U) +#define CCM_CSCDR1_GPMI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_GPMI_PODF_SHIFT)) & CCM_CSCDR1_GPMI_PODF_MASK) + +/*! @name CS1CDR - CCM SAI1 Clock Divider Register */ +#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU) +#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U) +#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U) +#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U) +#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK) +#define CCM_CS1CDR_ESAI_CLK_PRED_MASK (0xE00U) +#define CCM_CS1CDR_ESAI_CLK_PRED_SHIFT (9U) +#define CCM_CS1CDR_ESAI_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_ESAI_CLK_PRED_SHIFT)) & CCM_CS1CDR_ESAI_CLK_PRED_MASK) +#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U) +#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U) +#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U) +#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U) +#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK) +#define CCM_CS1CDR_ESAI_CLK_PODF_MASK (0xE000000U) +#define CCM_CS1CDR_ESAI_CLK_PODF_SHIFT (25U) +#define CCM_CS1CDR_ESAI_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_ESAI_CLK_PODF_SHIFT)) & CCM_CS1CDR_ESAI_CLK_PODF_MASK) + +/*! @name CS2CDR - CCM SAI2 Clock Divider Register */ +#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU) +#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U) +#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK) +#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U) +#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U) +#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK) +#define CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0xE00U) +#define CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT (9U) +#define CCM_CS2CDR_LDB_DI0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT)) & CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK) +#define CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x38000U) +#define CCM_CS2CDR_ENFC_CLK_SEL_SHIFT (15U) +#define CCM_CS2CDR_ENFC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_ENFC_CLK_SEL_SHIFT)) & CCM_CS2CDR_ENFC_CLK_SEL_MASK) +#define CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x1C0000U) +#define CCM_CS2CDR_ENFC_CLK_PRED_SHIFT (18U) +#define CCM_CS2CDR_ENFC_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_ENFC_CLK_PRED_SHIFT)) & CCM_CS2CDR_ENFC_CLK_PRED_MASK) +#define CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x7E00000U) +#define CCM_CS2CDR_ENFC_CLK_PODF_SHIFT (21U) +#define CCM_CS2CDR_ENFC_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_ENFC_CLK_PODF_SHIFT)) & CCM_CS2CDR_ENFC_CLK_PODF_MASK) + +/*! @name CDCDR - CCM D1 Clock Divider Register */ +#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U) +#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U) +#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U) +#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U) +#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U) +#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U) +#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK) + +/*! @name CHSCCDR - CCM HSC Clock Divider Register */ +#define CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0xE00U) +#define CCM_CHSCCDR_EPDC_CLK_SEL_SHIFT (9U) +#define CCM_CHSCCDR_EPDC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CHSCCDR_EPDC_CLK_SEL_SHIFT)) & CCM_CHSCCDR_EPDC_CLK_SEL_MASK) +#define CCM_CHSCCDR_EPDC_PODF_MASK (0x7000U) +#define CCM_CHSCCDR_EPDC_PODF_SHIFT (12U) +#define CCM_CHSCCDR_EPDC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CHSCCDR_EPDC_PODF_SHIFT)) & CCM_CHSCCDR_EPDC_PODF_MASK) +#define CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x38000U) +#define CCM_CHSCCDR_EPDC_PRE_CLK_SEL_SHIFT (15U) +#define CCM_CHSCCDR_EPDC_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CHSCCDR_EPDC_PRE_CLK_SEL_SHIFT)) & CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK) + +/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */ +#define CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0xE00U) +#define CCM_CSCDR2_LCDIF1_CLK_SEL_SHIFT (9U) +#define CCM_CSCDR2_LCDIF1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF1_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) +#define CCM_CSCDR2_LCDIF1_PRED_MASK (0x7000U) +#define CCM_CSCDR2_LCDIF1_PRED_SHIFT (12U) +#define CCM_CSCDR2_LCDIF1_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF1_PRED_SHIFT)) & CCM_CSCDR2_LCDIF1_PRED_MASK) +#define CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_MASK (0x38000U) +#define CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_SHIFT (15U) +#define CCM_CSCDR2_LCDIF1_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_MASK) +#define CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x40000U) +#define CCM_CSCDR2_ECSPI_CLK_SEL_SHIFT (18U) +#define CCM_CSCDR2_ECSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_ECSPI_CLK_SEL_SHIFT)) & CCM_CSCDR2_ECSPI_CLK_SEL_MASK) +#define CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x1F80000U) +#define CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT (19U) +#define CCM_CSCDR2_ECSPI_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT)) & CCM_CSCDR2_ECSPI_CLK_PODF_MASK) + +/*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */ +#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U) +#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U) +#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK) +#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U) +#define CCM_CSCDR3_CSI_PODF_SHIFT (11U) +#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK) + +/*! @name CDHIPR - CCM Divider Handshake In-Process Register */ +#define CCM_CDHIPR_AXI_PODF_BUSY_MASK (0x1U) +#define CCM_CDHIPR_AXI_PODF_BUSY_SHIFT (0U) +#define CCM_CDHIPR_AXI_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AXI_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AXI_PODF_BUSY_MASK) +#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U) +#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U) +#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK) +#define CCM_CDHIPR_MMDC_PODF_BUSY_MASK (0x4U) +#define CCM_CDHIPR_MMDC_PODF_BUSY_SHIFT (2U) +#define CCM_CDHIPR_MMDC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_MMDC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_MMDC_PODF_BUSY_MASK) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U) +#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U) +#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK) + +/*! @name CLPCR - CCM Low Power Control Register */ +#define CCM_CLPCR_LPM_MASK (0x3U) +#define CCM_CLPCR_LPM_SHIFT (0U) +#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK) +#define CCM_CLPCR_SBYOS_MASK (0x40U) +#define CCM_CLPCR_SBYOS_SHIFT (6U) +#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK) +#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U) +#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U) +#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK) +#define CCM_CLPCR_VSTBY_MASK (0x100U) +#define CCM_CLPCR_VSTBY_SHIFT (8U) +#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK) +#define CCM_CLPCR_STBY_COUNT_MASK (0x600U) +#define CCM_CLPCR_STBY_COUNT_SHIFT (9U) +#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK) +#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U) +#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U) +#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK) +#define CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_MASK (0x80000U) +#define CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_SHIFT (19U) +#define CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_SHIFT)) & CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_MASK) +#define CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_MASK (0x200000U) +#define CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_SHIFT (21U) +#define CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_SHIFT)) & CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_MASK) +#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U) +#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U) +#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK) +#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U) +#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U) +#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK) +#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U) +#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U) +#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK) + +/*! @name CISR - CCM Interrupt Status Register */ +#define CCM_CISR_LRF_PLL_MASK (0x1U) +#define CCM_CISR_LRF_PLL_SHIFT (0U) +#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK) +#define CCM_CISR_COSC_READY_MASK (0x40U) +#define CCM_CISR_COSC_READY_SHIFT (6U) +#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK) +#define CCM_CISR_AXI_PODF_LOADED_MASK (0x20000U) +#define CCM_CISR_AXI_PODF_LOADED_SHIFT (17U) +#define CCM_CISR_AXI_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AXI_PODF_LOADED_SHIFT)) & CCM_CISR_AXI_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U) +#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK) +#define CCM_CISR_MMDC_PODF_LOADED_MASK (0x200000U) +#define CCM_CISR_MMDC_PODF_LOADED_SHIFT (21U) +#define CCM_CISR_MMDC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_MMDC_PODF_LOADED_SHIFT)) & CCM_CISR_MMDC_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U) +#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK) + +/*! @name CIMR - CCM Interrupt Mask Register */ +#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U) +#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U) +#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK) +#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U) +#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U) +#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK) +#define CCM_CIMR_MASK_AXI_PODF_LOADED_MASK (0x20000U) +#define CCM_CIMR_MASK_AXI_PODF_LOADED_SHIFT (17U) +#define CCM_CIMR_MASK_AXI_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AXI_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AXI_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U) +#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_MMDC_PODF_LOADED_MASK (0x200000U) +#define CCM_CIMR_MASK_MMDC_PODF_LOADED_SHIFT (21U) +#define CCM_CIMR_MASK_MMDC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_MMDC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_MMDC_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U) +#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK) + +/*! @name CCOSR - CCM Clock Output Source Register */ +#define CCM_CCOSR_CLKO_SEL_MASK (0xFU) +#define CCM_CCOSR_CLKO_SEL_SHIFT (0U) +#define CCM_CCOSR_CLKO_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO_SEL_SHIFT)) & CCM_CCOSR_CLKO_SEL_MASK) +#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U) +#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U) +#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK) +#define CCM_CCOSR_CLKO1_EN_MASK (0x80U) +#define CCM_CCOSR_CLKO1_EN_SHIFT (7U) +#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK) +#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U) +#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U) +#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK) +#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U) +#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U) +#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK) +#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U) +#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U) +#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK) +#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) +#define CCM_CCOSR_CLKO2_EN_SHIFT (24U) +#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) + +/*! @name CGPR - CCM General Purpose Register */ +#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) +#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) +#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) +#define CCM_CGPR_MMDC_EXT_CLK_DIS_MASK (0x4U) +#define CCM_CGPR_MMDC_EXT_CLK_DIS_SHIFT (2U) +#define CCM_CGPR_MMDC_EXT_CLK_DIS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_MMDC_EXT_CLK_DIS_SHIFT)) & CCM_CGPR_MMDC_EXT_CLK_DIS_MASK) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK) +#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U) +#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U) +#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK) +#define CCM_CGPR_FPL_MASK (0x10000U) +#define CCM_CGPR_FPL_SHIFT (16U) +#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK) +#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) +#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) +#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) + +/*! @name CCGR0 - CCM Clock Gating Register 0 */ +#define CCM_CCGR0_CG0_MASK (0x3U) +#define CCM_CCGR0_CG0_SHIFT (0U) +#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) +#define CCM_CCGR0_CG1_MASK (0xCU) +#define CCM_CCGR0_CG1_SHIFT (2U) +#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK) +#define CCM_CCGR0_CG2_MASK (0x30U) +#define CCM_CCGR0_CG2_SHIFT (4U) +#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK) +#define CCM_CCGR0_CG3_MASK (0xC0U) +#define CCM_CCGR0_CG3_SHIFT (6U) +#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK) +#define CCM_CCGR0_CG4_MASK (0x300U) +#define CCM_CCGR0_CG4_SHIFT (8U) +#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK) +#define CCM_CCGR0_CG5_MASK (0xC00U) +#define CCM_CCGR0_CG5_SHIFT (10U) +#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK) +#define CCM_CCGR0_CG6_MASK (0x3000U) +#define CCM_CCGR0_CG6_SHIFT (12U) +#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK) +#define CCM_CCGR0_CG7_MASK (0xC000U) +#define CCM_CCGR0_CG7_SHIFT (14U) +#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK) +#define CCM_CCGR0_CG8_MASK (0x30000U) +#define CCM_CCGR0_CG8_SHIFT (16U) +#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK) +#define CCM_CCGR0_CG9_MASK (0xC0000U) +#define CCM_CCGR0_CG9_SHIFT (18U) +#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK) +#define CCM_CCGR0_CG10_MASK (0x300000U) +#define CCM_CCGR0_CG10_SHIFT (20U) +#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK) +#define CCM_CCGR0_CG11_MASK (0xC00000U) +#define CCM_CCGR0_CG11_SHIFT (22U) +#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK) +#define CCM_CCGR0_CG12_MASK (0x3000000U) +#define CCM_CCGR0_CG12_SHIFT (24U) +#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK) +#define CCM_CCGR0_CG13_MASK (0xC000000U) +#define CCM_CCGR0_CG13_SHIFT (26U) +#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK) +#define CCM_CCGR0_CG14_MASK (0x30000000U) +#define CCM_CCGR0_CG14_SHIFT (28U) +#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK) +#define CCM_CCGR0_CG15_MASK (0xC0000000U) +#define CCM_CCGR0_CG15_SHIFT (30U) +#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) + +/*! @name CCGR1 - CCM Clock Gating Register 1 */ +#define CCM_CCGR1_CG0_MASK (0x3U) +#define CCM_CCGR1_CG0_SHIFT (0U) +#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) +#define CCM_CCGR1_CG1_MASK (0xCU) +#define CCM_CCGR1_CG1_SHIFT (2U) +#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK) +#define CCM_CCGR1_CG2_MASK (0x30U) +#define CCM_CCGR1_CG2_SHIFT (4U) +#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK) +#define CCM_CCGR1_CG3_MASK (0xC0U) +#define CCM_CCGR1_CG3_SHIFT (6U) +#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK) +#define CCM_CCGR1_CG4_MASK (0x300U) +#define CCM_CCGR1_CG4_SHIFT (8U) +#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK) +#define CCM_CCGR1_CG5_MASK (0xC00U) +#define CCM_CCGR1_CG5_SHIFT (10U) +#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK) +#define CCM_CCGR1_CG6_MASK (0x3000U) +#define CCM_CCGR1_CG6_SHIFT (12U) +#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK) +#define CCM_CCGR1_CG7_MASK (0xC000U) +#define CCM_CCGR1_CG7_SHIFT (14U) +#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK) +#define CCM_CCGR1_CG8_MASK (0x30000U) +#define CCM_CCGR1_CG8_SHIFT (16U) +#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK) +#define CCM_CCGR1_CG9_MASK (0xC0000U) +#define CCM_CCGR1_CG9_SHIFT (18U) +#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK) +#define CCM_CCGR1_CG10_MASK (0x300000U) +#define CCM_CCGR1_CG10_SHIFT (20U) +#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK) +#define CCM_CCGR1_CG11_MASK (0xC00000U) +#define CCM_CCGR1_CG11_SHIFT (22U) +#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK) +#define CCM_CCGR1_CG12_MASK (0x3000000U) +#define CCM_CCGR1_CG12_SHIFT (24U) +#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK) +#define CCM_CCGR1_CG13_MASK (0xC000000U) +#define CCM_CCGR1_CG13_SHIFT (26U) +#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK) +#define CCM_CCGR1_CG14_MASK (0x30000000U) +#define CCM_CCGR1_CG14_SHIFT (28U) +#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK) +#define CCM_CCGR1_CG15_MASK (0xC0000000U) +#define CCM_CCGR1_CG15_SHIFT (30U) +#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK) + +/*! @name CCGR2 - CCM Clock Gating Register 2 */ +#define CCM_CCGR2_CG0_MASK (0x3U) +#define CCM_CCGR2_CG0_SHIFT (0U) +#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK) +#define CCM_CCGR2_CG1_MASK (0xCU) +#define CCM_CCGR2_CG1_SHIFT (2U) +#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK) +#define CCM_CCGR2_CG2_MASK (0x30U) +#define CCM_CCGR2_CG2_SHIFT (4U) +#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK) +#define CCM_CCGR2_CG3_MASK (0xC0U) +#define CCM_CCGR2_CG3_SHIFT (6U) +#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK) +#define CCM_CCGR2_CG4_MASK (0x300U) +#define CCM_CCGR2_CG4_SHIFT (8U) +#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK) +#define CCM_CCGR2_CG5_MASK (0xC00U) +#define CCM_CCGR2_CG5_SHIFT (10U) +#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK) +#define CCM_CCGR2_CG6_MASK (0x3000U) +#define CCM_CCGR2_CG6_SHIFT (12U) +#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK) +#define CCM_CCGR2_CG7_MASK (0xC000U) +#define CCM_CCGR2_CG7_SHIFT (14U) +#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK) +#define CCM_CCGR2_CG8_MASK (0x30000U) +#define CCM_CCGR2_CG8_SHIFT (16U) +#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK) +#define CCM_CCGR2_CG9_MASK (0xC0000U) +#define CCM_CCGR2_CG9_SHIFT (18U) +#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK) +#define CCM_CCGR2_CG10_MASK (0x300000U) +#define CCM_CCGR2_CG10_SHIFT (20U) +#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK) +#define CCM_CCGR2_CG11_MASK (0xC00000U) +#define CCM_CCGR2_CG11_SHIFT (22U) +#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK) +#define CCM_CCGR2_CG12_MASK (0x3000000U) +#define CCM_CCGR2_CG12_SHIFT (24U) +#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK) +#define CCM_CCGR2_CG13_MASK (0xC000000U) +#define CCM_CCGR2_CG13_SHIFT (26U) +#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK) +#define CCM_CCGR2_CG14_MASK (0x30000000U) +#define CCM_CCGR2_CG14_SHIFT (28U) +#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK) +#define CCM_CCGR2_CG15_MASK (0xC0000000U) +#define CCM_CCGR2_CG15_SHIFT (30U) +#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK) + +/*! @name CCGR3 - CCM Clock Gating Register 3 */ +#define CCM_CCGR3_CG0_MASK (0x3U) +#define CCM_CCGR3_CG0_SHIFT (0U) +#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK) +#define CCM_CCGR3_CG1_MASK (0xCU) +#define CCM_CCGR3_CG1_SHIFT (2U) +#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK) +#define CCM_CCGR3_CG2_MASK (0x30U) +#define CCM_CCGR3_CG2_SHIFT (4U) +#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK) +#define CCM_CCGR3_CG3_MASK (0xC0U) +#define CCM_CCGR3_CG3_SHIFT (6U) +#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK) +#define CCM_CCGR3_CG4_MASK (0x300U) +#define CCM_CCGR3_CG4_SHIFT (8U) +#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK) +#define CCM_CCGR3_CG5_MASK (0xC00U) +#define CCM_CCGR3_CG5_SHIFT (10U) +#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK) +#define CCM_CCGR3_CG6_MASK (0x3000U) +#define CCM_CCGR3_CG6_SHIFT (12U) +#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK) +#define CCM_CCGR3_CG7_MASK (0xC000U) +#define CCM_CCGR3_CG7_SHIFT (14U) +#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK) +#define CCM_CCGR3_CG8_MASK (0x30000U) +#define CCM_CCGR3_CG8_SHIFT (16U) +#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK) +#define CCM_CCGR3_CG9_MASK (0xC0000U) +#define CCM_CCGR3_CG9_SHIFT (18U) +#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK) +#define CCM_CCGR3_CG10_MASK (0x300000U) +#define CCM_CCGR3_CG10_SHIFT (20U) +#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK) +#define CCM_CCGR3_CG11_MASK (0xC00000U) +#define CCM_CCGR3_CG11_SHIFT (22U) +#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK) +#define CCM_CCGR3_CG12_MASK (0x3000000U) +#define CCM_CCGR3_CG12_SHIFT (24U) +#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK) +#define CCM_CCGR3_CG13_MASK (0xC000000U) +#define CCM_CCGR3_CG13_SHIFT (26U) +#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK) +#define CCM_CCGR3_CG14_MASK (0x30000000U) +#define CCM_CCGR3_CG14_SHIFT (28U) +#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK) +#define CCM_CCGR3_CG15_MASK (0xC0000000U) +#define CCM_CCGR3_CG15_SHIFT (30U) +#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK) + +/*! @name CCGR4 - CCM Clock Gating Register 4 */ +#define CCM_CCGR4_CG0_MASK (0x3U) +#define CCM_CCGR4_CG0_SHIFT (0U) +#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK) +#define CCM_CCGR4_CG1_MASK (0xCU) +#define CCM_CCGR4_CG1_SHIFT (2U) +#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK) +#define CCM_CCGR4_CG2_MASK (0x30U) +#define CCM_CCGR4_CG2_SHIFT (4U) +#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK) +#define CCM_CCGR4_CG3_MASK (0xC0U) +#define CCM_CCGR4_CG3_SHIFT (6U) +#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK) +#define CCM_CCGR4_CG4_MASK (0x300U) +#define CCM_CCGR4_CG4_SHIFT (8U) +#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK) +#define CCM_CCGR4_CG5_MASK (0xC00U) +#define CCM_CCGR4_CG5_SHIFT (10U) +#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK) +#define CCM_CCGR4_CG6_MASK (0x3000U) +#define CCM_CCGR4_CG6_SHIFT (12U) +#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK) +#define CCM_CCGR4_CG7_MASK (0xC000U) +#define CCM_CCGR4_CG7_SHIFT (14U) +#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK) +#define CCM_CCGR4_CG8_MASK (0x30000U) +#define CCM_CCGR4_CG8_SHIFT (16U) +#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK) +#define CCM_CCGR4_CG9_MASK (0xC0000U) +#define CCM_CCGR4_CG9_SHIFT (18U) +#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK) +#define CCM_CCGR4_CG10_MASK (0x300000U) +#define CCM_CCGR4_CG10_SHIFT (20U) +#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK) +#define CCM_CCGR4_CG11_MASK (0xC00000U) +#define CCM_CCGR4_CG11_SHIFT (22U) +#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK) +#define CCM_CCGR4_CG12_MASK (0x3000000U) +#define CCM_CCGR4_CG12_SHIFT (24U) +#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK) +#define CCM_CCGR4_CG13_MASK (0xC000000U) +#define CCM_CCGR4_CG13_SHIFT (26U) +#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK) +#define CCM_CCGR4_CG14_MASK (0x30000000U) +#define CCM_CCGR4_CG14_SHIFT (28U) +#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK) +#define CCM_CCGR4_CG15_MASK (0xC0000000U) +#define CCM_CCGR4_CG15_SHIFT (30U) +#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK) + +/*! @name CCGR5 - CCM Clock Gating Register 5 */ +#define CCM_CCGR5_CG0_MASK (0x3U) +#define CCM_CCGR5_CG0_SHIFT (0U) +#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK) +#define CCM_CCGR5_CG1_MASK (0xCU) +#define CCM_CCGR5_CG1_SHIFT (2U) +#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK) +#define CCM_CCGR5_CG2_MASK (0x30U) +#define CCM_CCGR5_CG2_SHIFT (4U) +#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK) +#define CCM_CCGR5_CG3_MASK (0xC0U) +#define CCM_CCGR5_CG3_SHIFT (6U) +#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK) +#define CCM_CCGR5_CG4_MASK (0x300U) +#define CCM_CCGR5_CG4_SHIFT (8U) +#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK) +#define CCM_CCGR5_CG5_MASK (0xC00U) +#define CCM_CCGR5_CG5_SHIFT (10U) +#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK) +#define CCM_CCGR5_CG6_MASK (0x3000U) +#define CCM_CCGR5_CG6_SHIFT (12U) +#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK) +#define CCM_CCGR5_CG7_MASK (0xC000U) +#define CCM_CCGR5_CG7_SHIFT (14U) +#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK) +#define CCM_CCGR5_CG8_MASK (0x30000U) +#define CCM_CCGR5_CG8_SHIFT (16U) +#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK) +#define CCM_CCGR5_CG9_MASK (0xC0000U) +#define CCM_CCGR5_CG9_SHIFT (18U) +#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK) +#define CCM_CCGR5_CG10_MASK (0x300000U) +#define CCM_CCGR5_CG10_SHIFT (20U) +#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK) +#define CCM_CCGR5_CG11_MASK (0xC00000U) +#define CCM_CCGR5_CG11_SHIFT (22U) +#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK) +#define CCM_CCGR5_CG12_MASK (0x3000000U) +#define CCM_CCGR5_CG12_SHIFT (24U) +#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK) +#define CCM_CCGR5_CG13_MASK (0xC000000U) +#define CCM_CCGR5_CG13_SHIFT (26U) +#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK) +#define CCM_CCGR5_CG14_MASK (0x30000000U) +#define CCM_CCGR5_CG14_SHIFT (28U) +#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK) +#define CCM_CCGR5_CG15_MASK (0xC0000000U) +#define CCM_CCGR5_CG15_SHIFT (30U) +#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK) + +/*! @name CCGR6 - CCM Clock Gating Register 6 */ +#define CCM_CCGR6_CG0_MASK (0x3U) +#define CCM_CCGR6_CG0_SHIFT (0U) +#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK) +#define CCM_CCGR6_CG1_MASK (0xCU) +#define CCM_CCGR6_CG1_SHIFT (2U) +#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK) +#define CCM_CCGR6_CG2_MASK (0x30U) +#define CCM_CCGR6_CG2_SHIFT (4U) +#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK) +#define CCM_CCGR6_CG3_MASK (0xC0U) +#define CCM_CCGR6_CG3_SHIFT (6U) +#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK) +#define CCM_CCGR6_CG4_MASK (0x300U) +#define CCM_CCGR6_CG4_SHIFT (8U) +#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK) +#define CCM_CCGR6_CG5_MASK (0xC00U) +#define CCM_CCGR6_CG5_SHIFT (10U) +#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK) +#define CCM_CCGR6_CG6_MASK (0x3000U) +#define CCM_CCGR6_CG6_SHIFT (12U) +#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK) +#define CCM_CCGR6_CG7_MASK (0xC000U) +#define CCM_CCGR6_CG7_SHIFT (14U) +#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK) +#define CCM_CCGR6_CG8_MASK (0x30000U) +#define CCM_CCGR6_CG8_SHIFT (16U) +#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK) +#define CCM_CCGR6_CG9_MASK (0xC0000U) +#define CCM_CCGR6_CG9_SHIFT (18U) +#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK) +#define CCM_CCGR6_CG10_MASK (0x300000U) +#define CCM_CCGR6_CG10_SHIFT (20U) +#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK) +#define CCM_CCGR6_CG11_MASK (0xC00000U) +#define CCM_CCGR6_CG11_SHIFT (22U) +#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK) +#define CCM_CCGR6_CG12_MASK (0x3000000U) +#define CCM_CCGR6_CG12_SHIFT (24U) +#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK) +#define CCM_CCGR6_CG13_MASK (0xC000000U) +#define CCM_CCGR6_CG13_SHIFT (26U) +#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK) +#define CCM_CCGR6_CG14_MASK (0x30000000U) +#define CCM_CCGR6_CG14_SHIFT (28U) +#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK) +#define CCM_CCGR6_CG15_MASK (0xC0000000U) +#define CCM_CCGR6_CG15_SHIFT (30U) +#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK) + +/*! @name CMEOR - CCM Module Enable Overide Register */ +#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U) +#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U) +#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK) +#define CCM_CMEOR_MOD_EN_OV_EPIT_MASK (0x40U) +#define CCM_CMEOR_MOD_EN_OV_EPIT_SHIFT (6U) +#define CCM_CMEOR_MOD_EN_OV_EPIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_EPIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_EPIT_MASK) +#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U) +#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U) +#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) + + +/*! + * @} + */ /* end of group CCM_Register_Masks */ + + +/* CCM - Peripheral instance base addresses */ +/** Peripheral CCM base address */ +#define CCM_BASE (g_ccm_vbase) //(0x20C4000u) +/** Peripheral CCM base pointer */ +#define CCM ((CCM_Type *)CCM_BASE) +/** Array initializer of CCM peripheral base addresses */ +#define CCM_BASE_ADDRS { CCM_BASE } +/** Array initializer of CCM peripheral base pointers */ +#define CCM_BASE_PTRS { CCM } +/** Interrupt vectors for the CCM peripheral type */ +#define CCM_IRQS { CCM_IRQ1_IRQn, CCM_IRQ2_IRQn } + +/*! + * @} + */ /* end of group CCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer + * @{ + */ + +/** CCM_ANALOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t PLL_ARM; /**< Analog ARM PLL control Register, offset: 0x0 */ + __IO uint32_t PLL_ARM_SET; /**< Analog ARM PLL control Register, offset: 0x4 */ + __IO uint32_t PLL_ARM_CLR; /**< Analog ARM PLL control Register, offset: 0x8 */ + __IO uint32_t PLL_ARM_TOG; /**< Analog ARM PLL control Register, offset: 0xC */ + __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */ + __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */ + __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */ + __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */ + __IO uint32_t PLL_USB2; /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */ + __IO uint32_t PLL_USB2_SET; /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */ + __IO uint32_t PLL_USB2_CLR; /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */ + __IO uint32_t PLL_USB2_TOG; /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */ + __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */ + __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */ + __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */ + __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */ + __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */ + uint8_t RESERVED_2[12]; + __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */ + __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */ + __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */ + __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */ + __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */ + uint8_t RESERVED_3[12]; + __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */ + uint8_t RESERVED_4[12]; + __IO uint32_t PLL_VIDEO; /**< Analog Video PLL control Register, offset: 0xA0 */ + __IO uint32_t PLL_VIDEO_SET; /**< Analog Video PLL control Register, offset: 0xA4 */ + __IO uint32_t PLL_VIDEO_CLR; /**< Analog Video PLL control Register, offset: 0xA8 */ + __IO uint32_t PLL_VIDEO_TOG; /**< Analog Video PLL control Register, offset: 0xAC */ + __IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */ + uint8_t RESERVED_6[28]; + __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */ + __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */ + __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */ + __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */ + __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */ + __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */ + __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */ + __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */ + __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */ + __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */ + __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */ + __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */ + uint8_t RESERVED_7[64]; + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ + __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ + __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ + __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ + __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */ + __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */ + __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */ + __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */ +} CCM_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/*! @name PLL_ARM - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK) + +/*! @name PLL_ARM_SET - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK) + +/*! @name PLL_ARM_CLR - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK) + +/*! @name PLL_ARM_TOG - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK) + +/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK) + +/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK) + +/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK) + +/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK) + +/*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK) + +/*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK) + +/*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK) + +/*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK) + +/*! @name PLL_SYS - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK) + +/*! @name PLL_SYS_SET - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) + +/*! @name PLL_SYS_CLR - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) + +/*! @name PLL_SYS_TOG - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) + +/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */ +#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) +#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) +#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) + +/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) + +/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) + +/*! @name PLL_AUDIO - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) + +/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) + +/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK) + +/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK) + +/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) + +/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) + +/*! @name PLL_VIDEO - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) + +/*! @name PLL_VIDEO_SET - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK) + +/*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK) + +/*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK) + +/*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) + +/*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) + +/*! @name PLL_ENET - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK) + +/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK) + +/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK) + +/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK) + +/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK) + +/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK) + +/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK) + +/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) + +/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) + +/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) + +/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK) + +/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK) + +/*! @name MISC0 - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK) + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK) + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK) + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK) + +/*! @name MISC1 - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK) + +/*! @name MISC1_SET - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK) + +/*! @name MISC1_CLR - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK) + +/*! @name MISC1_TOG - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK) + +/*! @name MISC2 - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) + +/*! @name MISC2_SET - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK) + +/*! @name MISC2_CLR - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK) + +/*! @name MISC2_TOG - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK) + + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Masks */ + + +/* CCM_ANALOG - Peripheral instance base addresses */ +/** Peripheral CCM_ANALOG base address */ +#define CCM_ANALOG_BASE (g_ccm_analog_vbase) //(0x20C8000u) +/** Peripheral CCM_ANALOG base pointer */ +#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) +/** Array initializer of CCM_ANALOG peripheral base addresses */ +#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } +/** Array initializer of CCM_ANALOG peripheral base pointers */ +#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } + +/*! + * @} + */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CSI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer + * @{ + */ + +/** CSI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */ + __IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */ + __IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */ + __I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */ + __I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */ + __IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */ + __IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */ + __IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */ + __IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */ + __IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */ + __IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */ + __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */ + uint8_t RESERVED_1[16]; + __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */ + __IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */ +} CSI_Type; + +/* ---------------------------------------------------------------------------- + -- CSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Masks CSI Register Masks + * @{ + */ + +/*! @name CSICR1 - CSI Control Register 1 */ +#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U) +#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U) +#define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK) +#define CSI_CSICR1_REDGE_MASK (0x2U) +#define CSI_CSICR1_REDGE_SHIFT (1U) +#define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK) +#define CSI_CSICR1_INV_PCLK_MASK (0x4U) +#define CSI_CSICR1_INV_PCLK_SHIFT (2U) +#define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK) +#define CSI_CSICR1_INV_DATA_MASK (0x8U) +#define CSI_CSICR1_INV_DATA_SHIFT (3U) +#define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK) +#define CSI_CSICR1_GCLK_MODE_MASK (0x10U) +#define CSI_CSICR1_GCLK_MODE_SHIFT (4U) +#define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK) +#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U) +#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U) +#define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK) +#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U) +#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U) +#define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK) +#define CSI_CSICR1_PACK_DIR_MASK (0x80U) +#define CSI_CSICR1_PACK_DIR_SHIFT (7U) +#define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK) +#define CSI_CSICR1_FCC_MASK (0x100U) +#define CSI_CSICR1_FCC_SHIFT (8U) +#define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK) +#define CSI_CSICR1_CCIR_EN_MASK (0x400U) +#define CSI_CSICR1_CCIR_EN_SHIFT (10U) +#define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK) +#define CSI_CSICR1_HSYNC_POL_MASK (0x800U) +#define CSI_CSICR1_HSYNC_POL_SHIFT (11U) +#define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK) +#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U) +#define CSI_CSICR1_SOF_INTEN_SHIFT (16U) +#define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK) +#define CSI_CSICR1_SOF_POL_MASK (0x20000U) +#define CSI_CSICR1_SOF_POL_SHIFT (17U) +#define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK) +#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U) +#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U) +#define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U) +#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U) +#define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U) +#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U) +#define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK) +#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U) +#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U) +#define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK) +#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U) +#define CSI_CSICR1_COF_INT_EN_SHIFT (26U) +#define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK) +#define CSI_CSICR1_VIDEO_MODE_MASK (0x8000000U) +#define CSI_CSICR1_VIDEO_MODE_SHIFT (27U) +#define CSI_CSICR1_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_VIDEO_MODE_SHIFT)) & CSI_CSICR1_VIDEO_MODE_MASK) +#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U) +#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U) +#define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK) +#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U) +#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U) +#define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK) +#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U) +#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U) +#define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK) +#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U) +#define CSI_CSICR1_SWAP16_EN_SHIFT (31U) +#define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK) + +/*! @name CSICR2 - CSI Control Register 2 */ +#define CSI_CSICR2_HSC_MASK (0xFFU) +#define CSI_CSICR2_HSC_SHIFT (0U) +#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK) +#define CSI_CSICR2_VSC_MASK (0xFF00U) +#define CSI_CSICR2_VSC_SHIFT (8U) +#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK) +#define CSI_CSICR2_LVRM_MASK (0x70000U) +#define CSI_CSICR2_LVRM_SHIFT (16U) +#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK) +#define CSI_CSICR2_BTS_MASK (0x180000U) +#define CSI_CSICR2_BTS_SHIFT (19U) +#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK) +#define CSI_CSICR2_SCE_MASK (0x800000U) +#define CSI_CSICR2_SCE_SHIFT (23U) +#define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK) +#define CSI_CSICR2_AFS_MASK (0x3000000U) +#define CSI_CSICR2_AFS_SHIFT (24U) +#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK) +#define CSI_CSICR2_DRM_MASK (0x4000000U) +#define CSI_CSICR2_DRM_SHIFT (26U) +#define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK) + +/*! @name CSICR3 - CSI Control Register 3 */ +#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U) +#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U) +#define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK) +#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U) +#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U) +#define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK) +#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U) +#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U) +#define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK) +#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U) +#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U) +#define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK) +#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U) +#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U) +#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK) +#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U) +#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U) +#define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK) +#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U) +#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U) +#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK) +#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U) +#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U) +#define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK) +#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U) +#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U) +#define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK) +#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U) +#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U) +#define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK) +#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U) +#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U) +#define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK) +#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U) +#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U) +#define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK) +#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U) +#define CSI_CSICR3_FRMCNT_SHIFT (16U) +#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK) + +/*! @name CSISTATFIFO - CSI Statistic FIFO Register */ +#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU) +#define CSI_CSISTATFIFO_STAT_SHIFT (0U) +#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK) + +/*! @name CSIRFIFO - CSI RX FIFO Register */ +#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU) +#define CSI_CSIRFIFO_IMAGE_SHIFT (0U) +#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK) + +/*! @name CSIRXCNT - CSI RX Count Register */ +#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU) +#define CSI_CSIRXCNT_RXCNT_SHIFT (0U) +#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK) + +/*! @name CSISR - CSI Status Register */ +#define CSI_CSISR_DRDY_MASK (0x1U) +#define CSI_CSISR_DRDY_SHIFT (0U) +#define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK) +#define CSI_CSISR_ECC_INT_MASK (0x2U) +#define CSI_CSISR_ECC_INT_SHIFT (1U) +#define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK) +#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U) +#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U) +#define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK) +#define CSI_CSISR_COF_INT_MASK (0x2000U) +#define CSI_CSISR_COF_INT_SHIFT (13U) +#define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK) +#define CSI_CSISR_F1_INT_MASK (0x4000U) +#define CSI_CSISR_F1_INT_SHIFT (14U) +#define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK) +#define CSI_CSISR_F2_INT_MASK (0x8000U) +#define CSI_CSISR_F2_INT_SHIFT (15U) +#define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK) +#define CSI_CSISR_SOF_INT_MASK (0x10000U) +#define CSI_CSISR_SOF_INT_SHIFT (16U) +#define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK) +#define CSI_CSISR_EOF_INT_MASK (0x20000U) +#define CSI_CSISR_EOF_INT_SHIFT (17U) +#define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK) +#define CSI_CSISR_RxFF_INT_MASK (0x40000U) +#define CSI_CSISR_RxFF_INT_SHIFT (18U) +#define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK) +#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U) +#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U) +#define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) +#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U) +#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U) +#define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK) +#define CSI_CSISR_STATFF_INT_MASK (0x200000U) +#define CSI_CSISR_STATFF_INT_SHIFT (21U) +#define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK) +#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U) +#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U) +#define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK) +#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U) +#define CSI_CSISR_RF_OR_INT_SHIFT (24U) +#define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK) +#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U) +#define CSI_CSISR_SF_OR_INT_SHIFT (25U) +#define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK) +#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U) +#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U) +#define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK) +#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U) +#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U) +#define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK) + +/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */ +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) + +/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */ +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) + +/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */ +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK) + +/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */ +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK) + +/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */ +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK) + +/*! @name CSIIMAG_PARA - CSI Image Parameter Register */ +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK) + +/*! @name CSICR18 - CSI Control Register 18 */ +#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U) +#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U) +#define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK) +#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U) +#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U) +#define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U) +#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK) +#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U) +#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U) +#define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U) +#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U) +#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK) +#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U) +#define CSI_CSICR18_AHB_HPROT_SHIFT (12U) +#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK) +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK (0x30000U) +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT (16U) +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT)) & CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK) +#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U) +#define CSI_CSICR18_MASK_OPTION_SHIFT (18U) +#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK) +#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U) +#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U) +#define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK) + +/*! @name CSICR19 - CSI Control Register 19 */ +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) + + +/*! + * @} + */ /* end of group CSI_Register_Masks */ + + +/* CSI - Peripheral instance base addresses */ +/** Peripheral CSI base address */ +#define CSI_BASE (0x21C4000u) +/** Peripheral CSI base pointer */ +#define CSI ((CSI_Type *)CSI_BASE) +/** Array initializer of CSI peripheral base addresses */ +#define CSI_BASE_ADDRS { CSI_BASE } +/** Array initializer of CSI peripheral base pointers */ +#define CSI_BASE_PTRS { CSI } +/** Interrupt vectors for the CSI peripheral type */ +#define CSI_IRQS { CSI_IRQn } + +/*! + * @} + */ /* end of group CSI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer + * @{ + */ + +/** DCP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DCP control register 0, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t STAT; /**< DCP status register, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CHANNELCTRL; /**< DCP channel control register, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CAPABILITY0; /**< DCP capability 0 register, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __I uint32_t CAPABILITY1; /**< DCP capability 1 register, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t CONTEXT; /**< DCP context buffer pointer, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t KEY; /**< DCP key index, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t KEYDATA; /**< DCP key data, offset: 0x70 */ + uint8_t RESERVED_7[12]; + __I uint32_t PACKET0; /**< DCP work packet 0 status register, offset: 0x80 */ + uint8_t RESERVED_8[12]; + __I uint32_t PACKET1; /**< DCP work packet 1 status register, offset: 0x90 */ + uint8_t RESERVED_9[12]; + __I uint32_t PACKET2; /**< DCP work packet 2 status register, offset: 0xA0 */ + uint8_t RESERVED_10[12]; + __I uint32_t PACKET3; /**< DCP work packet 3 status register, offset: 0xB0 */ + uint8_t RESERVED_11[12]; + __I uint32_t PACKET4; /**< DCP work packet 4 status register, offset: 0xC0 */ + uint8_t RESERVED_12[12]; + __I uint32_t PACKET5; /**< DCP work packet 5 status register, offset: 0xD0 */ + uint8_t RESERVED_13[12]; + __I uint32_t PACKET6; /**< DCP work packet 6 status register, offset: 0xE0 */ + uint8_t RESERVED_14[28]; + __IO uint32_t CH0CMDPTR; /**< DCP channel 0 command pointer address register, offset: 0x100 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CH0SEMA; /**< DCP channel 0 semaphore register, offset: 0x110 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CH0STAT; /**< DCP channel 0 status register, offset: 0x120 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CH0OPTS; /**< DCP channel 0 options register, offset: 0x130 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CH1CMDPTR; /**< DCP channel 1 command pointer address register, offset: 0x140 */ + uint8_t RESERVED_19[12]; + __IO uint32_t CH1SEMA; /**< DCP channel 1 semaphore register, offset: 0x150 */ + uint8_t RESERVED_20[12]; + __IO uint32_t CH1STAT; /**< DCP channel 1 status register, offset: 0x160 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CH1OPTS; /**< DCP channel 1 options register, offset: 0x170 */ + uint8_t RESERVED_22[12]; + __IO uint32_t CH2CMDPTR; /**< DCP channel 2 command pointer address register, offset: 0x180 */ + uint8_t RESERVED_23[12]; + __IO uint32_t CH2SEMA; /**< DCP channel 2 semaphore register, offset: 0x190 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CH2STAT; /**< DCP channel 2 status register, offset: 0x1A0 */ + uint8_t RESERVED_25[12]; + __IO uint32_t CH2OPTS; /**< DCP channel 2 options register, offset: 0x1B0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t CH3CMDPTR; /**< DCP channel 3 command pointer address register, offset: 0x1C0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CH3SEMA; /**< DCP channel 3 semaphore register, offset: 0x1D0 */ + uint8_t RESERVED_28[12]; + __IO uint32_t CH3STAT; /**< DCP channel 3 status register, offset: 0x1E0 */ + uint8_t RESERVED_29[12]; + __IO uint32_t CH3OPTS; /**< DCP channel 3 options register, offset: 0x1F0 */ + uint8_t RESERVED_30[524]; + __IO uint32_t DBGSELECT; /**< DCP debug select register, offset: 0x400 */ + uint8_t RESERVED_31[12]; + __I uint32_t DBGDATA; /**< DCP debug data register, offset: 0x410 */ + uint8_t RESERVED_32[12]; + __IO uint32_t PAGETABLE; /**< DCP page table register, offset: 0x420 */ + uint8_t RESERVED_33[12]; + __I uint32_t VERSION; /**< DCP version register, offset: 0x430 */ +} DCP_Type; + +/* ---------------------------------------------------------------------------- + -- DCP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Register_Masks DCP Register Masks + * @{ + */ + +/*! @name CTRL - DCP control register 0 */ +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_PRESENT_SHA_SHIFT (28U) +#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK) +#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U) +#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_CLKGATE_SHIFT (30U) +#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK) +#define DCP_CTRL_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_SFTRST_SHIFT (31U) +#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK) + +/*! @name STAT - DCP status register */ +#define DCP_STAT_IRQ_MASK (0xFU) +#define DCP_STAT_IRQ_SHIFT (0U) +#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK) +#define DCP_STAT_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK) +#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_READY_CHANNELS_SHIFT (16U) +#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK) +#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_CUR_CHANNEL_SHIFT (24U) +#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK) +#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK) + +/*! @name CHANNELCTRL - DCP channel control register */ +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U) +#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK) + +/*! @name CAPABILITY0 - DCP capability 0 register */ +#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU) +#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U) +#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK) +#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U) +#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U) +#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK) +#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U) +#define DCP_CAPABILITY0_RSVD_SHIFT (12U) +#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK) + +/*! @name CAPABILITY1 - DCP capability 1 register */ +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU) +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U) +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U) +#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK) + +/*! @name CONTEXT - DCP context buffer pointer */ +#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CONTEXT_ADDR_SHIFT (0U) +#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK) + +/*! @name KEY - DCP key index */ +#define DCP_KEY_SUBWORD_MASK (0x3U) +#define DCP_KEY_SUBWORD_SHIFT (0U) +#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK) +#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU) +#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U) +#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK) +#define DCP_KEY_INDEX_MASK (0x30U) +#define DCP_KEY_INDEX_SHIFT (4U) +#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK) +#define DCP_KEY_RSVD_INDEX_MASK (0xC0U) +#define DCP_KEY_RSVD_INDEX_SHIFT (6U) +#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK) +#define DCP_KEY_RSVD_MASK (0xFFFFFF00U) +#define DCP_KEY_RSVD_SHIFT (8U) +#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK) + +/*! @name KEYDATA - DCP key data */ +#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_KEYDATA_DATA_SHIFT (0U) +#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK) + +/*! @name PACKET0 - DCP work packet 0 status register */ +#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET0_ADDR_SHIFT (0U) +#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK) + +/*! @name PACKET1 - DCP work packet 1 status register */ +#define DCP_PACKET1_INTERRUPT_MASK (0x1U) +#define DCP_PACKET1_INTERRUPT_SHIFT (0U) +#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK) +#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U) +#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U) +#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK) +#define DCP_PACKET1_CHAIN_MASK (0x4U) +#define DCP_PACKET1_CHAIN_SHIFT (2U) +#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK) +#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U) +#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U) +#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK) +#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U) +#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U) +#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK) +#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U) +#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U) +#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK) +#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U) +#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U) +#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK) +#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U) +#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U) +#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK) +#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U) +#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U) +#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK) +#define DCP_PACKET1_OTP_KEY_MASK (0x400U) +#define DCP_PACKET1_OTP_KEY_SHIFT (10U) +#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK) +#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U) +#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U) +#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK) +#define DCP_PACKET1_HASH_INIT_MASK (0x1000U) +#define DCP_PACKET1_HASH_INIT_SHIFT (12U) +#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK) +#define DCP_PACKET1_HASH_TERM_MASK (0x2000U) +#define DCP_PACKET1_HASH_TERM_SHIFT (13U) +#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK) +#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U) +#define DCP_PACKET1_CHECK_HASH_SHIFT (14U) +#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK) +#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U) +#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U) +#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK) +#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U) +#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U) +#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK) +#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U) +#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U) +#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK) +#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U) +#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U) +#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK) +#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U) +#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U) +#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK) +#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U) +#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U) +#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK) +#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U) +#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U) +#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK) +#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U) +#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U) +#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK) +#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U) +#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U) +#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK) +#define DCP_PACKET1_TAG_MASK (0xFF000000U) +#define DCP_PACKET1_TAG_SHIFT (24U) +#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK) + +/*! @name PACKET2 - DCP work packet 2 status register */ +#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU) +#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U) +#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK) +#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U) +#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U) +#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK) +#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U) +#define DCP_PACKET2_KEY_SELECT_SHIFT (8U) +#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK) +#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U) +#define DCP_PACKET2_HASH_SELECT_SHIFT (16U) +#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK) +#define DCP_PACKET2_RSVD_MASK (0xF00000U) +#define DCP_PACKET2_RSVD_SHIFT (20U) +#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK) +#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U) +#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U) +#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK) + +/*! @name PACKET3 - DCP work packet 3 status register */ +#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET3_ADDR_SHIFT (0U) +#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK) + +/*! @name PACKET4 - DCP work packet 4 status register */ +#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET4_ADDR_SHIFT (0U) +#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK) + +/*! @name PACKET5 - DCP work packet 5 status register */ +#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU) +#define DCP_PACKET5_COUNT_SHIFT (0U) +#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK) + +/*! @name PACKET6 - DCP work packet 6 status register */ +#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET6_ADDR_SHIFT (0U) +#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK) + +/*! @name CH0CMDPTR - DCP channel 0 command pointer address register */ +#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH0CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK) + +/*! @name CH0SEMA - DCP channel 0 semaphore register */ +#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH0SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK) +#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH0SEMA_VALUE_SHIFT (16U) +#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK) + +/*! @name CH0STAT - DCP channel 0 status register */ +#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK) +#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK) +#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK) +#define DCP_CH0STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK) +#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK) +#define DCP_CH0STAT_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_TAG_SHIFT (24U) +#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK) + +/*! @name CH0OPTS - DCP channel 0 options register */ +#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK) + +/*! @name CH1CMDPTR - DCP channel 1 command pointer address register */ +#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH1CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK) + +/*! @name CH1SEMA - DCP channel 1 semaphore register */ +#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH1SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK) +#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH1SEMA_VALUE_SHIFT (16U) +#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK) + +/*! @name CH1STAT - DCP channel 1 status register */ +#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK) +#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK) +#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK) +#define DCP_CH1STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK) +#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK) +#define DCP_CH1STAT_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_TAG_SHIFT (24U) +#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK) + +/*! @name CH1OPTS - DCP channel 1 options register */ +#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK) + +/*! @name CH2CMDPTR - DCP channel 2 command pointer address register */ +#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH2CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK) + +/*! @name CH2SEMA - DCP channel 2 semaphore register */ +#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH2SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK) +#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH2SEMA_VALUE_SHIFT (16U) +#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK) + +/*! @name CH2STAT - DCP channel 2 status register */ +#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK) +#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK) +#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK) +#define DCP_CH2STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK) +#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK) +#define DCP_CH2STAT_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_TAG_SHIFT (24U) +#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK) + +/*! @name CH2OPTS - DCP channel 2 options register */ +#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK) + +/*! @name CH3CMDPTR - DCP channel 3 command pointer address register */ +#define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH3CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK) + +/*! @name CH3SEMA - DCP channel 3 semaphore register */ +#define DCP_CH3SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH3SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK) +#define DCP_CH3SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH3SEMA_VALUE_SHIFT (16U) +#define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK) + +/*! @name CH3STAT - DCP channel 3 status register */ +#define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK) +#define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK) +#define DCP_CH3STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK) +#define DCP_CH3STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK) +#define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK) +#define DCP_CH3STAT_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_TAG_SHIFT (24U) +#define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK) + +/*! @name CH3OPTS - DCP channel 3 options register */ +#define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK) + +/*! @name DBGSELECT - DCP debug select register */ +#define DCP_DBGSELECT_INDEX_MASK (0xFFU) +#define DCP_DBGSELECT_INDEX_SHIFT (0U) +#define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK) +#define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U) +#define DCP_DBGSELECT_RSVD_SHIFT (8U) +#define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK) + +/*! @name DBGDATA - DCP debug data register */ +#define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_DBGDATA_DATA_SHIFT (0U) +#define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK) + +/*! @name PAGETABLE - DCP page table register */ +#define DCP_PAGETABLE_ENABLE_MASK (0x1U) +#define DCP_PAGETABLE_ENABLE_SHIFT (0U) +#define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK) +#define DCP_PAGETABLE_FLUSH_MASK (0x2U) +#define DCP_PAGETABLE_FLUSH_SHIFT (1U) +#define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK) +#define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU) +#define DCP_PAGETABLE_BASE_SHIFT (2U) +#define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK) + +/*! @name VERSION - DCP version register */ +#define DCP_VERSION_STEP_MASK (0xFFFFU) +#define DCP_VERSION_STEP_SHIFT (0U) +#define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK) +#define DCP_VERSION_MINOR_MASK (0xFF0000U) +#define DCP_VERSION_MINOR_SHIFT (16U) +#define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK) +#define DCP_VERSION_MAJOR_MASK (0xFF000000U) +#define DCP_VERSION_MAJOR_SHIFT (24U) +#define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) + + +/*! + * @} + */ /* end of group DCP_Register_Masks */ + + +/* DCP - Peripheral instance base addresses */ +/** Peripheral DCP base address */ +#define DCP_BASE (0x2280000u) +/** Peripheral DCP base pointer */ +#define DCP ((DCP_Type *)DCP_BASE) +/** Array initializer of DCP peripheral base addresses */ +#define DCP_BASE_ADDRS { DCP_BASE } +/** Array initializer of DCP peripheral base pointers */ +#define DCP_BASE_PTRS { DCP } +/** Interrupt vectors for the DCP peripheral type */ +#define DCP_IRQS { DCP_IRQ_IRQn } +#define DCP_VMI_IRQS { DCP_VMI_IRQ_IRQn } +#define DCP_SEC_IRQS { DCP_SEC_IRQ_IRQn } + +/*! + * @} + */ /* end of group DCP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ECSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer + * @{ + */ + +/** ECSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t RXDATA; /**< Receive Data Register, offset: 0x0 */ + __O uint32_t TXDATA; /**< Transmit Data Register, offset: 0x4 */ + __IO uint32_t CONREG; /**< Control Register, offset: 0x8 */ + __IO uint32_t CONFIGREG; /**< Config Register, offset: 0xC */ + __IO uint32_t INTREG; /**< Interrupt Control Register, offset: 0x10 */ + __IO uint32_t DMAREG; /**< DMA Control Register, offset: 0x14 */ + __IO uint32_t STATREG; /**< Status Register, offset: 0x18 */ + __IO uint32_t PERIODREG; /**< Sample Period Control Register, offset: 0x1C */ + __IO uint32_t TESTREG; /**< Test Control Register, offset: 0x20 */ + uint8_t RESERVED_0[28]; + __O uint32_t MSGDATA; /**< Message Data Register, offset: 0x40 */ +} ECSPI_Type; + +/* ---------------------------------------------------------------------------- + -- ECSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Register_Masks ECSPI Register Masks + * @{ + */ + +/*! @name RXDATA - Receive Data Register */ +#define ECSPI_RXDATA_ECSPI_RXDATA_MASK (0xFFFFFFFFU) +#define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT (0U) +#define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_RXDATA_ECSPI_RXDATA_SHIFT)) & ECSPI_RXDATA_ECSPI_RXDATA_MASK) + +/*! @name TXDATA - Transmit Data Register */ +#define ECSPI_TXDATA_ECSPI_TXDATA_MASK (0xFFFFFFFFU) +#define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT (0U) +#define ECSPI_TXDATA_ECSPI_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TXDATA_ECSPI_TXDATA_SHIFT)) & ECSPI_TXDATA_ECSPI_TXDATA_MASK) + +/*! @name CONREG - Control Register */ +#define ECSPI_CONREG_EN_MASK (0x1U) +#define ECSPI_CONREG_EN_SHIFT (0U) +#define ECSPI_CONREG_EN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_EN_SHIFT)) & ECSPI_CONREG_EN_MASK) +#define ECSPI_CONREG_HT_MASK (0x2U) +#define ECSPI_CONREG_HT_SHIFT (1U) +#define ECSPI_CONREG_HT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_HT_SHIFT)) & ECSPI_CONREG_HT_MASK) +#define ECSPI_CONREG_XCH_MASK (0x4U) +#define ECSPI_CONREG_XCH_SHIFT (2U) +#define ECSPI_CONREG_XCH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_XCH_SHIFT)) & ECSPI_CONREG_XCH_MASK) +#define ECSPI_CONREG_SMC_MASK (0x8U) +#define ECSPI_CONREG_SMC_SHIFT (3U) +#define ECSPI_CONREG_SMC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_SMC_SHIFT)) & ECSPI_CONREG_SMC_MASK) +#define ECSPI_CONREG_CHANNEL_MODE_MASK (0xF0U) +#define ECSPI_CONREG_CHANNEL_MODE_SHIFT (4U) +#define ECSPI_CONREG_CHANNEL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_MODE_SHIFT)) & ECSPI_CONREG_CHANNEL_MODE_MASK) +#define ECSPI_CONREG_POST_DIVIDER_MASK (0xF00U) +#define ECSPI_CONREG_POST_DIVIDER_SHIFT (8U) +#define ECSPI_CONREG_POST_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_POST_DIVIDER_SHIFT)) & ECSPI_CONREG_POST_DIVIDER_MASK) +#define ECSPI_CONREG_PRE_DIVIDER_MASK (0xF000U) +#define ECSPI_CONREG_PRE_DIVIDER_SHIFT (12U) +#define ECSPI_CONREG_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_PRE_DIVIDER_SHIFT)) & ECSPI_CONREG_PRE_DIVIDER_MASK) +#define ECSPI_CONREG_DRCTL_MASK (0x30000U) +#define ECSPI_CONREG_DRCTL_SHIFT (16U) +#define ECSPI_CONREG_DRCTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_DRCTL_SHIFT)) & ECSPI_CONREG_DRCTL_MASK) +#define ECSPI_CONREG_CHANNEL_SELECT_MASK (0xC0000U) +#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT (18U) +#define ECSPI_CONREG_CHANNEL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_SELECT_SHIFT)) & ECSPI_CONREG_CHANNEL_SELECT_MASK) +#define ECSPI_CONREG_BURST_LENGTH_MASK (0xFFF00000U) +#define ECSPI_CONREG_BURST_LENGTH_SHIFT (20U) +#define ECSPI_CONREG_BURST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_BURST_LENGTH_SHIFT)) & ECSPI_CONREG_BURST_LENGTH_MASK) + +/*! @name CONFIGREG - Config Register */ +#define ECSPI_CONFIGREG_SCLK_PHA_MASK (0xFU) +#define ECSPI_CONFIGREG_SCLK_PHA_SHIFT (0U) +#define ECSPI_CONFIGREG_SCLK_PHA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_PHA_SHIFT)) & ECSPI_CONFIGREG_SCLK_PHA_MASK) +#define ECSPI_CONFIGREG_SCLK_POL_MASK (0xF0U) +#define ECSPI_CONFIGREG_SCLK_POL_SHIFT (4U) +#define ECSPI_CONFIGREG_SCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_POL_SHIFT)) & ECSPI_CONFIGREG_SCLK_POL_MASK) +#define ECSPI_CONFIGREG_SS_CTL_MASK (0xF00U) +#define ECSPI_CONFIGREG_SS_CTL_SHIFT (8U) +#define ECSPI_CONFIGREG_SS_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_CTL_SHIFT)) & ECSPI_CONFIGREG_SS_CTL_MASK) +#define ECSPI_CONFIGREG_SS_POL_MASK (0xF000U) +#define ECSPI_CONFIGREG_SS_POL_SHIFT (12U) +#define ECSPI_CONFIGREG_SS_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_POL_SHIFT)) & ECSPI_CONFIGREG_SS_POL_MASK) +#define ECSPI_CONFIGREG_DATA_CTL_MASK (0xF0000U) +#define ECSPI_CONFIGREG_DATA_CTL_SHIFT (16U) +#define ECSPI_CONFIGREG_DATA_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_DATA_CTL_SHIFT)) & ECSPI_CONFIGREG_DATA_CTL_MASK) +#define ECSPI_CONFIGREG_SCLK_CTL_MASK (0xF00000U) +#define ECSPI_CONFIGREG_SCLK_CTL_SHIFT (20U) +#define ECSPI_CONFIGREG_SCLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_CTL_SHIFT)) & ECSPI_CONFIGREG_SCLK_CTL_MASK) +#define ECSPI_CONFIGREG_HT_LENGTH_MASK (0x1F000000U) +#define ECSPI_CONFIGREG_HT_LENGTH_SHIFT (24U) +#define ECSPI_CONFIGREG_HT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_HT_LENGTH_SHIFT)) & ECSPI_CONFIGREG_HT_LENGTH_MASK) + +/*! @name INTREG - Interrupt Control Register */ +#define ECSPI_INTREG_TEEN_MASK (0x1U) +#define ECSPI_INTREG_TEEN_SHIFT (0U) +#define ECSPI_INTREG_TEEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TEEN_SHIFT)) & ECSPI_INTREG_TEEN_MASK) +#define ECSPI_INTREG_TDREN_MASK (0x2U) +#define ECSPI_INTREG_TDREN_SHIFT (1U) +#define ECSPI_INTREG_TDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TDREN_SHIFT)) & ECSPI_INTREG_TDREN_MASK) +#define ECSPI_INTREG_TFEN_MASK (0x4U) +#define ECSPI_INTREG_TFEN_SHIFT (2U) +#define ECSPI_INTREG_TFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TFEN_SHIFT)) & ECSPI_INTREG_TFEN_MASK) +#define ECSPI_INTREG_RREN_MASK (0x8U) +#define ECSPI_INTREG_RREN_SHIFT (3U) +#define ECSPI_INTREG_RREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RREN_SHIFT)) & ECSPI_INTREG_RREN_MASK) +#define ECSPI_INTREG_RDREN_MASK (0x10U) +#define ECSPI_INTREG_RDREN_SHIFT (4U) +#define ECSPI_INTREG_RDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RDREN_SHIFT)) & ECSPI_INTREG_RDREN_MASK) +#define ECSPI_INTREG_RFEN_MASK (0x20U) +#define ECSPI_INTREG_RFEN_SHIFT (5U) +#define ECSPI_INTREG_RFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RFEN_SHIFT)) & ECSPI_INTREG_RFEN_MASK) +#define ECSPI_INTREG_ROEN_MASK (0x40U) +#define ECSPI_INTREG_ROEN_SHIFT (6U) +#define ECSPI_INTREG_ROEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_ROEN_SHIFT)) & ECSPI_INTREG_ROEN_MASK) +#define ECSPI_INTREG_TCEN_MASK (0x80U) +#define ECSPI_INTREG_TCEN_SHIFT (7U) +#define ECSPI_INTREG_TCEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TCEN_SHIFT)) & ECSPI_INTREG_TCEN_MASK) + +/*! @name DMAREG - DMA Control Register */ +#define ECSPI_DMAREG_TX_THRESHOLD_MASK (0x3FU) +#define ECSPI_DMAREG_TX_THRESHOLD_SHIFT (0U) +#define ECSPI_DMAREG_TX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_TX_THRESHOLD_MASK) +#define ECSPI_DMAREG_TEDEN_MASK (0x80U) +#define ECSPI_DMAREG_TEDEN_SHIFT (7U) +#define ECSPI_DMAREG_TEDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TEDEN_SHIFT)) & ECSPI_DMAREG_TEDEN_MASK) +#define ECSPI_DMAREG_RX_THRESHOLD_MASK (0x3F0000U) +#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT (16U) +#define ECSPI_DMAREG_RX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_RX_THRESHOLD_MASK) +#define ECSPI_DMAREG_RXDEN_MASK (0x800000U) +#define ECSPI_DMAREG_RXDEN_SHIFT (23U) +#define ECSPI_DMAREG_RXDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXDEN_SHIFT)) & ECSPI_DMAREG_RXDEN_MASK) +#define ECSPI_DMAREG_RX_DMA_LENGTH_MASK (0x3F000000U) +#define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT (24U) +#define ECSPI_DMAREG_RX_DMA_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT)) & ECSPI_DMAREG_RX_DMA_LENGTH_MASK) +#define ECSPI_DMAREG_RXTDEN_MASK (0x80000000U) +#define ECSPI_DMAREG_RXTDEN_SHIFT (31U) +#define ECSPI_DMAREG_RXTDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXTDEN_SHIFT)) & ECSPI_DMAREG_RXTDEN_MASK) + +/*! @name STATREG - Status Register */ +#define ECSPI_STATREG_TE_MASK (0x1U) +#define ECSPI_STATREG_TE_SHIFT (0U) +#define ECSPI_STATREG_TE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TE_SHIFT)) & ECSPI_STATREG_TE_MASK) +#define ECSPI_STATREG_TDR_MASK (0x2U) +#define ECSPI_STATREG_TDR_SHIFT (1U) +#define ECSPI_STATREG_TDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TDR_SHIFT)) & ECSPI_STATREG_TDR_MASK) +#define ECSPI_STATREG_TF_MASK (0x4U) +#define ECSPI_STATREG_TF_SHIFT (2U) +#define ECSPI_STATREG_TF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TF_SHIFT)) & ECSPI_STATREG_TF_MASK) +#define ECSPI_STATREG_RR_MASK (0x8U) +#define ECSPI_STATREG_RR_SHIFT (3U) +#define ECSPI_STATREG_RR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RR_SHIFT)) & ECSPI_STATREG_RR_MASK) +#define ECSPI_STATREG_RDR_MASK (0x10U) +#define ECSPI_STATREG_RDR_SHIFT (4U) +#define ECSPI_STATREG_RDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RDR_SHIFT)) & ECSPI_STATREG_RDR_MASK) +#define ECSPI_STATREG_RF_MASK (0x20U) +#define ECSPI_STATREG_RF_SHIFT (5U) +#define ECSPI_STATREG_RF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RF_SHIFT)) & ECSPI_STATREG_RF_MASK) +#define ECSPI_STATREG_RO_MASK (0x40U) +#define ECSPI_STATREG_RO_SHIFT (6U) +#define ECSPI_STATREG_RO(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RO_SHIFT)) & ECSPI_STATREG_RO_MASK) +#define ECSPI_STATREG_TC_MASK (0x80U) +#define ECSPI_STATREG_TC_SHIFT (7U) +#define ECSPI_STATREG_TC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TC_SHIFT)) & ECSPI_STATREG_TC_MASK) + +/*! @name PERIODREG - Sample Period Control Register */ +#define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK (0x7FFFU) +#define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT (0U) +#define ECSPI_PERIODREG_SAMPLE_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT)) & ECSPI_PERIODREG_SAMPLE_PERIOD_MASK) +#define ECSPI_PERIODREG_CSRC_MASK (0x8000U) +#define ECSPI_PERIODREG_CSRC_SHIFT (15U) +#define ECSPI_PERIODREG_CSRC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSRC_SHIFT)) & ECSPI_PERIODREG_CSRC_MASK) +#define ECSPI_PERIODREG_CSD_CTL_MASK (0x3F0000U) +#define ECSPI_PERIODREG_CSD_CTL_SHIFT (16U) +#define ECSPI_PERIODREG_CSD_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSD_CTL_SHIFT)) & ECSPI_PERIODREG_CSD_CTL_MASK) + +/*! @name TESTREG - Test Control Register */ +#define ECSPI_TESTREG_TXCNT_MASK (0x7FU) +#define ECSPI_TESTREG_TXCNT_SHIFT (0U) +#define ECSPI_TESTREG_TXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_TXCNT_SHIFT)) & ECSPI_TESTREG_TXCNT_MASK) +#define ECSPI_TESTREG_RXCNT_MASK (0x7F00U) +#define ECSPI_TESTREG_RXCNT_SHIFT (8U) +#define ECSPI_TESTREG_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_RXCNT_SHIFT)) & ECSPI_TESTREG_RXCNT_MASK) +#define ECSPI_TESTREG_LBC_MASK (0x80000000U) +#define ECSPI_TESTREG_LBC_SHIFT (31U) +#define ECSPI_TESTREG_LBC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_LBC_SHIFT)) & ECSPI_TESTREG_LBC_MASK) + +/*! @name MSGDATA - Message Data Register */ +#define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK (0xFFFFFFFFU) +#define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT (0U) +#define ECSPI_MSGDATA_ECSPI_MSGDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT)) & ECSPI_MSGDATA_ECSPI_MSGDATA_MASK) + + +/*! + * @} + */ /* end of group ECSPI_Register_Masks */ + + +/* ECSPI - Peripheral instance base addresses */ +/** Peripheral ECSPI1 base address */ +#define ECSPI1_BASE (0x2008000u) +/** Peripheral ECSPI1 base pointer */ +#define ECSPI1 ((ECSPI_Type *)ECSPI1_BASE) +/** Peripheral ECSPI2 base address */ +#define ECSPI2_BASE (0x200C000u) +/** Peripheral ECSPI2 base pointer */ +#define ECSPI2 ((ECSPI_Type *)ECSPI2_BASE) +/** Peripheral ECSPI3 base address */ +#define ECSPI3_BASE (0x2010000u) +/** Peripheral ECSPI3 base pointer */ +#define ECSPI3 ((ECSPI_Type *)ECSPI3_BASE) +/** Peripheral ECSPI4 base address */ +#define ECSPI4_BASE (0x2014000u) +/** Peripheral ECSPI4 base pointer */ +#define ECSPI4 ((ECSPI_Type *)ECSPI4_BASE) +/** Array initializer of ECSPI peripheral base addresses */ +#define ECSPI_BASE_ADDRS { 0u, ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE, ECSPI4_BASE } +/** Array initializer of ECSPI peripheral base pointers */ +#define ECSPI_BASE_PTRS { (ECSPI_Type *)0u, ECSPI1, ECSPI2, ECSPI3, ECSPI4 } +/** Interrupt vectors for the ECSPI peripheral type */ +#define ECSPI_IRQS { NotAvail_IRQn, eCSPI1_IRQn, eCSPI2_IRQn, eCSPI3_IRQn, eCSPI4_IRQn } + +/*! + * @} + */ /* end of group ECSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer + * @{ + */ + +/** EIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CS0GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x0 */ + __IO uint32_t CS0GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x4 */ + __IO uint32_t CS0RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x8 */ + __IO uint32_t CS0RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0xC */ + __IO uint32_t CS0WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x10 */ + __IO uint32_t CS0WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x14 */ + __IO uint32_t CS1GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x18 */ + __IO uint32_t CS1GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x1C */ + __IO uint32_t CS1RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x20 */ + __IO uint32_t CS1RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x24 */ + __IO uint32_t CS1WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x28 */ + __IO uint32_t CS1WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x2C */ + __IO uint32_t CS2GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x30 */ + __IO uint32_t CS2GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x34 */ + __IO uint32_t CS2RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x38 */ + __IO uint32_t CS2RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x3C */ + __IO uint32_t CS2WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x40 */ + __IO uint32_t CS2WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x44 */ + __IO uint32_t CS3GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x48 */ + __IO uint32_t CS3GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x4C */ + __IO uint32_t CS3RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x50 */ + __IO uint32_t CS3RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x54 */ + __IO uint32_t CS3WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x58 */ + __IO uint32_t CS3WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x5C */ + __IO uint32_t CS4GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x60 */ + __IO uint32_t CS4GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x64 */ + __IO uint32_t CS4RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x68 */ + __IO uint32_t CS4RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x6C */ + __IO uint32_t CS4WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x70 */ + __IO uint32_t CS4WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x74 */ + __IO uint32_t CS5GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x78 */ + __IO uint32_t CS5GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x7C */ + __IO uint32_t CS5RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x80 */ + __IO uint32_t CS5RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x84 */ + __IO uint32_t CS5WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x88 */ + __IO uint32_t CS5WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x8C */ + __IO uint32_t WCR; /**< EIM Configuration Register, offset: 0x90 */ +} EIM_Type; + +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/*! @name CS0GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS0GCR1_CSEN_MASK (0x1U) +#define EIM_CS0GCR1_CSEN_SHIFT (0U) +#define EIM_CS0GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CSEN_SHIFT)) & EIM_CS0GCR1_CSEN_MASK) +#define EIM_CS0GCR1_SWR_MASK (0x2U) +#define EIM_CS0GCR1_SWR_SHIFT (1U) +#define EIM_CS0GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_SWR_SHIFT)) & EIM_CS0GCR1_SWR_MASK) +#define EIM_CS0GCR1_SRD_MASK (0x4U) +#define EIM_CS0GCR1_SRD_SHIFT (2U) +#define EIM_CS0GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_SRD_SHIFT)) & EIM_CS0GCR1_SRD_MASK) +#define EIM_CS0GCR1_MUM_MASK (0x8U) +#define EIM_CS0GCR1_MUM_SHIFT (3U) +#define EIM_CS0GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_MUM_SHIFT)) & EIM_CS0GCR1_MUM_MASK) +#define EIM_CS0GCR1_WFL_MASK (0x10U) +#define EIM_CS0GCR1_WFL_SHIFT (4U) +#define EIM_CS0GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_WFL_SHIFT)) & EIM_CS0GCR1_WFL_MASK) +#define EIM_CS0GCR1_RFL_MASK (0x20U) +#define EIM_CS0GCR1_RFL_SHIFT (5U) +#define EIM_CS0GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_RFL_SHIFT)) & EIM_CS0GCR1_RFL_MASK) +#define EIM_CS0GCR1_CRE_MASK (0x40U) +#define EIM_CS0GCR1_CRE_SHIFT (6U) +#define EIM_CS0GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CRE_SHIFT)) & EIM_CS0GCR1_CRE_MASK) +#define EIM_CS0GCR1_CREP_MASK (0x80U) +#define EIM_CS0GCR1_CREP_SHIFT (7U) +#define EIM_CS0GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CREP_SHIFT)) & EIM_CS0GCR1_CREP_MASK) +#define EIM_CS0GCR1_BL_MASK (0x700U) +#define EIM_CS0GCR1_BL_SHIFT (8U) +#define EIM_CS0GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_BL_SHIFT)) & EIM_CS0GCR1_BL_MASK) +#define EIM_CS0GCR1_WC_MASK (0x800U) +#define EIM_CS0GCR1_WC_SHIFT (11U) +#define EIM_CS0GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_WC_SHIFT)) & EIM_CS0GCR1_WC_MASK) +#define EIM_CS0GCR1_BCD_MASK (0x3000U) +#define EIM_CS0GCR1_BCD_SHIFT (12U) +#define EIM_CS0GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_BCD_SHIFT)) & EIM_CS0GCR1_BCD_MASK) +#define EIM_CS0GCR1_BCS_MASK (0xC000U) +#define EIM_CS0GCR1_BCS_SHIFT (14U) +#define EIM_CS0GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_BCS_SHIFT)) & EIM_CS0GCR1_BCS_MASK) +#define EIM_CS0GCR1_DSZ_MASK (0x70000U) +#define EIM_CS0GCR1_DSZ_SHIFT (16U) +#define EIM_CS0GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_DSZ_SHIFT)) & EIM_CS0GCR1_DSZ_MASK) +#define EIM_CS0GCR1_SP_MASK (0x80000U) +#define EIM_CS0GCR1_SP_SHIFT (19U) +#define EIM_CS0GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_SP_SHIFT)) & EIM_CS0GCR1_SP_MASK) +#define EIM_CS0GCR1_CSREC_MASK (0x700000U) +#define EIM_CS0GCR1_CSREC_SHIFT (20U) +#define EIM_CS0GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CSREC_SHIFT)) & EIM_CS0GCR1_CSREC_MASK) +#define EIM_CS0GCR1_AUS_MASK (0x800000U) +#define EIM_CS0GCR1_AUS_SHIFT (23U) +#define EIM_CS0GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_AUS_SHIFT)) & EIM_CS0GCR1_AUS_MASK) +#define EIM_CS0GCR1_GBC_MASK (0x7000000U) +#define EIM_CS0GCR1_GBC_SHIFT (24U) +#define EIM_CS0GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_GBC_SHIFT)) & EIM_CS0GCR1_GBC_MASK) +#define EIM_CS0GCR1_WP_MASK (0x8000000U) +#define EIM_CS0GCR1_WP_SHIFT (27U) +#define EIM_CS0GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_WP_SHIFT)) & EIM_CS0GCR1_WP_MASK) +#define EIM_CS0GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS0GCR1_PSZ_SHIFT (28U) +#define EIM_CS0GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_PSZ_SHIFT)) & EIM_CS0GCR1_PSZ_MASK) + +/*! @name CS0GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS0GCR2_ADH_MASK (0x3U) +#define EIM_CS0GCR2_ADH_SHIFT (0U) +#define EIM_CS0GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_ADH_SHIFT)) & EIM_CS0GCR2_ADH_MASK) +#define EIM_CS0GCR2_DAPS_MASK (0xF0U) +#define EIM_CS0GCR2_DAPS_SHIFT (4U) +#define EIM_CS0GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_DAPS_SHIFT)) & EIM_CS0GCR2_DAPS_MASK) +#define EIM_CS0GCR2_DAE_MASK (0x100U) +#define EIM_CS0GCR2_DAE_SHIFT (8U) +#define EIM_CS0GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_DAE_SHIFT)) & EIM_CS0GCR2_DAE_MASK) +#define EIM_CS0GCR2_DAP_MASK (0x200U) +#define EIM_CS0GCR2_DAP_SHIFT (9U) +#define EIM_CS0GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_DAP_SHIFT)) & EIM_CS0GCR2_DAP_MASK) +#define EIM_CS0GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS0GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS0GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS0GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS0RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS0RCR1_RCSN_MASK (0x7U) +#define EIM_CS0RCR1_RCSN_SHIFT (0U) +#define EIM_CS0RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RCSN_SHIFT)) & EIM_CS0RCR1_RCSN_MASK) +#define EIM_CS0RCR1_RCSA_MASK (0x70U) +#define EIM_CS0RCR1_RCSA_SHIFT (4U) +#define EIM_CS0RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RCSA_SHIFT)) & EIM_CS0RCR1_RCSA_MASK) +#define EIM_CS0RCR1_OEN_MASK (0x700U) +#define EIM_CS0RCR1_OEN_SHIFT (8U) +#define EIM_CS0RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_OEN_SHIFT)) & EIM_CS0RCR1_OEN_MASK) +#define EIM_CS0RCR1_OEA_MASK (0x7000U) +#define EIM_CS0RCR1_OEA_SHIFT (12U) +#define EIM_CS0RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_OEA_SHIFT)) & EIM_CS0RCR1_OEA_MASK) +#define EIM_CS0RCR1_RADVN_MASK (0x70000U) +#define EIM_CS0RCR1_RADVN_SHIFT (16U) +#define EIM_CS0RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RADVN_SHIFT)) & EIM_CS0RCR1_RADVN_MASK) +#define EIM_CS0RCR1_RAL_MASK (0x80000U) +#define EIM_CS0RCR1_RAL_SHIFT (19U) +#define EIM_CS0RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RAL_SHIFT)) & EIM_CS0RCR1_RAL_MASK) +#define EIM_CS0RCR1_RADVA_MASK (0x700000U) +#define EIM_CS0RCR1_RADVA_SHIFT (20U) +#define EIM_CS0RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RADVA_SHIFT)) & EIM_CS0RCR1_RADVA_MASK) +#define EIM_CS0RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS0RCR1_RWSC_SHIFT (24U) +#define EIM_CS0RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RWSC_SHIFT)) & EIM_CS0RCR1_RWSC_MASK) + +/*! @name CS0RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS0RCR2_RBEN_MASK (0x7U) +#define EIM_CS0RCR2_RBEN_SHIFT (0U) +#define EIM_CS0RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RBEN_SHIFT)) & EIM_CS0RCR2_RBEN_MASK) +#define EIM_CS0RCR2_RBE_MASK (0x8U) +#define EIM_CS0RCR2_RBE_SHIFT (3U) +#define EIM_CS0RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RBE_SHIFT)) & EIM_CS0RCR2_RBE_MASK) +#define EIM_CS0RCR2_RBEA_MASK (0x70U) +#define EIM_CS0RCR2_RBEA_SHIFT (4U) +#define EIM_CS0RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RBEA_SHIFT)) & EIM_CS0RCR2_RBEA_MASK) +#define EIM_CS0RCR2_RL_MASK (0x300U) +#define EIM_CS0RCR2_RL_SHIFT (8U) +#define EIM_CS0RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RL_SHIFT)) & EIM_CS0RCR2_RL_MASK) +#define EIM_CS0RCR2_PAT_MASK (0x7000U) +#define EIM_CS0RCR2_PAT_SHIFT (12U) +#define EIM_CS0RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_PAT_SHIFT)) & EIM_CS0RCR2_PAT_MASK) +#define EIM_CS0RCR2_APR_MASK (0x8000U) +#define EIM_CS0RCR2_APR_SHIFT (15U) +#define EIM_CS0RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_APR_SHIFT)) & EIM_CS0RCR2_APR_MASK) + +/*! @name CS0WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS0WCR1_WCSN_MASK (0x7U) +#define EIM_CS0WCR1_WCSN_SHIFT (0U) +#define EIM_CS0WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WCSN_SHIFT)) & EIM_CS0WCR1_WCSN_MASK) +#define EIM_CS0WCR1_WCSA_MASK (0x38U) +#define EIM_CS0WCR1_WCSA_SHIFT (3U) +#define EIM_CS0WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WCSA_SHIFT)) & EIM_CS0WCR1_WCSA_MASK) +#define EIM_CS0WCR1_WEN_MASK (0x1C0U) +#define EIM_CS0WCR1_WEN_SHIFT (6U) +#define EIM_CS0WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WEN_SHIFT)) & EIM_CS0WCR1_WEN_MASK) +#define EIM_CS0WCR1_WEA_MASK (0xE00U) +#define EIM_CS0WCR1_WEA_SHIFT (9U) +#define EIM_CS0WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WEA_SHIFT)) & EIM_CS0WCR1_WEA_MASK) +#define EIM_CS0WCR1_WBEN_MASK (0x7000U) +#define EIM_CS0WCR1_WBEN_SHIFT (12U) +#define EIM_CS0WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WBEN_SHIFT)) & EIM_CS0WCR1_WBEN_MASK) +#define EIM_CS0WCR1_WBEA_MASK (0x38000U) +#define EIM_CS0WCR1_WBEA_SHIFT (15U) +#define EIM_CS0WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WBEA_SHIFT)) & EIM_CS0WCR1_WBEA_MASK) +#define EIM_CS0WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS0WCR1_WADVN_SHIFT (18U) +#define EIM_CS0WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WADVN_SHIFT)) & EIM_CS0WCR1_WADVN_MASK) +#define EIM_CS0WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS0WCR1_WADVA_SHIFT (21U) +#define EIM_CS0WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WADVA_SHIFT)) & EIM_CS0WCR1_WADVA_MASK) +#define EIM_CS0WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS0WCR1_WWSC_SHIFT (24U) +#define EIM_CS0WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WWSC_SHIFT)) & EIM_CS0WCR1_WWSC_MASK) +#define EIM_CS0WCR1_WBED_MASK (0x40000000U) +#define EIM_CS0WCR1_WBED_SHIFT (30U) +#define EIM_CS0WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WBED_SHIFT)) & EIM_CS0WCR1_WBED_MASK) +#define EIM_CS0WCR1_WAL_MASK (0x80000000U) +#define EIM_CS0WCR1_WAL_SHIFT (31U) +#define EIM_CS0WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WAL_SHIFT)) & EIM_CS0WCR1_WAL_MASK) + +/*! @name CS0WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS0WCR2_WBCDD_MASK (0x1U) +#define EIM_CS0WCR2_WBCDD_SHIFT (0U) +#define EIM_CS0WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR2_WBCDD_SHIFT)) & EIM_CS0WCR2_WBCDD_MASK) + +/*! @name CS1GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS1GCR1_CSEN_MASK (0x1U) +#define EIM_CS1GCR1_CSEN_SHIFT (0U) +#define EIM_CS1GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CSEN_SHIFT)) & EIM_CS1GCR1_CSEN_MASK) +#define EIM_CS1GCR1_SWR_MASK (0x2U) +#define EIM_CS1GCR1_SWR_SHIFT (1U) +#define EIM_CS1GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_SWR_SHIFT)) & EIM_CS1GCR1_SWR_MASK) +#define EIM_CS1GCR1_SRD_MASK (0x4U) +#define EIM_CS1GCR1_SRD_SHIFT (2U) +#define EIM_CS1GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_SRD_SHIFT)) & EIM_CS1GCR1_SRD_MASK) +#define EIM_CS1GCR1_MUM_MASK (0x8U) +#define EIM_CS1GCR1_MUM_SHIFT (3U) +#define EIM_CS1GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_MUM_SHIFT)) & EIM_CS1GCR1_MUM_MASK) +#define EIM_CS1GCR1_WFL_MASK (0x10U) +#define EIM_CS1GCR1_WFL_SHIFT (4U) +#define EIM_CS1GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_WFL_SHIFT)) & EIM_CS1GCR1_WFL_MASK) +#define EIM_CS1GCR1_RFL_MASK (0x20U) +#define EIM_CS1GCR1_RFL_SHIFT (5U) +#define EIM_CS1GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_RFL_SHIFT)) & EIM_CS1GCR1_RFL_MASK) +#define EIM_CS1GCR1_CRE_MASK (0x40U) +#define EIM_CS1GCR1_CRE_SHIFT (6U) +#define EIM_CS1GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CRE_SHIFT)) & EIM_CS1GCR1_CRE_MASK) +#define EIM_CS1GCR1_CREP_MASK (0x80U) +#define EIM_CS1GCR1_CREP_SHIFT (7U) +#define EIM_CS1GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CREP_SHIFT)) & EIM_CS1GCR1_CREP_MASK) +#define EIM_CS1GCR1_BL_MASK (0x700U) +#define EIM_CS1GCR1_BL_SHIFT (8U) +#define EIM_CS1GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_BL_SHIFT)) & EIM_CS1GCR1_BL_MASK) +#define EIM_CS1GCR1_WC_MASK (0x800U) +#define EIM_CS1GCR1_WC_SHIFT (11U) +#define EIM_CS1GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_WC_SHIFT)) & EIM_CS1GCR1_WC_MASK) +#define EIM_CS1GCR1_BCD_MASK (0x3000U) +#define EIM_CS1GCR1_BCD_SHIFT (12U) +#define EIM_CS1GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_BCD_SHIFT)) & EIM_CS1GCR1_BCD_MASK) +#define EIM_CS1GCR1_BCS_MASK (0xC000U) +#define EIM_CS1GCR1_BCS_SHIFT (14U) +#define EIM_CS1GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_BCS_SHIFT)) & EIM_CS1GCR1_BCS_MASK) +#define EIM_CS1GCR1_DSZ_MASK (0x70000U) +#define EIM_CS1GCR1_DSZ_SHIFT (16U) +#define EIM_CS1GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_DSZ_SHIFT)) & EIM_CS1GCR1_DSZ_MASK) +#define EIM_CS1GCR1_SP_MASK (0x80000U) +#define EIM_CS1GCR1_SP_SHIFT (19U) +#define EIM_CS1GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_SP_SHIFT)) & EIM_CS1GCR1_SP_MASK) +#define EIM_CS1GCR1_CSREC_MASK (0x700000U) +#define EIM_CS1GCR1_CSREC_SHIFT (20U) +#define EIM_CS1GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CSREC_SHIFT)) & EIM_CS1GCR1_CSREC_MASK) +#define EIM_CS1GCR1_AUS_MASK (0x800000U) +#define EIM_CS1GCR1_AUS_SHIFT (23U) +#define EIM_CS1GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_AUS_SHIFT)) & EIM_CS1GCR1_AUS_MASK) +#define EIM_CS1GCR1_GBC_MASK (0x7000000U) +#define EIM_CS1GCR1_GBC_SHIFT (24U) +#define EIM_CS1GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_GBC_SHIFT)) & EIM_CS1GCR1_GBC_MASK) +#define EIM_CS1GCR1_WP_MASK (0x8000000U) +#define EIM_CS1GCR1_WP_SHIFT (27U) +#define EIM_CS1GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_WP_SHIFT)) & EIM_CS1GCR1_WP_MASK) +#define EIM_CS1GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS1GCR1_PSZ_SHIFT (28U) +#define EIM_CS1GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_PSZ_SHIFT)) & EIM_CS1GCR1_PSZ_MASK) + +/*! @name CS1GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS1GCR2_ADH_MASK (0x3U) +#define EIM_CS1GCR2_ADH_SHIFT (0U) +#define EIM_CS1GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_ADH_SHIFT)) & EIM_CS1GCR2_ADH_MASK) +#define EIM_CS1GCR2_DAPS_MASK (0xF0U) +#define EIM_CS1GCR2_DAPS_SHIFT (4U) +#define EIM_CS1GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_DAPS_SHIFT)) & EIM_CS1GCR2_DAPS_MASK) +#define EIM_CS1GCR2_DAE_MASK (0x100U) +#define EIM_CS1GCR2_DAE_SHIFT (8U) +#define EIM_CS1GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_DAE_SHIFT)) & EIM_CS1GCR2_DAE_MASK) +#define EIM_CS1GCR2_DAP_MASK (0x200U) +#define EIM_CS1GCR2_DAP_SHIFT (9U) +#define EIM_CS1GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_DAP_SHIFT)) & EIM_CS1GCR2_DAP_MASK) +#define EIM_CS1GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS1GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS1GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS1GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS1RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS1RCR1_RCSN_MASK (0x7U) +#define EIM_CS1RCR1_RCSN_SHIFT (0U) +#define EIM_CS1RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RCSN_SHIFT)) & EIM_CS1RCR1_RCSN_MASK) +#define EIM_CS1RCR1_RCSA_MASK (0x70U) +#define EIM_CS1RCR1_RCSA_SHIFT (4U) +#define EIM_CS1RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RCSA_SHIFT)) & EIM_CS1RCR1_RCSA_MASK) +#define EIM_CS1RCR1_OEN_MASK (0x700U) +#define EIM_CS1RCR1_OEN_SHIFT (8U) +#define EIM_CS1RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_OEN_SHIFT)) & EIM_CS1RCR1_OEN_MASK) +#define EIM_CS1RCR1_OEA_MASK (0x7000U) +#define EIM_CS1RCR1_OEA_SHIFT (12U) +#define EIM_CS1RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_OEA_SHIFT)) & EIM_CS1RCR1_OEA_MASK) +#define EIM_CS1RCR1_RADVN_MASK (0x70000U) +#define EIM_CS1RCR1_RADVN_SHIFT (16U) +#define EIM_CS1RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RADVN_SHIFT)) & EIM_CS1RCR1_RADVN_MASK) +#define EIM_CS1RCR1_RAL_MASK (0x80000U) +#define EIM_CS1RCR1_RAL_SHIFT (19U) +#define EIM_CS1RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RAL_SHIFT)) & EIM_CS1RCR1_RAL_MASK) +#define EIM_CS1RCR1_RADVA_MASK (0x700000U) +#define EIM_CS1RCR1_RADVA_SHIFT (20U) +#define EIM_CS1RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RADVA_SHIFT)) & EIM_CS1RCR1_RADVA_MASK) +#define EIM_CS1RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS1RCR1_RWSC_SHIFT (24U) +#define EIM_CS1RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RWSC_SHIFT)) & EIM_CS1RCR1_RWSC_MASK) + +/*! @name CS1RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS1RCR2_RBEN_MASK (0x7U) +#define EIM_CS1RCR2_RBEN_SHIFT (0U) +#define EIM_CS1RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RBEN_SHIFT)) & EIM_CS1RCR2_RBEN_MASK) +#define EIM_CS1RCR2_RBE_MASK (0x8U) +#define EIM_CS1RCR2_RBE_SHIFT (3U) +#define EIM_CS1RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RBE_SHIFT)) & EIM_CS1RCR2_RBE_MASK) +#define EIM_CS1RCR2_RBEA_MASK (0x70U) +#define EIM_CS1RCR2_RBEA_SHIFT (4U) +#define EIM_CS1RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RBEA_SHIFT)) & EIM_CS1RCR2_RBEA_MASK) +#define EIM_CS1RCR2_RL_MASK (0x300U) +#define EIM_CS1RCR2_RL_SHIFT (8U) +#define EIM_CS1RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RL_SHIFT)) & EIM_CS1RCR2_RL_MASK) +#define EIM_CS1RCR2_PAT_MASK (0x7000U) +#define EIM_CS1RCR2_PAT_SHIFT (12U) +#define EIM_CS1RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_PAT_SHIFT)) & EIM_CS1RCR2_PAT_MASK) +#define EIM_CS1RCR2_APR_MASK (0x8000U) +#define EIM_CS1RCR2_APR_SHIFT (15U) +#define EIM_CS1RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_APR_SHIFT)) & EIM_CS1RCR2_APR_MASK) + +/*! @name CS1WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS1WCR1_WCSN_MASK (0x7U) +#define EIM_CS1WCR1_WCSN_SHIFT (0U) +#define EIM_CS1WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WCSN_SHIFT)) & EIM_CS1WCR1_WCSN_MASK) +#define EIM_CS1WCR1_WCSA_MASK (0x38U) +#define EIM_CS1WCR1_WCSA_SHIFT (3U) +#define EIM_CS1WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WCSA_SHIFT)) & EIM_CS1WCR1_WCSA_MASK) +#define EIM_CS1WCR1_WEN_MASK (0x1C0U) +#define EIM_CS1WCR1_WEN_SHIFT (6U) +#define EIM_CS1WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WEN_SHIFT)) & EIM_CS1WCR1_WEN_MASK) +#define EIM_CS1WCR1_WEA_MASK (0xE00U) +#define EIM_CS1WCR1_WEA_SHIFT (9U) +#define EIM_CS1WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WEA_SHIFT)) & EIM_CS1WCR1_WEA_MASK) +#define EIM_CS1WCR1_WBEN_MASK (0x7000U) +#define EIM_CS1WCR1_WBEN_SHIFT (12U) +#define EIM_CS1WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WBEN_SHIFT)) & EIM_CS1WCR1_WBEN_MASK) +#define EIM_CS1WCR1_WBEA_MASK (0x38000U) +#define EIM_CS1WCR1_WBEA_SHIFT (15U) +#define EIM_CS1WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WBEA_SHIFT)) & EIM_CS1WCR1_WBEA_MASK) +#define EIM_CS1WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS1WCR1_WADVN_SHIFT (18U) +#define EIM_CS1WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WADVN_SHIFT)) & EIM_CS1WCR1_WADVN_MASK) +#define EIM_CS1WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS1WCR1_WADVA_SHIFT (21U) +#define EIM_CS1WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WADVA_SHIFT)) & EIM_CS1WCR1_WADVA_MASK) +#define EIM_CS1WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS1WCR1_WWSC_SHIFT (24U) +#define EIM_CS1WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WWSC_SHIFT)) & EIM_CS1WCR1_WWSC_MASK) +#define EIM_CS1WCR1_WBED_MASK (0x40000000U) +#define EIM_CS1WCR1_WBED_SHIFT (30U) +#define EIM_CS1WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WBED_SHIFT)) & EIM_CS1WCR1_WBED_MASK) +#define EIM_CS1WCR1_WAL_MASK (0x80000000U) +#define EIM_CS1WCR1_WAL_SHIFT (31U) +#define EIM_CS1WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WAL_SHIFT)) & EIM_CS1WCR1_WAL_MASK) + +/*! @name CS1WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS1WCR2_WBCDD_MASK (0x1U) +#define EIM_CS1WCR2_WBCDD_SHIFT (0U) +#define EIM_CS1WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR2_WBCDD_SHIFT)) & EIM_CS1WCR2_WBCDD_MASK) + +/*! @name CS2GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS2GCR1_CSEN_MASK (0x1U) +#define EIM_CS2GCR1_CSEN_SHIFT (0U) +#define EIM_CS2GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CSEN_SHIFT)) & EIM_CS2GCR1_CSEN_MASK) +#define EIM_CS2GCR1_SWR_MASK (0x2U) +#define EIM_CS2GCR1_SWR_SHIFT (1U) +#define EIM_CS2GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_SWR_SHIFT)) & EIM_CS2GCR1_SWR_MASK) +#define EIM_CS2GCR1_SRD_MASK (0x4U) +#define EIM_CS2GCR1_SRD_SHIFT (2U) +#define EIM_CS2GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_SRD_SHIFT)) & EIM_CS2GCR1_SRD_MASK) +#define EIM_CS2GCR1_MUM_MASK (0x8U) +#define EIM_CS2GCR1_MUM_SHIFT (3U) +#define EIM_CS2GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_MUM_SHIFT)) & EIM_CS2GCR1_MUM_MASK) +#define EIM_CS2GCR1_WFL_MASK (0x10U) +#define EIM_CS2GCR1_WFL_SHIFT (4U) +#define EIM_CS2GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_WFL_SHIFT)) & EIM_CS2GCR1_WFL_MASK) +#define EIM_CS2GCR1_RFL_MASK (0x20U) +#define EIM_CS2GCR1_RFL_SHIFT (5U) +#define EIM_CS2GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_RFL_SHIFT)) & EIM_CS2GCR1_RFL_MASK) +#define EIM_CS2GCR1_CRE_MASK (0x40U) +#define EIM_CS2GCR1_CRE_SHIFT (6U) +#define EIM_CS2GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CRE_SHIFT)) & EIM_CS2GCR1_CRE_MASK) +#define EIM_CS2GCR1_CREP_MASK (0x80U) +#define EIM_CS2GCR1_CREP_SHIFT (7U) +#define EIM_CS2GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CREP_SHIFT)) & EIM_CS2GCR1_CREP_MASK) +#define EIM_CS2GCR1_BL_MASK (0x700U) +#define EIM_CS2GCR1_BL_SHIFT (8U) +#define EIM_CS2GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_BL_SHIFT)) & EIM_CS2GCR1_BL_MASK) +#define EIM_CS2GCR1_WC_MASK (0x800U) +#define EIM_CS2GCR1_WC_SHIFT (11U) +#define EIM_CS2GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_WC_SHIFT)) & EIM_CS2GCR1_WC_MASK) +#define EIM_CS2GCR1_BCD_MASK (0x3000U) +#define EIM_CS2GCR1_BCD_SHIFT (12U) +#define EIM_CS2GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_BCD_SHIFT)) & EIM_CS2GCR1_BCD_MASK) +#define EIM_CS2GCR1_BCS_MASK (0xC000U) +#define EIM_CS2GCR1_BCS_SHIFT (14U) +#define EIM_CS2GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_BCS_SHIFT)) & EIM_CS2GCR1_BCS_MASK) +#define EIM_CS2GCR1_DSZ_MASK (0x70000U) +#define EIM_CS2GCR1_DSZ_SHIFT (16U) +#define EIM_CS2GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_DSZ_SHIFT)) & EIM_CS2GCR1_DSZ_MASK) +#define EIM_CS2GCR1_SP_MASK (0x80000U) +#define EIM_CS2GCR1_SP_SHIFT (19U) +#define EIM_CS2GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_SP_SHIFT)) & EIM_CS2GCR1_SP_MASK) +#define EIM_CS2GCR1_CSREC_MASK (0x700000U) +#define EIM_CS2GCR1_CSREC_SHIFT (20U) +#define EIM_CS2GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CSREC_SHIFT)) & EIM_CS2GCR1_CSREC_MASK) +#define EIM_CS2GCR1_AUS_MASK (0x800000U) +#define EIM_CS2GCR1_AUS_SHIFT (23U) +#define EIM_CS2GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_AUS_SHIFT)) & EIM_CS2GCR1_AUS_MASK) +#define EIM_CS2GCR1_GBC_MASK (0x7000000U) +#define EIM_CS2GCR1_GBC_SHIFT (24U) +#define EIM_CS2GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_GBC_SHIFT)) & EIM_CS2GCR1_GBC_MASK) +#define EIM_CS2GCR1_WP_MASK (0x8000000U) +#define EIM_CS2GCR1_WP_SHIFT (27U) +#define EIM_CS2GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_WP_SHIFT)) & EIM_CS2GCR1_WP_MASK) +#define EIM_CS2GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS2GCR1_PSZ_SHIFT (28U) +#define EIM_CS2GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_PSZ_SHIFT)) & EIM_CS2GCR1_PSZ_MASK) + +/*! @name CS2GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS2GCR2_ADH_MASK (0x3U) +#define EIM_CS2GCR2_ADH_SHIFT (0U) +#define EIM_CS2GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_ADH_SHIFT)) & EIM_CS2GCR2_ADH_MASK) +#define EIM_CS2GCR2_DAPS_MASK (0xF0U) +#define EIM_CS2GCR2_DAPS_SHIFT (4U) +#define EIM_CS2GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_DAPS_SHIFT)) & EIM_CS2GCR2_DAPS_MASK) +#define EIM_CS2GCR2_DAE_MASK (0x100U) +#define EIM_CS2GCR2_DAE_SHIFT (8U) +#define EIM_CS2GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_DAE_SHIFT)) & EIM_CS2GCR2_DAE_MASK) +#define EIM_CS2GCR2_DAP_MASK (0x200U) +#define EIM_CS2GCR2_DAP_SHIFT (9U) +#define EIM_CS2GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_DAP_SHIFT)) & EIM_CS2GCR2_DAP_MASK) +#define EIM_CS2GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS2GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS2GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS2GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS2RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS2RCR1_RCSN_MASK (0x7U) +#define EIM_CS2RCR1_RCSN_SHIFT (0U) +#define EIM_CS2RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RCSN_SHIFT)) & EIM_CS2RCR1_RCSN_MASK) +#define EIM_CS2RCR1_RCSA_MASK (0x70U) +#define EIM_CS2RCR1_RCSA_SHIFT (4U) +#define EIM_CS2RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RCSA_SHIFT)) & EIM_CS2RCR1_RCSA_MASK) +#define EIM_CS2RCR1_OEN_MASK (0x700U) +#define EIM_CS2RCR1_OEN_SHIFT (8U) +#define EIM_CS2RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_OEN_SHIFT)) & EIM_CS2RCR1_OEN_MASK) +#define EIM_CS2RCR1_OEA_MASK (0x7000U) +#define EIM_CS2RCR1_OEA_SHIFT (12U) +#define EIM_CS2RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_OEA_SHIFT)) & EIM_CS2RCR1_OEA_MASK) +#define EIM_CS2RCR1_RADVN_MASK (0x70000U) +#define EIM_CS2RCR1_RADVN_SHIFT (16U) +#define EIM_CS2RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RADVN_SHIFT)) & EIM_CS2RCR1_RADVN_MASK) +#define EIM_CS2RCR1_RAL_MASK (0x80000U) +#define EIM_CS2RCR1_RAL_SHIFT (19U) +#define EIM_CS2RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RAL_SHIFT)) & EIM_CS2RCR1_RAL_MASK) +#define EIM_CS2RCR1_RADVA_MASK (0x700000U) +#define EIM_CS2RCR1_RADVA_SHIFT (20U) +#define EIM_CS2RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RADVA_SHIFT)) & EIM_CS2RCR1_RADVA_MASK) +#define EIM_CS2RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS2RCR1_RWSC_SHIFT (24U) +#define EIM_CS2RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RWSC_SHIFT)) & EIM_CS2RCR1_RWSC_MASK) + +/*! @name CS2RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS2RCR2_RBEN_MASK (0x7U) +#define EIM_CS2RCR2_RBEN_SHIFT (0U) +#define EIM_CS2RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RBEN_SHIFT)) & EIM_CS2RCR2_RBEN_MASK) +#define EIM_CS2RCR2_RBE_MASK (0x8U) +#define EIM_CS2RCR2_RBE_SHIFT (3U) +#define EIM_CS2RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RBE_SHIFT)) & EIM_CS2RCR2_RBE_MASK) +#define EIM_CS2RCR2_RBEA_MASK (0x70U) +#define EIM_CS2RCR2_RBEA_SHIFT (4U) +#define EIM_CS2RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RBEA_SHIFT)) & EIM_CS2RCR2_RBEA_MASK) +#define EIM_CS2RCR2_RL_MASK (0x300U) +#define EIM_CS2RCR2_RL_SHIFT (8U) +#define EIM_CS2RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RL_SHIFT)) & EIM_CS2RCR2_RL_MASK) +#define EIM_CS2RCR2_PAT_MASK (0x7000U) +#define EIM_CS2RCR2_PAT_SHIFT (12U) +#define EIM_CS2RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_PAT_SHIFT)) & EIM_CS2RCR2_PAT_MASK) +#define EIM_CS2RCR2_APR_MASK (0x8000U) +#define EIM_CS2RCR2_APR_SHIFT (15U) +#define EIM_CS2RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_APR_SHIFT)) & EIM_CS2RCR2_APR_MASK) + +/*! @name CS2WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS2WCR1_WCSN_MASK (0x7U) +#define EIM_CS2WCR1_WCSN_SHIFT (0U) +#define EIM_CS2WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WCSN_SHIFT)) & EIM_CS2WCR1_WCSN_MASK) +#define EIM_CS2WCR1_WCSA_MASK (0x38U) +#define EIM_CS2WCR1_WCSA_SHIFT (3U) +#define EIM_CS2WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WCSA_SHIFT)) & EIM_CS2WCR1_WCSA_MASK) +#define EIM_CS2WCR1_WEN_MASK (0x1C0U) +#define EIM_CS2WCR1_WEN_SHIFT (6U) +#define EIM_CS2WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WEN_SHIFT)) & EIM_CS2WCR1_WEN_MASK) +#define EIM_CS2WCR1_WEA_MASK (0xE00U) +#define EIM_CS2WCR1_WEA_SHIFT (9U) +#define EIM_CS2WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WEA_SHIFT)) & EIM_CS2WCR1_WEA_MASK) +#define EIM_CS2WCR1_WBEN_MASK (0x7000U) +#define EIM_CS2WCR1_WBEN_SHIFT (12U) +#define EIM_CS2WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WBEN_SHIFT)) & EIM_CS2WCR1_WBEN_MASK) +#define EIM_CS2WCR1_WBEA_MASK (0x38000U) +#define EIM_CS2WCR1_WBEA_SHIFT (15U) +#define EIM_CS2WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WBEA_SHIFT)) & EIM_CS2WCR1_WBEA_MASK) +#define EIM_CS2WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS2WCR1_WADVN_SHIFT (18U) +#define EIM_CS2WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WADVN_SHIFT)) & EIM_CS2WCR1_WADVN_MASK) +#define EIM_CS2WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS2WCR1_WADVA_SHIFT (21U) +#define EIM_CS2WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WADVA_SHIFT)) & EIM_CS2WCR1_WADVA_MASK) +#define EIM_CS2WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS2WCR1_WWSC_SHIFT (24U) +#define EIM_CS2WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WWSC_SHIFT)) & EIM_CS2WCR1_WWSC_MASK) +#define EIM_CS2WCR1_WBED_MASK (0x40000000U) +#define EIM_CS2WCR1_WBED_SHIFT (30U) +#define EIM_CS2WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WBED_SHIFT)) & EIM_CS2WCR1_WBED_MASK) +#define EIM_CS2WCR1_WAL_MASK (0x80000000U) +#define EIM_CS2WCR1_WAL_SHIFT (31U) +#define EIM_CS2WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WAL_SHIFT)) & EIM_CS2WCR1_WAL_MASK) + +/*! @name CS2WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS2WCR2_WBCDD_MASK (0x1U) +#define EIM_CS2WCR2_WBCDD_SHIFT (0U) +#define EIM_CS2WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR2_WBCDD_SHIFT)) & EIM_CS2WCR2_WBCDD_MASK) + +/*! @name CS3GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS3GCR1_CSEN_MASK (0x1U) +#define EIM_CS3GCR1_CSEN_SHIFT (0U) +#define EIM_CS3GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CSEN_SHIFT)) & EIM_CS3GCR1_CSEN_MASK) +#define EIM_CS3GCR1_SWR_MASK (0x2U) +#define EIM_CS3GCR1_SWR_SHIFT (1U) +#define EIM_CS3GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_SWR_SHIFT)) & EIM_CS3GCR1_SWR_MASK) +#define EIM_CS3GCR1_SRD_MASK (0x4U) +#define EIM_CS3GCR1_SRD_SHIFT (2U) +#define EIM_CS3GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_SRD_SHIFT)) & EIM_CS3GCR1_SRD_MASK) +#define EIM_CS3GCR1_MUM_MASK (0x8U) +#define EIM_CS3GCR1_MUM_SHIFT (3U) +#define EIM_CS3GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_MUM_SHIFT)) & EIM_CS3GCR1_MUM_MASK) +#define EIM_CS3GCR1_WFL_MASK (0x10U) +#define EIM_CS3GCR1_WFL_SHIFT (4U) +#define EIM_CS3GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_WFL_SHIFT)) & EIM_CS3GCR1_WFL_MASK) +#define EIM_CS3GCR1_RFL_MASK (0x20U) +#define EIM_CS3GCR1_RFL_SHIFT (5U) +#define EIM_CS3GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_RFL_SHIFT)) & EIM_CS3GCR1_RFL_MASK) +#define EIM_CS3GCR1_CRE_MASK (0x40U) +#define EIM_CS3GCR1_CRE_SHIFT (6U) +#define EIM_CS3GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CRE_SHIFT)) & EIM_CS3GCR1_CRE_MASK) +#define EIM_CS3GCR1_CREP_MASK (0x80U) +#define EIM_CS3GCR1_CREP_SHIFT (7U) +#define EIM_CS3GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CREP_SHIFT)) & EIM_CS3GCR1_CREP_MASK) +#define EIM_CS3GCR1_BL_MASK (0x700U) +#define EIM_CS3GCR1_BL_SHIFT (8U) +#define EIM_CS3GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_BL_SHIFT)) & EIM_CS3GCR1_BL_MASK) +#define EIM_CS3GCR1_WC_MASK (0x800U) +#define EIM_CS3GCR1_WC_SHIFT (11U) +#define EIM_CS3GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_WC_SHIFT)) & EIM_CS3GCR1_WC_MASK) +#define EIM_CS3GCR1_BCD_MASK (0x3000U) +#define EIM_CS3GCR1_BCD_SHIFT (12U) +#define EIM_CS3GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_BCD_SHIFT)) & EIM_CS3GCR1_BCD_MASK) +#define EIM_CS3GCR1_BCS_MASK (0xC000U) +#define EIM_CS3GCR1_BCS_SHIFT (14U) +#define EIM_CS3GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_BCS_SHIFT)) & EIM_CS3GCR1_BCS_MASK) +#define EIM_CS3GCR1_DSZ_MASK (0x70000U) +#define EIM_CS3GCR1_DSZ_SHIFT (16U) +#define EIM_CS3GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_DSZ_SHIFT)) & EIM_CS3GCR1_DSZ_MASK) +#define EIM_CS3GCR1_SP_MASK (0x80000U) +#define EIM_CS3GCR1_SP_SHIFT (19U) +#define EIM_CS3GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_SP_SHIFT)) & EIM_CS3GCR1_SP_MASK) +#define EIM_CS3GCR1_CSREC_MASK (0x700000U) +#define EIM_CS3GCR1_CSREC_SHIFT (20U) +#define EIM_CS3GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CSREC_SHIFT)) & EIM_CS3GCR1_CSREC_MASK) +#define EIM_CS3GCR1_AUS_MASK (0x800000U) +#define EIM_CS3GCR1_AUS_SHIFT (23U) +#define EIM_CS3GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_AUS_SHIFT)) & EIM_CS3GCR1_AUS_MASK) +#define EIM_CS3GCR1_GBC_MASK (0x7000000U) +#define EIM_CS3GCR1_GBC_SHIFT (24U) +#define EIM_CS3GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_GBC_SHIFT)) & EIM_CS3GCR1_GBC_MASK) +#define EIM_CS3GCR1_WP_MASK (0x8000000U) +#define EIM_CS3GCR1_WP_SHIFT (27U) +#define EIM_CS3GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_WP_SHIFT)) & EIM_CS3GCR1_WP_MASK) +#define EIM_CS3GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS3GCR1_PSZ_SHIFT (28U) +#define EIM_CS3GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_PSZ_SHIFT)) & EIM_CS3GCR1_PSZ_MASK) + +/*! @name CS3GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS3GCR2_ADH_MASK (0x3U) +#define EIM_CS3GCR2_ADH_SHIFT (0U) +#define EIM_CS3GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_ADH_SHIFT)) & EIM_CS3GCR2_ADH_MASK) +#define EIM_CS3GCR2_DAPS_MASK (0xF0U) +#define EIM_CS3GCR2_DAPS_SHIFT (4U) +#define EIM_CS3GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_DAPS_SHIFT)) & EIM_CS3GCR2_DAPS_MASK) +#define EIM_CS3GCR2_DAE_MASK (0x100U) +#define EIM_CS3GCR2_DAE_SHIFT (8U) +#define EIM_CS3GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_DAE_SHIFT)) & EIM_CS3GCR2_DAE_MASK) +#define EIM_CS3GCR2_DAP_MASK (0x200U) +#define EIM_CS3GCR2_DAP_SHIFT (9U) +#define EIM_CS3GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_DAP_SHIFT)) & EIM_CS3GCR2_DAP_MASK) +#define EIM_CS3GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS3GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS3GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS3GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS3RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS3RCR1_RCSN_MASK (0x7U) +#define EIM_CS3RCR1_RCSN_SHIFT (0U) +#define EIM_CS3RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RCSN_SHIFT)) & EIM_CS3RCR1_RCSN_MASK) +#define EIM_CS3RCR1_RCSA_MASK (0x70U) +#define EIM_CS3RCR1_RCSA_SHIFT (4U) +#define EIM_CS3RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RCSA_SHIFT)) & EIM_CS3RCR1_RCSA_MASK) +#define EIM_CS3RCR1_OEN_MASK (0x700U) +#define EIM_CS3RCR1_OEN_SHIFT (8U) +#define EIM_CS3RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_OEN_SHIFT)) & EIM_CS3RCR1_OEN_MASK) +#define EIM_CS3RCR1_OEA_MASK (0x7000U) +#define EIM_CS3RCR1_OEA_SHIFT (12U) +#define EIM_CS3RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_OEA_SHIFT)) & EIM_CS3RCR1_OEA_MASK) +#define EIM_CS3RCR1_RADVN_MASK (0x70000U) +#define EIM_CS3RCR1_RADVN_SHIFT (16U) +#define EIM_CS3RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RADVN_SHIFT)) & EIM_CS3RCR1_RADVN_MASK) +#define EIM_CS3RCR1_RAL_MASK (0x80000U) +#define EIM_CS3RCR1_RAL_SHIFT (19U) +#define EIM_CS3RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RAL_SHIFT)) & EIM_CS3RCR1_RAL_MASK) +#define EIM_CS3RCR1_RADVA_MASK (0x700000U) +#define EIM_CS3RCR1_RADVA_SHIFT (20U) +#define EIM_CS3RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RADVA_SHIFT)) & EIM_CS3RCR1_RADVA_MASK) +#define EIM_CS3RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS3RCR1_RWSC_SHIFT (24U) +#define EIM_CS3RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RWSC_SHIFT)) & EIM_CS3RCR1_RWSC_MASK) + +/*! @name CS3RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS3RCR2_RBEN_MASK (0x7U) +#define EIM_CS3RCR2_RBEN_SHIFT (0U) +#define EIM_CS3RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RBEN_SHIFT)) & EIM_CS3RCR2_RBEN_MASK) +#define EIM_CS3RCR2_RBE_MASK (0x8U) +#define EIM_CS3RCR2_RBE_SHIFT (3U) +#define EIM_CS3RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RBE_SHIFT)) & EIM_CS3RCR2_RBE_MASK) +#define EIM_CS3RCR2_RBEA_MASK (0x70U) +#define EIM_CS3RCR2_RBEA_SHIFT (4U) +#define EIM_CS3RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RBEA_SHIFT)) & EIM_CS3RCR2_RBEA_MASK) +#define EIM_CS3RCR2_RL_MASK (0x300U) +#define EIM_CS3RCR2_RL_SHIFT (8U) +#define EIM_CS3RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RL_SHIFT)) & EIM_CS3RCR2_RL_MASK) +#define EIM_CS3RCR2_PAT_MASK (0x7000U) +#define EIM_CS3RCR2_PAT_SHIFT (12U) +#define EIM_CS3RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_PAT_SHIFT)) & EIM_CS3RCR2_PAT_MASK) +#define EIM_CS3RCR2_APR_MASK (0x8000U) +#define EIM_CS3RCR2_APR_SHIFT (15U) +#define EIM_CS3RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_APR_SHIFT)) & EIM_CS3RCR2_APR_MASK) + +/*! @name CS3WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS3WCR1_WCSN_MASK (0x7U) +#define EIM_CS3WCR1_WCSN_SHIFT (0U) +#define EIM_CS3WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WCSN_SHIFT)) & EIM_CS3WCR1_WCSN_MASK) +#define EIM_CS3WCR1_WCSA_MASK (0x38U) +#define EIM_CS3WCR1_WCSA_SHIFT (3U) +#define EIM_CS3WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WCSA_SHIFT)) & EIM_CS3WCR1_WCSA_MASK) +#define EIM_CS3WCR1_WEN_MASK (0x1C0U) +#define EIM_CS3WCR1_WEN_SHIFT (6U) +#define EIM_CS3WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WEN_SHIFT)) & EIM_CS3WCR1_WEN_MASK) +#define EIM_CS3WCR1_WEA_MASK (0xE00U) +#define EIM_CS3WCR1_WEA_SHIFT (9U) +#define EIM_CS3WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WEA_SHIFT)) & EIM_CS3WCR1_WEA_MASK) +#define EIM_CS3WCR1_WBEN_MASK (0x7000U) +#define EIM_CS3WCR1_WBEN_SHIFT (12U) +#define EIM_CS3WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WBEN_SHIFT)) & EIM_CS3WCR1_WBEN_MASK) +#define EIM_CS3WCR1_WBEA_MASK (0x38000U) +#define EIM_CS3WCR1_WBEA_SHIFT (15U) +#define EIM_CS3WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WBEA_SHIFT)) & EIM_CS3WCR1_WBEA_MASK) +#define EIM_CS3WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS3WCR1_WADVN_SHIFT (18U) +#define EIM_CS3WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WADVN_SHIFT)) & EIM_CS3WCR1_WADVN_MASK) +#define EIM_CS3WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS3WCR1_WADVA_SHIFT (21U) +#define EIM_CS3WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WADVA_SHIFT)) & EIM_CS3WCR1_WADVA_MASK) +#define EIM_CS3WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS3WCR1_WWSC_SHIFT (24U) +#define EIM_CS3WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WWSC_SHIFT)) & EIM_CS3WCR1_WWSC_MASK) +#define EIM_CS3WCR1_WBED_MASK (0x40000000U) +#define EIM_CS3WCR1_WBED_SHIFT (30U) +#define EIM_CS3WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WBED_SHIFT)) & EIM_CS3WCR1_WBED_MASK) +#define EIM_CS3WCR1_WAL_MASK (0x80000000U) +#define EIM_CS3WCR1_WAL_SHIFT (31U) +#define EIM_CS3WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WAL_SHIFT)) & EIM_CS3WCR1_WAL_MASK) + +/*! @name CS3WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS3WCR2_WBCDD_MASK (0x1U) +#define EIM_CS3WCR2_WBCDD_SHIFT (0U) +#define EIM_CS3WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR2_WBCDD_SHIFT)) & EIM_CS3WCR2_WBCDD_MASK) + +/*! @name CS4GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS4GCR1_CSEN_MASK (0x1U) +#define EIM_CS4GCR1_CSEN_SHIFT (0U) +#define EIM_CS4GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CSEN_SHIFT)) & EIM_CS4GCR1_CSEN_MASK) +#define EIM_CS4GCR1_SWR_MASK (0x2U) +#define EIM_CS4GCR1_SWR_SHIFT (1U) +#define EIM_CS4GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_SWR_SHIFT)) & EIM_CS4GCR1_SWR_MASK) +#define EIM_CS4GCR1_SRD_MASK (0x4U) +#define EIM_CS4GCR1_SRD_SHIFT (2U) +#define EIM_CS4GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_SRD_SHIFT)) & EIM_CS4GCR1_SRD_MASK) +#define EIM_CS4GCR1_MUM_MASK (0x8U) +#define EIM_CS4GCR1_MUM_SHIFT (3U) +#define EIM_CS4GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_MUM_SHIFT)) & EIM_CS4GCR1_MUM_MASK) +#define EIM_CS4GCR1_WFL_MASK (0x10U) +#define EIM_CS4GCR1_WFL_SHIFT (4U) +#define EIM_CS4GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_WFL_SHIFT)) & EIM_CS4GCR1_WFL_MASK) +#define EIM_CS4GCR1_RFL_MASK (0x20U) +#define EIM_CS4GCR1_RFL_SHIFT (5U) +#define EIM_CS4GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_RFL_SHIFT)) & EIM_CS4GCR1_RFL_MASK) +#define EIM_CS4GCR1_CRE_MASK (0x40U) +#define EIM_CS4GCR1_CRE_SHIFT (6U) +#define EIM_CS4GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CRE_SHIFT)) & EIM_CS4GCR1_CRE_MASK) +#define EIM_CS4GCR1_CREP_MASK (0x80U) +#define EIM_CS4GCR1_CREP_SHIFT (7U) +#define EIM_CS4GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CREP_SHIFT)) & EIM_CS4GCR1_CREP_MASK) +#define EIM_CS4GCR1_BL_MASK (0x700U) +#define EIM_CS4GCR1_BL_SHIFT (8U) +#define EIM_CS4GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_BL_SHIFT)) & EIM_CS4GCR1_BL_MASK) +#define EIM_CS4GCR1_WC_MASK (0x800U) +#define EIM_CS4GCR1_WC_SHIFT (11U) +#define EIM_CS4GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_WC_SHIFT)) & EIM_CS4GCR1_WC_MASK) +#define EIM_CS4GCR1_BCD_MASK (0x3000U) +#define EIM_CS4GCR1_BCD_SHIFT (12U) +#define EIM_CS4GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_BCD_SHIFT)) & EIM_CS4GCR1_BCD_MASK) +#define EIM_CS4GCR1_BCS_MASK (0xC000U) +#define EIM_CS4GCR1_BCS_SHIFT (14U) +#define EIM_CS4GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_BCS_SHIFT)) & EIM_CS4GCR1_BCS_MASK) +#define EIM_CS4GCR1_DSZ_MASK (0x70000U) +#define EIM_CS4GCR1_DSZ_SHIFT (16U) +#define EIM_CS4GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_DSZ_SHIFT)) & EIM_CS4GCR1_DSZ_MASK) +#define EIM_CS4GCR1_SP_MASK (0x80000U) +#define EIM_CS4GCR1_SP_SHIFT (19U) +#define EIM_CS4GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_SP_SHIFT)) & EIM_CS4GCR1_SP_MASK) +#define EIM_CS4GCR1_CSREC_MASK (0x700000U) +#define EIM_CS4GCR1_CSREC_SHIFT (20U) +#define EIM_CS4GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CSREC_SHIFT)) & EIM_CS4GCR1_CSREC_MASK) +#define EIM_CS4GCR1_AUS_MASK (0x800000U) +#define EIM_CS4GCR1_AUS_SHIFT (23U) +#define EIM_CS4GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_AUS_SHIFT)) & EIM_CS4GCR1_AUS_MASK) +#define EIM_CS4GCR1_GBC_MASK (0x7000000U) +#define EIM_CS4GCR1_GBC_SHIFT (24U) +#define EIM_CS4GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_GBC_SHIFT)) & EIM_CS4GCR1_GBC_MASK) +#define EIM_CS4GCR1_WP_MASK (0x8000000U) +#define EIM_CS4GCR1_WP_SHIFT (27U) +#define EIM_CS4GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_WP_SHIFT)) & EIM_CS4GCR1_WP_MASK) +#define EIM_CS4GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS4GCR1_PSZ_SHIFT (28U) +#define EIM_CS4GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_PSZ_SHIFT)) & EIM_CS4GCR1_PSZ_MASK) + +/*! @name CS4GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS4GCR2_ADH_MASK (0x3U) +#define EIM_CS4GCR2_ADH_SHIFT (0U) +#define EIM_CS4GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_ADH_SHIFT)) & EIM_CS4GCR2_ADH_MASK) +#define EIM_CS4GCR2_DAPS_MASK (0xF0U) +#define EIM_CS4GCR2_DAPS_SHIFT (4U) +#define EIM_CS4GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_DAPS_SHIFT)) & EIM_CS4GCR2_DAPS_MASK) +#define EIM_CS4GCR2_DAE_MASK (0x100U) +#define EIM_CS4GCR2_DAE_SHIFT (8U) +#define EIM_CS4GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_DAE_SHIFT)) & EIM_CS4GCR2_DAE_MASK) +#define EIM_CS4GCR2_DAP_MASK (0x200U) +#define EIM_CS4GCR2_DAP_SHIFT (9U) +#define EIM_CS4GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_DAP_SHIFT)) & EIM_CS4GCR2_DAP_MASK) +#define EIM_CS4GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS4GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS4GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS4GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS4RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS4RCR1_RCSN_MASK (0x7U) +#define EIM_CS4RCR1_RCSN_SHIFT (0U) +#define EIM_CS4RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RCSN_SHIFT)) & EIM_CS4RCR1_RCSN_MASK) +#define EIM_CS4RCR1_RCSA_MASK (0x70U) +#define EIM_CS4RCR1_RCSA_SHIFT (4U) +#define EIM_CS4RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RCSA_SHIFT)) & EIM_CS4RCR1_RCSA_MASK) +#define EIM_CS4RCR1_OEN_MASK (0x700U) +#define EIM_CS4RCR1_OEN_SHIFT (8U) +#define EIM_CS4RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_OEN_SHIFT)) & EIM_CS4RCR1_OEN_MASK) +#define EIM_CS4RCR1_OEA_MASK (0x7000U) +#define EIM_CS4RCR1_OEA_SHIFT (12U) +#define EIM_CS4RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_OEA_SHIFT)) & EIM_CS4RCR1_OEA_MASK) +#define EIM_CS4RCR1_RADVN_MASK (0x70000U) +#define EIM_CS4RCR1_RADVN_SHIFT (16U) +#define EIM_CS4RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RADVN_SHIFT)) & EIM_CS4RCR1_RADVN_MASK) +#define EIM_CS4RCR1_RAL_MASK (0x80000U) +#define EIM_CS4RCR1_RAL_SHIFT (19U) +#define EIM_CS4RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RAL_SHIFT)) & EIM_CS4RCR1_RAL_MASK) +#define EIM_CS4RCR1_RADVA_MASK (0x700000U) +#define EIM_CS4RCR1_RADVA_SHIFT (20U) +#define EIM_CS4RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RADVA_SHIFT)) & EIM_CS4RCR1_RADVA_MASK) +#define EIM_CS4RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS4RCR1_RWSC_SHIFT (24U) +#define EIM_CS4RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RWSC_SHIFT)) & EIM_CS4RCR1_RWSC_MASK) + +/*! @name CS4RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS4RCR2_RBEN_MASK (0x7U) +#define EIM_CS4RCR2_RBEN_SHIFT (0U) +#define EIM_CS4RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RBEN_SHIFT)) & EIM_CS4RCR2_RBEN_MASK) +#define EIM_CS4RCR2_RBE_MASK (0x8U) +#define EIM_CS4RCR2_RBE_SHIFT (3U) +#define EIM_CS4RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RBE_SHIFT)) & EIM_CS4RCR2_RBE_MASK) +#define EIM_CS4RCR2_RBEA_MASK (0x70U) +#define EIM_CS4RCR2_RBEA_SHIFT (4U) +#define EIM_CS4RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RBEA_SHIFT)) & EIM_CS4RCR2_RBEA_MASK) +#define EIM_CS4RCR2_RL_MASK (0x300U) +#define EIM_CS4RCR2_RL_SHIFT (8U) +#define EIM_CS4RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RL_SHIFT)) & EIM_CS4RCR2_RL_MASK) +#define EIM_CS4RCR2_PAT_MASK (0x7000U) +#define EIM_CS4RCR2_PAT_SHIFT (12U) +#define EIM_CS4RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_PAT_SHIFT)) & EIM_CS4RCR2_PAT_MASK) +#define EIM_CS4RCR2_APR_MASK (0x8000U) +#define EIM_CS4RCR2_APR_SHIFT (15U) +#define EIM_CS4RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_APR_SHIFT)) & EIM_CS4RCR2_APR_MASK) + +/*! @name CS4WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS4WCR1_WCSN_MASK (0x7U) +#define EIM_CS4WCR1_WCSN_SHIFT (0U) +#define EIM_CS4WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WCSN_SHIFT)) & EIM_CS4WCR1_WCSN_MASK) +#define EIM_CS4WCR1_WCSA_MASK (0x38U) +#define EIM_CS4WCR1_WCSA_SHIFT (3U) +#define EIM_CS4WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WCSA_SHIFT)) & EIM_CS4WCR1_WCSA_MASK) +#define EIM_CS4WCR1_WEN_MASK (0x1C0U) +#define EIM_CS4WCR1_WEN_SHIFT (6U) +#define EIM_CS4WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WEN_SHIFT)) & EIM_CS4WCR1_WEN_MASK) +#define EIM_CS4WCR1_WEA_MASK (0xE00U) +#define EIM_CS4WCR1_WEA_SHIFT (9U) +#define EIM_CS4WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WEA_SHIFT)) & EIM_CS4WCR1_WEA_MASK) +#define EIM_CS4WCR1_WBEN_MASK (0x7000U) +#define EIM_CS4WCR1_WBEN_SHIFT (12U) +#define EIM_CS4WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WBEN_SHIFT)) & EIM_CS4WCR1_WBEN_MASK) +#define EIM_CS4WCR1_WBEA_MASK (0x38000U) +#define EIM_CS4WCR1_WBEA_SHIFT (15U) +#define EIM_CS4WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WBEA_SHIFT)) & EIM_CS4WCR1_WBEA_MASK) +#define EIM_CS4WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS4WCR1_WADVN_SHIFT (18U) +#define EIM_CS4WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WADVN_SHIFT)) & EIM_CS4WCR1_WADVN_MASK) +#define EIM_CS4WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS4WCR1_WADVA_SHIFT (21U) +#define EIM_CS4WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WADVA_SHIFT)) & EIM_CS4WCR1_WADVA_MASK) +#define EIM_CS4WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS4WCR1_WWSC_SHIFT (24U) +#define EIM_CS4WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WWSC_SHIFT)) & EIM_CS4WCR1_WWSC_MASK) +#define EIM_CS4WCR1_WBED_MASK (0x40000000U) +#define EIM_CS4WCR1_WBED_SHIFT (30U) +#define EIM_CS4WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WBED_SHIFT)) & EIM_CS4WCR1_WBED_MASK) +#define EIM_CS4WCR1_WAL_MASK (0x80000000U) +#define EIM_CS4WCR1_WAL_SHIFT (31U) +#define EIM_CS4WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WAL_SHIFT)) & EIM_CS4WCR1_WAL_MASK) + +/*! @name CS4WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS4WCR2_WBCDD_MASK (0x1U) +#define EIM_CS4WCR2_WBCDD_SHIFT (0U) +#define EIM_CS4WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR2_WBCDD_SHIFT)) & EIM_CS4WCR2_WBCDD_MASK) + +/*! @name CS5GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS5GCR1_CSEN_MASK (0x1U) +#define EIM_CS5GCR1_CSEN_SHIFT (0U) +#define EIM_CS5GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CSEN_SHIFT)) & EIM_CS5GCR1_CSEN_MASK) +#define EIM_CS5GCR1_SWR_MASK (0x2U) +#define EIM_CS5GCR1_SWR_SHIFT (1U) +#define EIM_CS5GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_SWR_SHIFT)) & EIM_CS5GCR1_SWR_MASK) +#define EIM_CS5GCR1_SRD_MASK (0x4U) +#define EIM_CS5GCR1_SRD_SHIFT (2U) +#define EIM_CS5GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_SRD_SHIFT)) & EIM_CS5GCR1_SRD_MASK) +#define EIM_CS5GCR1_MUM_MASK (0x8U) +#define EIM_CS5GCR1_MUM_SHIFT (3U) +#define EIM_CS5GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_MUM_SHIFT)) & EIM_CS5GCR1_MUM_MASK) +#define EIM_CS5GCR1_WFL_MASK (0x10U) +#define EIM_CS5GCR1_WFL_SHIFT (4U) +#define EIM_CS5GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_WFL_SHIFT)) & EIM_CS5GCR1_WFL_MASK) +#define EIM_CS5GCR1_RFL_MASK (0x20U) +#define EIM_CS5GCR1_RFL_SHIFT (5U) +#define EIM_CS5GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_RFL_SHIFT)) & EIM_CS5GCR1_RFL_MASK) +#define EIM_CS5GCR1_CRE_MASK (0x40U) +#define EIM_CS5GCR1_CRE_SHIFT (6U) +#define EIM_CS5GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CRE_SHIFT)) & EIM_CS5GCR1_CRE_MASK) +#define EIM_CS5GCR1_CREP_MASK (0x80U) +#define EIM_CS5GCR1_CREP_SHIFT (7U) +#define EIM_CS5GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CREP_SHIFT)) & EIM_CS5GCR1_CREP_MASK) +#define EIM_CS5GCR1_BL_MASK (0x700U) +#define EIM_CS5GCR1_BL_SHIFT (8U) +#define EIM_CS5GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_BL_SHIFT)) & EIM_CS5GCR1_BL_MASK) +#define EIM_CS5GCR1_WC_MASK (0x800U) +#define EIM_CS5GCR1_WC_SHIFT (11U) +#define EIM_CS5GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_WC_SHIFT)) & EIM_CS5GCR1_WC_MASK) +#define EIM_CS5GCR1_BCD_MASK (0x3000U) +#define EIM_CS5GCR1_BCD_SHIFT (12U) +#define EIM_CS5GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_BCD_SHIFT)) & EIM_CS5GCR1_BCD_MASK) +#define EIM_CS5GCR1_BCS_MASK (0xC000U) +#define EIM_CS5GCR1_BCS_SHIFT (14U) +#define EIM_CS5GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_BCS_SHIFT)) & EIM_CS5GCR1_BCS_MASK) +#define EIM_CS5GCR1_DSZ_MASK (0x70000U) +#define EIM_CS5GCR1_DSZ_SHIFT (16U) +#define EIM_CS5GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_DSZ_SHIFT)) & EIM_CS5GCR1_DSZ_MASK) +#define EIM_CS5GCR1_SP_MASK (0x80000U) +#define EIM_CS5GCR1_SP_SHIFT (19U) +#define EIM_CS5GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_SP_SHIFT)) & EIM_CS5GCR1_SP_MASK) +#define EIM_CS5GCR1_CSREC_MASK (0x700000U) +#define EIM_CS5GCR1_CSREC_SHIFT (20U) +#define EIM_CS5GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CSREC_SHIFT)) & EIM_CS5GCR1_CSREC_MASK) +#define EIM_CS5GCR1_AUS_MASK (0x800000U) +#define EIM_CS5GCR1_AUS_SHIFT (23U) +#define EIM_CS5GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_AUS_SHIFT)) & EIM_CS5GCR1_AUS_MASK) +#define EIM_CS5GCR1_GBC_MASK (0x7000000U) +#define EIM_CS5GCR1_GBC_SHIFT (24U) +#define EIM_CS5GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_GBC_SHIFT)) & EIM_CS5GCR1_GBC_MASK) +#define EIM_CS5GCR1_WP_MASK (0x8000000U) +#define EIM_CS5GCR1_WP_SHIFT (27U) +#define EIM_CS5GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_WP_SHIFT)) & EIM_CS5GCR1_WP_MASK) +#define EIM_CS5GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS5GCR1_PSZ_SHIFT (28U) +#define EIM_CS5GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_PSZ_SHIFT)) & EIM_CS5GCR1_PSZ_MASK) + +/*! @name CS5GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS5GCR2_ADH_MASK (0x3U) +#define EIM_CS5GCR2_ADH_SHIFT (0U) +#define EIM_CS5GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_ADH_SHIFT)) & EIM_CS5GCR2_ADH_MASK) +#define EIM_CS5GCR2_DAPS_MASK (0xF0U) +#define EIM_CS5GCR2_DAPS_SHIFT (4U) +#define EIM_CS5GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_DAPS_SHIFT)) & EIM_CS5GCR2_DAPS_MASK) +#define EIM_CS5GCR2_DAE_MASK (0x100U) +#define EIM_CS5GCR2_DAE_SHIFT (8U) +#define EIM_CS5GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_DAE_SHIFT)) & EIM_CS5GCR2_DAE_MASK) +#define EIM_CS5GCR2_DAP_MASK (0x200U) +#define EIM_CS5GCR2_DAP_SHIFT (9U) +#define EIM_CS5GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_DAP_SHIFT)) & EIM_CS5GCR2_DAP_MASK) +#define EIM_CS5GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS5GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS5GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS5GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS5RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS5RCR1_RCSN_MASK (0x7U) +#define EIM_CS5RCR1_RCSN_SHIFT (0U) +#define EIM_CS5RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RCSN_SHIFT)) & EIM_CS5RCR1_RCSN_MASK) +#define EIM_CS5RCR1_RCSA_MASK (0x70U) +#define EIM_CS5RCR1_RCSA_SHIFT (4U) +#define EIM_CS5RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RCSA_SHIFT)) & EIM_CS5RCR1_RCSA_MASK) +#define EIM_CS5RCR1_OEN_MASK (0x700U) +#define EIM_CS5RCR1_OEN_SHIFT (8U) +#define EIM_CS5RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_OEN_SHIFT)) & EIM_CS5RCR1_OEN_MASK) +#define EIM_CS5RCR1_OEA_MASK (0x7000U) +#define EIM_CS5RCR1_OEA_SHIFT (12U) +#define EIM_CS5RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_OEA_SHIFT)) & EIM_CS5RCR1_OEA_MASK) +#define EIM_CS5RCR1_RADVN_MASK (0x70000U) +#define EIM_CS5RCR1_RADVN_SHIFT (16U) +#define EIM_CS5RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RADVN_SHIFT)) & EIM_CS5RCR1_RADVN_MASK) +#define EIM_CS5RCR1_RAL_MASK (0x80000U) +#define EIM_CS5RCR1_RAL_SHIFT (19U) +#define EIM_CS5RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RAL_SHIFT)) & EIM_CS5RCR1_RAL_MASK) +#define EIM_CS5RCR1_RADVA_MASK (0x700000U) +#define EIM_CS5RCR1_RADVA_SHIFT (20U) +#define EIM_CS5RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RADVA_SHIFT)) & EIM_CS5RCR1_RADVA_MASK) +#define EIM_CS5RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS5RCR1_RWSC_SHIFT (24U) +#define EIM_CS5RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RWSC_SHIFT)) & EIM_CS5RCR1_RWSC_MASK) + +/*! @name CS5RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS5RCR2_RBEN_MASK (0x7U) +#define EIM_CS5RCR2_RBEN_SHIFT (0U) +#define EIM_CS5RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RBEN_SHIFT)) & EIM_CS5RCR2_RBEN_MASK) +#define EIM_CS5RCR2_RBE_MASK (0x8U) +#define EIM_CS5RCR2_RBE_SHIFT (3U) +#define EIM_CS5RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RBE_SHIFT)) & EIM_CS5RCR2_RBE_MASK) +#define EIM_CS5RCR2_RBEA_MASK (0x70U) +#define EIM_CS5RCR2_RBEA_SHIFT (4U) +#define EIM_CS5RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RBEA_SHIFT)) & EIM_CS5RCR2_RBEA_MASK) +#define EIM_CS5RCR2_RL_MASK (0x300U) +#define EIM_CS5RCR2_RL_SHIFT (8U) +#define EIM_CS5RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RL_SHIFT)) & EIM_CS5RCR2_RL_MASK) +#define EIM_CS5RCR2_PAT_MASK (0x7000U) +#define EIM_CS5RCR2_PAT_SHIFT (12U) +#define EIM_CS5RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_PAT_SHIFT)) & EIM_CS5RCR2_PAT_MASK) +#define EIM_CS5RCR2_APR_MASK (0x8000U) +#define EIM_CS5RCR2_APR_SHIFT (15U) +#define EIM_CS5RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_APR_SHIFT)) & EIM_CS5RCR2_APR_MASK) + +/*! @name CS5WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS5WCR1_WCSN_MASK (0x7U) +#define EIM_CS5WCR1_WCSN_SHIFT (0U) +#define EIM_CS5WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WCSN_SHIFT)) & EIM_CS5WCR1_WCSN_MASK) +#define EIM_CS5WCR1_WCSA_MASK (0x38U) +#define EIM_CS5WCR1_WCSA_SHIFT (3U) +#define EIM_CS5WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WCSA_SHIFT)) & EIM_CS5WCR1_WCSA_MASK) +#define EIM_CS5WCR1_WEN_MASK (0x1C0U) +#define EIM_CS5WCR1_WEN_SHIFT (6U) +#define EIM_CS5WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WEN_SHIFT)) & EIM_CS5WCR1_WEN_MASK) +#define EIM_CS5WCR1_WEA_MASK (0xE00U) +#define EIM_CS5WCR1_WEA_SHIFT (9U) +#define EIM_CS5WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WEA_SHIFT)) & EIM_CS5WCR1_WEA_MASK) +#define EIM_CS5WCR1_WBEN_MASK (0x7000U) +#define EIM_CS5WCR1_WBEN_SHIFT (12U) +#define EIM_CS5WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WBEN_SHIFT)) & EIM_CS5WCR1_WBEN_MASK) +#define EIM_CS5WCR1_WBEA_MASK (0x38000U) +#define EIM_CS5WCR1_WBEA_SHIFT (15U) +#define EIM_CS5WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WBEA_SHIFT)) & EIM_CS5WCR1_WBEA_MASK) +#define EIM_CS5WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS5WCR1_WADVN_SHIFT (18U) +#define EIM_CS5WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WADVN_SHIFT)) & EIM_CS5WCR1_WADVN_MASK) +#define EIM_CS5WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS5WCR1_WADVA_SHIFT (21U) +#define EIM_CS5WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WADVA_SHIFT)) & EIM_CS5WCR1_WADVA_MASK) +#define EIM_CS5WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS5WCR1_WWSC_SHIFT (24U) +#define EIM_CS5WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WWSC_SHIFT)) & EIM_CS5WCR1_WWSC_MASK) +#define EIM_CS5WCR1_WBED_MASK (0x40000000U) +#define EIM_CS5WCR1_WBED_SHIFT (30U) +#define EIM_CS5WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WBED_SHIFT)) & EIM_CS5WCR1_WBED_MASK) +#define EIM_CS5WCR1_WAL_MASK (0x80000000U) +#define EIM_CS5WCR1_WAL_SHIFT (31U) +#define EIM_CS5WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WAL_SHIFT)) & EIM_CS5WCR1_WAL_MASK) + +/*! @name CS5WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS5WCR2_WBCDD_MASK (0x1U) +#define EIM_CS5WCR2_WBCDD_SHIFT (0U) +#define EIM_CS5WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR2_WBCDD_SHIFT)) & EIM_CS5WCR2_WBCDD_MASK) + +/*! @name WCR - EIM Configuration Register */ +#define EIM_WCR_BCM_MASK (0x1U) +#define EIM_WCR_BCM_SHIFT (0U) +#define EIM_WCR_BCM(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_BCM_SHIFT)) & EIM_WCR_BCM_MASK) +#define EIM_WCR_GBCD_MASK (0x6U) +#define EIM_WCR_GBCD_SHIFT (1U) +#define EIM_WCR_GBCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_GBCD_SHIFT)) & EIM_WCR_GBCD_MASK) +#define EIM_WCR_CONT_BCLK_SEL_MASK (0x8U) +#define EIM_WCR_CONT_BCLK_SEL_SHIFT (3U) +#define EIM_WCR_CONT_BCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_CONT_BCLK_SEL_SHIFT)) & EIM_WCR_CONT_BCLK_SEL_MASK) +#define EIM_WCR_INTEN_MASK (0x10U) +#define EIM_WCR_INTEN_SHIFT (4U) +#define EIM_WCR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_INTEN_SHIFT)) & EIM_WCR_INTEN_MASK) +#define EIM_WCR_INTPOL_MASK (0x20U) +#define EIM_WCR_INTPOL_SHIFT (5U) +#define EIM_WCR_INTPOL(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_INTPOL_SHIFT)) & EIM_WCR_INTPOL_MASK) +#define EIM_WCR_WDOG_EN_MASK (0x100U) +#define EIM_WCR_WDOG_EN_SHIFT (8U) +#define EIM_WCR_WDOG_EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_WDOG_EN_SHIFT)) & EIM_WCR_WDOG_EN_MASK) +#define EIM_WCR_WDOG_LIMIT_MASK (0x600U) +#define EIM_WCR_WDOG_LIMIT_SHIFT (9U) +#define EIM_WCR_WDOG_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_WDOG_LIMIT_SHIFT)) & EIM_WCR_WDOG_LIMIT_MASK) +#define EIM_WCR_FRUN_ACLK_EN_MASK (0x800U) +#define EIM_WCR_FRUN_ACLK_EN_SHIFT (11U) +#define EIM_WCR_FRUN_ACLK_EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_FRUN_ACLK_EN_SHIFT)) & EIM_WCR_FRUN_ACLK_EN_MASK) + + +/*! + * @} + */ /* end of group EIM_Register_Masks */ + + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM base address */ +#define EIM_BASE (0x21B8000u) +/** Peripheral EIM base pointer */ +#define EIM ((EIM_Type *)EIM_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM } +/** Interrupt vectors for the EIM peripheral type */ +#define EIM_IRQS { WEIM_IRQn } + +/*! + * @} + */ /* end of group EIM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/** ENET - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ + __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ + __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ + uint8_t RESERVED_2[12]; + __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ + __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ + uint8_t RESERVED_5[28]; + __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ + uint8_t RESERVED_6[60]; + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ + uint8_t RESERVED_7[28]; + __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ + __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ + __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ + __IO uint32_t TXIC; /**< Transmit Interrupt Coalescing Register, offset: 0xF0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t RXIC; /**< Receive Interrupt Coalescing Register, offset: 0x100 */ + uint8_t RESERVED_9[20]; + __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ + __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ + __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ + __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ + uint8_t RESERVED_10[28]; + __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ + uint8_t RESERVED_11[56]; + __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */ + __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */ + __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ + uint8_t RESERVED_12[4]; + __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ + __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ + __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ + __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ + __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ + __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ + __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ + __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ + __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ + __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ + uint8_t RESERVED_14[56]; + __I uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ + __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ + __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ + __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ + __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ + __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ + __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ + __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ + __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ + __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ + __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ + __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ + __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ + __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ + __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ + __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ + __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ + __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ + __I uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */ + __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ + __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ + __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ + __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ + __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ + __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ + __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ + __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ + __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ + __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ + __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ + uint8_t RESERVED_15[12]; + __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ + __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ + __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ + __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ + __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ + __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ + __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ + __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ + __I uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ + __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ + __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ + __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ + __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ + __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ + __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ + __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ + __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ + __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ + __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ + __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ + __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ + __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ + __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ + __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ + uint8_t RESERVED_16[284]; + __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_17[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type; + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/*! @name EIR - Interrupt Event Register */ +#define ENET_EIR_TS_TIMER_MASK (0x8000U) +#define ENET_EIR_TS_TIMER_SHIFT (15U) +#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) +#define ENET_EIR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIR_TS_AVAIL_SHIFT (16U) +#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) +#define ENET_EIR_WAKEUP_MASK (0x20000U) +#define ENET_EIR_WAKEUP_SHIFT (17U) +#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) +#define ENET_EIR_PLR_MASK (0x40000U) +#define ENET_EIR_PLR_SHIFT (18U) +#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) +#define ENET_EIR_UN_MASK (0x80000U) +#define ENET_EIR_UN_SHIFT (19U) +#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) +#define ENET_EIR_RL_MASK (0x100000U) +#define ENET_EIR_RL_SHIFT (20U) +#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) +#define ENET_EIR_LC_MASK (0x200000U) +#define ENET_EIR_LC_SHIFT (21U) +#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) +#define ENET_EIR_EBERR_MASK (0x400000U) +#define ENET_EIR_EBERR_SHIFT (22U) +#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) +#define ENET_EIR_MII_MASK (0x800000U) +#define ENET_EIR_MII_SHIFT (23U) +#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) +#define ENET_EIR_RXB_MASK (0x1000000U) +#define ENET_EIR_RXB_SHIFT (24U) +#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) +#define ENET_EIR_RXF_MASK (0x2000000U) +#define ENET_EIR_RXF_SHIFT (25U) +#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) +#define ENET_EIR_TXB_MASK (0x4000000U) +#define ENET_EIR_TXB_SHIFT (26U) +#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) +#define ENET_EIR_TXF_MASK (0x8000000U) +#define ENET_EIR_TXF_SHIFT (27U) +#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) +#define ENET_EIR_GRA_MASK (0x10000000U) +#define ENET_EIR_GRA_SHIFT (28U) +#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) +#define ENET_EIR_BABT_MASK (0x20000000U) +#define ENET_EIR_BABT_SHIFT (29U) +#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) +#define ENET_EIR_BABR_MASK (0x40000000U) +#define ENET_EIR_BABR_SHIFT (30U) +#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) + +/*! @name EIMR - Interrupt Mask Register */ +#define ENET_EIMR_TS_TIMER_MASK (0x8000U) +#define ENET_EIMR_TS_TIMER_SHIFT (15U) +#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) +#define ENET_EIMR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIMR_TS_AVAIL_SHIFT (16U) +#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) +#define ENET_EIMR_WAKEUP_MASK (0x20000U) +#define ENET_EIMR_WAKEUP_SHIFT (17U) +#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) +#define ENET_EIMR_PLR_MASK (0x40000U) +#define ENET_EIMR_PLR_SHIFT (18U) +#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) +#define ENET_EIMR_UN_MASK (0x80000U) +#define ENET_EIMR_UN_SHIFT (19U) +#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) +#define ENET_EIMR_RL_MASK (0x100000U) +#define ENET_EIMR_RL_SHIFT (20U) +#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) +#define ENET_EIMR_LC_MASK (0x200000U) +#define ENET_EIMR_LC_SHIFT (21U) +#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) +#define ENET_EIMR_EBERR_MASK (0x400000U) +#define ENET_EIMR_EBERR_SHIFT (22U) +#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) +#define ENET_EIMR_MII_MASK (0x800000U) +#define ENET_EIMR_MII_SHIFT (23U) +#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) +#define ENET_EIMR_RXB_MASK (0x1000000U) +#define ENET_EIMR_RXB_SHIFT (24U) +#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) +#define ENET_EIMR_RXF_MASK (0x2000000U) +#define ENET_EIMR_RXF_SHIFT (25U) +#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) +#define ENET_EIMR_TXB_MASK (0x4000000U) +#define ENET_EIMR_TXB_SHIFT (26U) +#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) +#define ENET_EIMR_TXF_MASK (0x8000000U) +#define ENET_EIMR_TXF_SHIFT (27U) +#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) +#define ENET_EIMR_GRA_MASK (0x10000000U) +#define ENET_EIMR_GRA_SHIFT (28U) +#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) +#define ENET_EIMR_BABT_MASK (0x20000000U) +#define ENET_EIMR_BABT_SHIFT (29U) +#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) +#define ENET_EIMR_BABR_MASK (0x40000000U) +#define ENET_EIMR_BABR_SHIFT (30U) +#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) + +/*! @name RDAR - Receive Descriptor Active Register */ +#define ENET_RDAR_RDAR_MASK (0x1000000U) +#define ENET_RDAR_RDAR_SHIFT (24U) +#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) + +/*! @name TDAR - Transmit Descriptor Active Register */ +#define ENET_TDAR_TDAR_MASK (0x1000000U) +#define ENET_TDAR_TDAR_SHIFT (24U) +#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) + +/*! @name ECR - Ethernet Control Register */ +#define ENET_ECR_RESET_MASK (0x1U) +#define ENET_ECR_RESET_SHIFT (0U) +#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) +#define ENET_ECR_ETHEREN_MASK (0x2U) +#define ENET_ECR_ETHEREN_SHIFT (1U) +#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) +#define ENET_ECR_MAGICEN_MASK (0x4U) +#define ENET_ECR_MAGICEN_SHIFT (2U) +#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) +#define ENET_ECR_SLEEP_MASK (0x8U) +#define ENET_ECR_SLEEP_SHIFT (3U) +#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) +#define ENET_ECR_EN1588_MASK (0x10U) +#define ENET_ECR_EN1588_SHIFT (4U) +#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) +#define ENET_ECR_DBGEN_MASK (0x40U) +#define ENET_ECR_DBGEN_SHIFT (6U) +#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) +#define ENET_ECR_DBSWP_MASK (0x100U) +#define ENET_ECR_DBSWP_SHIFT (8U) +#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) + +/*! @name MMFR - MII Management Frame Register */ +#define ENET_MMFR_DATA_MASK (0xFFFFU) +#define ENET_MMFR_DATA_SHIFT (0U) +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) +#define ENET_MMFR_TA_MASK (0x30000U) +#define ENET_MMFR_TA_SHIFT (16U) +#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) +#define ENET_MMFR_RA_MASK (0x7C0000U) +#define ENET_MMFR_RA_SHIFT (18U) +#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) +#define ENET_MMFR_PA_MASK (0xF800000U) +#define ENET_MMFR_PA_SHIFT (23U) +#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) +#define ENET_MMFR_OP_MASK (0x30000000U) +#define ENET_MMFR_OP_SHIFT (28U) +#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) +#define ENET_MMFR_ST_MASK (0xC0000000U) +#define ENET_MMFR_ST_SHIFT (30U) +#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) + +/*! @name MSCR - MII Speed Control Register */ +#define ENET_MSCR_MII_SPEED_MASK (0x7EU) +#define ENET_MSCR_MII_SPEED_SHIFT (1U) +#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) +#define ENET_MSCR_DIS_PRE_MASK (0x80U) +#define ENET_MSCR_DIS_PRE_SHIFT (7U) +#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) +#define ENET_MSCR_HOLDTIME_MASK (0x700U) +#define ENET_MSCR_HOLDTIME_SHIFT (8U) +#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) + +/*! @name MIBC - MIB Control Register */ +#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) +#define ENET_MIBC_MIB_CLEAR_SHIFT (29U) +#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) +#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) +#define ENET_MIBC_MIB_IDLE_SHIFT (30U) +#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) +#define ENET_MIBC_MIB_DIS_MASK (0x80000000U) +#define ENET_MIBC_MIB_DIS_SHIFT (31U) +#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) + +/*! @name RCR - Receive Control Register */ +#define ENET_RCR_LOOP_MASK (0x1U) +#define ENET_RCR_LOOP_SHIFT (0U) +#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) +#define ENET_RCR_DRT_MASK (0x2U) +#define ENET_RCR_DRT_SHIFT (1U) +#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) +#define ENET_RCR_MII_MODE_MASK (0x4U) +#define ENET_RCR_MII_MODE_SHIFT (2U) +#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) +#define ENET_RCR_PROM_MASK (0x8U) +#define ENET_RCR_PROM_SHIFT (3U) +#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) +#define ENET_RCR_BC_REJ_MASK (0x10U) +#define ENET_RCR_BC_REJ_SHIFT (4U) +#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) +#define ENET_RCR_FCE_MASK (0x20U) +#define ENET_RCR_FCE_SHIFT (5U) +#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) +#define ENET_RCR_RMII_MODE_MASK (0x100U) +#define ENET_RCR_RMII_MODE_SHIFT (8U) +#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) +#define ENET_RCR_RMII_10T_MASK (0x200U) +#define ENET_RCR_RMII_10T_SHIFT (9U) +#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) +#define ENET_RCR_PADEN_MASK (0x1000U) +#define ENET_RCR_PADEN_SHIFT (12U) +#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) +#define ENET_RCR_PAUFWD_MASK (0x2000U) +#define ENET_RCR_PAUFWD_SHIFT (13U) +#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) +#define ENET_RCR_CRCFWD_MASK (0x4000U) +#define ENET_RCR_CRCFWD_SHIFT (14U) +#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) +#define ENET_RCR_CFEN_MASK (0x8000U) +#define ENET_RCR_CFEN_SHIFT (15U) +#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) +#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) +#define ENET_RCR_MAX_FL_SHIFT (16U) +#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) +#define ENET_RCR_NLC_MASK (0x40000000U) +#define ENET_RCR_NLC_SHIFT (30U) +#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) +#define ENET_RCR_GRS_MASK (0x80000000U) +#define ENET_RCR_GRS_SHIFT (31U) +#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) + +/*! @name TCR - Transmit Control Register */ +#define ENET_TCR_GTS_MASK (0x1U) +#define ENET_TCR_GTS_SHIFT (0U) +#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) +#define ENET_TCR_FDEN_MASK (0x4U) +#define ENET_TCR_FDEN_SHIFT (2U) +#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) +#define ENET_TCR_TFC_PAUSE_MASK (0x8U) +#define ENET_TCR_TFC_PAUSE_SHIFT (3U) +#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) +#define ENET_TCR_RFC_PAUSE_MASK (0x10U) +#define ENET_TCR_RFC_PAUSE_SHIFT (4U) +#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) +#define ENET_TCR_ADDSEL_MASK (0xE0U) +#define ENET_TCR_ADDSEL_SHIFT (5U) +#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) +#define ENET_TCR_ADDINS_MASK (0x100U) +#define ENET_TCR_ADDINS_SHIFT (8U) +#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) +#define ENET_TCR_CRCFWD_MASK (0x200U) +#define ENET_TCR_CRCFWD_SHIFT (9U) +#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) + +/*! @name PALR - Physical Address Lower Register */ +#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) +#define ENET_PALR_PADDR1_SHIFT (0U) +#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) + +/*! @name PAUR - Physical Address Upper Register */ +#define ENET_PAUR_TYPE_MASK (0xFFFFU) +#define ENET_PAUR_TYPE_SHIFT (0U) +#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) +#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) +#define ENET_PAUR_PADDR2_SHIFT (16U) +#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) + +/*! @name OPD - Opcode/Pause Duration Register */ +#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) +#define ENET_OPD_PAUSE_DUR_SHIFT (0U) +#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) +#define ENET_OPD_OPCODE_MASK (0xFFFF0000U) +#define ENET_OPD_OPCODE_SHIFT (16U) +#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) + +/*! @name TXIC - Transmit Interrupt Coalescing Register */ +#define ENET_TXIC_ICTT_MASK (0xFFFFU) +#define ENET_TXIC_ICTT_SHIFT (0U) +#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) +#define ENET_TXIC_ICFT_MASK (0xFF00000U) +#define ENET_TXIC_ICFT_SHIFT (20U) +#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) +#define ENET_TXIC_ICCS_MASK (0x40000000U) +#define ENET_TXIC_ICCS_SHIFT (30U) +#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) +#define ENET_TXIC_ICEN_MASK (0x80000000U) +#define ENET_TXIC_ICEN_SHIFT (31U) +#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) + +/*! @name RXIC - Receive Interrupt Coalescing Register */ +#define ENET_RXIC_ICTT_MASK (0xFFFFU) +#define ENET_RXIC_ICTT_SHIFT (0U) +#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) +#define ENET_RXIC_ICFT_MASK (0xFF00000U) +#define ENET_RXIC_ICFT_SHIFT (20U) +#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) +#define ENET_RXIC_ICCS_MASK (0x40000000U) +#define ENET_RXIC_ICCS_SHIFT (30U) +#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) +#define ENET_RXIC_ICEN_MASK (0x80000000U) +#define ENET_RXIC_ICEN_SHIFT (31U) +#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) + +/*! @name IAUR - Descriptor Individual Upper Address Register */ +#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) +#define ENET_IAUR_IADDR1_SHIFT (0U) +#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) + +/*! @name IALR - Descriptor Individual Lower Address Register */ +#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) +#define ENET_IALR_IADDR2_SHIFT (0U) +#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) + +/*! @name GAUR - Descriptor Group Upper Address Register */ +#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) +#define ENET_GAUR_GADDR1_SHIFT (0U) +#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) + +/*! @name GALR - Descriptor Group Lower Address Register */ +#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) +#define ENET_GALR_GADDR2_SHIFT (0U) +#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) + +/*! @name TFWR - Transmit FIFO Watermark Register */ +#define ENET_TFWR_TFWR_MASK (0x3FU) +#define ENET_TFWR_TFWR_SHIFT (0U) +#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) +#define ENET_TFWR_STRFWD_MASK (0x100U) +#define ENET_TFWR_STRFWD_SHIFT (8U) +#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) + +/*! @name RDSR - Receive Descriptor Ring Start Register */ +#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR_R_DES_START_SHIFT (3U) +#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) + +/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ +#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR_X_DES_START_SHIFT (3U) +#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) + +/*! @name MRBR - Maximum Receive Buffer Size Register */ +#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) + +/*! @name RSFL - Receive FIFO Section Full Threshold */ +#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) +#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) +#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) + +/*! @name RSEM - Receive FIFO Section Empty Threshold */ +#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) +#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) +#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) +#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) +#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) + +/*! @name RAEM - Receive FIFO Almost Empty Threshold */ +#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) + +/*! @name RAFL - Receive FIFO Almost Full Threshold */ +#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) +#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) +#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) + +/*! @name TSEM - Transmit FIFO Section Empty Threshold */ +#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) +#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) + +/*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) + +/*! @name TAFL - Transmit FIFO Almost Full Threshold */ +#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) +#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) +#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) + +/*! @name TIPG - Transmit Inter-Packet Gap */ +#define ENET_TIPG_IPG_MASK (0x1FU) +#define ENET_TIPG_IPG_SHIFT (0U) +#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) + +/*! @name FTRL - Frame Truncation Length */ +#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) +#define ENET_FTRL_TRUNC_FL_SHIFT (0U) +#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) + +/*! @name TACC - Transmit Accelerator Function Configuration */ +#define ENET_TACC_SHIFT16_MASK (0x1U) +#define ENET_TACC_SHIFT16_SHIFT (0U) +#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) +#define ENET_TACC_IPCHK_MASK (0x8U) +#define ENET_TACC_IPCHK_SHIFT (3U) +#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) +#define ENET_TACC_PROCHK_MASK (0x10U) +#define ENET_TACC_PROCHK_SHIFT (4U) +#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) + +/*! @name RACC - Receive Accelerator Function Configuration */ +#define ENET_RACC_PADREM_MASK (0x1U) +#define ENET_RACC_PADREM_SHIFT (0U) +#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) +#define ENET_RACC_IPDIS_MASK (0x2U) +#define ENET_RACC_IPDIS_SHIFT (1U) +#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) +#define ENET_RACC_PRODIS_MASK (0x4U) +#define ENET_RACC_PRODIS_SHIFT (2U) +#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) +#define ENET_RACC_LINEDIS_MASK (0x40U) +#define ENET_RACC_LINEDIS_SHIFT (6U) +#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) +#define ENET_RACC_SHIFT16_MASK (0x80U) +#define ENET_RACC_SHIFT16_SHIFT (7U) +#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) + +/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) + +/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) + +/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) + +/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) + +/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) + +/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) + +/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) + +/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) + +/*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) + +/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) + +/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) + +/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) + +/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) + +/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) + +/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) + +/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) + +/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) + +/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) + +/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) + +/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) + +/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) + +/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) + +/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) + +/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) + +/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) + +/*! @name IEEE_T_SQE - Reserved Statistic Register */ +#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) +#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) + +/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) + +/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) + +/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) + +/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) + +/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) + +/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) + +/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) + +/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) + +/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) + +/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) + +/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P64_COUNT_SHIFT (0U) +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) + +/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) + +/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) + +/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) + +/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) + +/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) + +/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) + +/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) +#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) + +/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) + +/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) + +/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) + +/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) + +/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) + +/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) + +/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) + +/*! @name ATCR - Adjustable Timer Control Register */ +#define ENET_ATCR_EN_MASK (0x1U) +#define ENET_ATCR_EN_SHIFT (0U) +#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) +#define ENET_ATCR_OFFEN_MASK (0x4U) +#define ENET_ATCR_OFFEN_SHIFT (2U) +#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) +#define ENET_ATCR_OFFRST_MASK (0x8U) +#define ENET_ATCR_OFFRST_SHIFT (3U) +#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) +#define ENET_ATCR_PEREN_MASK (0x10U) +#define ENET_ATCR_PEREN_SHIFT (4U) +#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) +#define ENET_ATCR_PINPER_MASK (0x80U) +#define ENET_ATCR_PINPER_SHIFT (7U) +#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) +#define ENET_ATCR_RESTART_MASK (0x200U) +#define ENET_ATCR_RESTART_SHIFT (9U) +#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) +#define ENET_ATCR_CAPTURE_MASK (0x800U) +#define ENET_ATCR_CAPTURE_SHIFT (11U) +#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) +#define ENET_ATCR_SLAVE_MASK (0x2000U) +#define ENET_ATCR_SLAVE_SHIFT (13U) +#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) + +/*! @name ATVR - Timer Value Register */ +#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) +#define ENET_ATVR_ATIME_SHIFT (0U) +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) + +/*! @name ATOFF - Timer Offset Register */ +#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) +#define ENET_ATOFF_OFFSET_SHIFT (0U) +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) + +/*! @name ATPER - Timer Period Register */ +#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) +#define ENET_ATPER_PERIOD_SHIFT (0U) +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) + +/*! @name ATCOR - Timer Correction Register */ +#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) +#define ENET_ATCOR_COR_SHIFT (0U) +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) + +/*! @name ATINC - Time-Stamping Clock Period Register */ +#define ENET_ATINC_INC_MASK (0x7FU) +#define ENET_ATINC_INC_SHIFT (0U) +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) +#define ENET_ATINC_INC_CORR_MASK (0x7F00U) +#define ENET_ATINC_INC_CORR_SHIFT (8U) +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) + +/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) +#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) + +/*! @name TGSR - Timer Global Status Register */ +#define ENET_TGSR_TF0_MASK (0x1U) +#define ENET_TGSR_TF0_SHIFT (0U) +#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) +#define ENET_TGSR_TF1_MASK (0x2U) +#define ENET_TGSR_TF1_SHIFT (1U) +#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) +#define ENET_TGSR_TF2_MASK (0x4U) +#define ENET_TGSR_TF2_SHIFT (2U) +#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) +#define ENET_TGSR_TF3_MASK (0x8U) +#define ENET_TGSR_TF3_SHIFT (3U) +#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) + +/*! @name TCSR - Timer Control Status Register */ +#define ENET_TCSR_TDRE_MASK (0x1U) +#define ENET_TCSR_TDRE_SHIFT (0U) +#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) +#define ENET_TCSR_TMODE_MASK (0x3CU) +#define ENET_TCSR_TMODE_SHIFT (2U) +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) +#define ENET_TCSR_TIE_MASK (0x40U) +#define ENET_TCSR_TIE_SHIFT (6U) +#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) +#define ENET_TCSR_TF_MASK (0x80U) +#define ENET_TCSR_TF_SHIFT (7U) +#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) +#define ENET_TCSR_TPWC_MASK (0xF800U) +#define ENET_TCSR_TPWC_SHIFT (11U) +#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK) + +/* The count of ENET_TCSR */ +#define ENET_TCSR_COUNT (4U) + +/*! @name TCCR - Timer Compare Capture Register */ +#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) +#define ENET_TCCR_TCC_SHIFT (0U) +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) + +/* The count of ENET_TCCR */ +#define ENET_TCCR_COUNT (4U) + + +/*! + * @} + */ /* end of group ENET_Register_Masks */ + + +/* ENET - Peripheral instance base addresses */ +/** Peripheral ENET1 base address */ +#define ENET1_BASE (0x2188000u) +/** Peripheral ENET1 base pointer */ +#define ENET1 ((ENET_Type *)ENET1_BASE) +/** Peripheral ENET2 base address */ +#define ENET2_BASE (0x20B4000u) +/** Peripheral ENET2 base pointer */ +#define ENET2 ((ENET_Type *)ENET2_BASE) +/** Array initializer of ENET peripheral base addresses */ +#define ENET_BASE_ADDRS { 0u, ENET1_BASE, ENET2_BASE } +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1, ENET2 } +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EPIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPIT_Peripheral_Access_Layer EPIT Peripheral Access Layer + * @{ + */ + +/** EPIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control register, offset: 0x0 */ + __IO uint32_t SR; /**< Status register, offset: 0x4 */ + __IO uint32_t LR; /**< Load register, offset: 0x8 */ + __IO uint32_t CMPR; /**< Compare register, offset: 0xC */ + __I uint32_t CNR; /**< Counter register, offset: 0x10 */ +} EPIT_Type; + +/* ---------------------------------------------------------------------------- + -- EPIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPIT_Register_Masks EPIT Register Masks + * @{ + */ + +/*! @name CR - Control register */ +#define EPIT_CR_EN_MASK (0x1U) +#define EPIT_CR_EN_SHIFT (0U) +#define EPIT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_EN_SHIFT)) & EPIT_CR_EN_MASK) +#define EPIT_CR_ENMOD_MASK (0x2U) +#define EPIT_CR_ENMOD_SHIFT (1U) +#define EPIT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_ENMOD_SHIFT)) & EPIT_CR_ENMOD_MASK) +#define EPIT_CR_OCIEN_MASK (0x4U) +#define EPIT_CR_OCIEN_SHIFT (2U) +#define EPIT_CR_OCIEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_OCIEN_SHIFT)) & EPIT_CR_OCIEN_MASK) +#define EPIT_CR_RLD_MASK (0x8U) +#define EPIT_CR_RLD_SHIFT (3U) +#define EPIT_CR_RLD(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_RLD_SHIFT)) & EPIT_CR_RLD_MASK) +#define EPIT_CR_PRESCALAR_MASK (0xFFF0U) +#define EPIT_CR_PRESCALAR_SHIFT (4U) +#define EPIT_CR_PRESCALAR(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_PRESCALAR_SHIFT)) & EPIT_CR_PRESCALAR_MASK) +#define EPIT_CR_SWR_MASK (0x10000U) +#define EPIT_CR_SWR_SHIFT (16U) +#define EPIT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_SWR_SHIFT)) & EPIT_CR_SWR_MASK) +#define EPIT_CR_IOVW_MASK (0x20000U) +#define EPIT_CR_IOVW_SHIFT (17U) +#define EPIT_CR_IOVW(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_IOVW_SHIFT)) & EPIT_CR_IOVW_MASK) +#define EPIT_CR_DBGEN_MASK (0x40000U) +#define EPIT_CR_DBGEN_SHIFT (18U) +#define EPIT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_DBGEN_SHIFT)) & EPIT_CR_DBGEN_MASK) +#define EPIT_CR_WAITEN_MASK (0x80000U) +#define EPIT_CR_WAITEN_SHIFT (19U) +#define EPIT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_WAITEN_SHIFT)) & EPIT_CR_WAITEN_MASK) +#define EPIT_CR_STOPEN_MASK (0x200000U) +#define EPIT_CR_STOPEN_SHIFT (21U) +#define EPIT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_STOPEN_SHIFT)) & EPIT_CR_STOPEN_MASK) +#define EPIT_CR_OM_MASK (0xC00000U) +#define EPIT_CR_OM_SHIFT (22U) +#define EPIT_CR_OM(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_OM_SHIFT)) & EPIT_CR_OM_MASK) +#define EPIT_CR_CLKSRC_MASK (0x3000000U) +#define EPIT_CR_CLKSRC_SHIFT (24U) +#define EPIT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_CLKSRC_SHIFT)) & EPIT_CR_CLKSRC_MASK) + +/*! @name SR - Status register */ +#define EPIT_SR_OCIF_MASK (0x1U) +#define EPIT_SR_OCIF_SHIFT (0U) +#define EPIT_SR_OCIF(x) (((uint32_t)(((uint32_t)(x)) << EPIT_SR_OCIF_SHIFT)) & EPIT_SR_OCIF_MASK) + +/*! @name LR - Load register */ +#define EPIT_LR_LOAD_MASK (0xFFFFFFFFU) +#define EPIT_LR_LOAD_SHIFT (0U) +#define EPIT_LR_LOAD(x) (((uint32_t)(((uint32_t)(x)) << EPIT_LR_LOAD_SHIFT)) & EPIT_LR_LOAD_MASK) + +/*! @name CMPR - Compare register */ +#define EPIT_CMPR_COMPARE_MASK (0xFFFFFFFFU) +#define EPIT_CMPR_COMPARE_SHIFT (0U) +#define EPIT_CMPR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CMPR_COMPARE_SHIFT)) & EPIT_CMPR_COMPARE_MASK) + +/*! @name CNR - Counter register */ +#define EPIT_CNR_COUNT_MASK (0xFFFFFFFFU) +#define EPIT_CNR_COUNT_SHIFT (0U) +#define EPIT_CNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CNR_COUNT_SHIFT)) & EPIT_CNR_COUNT_MASK) + + +/*! + * @} + */ /* end of group EPIT_Register_Masks */ + + +/* EPIT - Peripheral instance base addresses */ +/** Peripheral EPIT1 base address */ +#define EPIT1_BASE (0x20D0000u) +/** Peripheral EPIT1 base pointer */ +#define EPIT1 ((EPIT_Type *)EPIT1_BASE) +/** Peripheral EPIT2 base address */ +#define EPIT2_BASE (0x20D4000u) +/** Peripheral EPIT2 base pointer */ +#define EPIT2 ((EPIT_Type *)EPIT2_BASE) +/** Array initializer of EPIT peripheral base addresses */ +#define EPIT_BASE_ADDRS { 0u, EPIT1_BASE, EPIT2_BASE } +/** Array initializer of EPIT peripheral base pointers */ +#define EPIT_BASE_PTRS { (EPIT_Type *)0u, EPIT1, EPIT2 } +/** Interrupt vectors for the EPIT peripheral type */ +#define EPIT_IRQS { NotAvail_IRQn, EPIT1_IRQn, EPIT2_IRQn } + +/*! + * @} + */ /* end of group EPIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ESAI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ESAI_Peripheral_Access_Layer ESAI Peripheral Access Layer + * @{ + */ + +/** ESAI - Register Layout Typedef */ +typedef struct { + __O uint32_t ETDR; /**< ESAI Transmit Data Register, offset: 0x0 */ + __I uint32_t ERDR; /**< ESAI Receive Data Register, offset: 0x4 */ + __IO uint32_t ECR; /**< ESAI Control Register, offset: 0x8 */ + __I uint32_t ESR; /**< ESAI Status Register, offset: 0xC */ + __IO uint32_t TFCR; /**< Transmit FIFO Configuration Register, offset: 0x10 */ + __I uint32_t TFSR; /**< Transmit FIFO Status Register, offset: 0x14 */ + __IO uint32_t RFCR; /**< Receive FIFO Configuration Register, offset: 0x18 */ + __I uint32_t RFSR; /**< Receive FIFO Status Register, offset: 0x1C */ + uint8_t RESERVED_0[96]; + __IO uint32_t TX[6]; /**< Transmit Data Register n, array offset: 0x80, array step: 0x4 */ + __IO uint32_t TSR; /**< ESAI Transmit Slot Register, offset: 0x98 */ + uint8_t RESERVED_1[4]; + __I uint32_t RX[4]; /**< Receive Data Register n, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_2[28]; + __I uint32_t SAISR; /**< Serial Audio Interface Status Register, offset: 0xCC */ + __IO uint32_t SAICR; /**< Serial Audio Interface Control Register, offset: 0xD0 */ + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xD4 */ + __IO uint32_t TCCR; /**< Transmit Clock Control Register, offset: 0xD8 */ + __IO uint32_t RCR; /**< Receive Control Register, offset: 0xDC */ + __IO uint32_t RCCR; /**< Receive Clock Control Register, offset: 0xE0 */ + __IO uint32_t TSMA; /**< Transmit Slot Mask Register A, offset: 0xE4 */ + __IO uint32_t TSMB; /**< Transmit Slot Mask Register B, offset: 0xE8 */ + __IO uint32_t RSMA; /**< Receive Slot Mask Register A, offset: 0xEC */ + __IO uint32_t RSMB; /**< Receive Slot Mask Register B, offset: 0xF0 */ + uint8_t RESERVED_3[4]; + __IO uint32_t PRRC; /**< Port C Direction Register, offset: 0xF8 */ + __IO uint32_t PCRC; /**< Port C Control Register, offset: 0xFC */ +} ESAI_Type; + +/* ---------------------------------------------------------------------------- + -- ESAI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ESAI_Register_Masks ESAI Register Masks + * @{ + */ + +/*! @name ETDR - ESAI Transmit Data Register */ +#define ESAI_ETDR_ETDR_MASK (0xFFFFFFFFU) +#define ESAI_ETDR_ETDR_SHIFT (0U) +#define ESAI_ETDR_ETDR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ETDR_ETDR_SHIFT)) & ESAI_ETDR_ETDR_MASK) + +/*! @name ERDR - ESAI Receive Data Register */ +#define ESAI_ERDR_ERDR_MASK (0xFFFFFFFFU) +#define ESAI_ERDR_ERDR_SHIFT (0U) +#define ESAI_ERDR_ERDR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ERDR_ERDR_SHIFT)) & ESAI_ERDR_ERDR_MASK) + +/*! @name ECR - ESAI Control Register */ +#define ESAI_ECR_ESAIEN_MASK (0x1U) +#define ESAI_ECR_ESAIEN_SHIFT (0U) +#define ESAI_ECR_ESAIEN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ESAIEN_SHIFT)) & ESAI_ECR_ESAIEN_MASK) +#define ESAI_ECR_ERST_MASK (0x2U) +#define ESAI_ECR_ERST_SHIFT (1U) +#define ESAI_ECR_ERST(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERST_SHIFT)) & ESAI_ECR_ERST_MASK) +#define ESAI_ECR_ERO_MASK (0x10000U) +#define ESAI_ECR_ERO_SHIFT (16U) +#define ESAI_ECR_ERO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERO_SHIFT)) & ESAI_ECR_ERO_MASK) +#define ESAI_ECR_ERI_MASK (0x20000U) +#define ESAI_ECR_ERI_SHIFT (17U) +#define ESAI_ECR_ERI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERI_SHIFT)) & ESAI_ECR_ERI_MASK) +#define ESAI_ECR_ETO_MASK (0x40000U) +#define ESAI_ECR_ETO_SHIFT (18U) +#define ESAI_ECR_ETO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETO_SHIFT)) & ESAI_ECR_ETO_MASK) +#define ESAI_ECR_ETI_MASK (0x80000U) +#define ESAI_ECR_ETI_SHIFT (19U) +#define ESAI_ECR_ETI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETI_SHIFT)) & ESAI_ECR_ETI_MASK) + +/*! @name ESR - ESAI Status Register */ +#define ESAI_ESR_RD_MASK (0x1U) +#define ESAI_ESR_RD_SHIFT (0U) +#define ESAI_ESR_RD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RD_SHIFT)) & ESAI_ESR_RD_MASK) +#define ESAI_ESR_RED_MASK (0x2U) +#define ESAI_ESR_RED_SHIFT (1U) +#define ESAI_ESR_RED(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RED_SHIFT)) & ESAI_ESR_RED_MASK) +#define ESAI_ESR_RDE_MASK (0x4U) +#define ESAI_ESR_RDE_SHIFT (2U) +#define ESAI_ESR_RDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RDE_SHIFT)) & ESAI_ESR_RDE_MASK) +#define ESAI_ESR_RLS_MASK (0x8U) +#define ESAI_ESR_RLS_SHIFT (3U) +#define ESAI_ESR_RLS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RLS_SHIFT)) & ESAI_ESR_RLS_MASK) +#define ESAI_ESR_TD_MASK (0x10U) +#define ESAI_ESR_TD_SHIFT (4U) +#define ESAI_ESR_TD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TD_SHIFT)) & ESAI_ESR_TD_MASK) +#define ESAI_ESR_TED_MASK (0x20U) +#define ESAI_ESR_TED_SHIFT (5U) +#define ESAI_ESR_TED(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TED_SHIFT)) & ESAI_ESR_TED_MASK) +#define ESAI_ESR_TDE_MASK (0x40U) +#define ESAI_ESR_TDE_SHIFT (6U) +#define ESAI_ESR_TDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TDE_SHIFT)) & ESAI_ESR_TDE_MASK) +#define ESAI_ESR_TLS_MASK (0x80U) +#define ESAI_ESR_TLS_SHIFT (7U) +#define ESAI_ESR_TLS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TLS_SHIFT)) & ESAI_ESR_TLS_MASK) +#define ESAI_ESR_TFE_MASK (0x100U) +#define ESAI_ESR_TFE_SHIFT (8U) +#define ESAI_ESR_TFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TFE_SHIFT)) & ESAI_ESR_TFE_MASK) +#define ESAI_ESR_RFF_MASK (0x200U) +#define ESAI_ESR_RFF_SHIFT (9U) +#define ESAI_ESR_RFF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RFF_SHIFT)) & ESAI_ESR_RFF_MASK) +#define ESAI_ESR_TINIT_MASK (0x400U) +#define ESAI_ESR_TINIT_SHIFT (10U) +#define ESAI_ESR_TINIT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TINIT_SHIFT)) & ESAI_ESR_TINIT_MASK) + +/*! @name TFCR - Transmit FIFO Configuration Register */ +#define ESAI_TFCR_TFE_MASK (0x1U) +#define ESAI_TFCR_TFE_SHIFT (0U) +#define ESAI_TFCR_TFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFE_SHIFT)) & ESAI_TFCR_TFE_MASK) +#define ESAI_TFCR_TFR_MASK (0x2U) +#define ESAI_TFCR_TFR_SHIFT (1U) +#define ESAI_TFCR_TFR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFR_SHIFT)) & ESAI_TFCR_TFR_MASK) +#define ESAI_TFCR_TE0_MASK (0x4U) +#define ESAI_TFCR_TE0_SHIFT (2U) +#define ESAI_TFCR_TE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE0_SHIFT)) & ESAI_TFCR_TE0_MASK) +#define ESAI_TFCR_TE1_MASK (0x8U) +#define ESAI_TFCR_TE1_SHIFT (3U) +#define ESAI_TFCR_TE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE1_SHIFT)) & ESAI_TFCR_TE1_MASK) +#define ESAI_TFCR_TE2_MASK (0x10U) +#define ESAI_TFCR_TE2_SHIFT (4U) +#define ESAI_TFCR_TE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE2_SHIFT)) & ESAI_TFCR_TE2_MASK) +#define ESAI_TFCR_TE3_MASK (0x20U) +#define ESAI_TFCR_TE3_SHIFT (5U) +#define ESAI_TFCR_TE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE3_SHIFT)) & ESAI_TFCR_TE3_MASK) +#define ESAI_TFCR_TE4_MASK (0x40U) +#define ESAI_TFCR_TE4_SHIFT (6U) +#define ESAI_TFCR_TE4(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE4_SHIFT)) & ESAI_TFCR_TE4_MASK) +#define ESAI_TFCR_TE5_MASK (0x80U) +#define ESAI_TFCR_TE5_SHIFT (7U) +#define ESAI_TFCR_TE5(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE5_SHIFT)) & ESAI_TFCR_TE5_MASK) +#define ESAI_TFCR_TFWM_MASK (0xFF00U) +#define ESAI_TFCR_TFWM_SHIFT (8U) +#define ESAI_TFCR_TFWM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFWM_SHIFT)) & ESAI_TFCR_TFWM_MASK) +#define ESAI_TFCR_TWA_MASK (0x70000U) +#define ESAI_TFCR_TWA_SHIFT (16U) +#define ESAI_TFCR_TWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TWA_SHIFT)) & ESAI_TFCR_TWA_MASK) +#define ESAI_TFCR_TIEN_MASK (0x80000U) +#define ESAI_TFCR_TIEN_SHIFT (19U) +#define ESAI_TFCR_TIEN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TIEN_SHIFT)) & ESAI_TFCR_TIEN_MASK) +#define ESAI_TFCR_TAENB_MASK (0x100000U) +#define ESAI_TFCR_TAENB_SHIFT (20U) +#define ESAI_TFCR_TAENB(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TAENB_SHIFT)) & ESAI_TFCR_TAENB_MASK) +#define ESAI_TFCR_TFIN_MASK (0x200000U) +#define ESAI_TFCR_TFIN_SHIFT (21U) +#define ESAI_TFCR_TFIN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFIN_SHIFT)) & ESAI_TFCR_TFIN_MASK) + +/*! @name TFSR - Transmit FIFO Status Register */ +#define ESAI_TFSR_TFCNT_MASK (0xFFU) +#define ESAI_TFSR_TFCNT_SHIFT (0U) +#define ESAI_TFSR_TFCNT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_TFCNT_SHIFT)) & ESAI_TFSR_TFCNT_MASK) +#define ESAI_TFSR_NTFI_MASK (0x700U) +#define ESAI_TFSR_NTFI_SHIFT (8U) +#define ESAI_TFSR_NTFI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFI_SHIFT)) & ESAI_TFSR_NTFI_MASK) +#define ESAI_TFSR_NTFO_MASK (0x7000U) +#define ESAI_TFSR_NTFO_SHIFT (12U) +#define ESAI_TFSR_NTFO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFO_SHIFT)) & ESAI_TFSR_NTFO_MASK) + +/*! @name RFCR - Receive FIFO Configuration Register */ +#define ESAI_RFCR_RFE_MASK (0x1U) +#define ESAI_RFCR_RFE_SHIFT (0U) +#define ESAI_RFCR_RFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFE_SHIFT)) & ESAI_RFCR_RFE_MASK) +#define ESAI_RFCR_RFR_MASK (0x2U) +#define ESAI_RFCR_RFR_SHIFT (1U) +#define ESAI_RFCR_RFR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFR_SHIFT)) & ESAI_RFCR_RFR_MASK) +#define ESAI_RFCR_RE0_MASK (0x4U) +#define ESAI_RFCR_RE0_SHIFT (2U) +#define ESAI_RFCR_RE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE0_SHIFT)) & ESAI_RFCR_RE0_MASK) +#define ESAI_RFCR_RE1_MASK (0x8U) +#define ESAI_RFCR_RE1_SHIFT (3U) +#define ESAI_RFCR_RE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE1_SHIFT)) & ESAI_RFCR_RE1_MASK) +#define ESAI_RFCR_RE2_MASK (0x10U) +#define ESAI_RFCR_RE2_SHIFT (4U) +#define ESAI_RFCR_RE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE2_SHIFT)) & ESAI_RFCR_RE2_MASK) +#define ESAI_RFCR_RE3_MASK (0x20U) +#define ESAI_RFCR_RE3_SHIFT (5U) +#define ESAI_RFCR_RE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE3_SHIFT)) & ESAI_RFCR_RE3_MASK) +#define ESAI_RFCR_RFWM_MASK (0xFF00U) +#define ESAI_RFCR_RFWM_SHIFT (8U) +#define ESAI_RFCR_RFWM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFWM_SHIFT)) & ESAI_RFCR_RFWM_MASK) +#define ESAI_RFCR_RWA_MASK (0x70000U) +#define ESAI_RFCR_RWA_SHIFT (16U) +#define ESAI_RFCR_RWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RWA_SHIFT)) & ESAI_RFCR_RWA_MASK) +#define ESAI_RFCR_REXT_MASK (0x80000U) +#define ESAI_RFCR_REXT_SHIFT (19U) +#define ESAI_RFCR_REXT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_REXT_SHIFT)) & ESAI_RFCR_REXT_MASK) +#define ESAI_RFCR_RAENB_MASK (0x100000U) +#define ESAI_RFCR_RAENB_SHIFT (20U) +#define ESAI_RFCR_RAENB(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RAENB_SHIFT)) & ESAI_RFCR_RAENB_MASK) +#define ESAI_RFCR_RFIN_MASK (0x200000U) +#define ESAI_RFCR_RFIN_SHIFT (21U) +#define ESAI_RFCR_RFIN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFIN_SHIFT)) & ESAI_RFCR_RFIN_MASK) + +/*! @name RFSR - Receive FIFO Status Register */ +#define ESAI_RFSR_RFCNT_MASK (0xFFU) +#define ESAI_RFSR_RFCNT_SHIFT (0U) +#define ESAI_RFSR_RFCNT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_RFCNT_SHIFT)) & ESAI_RFSR_RFCNT_MASK) +#define ESAI_RFSR_NRFO_MASK (0x300U) +#define ESAI_RFSR_NRFO_SHIFT (8U) +#define ESAI_RFSR_NRFO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFO_SHIFT)) & ESAI_RFSR_NRFO_MASK) +#define ESAI_RFSR_NRFI_MASK (0x3000U) +#define ESAI_RFSR_NRFI_SHIFT (12U) +#define ESAI_RFSR_NRFI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFI_SHIFT)) & ESAI_RFSR_NRFI_MASK) + +/*! @name TX - Transmit Data Register n */ +#define ESAI_TX_TXn_MASK (0xFFFFFFU) +#define ESAI_TX_TXn_SHIFT (0U) +#define ESAI_TX_TXn(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TX_TXn_SHIFT)) & ESAI_TX_TXn_MASK) + +/* The count of ESAI_TX */ +#define ESAI_TX_COUNT (6U) + +/*! @name TSR - ESAI Transmit Slot Register */ +#define ESAI_TSR_TSR_MASK (0xFFFFFFU) +#define ESAI_TSR_TSR_SHIFT (0U) +#define ESAI_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSR_TSR_SHIFT)) & ESAI_TSR_TSR_MASK) + +/*! @name RX - Receive Data Register n */ +#define ESAI_RX_RXn_MASK (0xFFFFFFU) +#define ESAI_RX_RXn_SHIFT (0U) +#define ESAI_RX_RXn(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RX_RXn_SHIFT)) & ESAI_RX_RXn_MASK) + +/* The count of ESAI_RX */ +#define ESAI_RX_COUNT (4U) + +/*! @name SAISR - Serial Audio Interface Status Register */ +#define ESAI_SAISR_IF0_MASK (0x1U) +#define ESAI_SAISR_IF0_SHIFT (0U) +#define ESAI_SAISR_IF0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF0_SHIFT)) & ESAI_SAISR_IF0_MASK) +#define ESAI_SAISR_IF1_MASK (0x2U) +#define ESAI_SAISR_IF1_SHIFT (1U) +#define ESAI_SAISR_IF1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF1_SHIFT)) & ESAI_SAISR_IF1_MASK) +#define ESAI_SAISR_IF2_MASK (0x4U) +#define ESAI_SAISR_IF2_SHIFT (2U) +#define ESAI_SAISR_IF2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF2_SHIFT)) & ESAI_SAISR_IF2_MASK) +#define ESAI_SAISR_RFS_MASK (0x40U) +#define ESAI_SAISR_RFS_SHIFT (6U) +#define ESAI_SAISR_RFS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RFS_SHIFT)) & ESAI_SAISR_RFS_MASK) +#define ESAI_SAISR_ROE_MASK (0x80U) +#define ESAI_SAISR_ROE_SHIFT (7U) +#define ESAI_SAISR_ROE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_ROE_SHIFT)) & ESAI_SAISR_ROE_MASK) +#define ESAI_SAISR_RDF_MASK (0x100U) +#define ESAI_SAISR_RDF_SHIFT (8U) +#define ESAI_SAISR_RDF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RDF_SHIFT)) & ESAI_SAISR_RDF_MASK) +#define ESAI_SAISR_REDF_MASK (0x200U) +#define ESAI_SAISR_REDF_SHIFT (9U) +#define ESAI_SAISR_REDF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_REDF_SHIFT)) & ESAI_SAISR_REDF_MASK) +#define ESAI_SAISR_RODF_MASK (0x400U) +#define ESAI_SAISR_RODF_SHIFT (10U) +#define ESAI_SAISR_RODF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RODF_SHIFT)) & ESAI_SAISR_RODF_MASK) +#define ESAI_SAISR_TFS_MASK (0x2000U) +#define ESAI_SAISR_TFS_SHIFT (13U) +#define ESAI_SAISR_TFS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TFS_SHIFT)) & ESAI_SAISR_TFS_MASK) +#define ESAI_SAISR_TUE_MASK (0x4000U) +#define ESAI_SAISR_TUE_SHIFT (14U) +#define ESAI_SAISR_TUE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TUE_SHIFT)) & ESAI_SAISR_TUE_MASK) +#define ESAI_SAISR_TDE_MASK (0x8000U) +#define ESAI_SAISR_TDE_SHIFT (15U) +#define ESAI_SAISR_TDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TDE_SHIFT)) & ESAI_SAISR_TDE_MASK) +#define ESAI_SAISR_TEDE_MASK (0x10000U) +#define ESAI_SAISR_TEDE_SHIFT (16U) +#define ESAI_SAISR_TEDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TEDE_SHIFT)) & ESAI_SAISR_TEDE_MASK) +#define ESAI_SAISR_TODFE_MASK (0x20000U) +#define ESAI_SAISR_TODFE_SHIFT (17U) +#define ESAI_SAISR_TODFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TODFE_SHIFT)) & ESAI_SAISR_TODFE_MASK) + +/*! @name SAICR - Serial Audio Interface Control Register */ +#define ESAI_SAICR_OF0_MASK (0x1U) +#define ESAI_SAICR_OF0_SHIFT (0U) +#define ESAI_SAICR_OF0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF0_SHIFT)) & ESAI_SAICR_OF0_MASK) +#define ESAI_SAICR_OF1_MASK (0x2U) +#define ESAI_SAICR_OF1_SHIFT (1U) +#define ESAI_SAICR_OF1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF1_SHIFT)) & ESAI_SAICR_OF1_MASK) +#define ESAI_SAICR_OF2_MASK (0x4U) +#define ESAI_SAICR_OF2_SHIFT (2U) +#define ESAI_SAICR_OF2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF2_SHIFT)) & ESAI_SAICR_OF2_MASK) +#define ESAI_SAICR_SYN_MASK (0x40U) +#define ESAI_SAICR_SYN_SHIFT (6U) +#define ESAI_SAICR_SYN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_SYN_SHIFT)) & ESAI_SAICR_SYN_MASK) +#define ESAI_SAICR_TEBE_MASK (0x80U) +#define ESAI_SAICR_TEBE_SHIFT (7U) +#define ESAI_SAICR_TEBE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_TEBE_SHIFT)) & ESAI_SAICR_TEBE_MASK) +#define ESAI_SAICR_ALC_MASK (0x100U) +#define ESAI_SAICR_ALC_SHIFT (8U) +#define ESAI_SAICR_ALC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_ALC_SHIFT)) & ESAI_SAICR_ALC_MASK) + +/*! @name TCR - Transmit Control Register */ +#define ESAI_TCR_TE0_MASK (0x1U) +#define ESAI_TCR_TE0_SHIFT (0U) +#define ESAI_TCR_TE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE0_SHIFT)) & ESAI_TCR_TE0_MASK) +#define ESAI_TCR_TE1_MASK (0x2U) +#define ESAI_TCR_TE1_SHIFT (1U) +#define ESAI_TCR_TE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE1_SHIFT)) & ESAI_TCR_TE1_MASK) +#define ESAI_TCR_TE2_MASK (0x4U) +#define ESAI_TCR_TE2_SHIFT (2U) +#define ESAI_TCR_TE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE2_SHIFT)) & ESAI_TCR_TE2_MASK) +#define ESAI_TCR_TE3_MASK (0x8U) +#define ESAI_TCR_TE3_SHIFT (3U) +#define ESAI_TCR_TE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE3_SHIFT)) & ESAI_TCR_TE3_MASK) +#define ESAI_TCR_TE4_MASK (0x10U) +#define ESAI_TCR_TE4_SHIFT (4U) +#define ESAI_TCR_TE4(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE4_SHIFT)) & ESAI_TCR_TE4_MASK) +#define ESAI_TCR_TE5_MASK (0x20U) +#define ESAI_TCR_TE5_SHIFT (5U) +#define ESAI_TCR_TE5(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE5_SHIFT)) & ESAI_TCR_TE5_MASK) +#define ESAI_TCR_TSHFD_MASK (0x40U) +#define ESAI_TCR_TSHFD_SHIFT (6U) +#define ESAI_TCR_TSHFD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSHFD_SHIFT)) & ESAI_TCR_TSHFD_MASK) +#define ESAI_TCR_TWA_MASK (0x80U) +#define ESAI_TCR_TWA_SHIFT (7U) +#define ESAI_TCR_TWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TWA_SHIFT)) & ESAI_TCR_TWA_MASK) +#define ESAI_TCR_TMOD_MASK (0x300U) +#define ESAI_TCR_TMOD_SHIFT (8U) +#define ESAI_TCR_TMOD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TMOD_SHIFT)) & ESAI_TCR_TMOD_MASK) +#define ESAI_TCR_TSWS_MASK (0x7C00U) +#define ESAI_TCR_TSWS_SHIFT (10U) +#define ESAI_TCR_TSWS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSWS_SHIFT)) & ESAI_TCR_TSWS_MASK) +#define ESAI_TCR_TFSL_MASK (0x8000U) +#define ESAI_TCR_TFSL_SHIFT (15U) +#define ESAI_TCR_TFSL(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSL_SHIFT)) & ESAI_TCR_TFSL_MASK) +#define ESAI_TCR_TFSR_MASK (0x10000U) +#define ESAI_TCR_TFSR_SHIFT (16U) +#define ESAI_TCR_TFSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSR_SHIFT)) & ESAI_TCR_TFSR_MASK) +#define ESAI_TCR_PADC_MASK (0x20000U) +#define ESAI_TCR_PADC_SHIFT (17U) +#define ESAI_TCR_PADC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_PADC_SHIFT)) & ESAI_TCR_PADC_MASK) +#define ESAI_TCR_TPR_MASK (0x80000U) +#define ESAI_TCR_TPR_SHIFT (19U) +#define ESAI_TCR_TPR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TPR_SHIFT)) & ESAI_TCR_TPR_MASK) +#define ESAI_TCR_TEIE_MASK (0x100000U) +#define ESAI_TCR_TEIE_SHIFT (20U) +#define ESAI_TCR_TEIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEIE_SHIFT)) & ESAI_TCR_TEIE_MASK) +#define ESAI_TCR_TEDIE_MASK (0x200000U) +#define ESAI_TCR_TEDIE_SHIFT (21U) +#define ESAI_TCR_TEDIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEDIE_SHIFT)) & ESAI_TCR_TEDIE_MASK) +#define ESAI_TCR_TIE_MASK (0x400000U) +#define ESAI_TCR_TIE_SHIFT (22U) +#define ESAI_TCR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TIE_SHIFT)) & ESAI_TCR_TIE_MASK) +#define ESAI_TCR_TLIE_MASK (0x800000U) +#define ESAI_TCR_TLIE_SHIFT (23U) +#define ESAI_TCR_TLIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TLIE_SHIFT)) & ESAI_TCR_TLIE_MASK) + +/*! @name TCCR - Transmit Clock Control Register */ +#define ESAI_TCCR_TPM_MASK (0xFFU) +#define ESAI_TCCR_TPM_SHIFT (0U) +#define ESAI_TCCR_TPM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPM_SHIFT)) & ESAI_TCCR_TPM_MASK) +#define ESAI_TCCR_TPSR_MASK (0x100U) +#define ESAI_TCCR_TPSR_SHIFT (8U) +#define ESAI_TCCR_TPSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPSR_SHIFT)) & ESAI_TCCR_TPSR_MASK) +#define ESAI_TCCR_TDC_MASK (0x3E00U) +#define ESAI_TCCR_TDC_SHIFT (9U) +#define ESAI_TCCR_TDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TDC_SHIFT)) & ESAI_TCCR_TDC_MASK) +#define ESAI_TCCR_TFP_MASK (0x3C000U) +#define ESAI_TCCR_TFP_SHIFT (14U) +#define ESAI_TCCR_TFP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFP_SHIFT)) & ESAI_TCCR_TFP_MASK) +#define ESAI_TCCR_TCKP_MASK (0x40000U) +#define ESAI_TCCR_TCKP_SHIFT (18U) +#define ESAI_TCCR_TCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKP_SHIFT)) & ESAI_TCCR_TCKP_MASK) +#define ESAI_TCCR_TFSP_MASK (0x80000U) +#define ESAI_TCCR_TFSP_SHIFT (19U) +#define ESAI_TCCR_TFSP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSP_SHIFT)) & ESAI_TCCR_TFSP_MASK) +#define ESAI_TCCR_THCKP_MASK (0x100000U) +#define ESAI_TCCR_THCKP_SHIFT (20U) +#define ESAI_TCCR_THCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKP_SHIFT)) & ESAI_TCCR_THCKP_MASK) +#define ESAI_TCCR_TCKD_MASK (0x200000U) +#define ESAI_TCCR_TCKD_SHIFT (21U) +#define ESAI_TCCR_TCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKD_SHIFT)) & ESAI_TCCR_TCKD_MASK) +#define ESAI_TCCR_TFSD_MASK (0x400000U) +#define ESAI_TCCR_TFSD_SHIFT (22U) +#define ESAI_TCCR_TFSD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSD_SHIFT)) & ESAI_TCCR_TFSD_MASK) +#define ESAI_TCCR_THCKD_MASK (0x800000U) +#define ESAI_TCCR_THCKD_SHIFT (23U) +#define ESAI_TCCR_THCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKD_SHIFT)) & ESAI_TCCR_THCKD_MASK) + +/*! @name RCR - Receive Control Register */ +#define ESAI_RCR_RE0_MASK (0x1U) +#define ESAI_RCR_RE0_SHIFT (0U) +#define ESAI_RCR_RE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE0_SHIFT)) & ESAI_RCR_RE0_MASK) +#define ESAI_RCR_RE1_MASK (0x2U) +#define ESAI_RCR_RE1_SHIFT (1U) +#define ESAI_RCR_RE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE1_SHIFT)) & ESAI_RCR_RE1_MASK) +#define ESAI_RCR_RE2_MASK (0x4U) +#define ESAI_RCR_RE2_SHIFT (2U) +#define ESAI_RCR_RE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE2_SHIFT)) & ESAI_RCR_RE2_MASK) +#define ESAI_RCR_RE3_MASK (0x8U) +#define ESAI_RCR_RE3_SHIFT (3U) +#define ESAI_RCR_RE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE3_SHIFT)) & ESAI_RCR_RE3_MASK) +#define ESAI_RCR_RSHFD_MASK (0x40U) +#define ESAI_RCR_RSHFD_SHIFT (6U) +#define ESAI_RCR_RSHFD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSHFD_SHIFT)) & ESAI_RCR_RSHFD_MASK) +#define ESAI_RCR_RWA_MASK (0x80U) +#define ESAI_RCR_RWA_SHIFT (7U) +#define ESAI_RCR_RWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RWA_SHIFT)) & ESAI_RCR_RWA_MASK) +#define ESAI_RCR_RMOD_MASK (0x300U) +#define ESAI_RCR_RMOD_SHIFT (8U) +#define ESAI_RCR_RMOD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RMOD_SHIFT)) & ESAI_RCR_RMOD_MASK) +#define ESAI_RCR_RSWS_MASK (0x7C00U) +#define ESAI_RCR_RSWS_SHIFT (10U) +#define ESAI_RCR_RSWS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSWS_SHIFT)) & ESAI_RCR_RSWS_MASK) +#define ESAI_RCR_RFSL_MASK (0x8000U) +#define ESAI_RCR_RFSL_SHIFT (15U) +#define ESAI_RCR_RFSL(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSL_SHIFT)) & ESAI_RCR_RFSL_MASK) +#define ESAI_RCR_RFSR_MASK (0x10000U) +#define ESAI_RCR_RFSR_SHIFT (16U) +#define ESAI_RCR_RFSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSR_SHIFT)) & ESAI_RCR_RFSR_MASK) +#define ESAI_RCR_RPR_MASK (0x80000U) +#define ESAI_RCR_RPR_SHIFT (19U) +#define ESAI_RCR_RPR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RPR_SHIFT)) & ESAI_RCR_RPR_MASK) +#define ESAI_RCR_REIE_MASK (0x100000U) +#define ESAI_RCR_REIE_SHIFT (20U) +#define ESAI_RCR_REIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REIE_SHIFT)) & ESAI_RCR_REIE_MASK) +#define ESAI_RCR_REDIE_MASK (0x200000U) +#define ESAI_RCR_REDIE_SHIFT (21U) +#define ESAI_RCR_REDIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REDIE_SHIFT)) & ESAI_RCR_REDIE_MASK) +#define ESAI_RCR_RIE_MASK (0x400000U) +#define ESAI_RCR_RIE_SHIFT (22U) +#define ESAI_RCR_RIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RIE_SHIFT)) & ESAI_RCR_RIE_MASK) +#define ESAI_RCR_RLIE_MASK (0x800000U) +#define ESAI_RCR_RLIE_SHIFT (23U) +#define ESAI_RCR_RLIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RLIE_SHIFT)) & ESAI_RCR_RLIE_MASK) + +/*! @name RCCR - Receive Clock Control Register */ +#define ESAI_RCCR_RPM_MASK (0xFFU) +#define ESAI_RCCR_RPM_SHIFT (0U) +#define ESAI_RCCR_RPM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPM_SHIFT)) & ESAI_RCCR_RPM_MASK) +#define ESAI_RCCR_RPSR_MASK (0x100U) +#define ESAI_RCCR_RPSR_SHIFT (8U) +#define ESAI_RCCR_RPSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPSR_SHIFT)) & ESAI_RCCR_RPSR_MASK) +#define ESAI_RCCR_RDC_MASK (0x3E00U) +#define ESAI_RCCR_RDC_SHIFT (9U) +#define ESAI_RCCR_RDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RDC_SHIFT)) & ESAI_RCCR_RDC_MASK) +#define ESAI_RCCR_RFP_MASK (0x3C000U) +#define ESAI_RCCR_RFP_SHIFT (14U) +#define ESAI_RCCR_RFP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFP_SHIFT)) & ESAI_RCCR_RFP_MASK) +#define ESAI_RCCR_RCKP_MASK (0x40000U) +#define ESAI_RCCR_RCKP_SHIFT (18U) +#define ESAI_RCCR_RCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKP_SHIFT)) & ESAI_RCCR_RCKP_MASK) +#define ESAI_RCCR_RFSP_MASK (0x80000U) +#define ESAI_RCCR_RFSP_SHIFT (19U) +#define ESAI_RCCR_RFSP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSP_SHIFT)) & ESAI_RCCR_RFSP_MASK) +#define ESAI_RCCR_RHCKP_MASK (0x100000U) +#define ESAI_RCCR_RHCKP_SHIFT (20U) +#define ESAI_RCCR_RHCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKP_SHIFT)) & ESAI_RCCR_RHCKP_MASK) +#define ESAI_RCCR_RCKD_MASK (0x200000U) +#define ESAI_RCCR_RCKD_SHIFT (21U) +#define ESAI_RCCR_RCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKD_SHIFT)) & ESAI_RCCR_RCKD_MASK) +#define ESAI_RCCR_RFSD_MASK (0x400000U) +#define ESAI_RCCR_RFSD_SHIFT (22U) +#define ESAI_RCCR_RFSD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSD_SHIFT)) & ESAI_RCCR_RFSD_MASK) +#define ESAI_RCCR_RHCKD_MASK (0x800000U) +#define ESAI_RCCR_RHCKD_SHIFT (23U) +#define ESAI_RCCR_RHCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKD_SHIFT)) & ESAI_RCCR_RHCKD_MASK) + +/*! @name TSMA - Transmit Slot Mask Register A */ +#define ESAI_TSMA_TS_MASK (0xFFFFU) +#define ESAI_TSMA_TS_SHIFT (0U) +#define ESAI_TSMA_TS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSMA_TS_SHIFT)) & ESAI_TSMA_TS_MASK) + +/*! @name TSMB - Transmit Slot Mask Register B */ +#define ESAI_TSMB_TS_MASK (0xFFFFU) +#define ESAI_TSMB_TS_SHIFT (0U) +#define ESAI_TSMB_TS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSMB_TS_SHIFT)) & ESAI_TSMB_TS_MASK) + +/*! @name RSMA - Receive Slot Mask Register A */ +#define ESAI_RSMA_RS_MASK (0xFFFFU) +#define ESAI_RSMA_RS_SHIFT (0U) +#define ESAI_RSMA_RS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RSMA_RS_SHIFT)) & ESAI_RSMA_RS_MASK) + +/*! @name RSMB - Receive Slot Mask Register B */ +#define ESAI_RSMB_RS_MASK (0xFFFFU) +#define ESAI_RSMB_RS_SHIFT (0U) +#define ESAI_RSMB_RS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RSMB_RS_SHIFT)) & ESAI_RSMB_RS_MASK) + +/*! @name PRRC - Port C Direction Register */ +#define ESAI_PRRC_PDC_MASK (0xFFFU) +#define ESAI_PRRC_PDC_SHIFT (0U) +#define ESAI_PRRC_PDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_PRRC_PDC_SHIFT)) & ESAI_PRRC_PDC_MASK) + +/*! @name PCRC - Port C Control Register */ +#define ESAI_PCRC_PC_MASK (0xFFFU) +#define ESAI_PCRC_PC_SHIFT (0U) +#define ESAI_PCRC_PC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_PCRC_PC_SHIFT)) & ESAI_PCRC_PC_MASK) + + +/*! + * @} + */ /* end of group ESAI_Register_Masks */ + + +/* ESAI - Peripheral instance base addresses */ +/** Peripheral ESAI base address */ +#define ESAI_BASE (0x2024000u) +/** Peripheral ESAI base pointer */ +#define ESAI ((ESAI_Type *)ESAI_BASE) +/** Array initializer of ESAI peripheral base addresses */ +#define ESAI_BASE_ADDRS { ESAI_BASE } +/** Array initializer of ESAI peripheral base pointers */ +#define ESAI_BASE_PTRS { ESAI } +/** Interrupt vectors for the ESAI peripheral type */ +#define ESAI_IRQS { ESAI_IRQn } + +/*! + * @} + */ /* end of group ESAI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer + * @{ + */ + +/** GPC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */ + __IO uint32_t PGR; /**< GPC Power Gating Register, offset: 0x4 */ + __IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4 */ + __I uint32_t ISR[4]; /**< IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4 */ +} GPC_Type; + +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/*! @name CNTR - GPC Interface control register */ +#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) +#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) +#define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) +#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U) +#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U) +#define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK) +#define GPC_CNTR_DISPLAY_PDN_REQ_MASK (0x10U) +#define GPC_CNTR_DISPLAY_PDN_REQ_SHIFT (4U) +#define GPC_CNTR_DISPLAY_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_DISPLAY_PDN_REQ_SHIFT)) & GPC_CNTR_DISPLAY_PDN_REQ_MASK) +#define GPC_CNTR_DISPLAY_PUP_REQ_MASK (0x20U) +#define GPC_CNTR_DISPLAY_PUP_REQ_SHIFT (5U) +#define GPC_CNTR_DISPLAY_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_DISPLAY_PUP_REQ_SHIFT)) & GPC_CNTR_DISPLAY_PUP_REQ_MASK) +#define GPC_CNTR_VADC_ANALOG_OFF_MASK (0x20000U) +#define GPC_CNTR_VADC_ANALOG_OFF_SHIFT (17U) +#define GPC_CNTR_VADC_ANALOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_VADC_ANALOG_OFF_SHIFT)) & GPC_CNTR_VADC_ANALOG_OFF_MASK) +#define GPC_CNTR_VADC_EXT_PWD_N_MASK (0x40000U) +#define GPC_CNTR_VADC_EXT_PWD_N_SHIFT (18U) +#define GPC_CNTR_VADC_EXT_PWD_N(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_VADC_EXT_PWD_N_SHIFT)) & GPC_CNTR_VADC_EXT_PWD_N_MASK) +#define GPC_CNTR_GPCIRQM_MASK (0x200000U) +#define GPC_CNTR_GPCIRQM_SHIFT (21U) +#define GPC_CNTR_GPCIRQM(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_GPCIRQM_SHIFT)) & GPC_CNTR_GPCIRQM_MASK) +#define GPC_CNTR_L2_PGE_MASK (0x400000U) +#define GPC_CNTR_L2_PGE_SHIFT (22U) +#define GPC_CNTR_L2_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_L2_PGE_SHIFT)) & GPC_CNTR_L2_PGE_MASK) + +/*! @name PGR - GPC Power Gating Register */ +#define GPC_PGR_DRCIC_MASK (0x60000000U) +#define GPC_PGR_DRCIC_SHIFT (29U) +#define GPC_PGR_DRCIC(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGR_DRCIC_SHIFT)) & GPC_PGR_DRCIC_MASK) + +/*! @name IMR - IRQ masking register 1..IRQ masking register 4 */ +#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR1_SHIFT (0U) +#define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) +#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR2_SHIFT (0U) +#define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK) +#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR3_SHIFT (0U) +#define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK) +#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR4_SHIFT (0U) +#define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) + +/* The count of GPC_IMR */ +#define GPC_IMR_COUNT (4U) + +/*! @name ISR - IRQ status resister 1..IRQ status resister 4 */ +#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR1_SHIFT (0U) +#define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) +#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR2_SHIFT (0U) +#define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK) +#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR3_SHIFT (0U) +#define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK) +#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR4_SHIFT (0U) +#define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) + +/* The count of GPC_ISR */ +#define GPC_ISR_COUNT (4U) + + +/*! + * @} + */ /* end of group GPC_Register_Masks */ + + +/* GPC - Peripheral instance base addresses */ +/** Peripheral GPC base address */ +#define GPC_BASE (0x20DC000u) +/** Peripheral GPC base pointer */ +#define GPC ((GPC_Type *)GPC_BASE) +/** Array initializer of GPC peripheral base addresses */ +#define GPC_BASE_ADDRS { GPC_BASE } +/** Array initializer of GPC peripheral base pointers */ +#define GPC_BASE_PTRS { GPC } +/** Interrupt vectors for the GPC peripheral type */ +#define GPC_IRQS { GPC_IRQn } + +/*! + * @} + */ /* end of group GPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ + __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ + __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ + __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ + __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ + __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ + __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ + __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name DR - GPIO data register */ +#define GPIO_DR_DR_MASK (0xFFFFFFFFU) +#define GPIO_DR_DR_SHIFT (0U) +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) + +/*! @name GDIR - GPIO direction register */ +#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) +#define GPIO_GDIR_GDIR_SHIFT (0U) +#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) + +/*! @name PSR - GPIO pad status register */ +#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) +#define GPIO_PSR_PSR_SHIFT (0U) +#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) + +/*! @name ICR1 - GPIO interrupt configuration register1 */ +#define GPIO_ICR1_ICR0_MASK (0x3U) +#define GPIO_ICR1_ICR0_SHIFT (0U) +#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) +#define GPIO_ICR1_ICR1_MASK (0xCU) +#define GPIO_ICR1_ICR1_SHIFT (2U) +#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) +#define GPIO_ICR1_ICR2_MASK (0x30U) +#define GPIO_ICR1_ICR2_SHIFT (4U) +#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) +#define GPIO_ICR1_ICR3_MASK (0xC0U) +#define GPIO_ICR1_ICR3_SHIFT (6U) +#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) +#define GPIO_ICR1_ICR4_MASK (0x300U) +#define GPIO_ICR1_ICR4_SHIFT (8U) +#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) +#define GPIO_ICR1_ICR5_MASK (0xC00U) +#define GPIO_ICR1_ICR5_SHIFT (10U) +#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) +#define GPIO_ICR1_ICR6_MASK (0x3000U) +#define GPIO_ICR1_ICR6_SHIFT (12U) +#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) +#define GPIO_ICR1_ICR7_MASK (0xC000U) +#define GPIO_ICR1_ICR7_SHIFT (14U) +#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) +#define GPIO_ICR1_ICR8_MASK (0x30000U) +#define GPIO_ICR1_ICR8_SHIFT (16U) +#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) +#define GPIO_ICR1_ICR9_MASK (0xC0000U) +#define GPIO_ICR1_ICR9_SHIFT (18U) +#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) +#define GPIO_ICR1_ICR10_MASK (0x300000U) +#define GPIO_ICR1_ICR10_SHIFT (20U) +#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) +#define GPIO_ICR1_ICR11_MASK (0xC00000U) +#define GPIO_ICR1_ICR11_SHIFT (22U) +#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) +#define GPIO_ICR1_ICR12_MASK (0x3000000U) +#define GPIO_ICR1_ICR12_SHIFT (24U) +#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) +#define GPIO_ICR1_ICR13_MASK (0xC000000U) +#define GPIO_ICR1_ICR13_SHIFT (26U) +#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) +#define GPIO_ICR1_ICR14_MASK (0x30000000U) +#define GPIO_ICR1_ICR14_SHIFT (28U) +#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) +#define GPIO_ICR1_ICR15_MASK (0xC0000000U) +#define GPIO_ICR1_ICR15_SHIFT (30U) +#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) + +/*! @name ICR2 - GPIO interrupt configuration register2 */ +#define GPIO_ICR2_ICR16_MASK (0x3U) +#define GPIO_ICR2_ICR16_SHIFT (0U) +#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) +#define GPIO_ICR2_ICR17_MASK (0xCU) +#define GPIO_ICR2_ICR17_SHIFT (2U) +#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) +#define GPIO_ICR2_ICR18_MASK (0x30U) +#define GPIO_ICR2_ICR18_SHIFT (4U) +#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) +#define GPIO_ICR2_ICR19_MASK (0xC0U) +#define GPIO_ICR2_ICR19_SHIFT (6U) +#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) +#define GPIO_ICR2_ICR20_MASK (0x300U) +#define GPIO_ICR2_ICR20_SHIFT (8U) +#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) +#define GPIO_ICR2_ICR21_MASK (0xC00U) +#define GPIO_ICR2_ICR21_SHIFT (10U) +#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) +#define GPIO_ICR2_ICR22_MASK (0x3000U) +#define GPIO_ICR2_ICR22_SHIFT (12U) +#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) +#define GPIO_ICR2_ICR23_MASK (0xC000U) +#define GPIO_ICR2_ICR23_SHIFT (14U) +#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) +#define GPIO_ICR2_ICR24_MASK (0x30000U) +#define GPIO_ICR2_ICR24_SHIFT (16U) +#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) +#define GPIO_ICR2_ICR25_MASK (0xC0000U) +#define GPIO_ICR2_ICR25_SHIFT (18U) +#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) +#define GPIO_ICR2_ICR26_MASK (0x300000U) +#define GPIO_ICR2_ICR26_SHIFT (20U) +#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) +#define GPIO_ICR2_ICR27_MASK (0xC00000U) +#define GPIO_ICR2_ICR27_SHIFT (22U) +#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) +#define GPIO_ICR2_ICR28_MASK (0x3000000U) +#define GPIO_ICR2_ICR28_SHIFT (24U) +#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) +#define GPIO_ICR2_ICR29_MASK (0xC000000U) +#define GPIO_ICR2_ICR29_SHIFT (26U) +#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) +#define GPIO_ICR2_ICR30_MASK (0x30000000U) +#define GPIO_ICR2_ICR30_SHIFT (28U) +#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) +#define GPIO_ICR2_ICR31_MASK (0xC0000000U) +#define GPIO_ICR2_ICR31_SHIFT (30U) +#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) + +/*! @name IMR - GPIO interrupt mask register */ +#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) +#define GPIO_IMR_IMR_SHIFT (0U) +#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) + +/*! @name ISR - GPIO interrupt status register */ +#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) +#define GPIO_ISR_ISR_SHIFT (0U) +#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) + +/*! @name EDGE_SEL - GPIO edge select register */ +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x209C000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x20A0000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x20A4000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x20A8000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Peripheral GPIO5 base address */ +#define GPIO5_BASE (0x20AC000u) +/** Peripheral GPIO5 base pointer */ +#define GPIO5 ((GPIO_Type *)GPIO5_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } +#define GPIO_COMBINED_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_0_15_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_0_15_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_0_15_IRQn, GPIO5_Combined_16_31_IRQn } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPMI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer + * @{ + */ + +/** GPMI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< GPMI Control Register 0 Description, offset: 0x0 */ + __IO uint32_t CTRL0_SET; /**< GPMI Control Register 0 Description, offset: 0x4 */ + __IO uint32_t CTRL0_CLR; /**< GPMI Control Register 0 Description, offset: 0x8 */ + __IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset: 0xC */ + __IO uint32_t COMPARE; /**< GPMI Compare Register Description, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t ECCCTRL; /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */ + __IO uint32_t ECCCTRL_SET; /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */ + __IO uint32_t ECCCTRL_CLR; /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */ + __IO uint32_t ECCCTRL_TOG; /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */ + __IO uint32_t ECCCOUNT; /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PAYLOAD; /**< GPMI Payload Address Register Description, offset: 0x40 */ + uint8_t RESERVED_2[12]; + __IO uint32_t AUXILIARY; /**< GPMI Auxiliary Address Register Description, offset: 0x50 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CTRL1; /**< GPMI Control Register 1 Description, offset: 0x60 */ + __IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset: 0x64 */ + __IO uint32_t CTRL1_CLR; /**< GPMI Control Register 1 Description, offset: 0x68 */ + __IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset: 0x6C */ + __IO uint32_t TIMING0; /**< GPMI Timing Register 0 Description, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __IO uint32_t TIMING1; /**< GPMI Timing Register 1 Description, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __IO uint32_t TIMING2; /**< GPMI Timing Register 2 Description, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DATA; /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __I uint32_t STAT; /**< GPMI Status Register Description, offset: 0xB0 */ + uint8_t RESERVED_8[12]; + __I uint32_t DEBUGr; /**< GPMI Debug Information Register Description, offset: 0xC0 */ + uint8_t RESERVED_9[12]; + __I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */ + uint8_t RESERVED_11[12]; + __I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */ + uint8_t RESERVED_12[12]; + __IO uint32_t READ_DDR_DLL_CTRL; /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */ + uint8_t RESERVED_13[12]; + __IO uint32_t WRITE_DDR_DLL_CTRL; /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */ + uint8_t RESERVED_14[12]; + __I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */ + uint8_t RESERVED_15[12]; + __I uint32_t WRITE_DDR_DLL_STS; /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */ +} GPMI_Type; + +/* ---------------------------------------------------------------------------- + -- GPMI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Register_Masks GPMI Register Masks + * @{ + */ + +/*! @name CTRL0 - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK) +#define GPMI_CTRL0_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK) +#define GPMI_CTRL0_CS_MASK (0x700000U) +#define GPMI_CTRL0_CS_SHIFT (20U) +#define GPMI_CTRL0_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK) +#define GPMI_CTRL0_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK) +#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK) +#define GPMI_CTRL0_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_UDMA_SHIFT (26U) +#define GPMI_CTRL0_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK) +#define GPMI_CTRL0_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK) +#define GPMI_CTRL0_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_RUN_SHIFT (29U) +#define GPMI_CTRL0_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK) +#define GPMI_CTRL0_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK) +#define GPMI_CTRL0_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK) + +/*! @name CTRL0_SET - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_SET_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_SET_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_SET_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_XFER_COUNT_SHIFT)) & GPMI_CTRL0_SET_XFER_COUNT_MASK) +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_SET_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_SET_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_SET_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_MASK) +#define GPMI_CTRL0_SET_CS_MASK (0x700000U) +#define GPMI_CTRL0_SET_CS_SHIFT (20U) +#define GPMI_CTRL0_SET_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CS_SHIFT)) & GPMI_CTRL0_SET_CS_MASK) +#define GPMI_CTRL0_SET_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_SET_WORD_LENGTH_MASK) +#define GPMI_CTRL0_SET_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_SET_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_SET_COMMAND_MODE_MASK) +#define GPMI_CTRL0_SET_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_SET_UDMA_SHIFT (26U) +#define GPMI_CTRL0_SET_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_UDMA_SHIFT)) & GPMI_CTRL0_SET_UDMA_MASK) +#define GPMI_CTRL0_SET_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_SET_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_SET_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_LOCK_CS_SHIFT)) & GPMI_CTRL0_SET_LOCK_CS_MASK) +#define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_SET_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_SET_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_SET_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_SET_RUN_SHIFT (29U) +#define GPMI_CTRL0_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_RUN_SHIFT)) & GPMI_CTRL0_SET_RUN_MASK) +#define GPMI_CTRL0_SET_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_SET_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CLKGATE_SHIFT)) & GPMI_CTRL0_SET_CLKGATE_MASK) +#define GPMI_CTRL0_SET_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_SET_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_SFTRST_SHIFT)) & GPMI_CTRL0_SET_SFTRST_MASK) + +/*! @name CTRL0_CLR - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_CLR_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_CLR_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_XFER_COUNT_SHIFT)) & GPMI_CTRL0_CLR_XFER_COUNT_MASK) +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_CLR_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_CLR_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_CLR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_MASK) +#define GPMI_CTRL0_CLR_CS_MASK (0x700000U) +#define GPMI_CTRL0_CLR_CS_SHIFT (20U) +#define GPMI_CTRL0_CLR_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CS_SHIFT)) & GPMI_CTRL0_CLR_CS_MASK) +#define GPMI_CTRL0_CLR_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_CLR_WORD_LENGTH_MASK) +#define GPMI_CTRL0_CLR_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_CLR_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_CLR_COMMAND_MODE_MASK) +#define GPMI_CTRL0_CLR_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_CLR_UDMA_SHIFT (26U) +#define GPMI_CTRL0_CLR_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_UDMA_SHIFT)) & GPMI_CTRL0_CLR_UDMA_MASK) +#define GPMI_CTRL0_CLR_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_CLR_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_CLR_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_LOCK_CS_SHIFT)) & GPMI_CTRL0_CLR_LOCK_CS_MASK) +#define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_CLR_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_CLR_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_CLR_RUN_SHIFT (29U) +#define GPMI_CTRL0_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_RUN_SHIFT)) & GPMI_CTRL0_CLR_RUN_MASK) +#define GPMI_CTRL0_CLR_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_CLR_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CLKGATE_SHIFT)) & GPMI_CTRL0_CLR_CLKGATE_MASK) +#define GPMI_CTRL0_CLR_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_CLR_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_SFTRST_SHIFT)) & GPMI_CTRL0_CLR_SFTRST_MASK) + +/*! @name CTRL0_TOG - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_TOG_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_TOG_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_XFER_COUNT_SHIFT)) & GPMI_CTRL0_TOG_XFER_COUNT_MASK) +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_TOG_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_TOG_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_TOG_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_MASK) +#define GPMI_CTRL0_TOG_CS_MASK (0x700000U) +#define GPMI_CTRL0_TOG_CS_SHIFT (20U) +#define GPMI_CTRL0_TOG_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CS_SHIFT)) & GPMI_CTRL0_TOG_CS_MASK) +#define GPMI_CTRL0_TOG_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_TOG_WORD_LENGTH_MASK) +#define GPMI_CTRL0_TOG_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_TOG_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_TOG_COMMAND_MODE_MASK) +#define GPMI_CTRL0_TOG_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_TOG_UDMA_SHIFT (26U) +#define GPMI_CTRL0_TOG_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_UDMA_SHIFT)) & GPMI_CTRL0_TOG_UDMA_MASK) +#define GPMI_CTRL0_TOG_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_TOG_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_TOG_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_LOCK_CS_SHIFT)) & GPMI_CTRL0_TOG_LOCK_CS_MASK) +#define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_TOG_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_TOG_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_TOG_RUN_SHIFT (29U) +#define GPMI_CTRL0_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_RUN_SHIFT)) & GPMI_CTRL0_TOG_RUN_MASK) +#define GPMI_CTRL0_TOG_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_TOG_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CLKGATE_SHIFT)) & GPMI_CTRL0_TOG_CLKGATE_MASK) +#define GPMI_CTRL0_TOG_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_TOG_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_SFTRST_SHIFT)) & GPMI_CTRL0_TOG_SFTRST_MASK) + +/*! @name COMPARE - GPMI Compare Register Description */ +#define GPMI_COMPARE_REFERENCE_MASK (0xFFFFU) +#define GPMI_COMPARE_REFERENCE_SHIFT (0U) +#define GPMI_COMPARE_REFERENCE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK) +#define GPMI_COMPARE_MASK_MASK (0xFFFF0000U) +#define GPMI_COMPARE_MASK_SHIFT (16U) +#define GPMI_COMPARE_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK) + +/*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD1_SHIFT)) & GPMI_ECCCTRL_RSVD1_MASK) +#define GPMI_ECCCTRL_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK) +#define GPMI_ECCCTRL_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK) +#define GPMI_ECCCTRL_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK) + +/*! @name ECCCTRL_SET - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_SET_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_SET_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_SET_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_SET_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD1_SHIFT)) & GPMI_ECCCTRL_SET_RSVD1_MASK) +#define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_SET_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_SET_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_SET_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_SET_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_SET_ECC_CMD_MASK) +#define GPMI_ECCCTRL_SET_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_SET_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD2_SHIFT)) & GPMI_ECCCTRL_SET_RSVD2_MASK) +#define GPMI_ECCCTRL_SET_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_SET_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_HANDLE_SHIFT)) & GPMI_ECCCTRL_SET_HANDLE_MASK) + +/*! @name ECCCTRL_CLR - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_CLR_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_CLR_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_CLR_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD1_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD1_MASK) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_CLR_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_CLR_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_CLR_ECC_CMD_MASK) +#define GPMI_ECCCTRL_CLR_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_CLR_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD2_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD2_MASK) +#define GPMI_ECCCTRL_CLR_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_CLR_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_HANDLE_SHIFT)) & GPMI_ECCCTRL_CLR_HANDLE_MASK) + +/*! @name ECCCTRL_TOG - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_TOG_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_TOG_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_TOG_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD1_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD1_MASK) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_TOG_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_TOG_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_TOG_ECC_CMD_MASK) +#define GPMI_ECCCTRL_TOG_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_TOG_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD2_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD2_MASK) +#define GPMI_ECCCTRL_TOG_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_TOG_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_HANDLE_SHIFT)) & GPMI_ECCCTRL_TOG_HANDLE_MASK) + +/*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */ +#define GPMI_ECCCOUNT_COUNT_MASK (0xFFFFU) +#define GPMI_ECCCOUNT_COUNT_SHIFT (0U) +#define GPMI_ECCCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK) +#define GPMI_ECCCOUNT_RSVD2_MASK (0xFFFF0000U) +#define GPMI_ECCCOUNT_RSVD2_SHIFT (16U) +#define GPMI_ECCCOUNT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RSVD2_SHIFT)) & GPMI_ECCCOUNT_RSVD2_MASK) + +/*! @name PAYLOAD - GPMI Payload Address Register Description */ +#define GPMI_PAYLOAD_RSVD0_MASK (0x3U) +#define GPMI_PAYLOAD_RSVD0_SHIFT (0U) +#define GPMI_PAYLOAD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK) +#define GPMI_PAYLOAD_ADDRESS_MASK (0xFFFFFFFCU) +#define GPMI_PAYLOAD_ADDRESS_SHIFT (2U) +#define GPMI_PAYLOAD_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK) + +/*! @name AUXILIARY - GPMI Auxiliary Address Register Description */ +#define GPMI_AUXILIARY_RSVD0_MASK (0x3U) +#define GPMI_AUXILIARY_RSVD0_SHIFT (0U) +#define GPMI_AUXILIARY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK) +#define GPMI_AUXILIARY_ADDRESS_MASK (0xFFFFFFFCU) +#define GPMI_AUXILIARY_ADDRESS_SHIFT (2U) +#define GPMI_AUXILIARY_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK) + +/*! @name CTRL1 - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK) +#define GPMI_CTRL1_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK) +#define GPMI_CTRL1_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK) +#define GPMI_CTRL1_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK) +#define GPMI_CTRL1_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK) +#define GPMI_CTRL1_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK) +#define GPMI_CTRL1_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK) +#define GPMI_CTRL1_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK) +#define GPMI_CTRL1_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK) +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK) + +/*! @name CTRL1_SET - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_SET_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_SET_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_SET_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_MODE_SHIFT)) & GPMI_CTRL1_SET_GPMI_MODE_MASK) +#define GPMI_CTRL1_SET_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_SET_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_SET_CAMERA_MODE_MASK) +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_SET_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_SET_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_SET_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_RESET_SHIFT)) & GPMI_CTRL1_SET_DEV_RESET_MASK) +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_SET_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_SET_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_SET_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BURST_EN_SHIFT)) & GPMI_CTRL1_SET_BURST_EN_MASK) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_SET_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_SET_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_SET_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_IRQ_SHIFT)) & GPMI_CTRL1_SET_DEV_IRQ_MASK) +#define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_SET_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_SET_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_SET_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_SET_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_SET_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_RDN_DELAY_SHIFT)) & GPMI_CTRL1_SET_RDN_DELAY_MASK) +#define GPMI_CTRL1_SET_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_SET_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_SET_HALF_PERIOD_MASK) +#define GPMI_CTRL1_SET_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_SET_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_SET_DLL_ENABLE_MASK) +#define GPMI_CTRL1_SET_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_SET_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_SET_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BCH_MODE_SHIFT)) & GPMI_CTRL1_SET_BCH_MODE_MASK) +#define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_SET_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_SET_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_SET_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_SET_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_SET_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_SET_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_SET_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_SET_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_SET_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_SET_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_SET_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_SET_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SET_SSYNCMODE_MASK) +#define GPMI_CTRL1_SET_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_SET_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_SET_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_UPDATE_CS_SHIFT)) & GPMI_CTRL1_SET_UPDATE_CS_MASK) +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_SET_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_SET_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_SET_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_SET_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_SET_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_DEV_CLK_STOP_MASK) + +/*! @name CTRL1_CLR - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_CLR_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_CLR_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_MODE_SHIFT)) & GPMI_CTRL1_CLR_GPMI_MODE_MASK) +#define GPMI_CTRL1_CLR_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_CLR_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CLR_CAMERA_MODE_MASK) +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_CLR_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_CLR_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_CLR_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_RESET_SHIFT)) & GPMI_CTRL1_CLR_DEV_RESET_MASK) +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_CLR_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_CLR_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_CLR_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BURST_EN_SHIFT)) & GPMI_CTRL1_CLR_BURST_EN_MASK) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_CLR_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_CLR_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_IRQ_SHIFT)) & GPMI_CTRL1_CLR_DEV_IRQ_MASK) +#define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_CLR_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_CLR_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_CLR_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_RDN_DELAY_SHIFT)) & GPMI_CTRL1_CLR_RDN_DELAY_MASK) +#define GPMI_CTRL1_CLR_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_CLR_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_CLR_HALF_PERIOD_MASK) +#define GPMI_CTRL1_CLR_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_CLR_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_CLR_DLL_ENABLE_MASK) +#define GPMI_CTRL1_CLR_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_CLR_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_CLR_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BCH_MODE_SHIFT)) & GPMI_CTRL1_CLR_BCH_MODE_MASK) +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_CLR_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_CLR_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_CLR_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_CLR_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_CLR_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_CLR_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_CLR_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNCMODE_SHIFT)) & GPMI_CTRL1_CLR_SSYNCMODE_MASK) +#define GPMI_CTRL1_CLR_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_CLR_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_UPDATE_CS_SHIFT)) & GPMI_CTRL1_CLR_UPDATE_CS_MASK) +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_CLR_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_CLR_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_CLR_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK) + +/*! @name CTRL1_TOG - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_TOG_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_TOG_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_MODE_SHIFT)) & GPMI_CTRL1_TOG_GPMI_MODE_MASK) +#define GPMI_CTRL1_TOG_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_TOG_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_TOG_CAMERA_MODE_MASK) +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_TOG_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_TOG_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_TOG_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_RESET_SHIFT)) & GPMI_CTRL1_TOG_DEV_RESET_MASK) +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_TOG_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_TOG_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_TOG_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BURST_EN_SHIFT)) & GPMI_CTRL1_TOG_BURST_EN_MASK) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_TOG_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_TOG_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_IRQ_SHIFT)) & GPMI_CTRL1_TOG_DEV_IRQ_MASK) +#define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_TOG_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_TOG_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_TOG_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_RDN_DELAY_SHIFT)) & GPMI_CTRL1_TOG_RDN_DELAY_MASK) +#define GPMI_CTRL1_TOG_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_TOG_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_TOG_HALF_PERIOD_MASK) +#define GPMI_CTRL1_TOG_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_TOG_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_TOG_DLL_ENABLE_MASK) +#define GPMI_CTRL1_TOG_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_TOG_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_TOG_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BCH_MODE_SHIFT)) & GPMI_CTRL1_TOG_BCH_MODE_MASK) +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_TOG_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TOG_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_TOG_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_TOG_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_TOG_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_TOG_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_TOG_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNCMODE_SHIFT)) & GPMI_CTRL1_TOG_SSYNCMODE_MASK) +#define GPMI_CTRL1_TOG_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_TOG_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_UPDATE_CS_SHIFT)) & GPMI_CTRL1_TOG_UPDATE_CS_MASK) +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_TOG_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOG_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_TOG_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK) + +/*! @name TIMING0 - GPMI Timing Register 0 Description */ +#define GPMI_TIMING0_DATA_SETUP_MASK (0xFFU) +#define GPMI_TIMING0_DATA_SETUP_SHIFT (0U) +#define GPMI_TIMING0_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK) +#define GPMI_TIMING0_DATA_HOLD_MASK (0xFF00U) +#define GPMI_TIMING0_DATA_HOLD_SHIFT (8U) +#define GPMI_TIMING0_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK) +#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xFF0000U) +#define GPMI_TIMING0_ADDRESS_SETUP_SHIFT (16U) +#define GPMI_TIMING0_ADDRESS_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK) +#define GPMI_TIMING0_RSVD1_MASK (0xFF000000U) +#define GPMI_TIMING0_RSVD1_SHIFT (24U) +#define GPMI_TIMING0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK) + +/*! @name TIMING1 - GPMI Timing Register 1 Description */ +#define GPMI_TIMING1_RSVD1_MASK (0xFFFFU) +#define GPMI_TIMING1_RSVD1_SHIFT (0U) +#define GPMI_TIMING1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xFFFF0000U) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT (16U) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK) + +/*! @name TIMING2 - GPMI Timing Register 2 Description */ +#define GPMI_TIMING2_DATA_PAUSE_MASK (0xFU) +#define GPMI_TIMING2_DATA_PAUSE_SHIFT (0U) +#define GPMI_TIMING2_DATA_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK) +#define GPMI_TIMING2_CMDADD_PAUSE_MASK (0xF0U) +#define GPMI_TIMING2_CMDADD_PAUSE_SHIFT (4U) +#define GPMI_TIMING2_CMDADD_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK) +#define GPMI_TIMING2_POSTAMBLE_DELAY_MASK (0xF00U) +#define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT (8U) +#define GPMI_TIMING2_POSTAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK) +#define GPMI_TIMING2_PREAMBLE_DELAY_MASK (0xF000U) +#define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT (12U) +#define GPMI_TIMING2_PREAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK) +#define GPMI_TIMING2_CE_DELAY_MASK (0x1F0000U) +#define GPMI_TIMING2_CE_DELAY_SHIFT (16U) +#define GPMI_TIMING2_CE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK) +#define GPMI_TIMING2_RSVD0_MASK (0xE00000U) +#define GPMI_TIMING2_RSVD0_SHIFT (21U) +#define GPMI_TIMING2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK) +#define GPMI_TIMING2_READ_LATENCY_MASK (0x7000000U) +#define GPMI_TIMING2_READ_LATENCY_SHIFT (24U) +#define GPMI_TIMING2_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK) +#define GPMI_TIMING2_TCR_MASK (0x18000000U) +#define GPMI_TIMING2_TCR_SHIFT (27U) +#define GPMI_TIMING2_TCR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TCR_SHIFT)) & GPMI_TIMING2_TCR_MASK) +#define GPMI_TIMING2_TRPSTH_MASK (0xE0000000U) +#define GPMI_TIMING2_TRPSTH_SHIFT (29U) +#define GPMI_TIMING2_TRPSTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TRPSTH_SHIFT)) & GPMI_TIMING2_TRPSTH_MASK) + +/*! @name DATA - GPMI DMA Data Transfer Register Description */ +#define GPMI_DATA_DATA_MASK (0xFFFFFFFFU) +#define GPMI_DATA_DATA_SHIFT (0U) +#define GPMI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK) + +/*! @name STAT - GPMI Status Register Description */ +#define GPMI_STAT_PRESENT_MASK (0x1U) +#define GPMI_STAT_PRESENT_SHIFT (0U) +#define GPMI_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK) +#define GPMI_STAT_FIFO_FULL_MASK (0x2U) +#define GPMI_STAT_FIFO_FULL_SHIFT (1U) +#define GPMI_STAT_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK) +#define GPMI_STAT_FIFO_EMPTY_MASK (0x4U) +#define GPMI_STAT_FIFO_EMPTY_SHIFT (2U) +#define GPMI_STAT_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK) +#define GPMI_STAT_INVALID_BUFFER_MASK_MASK (0x8U) +#define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT (3U) +#define GPMI_STAT_INVALID_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK) +#define GPMI_STAT_ATA_IRQ_MASK (0x10U) +#define GPMI_STAT_ATA_IRQ_SHIFT (4U) +#define GPMI_STAT_ATA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK) +#define GPMI_STAT_RSVD1_MASK (0xE0U) +#define GPMI_STAT_RSVD1_SHIFT (5U) +#define GPMI_STAT_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK) +#define GPMI_STAT_DEV0_ERROR_MASK (0x100U) +#define GPMI_STAT_DEV0_ERROR_SHIFT (8U) +#define GPMI_STAT_DEV0_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK) +#define GPMI_STAT_DEV1_ERROR_MASK (0x200U) +#define GPMI_STAT_DEV1_ERROR_SHIFT (9U) +#define GPMI_STAT_DEV1_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK) +#define GPMI_STAT_DEV2_ERROR_MASK (0x400U) +#define GPMI_STAT_DEV2_ERROR_SHIFT (10U) +#define GPMI_STAT_DEV2_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK) +#define GPMI_STAT_DEV3_ERROR_MASK (0x800U) +#define GPMI_STAT_DEV3_ERROR_SHIFT (11U) +#define GPMI_STAT_DEV3_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK) +#define GPMI_STAT_DEV4_ERROR_MASK (0x1000U) +#define GPMI_STAT_DEV4_ERROR_SHIFT (12U) +#define GPMI_STAT_DEV4_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK) +#define GPMI_STAT_DEV5_ERROR_MASK (0x2000U) +#define GPMI_STAT_DEV5_ERROR_SHIFT (13U) +#define GPMI_STAT_DEV5_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK) +#define GPMI_STAT_DEV6_ERROR_MASK (0x4000U) +#define GPMI_STAT_DEV6_ERROR_SHIFT (14U) +#define GPMI_STAT_DEV6_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK) +#define GPMI_STAT_DEV7_ERROR_MASK (0x8000U) +#define GPMI_STAT_DEV7_ERROR_SHIFT (15U) +#define GPMI_STAT_DEV7_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK) +#define GPMI_STAT_RDY_TIMEOUT_MASK (0xFF0000U) +#define GPMI_STAT_RDY_TIMEOUT_SHIFT (16U) +#define GPMI_STAT_RDY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK) +#define GPMI_STAT_READY_BUSY_MASK (0xFF000000U) +#define GPMI_STAT_READY_BUSY_SHIFT (24U) +#define GPMI_STAT_READY_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK) + +/*! @name DEBUG - GPMI Debug Information Register Description */ +#define GPMI_DEBUG_CMD_END_MASK (0xFFU) +#define GPMI_DEBUG_CMD_END_SHIFT (0U) +#define GPMI_DEBUG_CMD_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK) +#define GPMI_DEBUG_DMAREQ_MASK (0xFF00U) +#define GPMI_DEBUG_DMAREQ_SHIFT (8U) +#define GPMI_DEBUG_DMAREQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK) +#define GPMI_DEBUG_DMA_SENSE_MASK (0xFF0000U) +#define GPMI_DEBUG_DMA_SENSE_SHIFT (16U) +#define GPMI_DEBUG_DMA_SENSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK) +#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xFF000000U) +#define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT (24U) +#define GPMI_DEBUG_WAIT_FOR_READY_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK) + +/*! @name VERSION - GPMI Version Register Description */ +#define GPMI_VERSION_STEP_MASK (0xFFFFU) +#define GPMI_VERSION_STEP_SHIFT (0U) +#define GPMI_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK) +#define GPMI_VERSION_MINOR_MASK (0xFF0000U) +#define GPMI_VERSION_MINOR_SHIFT (16U) +#define GPMI_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK) +#define GPMI_VERSION_MAJOR_MASK (0xFF000000U) +#define GPMI_VERSION_MAJOR_SHIFT (24U) +#define GPMI_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK) + +/*! @name DEBUG2 - GPMI Debug2 Information Register Description */ +#define GPMI_DEBUG2_RDN_TAP_MASK (0x3FU) +#define GPMI_DEBUG2_RDN_TAP_SHIFT (0U) +#define GPMI_DEBUG2_RDN_TAP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK) +#define GPMI_DEBUG2_UPDATE_WINDOW_MASK (0x40U) +#define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT (6U) +#define GPMI_DEBUG2_UPDATE_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK (0x80U) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT (7U) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK) +#define GPMI_DEBUG2_SYND2GPMI_READY_MASK (0x100U) +#define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT (8U) +#define GPMI_DEBUG2_SYND2GPMI_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK) +#define GPMI_DEBUG2_SYND2GPMI_VALID_MASK (0x200U) +#define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT (9U) +#define GPMI_DEBUG2_SYND2GPMI_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK) +#define GPMI_DEBUG2_GPMI2SYND_READY_MASK (0x400U) +#define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT (10U) +#define GPMI_DEBUG2_GPMI2SYND_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK) +#define GPMI_DEBUG2_GPMI2SYND_VALID_MASK (0x800U) +#define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT (11U) +#define GPMI_DEBUG2_GPMI2SYND_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK) +#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xF000U) +#define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT (12U) +#define GPMI_DEBUG2_SYND2GPMI_BE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK) +#define GPMI_DEBUG2_MAIN_STATE_MASK (0xF0000U) +#define GPMI_DEBUG2_MAIN_STATE_SHIFT (16U) +#define GPMI_DEBUG2_MAIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK) +#define GPMI_DEBUG2_PIN_STATE_MASK (0x700000U) +#define GPMI_DEBUG2_PIN_STATE_SHIFT (20U) +#define GPMI_DEBUG2_PIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK) +#define GPMI_DEBUG2_BUSY_MASK (0x800000U) +#define GPMI_DEBUG2_BUSY_SHIFT (23U) +#define GPMI_DEBUG2_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK) +#define GPMI_DEBUG2_UDMA_STATE_MASK (0xF000000U) +#define GPMI_DEBUG2_UDMA_STATE_SHIFT (24U) +#define GPMI_DEBUG2_UDMA_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK) +#define GPMI_DEBUG2_RSVD1_MASK (0xF0000000U) +#define GPMI_DEBUG2_RSVD1_SHIFT (28U) +#define GPMI_DEBUG2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK) + +/*! @name DEBUG3 - GPMI Debug3 Information Register Description */ +#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK (0xFFFFU) +#define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT (0U) +#define GPMI_DEBUG3_DEV_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK) +#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xFFFF0000U) +#define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT (16U) +#define GPMI_DEBUG3_APB_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK) + +/*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */ +#define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK (0x1U) +#define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT (0U) +#define GPMI_READ_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK) +#define GPMI_READ_DDR_DLL_CTRL_RESET_MASK (0x2U) +#define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT (1U) +#define GPMI_READ_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK) +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT (18U) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) + +/*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */ +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK (0x1U) +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT (0U) +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK (0x2U) +#define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT (1U) +#define GPMI_WRITE_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT (18U) +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) + +/*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */ +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK) +#define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) +#define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT (1U) +#define GPMI_READ_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK) +#define GPMI_READ_DDR_DLL_STS_RSVD0_MASK (0xFE00U) +#define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT (9U) +#define GPMI_READ_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT (16U) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK) +#define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) +#define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT (17U) +#define GPMI_READ_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK) +#define GPMI_READ_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) +#define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT (25U) +#define GPMI_READ_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK) + +/*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */ +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK) +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT (1U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK) +#define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK (0xFE00U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT (9U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK) +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT (16U) +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK) +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT (17U) +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK) +#define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT (25U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK) + + +/*! + * @} + */ /* end of group GPMI_Register_Masks */ + + +/* GPMI - Peripheral instance base addresses */ +/** Peripheral GPMI base address */ +#define GPMI_BASE (0x1806000u) +/** Peripheral GPMI base pointer */ +#define GPMI ((GPMI_Type *)GPMI_BASE) +/** Array initializer of GPMI peripheral base addresses */ +#define GPMI_BASE_ADDRS { GPMI_BASE } +/** Array initializer of GPMI peripheral base pointers */ +#define GPMI_BASE_PTRS { GPMI } +/** Interrupt vectors for the GPMI peripheral type */ +#define GPMI_IRQS { RAWNAND_GPMI_IRQn } + +/*! + * @} + */ /* end of group GPMI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer + * @{ + */ + +/** GPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ + __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ + __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ + __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ + __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ + __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ + __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ +} GPT_Type; + +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/*! @name CR - GPT Control Register */ +#define GPT_CR_EN_MASK (0x1U) +#define GPT_CR_EN_SHIFT (0U) +#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) +#define GPT_CR_ENMOD_MASK (0x2U) +#define GPT_CR_ENMOD_SHIFT (1U) +#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) +#define GPT_CR_DBGEN_MASK (0x4U) +#define GPT_CR_DBGEN_SHIFT (2U) +#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) +#define GPT_CR_WAITEN_MASK (0x8U) +#define GPT_CR_WAITEN_SHIFT (3U) +#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) +#define GPT_CR_DOZEEN_MASK (0x10U) +#define GPT_CR_DOZEEN_SHIFT (4U) +#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) +#define GPT_CR_STOPEN_MASK (0x20U) +#define GPT_CR_STOPEN_SHIFT (5U) +#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) +#define GPT_CR_CLKSRC_MASK (0x1C0U) +#define GPT_CR_CLKSRC_SHIFT (6U) +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) +#define GPT_CR_FRR_MASK (0x200U) +#define GPT_CR_FRR_SHIFT (9U) +#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) +#define GPT_CR_EN_24M_MASK (0x400U) +#define GPT_CR_EN_24M_SHIFT (10U) +#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) +#define GPT_CR_SWR_MASK (0x8000U) +#define GPT_CR_SWR_SHIFT (15U) +#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) +#define GPT_CR_IM1_MASK (0x30000U) +#define GPT_CR_IM1_SHIFT (16U) +#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) +#define GPT_CR_IM2_MASK (0xC0000U) +#define GPT_CR_IM2_SHIFT (18U) +#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) +#define GPT_CR_OM1_MASK (0x700000U) +#define GPT_CR_OM1_SHIFT (20U) +#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) +#define GPT_CR_OM2_MASK (0x3800000U) +#define GPT_CR_OM2_SHIFT (23U) +#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) +#define GPT_CR_OM3_MASK (0x1C000000U) +#define GPT_CR_OM3_SHIFT (26U) +#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) +#define GPT_CR_FO1_MASK (0x20000000U) +#define GPT_CR_FO1_SHIFT (29U) +#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) +#define GPT_CR_FO2_MASK (0x40000000U) +#define GPT_CR_FO2_SHIFT (30U) +#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) +#define GPT_CR_FO3_MASK (0x80000000U) +#define GPT_CR_FO3_SHIFT (31U) +#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) + +/*! @name PR - GPT Prescaler Register */ +#define GPT_PR_PRESCALER_MASK (0xFFFU) +#define GPT_PR_PRESCALER_SHIFT (0U) +#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) +#define GPT_PR_PRESCALER24M_MASK (0xF000U) +#define GPT_PR_PRESCALER24M_SHIFT (12U) +#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) + +/*! @name SR - GPT Status Register */ +#define GPT_SR_OF1_MASK (0x1U) +#define GPT_SR_OF1_SHIFT (0U) +#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) +#define GPT_SR_OF2_MASK (0x2U) +#define GPT_SR_OF2_SHIFT (1U) +#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) +#define GPT_SR_OF3_MASK (0x4U) +#define GPT_SR_OF3_SHIFT (2U) +#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) +#define GPT_SR_IF1_MASK (0x8U) +#define GPT_SR_IF1_SHIFT (3U) +#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) +#define GPT_SR_IF2_MASK (0x10U) +#define GPT_SR_IF2_SHIFT (4U) +#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) +#define GPT_SR_ROV_MASK (0x20U) +#define GPT_SR_ROV_SHIFT (5U) +#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) + +/*! @name IR - GPT Interrupt Register */ +#define GPT_IR_OF1IE_MASK (0x1U) +#define GPT_IR_OF1IE_SHIFT (0U) +#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) +#define GPT_IR_OF2IE_MASK (0x2U) +#define GPT_IR_OF2IE_SHIFT (1U) +#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) +#define GPT_IR_OF3IE_MASK (0x4U) +#define GPT_IR_OF3IE_SHIFT (2U) +#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) +#define GPT_IR_IF1IE_MASK (0x8U) +#define GPT_IR_IF1IE_SHIFT (3U) +#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) +#define GPT_IR_IF2IE_MASK (0x10U) +#define GPT_IR_IF2IE_SHIFT (4U) +#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) +#define GPT_IR_ROVIE_MASK (0x20U) +#define GPT_IR_ROVIE_SHIFT (5U) +#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) + +/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ +#define GPT_OCR_COMP_MASK (0xFFFFFFFFU) +#define GPT_OCR_COMP_SHIFT (0U) +#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) + +/* The count of GPT_OCR */ +#define GPT_OCR_COUNT (3U) + +/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ +#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) +#define GPT_ICR_CAPT_SHIFT (0U) +#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) + +/* The count of GPT_ICR */ +#define GPT_ICR_COUNT (2U) + +/*! @name CNT - GPT Counter Register */ +#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) +#define GPT_CNT_COUNT_SHIFT (0U) +#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) + + +/*! + * @} + */ /* end of group GPT_Register_Masks */ + + +/* GPT - Peripheral instance base addresses */ +/** Peripheral GPT1 base address */ +#define GPT1_BASE (0x2098000u) +/** Peripheral GPT1 base pointer */ +#define GPT1 ((GPT_Type *)GPT1_BASE) +/** Peripheral GPT2 base address */ +#define GPT2_BASE (0x20E8000u) +/** Peripheral GPT2 base pointer */ +#define GPT2 ((GPT_Type *)GPT2_BASE) +/** Array initializer of GPT peripheral base addresses */ +#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE } +/** Array initializer of GPT peripheral base pointers */ +#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 } +/** Interrupt vectors for the GPT peripheral type */ +#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn } + +/*! + * @} + */ /* end of group GPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */ + uint8_t RESERVED_0[2]; + __IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 */ + uint8_t RESERVED_1[2]; + __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */ + uint8_t RESERVED_2[2]; + __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */ + uint8_t RESERVED_3[2]; + __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name IADR - I2C Address Register */ +#define I2C_IADR_ADR_MASK (0xFEU) +#define I2C_IADR_ADR_SHIFT (1U) +#define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x)) << I2C_IADR_ADR_SHIFT)) & I2C_IADR_ADR_MASK) + +/*! @name IFDR - I2C Frequency Divider Register */ +#define I2C_IFDR_IC_MASK (0x3FU) +#define I2C_IFDR_IC_SHIFT (0U) +#define I2C_IFDR_IC(x) (((uint16_t)(((uint16_t)(x)) << I2C_IFDR_IC_SHIFT)) & I2C_IFDR_IC_MASK) + +/*! @name I2CR - I2C Control Register */ +#define I2C_I2CR_RSTA_MASK (0x4U) +#define I2C_I2CR_RSTA_SHIFT (2U) +#define I2C_I2CR_RSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_RSTA_SHIFT)) & I2C_I2CR_RSTA_MASK) +#define I2C_I2CR_TXAK_MASK (0x8U) +#define I2C_I2CR_TXAK_SHIFT (3U) +#define I2C_I2CR_TXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_TXAK_SHIFT)) & I2C_I2CR_TXAK_MASK) +#define I2C_I2CR_MTX_MASK (0x10U) +#define I2C_I2CR_MTX_SHIFT (4U) +#define I2C_I2CR_MTX(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MTX_SHIFT)) & I2C_I2CR_MTX_MASK) +#define I2C_I2CR_MSTA_MASK (0x20U) +#define I2C_I2CR_MSTA_SHIFT (5U) +#define I2C_I2CR_MSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MSTA_SHIFT)) & I2C_I2CR_MSTA_MASK) +#define I2C_I2CR_IIEN_MASK (0x40U) +#define I2C_I2CR_IIEN_SHIFT (6U) +#define I2C_I2CR_IIEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IIEN_SHIFT)) & I2C_I2CR_IIEN_MASK) +#define I2C_I2CR_IEN_MASK (0x80U) +#define I2C_I2CR_IEN_SHIFT (7U) +#define I2C_I2CR_IEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IEN_SHIFT)) & I2C_I2CR_IEN_MASK) + +/*! @name I2SR - I2C Status Register */ +#define I2C_I2SR_RXAK_MASK (0x1U) +#define I2C_I2SR_RXAK_SHIFT (0U) +#define I2C_I2SR_RXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_RXAK_SHIFT)) & I2C_I2SR_RXAK_MASK) +#define I2C_I2SR_IIF_MASK (0x2U) +#define I2C_I2SR_IIF_SHIFT (1U) +#define I2C_I2SR_IIF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IIF_SHIFT)) & I2C_I2SR_IIF_MASK) +#define I2C_I2SR_SRW_MASK (0x4U) +#define I2C_I2SR_SRW_SHIFT (2U) +#define I2C_I2SR_SRW(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_SRW_SHIFT)) & I2C_I2SR_SRW_MASK) +#define I2C_I2SR_IAL_MASK (0x10U) +#define I2C_I2SR_IAL_SHIFT (4U) +#define I2C_I2SR_IAL(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAL_SHIFT)) & I2C_I2SR_IAL_MASK) +#define I2C_I2SR_IBB_MASK (0x20U) +#define I2C_I2SR_IBB_SHIFT (5U) +#define I2C_I2SR_IBB(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IBB_SHIFT)) & I2C_I2SR_IBB_MASK) +#define I2C_I2SR_IAAS_MASK (0x40U) +#define I2C_I2SR_IAAS_SHIFT (6U) +#define I2C_I2SR_IAAS(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAAS_SHIFT)) & I2C_I2SR_IAAS_MASK) +#define I2C_I2SR_ICF_MASK (0x80U) +#define I2C_I2SR_ICF_SHIFT (7U) +#define I2C_I2SR_ICF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_ICF_SHIFT)) & I2C_I2SR_ICF_MASK) + +/*! @name I2DR - I2C Data I/O Register */ +#define I2C_I2DR_DATA_MASK (0xFFU) +#define I2C_I2DR_DATA_SHIFT (0U) +#define I2C_I2DR_DATA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2DR_DATA_SHIFT)) & I2C_I2DR_DATA_MASK) + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C1 base address */ +#define I2C1_BASE (0x21A0000u) +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_Type *)I2C1_BASE) +/** Peripheral I2C2 base address */ +#define I2C2_BASE (0x21A4000u) +/** Peripheral I2C2 base pointer */ +#define I2C2 ((I2C_Type *)I2C2_BASE) +/** Peripheral I2C3 base address */ +#define I2C3_BASE (0x21A8000u) +/** Peripheral I2C3 base pointer */ +#define I2C3 ((I2C_Type *)I2C3_BASE) +/** Peripheral I2C4 base address */ +#define I2C4_BASE (0x21F8000u) +/** Peripheral I2C4 base pointer */ +#define I2C4 ((I2C_Type *)I2C4_BASE) +/** Array initializer of I2C peripheral base addresses */ +#define I2C_BASE_ADDRS { 0u, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE } +/** Array initializer of I2C peripheral base pointers */ +#define I2C_BASE_PTRS { (I2C_Type *)0u, I2C1, I2C2, I2C3, I2C4 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { NotAvail_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[28]; + __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[28]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_3[28]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ + uint8_t RESERVED_4[8]; + __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_5[28]; + __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_6[28]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name TCSR - SAI Transmit Control Register */ +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) + +/*! @name TCR1 - SAI Transmit Configuration 1 Register */ +#define I2S_TCR1_TFW_MASK (0x1FU) +#define I2S_TCR1_TFW_SHIFT (0U) +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) + +/*! @name TCR2 - SAI Transmit Configuration 2 Register */ +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) + +/*! @name TCR3 - SAI Transmit Configuration 3 Register */ +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK (0x10000U) +#define I2S_TCR3_TCE_SHIFT (16U) +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) + +/*! @name TCR4 - SAI Transmit Configuration 4 Register */ +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) + +/*! @name TCR5 - SAI Transmit Configuration 5 Register */ +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) + +/*! @name TDR - SAI Transmit Data Register */ +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (1U) + +/*! @name TFR - SAI Transmit FIFO Register */ +#define I2S_TFR_RFP_MASK (0x3FU) +#define I2S_TFR_RFP_SHIFT (0U) +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK (0x3F0000U) +#define I2S_TFR_WFP_SHIFT (16U) +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (1U) + +/*! @name TMR - SAI Transmit Mask Register */ +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) + +/*! @name RCSR - SAI Receive Control Register */ +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) + +/*! @name RCR1 - SAI Receive Configuration 1 Register */ +#define I2S_RCR1_RFW_MASK (0x1FU) +#define I2S_RCR1_RFW_SHIFT (0U) +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) + +/*! @name RCR2 - SAI Receive Configuration 2 Register */ +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) + +/*! @name RCR3 - SAI Receive Configuration 3 Register */ +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK (0x10000U) +#define I2S_RCR3_RCE_SHIFT (16U) +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) + +/*! @name RCR4 - SAI Receive Configuration 4 Register */ +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) + +/*! @name RCR5 - SAI Receive Configuration 5 Register */ +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) + +/*! @name RDR - SAI Receive Data Register */ +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (1U) + +/*! @name RFR - SAI Receive FIFO Register */ +#define I2S_RFR_RFP_MASK (0x3FU) +#define I2S_RFR_RFP_SHIFT (0U) +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) +#define I2S_RFR_WFP_MASK (0x3F0000U) +#define I2S_RFR_WFP_SHIFT (16U) +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (1U) + +/*! @name RMR - SAI Receive Mask Register */ +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S1 base address */ +#define I2S1_BASE (0x2028000u) +/** Peripheral I2S1 base pointer */ +#define I2S1 ((I2S_Type *)I2S1_BASE) +/** Peripheral I2S2 base address */ +#define I2S2_BASE (0x202C000u) +/** Peripheral I2S2 base pointer */ +#define I2S2 ((I2S_Type *)I2S2_BASE) +/** Peripheral I2S3 base address */ +#define I2S3_BASE (0x2030000u) +/** Peripheral I2S3 base pointer */ +#define I2S3 ((I2S_Type *)I2S3_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { 0u, I2S1_BASE, I2S2_BASE, I2S3_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { (I2S_Type *)0u, I2S1, I2S2, I2S3 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer + * @{ + */ + +/** IOMUXC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[68]; + __IO uint32_t SW_MUX_CTL_PAD[112]; /**< SW_MUX_CTL_PAD_JTAG_MOD SW MUX Control Register..SW_MUX_CTL_PAD_CSI_DATA07 SW MUX Control Register, array offset: 0x44, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD_DDR[34]; /**< SW_PAD_CTL_PAD_DRAM_ADDR00 SW PAD Control Register..SW_PAD_CTL_PAD_DRAM_RESET SW PAD Control Register, array offset: 0x204, array step: 0x4 */ + uint8_t RESERVED_1[68]; + __IO uint32_t SW_PAD_CTL_PAD[112]; /**< SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register..SW_PAD_CTL_PAD_CSI_DATA07 SW PAD Control Register, array offset: 0x2D0, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_GRP[10]; /**< SW_PAD_CTL_GRP_ADDDS SW GRP Register..SW_PAD_CTL_GRP_DDR_TYPE SW GRP Register, array offset: 0x490, array step: 0x4 */ + __IO uint32_t SELECT_INPUT[122]; /**< USB_OTG1_ID_SELECT_INPUT DAISY Register..USDHC2_WP_SELECT_INPUT DAISY Register, array offset: 0x4B8, array step: 0x4 */ +} IOMUXC_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_JTAG_MOD SW MUX Control Register..SW_MUX_CTL_PAD_CSI_DATA07 SW MUX Control Register */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) +#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) + +/* The count of IOMUXC_SW_MUX_CTL_PAD */ +#define IOMUXC_SW_MUX_CTL_PAD_COUNT (112U) + +/*! @name SW_PAD_CTL_PAD_DDR - SW_PAD_CTL_PAD_DRAM_ADDR00 SW PAD Control Register..SW_PAD_CTL_PAD_DRAM_RESET SW PAD Control Register */ +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_SHIFT (3U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_MASK (0x700U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_SHIFT (8U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_ODT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_SHIFT (12U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_SHIFT (13U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_SHIFT (14U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_SHIFT (16U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_MASK (0x20000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_SHIFT (17U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_MASK (0xC0000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_SHIFT (18U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_MASK (0x300000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_SHIFT (20U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_MASK (0x3000000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_SHIFT (24U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_MASK) + +/* The count of IOMUXC_SW_PAD_CTL_PAD_DDR */ +#define IOMUXC_SW_PAD_CTL_PAD_DDR_COUNT (34U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register..SW_PAD_CTL_PAD_CSI_DATA07 SW PAD Control Register */ +#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +#define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) + +/* The count of IOMUXC_SW_PAD_CTL_PAD */ +#define IOMUXC_SW_PAD_CTL_PAD_COUNT (112U) + +/*! @name SW_PAD_CTL_GRP - SW_PAD_CTL_GRP_ADDDS SW GRP Register..SW_PAD_CTL_GRP_DDR_TYPE SW GRP Register */ +#define IOMUXC_SW_PAD_CTL_GRP_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_GRP_DSE_SHIFT (3U) +#define IOMUXC_SW_PAD_CTL_GRP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_GRP_PKE_SHIFT (12U) +#define IOMUXC_SW_PAD_CTL_GRP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_GRP_PUE_SHIFT (13U) +#define IOMUXC_SW_PAD_CTL_GRP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_GRP_HYS_SHIFT (16U) +#define IOMUXC_SW_PAD_CTL_GRP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_HYS_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_MASK (0x20000U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_SHIFT (17U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_MASK (0xC0000U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_SHIFT (18U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_MASK) + +/* The count of IOMUXC_SW_PAD_CTL_GRP */ +#define IOMUXC_SW_PAD_CTL_GRP_COUNT (10U) + +/*! @name SELECT_INPUT - USB_OTG1_ID_SELECT_INPUT DAISY Register..USDHC2_WP_SELECT_INPUT DAISY Register */ +#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) +#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ + +/* The count of IOMUXC_SELECT_INPUT */ +#define IOMUXC_SELECT_INPUT_COUNT (122U) + + +/*! + * @} + */ /* end of group IOMUXC_Register_Masks */ + + +/* IOMUXC - Peripheral instance base addresses */ +/** Peripheral IOMUXC base address */ +#define IOMUXC_BASE (0x20E0000u) +/** Peripheral IOMUXC base pointer */ +#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) +/** Array initializer of IOMUXC peripheral base addresses */ +#define IOMUXC_BASE_ADDRS { IOMUXC_BASE } +/** Array initializer of IOMUXC peripheral base pointers */ +#define IOMUXC_BASE_PTRS { IOMUXC } + +/*! + * @} + */ /* end of group IOMUXC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_GPR - Register Layout Typedef */ +typedef struct { + __IO uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + __IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + __IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ + __IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */ + __IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */ + uint8_t RESERVED_0[12]; + __I uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */ + __IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */ + uint8_t RESERVED_1[12]; + __IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */ +} IOMUXC_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/*! @name GPR0 - GPR0 General Purpose Register */ +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK (0x1U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT (0U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK (0x2U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT (1U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK (0x4U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT (2U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK (0x8U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT (3U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK (0x10U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT (4U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK (0x20U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT (5U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK (0x40U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT (6U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_MASK (0x80U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_SHIFT (7U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_MASK (0x100U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_SHIFT (8U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_MASK (0x200U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_SHIFT (9U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_MASK (0x400U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_SHIFT (10U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_MASK (0x800U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_SHIFT (11U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_MASK (0x1000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_SHIFT (12U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_MASK (0x2000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_SHIFT (13U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_MASK (0x4000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_SHIFT (14U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_MASK (0x8000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_SHIFT (15U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_MASK (0x10000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_SHIFT (16U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_MASK (0x20000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_SHIFT (17U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_MASK (0x40000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_SHIFT (18U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_MASK (0x80000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_SHIFT (19U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_MASK (0x100000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_SHIFT (20U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_MASK (0x200000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_SHIFT (21U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_MASK (0x400000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_SHIFT (22U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_MASK) + +/*! @name GPR1 - GPR1 General Purpose Register */ +#define IOMUXC_GPR_GPR1_ACT_CS0_MASK (0x1U) +#define IOMUXC_GPR_GPR1_ACT_CS0_SHIFT (0U) +#define IOMUXC_GPR_GPR1_ACT_CS0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS0_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS0_MASK) +#define IOMUXC_GPR_GPR1_ADDRS0_MASK (0x6U) +#define IOMUXC_GPR_GPR1_ADDRS0_SHIFT (1U) +#define IOMUXC_GPR_GPR1_ADDRS0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS0_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS0_MASK) +#define IOMUXC_GPR_GPR1_ACT_CS1_MASK (0x8U) +#define IOMUXC_GPR_GPR1_ACT_CS1_SHIFT (3U) +#define IOMUXC_GPR_GPR1_ACT_CS1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS1_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS1_MASK) +#define IOMUXC_GPR_GPR1_ADDRS1_MASK (0x30U) +#define IOMUXC_GPR_GPR1_ADDRS1_SHIFT (4U) +#define IOMUXC_GPR_GPR1_ADDRS1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS1_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS1_MASK) +#define IOMUXC_GPR_GPR1_ACT_CS2_MASK (0x40U) +#define IOMUXC_GPR_GPR1_ACT_CS2_SHIFT (6U) +#define IOMUXC_GPR_GPR1_ACT_CS2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS2_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS2_MASK) +#define IOMUXC_GPR_GPR1_ADDRS2_MASK (0x180U) +#define IOMUXC_GPR_GPR1_ADDRS2_SHIFT (7U) +#define IOMUXC_GPR_GPR1_ADDRS2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS2_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS2_MASK) +#define IOMUXC_GPR_GPR1_ACT_CS3_MASK (0x200U) +#define IOMUXC_GPR_GPR1_ACT_CS3_SHIFT (9U) +#define IOMUXC_GPR_GPR1_ACT_CS3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS3_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS3_MASK) +#define IOMUXC_GPR_GPR1_ADDRS3_MASK (0xC00U) +#define IOMUXC_GPR_GPR1_ADDRS3_SHIFT (10U) +#define IOMUXC_GPR_GPR1_ADDRS3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS3_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS3_MASK) +#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U) +#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U) +#define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK) +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK (0x4000U) +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT (14U) +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK) +#define IOMUXC_GPR_GPR1_ADD_DS_MASK (0x10000U) +#define IOMUXC_GPR_GPR1_ADD_DS_SHIFT (16U) +#define IOMUXC_GPR_GPR1_ADD_DS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADD_DS_SHIFT)) & IOMUXC_GPR_GPR1_ADD_DS_MASK) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK (0x40000U) +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT (18U) +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U) +#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U) +#define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK) +#define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_MASK (0x800000U) +#define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_SHIFT (23U) +#define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_MASK) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_MASK (0x1000000U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_SHIFT (24U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_MASK) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_MASK (0x2000000U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_SHIFT (25U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_SHIFT)) & IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_MASK) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_MASK (0x4000000U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_SHIFT (26U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_SHIFT)) & IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_MASK) + +/*! @name GPR2 - GPR2 General Purpose Register */ +#define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_MASK (0x1U) +#define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_SHIFT (0U) +#define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_MASK (0x2U) +#define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_SHIFT (1U) +#define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_MASK (0x4U) +#define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_SHIFT (2U) +#define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_MASK (0x8U) +#define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_SHIFT (3U) +#define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_MASK (0x10U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_SHIFT (4U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_MASK (0x20U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_SHIFT (5U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_MASK (0x40U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_SHIFT (6U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_MASK (0x80U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_SHIFT (7U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_MASK (0x100U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_SHIFT (8U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_MASK (0x200U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_SHIFT (9U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_MASK (0x400U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_SHIFT (10U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_MASK (0x800U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_SHIFT (11U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_MASK (0x2000U) +#define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_SHIFT (13U) +#define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_MASK (0x8000U) +#define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_SHIFT (15U) +#define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U) +#define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK) +#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U) +#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U) +#define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK) +#define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_MASK (0x8000000U) +#define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_SHIFT (27U) +#define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_MASK) +#define IOMUXC_GPR_GPR2_DRAM_RESET_MASK (0x10000000U) +#define IOMUXC_GPR_GPR2_DRAM_RESET_SHIFT (28U) +#define IOMUXC_GPR_GPR2_DRAM_RESET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_RESET_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_RESET_MASK) +#define IOMUXC_GPR_GPR2_DRAM_CKE0_MASK (0x20000000U) +#define IOMUXC_GPR_GPR2_DRAM_CKE0_SHIFT (29U) +#define IOMUXC_GPR_GPR2_DRAM_CKE0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_CKE0_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_CKE0_MASK) +#define IOMUXC_GPR_GPR2_DRAM_CKE1_MASK (0x40000000U) +#define IOMUXC_GPR_GPR2_DRAM_CKE1_SHIFT (30U) +#define IOMUXC_GPR_GPR2_DRAM_CKE1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_CKE1_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_CKE1_MASK) +#define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_MASK (0x80000000U) +#define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_SHIFT (31U) +#define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_MASK) + +/*! @name GPR3 - GPR3 General Purpose Register */ +#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU) +#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U) +#define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK) +#define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_MASK (0x2000U) +#define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_SHIFT (13U) +#define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_SHIFT)) & IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_MASK) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK) + +/*! @name GPR4 - GPR4 General Purpose Register */ +#define IOMUXC_GPR_GPR4_SDMA_STOP_REQ_MASK (0x1U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_REQ_SHIFT (0U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SDMA_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET1_STOP_REQ_MASK (0x8U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_REQ_SHIFT (3U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK (0x10U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT (4U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_SHIFT (8U) +#define IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_MASK) +#define IOMUXC_GPR_GPR4_SDMA_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_ACK_SHIFT (16U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SDMA_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ENET1_STOP_ACK_MASK (0x80000U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_ACK_SHIFT (19U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT (20U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ARM_WFI_MASK (0x40000000U) +#define IOMUXC_GPR_GPR4_ARM_WFI_SHIFT (30U) +#define IOMUXC_GPR_GPR4_ARM_WFI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ARM_WFI_SHIFT)) & IOMUXC_GPR_GPR4_ARM_WFI_MASK) +#define IOMUXC_GPR_GPR4_ARM_WFE_MASK (0x80000000U) +#define IOMUXC_GPR_GPR4_ARM_WFE_SHIFT (31U) +#define IOMUXC_GPR_GPR4_ARM_WFE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ARM_WFE_SHIFT)) & IOMUXC_GPR_GPR4_ARM_WFE_MASK) + +/*! @name GPR5 - GPR5 General Purpose Register */ +#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U) +#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U) +#define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U) +#define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_MASK (0x300U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_SHIFT (8U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_SHIFT)) & IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_MASK) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_MASK (0x3000U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_SHIFT (12U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_SHIFT)) & IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_MASK) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_MASK (0x30000U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_SHIFT (16U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_SHIFT)) & IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_MASK) +#define IOMUXC_GPR_GPR5_WDOG3_MASK_MASK (0x100000U) +#define IOMUXC_GPR_GPR5_WDOG3_MASK_SHIFT (20U) +#define IOMUXC_GPR_GPR5_WDOG3_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG3_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG3_MASK_MASK) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK) +#define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_MASK (0x2000000U) +#define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_SHIFT (25U) +#define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_MASK) +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK (0x4000000U) +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT (26U) +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_MASK (0x40000000U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_SHIFT (30U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_SHIFT)) & IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_MASK) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_MASK (0x80000000U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_SHIFT (31U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_SHIFT)) & IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_MASK) + +/*! @name GPR9 - GPR9 General Purpose Register */ +#define IOMUXC_GPR_GPR9_TZASC1_BYP_MASK (0x1U) +#define IOMUXC_GPR_GPR9_TZASC1_BYP_SHIFT (0U) +#define IOMUXC_GPR_GPR9_TZASC1_BYP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_TZASC1_BYP_SHIFT)) & IOMUXC_GPR_GPR9_TZASC1_BYP_MASK) + +/*! @name GPR10 - GPR10 General Purpose Register */ +#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x1U) +#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (0U) +#define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK) +#define IOMUXC_GPR_GPR10_DBG_CLK_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR10_DBG_CLK_EN_SHIFT (1U) +#define IOMUXC_GPR_GPR10_DBG_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_CLK_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_CLK_EN_MASK) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x400U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (10U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xF800U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (11U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK) + +/*! @name GPR14 - GPR14 General Purpose Register */ +#define IOMUXC_GPR_GPR14_GPR_MASK (0xFFFFFFFCU) +#define IOMUXC_GPR_GPR14_GPR_SHIFT (2U) +#define IOMUXC_GPR_GPR14_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_SHIFT)) & IOMUXC_GPR_GPR14_GPR_MASK) + + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Masks */ + + +/* IOMUXC_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_GPR base address */ +#define IOMUXC_GPR_BASE (0x20E4000u) +/** Peripheral IOMUXC_GPR base pointer */ +#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) +/** Array initializer of IOMUXC_GPR peripheral base addresses */ +#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } +/** Array initializer of IOMUXC_GPR peripheral base pointers */ +#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } + +/*! + * @} + */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer + * @{ + */ + +/** IOMUXC_SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t SW_MUX_CTL_PAD[12]; /**< SW_MUX_CTL_PAD_BOOT_MODE0 SW MUX Control Register..SW_MUX_CTL_PAD_SNVS_TAMPER9 SW MUX Control Register, array offset: 0x0, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD[17]; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register..SW_PAD_CTL_PAD_SNVS_TAMPER9 SW PAD Control Register, array offset: 0x30, array step: 0x4 */ +} IOMUXC_SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_BOOT_MODE0 SW MUX Control Register..SW_MUX_CTL_PAD_SNVS_TAMPER9 SW MUX Control Register */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_SHIFT (4U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_MASK) + +/* The count of IOMUXC_SNVS_SW_MUX_CTL_PAD */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_COUNT (12U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register..SW_PAD_CTL_PAD_SNVS_TAMPER9 SW PAD Control Register */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_MASK) + +/* The count of IOMUXC_SNVS_SW_PAD_CTL_PAD */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_COUNT (17U) + + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Register_Masks */ + + +/* IOMUXC_SNVS - Peripheral instance base addresses */ +/** Peripheral IOMUXC_SNVS base address */ +#define IOMUXC_SNVS_BASE (0x2290000u) +/** Peripheral IOMUXC_SNVS base pointer */ +#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE) +/** Array initializer of IOMUXC_SNVS peripheral base addresses */ +#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE } +/** Array initializer of IOMUXC_SNVS peripheral base pointers */ +#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS } + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- KPP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer + * @{ + */ + +/** KPP - Register Layout Typedef */ +typedef struct { + __IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */ + __IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */ + __IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */ + __IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */ +} KPP_Type; + +/* ---------------------------------------------------------------------------- + -- KPP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Masks KPP Register Masks + * @{ + */ + +/*! @name KPCR - Keypad Control Register */ +#define KPP_KPCR_KRE_MASK (0xFFU) +#define KPP_KPCR_KRE_SHIFT (0U) +#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) +#define KPP_KPCR_KCO_MASK (0xFF00U) +#define KPP_KPCR_KCO_SHIFT (8U) +#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) + +/*! @name KPSR - Keypad Status Register */ +#define KPP_KPSR_KPKD_MASK (0x1U) +#define KPP_KPSR_KPKD_SHIFT (0U) +#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) +#define KPP_KPSR_KPKR_MASK (0x2U) +#define KPP_KPSR_KPKR_SHIFT (1U) +#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) +#define KPP_KPSR_KDSC_MASK (0x4U) +#define KPP_KPSR_KDSC_SHIFT (2U) +#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) +#define KPP_KPSR_KRSS_MASK (0x8U) +#define KPP_KPSR_KRSS_SHIFT (3U) +#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) +#define KPP_KPSR_KDIE_MASK (0x100U) +#define KPP_KPSR_KDIE_SHIFT (8U) +#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) +#define KPP_KPSR_KRIE_MASK (0x200U) +#define KPP_KPSR_KRIE_SHIFT (9U) +#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) + +/*! @name KDDR - Keypad Data Direction Register */ +#define KPP_KDDR_KRDD_MASK (0xFFU) +#define KPP_KDDR_KRDD_SHIFT (0U) +#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) +#define KPP_KDDR_KCDD_MASK (0xFF00U) +#define KPP_KDDR_KCDD_SHIFT (8U) +#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) + +/*! @name KPDR - Keypad Data Register */ +#define KPP_KPDR_KRD_MASK (0xFFU) +#define KPP_KPDR_KRD_SHIFT (0U) +#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) +#define KPP_KPDR_KCD_MASK (0xFF00U) +#define KPP_KPDR_KCD_SHIFT (8U) +#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) + + +/*! + * @} + */ /* end of group KPP_Register_Masks */ + + +/* KPP - Peripheral instance base addresses */ +/** Peripheral KPP base address */ +#define KPP_BASE (0x20B8000u) +/** Peripheral KPP base pointer */ +#define KPP ((KPP_Type *)KPP_BASE) +/** Array initializer of KPP peripheral base addresses */ +#define KPP_BASE_ADDRS { KPP_BASE } +/** Array initializer of KPP peripheral base pointers */ +#define KPP_BASE_PTRS { KPP } +/** Interrupt vectors for the KPP peripheral type */ +#define KPP_IRQS { KPP_IRQn } + +/*! + * @} + */ /* end of group KPP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LCDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer + * @{ + */ + +/** LCDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< eLCDIF General Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< eLCDIF General Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< eLCDIF General Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< eLCDIF General Control Register, offset: 0xC */ + __IO uint32_t CTRL1; /**< eLCDIF General Control1 Register, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< eLCDIF General Control1 Register, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< eLCDIF General Control1 Register, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< eLCDIF General Control1 Register, offset: 0x1C */ + __IO uint32_t CTRL2; /**< eLCDIF General Control2 Register, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< eLCDIF General Control2 Register, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< eLCDIF General Control2 Register, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< eLCDIF General Control2 Register, offset: 0x2C */ + __IO uint32_t TRANSFER_COUNT; /**< eLCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t TIMING; /**< LCD Interface Timing Register, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t VDCTRL0; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ + __IO uint32_t VDCTRL0_SET; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ + __IO uint32_t VDCTRL0_CLR; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ + __IO uint32_t VDCTRL0_TOG; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ + __IO uint32_t VDCTRL1; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ + uint8_t RESERVED_4[12]; + __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ + uint8_t RESERVED_5[12]; + __IO uint32_t VDCTRL3; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ + uint8_t RESERVED_6[12]; + __IO uint32_t VDCTRL4; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ + uint8_t RESERVED_7[12]; + __IO uint32_t DVICTRL0; /**< Digital Video Interface Control0 Register, offset: 0xC0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t DVICTRL1; /**< Digital Video Interface Control1 Register, offset: 0xD0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t DVICTRL2; /**< Digital Video Interface Control2 Register, offset: 0xE0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t DVICTRL3; /**< Digital Video Interface Control3 Register, offset: 0xF0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t DVICTRL4; /**< Digital Video Interface Control4 Register, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CSC_COEFF0; /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CSC_COEFF1; /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CSC_COEFF2; /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CSC_COEFF3; /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CSC_COEFF4; /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CSC_OFFSET; /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CSC_LIMIT; /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */ + uint8_t RESERVED_19[12]; + __IO uint32_t DATA; /**< LCD Interface Data Register, offset: 0x180 */ + uint8_t RESERVED_20[12]; + __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ + uint8_t RESERVED_22[12]; + __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ + uint8_t RESERVED_23[76]; + __IO uint32_t THRES; /**< eLCDIF Threshold Register, offset: 0x200 */ + uint8_t RESERVED_24[12]; + __IO uint32_t AS_CTRL; /**< eLCDIF AS Buffer Control Register, offset: 0x210 */ + uint8_t RESERVED_25[12]; + __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x220 */ + uint8_t RESERVED_26[12]; + __IO uint32_t AS_NEXT_BUF; /**< , offset: 0x230 */ + uint8_t RESERVED_27[12]; + __IO uint32_t AS_CLRKEYLOW; /**< eLCDIF Overlay Color Key Low, offset: 0x240 */ + uint8_t RESERVED_28[12]; + __IO uint32_t AS_CLRKEYHIGH; /**< eLCDIF Overlay Color Key High, offset: 0x250 */ + uint8_t RESERVED_29[12]; + __IO uint32_t SYNC_DELAY; /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */ +} LCDIF_Type; + +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/*! @name CTRL - eLCDIF General Control Register */ +#define LCDIF_CTRL_RUN_MASK (0x1U) +#define LCDIF_CTRL_RUN_SHIFT (0U) +#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) +#define LCDIF_CTRL_MASTER_MASK (0x20U) +#define LCDIF_CTRL_MASTER_SHIFT (5U) +#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SELECT_SHIFT)) & LCDIF_CTRL_DATA_SELECT_MASK) +#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_VSYNC_MODE_MASK) +#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DVI_MODE_SHIFT)) & LCDIF_CTRL_DVI_MODE_MASK) +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_READ_WRITEB_SHIFT)) & LCDIF_CTRL_READ_WRITEB_MASK) +#define LCDIF_CTRL_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) +#define LCDIF_CTRL_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - eLCDIF General Control Register */ +#define LCDIF_CTRL_SET_RUN_MASK (0x1U) +#define LCDIF_CTRL_SET_RUN_SHIFT (0U) +#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) +#define LCDIF_CTRL_SET_MASTER_MASK (0x20U) +#define LCDIF_CTRL_SET_MASTER_SHIFT (5U) +#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_SET_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_SET_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SELECT_SHIFT)) & LCDIF_CTRL_SET_DATA_SELECT_MASK) +#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_SET_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_SET_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_SET_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_SET_VSYNC_MODE_MASK) +#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_SET_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_SET_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_SET_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DVI_MODE_SHIFT)) & LCDIF_CTRL_SET_DVI_MODE_MASK) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_SET_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_SET_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_SET_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_READ_WRITEB_SHIFT)) & LCDIF_CTRL_SET_READ_WRITEB_MASK) +#define LCDIF_CTRL_SET_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_SET_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_SET_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) +#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - eLCDIF General Control Register */ +#define LCDIF_CTRL_CLR_RUN_MASK (0x1U) +#define LCDIF_CTRL_CLR_RUN_SHIFT (0U) +#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) +#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) +#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) +#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_CLR_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_CLR_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SELECT_SHIFT)) & LCDIF_CTRL_CLR_DATA_SELECT_MASK) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_CLR_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_CLR_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_CLR_VSYNC_MODE_MASK) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_CLR_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_CLR_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_CLR_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DVI_MODE_SHIFT)) & LCDIF_CTRL_CLR_DVI_MODE_MASK) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_CLR_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_CLR_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_CLR_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_READ_WRITEB_SHIFT)) & LCDIF_CTRL_CLR_READ_WRITEB_MASK) +#define LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_CLR_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) +#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - eLCDIF General Control Register */ +#define LCDIF_CTRL_TOG_RUN_MASK (0x1U) +#define LCDIF_CTRL_TOG_RUN_SHIFT (0U) +#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) +#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) +#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) +#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_TOG_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_TOG_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SELECT_SHIFT)) & LCDIF_CTRL_TOG_DATA_SELECT_MASK) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_TOG_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_TOG_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_TOG_VSYNC_MODE_MASK) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_TOG_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_TOG_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_TOG_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DVI_MODE_SHIFT)) & LCDIF_CTRL_TOG_DVI_MODE_MASK) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_TOG_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_TOG_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_TOG_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_READ_WRITEB_SHIFT)) & LCDIF_CTRL_TOG_READ_WRITEB_MASK) +#define LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_TOG_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) +#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) + +/*! @name CTRL1 - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_RESET_MASK (0x1U) +#define LCDIF_CTRL1_RESET_SHIFT (0U) +#define LCDIF_CTRL1_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RESET_SHIFT)) & LCDIF_CTRL1_RESET_MASK) +#define LCDIF_CTRL1_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_MODE86_SHIFT)) & LCDIF_CTRL1_MODE86_MASK) +#define LCDIF_CTRL1_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD1_SHIFT)) & LCDIF_CTRL1_RSRVD1_MASK) + +/*! @name CTRL1_SET - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_SET_RESET_MASK (0x1U) +#define LCDIF_CTRL1_SET_RESET_SHIFT (0U) +#define LCDIF_CTRL1_SET_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RESET_SHIFT)) & LCDIF_CTRL1_SET_RESET_MASK) +#define LCDIF_CTRL1_SET_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_SET_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_SET_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_MODE86_SHIFT)) & LCDIF_CTRL1_SET_MODE86_MASK) +#define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_SET_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_SET_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_SET_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_SET_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD1_SHIFT)) & LCDIF_CTRL1_SET_RSRVD1_MASK) + +/*! @name CTRL1_CLR - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_CLR_RESET_MASK (0x1U) +#define LCDIF_CTRL1_CLR_RESET_SHIFT (0U) +#define LCDIF_CTRL1_CLR_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RESET_SHIFT)) & LCDIF_CTRL1_CLR_RESET_MASK) +#define LCDIF_CTRL1_CLR_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_CLR_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_CLR_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_MODE86_SHIFT)) & LCDIF_CTRL1_CLR_MODE86_MASK) +#define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_CLR_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_CLR_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_CLR_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD1_MASK) + +/*! @name CTRL1_TOG - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_TOG_RESET_MASK (0x1U) +#define LCDIF_CTRL1_TOG_RESET_SHIFT (0U) +#define LCDIF_CTRL1_TOG_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RESET_SHIFT)) & LCDIF_CTRL1_TOG_RESET_MASK) +#define LCDIF_CTRL1_TOG_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_TOG_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_TOG_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_MODE86_SHIFT)) & LCDIF_CTRL1_TOG_MODE86_MASK) +#define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_TOG_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_TOG_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_TOG_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD1_MASK) + +/*! @name CTRL2 - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD1_SHIFT)) & LCDIF_CTRL2_RSRVD1_MASK) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD2_SHIFT)) & LCDIF_CTRL2_RSRVD2_MASK) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) +#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) + +/*! @name CTRL2_SET - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_SET_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_SET_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_SET_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD1_SHIFT)) & LCDIF_CTRL2_SET_RSRVD1_MASK) +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_SET_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_SET_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_SET_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_SET_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD2_SHIFT)) & LCDIF_CTRL2_SET_RSRVD2_MASK) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) +#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) + +/*! @name CTRL2_CLR - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_CLR_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_CLR_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD1_MASK) +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_CLR_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_CLR_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_CLR_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD2_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD2_MASK) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) + +/*! @name CTRL2_TOG - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_TOG_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_TOG_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD1_MASK) +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_TOG_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_TOG_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_TOG_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD2_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD2_MASK) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) + +/*! @name TRANSFER_COUNT - eLCDIF Horizontal and Vertical Valid Data Count Register */ +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) +#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) +#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) +#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) +#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) + +/*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ +#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_CUR_BUF_ADDR_SHIFT (0U) +#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) + +/*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ +#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) +#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) + +/*! @name TIMING - LCD Interface Timing Register */ +#define LCDIF_TIMING_DATA_SETUP_MASK (0xFFU) +#define LCDIF_TIMING_DATA_SETUP_SHIFT (0U) +#define LCDIF_TIMING_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_SETUP_SHIFT)) & LCDIF_TIMING_DATA_SETUP_MASK) +#define LCDIF_TIMING_DATA_HOLD_MASK (0xFF00U) +#define LCDIF_TIMING_DATA_HOLD_SHIFT (8U) +#define LCDIF_TIMING_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_HOLD_SHIFT)) & LCDIF_TIMING_DATA_HOLD_MASK) +#define LCDIF_TIMING_CMD_SETUP_MASK (0xFF0000U) +#define LCDIF_TIMING_CMD_SETUP_SHIFT (16U) +#define LCDIF_TIMING_CMD_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_SETUP_SHIFT)) & LCDIF_TIMING_CMD_SETUP_MASK) +#define LCDIF_TIMING_CMD_HOLD_MASK (0xFF000000U) +#define LCDIF_TIMING_CMD_HOLD_SHIFT (24U) +#define LCDIF_TIMING_CMD_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_HOLD_SHIFT)) & LCDIF_TIMING_CMD_HOLD_MASK) + +/*! @name VDCTRL0 - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) +#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) + +/*! @name VDCTRL0_SET - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) + +/*! @name VDCTRL0_CLR - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) + +/*! @name VDCTRL0_TOG - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) + +/*! @name VDCTRL1 - eLCDIF VSYNC Mode and Dotclk Mode Control Register1 */ +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) +#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) + +/*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) +#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) + +/*! @name VDCTRL3 - eLCDIF VSYNC Mode and Dotclk Mode Control Register3 */ +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) +#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) +#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) +#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) +#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) +#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) + +/*! @name VDCTRL4 - eLCDIF VSYNC Mode and Dotclk Mode Control Register4 */ +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) +#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) +#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) +#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) + +/*! @name DVICTRL0 - Digital Video Interface Control0 Register */ +#define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK (0xFFFU) +#define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT (0U) +#define LCDIF_DVICTRL0_H_BLANKING_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT)) & LCDIF_DVICTRL0_H_BLANKING_CNT_MASK) +#define LCDIF_DVICTRL0_RSRVD0_MASK (0xF000U) +#define LCDIF_DVICTRL0_RSRVD0_SHIFT (12U) +#define LCDIF_DVICTRL0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD0_SHIFT)) & LCDIF_DVICTRL0_RSRVD0_MASK) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK (0xFFF0000U) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT (16U) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT)) & LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK) +#define LCDIF_DVICTRL0_RSRVD1_MASK (0xF0000000U) +#define LCDIF_DVICTRL0_RSRVD1_SHIFT (28U) +#define LCDIF_DVICTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD1_SHIFT)) & LCDIF_DVICTRL0_RSRVD1_MASK) + +/*! @name DVICTRL1 - Digital Video Interface Control1 Register */ +#define LCDIF_DVICTRL1_F2_START_LINE_MASK (0x3FFU) +#define LCDIF_DVICTRL1_F2_START_LINE_SHIFT (0U) +#define LCDIF_DVICTRL1_F2_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F2_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F2_START_LINE_MASK) +#define LCDIF_DVICTRL1_F1_END_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL1_F1_END_LINE_SHIFT (10U) +#define LCDIF_DVICTRL1_F1_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_END_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_END_LINE_MASK) +#define LCDIF_DVICTRL1_F1_START_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL1_F1_START_LINE_SHIFT (20U) +#define LCDIF_DVICTRL1_F1_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_START_LINE_MASK) +#define LCDIF_DVICTRL1_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL1_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_RSRVD0_SHIFT)) & LCDIF_DVICTRL1_RSRVD0_MASK) + +/*! @name DVICTRL2 - Digital Video Interface Control2 Register */ +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK (0x3FFU) +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT (0U) +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT (10U) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK) +#define LCDIF_DVICTRL2_F2_END_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL2_F2_END_LINE_SHIFT (20U) +#define LCDIF_DVICTRL2_F2_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_F2_END_LINE_SHIFT)) & LCDIF_DVICTRL2_F2_END_LINE_MASK) +#define LCDIF_DVICTRL2_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL2_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_RSRVD0_SHIFT)) & LCDIF_DVICTRL2_RSRVD0_MASK) + +/*! @name DVICTRL3 - Digital Video Interface Control3 Register */ +#define LCDIF_DVICTRL3_V_LINES_CNT_MASK (0x3FFU) +#define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT (0U) +#define LCDIF_DVICTRL3_V_LINES_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V_LINES_CNT_SHIFT)) & LCDIF_DVICTRL3_V_LINES_CNT_MASK) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT (10U) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT (20U) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK) +#define LCDIF_DVICTRL3_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL3_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_RSRVD0_SHIFT)) & LCDIF_DVICTRL3_RSRVD0_MASK) + +/*! @name DVICTRL4 - Digital Video Interface Control4 Register */ +#define LCDIF_DVICTRL4_H_FILL_CNT_MASK (0xFFU) +#define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT (0U) +#define LCDIF_DVICTRL4_H_FILL_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_H_FILL_CNT_SHIFT)) & LCDIF_DVICTRL4_H_FILL_CNT_MASK) +#define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK (0xFF00U) +#define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT (8U) +#define LCDIF_DVICTRL4_CR_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CR_FILL_VALUE_MASK) +#define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK (0xFF0000U) +#define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT (16U) +#define LCDIF_DVICTRL4_CB_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CB_FILL_VALUE_MASK) +#define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK (0xFF000000U) +#define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT (24U) +#define LCDIF_DVICTRL4_Y_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_Y_FILL_VALUE_MASK) + +/*! @name CSC_COEFF0 - RGB to YCbCr 4:2:2 CSC Coefficient0 Register */ +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK (0x3U) +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT (0U) +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT)) & LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK) +#define LCDIF_CSC_COEFF0_RSRVD0_MASK (0xFFFCU) +#define LCDIF_CSC_COEFF0_RSRVD0_SHIFT (2U) +#define LCDIF_CSC_COEFF0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD0_MASK) +#define LCDIF_CSC_COEFF0_C0_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF0_C0_SHIFT (16U) +#define LCDIF_CSC_COEFF0_C0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_C0_SHIFT)) & LCDIF_CSC_COEFF0_C0_MASK) +#define LCDIF_CSC_COEFF0_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF0_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD1_MASK) + +/*! @name CSC_COEFF1 - RGB to YCbCr 4:2:2 CSC Coefficient1 Register */ +#define LCDIF_CSC_COEFF1_C1_MASK (0x3FFU) +#define LCDIF_CSC_COEFF1_C1_SHIFT (0U) +#define LCDIF_CSC_COEFF1_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C1_SHIFT)) & LCDIF_CSC_COEFF1_C1_MASK) +#define LCDIF_CSC_COEFF1_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF1_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD0_MASK) +#define LCDIF_CSC_COEFF1_C2_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF1_C2_SHIFT (16U) +#define LCDIF_CSC_COEFF1_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C2_SHIFT)) & LCDIF_CSC_COEFF1_C2_MASK) +#define LCDIF_CSC_COEFF1_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF1_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF1_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD1_MASK) + +/*! @name CSC_COEFF2 - RGB to YCbCr 4:2:2 CSC Coefficent2 Register */ +#define LCDIF_CSC_COEFF2_C3_MASK (0x3FFU) +#define LCDIF_CSC_COEFF2_C3_SHIFT (0U) +#define LCDIF_CSC_COEFF2_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C3_SHIFT)) & LCDIF_CSC_COEFF2_C3_MASK) +#define LCDIF_CSC_COEFF2_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF2_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD0_MASK) +#define LCDIF_CSC_COEFF2_C4_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF2_C4_SHIFT (16U) +#define LCDIF_CSC_COEFF2_C4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C4_SHIFT)) & LCDIF_CSC_COEFF2_C4_MASK) +#define LCDIF_CSC_COEFF2_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF2_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD1_MASK) + +/*! @name CSC_COEFF3 - RGB to YCbCr 4:2:2 CSC Coefficient3 Register */ +#define LCDIF_CSC_COEFF3_C5_MASK (0x3FFU) +#define LCDIF_CSC_COEFF3_C5_SHIFT (0U) +#define LCDIF_CSC_COEFF3_C5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C5_SHIFT)) & LCDIF_CSC_COEFF3_C5_MASK) +#define LCDIF_CSC_COEFF3_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF3_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD0_MASK) +#define LCDIF_CSC_COEFF3_C6_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF3_C6_SHIFT (16U) +#define LCDIF_CSC_COEFF3_C6(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C6_SHIFT)) & LCDIF_CSC_COEFF3_C6_MASK) +#define LCDIF_CSC_COEFF3_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF3_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF3_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD1_MASK) + +/*! @name CSC_COEFF4 - RGB to YCbCr 4:2:2 CSC Coefficient4 Register */ +#define LCDIF_CSC_COEFF4_C7_MASK (0x3FFU) +#define LCDIF_CSC_COEFF4_C7_SHIFT (0U) +#define LCDIF_CSC_COEFF4_C7(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C7_SHIFT)) & LCDIF_CSC_COEFF4_C7_MASK) +#define LCDIF_CSC_COEFF4_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF4_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD0_MASK) +#define LCDIF_CSC_COEFF4_C8_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF4_C8_SHIFT (16U) +#define LCDIF_CSC_COEFF4_C8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C8_SHIFT)) & LCDIF_CSC_COEFF4_C8_MASK) +#define LCDIF_CSC_COEFF4_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF4_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF4_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD1_MASK) + +/*! @name CSC_OFFSET - RGB to YCbCr 4:2:2 CSC Offset Register */ +#define LCDIF_CSC_OFFSET_Y_OFFSET_MASK (0x1FFU) +#define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT (0U) +#define LCDIF_CSC_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_Y_OFFSET_MASK) +#define LCDIF_CSC_OFFSET_RSRVD0_MASK (0xFE00U) +#define LCDIF_CSC_OFFSET_RSRVD0_SHIFT (9U) +#define LCDIF_CSC_OFFSET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD0_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD0_MASK) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK (0x1FF0000U) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT (16U) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK) +#define LCDIF_CSC_OFFSET_RSRVD1_MASK (0xFE000000U) +#define LCDIF_CSC_OFFSET_RSRVD1_SHIFT (25U) +#define LCDIF_CSC_OFFSET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD1_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD1_MASK) + +/*! @name CSC_LIMIT - RGB to YCbCr 4:2:2 CSC Limit Register */ +#define LCDIF_CSC_LIMIT_Y_MAX_MASK (0xFFU) +#define LCDIF_CSC_LIMIT_Y_MAX_SHIFT (0U) +#define LCDIF_CSC_LIMIT_Y_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MAX_SHIFT)) & LCDIF_CSC_LIMIT_Y_MAX_MASK) +#define LCDIF_CSC_LIMIT_Y_MIN_MASK (0xFF00U) +#define LCDIF_CSC_LIMIT_Y_MIN_SHIFT (8U) +#define LCDIF_CSC_LIMIT_Y_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MIN_SHIFT)) & LCDIF_CSC_LIMIT_Y_MIN_MASK) +#define LCDIF_CSC_LIMIT_CBCR_MAX_MASK (0xFF0000U) +#define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT (16U) +#define LCDIF_CSC_LIMIT_CBCR_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MAX_MASK) +#define LCDIF_CSC_LIMIT_CBCR_MIN_MASK (0xFF000000U) +#define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT (24U) +#define LCDIF_CSC_LIMIT_CBCR_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MIN_MASK) + +/*! @name DATA - LCD Interface Data Register */ +#define LCDIF_DATA_DATA_ZERO_MASK (0xFFU) +#define LCDIF_DATA_DATA_ZERO_SHIFT (0U) +#define LCDIF_DATA_DATA_ZERO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ZERO_SHIFT)) & LCDIF_DATA_DATA_ZERO_MASK) +#define LCDIF_DATA_DATA_ONE_MASK (0xFF00U) +#define LCDIF_DATA_DATA_ONE_SHIFT (8U) +#define LCDIF_DATA_DATA_ONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ONE_SHIFT)) & LCDIF_DATA_DATA_ONE_MASK) +#define LCDIF_DATA_DATA_TWO_MASK (0xFF0000U) +#define LCDIF_DATA_DATA_TWO_SHIFT (16U) +#define LCDIF_DATA_DATA_TWO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_TWO_SHIFT)) & LCDIF_DATA_DATA_TWO_MASK) +#define LCDIF_DATA_DATA_THREE_MASK (0xFF000000U) +#define LCDIF_DATA_DATA_THREE_SHIFT (24U) +#define LCDIF_DATA_DATA_THREE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_THREE_SHIFT)) & LCDIF_DATA_DATA_THREE_MASK) + +/*! @name BM_ERROR_STAT - Bus Master Error Status Register */ +#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) +#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) + +/*! @name CRC_STAT - CRC Status Register */ +#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) +#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) +#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) + +/*! @name STAT - LCD Interface Status Register */ +#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) +#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) +#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) +#define LCDIF_STAT_RSRVD0_MASK (0xFFFE00U) +#define LCDIF_STAT_RSRVD0_SHIFT (9U) +#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) +#define LCDIF_STAT_DVI_CURRENT_FIELD_MASK (0x1000000U) +#define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT (24U) +#define LCDIF_STAT_DVI_CURRENT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT)) & LCDIF_STAT_DVI_CURRENT_FIELD_MASK) +#define LCDIF_STAT_BUSY_MASK (0x2000000U) +#define LCDIF_STAT_BUSY_SHIFT (25U) +#define LCDIF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_BUSY_SHIFT)) & LCDIF_STAT_BUSY_MASK) +#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) +#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) +#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) +#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) +#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) +#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) +#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) +#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) +#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) +#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) +#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) +#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) +#define LCDIF_STAT_PRESENT_MASK (0x80000000U) +#define LCDIF_STAT_PRESENT_SHIFT (31U) +#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) + +/*! @name THRES - eLCDIF Threshold Register */ +#define LCDIF_THRES_PANIC_MASK (0x1FFU) +#define LCDIF_THRES_PANIC_SHIFT (0U) +#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) +#define LCDIF_THRES_RSRVD1_MASK (0xFE00U) +#define LCDIF_THRES_RSRVD1_SHIFT (9U) +#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) +#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U) +#define LCDIF_THRES_FASTCLOCK_SHIFT (16U) +#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) +#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) +#define LCDIF_THRES_RSRVD2_SHIFT (25U) +#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) + +/*! @name AS_CTRL - eLCDIF AS Buffer Control Register */ +#define LCDIF_AS_CTRL_AS_ENABLE_MASK (0x1U) +#define LCDIF_AS_CTRL_AS_ENABLE_SHIFT (0U) +#define LCDIF_AS_CTRL_AS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_AS_ENABLE_SHIFT)) & LCDIF_AS_CTRL_AS_ENABLE_MASK) +#define LCDIF_AS_CTRL_ALPHA_CTRL_MASK (0x6U) +#define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT (1U) +#define LCDIF_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT)) & LCDIF_AS_CTRL_ALPHA_CTRL_MASK) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK) +#define LCDIF_AS_CTRL_FORMAT_MASK (0xF0U) +#define LCDIF_AS_CTRL_FORMAT_SHIFT (4U) +#define LCDIF_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_FORMAT_SHIFT)) & LCDIF_AS_CTRL_FORMAT_MASK) +#define LCDIF_AS_CTRL_ALPHA_MASK (0xFF00U) +#define LCDIF_AS_CTRL_ALPHA_SHIFT (8U) +#define LCDIF_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_SHIFT)) & LCDIF_AS_CTRL_ALPHA_MASK) +#define LCDIF_AS_CTRL_ROP_MASK (0xF0000U) +#define LCDIF_AS_CTRL_ROP_SHIFT (16U) +#define LCDIF_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ROP_SHIFT)) & LCDIF_AS_CTRL_ROP_MASK) +#define LCDIF_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) +#define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT (20U) +#define LCDIF_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT)) & LCDIF_AS_CTRL_ALPHA_INVERT_MASK) +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK (0x600000U) +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT (21U) +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_AS_CTRL_PS_DISABLE_MASK (0x800000U) +#define LCDIF_AS_CTRL_PS_DISABLE_SHIFT (23U) +#define LCDIF_AS_CTRL_PS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_PS_DISABLE_SHIFT)) & LCDIF_AS_CTRL_PS_DISABLE_MASK) +#define LCDIF_AS_CTRL_RVDS1_MASK (0x7000000U) +#define LCDIF_AS_CTRL_RVDS1_SHIFT (24U) +#define LCDIF_AS_CTRL_RVDS1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_RVDS1_SHIFT)) & LCDIF_AS_CTRL_RVDS1_MASK) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK (0x8000000U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT (27U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK (0x10000000U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT (28U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK (0x20000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT (29U) +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK) +#define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK (0x40000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT (30U) +#define LCDIF_AS_CTRL_CSI_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK) +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK (0x80000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT (31U) +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK) + +/*! @name AS_BUF - Alpha Surface Buffer Pointer */ +#define LCDIF_AS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_AS_BUF_ADDR_SHIFT (0U) +#define LCDIF_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_BUF_ADDR_SHIFT)) & LCDIF_AS_BUF_ADDR_MASK) + +/*! @name AS_NEXT_BUF - */ +#define LCDIF_AS_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_AS_NEXT_BUF_ADDR_SHIFT (0U) +#define LCDIF_AS_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_NEXT_BUF_ADDR_SHIFT)) & LCDIF_AS_NEXT_BUF_ADDR_MASK) + +/*! @name AS_CLRKEYLOW - eLCDIF Overlay Color Key Low */ +#define LCDIF_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) +#define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT (0U) +#define LCDIF_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYLOW_PIXEL_MASK) +#define LCDIF_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) +#define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT (24U) +#define LCDIF_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYLOW_RSVD1_MASK) + +/*! @name AS_CLRKEYHIGH - eLCDIF Overlay Color Key High */ +#define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) +#define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) +#define LCDIF_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYHIGH_PIXEL_MASK) +#define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) +#define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) +#define LCDIF_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYHIGH_RSVD1_MASK) + +/*! @name SYNC_DELAY - LCD working insync mode with CSI for VSYNC delay */ +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK (0xFFFFU) +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT (0U) +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK (0xFFFF0000U) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT (16U) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK) + + +/*! + * @} + */ /* end of group LCDIF_Register_Masks */ + + +/* LCDIF - Peripheral instance base addresses */ +/** Peripheral LCDIF base address */ +#define LCDIF_BASE (0x21C8000u) +/** Peripheral LCDIF base pointer */ +#define LCDIF ((LCDIF_Type *)LCDIF_BASE) +/** Array initializer of LCDIF peripheral base addresses */ +#define LCDIF_BASE_ADDRS { LCDIF_BASE } +/** Array initializer of LCDIF peripheral base pointers */ +#define LCDIF_BASE_PTRS { LCDIF } + +/*! + * @} + */ /* end of group LCDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MMDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MMDC_Peripheral_Access_Layer MMDC Peripheral Access Layer + * @{ + */ + +/** MMDC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MDCTL; /**< MMDC Core Control Register, offset: 0x0 */ + __IO uint32_t MDPDC; /**< MMDC Core Power Down Control Register, offset: 0x4 */ + __IO uint32_t MDOTC; /**< MMDC Core ODT Timing Control Register, offset: 0x8 */ + __IO uint32_t MDCFG0; /**< MMDC Core Timing Configuration Register 0, offset: 0xC */ + __IO uint32_t MDCFG1; /**< MMDC Core Timing Configuration Register 1, offset: 0x10 */ + __IO uint32_t MDCFG2; /**< MMDC Core Timing Configuration Register 2, offset: 0x14 */ + __IO uint32_t MDMISC; /**< MMDC Core Miscellaneous Register, offset: 0x18 */ + __IO uint32_t MDSCR; /**< MMDC Core Special Command Register, offset: 0x1C */ + __IO uint32_t MDREF; /**< MMDC Core Refresh Control Register, offset: 0x20 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MDRWD; /**< MMDC Core Read/Write Command Delay Register, offset: 0x2C */ + __IO uint32_t MDOR; /**< MMDC Core Out of Reset Delays Register, offset: 0x30 */ + __I uint32_t MDMRR; /**< MMDC Core MRR Data Register, offset: 0x34 */ + __IO uint32_t MDCFG3LP; /**< MMDC Core Timing Configuration Register 3, offset: 0x38 */ + __IO uint32_t MDMR4; /**< MMDC Core MR4 Derating Register, offset: 0x3C */ + __IO uint32_t MDASP; /**< MMDC Core Address Space Partition Register, offset: 0x40 */ + uint8_t RESERVED_1[956]; + __IO uint32_t MAARCR; /**< MMDC Core AXI Reordering Control Register, offset: 0x400 */ + __IO uint32_t MAPSR; /**< MMDC Core Power Saving Control and Status Register, offset: 0x404 */ + __IO uint32_t MAEXIDR0; /**< MMDC Core Exclusive ID Monitor Register0, offset: 0x408 */ + __IO uint32_t MAEXIDR1; /**< MMDC Core Exclusive ID Monitor Register1, offset: 0x40C */ + __IO uint32_t MADPCR0; /**< MMDC Core Debug and Profiling Control Register 0, offset: 0x410 */ + __IO uint32_t MADPCR1; /**< MMDC Core Debug and Profiling Control Register 1, offset: 0x414 */ + __I uint32_t MADPSR0; /**< MMDC Core Debug and Profiling Status Register 0, offset: 0x418 */ + __I uint32_t MADPSR1; /**< MMDC Core Debug and Profiling Status Register 1, offset: 0x41C */ + __I uint32_t MADPSR2; /**< MMDC Core Debug and Profiling Status Register 2, offset: 0x420 */ + __I uint32_t MADPSR3; /**< MMDC Core Debug and Profiling Status Register 3, offset: 0x424 */ + __I uint32_t MADPSR4; /**< MMDC Core Debug and Profiling Status Register 4, offset: 0x428 */ + __I uint32_t MADPSR5; /**< MMDC Core Debug and Profiling Status Register 5, offset: 0x42C */ + __I uint32_t MASBS0; /**< MMDC Core Step By Step Address Register, offset: 0x430 */ + __I uint32_t MASBS1; /**< MMDC Core Step By Step Address Attributes Register, offset: 0x434 */ + uint8_t RESERVED_2[8]; + __IO uint32_t MAGENP; /**< MMDC Core General Purpose Register, offset: 0x440 */ + uint8_t RESERVED_3[956]; + __IO uint32_t MPZQHWCTRL; /**< MMDC PHY ZQ HW control register, offset: 0x800 */ + __IO uint32_t MPZQSWCTRL; /**< MMDC PHY ZQ SW control register, offset: 0x804 */ + __IO uint32_t MPWLGCR; /**< MMDC PHY Write Leveling Configuration and Error Status Register, offset: 0x808 */ + __IO uint32_t MPWLDECTRL0; /**< MMDC PHY Write Leveling Delay Control Register 0, offset: 0x80C */ + __IO uint32_t MPWLDECTRL1; /**< MMDC PHY Write Leveling Delay Control Register 1, offset: 0x810 */ + __I uint32_t MPWLDLST; /**< MMDC PHY Write Leveling delay-line Status Register, offset: 0x814 */ + __IO uint32_t MPODTCTRL; /**< MMDC PHY ODT control register, offset: 0x818 */ + __IO uint32_t MPRDDQBY0DL; /**< MMDC PHY Read DQ Byte0 Delay Register, offset: 0x81C */ + __IO uint32_t MPRDDQBY1DL; /**< MMDC PHY Read DQ Byte1 Delay Register, offset: 0x820 */ + uint8_t RESERVED_4[8]; + __IO uint32_t MPWRDQBY0DL; /**< MMDC PHY Write DQ Byte0 Delay Register, offset: 0x82C */ + __IO uint32_t MPWRDQBY1DL; /**< MMDC PHY Write DQ Byte1 Delay Register, offset: 0x830 */ + __IO uint32_t MPWRDQBY2DL; /**< MMDC PHY Write DQ Byte2 Delay Register, offset: 0x834 */ + __IO uint32_t MPWRDQBY3DL; /**< MMDC PHY Write DQ Byte3 Delay Register, offset: 0x838 */ + __IO uint32_t MPDGCTRL0; /**< MMDC PHY Read DQS Gating Control Register 0, offset: 0x83C */ + uint8_t RESERVED_5[4]; + __I uint32_t MPDGDLST0; /**< MMDC PHY Read DQS Gating delay-line Status Register, offset: 0x844 */ + __IO uint32_t MPRDDLCTL; /**< MMDC PHY Read delay-lines Configuration Register, offset: 0x848 */ + __I uint32_t MPRDDLST; /**< MMDC PHY Read delay-lines Status Register, offset: 0x84C */ + __IO uint32_t MPWRDLCTL; /**< MMDC PHY Write delay-lines Configuration Register, offset: 0x850 */ + __I uint32_t MPWRDLST; /**< MMDC PHY Write delay-lines Status Register, offset: 0x854 */ + __IO uint32_t MPSDCTRL; /**< MMDC PHY CK Control Register, offset: 0x858 */ + __IO uint32_t MPZQLP2CTL; /**< MMDC ZQ LPDDR2 HW Control Register, offset: 0x85C */ + __IO uint32_t MPRDDLHWCTL; /**< MMDC PHY Read Delay HW Calibration Control Register, offset: 0x860 */ + __IO uint32_t MPWRDLHWCTL; /**< MMDC PHY Write Delay HW Calibration Control Register, offset: 0x864 */ + __I uint32_t MPRDDLHWST0; /**< MMDC PHY Read Delay HW Calibration Status Register 0, offset: 0x868 */ + uint8_t RESERVED_6[4]; + __I uint32_t MPWRDLHWST0; /**< MMDC PHY Write Delay HW Calibration Status Register 0, offset: 0x870 */ + uint8_t RESERVED_7[4]; + __I uint32_t MPWLHWERR; /**< MMDC PHY Write Leveling HW Error Register, offset: 0x878 */ + __I uint32_t MPDGHWST0; /**< MMDC PHY Read DQS Gating HW Status Register 0, offset: 0x87C */ + __I uint32_t MPDGHWST1; /**< MMDC PHY Read DQS Gating HW Status Register 1, offset: 0x880 */ + uint8_t RESERVED_8[8]; + __IO uint32_t MPPDCMPR1; /**< MMDC PHY Pre-defined Compare Register 1, offset: 0x88C */ + __IO uint32_t MPPDCMPR2; /**< MMDC PHY Pre-defined Compare and CA delay-line Configuration Register, offset: 0x890 */ + __IO uint32_t MPSWDAR0; /**< MMDC PHY SW Dummy Access Register, offset: 0x894 */ + __I uint32_t MPSWDRDR0; /**< MMDC PHY SW Dummy Read Data Register 0, offset: 0x898 */ + __I uint32_t MPSWDRDR1; /**< MMDC PHY SW Dummy Read Data Register 1, offset: 0x89C */ + __I uint32_t MPSWDRDR2; /**< MMDC PHY SW Dummy Read Data Register 2, offset: 0x8A0 */ + __I uint32_t MPSWDRDR3; /**< MMDC PHY SW Dummy Read Data Register 3, offset: 0x8A4 */ + __I uint32_t MPSWDRDR4; /**< MMDC PHY SW Dummy Read Data Register 4, offset: 0x8A8 */ + __I uint32_t MPSWDRDR5; /**< MMDC PHY SW Dummy Read Data Register 5, offset: 0x8AC */ + __I uint32_t MPSWDRDR6; /**< MMDC PHY SW Dummy Read Data Register 6, offset: 0x8B0 */ + __I uint32_t MPSWDRDR7; /**< MMDC PHY SW Dummy Read Data Register 7, offset: 0x8B4 */ + __IO uint32_t MPMUR0; /**< MMDC PHY Measure Unit Register, offset: 0x8B8 */ + __IO uint32_t MPWRCADL; /**< MMDC Write CA delay-line controller, offset: 0x8BC */ + __IO uint32_t MPDCCR; /**< MMDC Duty Cycle Control Register, offset: 0x8C0 */ +} MMDC_Type; + +/* ---------------------------------------------------------------------------- + -- MMDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MMDC_Register_Masks MMDC Register Masks + * @{ + */ + +/*! @name MDCTL - MMDC Core Control Register */ +#define MMDC_MDCTL_DSIZ_MASK (0x30000U) +#define MMDC_MDCTL_DSIZ_SHIFT (16U) +#define MMDC_MDCTL_DSIZ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_DSIZ_SHIFT)) & MMDC_MDCTL_DSIZ_MASK) +#define MMDC_MDCTL_BL_MASK (0x80000U) +#define MMDC_MDCTL_BL_SHIFT (19U) +#define MMDC_MDCTL_BL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_BL_SHIFT)) & MMDC_MDCTL_BL_MASK) +#define MMDC_MDCTL_COL_MASK (0x700000U) +#define MMDC_MDCTL_COL_SHIFT (20U) +#define MMDC_MDCTL_COL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_COL_SHIFT)) & MMDC_MDCTL_COL_MASK) +#define MMDC_MDCTL_ROW_MASK (0x7000000U) +#define MMDC_MDCTL_ROW_SHIFT (24U) +#define MMDC_MDCTL_ROW(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_ROW_SHIFT)) & MMDC_MDCTL_ROW_MASK) +#define MMDC_MDCTL_SDE_1_MASK (0x40000000U) +#define MMDC_MDCTL_SDE_1_SHIFT (30U) +#define MMDC_MDCTL_SDE_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_SDE_1_SHIFT)) & MMDC_MDCTL_SDE_1_MASK) +#define MMDC_MDCTL_SDE_0_MASK (0x80000000U) +#define MMDC_MDCTL_SDE_0_SHIFT (31U) +#define MMDC_MDCTL_SDE_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_SDE_0_SHIFT)) & MMDC_MDCTL_SDE_0_MASK) + +/*! @name MDPDC - MMDC Core Power Down Control Register */ +#define MMDC_MDPDC_TCKSRE_MASK (0x7U) +#define MMDC_MDPDC_TCKSRE_SHIFT (0U) +#define MMDC_MDPDC_TCKSRE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_TCKSRE_SHIFT)) & MMDC_MDPDC_TCKSRE_MASK) +#define MMDC_MDPDC_TCKSRX_MASK (0x38U) +#define MMDC_MDPDC_TCKSRX_SHIFT (3U) +#define MMDC_MDPDC_TCKSRX(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_TCKSRX_SHIFT)) & MMDC_MDPDC_TCKSRX_MASK) +#define MMDC_MDPDC_BOTH_CS_PD_MASK (0x40U) +#define MMDC_MDPDC_BOTH_CS_PD_SHIFT (6U) +#define MMDC_MDPDC_BOTH_CS_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_BOTH_CS_PD_SHIFT)) & MMDC_MDPDC_BOTH_CS_PD_MASK) +#define MMDC_MDPDC_SLOW_PD_MASK (0x80U) +#define MMDC_MDPDC_SLOW_PD_SHIFT (7U) +#define MMDC_MDPDC_SLOW_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_SLOW_PD_SHIFT)) & MMDC_MDPDC_SLOW_PD_MASK) +#define MMDC_MDPDC_PWDT_0_MASK (0xF00U) +#define MMDC_MDPDC_PWDT_0_SHIFT (8U) +#define MMDC_MDPDC_PWDT_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PWDT_0_SHIFT)) & MMDC_MDPDC_PWDT_0_MASK) +#define MMDC_MDPDC_PWDT_1_MASK (0xF000U) +#define MMDC_MDPDC_PWDT_1_SHIFT (12U) +#define MMDC_MDPDC_PWDT_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PWDT_1_SHIFT)) & MMDC_MDPDC_PWDT_1_MASK) +#define MMDC_MDPDC_TCKE_MASK (0x70000U) +#define MMDC_MDPDC_TCKE_SHIFT (16U) +#define MMDC_MDPDC_TCKE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_TCKE_SHIFT)) & MMDC_MDPDC_TCKE_MASK) +#define MMDC_MDPDC_PRCT_0_MASK (0x7000000U) +#define MMDC_MDPDC_PRCT_0_SHIFT (24U) +#define MMDC_MDPDC_PRCT_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PRCT_0_SHIFT)) & MMDC_MDPDC_PRCT_0_MASK) +#define MMDC_MDPDC_PRCT_1_MASK (0x70000000U) +#define MMDC_MDPDC_PRCT_1_SHIFT (28U) +#define MMDC_MDPDC_PRCT_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PRCT_1_SHIFT)) & MMDC_MDPDC_PRCT_1_MASK) + +/*! @name MDOTC - MMDC Core ODT Timing Control Register */ +#define MMDC_MDOTC_TODT_IDLE_OFF_MASK (0x1F0U) +#define MMDC_MDOTC_TODT_IDLE_OFF_SHIFT (4U) +#define MMDC_MDOTC_TODT_IDLE_OFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TODT_IDLE_OFF_SHIFT)) & MMDC_MDOTC_TODT_IDLE_OFF_MASK) +#define MMDC_MDOTC_TODTLON_MASK (0x7000U) +#define MMDC_MDOTC_TODTLON_SHIFT (12U) +#define MMDC_MDOTC_TODTLON(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TODTLON_SHIFT)) & MMDC_MDOTC_TODTLON_MASK) +#define MMDC_MDOTC_TAXPD_MASK (0xF0000U) +#define MMDC_MDOTC_TAXPD_SHIFT (16U) +#define MMDC_MDOTC_TAXPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TAXPD_SHIFT)) & MMDC_MDOTC_TAXPD_MASK) +#define MMDC_MDOTC_TANPD_MASK (0xF00000U) +#define MMDC_MDOTC_TANPD_SHIFT (20U) +#define MMDC_MDOTC_TANPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TANPD_SHIFT)) & MMDC_MDOTC_TANPD_MASK) +#define MMDC_MDOTC_TAONPD_MASK (0x7000000U) +#define MMDC_MDOTC_TAONPD_SHIFT (24U) +#define MMDC_MDOTC_TAONPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TAONPD_SHIFT)) & MMDC_MDOTC_TAONPD_MASK) +#define MMDC_MDOTC_TAOFPD_MASK (0x38000000U) +#define MMDC_MDOTC_TAOFPD_SHIFT (27U) +#define MMDC_MDOTC_TAOFPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TAOFPD_SHIFT)) & MMDC_MDOTC_TAOFPD_MASK) + +/*! @name MDCFG0 - MMDC Core Timing Configuration Register 0 */ +#define MMDC_MDCFG0_TCL_MASK (0xFU) +#define MMDC_MDCFG0_TCL_SHIFT (0U) +#define MMDC_MDCFG0_TCL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TCL_SHIFT)) & MMDC_MDCFG0_TCL_MASK) +#define MMDC_MDCFG0_TFAW_MASK (0x1F0U) +#define MMDC_MDCFG0_TFAW_SHIFT (4U) +#define MMDC_MDCFG0_TFAW(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TFAW_SHIFT)) & MMDC_MDCFG0_TFAW_MASK) +#define MMDC_MDCFG0_TXPDLL_MASK (0x1E00U) +#define MMDC_MDCFG0_TXPDLL_SHIFT (9U) +#define MMDC_MDCFG0_TXPDLL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TXPDLL_SHIFT)) & MMDC_MDCFG0_TXPDLL_MASK) +#define MMDC_MDCFG0_TXP_MASK (0xE000U) +#define MMDC_MDCFG0_TXP_SHIFT (13U) +#define MMDC_MDCFG0_TXP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TXP_SHIFT)) & MMDC_MDCFG0_TXP_MASK) +#define MMDC_MDCFG0_TXS_MASK (0xFF0000U) +#define MMDC_MDCFG0_TXS_SHIFT (16U) +#define MMDC_MDCFG0_TXS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TXS_SHIFT)) & MMDC_MDCFG0_TXS_MASK) +#define MMDC_MDCFG0_TRFC_MASK (0xFF000000U) +#define MMDC_MDCFG0_TRFC_SHIFT (24U) +#define MMDC_MDCFG0_TRFC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TRFC_SHIFT)) & MMDC_MDCFG0_TRFC_MASK) + +/*! @name MDCFG1 - MMDC Core Timing Configuration Register 1 */ +#define MMDC_MDCFG1_TCWL_MASK (0x7U) +#define MMDC_MDCFG1_TCWL_SHIFT (0U) +#define MMDC_MDCFG1_TCWL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TCWL_SHIFT)) & MMDC_MDCFG1_TCWL_MASK) +#define MMDC_MDCFG1_TMRD_MASK (0x1E0U) +#define MMDC_MDCFG1_TMRD_SHIFT (5U) +#define MMDC_MDCFG1_TMRD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TMRD_SHIFT)) & MMDC_MDCFG1_TMRD_MASK) +#define MMDC_MDCFG1_TWR_MASK (0xE00U) +#define MMDC_MDCFG1_TWR_SHIFT (9U) +#define MMDC_MDCFG1_TWR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TWR_SHIFT)) & MMDC_MDCFG1_TWR_MASK) +#define MMDC_MDCFG1_TRPA_MASK (0x8000U) +#define MMDC_MDCFG1_TRPA_SHIFT (15U) +#define MMDC_MDCFG1_TRPA(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRPA_SHIFT)) & MMDC_MDCFG1_TRPA_MASK) +#define MMDC_MDCFG1_TRAS_MASK (0x1F0000U) +#define MMDC_MDCFG1_TRAS_SHIFT (16U) +#define MMDC_MDCFG1_TRAS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRAS_SHIFT)) & MMDC_MDCFG1_TRAS_MASK) +#define MMDC_MDCFG1_TRC_MASK (0x3E00000U) +#define MMDC_MDCFG1_TRC_SHIFT (21U) +#define MMDC_MDCFG1_TRC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRC_SHIFT)) & MMDC_MDCFG1_TRC_MASK) +#define MMDC_MDCFG1_TRP_MASK (0x1C000000U) +#define MMDC_MDCFG1_TRP_SHIFT (26U) +#define MMDC_MDCFG1_TRP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRP_SHIFT)) & MMDC_MDCFG1_TRP_MASK) +#define MMDC_MDCFG1_TRCD_MASK (0xE0000000U) +#define MMDC_MDCFG1_TRCD_SHIFT (29U) +#define MMDC_MDCFG1_TRCD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRCD_SHIFT)) & MMDC_MDCFG1_TRCD_MASK) + +/*! @name MDCFG2 - MMDC Core Timing Configuration Register 2 */ +#define MMDC_MDCFG2_TRRD_MASK (0x7U) +#define MMDC_MDCFG2_TRRD_SHIFT (0U) +#define MMDC_MDCFG2_TRRD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TRRD_SHIFT)) & MMDC_MDCFG2_TRRD_MASK) +#define MMDC_MDCFG2_TWTR_MASK (0x38U) +#define MMDC_MDCFG2_TWTR_SHIFT (3U) +#define MMDC_MDCFG2_TWTR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TWTR_SHIFT)) & MMDC_MDCFG2_TWTR_MASK) +#define MMDC_MDCFG2_TRTP_MASK (0x1C0U) +#define MMDC_MDCFG2_TRTP_SHIFT (6U) +#define MMDC_MDCFG2_TRTP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TRTP_SHIFT)) & MMDC_MDCFG2_TRTP_MASK) +#define MMDC_MDCFG2_TDLLK_MASK (0x1FF0000U) +#define MMDC_MDCFG2_TDLLK_SHIFT (16U) +#define MMDC_MDCFG2_TDLLK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TDLLK_SHIFT)) & MMDC_MDCFG2_TDLLK_MASK) + +/*! @name MDMISC - MMDC Core Miscellaneous Register */ +#define MMDC_MDMISC_RST_MASK (0x2U) +#define MMDC_MDMISC_RST_SHIFT (1U) +#define MMDC_MDMISC_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_RST_SHIFT)) & MMDC_MDMISC_RST_MASK) +#define MMDC_MDMISC_DDR_TYPE_MASK (0x18U) +#define MMDC_MDMISC_DDR_TYPE_SHIFT (3U) +#define MMDC_MDMISC_DDR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_DDR_TYPE_SHIFT)) & MMDC_MDMISC_DDR_TYPE_MASK) +#define MMDC_MDMISC_DDR_4_BANK_MASK (0x20U) +#define MMDC_MDMISC_DDR_4_BANK_SHIFT (5U) +#define MMDC_MDMISC_DDR_4_BANK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_DDR_4_BANK_SHIFT)) & MMDC_MDMISC_DDR_4_BANK_MASK) +#define MMDC_MDMISC_RALAT_MASK (0x1C0U) +#define MMDC_MDMISC_RALAT_SHIFT (6U) +#define MMDC_MDMISC_RALAT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_RALAT_SHIFT)) & MMDC_MDMISC_RALAT_MASK) +#define MMDC_MDMISC_MIF3_MODE_MASK (0x600U) +#define MMDC_MDMISC_MIF3_MODE_SHIFT (9U) +#define MMDC_MDMISC_MIF3_MODE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_MIF3_MODE_SHIFT)) & MMDC_MDMISC_MIF3_MODE_MASK) +#define MMDC_MDMISC_LPDDR2_S2_MASK (0x800U) +#define MMDC_MDMISC_LPDDR2_S2_SHIFT (11U) +#define MMDC_MDMISC_LPDDR2_S2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_LPDDR2_S2_SHIFT)) & MMDC_MDMISC_LPDDR2_S2_MASK) +#define MMDC_MDMISC_BI_ON_MASK (0x1000U) +#define MMDC_MDMISC_BI_ON_SHIFT (12U) +#define MMDC_MDMISC_BI_ON(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_BI_ON_SHIFT)) & MMDC_MDMISC_BI_ON_MASK) +#define MMDC_MDMISC_WALAT_MASK (0x30000U) +#define MMDC_MDMISC_WALAT_SHIFT (16U) +#define MMDC_MDMISC_WALAT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_WALAT_SHIFT)) & MMDC_MDMISC_WALAT_MASK) +#define MMDC_MDMISC_LHD_MASK (0x40000U) +#define MMDC_MDMISC_LHD_SHIFT (18U) +#define MMDC_MDMISC_LHD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_LHD_SHIFT)) & MMDC_MDMISC_LHD_MASK) +#define MMDC_MDMISC_ADDR_MIRROR_MASK (0x80000U) +#define MMDC_MDMISC_ADDR_MIRROR_SHIFT (19U) +#define MMDC_MDMISC_ADDR_MIRROR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_ADDR_MIRROR_SHIFT)) & MMDC_MDMISC_ADDR_MIRROR_MASK) +#define MMDC_MDMISC_CALIB_PER_CS_MASK (0x100000U) +#define MMDC_MDMISC_CALIB_PER_CS_SHIFT (20U) +#define MMDC_MDMISC_CALIB_PER_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CALIB_PER_CS_SHIFT)) & MMDC_MDMISC_CALIB_PER_CS_MASK) +#define MMDC_MDMISC_CK1_GATING_MASK (0x200000U) +#define MMDC_MDMISC_CK1_GATING_SHIFT (21U) +#define MMDC_MDMISC_CK1_GATING(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CK1_GATING_SHIFT)) & MMDC_MDMISC_CK1_GATING_MASK) +#define MMDC_MDMISC_CS1_RDY_MASK (0x40000000U) +#define MMDC_MDMISC_CS1_RDY_SHIFT (30U) +#define MMDC_MDMISC_CS1_RDY(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CS1_RDY_SHIFT)) & MMDC_MDMISC_CS1_RDY_MASK) +#define MMDC_MDMISC_CS0_RDY_MASK (0x80000000U) +#define MMDC_MDMISC_CS0_RDY_SHIFT (31U) +#define MMDC_MDMISC_CS0_RDY(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CS0_RDY_SHIFT)) & MMDC_MDMISC_CS0_RDY_MASK) + +/*! @name MDSCR - MMDC Core Special Command Register */ +#define MMDC_MDSCR_CMD_BA_MASK (0x7U) +#define MMDC_MDSCR_CMD_BA_SHIFT (0U) +#define MMDC_MDSCR_CMD_BA(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_BA_SHIFT)) & MMDC_MDSCR_CMD_BA_MASK) +#define MMDC_MDSCR_CMD_CS_MASK (0x8U) +#define MMDC_MDSCR_CMD_CS_SHIFT (3U) +#define MMDC_MDSCR_CMD_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_CS_SHIFT)) & MMDC_MDSCR_CMD_CS_MASK) +#define MMDC_MDSCR_CMD_MASK (0x70U) +#define MMDC_MDSCR_CMD_SHIFT (4U) +#define MMDC_MDSCR_CMD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_SHIFT)) & MMDC_MDSCR_CMD_MASK) +#define MMDC_MDSCR_WL_EN_MASK (0x200U) +#define MMDC_MDSCR_WL_EN_SHIFT (9U) +#define MMDC_MDSCR_WL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_WL_EN_SHIFT)) & MMDC_MDSCR_WL_EN_MASK) +#define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK (0x400U) +#define MMDC_MDSCR_MRR_READ_DATA_VALID_SHIFT (10U) +#define MMDC_MDSCR_MRR_READ_DATA_VALID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_MRR_READ_DATA_VALID_SHIFT)) & MMDC_MDSCR_MRR_READ_DATA_VALID_MASK) +#define MMDC_MDSCR_CON_ACK_MASK (0x4000U) +#define MMDC_MDSCR_CON_ACK_SHIFT (14U) +#define MMDC_MDSCR_CON_ACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CON_ACK_SHIFT)) & MMDC_MDSCR_CON_ACK_MASK) +#define MMDC_MDSCR_CON_REQ_MASK (0x8000U) +#define MMDC_MDSCR_CON_REQ_SHIFT (15U) +#define MMDC_MDSCR_CON_REQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CON_REQ_SHIFT)) & MMDC_MDSCR_CON_REQ_MASK) +#define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_MASK (0xFF0000U) +#define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_SHIFT (16U) +#define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_SHIFT)) & MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_MASK) +#define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_MASK (0xFF000000U) +#define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_SHIFT (24U) +#define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_SHIFT)) & MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_MASK) + +/*! @name MDREF - MMDC Core Refresh Control Register */ +#define MMDC_MDREF_START_REF_MASK (0x1U) +#define MMDC_MDREF_START_REF_SHIFT (0U) +#define MMDC_MDREF_START_REF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_START_REF_SHIFT)) & MMDC_MDREF_START_REF_MASK) +#define MMDC_MDREF_REFR_MASK (0x3800U) +#define MMDC_MDREF_REFR_SHIFT (11U) +#define MMDC_MDREF_REFR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REFR_SHIFT)) & MMDC_MDREF_REFR_MASK) +#define MMDC_MDREF_REF_SEL_MASK (0xC000U) +#define MMDC_MDREF_REF_SEL_SHIFT (14U) +#define MMDC_MDREF_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REF_SEL_SHIFT)) & MMDC_MDREF_REF_SEL_MASK) +#define MMDC_MDREF_REF_CNT_MASK (0xFFFF0000U) +#define MMDC_MDREF_REF_CNT_SHIFT (16U) +#define MMDC_MDREF_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REF_CNT_SHIFT)) & MMDC_MDREF_REF_CNT_MASK) + +/*! @name MDRWD - MMDC Core Read/Write Command Delay Register */ +#define MMDC_MDRWD_RTR_DIFF_MASK (0x7U) +#define MMDC_MDRWD_RTR_DIFF_SHIFT (0U) +#define MMDC_MDRWD_RTR_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTR_DIFF_SHIFT)) & MMDC_MDRWD_RTR_DIFF_MASK) +#define MMDC_MDRWD_RTW_DIFF_MASK (0x38U) +#define MMDC_MDRWD_RTW_DIFF_SHIFT (3U) +#define MMDC_MDRWD_RTW_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTW_DIFF_SHIFT)) & MMDC_MDRWD_RTW_DIFF_MASK) +#define MMDC_MDRWD_WTW_DIFF_MASK (0x1C0U) +#define MMDC_MDRWD_WTW_DIFF_SHIFT (6U) +#define MMDC_MDRWD_WTW_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_WTW_DIFF_SHIFT)) & MMDC_MDRWD_WTW_DIFF_MASK) +#define MMDC_MDRWD_WTR_DIFF_MASK (0xE00U) +#define MMDC_MDRWD_WTR_DIFF_SHIFT (9U) +#define MMDC_MDRWD_WTR_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_WTR_DIFF_SHIFT)) & MMDC_MDRWD_WTR_DIFF_MASK) +#define MMDC_MDRWD_RTW_SAME_MASK (0x7000U) +#define MMDC_MDRWD_RTW_SAME_SHIFT (12U) +#define MMDC_MDRWD_RTW_SAME(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTW_SAME_SHIFT)) & MMDC_MDRWD_RTW_SAME_MASK) +#define MMDC_MDRWD_TDAI_MASK (0x1FFF0000U) +#define MMDC_MDRWD_TDAI_SHIFT (16U) +#define MMDC_MDRWD_TDAI(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_TDAI_SHIFT)) & MMDC_MDRWD_TDAI_MASK) + +/*! @name MDOR - MMDC Core Out of Reset Delays Register */ +#define MMDC_MDOR_RST_TO_CKE_MASK (0x3FU) +#define MMDC_MDOR_RST_TO_CKE_SHIFT (0U) +#define MMDC_MDOR_RST_TO_CKE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_RST_TO_CKE_SHIFT)) & MMDC_MDOR_RST_TO_CKE_MASK) +#define MMDC_MDOR_SDE_TO_RST_MASK (0x3F00U) +#define MMDC_MDOR_SDE_TO_RST_SHIFT (8U) +#define MMDC_MDOR_SDE_TO_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_SDE_TO_RST_SHIFT)) & MMDC_MDOR_SDE_TO_RST_MASK) +#define MMDC_MDOR_TXPR_MASK (0xFF0000U) +#define MMDC_MDOR_TXPR_SHIFT (16U) +#define MMDC_MDOR_TXPR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_TXPR_SHIFT)) & MMDC_MDOR_TXPR_MASK) + +/*! @name MDMRR - MMDC Core MRR Data Register */ +#define MMDC_MDMRR_MRR_READ_DATA0_MASK (0xFFU) +#define MMDC_MDMRR_MRR_READ_DATA0_SHIFT (0U) +#define MMDC_MDMRR_MRR_READ_DATA0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMRR_MRR_READ_DATA0_SHIFT)) & MMDC_MDMRR_MRR_READ_DATA0_MASK) +#define MMDC_MDMRR_MRR_READ_DATA1_MASK (0xFF00U) +#define MMDC_MDMRR_MRR_READ_DATA1_SHIFT (8U) +#define MMDC_MDMRR_MRR_READ_DATA1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMRR_MRR_READ_DATA1_SHIFT)) & MMDC_MDMRR_MRR_READ_DATA1_MASK) + +/*! @name MDCFG3LP - MMDC Core Timing Configuration Register 3 */ +#define MMDC_MDCFG3LP_TRPAB_LP_MASK (0xFU) +#define MMDC_MDCFG3LP_TRPAB_LP_SHIFT (0U) +#define MMDC_MDCFG3LP_TRPAB_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_TRPAB_LP_SHIFT)) & MMDC_MDCFG3LP_TRPAB_LP_MASK) +#define MMDC_MDCFG3LP_TRPPB_LP_MASK (0xF0U) +#define MMDC_MDCFG3LP_TRPPB_LP_SHIFT (4U) +#define MMDC_MDCFG3LP_TRPPB_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_TRPPB_LP_SHIFT)) & MMDC_MDCFG3LP_TRPPB_LP_MASK) +#define MMDC_MDCFG3LP_TRCD_LP_MASK (0xF00U) +#define MMDC_MDCFG3LP_TRCD_LP_SHIFT (8U) +#define MMDC_MDCFG3LP_TRCD_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_TRCD_LP_SHIFT)) & MMDC_MDCFG3LP_TRCD_LP_MASK) +#define MMDC_MDCFG3LP_RC_LP_MASK (0x3F0000U) +#define MMDC_MDCFG3LP_RC_LP_SHIFT (16U) +#define MMDC_MDCFG3LP_RC_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_RC_LP_SHIFT)) & MMDC_MDCFG3LP_RC_LP_MASK) + +/*! @name MDMR4 - MMDC Core MR4 Derating Register */ +#define MMDC_MDMR4_UPDATE_DE_REQ_MASK (0x1U) +#define MMDC_MDMR4_UPDATE_DE_REQ_SHIFT (0U) +#define MMDC_MDMR4_UPDATE_DE_REQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_UPDATE_DE_REQ_SHIFT)) & MMDC_MDMR4_UPDATE_DE_REQ_MASK) +#define MMDC_MDMR4_UPDATE_DE_ACK_MASK (0x2U) +#define MMDC_MDMR4_UPDATE_DE_ACK_SHIFT (1U) +#define MMDC_MDMR4_UPDATE_DE_ACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_UPDATE_DE_ACK_SHIFT)) & MMDC_MDMR4_UPDATE_DE_ACK_MASK) +#define MMDC_MDMR4_TRCD_DE_MASK (0x10U) +#define MMDC_MDMR4_TRCD_DE_SHIFT (4U) +#define MMDC_MDMR4_TRCD_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRCD_DE_SHIFT)) & MMDC_MDMR4_TRCD_DE_MASK) +#define MMDC_MDMR4_TRC_DE_MASK (0x20U) +#define MMDC_MDMR4_TRC_DE_SHIFT (5U) +#define MMDC_MDMR4_TRC_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRC_DE_SHIFT)) & MMDC_MDMR4_TRC_DE_MASK) +#define MMDC_MDMR4_TRAS_DE_MASK (0x40U) +#define MMDC_MDMR4_TRAS_DE_SHIFT (6U) +#define MMDC_MDMR4_TRAS_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRAS_DE_SHIFT)) & MMDC_MDMR4_TRAS_DE_MASK) +#define MMDC_MDMR4_TRP_DE_MASK (0x80U) +#define MMDC_MDMR4_TRP_DE_SHIFT (7U) +#define MMDC_MDMR4_TRP_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRP_DE_SHIFT)) & MMDC_MDMR4_TRP_DE_MASK) +#define MMDC_MDMR4_TRRD_DE_MASK (0x100U) +#define MMDC_MDMR4_TRRD_DE_SHIFT (8U) +#define MMDC_MDMR4_TRRD_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRRD_DE_SHIFT)) & MMDC_MDMR4_TRRD_DE_MASK) + +/*! @name MDASP - MMDC Core Address Space Partition Register */ +#define MMDC_MDASP_CS0_END_MASK (0x7FU) +#define MMDC_MDASP_CS0_END_SHIFT (0U) +#define MMDC_MDASP_CS0_END(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDASP_CS0_END_SHIFT)) & MMDC_MDASP_CS0_END_MASK) + +/*! @name MAARCR - MMDC Core AXI Reordering Control Register */ +#define MMDC_MAARCR_ARCR_GUARD_MASK (0xFU) +#define MMDC_MAARCR_ARCR_GUARD_SHIFT (0U) +#define MMDC_MAARCR_ARCR_GUARD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_GUARD_SHIFT)) & MMDC_MAARCR_ARCR_GUARD_MASK) +#define MMDC_MAARCR_ARCR_DYN_MAX_MASK (0xF0U) +#define MMDC_MAARCR_ARCR_DYN_MAX_SHIFT (4U) +#define MMDC_MAARCR_ARCR_DYN_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_DYN_MAX_SHIFT)) & MMDC_MAARCR_ARCR_DYN_MAX_MASK) +#define MMDC_MAARCR_ARCR_DYN_JMP_MASK (0xF00U) +#define MMDC_MAARCR_ARCR_DYN_JMP_SHIFT (8U) +#define MMDC_MAARCR_ARCR_DYN_JMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_DYN_JMP_SHIFT)) & MMDC_MAARCR_ARCR_DYN_JMP_MASK) +#define MMDC_MAARCR_ARCR_ACC_HIT_MASK (0x70000U) +#define MMDC_MAARCR_ARCR_ACC_HIT_SHIFT (16U) +#define MMDC_MAARCR_ARCR_ACC_HIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_ACC_HIT_SHIFT)) & MMDC_MAARCR_ARCR_ACC_HIT_MASK) +#define MMDC_MAARCR_ARCR_PAG_HIT_MASK (0x700000U) +#define MMDC_MAARCR_ARCR_PAG_HIT_SHIFT (20U) +#define MMDC_MAARCR_ARCR_PAG_HIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_PAG_HIT_SHIFT)) & MMDC_MAARCR_ARCR_PAG_HIT_MASK) +#define MMDC_MAARCR_ARCR_RCH_EN_MASK (0x1000000U) +#define MMDC_MAARCR_ARCR_RCH_EN_SHIFT (24U) +#define MMDC_MAARCR_ARCR_RCH_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_RCH_EN_SHIFT)) & MMDC_MAARCR_ARCR_RCH_EN_MASK) +#define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK (0x10000000U) +#define MMDC_MAARCR_ARCR_EXC_ERR_EN_SHIFT (28U) +#define MMDC_MAARCR_ARCR_EXC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_EXC_ERR_EN_SHIFT)) & MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK) +#define MMDC_MAARCR_ARCR_SEC_ERR_EN_MASK (0x40000000U) +#define MMDC_MAARCR_ARCR_SEC_ERR_EN_SHIFT (30U) +#define MMDC_MAARCR_ARCR_SEC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_SEC_ERR_EN_SHIFT)) & MMDC_MAARCR_ARCR_SEC_ERR_EN_MASK) +#define MMDC_MAARCR_ARCR_SEC_ERR_LOCK_MASK (0x80000000U) +#define MMDC_MAARCR_ARCR_SEC_ERR_LOCK_SHIFT (31U) +#define MMDC_MAARCR_ARCR_SEC_ERR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_SEC_ERR_LOCK_SHIFT)) & MMDC_MAARCR_ARCR_SEC_ERR_LOCK_MASK) + +/*! @name MAPSR - MMDC Core Power Saving Control and Status Register */ +#define MMDC_MAPSR_PSD_MASK (0x1U) +#define MMDC_MAPSR_PSD_SHIFT (0U) +#define MMDC_MAPSR_PSD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PSD_SHIFT)) & MMDC_MAPSR_PSD_MASK) +#define MMDC_MAPSR_PSS_MASK (0x10U) +#define MMDC_MAPSR_PSS_SHIFT (4U) +#define MMDC_MAPSR_PSS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PSS_SHIFT)) & MMDC_MAPSR_PSS_MASK) +#define MMDC_MAPSR_RIS_MASK (0x20U) +#define MMDC_MAPSR_RIS_SHIFT (5U) +#define MMDC_MAPSR_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_RIS_SHIFT)) & MMDC_MAPSR_RIS_MASK) +#define MMDC_MAPSR_WIS_MASK (0x40U) +#define MMDC_MAPSR_WIS_SHIFT (6U) +#define MMDC_MAPSR_WIS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_WIS_SHIFT)) & MMDC_MAPSR_WIS_MASK) +#define MMDC_MAPSR_PST_MASK (0xFF00U) +#define MMDC_MAPSR_PST_SHIFT (8U) +#define MMDC_MAPSR_PST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PST_SHIFT)) & MMDC_MAPSR_PST_MASK) +#define MMDC_MAPSR_LPMD_MASK (0x100000U) +#define MMDC_MAPSR_LPMD_SHIFT (20U) +#define MMDC_MAPSR_LPMD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_LPMD_SHIFT)) & MMDC_MAPSR_LPMD_MASK) +#define MMDC_MAPSR_DVFS_MASK (0x200000U) +#define MMDC_MAPSR_DVFS_SHIFT (21U) +#define MMDC_MAPSR_DVFS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_DVFS_SHIFT)) & MMDC_MAPSR_DVFS_MASK) +#define MMDC_MAPSR_LPACK_MASK (0x1000000U) +#define MMDC_MAPSR_LPACK_SHIFT (24U) +#define MMDC_MAPSR_LPACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_LPACK_SHIFT)) & MMDC_MAPSR_LPACK_MASK) +#define MMDC_MAPSR_DVACK_MASK (0x2000000U) +#define MMDC_MAPSR_DVACK_SHIFT (25U) +#define MMDC_MAPSR_DVACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_DVACK_SHIFT)) & MMDC_MAPSR_DVACK_MASK) + +/*! @name MAEXIDR0 - MMDC Core Exclusive ID Monitor Register0 */ +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK (0xFFFFU) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_SHIFT (0U) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR0_EXC_ID_MONITOR0_SHIFT)) & MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK (0xFFFF0000U) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_SHIFT (16U) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR0_EXC_ID_MONITOR1_SHIFT)) & MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK) + +/*! @name MAEXIDR1 - MMDC Core Exclusive ID Monitor Register1 */ +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK (0xFFFFU) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_SHIFT (0U) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR1_EXC_ID_MONITOR2_SHIFT)) & MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK (0xFFFF0000U) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_SHIFT (16U) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR1_EXC_ID_MONITOR3_SHIFT)) & MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK) + +/*! @name MADPCR0 - MMDC Core Debug and Profiling Control Register 0 */ +#define MMDC_MADPCR0_DBG_EN_MASK (0x1U) +#define MMDC_MADPCR0_DBG_EN_SHIFT (0U) +#define MMDC_MADPCR0_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_DBG_EN_SHIFT)) & MMDC_MADPCR0_DBG_EN_MASK) +#define MMDC_MADPCR0_DBG_RST_MASK (0x2U) +#define MMDC_MADPCR0_DBG_RST_SHIFT (1U) +#define MMDC_MADPCR0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_DBG_RST_SHIFT)) & MMDC_MADPCR0_DBG_RST_MASK) +#define MMDC_MADPCR0_PRF_FRZ_MASK (0x4U) +#define MMDC_MADPCR0_PRF_FRZ_SHIFT (2U) +#define MMDC_MADPCR0_PRF_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_PRF_FRZ_SHIFT)) & MMDC_MADPCR0_PRF_FRZ_MASK) +#define MMDC_MADPCR0_CYC_OVF_MASK (0x8U) +#define MMDC_MADPCR0_CYC_OVF_SHIFT (3U) +#define MMDC_MADPCR0_CYC_OVF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_CYC_OVF_SHIFT)) & MMDC_MADPCR0_CYC_OVF_MASK) +#define MMDC_MADPCR0_SBS_EN_MASK (0x100U) +#define MMDC_MADPCR0_SBS_EN_SHIFT (8U) +#define MMDC_MADPCR0_SBS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_SBS_EN_SHIFT)) & MMDC_MADPCR0_SBS_EN_MASK) +#define MMDC_MADPCR0_SBS_MASK (0x200U) +#define MMDC_MADPCR0_SBS_SHIFT (9U) +#define MMDC_MADPCR0_SBS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_SBS_SHIFT)) & MMDC_MADPCR0_SBS_MASK) + +/*! @name MADPCR1 - MMDC Core Debug and Profiling Control Register 1 */ +#define MMDC_MADPCR1_PRF_AXI_ID_MASK (0xFFFFU) +#define MMDC_MADPCR1_PRF_AXI_ID_SHIFT (0U) +#define MMDC_MADPCR1_PRF_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR1_PRF_AXI_ID_SHIFT)) & MMDC_MADPCR1_PRF_AXI_ID_MASK) +#define MMDC_MADPCR1_PRF_AXI_IDMASK_MASK (0xFFFF0000U) +#define MMDC_MADPCR1_PRF_AXI_IDMASK_SHIFT (16U) +#define MMDC_MADPCR1_PRF_AXI_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR1_PRF_AXI_IDMASK_SHIFT)) & MMDC_MADPCR1_PRF_AXI_IDMASK_MASK) + +/*! @name MADPSR0 - MMDC Core Debug and Profiling Status Register 0 */ +#define MMDC_MADPSR0_CYC_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR0_CYC_COUNT_SHIFT (0U) +#define MMDC_MADPSR0_CYC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR0_CYC_COUNT_SHIFT)) & MMDC_MADPSR0_CYC_COUNT_MASK) + +/*! @name MADPSR1 - MMDC Core Debug and Profiling Status Register 1 */ +#define MMDC_MADPSR1_BUSY_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR1_BUSY_COUNT_SHIFT (0U) +#define MMDC_MADPSR1_BUSY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR1_BUSY_COUNT_SHIFT)) & MMDC_MADPSR1_BUSY_COUNT_MASK) + +/*! @name MADPSR2 - MMDC Core Debug and Profiling Status Register 2 */ +#define MMDC_MADPSR2_RD_ACC_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR2_RD_ACC_COUNT_SHIFT (0U) +#define MMDC_MADPSR2_RD_ACC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR2_RD_ACC_COUNT_SHIFT)) & MMDC_MADPSR2_RD_ACC_COUNT_MASK) + +/*! @name MADPSR3 - MMDC Core Debug and Profiling Status Register 3 */ +#define MMDC_MADPSR3_WR_ACC_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR3_WR_ACC_COUNT_SHIFT (0U) +#define MMDC_MADPSR3_WR_ACC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR3_WR_ACC_COUNT_SHIFT)) & MMDC_MADPSR3_WR_ACC_COUNT_MASK) + +/*! @name MADPSR4 - MMDC Core Debug and Profiling Status Register 4 */ +#define MMDC_MADPSR4_RD_BYTES_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR4_RD_BYTES_COUNT_SHIFT (0U) +#define MMDC_MADPSR4_RD_BYTES_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR4_RD_BYTES_COUNT_SHIFT)) & MMDC_MADPSR4_RD_BYTES_COUNT_MASK) + +/*! @name MADPSR5 - MMDC Core Debug and Profiling Status Register 5 */ +#define MMDC_MADPSR5_WR_BYTES_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR5_WR_BYTES_COUNT_SHIFT (0U) +#define MMDC_MADPSR5_WR_BYTES_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR5_WR_BYTES_COUNT_SHIFT)) & MMDC_MADPSR5_WR_BYTES_COUNT_MASK) + +/*! @name MASBS0 - MMDC Core Step By Step Address Register */ +#define MMDC_MASBS0_SBS_ADDR_MASK (0xFFFFFFFFU) +#define MMDC_MASBS0_SBS_ADDR_SHIFT (0U) +#define MMDC_MASBS0_SBS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS0_SBS_ADDR_SHIFT)) & MMDC_MASBS0_SBS_ADDR_MASK) + +/*! @name MASBS1 - MMDC Core Step By Step Address Attributes Register */ +#define MMDC_MASBS1_SBS_VLD_MASK (0x1U) +#define MMDC_MASBS1_SBS_VLD_SHIFT (0U) +#define MMDC_MASBS1_SBS_VLD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_VLD_SHIFT)) & MMDC_MASBS1_SBS_VLD_MASK) +#define MMDC_MASBS1_SBS_TYPE_MASK (0x2U) +#define MMDC_MASBS1_SBS_TYPE_SHIFT (1U) +#define MMDC_MASBS1_SBS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_TYPE_SHIFT)) & MMDC_MASBS1_SBS_TYPE_MASK) +#define MMDC_MASBS1_SBS_LOCK_MASK (0xCU) +#define MMDC_MASBS1_SBS_LOCK_SHIFT (2U) +#define MMDC_MASBS1_SBS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_LOCK_SHIFT)) & MMDC_MASBS1_SBS_LOCK_MASK) +#define MMDC_MASBS1_SBS_PROT_MASK (0x70U) +#define MMDC_MASBS1_SBS_PROT_SHIFT (4U) +#define MMDC_MASBS1_SBS_PROT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_PROT_SHIFT)) & MMDC_MASBS1_SBS_PROT_MASK) +#define MMDC_MASBS1_SBS_SIZE_MASK (0x380U) +#define MMDC_MASBS1_SBS_SIZE_SHIFT (7U) +#define MMDC_MASBS1_SBS_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_SIZE_SHIFT)) & MMDC_MASBS1_SBS_SIZE_MASK) +#define MMDC_MASBS1_SBS_BURST_MASK (0xC00U) +#define MMDC_MASBS1_SBS_BURST_SHIFT (10U) +#define MMDC_MASBS1_SBS_BURST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_BURST_SHIFT)) & MMDC_MASBS1_SBS_BURST_MASK) +#define MMDC_MASBS1_SBS_BUFF_MASK (0x1000U) +#define MMDC_MASBS1_SBS_BUFF_SHIFT (12U) +#define MMDC_MASBS1_SBS_BUFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_BUFF_SHIFT)) & MMDC_MASBS1_SBS_BUFF_MASK) +#define MMDC_MASBS1_SBS_LEN_MASK (0xE000U) +#define MMDC_MASBS1_SBS_LEN_SHIFT (13U) +#define MMDC_MASBS1_SBS_LEN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_LEN_SHIFT)) & MMDC_MASBS1_SBS_LEN_MASK) +#define MMDC_MASBS1_SBS_AXI_ID_MASK (0xFFFF0000U) +#define MMDC_MASBS1_SBS_AXI_ID_SHIFT (16U) +#define MMDC_MASBS1_SBS_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_AXI_ID_SHIFT)) & MMDC_MASBS1_SBS_AXI_ID_MASK) + +/*! @name MAGENP - MMDC Core General Purpose Register */ +#define MMDC_MAGENP_GP31_GP0_MASK (0xFFFFFFFFU) +#define MMDC_MAGENP_GP31_GP0_SHIFT (0U) +#define MMDC_MAGENP_GP31_GP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAGENP_GP31_GP0_SHIFT)) & MMDC_MAGENP_GP31_GP0_MASK) + +/*! @name MPZQHWCTRL - MMDC PHY ZQ HW control register */ +#define MMDC_MPZQHWCTRL_ZQ_MODE_MASK (0x3U) +#define MMDC_MPZQHWCTRL_ZQ_MODE_SHIFT (0U) +#define MMDC_MPZQHWCTRL_ZQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_MODE_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_MODE_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_PER_MASK (0x3CU) +#define MMDC_MPZQHWCTRL_ZQ_HW_PER_SHIFT (2U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PER_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PER_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_MASK (0x7C0U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_SHIFT (6U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_MASK (0xF800U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_SHIFT (11U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK (0x10000U) +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_SHIFT (16U) +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_FOR_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK) +#define MMDC_MPZQHWCTRL_TZQ_INIT_MASK (0xE0000U) +#define MMDC_MPZQHWCTRL_TZQ_INIT_SHIFT (17U) +#define MMDC_MPZQHWCTRL_TZQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_INIT_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_INIT_MASK) +#define MMDC_MPZQHWCTRL_TZQ_OPER_MASK (0x700000U) +#define MMDC_MPZQHWCTRL_TZQ_OPER_SHIFT (20U) +#define MMDC_MPZQHWCTRL_TZQ_OPER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_OPER_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_OPER_MASK) +#define MMDC_MPZQHWCTRL_TZQ_CS_MASK (0x3800000U) +#define MMDC_MPZQHWCTRL_TZQ_CS_SHIFT (23U) +#define MMDC_MPZQHWCTRL_TZQ_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_CS_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_CS_MASK) +#define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_MASK (0xF8000000U) +#define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_SHIFT (27U) +#define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_MASK) + +/*! @name MPZQSWCTRL - MMDC PHY ZQ SW control register */ +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK (0x1U) +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_SHIFT (0U) +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_FOR_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK (0x2U) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES_SHIFT (1U) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_RES_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK (0x7CU) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_SHIFT (2U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK (0xF80U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT (7U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK (0x1000U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_SHIFT (12U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PD_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK (0x2000U) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_SHIFT (13U) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_SHIFT)) & MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK) +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK (0x30000U) +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_SHIFT (16U) +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK) + +/*! @name MPWLGCR - MMDC PHY Write Leveling Configuration and Error Status Register */ +#define MMDC_MPWLGCR_HW_WL_EN_MASK (0x1U) +#define MMDC_MPWLGCR_HW_WL_EN_SHIFT (0U) +#define MMDC_MPWLGCR_HW_WL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_HW_WL_EN_SHIFT)) & MMDC_MPWLGCR_HW_WL_EN_MASK) +#define MMDC_MPWLGCR_SW_WL_EN_MASK (0x2U) +#define MMDC_MPWLGCR_SW_WL_EN_SHIFT (1U) +#define MMDC_MPWLGCR_SW_WL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_SW_WL_EN_SHIFT)) & MMDC_MPWLGCR_SW_WL_EN_MASK) +#define MMDC_MPWLGCR_SW_WL_CNT_EN_MASK (0x4U) +#define MMDC_MPWLGCR_SW_WL_CNT_EN_SHIFT (2U) +#define MMDC_MPWLGCR_SW_WL_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_SW_WL_CNT_EN_SHIFT)) & MMDC_MPWLGCR_SW_WL_CNT_EN_MASK) +#define MMDC_MPWLGCR_WL_SW_RES0_MASK (0x10U) +#define MMDC_MPWLGCR_WL_SW_RES0_SHIFT (4U) +#define MMDC_MPWLGCR_WL_SW_RES0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_SW_RES0_SHIFT)) & MMDC_MPWLGCR_WL_SW_RES0_MASK) +#define MMDC_MPWLGCR_WL_SW_RES1_MASK (0x20U) +#define MMDC_MPWLGCR_WL_SW_RES1_SHIFT (5U) +#define MMDC_MPWLGCR_WL_SW_RES1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_SW_RES1_SHIFT)) & MMDC_MPWLGCR_WL_SW_RES1_MASK) +#define MMDC_MPWLGCR_WL_HW_ERR0_MASK (0x100U) +#define MMDC_MPWLGCR_WL_HW_ERR0_SHIFT (8U) +#define MMDC_MPWLGCR_WL_HW_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_HW_ERR0_SHIFT)) & MMDC_MPWLGCR_WL_HW_ERR0_MASK) +#define MMDC_MPWLGCR_WL_HW_ERR1_MASK (0x200U) +#define MMDC_MPWLGCR_WL_HW_ERR1_SHIFT (9U) +#define MMDC_MPWLGCR_WL_HW_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_HW_ERR1_SHIFT)) & MMDC_MPWLGCR_WL_HW_ERR1_MASK) + +/*! @name MPWLDECTRL0 - MMDC PHY Write Leveling Delay Control Register 0 */ +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_MASK) +#define MMDC_MPWLDECTRL0_WL_HC_DEL0_MASK (0x100U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL0_SHIFT (8U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_HC_DEL0_SHIFT)) & MMDC_MPWLDECTRL0_WL_HC_DEL0_MASK) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL0_MASK (0x600U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL0_SHIFT (9U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_CYC_DEL0_SHIFT)) & MMDC_MPWLDECTRL0_WL_CYC_DEL0_MASK) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_MASK (0x7F0000U) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_SHIFT (16U) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_MASK) +#define MMDC_MPWLDECTRL0_WL_HC_DEL1_MASK (0x1000000U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL1_SHIFT (24U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_HC_DEL1_SHIFT)) & MMDC_MPWLDECTRL0_WL_HC_DEL1_MASK) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL1_MASK (0x6000000U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL1_SHIFT (25U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_CYC_DEL1_SHIFT)) & MMDC_MPWLDECTRL0_WL_CYC_DEL1_MASK) + +/*! @name MPWLDECTRL1 - MMDC PHY Write Leveling Delay Control Register 1 */ +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_MASK (0x7FU) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_SHIFT (0U) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_SHIFT)) & MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_MASK) +#define MMDC_MPWLDECTRL1_WL_HC_DEL2_MASK (0x100U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL2_SHIFT (8U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_HC_DEL2_SHIFT)) & MMDC_MPWLDECTRL1_WL_HC_DEL2_MASK) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL2_MASK (0x600U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL2_SHIFT (9U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_CYC_DEL2_SHIFT)) & MMDC_MPWLDECTRL1_WL_CYC_DEL2_MASK) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_MASK (0x7F0000U) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_SHIFT (16U) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_SHIFT)) & MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_MASK) +#define MMDC_MPWLDECTRL1_WL_HC_DEL3_MASK (0x1000000U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL3_SHIFT (24U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_HC_DEL3_SHIFT)) & MMDC_MPWLDECTRL1_WL_HC_DEL3_MASK) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL3_MASK (0x6000000U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL3_SHIFT (25U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_CYC_DEL3_SHIFT)) & MMDC_MPWLDECTRL1_WL_CYC_DEL3_MASK) + +/*! @name MPWLDLST - MMDC PHY Write Leveling delay-line Status Register */ +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDLST_WL_DL_UNIT_NUM0_SHIFT)) & MMDC_MPWLDLST_WL_DL_UNIT_NUM0_MASK) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDLST_WL_DL_UNIT_NUM1_SHIFT)) & MMDC_MPWLDLST_WL_DL_UNIT_NUM1_MASK) + +/*! @name MPODTCTRL - MMDC PHY ODT control register */ +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK (0x1U) +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_SHIFT (0U) +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_WR_PAS_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK (0x2U) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_SHIFT (1U) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_WR_ACT_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK (0x4U) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_SHIFT (2U) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_RD_PAS_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK) +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK (0x8U) +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_SHIFT (3U) +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_RD_ACT_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK) +#define MMDC_MPODTCTRL_ODT0_INT_RES_MASK (0x70U) +#define MMDC_MPODTCTRL_ODT0_INT_RES_SHIFT (4U) +#define MMDC_MPODTCTRL_ODT0_INT_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT0_INT_RES_SHIFT)) & MMDC_MPODTCTRL_ODT0_INT_RES_MASK) +#define MMDC_MPODTCTRL_ODT1_INT_RES_MASK (0x700U) +#define MMDC_MPODTCTRL_ODT1_INT_RES_SHIFT (8U) +#define MMDC_MPODTCTRL_ODT1_INT_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT1_INT_RES_SHIFT)) & MMDC_MPODTCTRL_ODT1_INT_RES_MASK) + +/*! @name MPRDDQBY0DL - MMDC PHY Read DQ Byte0 Delay Register */ +#define MMDC_MPRDDQBY0DL_RD_DQ0_DEL_MASK (0x7U) +#define MMDC_MPRDDQBY0DL_RD_DQ0_DEL_SHIFT (0U) +#define MMDC_MPRDDQBY0DL_RD_DQ0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ0_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ0_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ1_DEL_MASK (0x70U) +#define MMDC_MPRDDQBY0DL_RD_DQ1_DEL_SHIFT (4U) +#define MMDC_MPRDDQBY0DL_RD_DQ1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ1_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ1_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ2_DEL_MASK (0x700U) +#define MMDC_MPRDDQBY0DL_RD_DQ2_DEL_SHIFT (8U) +#define MMDC_MPRDDQBY0DL_RD_DQ2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ2_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ2_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ3_DEL_MASK (0x7000U) +#define MMDC_MPRDDQBY0DL_RD_DQ3_DEL_SHIFT (12U) +#define MMDC_MPRDDQBY0DL_RD_DQ3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ3_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ3_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ4_DEL_MASK (0x70000U) +#define MMDC_MPRDDQBY0DL_RD_DQ4_DEL_SHIFT (16U) +#define MMDC_MPRDDQBY0DL_RD_DQ4_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ4_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ4_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ5_DEL_MASK (0x700000U) +#define MMDC_MPRDDQBY0DL_RD_DQ5_DEL_SHIFT (20U) +#define MMDC_MPRDDQBY0DL_RD_DQ5_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ5_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ5_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ6_DEL_MASK (0x7000000U) +#define MMDC_MPRDDQBY0DL_RD_DQ6_DEL_SHIFT (24U) +#define MMDC_MPRDDQBY0DL_RD_DQ6_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ6_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ6_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ7_DEL_MASK (0x70000000U) +#define MMDC_MPRDDQBY0DL_RD_DQ7_DEL_SHIFT (28U) +#define MMDC_MPRDDQBY0DL_RD_DQ7_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ7_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ7_DEL_MASK) + +/*! @name MPRDDQBY1DL - MMDC PHY Read DQ Byte1 Delay Register */ +#define MMDC_MPRDDQBY1DL_RD_DQ8_DEL_MASK (0x7U) +#define MMDC_MPRDDQBY1DL_RD_DQ8_DEL_SHIFT (0U) +#define MMDC_MPRDDQBY1DL_RD_DQ8_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ8_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ8_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ9_DEL_MASK (0x70U) +#define MMDC_MPRDDQBY1DL_RD_DQ9_DEL_SHIFT (4U) +#define MMDC_MPRDDQBY1DL_RD_DQ9_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ9_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ9_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ10_DEL_MASK (0x700U) +#define MMDC_MPRDDQBY1DL_RD_DQ10_DEL_SHIFT (8U) +#define MMDC_MPRDDQBY1DL_RD_DQ10_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ10_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ10_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ11_DEL_MASK (0x7000U) +#define MMDC_MPRDDQBY1DL_RD_DQ11_DEL_SHIFT (12U) +#define MMDC_MPRDDQBY1DL_RD_DQ11_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ11_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ11_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ12_DEL_MASK (0x70000U) +#define MMDC_MPRDDQBY1DL_RD_DQ12_DEL_SHIFT (16U) +#define MMDC_MPRDDQBY1DL_RD_DQ12_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ12_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ12_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ13_DEL_MASK (0x700000U) +#define MMDC_MPRDDQBY1DL_RD_DQ13_DEL_SHIFT (20U) +#define MMDC_MPRDDQBY1DL_RD_DQ13_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ13_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ13_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ14_DEL_MASK (0x7000000U) +#define MMDC_MPRDDQBY1DL_RD_DQ14_DEL_SHIFT (24U) +#define MMDC_MPRDDQBY1DL_RD_DQ14_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ14_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ14_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ15_DEL_MASK (0x70000000U) +#define MMDC_MPRDDQBY1DL_RD_DQ15_DEL_SHIFT (28U) +#define MMDC_MPRDDQBY1DL_RD_DQ15_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ15_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ15_DEL_MASK) + +/*! @name MPWRDQBY0DL - MMDC PHY Write DQ Byte0 Delay Register */ +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ0_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ1_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ2_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ3_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ4_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ5_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ6_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ7_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DM0_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK) + +/*! @name MPWRDQBY1DL - MMDC PHY Write DQ Byte1 Delay Register */ +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ8_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ9_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ10_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ11_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ12_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ13_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ14_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ15_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DM1_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK) + +/*! @name MPWRDQBY2DL - MMDC PHY Write DQ Byte2 Delay Register */ +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ16_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ17_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ18_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ19_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ20_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ21_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ22_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ23_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DM2_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK) + +/*! @name MPWRDQBY3DL - MMDC PHY Write DQ Byte3 Delay Register */ +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ24_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ25_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ26_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ27_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ28_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ29_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ30_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ31_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DM3_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK) + +/*! @name MPDGCTRL0 - MMDC PHY Read DQS Gating Control Register 0 */ +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_MASK) +#define MMDC_MPDGCTRL0_DG_HC_DEL0_MASK (0xF00U) +#define MMDC_MPDGCTRL0_DG_HC_DEL0_SHIFT (8U) +#define MMDC_MPDGCTRL0_DG_HC_DEL0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_HC_DEL0_SHIFT)) & MMDC_MPDGCTRL0_DG_HC_DEL0_MASK) +#define MMDC_MPDGCTRL0_HW_DG_ERR_MASK (0x1000U) +#define MMDC_MPDGCTRL0_HW_DG_ERR_SHIFT (12U) +#define MMDC_MPDGCTRL0_HW_DG_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_HW_DG_ERR_SHIFT)) & MMDC_MPDGCTRL0_HW_DG_ERR_MASK) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_MASK (0x7F0000U) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_SHIFT (16U) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_MASK) +#define MMDC_MPDGCTRL0_DG_EXT_UP_MASK (0x800000U) +#define MMDC_MPDGCTRL0_DG_EXT_UP_SHIFT (23U) +#define MMDC_MPDGCTRL0_DG_EXT_UP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_EXT_UP_SHIFT)) & MMDC_MPDGCTRL0_DG_EXT_UP_MASK) +#define MMDC_MPDGCTRL0_DG_HC_DEL1_MASK (0xF000000U) +#define MMDC_MPDGCTRL0_DG_HC_DEL1_SHIFT (24U) +#define MMDC_MPDGCTRL0_DG_HC_DEL1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_HC_DEL1_SHIFT)) & MMDC_MPDGCTRL0_DG_HC_DEL1_MASK) +#define MMDC_MPDGCTRL0_HW_DG_EN_MASK (0x10000000U) +#define MMDC_MPDGCTRL0_HW_DG_EN_SHIFT (28U) +#define MMDC_MPDGCTRL0_HW_DG_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_HW_DG_EN_SHIFT)) & MMDC_MPDGCTRL0_HW_DG_EN_MASK) +#define MMDC_MPDGCTRL0_DG_DIS_MASK (0x20000000U) +#define MMDC_MPDGCTRL0_DG_DIS_SHIFT (29U) +#define MMDC_MPDGCTRL0_DG_DIS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_DIS_SHIFT)) & MMDC_MPDGCTRL0_DG_DIS_MASK) +#define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK (0x40000000U) +#define MMDC_MPDGCTRL0_DG_CMP_CYC_SHIFT (30U) +#define MMDC_MPDGCTRL0_DG_CMP_CYC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_CMP_CYC_SHIFT)) & MMDC_MPDGCTRL0_DG_CMP_CYC_MASK) +#define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK (0x80000000U) +#define MMDC_MPDGCTRL0_RST_RD_FIFO_SHIFT (31U) +#define MMDC_MPDGCTRL0_RST_RD_FIFO(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_RST_RD_FIFO_SHIFT)) & MMDC_MPDGCTRL0_RST_RD_FIFO_MASK) + +/*! @name MPDGDLST0 - MMDC PHY Read DQS Gating delay-line Status Register */ +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_SHIFT)) & MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_MASK) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_SHIFT)) & MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_MASK) + +/*! @name MPRDDLCTL - MMDC PHY Read delay-lines Configuration Register */ +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK (0x7F00U) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT (8U) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK) + +/*! @name MPRDDLST - MMDC PHY Read delay-lines Status Register */ +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLST_RD_DL_UNIT_NUM0_SHIFT)) & MMDC_MPRDDLST_RD_DL_UNIT_NUM0_MASK) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLST_RD_DL_UNIT_NUM1_SHIFT)) & MMDC_MPRDDLST_RD_DL_UNIT_NUM1_MASK) + +/*! @name MPWRDLCTL - MMDC PHY Write delay-lines Configuration Register */ +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK (0x7F00U) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_SHIFT (8U) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK) + +/*! @name MPWRDLST - MMDC PHY Write delay-lines Status Register */ +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLST_WR_DL_UNIT_NUM0_SHIFT)) & MMDC_MPWRDLST_WR_DL_UNIT_NUM0_MASK) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLST_WR_DL_UNIT_NUM1_SHIFT)) & MMDC_MPWRDLST_WR_DL_UNIT_NUM1_MASK) + +/*! @name MPSDCTRL - MMDC PHY CK Control Register */ +#define MMDC_MPSDCTRL_SDCLK0_DEL_MASK (0x300U) +#define MMDC_MPSDCTRL_SDCLK0_DEL_SHIFT (8U) +#define MMDC_MPSDCTRL_SDCLK0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSDCTRL_SDCLK0_DEL_SHIFT)) & MMDC_MPSDCTRL_SDCLK0_DEL_MASK) +#define MMDC_MPSDCTRL_SDCLK1_DEL_MASK (0xC00U) +#define MMDC_MPSDCTRL_SDCLK1_DEL_SHIFT (10U) +#define MMDC_MPSDCTRL_SDCLK1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSDCTRL_SDCLK1_DEL_SHIFT)) & MMDC_MPSDCTRL_SDCLK1_DEL_MASK) + +/*! @name MPZQLP2CTL - MMDC ZQ LPDDR2 HW Control Register */ +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK (0x1FFU) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_SHIFT (0U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK (0xFF0000U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_SHIFT (16U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK (0x7F000000U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_SHIFT (24U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK) + +/*! @name MPRDDLHWCTL - MMDC PHY Read Delay HW Calibration Control Register */ +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_MASK (0x1U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_SHIFT (0U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_MASK) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_MASK (0x2U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_SHIFT (1U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_MASK) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK (0x10U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_SHIFT (4U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_EN_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK (0x20U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_SHIFT (5U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK) + +/*! @name MPWRDLHWCTL - MMDC PHY Write Delay HW Calibration Control Register */ +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_MASK (0x1U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_SHIFT (0U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_MASK) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_MASK (0x2U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_SHIFT (1U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_MASK) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK (0x10U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_SHIFT (4U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_EN_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK (0x20U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_SHIFT (5U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK) + +/*! @name MPRDDLHWST0 - MMDC PHY Read Delay HW Calibration Status Register 0 */ +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_MASK (0x7FU) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_SHIFT (0U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_MASK) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP0_MASK (0x7F00U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP0_SHIFT (8U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_UP0_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_UP0_MASK) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_MASK (0x7F0000U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_SHIFT (16U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_MASK) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP1_MASK (0x7F000000U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP1_SHIFT (24U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_UP1_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_UP1_MASK) + +/*! @name MPWRDLHWST0 - MMDC PHY Write Delay HW Calibration Status Register 0 */ +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_MASK (0x7FU) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_SHIFT (0U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_MASK) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP0_MASK (0x7F00U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP0_SHIFT (8U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_UP0_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_UP0_MASK) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_MASK (0x7F0000U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_SHIFT (16U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_MASK) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP1_MASK (0x7F000000U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP1_SHIFT (24U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_UP1_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_UP1_MASK) + +/*! @name MPWLHWERR - MMDC PHY Write Leveling HW Error Register */ +#define MMDC_MPWLHWERR_HW_WL0_DQ_MASK (0xFFU) +#define MMDC_MPWLHWERR_HW_WL0_DQ_SHIFT (0U) +#define MMDC_MPWLHWERR_HW_WL0_DQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLHWERR_HW_WL0_DQ_SHIFT)) & MMDC_MPWLHWERR_HW_WL0_DQ_MASK) +#define MMDC_MPWLHWERR_HW_WL1_DQ_MASK (0xFF00U) +#define MMDC_MPWLHWERR_HW_WL1_DQ_SHIFT (8U) +#define MMDC_MPWLHWERR_HW_WL1_DQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLHWERR_HW_WL1_DQ_SHIFT)) & MMDC_MPWLHWERR_HW_WL1_DQ_MASK) + +/*! @name MPDGHWST0 - MMDC PHY Read DQS Gating HW Status Register 0 */ +#define MMDC_MPDGHWST0_HW_DG_LOW0_MASK (0x7FFU) +#define MMDC_MPDGHWST0_HW_DG_LOW0_SHIFT (0U) +#define MMDC_MPDGHWST0_HW_DG_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST0_HW_DG_LOW0_SHIFT)) & MMDC_MPDGHWST0_HW_DG_LOW0_MASK) +#define MMDC_MPDGHWST0_HW_DG_UP0_MASK (0x7FF0000U) +#define MMDC_MPDGHWST0_HW_DG_UP0_SHIFT (16U) +#define MMDC_MPDGHWST0_HW_DG_UP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST0_HW_DG_UP0_SHIFT)) & MMDC_MPDGHWST0_HW_DG_UP0_MASK) + +/*! @name MPDGHWST1 - MMDC PHY Read DQS Gating HW Status Register 1 */ +#define MMDC_MPDGHWST1_HW_DG_LOW1_MASK (0x7FFU) +#define MMDC_MPDGHWST1_HW_DG_LOW1_SHIFT (0U) +#define MMDC_MPDGHWST1_HW_DG_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST1_HW_DG_LOW1_SHIFT)) & MMDC_MPDGHWST1_HW_DG_LOW1_MASK) +#define MMDC_MPDGHWST1_HW_DG_UP1_MASK (0x7FF0000U) +#define MMDC_MPDGHWST1_HW_DG_UP1_SHIFT (16U) +#define MMDC_MPDGHWST1_HW_DG_UP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST1_HW_DG_UP1_SHIFT)) & MMDC_MPDGHWST1_HW_DG_UP1_MASK) + +/*! @name MPPDCMPR1 - MMDC PHY Pre-defined Compare Register 1 */ +#define MMDC_MPPDCMPR1_PDV1_MASK (0xFFFFU) +#define MMDC_MPPDCMPR1_PDV1_SHIFT (0U) +#define MMDC_MPPDCMPR1_PDV1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR1_PDV1_SHIFT)) & MMDC_MPPDCMPR1_PDV1_MASK) +#define MMDC_MPPDCMPR1_PDV2_MASK (0xFFFF0000U) +#define MMDC_MPPDCMPR1_PDV2_SHIFT (16U) +#define MMDC_MPPDCMPR1_PDV2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR1_PDV2_SHIFT)) & MMDC_MPPDCMPR1_PDV2_MASK) + +/*! @name MPPDCMPR2 - MMDC PHY Pre-defined Compare and CA delay-line Configuration Register */ +#define MMDC_MPPDCMPR2_MPR_CMP_MASK (0x1U) +#define MMDC_MPPDCMPR2_MPR_CMP_SHIFT (0U) +#define MMDC_MPPDCMPR2_MPR_CMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_MPR_CMP_SHIFT)) & MMDC_MPPDCMPR2_MPR_CMP_MASK) +#define MMDC_MPPDCMPR2_MPR_FULL_CMP_MASK (0x2U) +#define MMDC_MPPDCMPR2_MPR_FULL_CMP_SHIFT (1U) +#define MMDC_MPPDCMPR2_MPR_FULL_CMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_MPR_FULL_CMP_SHIFT)) & MMDC_MPPDCMPR2_MPR_FULL_CMP_MASK) +#define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_MASK (0x4U) +#define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_SHIFT (2U) +#define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_SHIFT)) & MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_MASK) +#define MMDC_MPPDCMPR2_ZQ_OFFSET_EN_MASK (0x8U) +#define MMDC_MPPDCMPR2_ZQ_OFFSET_EN_SHIFT (3U) +#define MMDC_MPPDCMPR2_ZQ_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_OFFSET_EN_SHIFT)) & MMDC_MPPDCMPR2_ZQ_OFFSET_EN_MASK) +#define MMDC_MPPDCMPR2_ZQ_PD_OFFSET_MASK (0xF0U) +#define MMDC_MPPDCMPR2_ZQ_PD_OFFSET_SHIFT (4U) +#define MMDC_MPPDCMPR2_ZQ_PD_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_PD_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_ZQ_PD_OFFSET_MASK) +#define MMDC_MPPDCMPR2_ZQ_PU_OFFSET_MASK (0xF00U) +#define MMDC_MPPDCMPR2_ZQ_PU_OFFSET_SHIFT (8U) +#define MMDC_MPPDCMPR2_ZQ_PU_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_PU_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_ZQ_PU_OFFSET_MASK) +#define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_MASK (0x7F0000U) +#define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_SHIFT (16U) +#define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_MASK) +#define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_MASK (0x7F000000U) +#define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_SHIFT (24U) +#define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_SHIFT)) & MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_MASK) + +/*! @name MPSWDAR0 - MMDC PHY SW Dummy Access Register */ +#define MMDC_MPSWDAR0_SW_DUMMY_WR_MASK (0x1U) +#define MMDC_MPSWDAR0_SW_DUMMY_WR_SHIFT (0U) +#define MMDC_MPSWDAR0_SW_DUMMY_WR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUMMY_WR_SHIFT)) & MMDC_MPSWDAR0_SW_DUMMY_WR_MASK) +#define MMDC_MPSWDAR0_SW_DUMMY_RD_MASK (0x2U) +#define MMDC_MPSWDAR0_SW_DUMMY_RD_SHIFT (1U) +#define MMDC_MPSWDAR0_SW_DUMMY_RD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUMMY_RD_SHIFT)) & MMDC_MPSWDAR0_SW_DUMMY_RD_MASK) +#define MMDC_MPSWDAR0_SW_DUM_CMP0_MASK (0x4U) +#define MMDC_MPSWDAR0_SW_DUM_CMP0_SHIFT (2U) +#define MMDC_MPSWDAR0_SW_DUM_CMP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUM_CMP0_SHIFT)) & MMDC_MPSWDAR0_SW_DUM_CMP0_MASK) +#define MMDC_MPSWDAR0_SW_DUM_CMP1_MASK (0x8U) +#define MMDC_MPSWDAR0_SW_DUM_CMP1_SHIFT (3U) +#define MMDC_MPSWDAR0_SW_DUM_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUM_CMP1_SHIFT)) & MMDC_MPSWDAR0_SW_DUM_CMP1_MASK) + +/*! @name MPSWDRDR0 - MMDC PHY SW Dummy Read Data Register 0 */ +#define MMDC_MPSWDRDR0_DUM_RD0_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR0_DUM_RD0_SHIFT (0U) +#define MMDC_MPSWDRDR0_DUM_RD0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR0_DUM_RD0_SHIFT)) & MMDC_MPSWDRDR0_DUM_RD0_MASK) + +/*! @name MPSWDRDR1 - MMDC PHY SW Dummy Read Data Register 1 */ +#define MMDC_MPSWDRDR1_DUM_RD1_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR1_DUM_RD1_SHIFT (0U) +#define MMDC_MPSWDRDR1_DUM_RD1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR1_DUM_RD1_SHIFT)) & MMDC_MPSWDRDR1_DUM_RD1_MASK) + +/*! @name MPSWDRDR2 - MMDC PHY SW Dummy Read Data Register 2 */ +#define MMDC_MPSWDRDR2_DUM_RD2_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR2_DUM_RD2_SHIFT (0U) +#define MMDC_MPSWDRDR2_DUM_RD2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR2_DUM_RD2_SHIFT)) & MMDC_MPSWDRDR2_DUM_RD2_MASK) + +/*! @name MPSWDRDR3 - MMDC PHY SW Dummy Read Data Register 3 */ +#define MMDC_MPSWDRDR3_DUM_RD3_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR3_DUM_RD3_SHIFT (0U) +#define MMDC_MPSWDRDR3_DUM_RD3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR3_DUM_RD3_SHIFT)) & MMDC_MPSWDRDR3_DUM_RD3_MASK) + +/*! @name MPSWDRDR4 - MMDC PHY SW Dummy Read Data Register 4 */ +#define MMDC_MPSWDRDR4_DUM_RD4_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR4_DUM_RD4_SHIFT (0U) +#define MMDC_MPSWDRDR4_DUM_RD4(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR4_DUM_RD4_SHIFT)) & MMDC_MPSWDRDR4_DUM_RD4_MASK) + +/*! @name MPSWDRDR5 - MMDC PHY SW Dummy Read Data Register 5 */ +#define MMDC_MPSWDRDR5_DUM_RD5_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR5_DUM_RD5_SHIFT (0U) +#define MMDC_MPSWDRDR5_DUM_RD5(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR5_DUM_RD5_SHIFT)) & MMDC_MPSWDRDR5_DUM_RD5_MASK) + +/*! @name MPSWDRDR6 - MMDC PHY SW Dummy Read Data Register 6 */ +#define MMDC_MPSWDRDR6_DUM_RD6_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR6_DUM_RD6_SHIFT (0U) +#define MMDC_MPSWDRDR6_DUM_RD6(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR6_DUM_RD6_SHIFT)) & MMDC_MPSWDRDR6_DUM_RD6_MASK) + +/*! @name MPSWDRDR7 - MMDC PHY SW Dummy Read Data Register 7 */ +#define MMDC_MPSWDRDR7_DUM_RD7_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR7_DUM_RD7_SHIFT (0U) +#define MMDC_MPSWDRDR7_DUM_RD7(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR7_DUM_RD7_SHIFT)) & MMDC_MPSWDRDR7_DUM_RD7_MASK) + +/*! @name MPMUR0 - MMDC PHY Measure Unit Register */ +#define MMDC_MPMUR0_MU_BYP_VAL_MASK (0x3FFU) +#define MMDC_MPMUR0_MU_BYP_VAL_SHIFT (0U) +#define MMDC_MPMUR0_MU_BYP_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_BYP_VAL_SHIFT)) & MMDC_MPMUR0_MU_BYP_VAL_MASK) +#define MMDC_MPMUR0_MU_BYP_EN_MASK (0x400U) +#define MMDC_MPMUR0_MU_BYP_EN_SHIFT (10U) +#define MMDC_MPMUR0_MU_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_BYP_EN_SHIFT)) & MMDC_MPMUR0_MU_BYP_EN_MASK) +#define MMDC_MPMUR0_FRC_MSR_MASK (0x800U) +#define MMDC_MPMUR0_FRC_MSR_SHIFT (11U) +#define MMDC_MPMUR0_FRC_MSR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_FRC_MSR_SHIFT)) & MMDC_MPMUR0_FRC_MSR_MASK) +#define MMDC_MPMUR0_MU_UNIT_DEL_NUM_MASK (0x3FF0000U) +#define MMDC_MPMUR0_MU_UNIT_DEL_NUM_SHIFT (16U) +#define MMDC_MPMUR0_MU_UNIT_DEL_NUM(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_UNIT_DEL_NUM_SHIFT)) & MMDC_MPMUR0_MU_UNIT_DEL_NUM_MASK) + +/*! @name MPWRCADL - MMDC Write CA delay-line controller */ +#define MMDC_MPWRCADL_WR_CA0_DEL_MASK (0x3U) +#define MMDC_MPWRCADL_WR_CA0_DEL_SHIFT (0U) +#define MMDC_MPWRCADL_WR_CA0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA0_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA0_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA1_DEL_MASK (0xCU) +#define MMDC_MPWRCADL_WR_CA1_DEL_SHIFT (2U) +#define MMDC_MPWRCADL_WR_CA1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA1_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA1_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA2_DEL_MASK (0x30U) +#define MMDC_MPWRCADL_WR_CA2_DEL_SHIFT (4U) +#define MMDC_MPWRCADL_WR_CA2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA2_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA2_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA3_DEL_MASK (0xC0U) +#define MMDC_MPWRCADL_WR_CA3_DEL_SHIFT (6U) +#define MMDC_MPWRCADL_WR_CA3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA3_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA3_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA4_DEL_MASK (0x300U) +#define MMDC_MPWRCADL_WR_CA4_DEL_SHIFT (8U) +#define MMDC_MPWRCADL_WR_CA4_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA4_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA4_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA5_DEL_MASK (0xC00U) +#define MMDC_MPWRCADL_WR_CA5_DEL_SHIFT (10U) +#define MMDC_MPWRCADL_WR_CA5_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA5_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA5_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA6_DEL_MASK (0x3000U) +#define MMDC_MPWRCADL_WR_CA6_DEL_SHIFT (12U) +#define MMDC_MPWRCADL_WR_CA6_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA6_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA6_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA7_DEL_MASK (0xC000U) +#define MMDC_MPWRCADL_WR_CA7_DEL_SHIFT (14U) +#define MMDC_MPWRCADL_WR_CA7_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA7_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA7_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA8_DEL_MASK (0x30000U) +#define MMDC_MPWRCADL_WR_CA8_DEL_SHIFT (16U) +#define MMDC_MPWRCADL_WR_CA8_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA8_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA8_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA9_DEL_MASK (0xC0000U) +#define MMDC_MPWRCADL_WR_CA9_DEL_SHIFT (18U) +#define MMDC_MPWRCADL_WR_CA9_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA9_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA9_DEL_MASK) + +/*! @name MPDCCR - MMDC Duty Cycle Control Register */ +#define MMDC_MPDCCR_WR_DQS0_FT_DCC_MASK (0x7U) +#define MMDC_MPDCCR_WR_DQS0_FT_DCC_SHIFT (0U) +#define MMDC_MPDCCR_WR_DQS0_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_WR_DQS0_FT_DCC_SHIFT)) & MMDC_MPDCCR_WR_DQS0_FT_DCC_MASK) +#define MMDC_MPDCCR_WR_DQS1_FT_DCC_MASK (0x38U) +#define MMDC_MPDCCR_WR_DQS1_FT_DCC_SHIFT (3U) +#define MMDC_MPDCCR_WR_DQS1_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_WR_DQS1_FT_DCC_SHIFT)) & MMDC_MPDCCR_WR_DQS1_FT_DCC_MASK) +#define MMDC_MPDCCR_CK_FT0_DCC_MASK (0x7000U) +#define MMDC_MPDCCR_CK_FT0_DCC_SHIFT (12U) +#define MMDC_MPDCCR_CK_FT0_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_CK_FT0_DCC_SHIFT)) & MMDC_MPDCCR_CK_FT0_DCC_MASK) +#define MMDC_MPDCCR_CK_FT1_DCC_MASK (0x70000U) +#define MMDC_MPDCCR_CK_FT1_DCC_SHIFT (16U) +#define MMDC_MPDCCR_CK_FT1_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_CK_FT1_DCC_SHIFT)) & MMDC_MPDCCR_CK_FT1_DCC_MASK) +#define MMDC_MPDCCR_RD_DQS0_FT_DCC_MASK (0x380000U) +#define MMDC_MPDCCR_RD_DQS0_FT_DCC_SHIFT (19U) +#define MMDC_MPDCCR_RD_DQS0_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_RD_DQS0_FT_DCC_SHIFT)) & MMDC_MPDCCR_RD_DQS0_FT_DCC_MASK) +#define MMDC_MPDCCR_RD_DQS1_FT_DCC_MASK (0x1C00000U) +#define MMDC_MPDCCR_RD_DQS1_FT_DCC_SHIFT (22U) +#define MMDC_MPDCCR_RD_DQS1_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_RD_DQS1_FT_DCC_SHIFT)) & MMDC_MPDCCR_RD_DQS1_FT_DCC_MASK) + + +/*! + * @} + */ /* end of group MMDC_Register_Masks */ + + +/* MMDC - Peripheral instance base addresses */ +/** Peripheral MMDC base address */ +#define MMDC_BASE (0x21B0000u) +/** Peripheral MMDC base pointer */ +#define MMDC ((MMDC_Type *)MMDC_BASE) +/** Array initializer of MMDC peripheral base addresses */ +#define MMDC_BASE_ADDRS { MMDC_BASE } +/** Array initializer of MMDC peripheral base pointers */ +#define MMDC_BASE_PTRS { MMDC } +/* MMDC max frequency (MHz). */ +#define MMDC_MAX_FREQUENCY (400) +/* MMDC device start address. */ +#define MMDC_DEVICE_START_ADDRESS (0x80000000U) + + +/*! + * @} + */ /* end of group MMDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OCOTP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer + * @{ + */ + +/** OCOTP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ + __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t READ_CTRL; /**< OTP Controller Read Control Register, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Fuse Data Register, offset: 0x40 */ + uint8_t RESERVED_3[12]; + __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */ + __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ + __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ + __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ + __IO uint32_t CRC_ADDR; /**< OTP Controller CRC Test Address, offset: 0x70 */ + uint8_t RESERVED_5[12]; + __IO uint32_t CRC_VALUE; /**< OTP Controller CRC Value Register, offset: 0x80 */ + uint8_t RESERVED_6[12]; + __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */ + uint8_t RESERVED_7[108]; + __IO uint32_t TIMING2; /**< OTP Controller Timing Register 2, offset: 0x100 */ + uint8_t RESERVED_8[764]; + __IO uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ + uint8_t RESERVED_9[12]; + __IO uint32_t CFG0; /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CFG1; /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */ + uint8_t RESERVED_11[12]; + __IO uint32_t CFG2; /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CFG3; /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CFG4; /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CFG5; /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CFG6; /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */ + uint8_t RESERVED_16[12]; + __IO uint32_t MEM0; /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */ + uint8_t RESERVED_17[12]; + __IO uint32_t MEM1; /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */ + uint8_t RESERVED_18[12]; + __IO uint32_t MEM2; /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */ + uint8_t RESERVED_19[12]; + __IO uint32_t MEM3; /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */ + uint8_t RESERVED_20[12]; + __IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */ + uint8_t RESERVED_21[12]; + __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Memory Related Info.), offset: 0x4D0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.), offset: 0x4E0 */ + uint8_t RESERVED_23[12]; + __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.), offset: 0x4F0 */ + uint8_t RESERVED_24[12]; + __IO uint32_t OTPMK0; /**< Value of OTP Bank2 Word0 (OTPMK Key), offset: 0x500 */ + uint8_t RESERVED_25[12]; + __IO uint32_t OTPMK1; /**< Value of OTP Bank2 Word1 (OTPMK Key), offset: 0x510 */ + uint8_t RESERVED_26[12]; + __IO uint32_t OTPMK2; /**< Value of OTP Bank2 Word2 (OTPMK Key), offset: 0x520 */ + uint8_t RESERVED_27[12]; + __IO uint32_t OTPMK3; /**< Value of OTP Bank2 Word3 (OTPMK Key), offset: 0x530 */ + uint8_t RESERVED_28[12]; + __IO uint32_t OTPMK4; /**< Value of OTP Bank2 Word4 (OTPMK Key), offset: 0x540 */ + uint8_t RESERVED_29[12]; + __IO uint32_t OTPMK5; /**< Value of OTP Bank2 Word5 (OTPMK Key), offset: 0x550 */ + uint8_t RESERVED_30[12]; + __IO uint32_t OTPMK6; /**< Value of OTP Bank2 Word6 (OTPMK Key), offset: 0x560 */ + uint8_t RESERVED_31[12]; + __IO uint32_t OTPMK7; /**< Value of OTP Bank2 Word7 (OTPMK Key), offset: 0x570 */ + uint8_t RESERVED_32[12]; + __IO uint32_t SRK0; /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */ + uint8_t RESERVED_33[12]; + __IO uint32_t SRK1; /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */ + uint8_t RESERVED_34[12]; + __IO uint32_t SRK2; /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */ + uint8_t RESERVED_35[12]; + __IO uint32_t SRK3; /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */ + uint8_t RESERVED_36[12]; + __IO uint32_t SRK4; /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */ + uint8_t RESERVED_37[12]; + __IO uint32_t SRK5; /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */ + uint8_t RESERVED_38[12]; + __IO uint32_t SRK6; /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */ + uint8_t RESERVED_39[12]; + __IO uint32_t SRK7; /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */ + uint8_t RESERVED_40[12]; + __IO uint32_t SJC_RESP0; /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */ + uint8_t RESERVED_41[12]; + __IO uint32_t SJC_RESP1; /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */ + uint8_t RESERVED_42[12]; + __IO uint32_t MAC0; /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */ + uint8_t RESERVED_43[12]; + __IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */ + uint8_t RESERVED_44[12]; + __IO uint32_t MAC; /**< Value of OTP Bank4 Word4 (MAC Address) (OCOTP_RESERVED), offset: 0x640 */ + uint8_t RESERVED_45[12]; + __IO uint32_t CRC; /**< Value of OTP Bank4 Word5 (CRC Key), offset: 0x650 */ + uint8_t RESERVED_46[12]; + __IO uint32_t GP1; /**< Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660 */ + uint8_t RESERVED_47[12]; + __IO uint32_t GP2; /**< Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670 */ + uint8_t RESERVED_48[12]; + __IO uint32_t SW_GP0; /**< Value of OTP Bank5 Word0 (SW GP), offset: 0x680 */ + uint8_t RESERVED_49[12]; + __IO uint32_t SW_GP1; /**< Value of OTP Bank5 Word1 (SW GP), offset: 0x690 */ + uint8_t RESERVED_50[12]; + __IO uint32_t SW_GP2; /**< Value of OTP Bank5 Word2 (SW GP), offset: 0x6A0 */ + uint8_t RESERVED_51[12]; + __IO uint32_t SW_GP3; /**< Value of OTP Bank5 Word3 (SW GP), offset: 0x6B0 */ + uint8_t RESERVED_52[12]; + __IO uint32_t SW_GP4; /**< Value of OTP Bank5 Word4 (SW GP), offset: 0x6C0 */ + uint8_t RESERVED_53[12]; + __IO uint32_t MISC_CONF; /**< Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0 */ + uint8_t RESERVED_54[12]; + __IO uint32_t FIELD_RETURN; /**< Value of OTP Bank5 Word6 (Field Return), offset: 0x6E0 */ + uint8_t RESERVED_55[12]; + __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0 */ + uint8_t RESERVED_56[268]; + __IO uint32_t ROM_PATCH0; /**< Value of OTP Bank6 Word0 (ROM Patch), offset: 0x800 */ + uint8_t RESERVED_57[12]; + __IO uint32_t ROM_PATCH1; /**< Value of OTP Bank6 Word1 (ROM Patch), offset: 0x810 */ + uint8_t RESERVED_58[12]; + __IO uint32_t ROM_PATCH2; /**< Value of OTP Bank6 Word2 (ROM Patch), offset: 0x820 */ + uint8_t RESERVED_59[12]; + __IO uint32_t ROM_PATCH3; /**< Value of OTP Bank6 Word3 (ROM Patch), offset: 0x830 */ + uint8_t RESERVED_60[12]; + __IO uint32_t ROM_PATCH4; /**< Value of OTP Bank6 Word4 (ROM Patch), offset: 0x840 */ + uint8_t RESERVED_61[12]; + __IO uint32_t ROM_PATCH5; /**< Value of OTP Bank6 Word5 (ROM Patch), offset: 0x850 */ + uint8_t RESERVED_62[12]; + __IO uint32_t ROM_PATCH6; /**< Value of OTP Bank6 Word6 (ROM Patch), offset: 0x860 */ + uint8_t RESERVED_63[12]; + __IO uint32_t ROM_PATCH7; /**< Value of OTP Bank6 Word7 (ROM Patch), offset: 0x870 */ + uint8_t RESERVED_64[12]; + __IO uint32_t GP3_0; /**< Value of OTP Bank7 Word0 (General Purpose Customer Defined Info), offset: 0x880 */ + uint8_t RESERVED_65[12]; + __IO uint32_t GP3_1; /**< Value of OTP Bank7 Word1 (General Purpose Customer Defined Info), offset: 0x890 */ + uint8_t RESERVED_66[12]; + __IO uint32_t GP3_2; /**< Value of OTP Bank7 Word2 (General Purpose Customer Defined Info), offset: 0x8A0 */ + uint8_t RESERVED_67[12]; + __IO uint32_t GP3_3; /**< Value of OTP Bank7 Word3 (General Purpose Customer Defined Info), offset: 0x8B0 */ + uint8_t RESERVED_68[12]; + __IO uint32_t GP3_4; /**< Value of OTP Bank8 Word4 (General Purpose Customer Defined Info), offset: 0x8C0 */ + uint8_t RESERVED_69[12]; + __IO uint32_t GP4_0; /**< Value of OTP Bank7 Word5 (General Purpose Customer Defined Info), offset: 0x8D0 */ + uint8_t RESERVED_70[12]; + __IO uint32_t GP4_1; /**< Value of OTP Bank7 Word6 (General Purpose Customer Defined Info), offset: 0x8E0 */ + uint8_t RESERVED_71[12]; + __IO uint32_t GP4_2; /**< Value of OTP Bank7 Word7 (General Purpose Customer Defined Info), offset: 0x8F0 */ +} OCOTP_Type; + +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/*! @name CTRL - OTP Controller Control Register */ +#define OCOTP_CTRL_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_ADDR_SHIFT (0U) +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) +#define OCOTP_CTRL_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD0_SHIFT)) & OCOTP_CTRL_RSVD0_MASK) +#define OCOTP_CTRL_BUSY_MASK (0x100U) +#define OCOTP_CTRL_BUSY_SHIFT (8U) +#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) +#define OCOTP_CTRL_ERROR_MASK (0x200U) +#define OCOTP_CTRL_ERROR_SHIFT (9U) +#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) +#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_TEST_SHIFT)) & OCOTP_CTRL_CRC_TEST_MASK) +#define OCOTP_CTRL_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CRC_FAIL_MASK) +#define OCOTP_CTRL_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD1_SHIFT)) & OCOTP_CTRL_RSVD1_MASK) +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) + +/*! @name CTRL_SET - OTP Controller Control Register */ +#define OCOTP_CTRL_SET_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_SET_ADDR_SHIFT (0U) +#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) +#define OCOTP_CTRL_SET_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_SET_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD0_SHIFT)) & OCOTP_CTRL_SET_RSVD0_MASK) +#define OCOTP_CTRL_SET_BUSY_MASK (0x100U) +#define OCOTP_CTRL_SET_BUSY_SHIFT (8U) +#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) +#define OCOTP_CTRL_SET_ERROR_MASK (0x200U) +#define OCOTP_CTRL_SET_ERROR_SHIFT (9U) +#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_SET_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_SET_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_SET_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_TEST_SHIFT)) & OCOTP_CTRL_SET_CRC_TEST_MASK) +#define OCOTP_CTRL_SET_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_SET_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_SET_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_FAIL_SHIFT)) & OCOTP_CTRL_SET_CRC_FAIL_MASK) +#define OCOTP_CTRL_SET_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_SET_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD1_SHIFT)) & OCOTP_CTRL_SET_RSVD1_MASK) +#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) + +/*! @name CTRL_CLR - OTP Controller Control Register */ +#define OCOTP_CTRL_CLR_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) +#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) +#define OCOTP_CTRL_CLR_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_CLR_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD0_SHIFT)) & OCOTP_CTRL_CLR_RSVD0_MASK) +#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U) +#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U) +#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) +#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U) +#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U) +#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_CLR_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_CLR_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_CLR_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_TEST_SHIFT)) & OCOTP_CTRL_CLR_CRC_TEST_MASK) +#define OCOTP_CTRL_CLR_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_CLR_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_CLR_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CLR_CRC_FAIL_MASK) +#define OCOTP_CTRL_CLR_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_CLR_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD1_SHIFT)) & OCOTP_CTRL_CLR_RSVD1_MASK) +#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) + +/*! @name CTRL_TOG - OTP Controller Control Register */ +#define OCOTP_CTRL_TOG_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) +#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) +#define OCOTP_CTRL_TOG_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_TOG_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD0_SHIFT)) & OCOTP_CTRL_TOG_RSVD0_MASK) +#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U) +#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U) +#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) +#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U) +#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U) +#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_TOG_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_TOG_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_TOG_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_TEST_SHIFT)) & OCOTP_CTRL_TOG_CRC_TEST_MASK) +#define OCOTP_CTRL_TOG_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_TOG_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_TOG_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_FAIL_SHIFT)) & OCOTP_CTRL_TOG_CRC_FAIL_MASK) +#define OCOTP_CTRL_TOG_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_TOG_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD1_SHIFT)) & OCOTP_CTRL_TOG_RSVD1_MASK) +#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) + +/*! @name TIMING - OTP Controller Timing Register */ +#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) +#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) +#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) +#define OCOTP_TIMING_RELAX_MASK (0xF000U) +#define OCOTP_TIMING_RELAX_SHIFT (12U) +#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK) +#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U) +#define OCOTP_TIMING_STROBE_READ_SHIFT (16U) +#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK) +#define OCOTP_TIMING_WAIT_MASK (0xFC00000U) +#define OCOTP_TIMING_WAIT_SHIFT (22U) +#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) +#define OCOTP_TIMING_RSRVD0_MASK (0xF0000000U) +#define OCOTP_TIMING_RSRVD0_SHIFT (28U) +#define OCOTP_TIMING_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RSRVD0_SHIFT)) & OCOTP_TIMING_RSRVD0_MASK) + +/*! @name DATA - OTP Controller Write Data Register */ +#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_DATA_DATA_SHIFT (0U) +#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) + +/*! @name READ_CTRL - OTP Controller Read Control Register */ +#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) +#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) +#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) +#define OCOTP_READ_CTRL_RSVD0_MASK (0xFFFFFFFEU) +#define OCOTP_READ_CTRL_RSVD0_SHIFT (1U) +#define OCOTP_READ_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_RSVD0_SHIFT)) & OCOTP_READ_CTRL_RSVD0_MASK) + +/*! @name READ_FUSE_DATA - OTP Controller Read Fuse Data Register */ +#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) +#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) + +/*! @name SW_STICKY - Sticky bit Register */ +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK) +#define OCOTP_SW_STICKY_RSVD0_MASK (0xFFFFFFE0U) +#define OCOTP_SW_STICKY_RSVD0_SHIFT (5U) +#define OCOTP_SW_STICKY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_RSVD0_SHIFT)) & OCOTP_SW_STICKY_RSVD0_MASK) + +/*! @name SCS - Software Controllable Signals Register */ +#define OCOTP_SCS_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) +#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SPARE_SHIFT (1U) +#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK) +#define OCOTP_SCS_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_LOCK_SHIFT (31U) +#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) + +/*! @name SCS_SET - Software Controllable Signals Register */ +#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) +#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SET_SPARE_SHIFT (1U) +#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK) +#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_SET_LOCK_SHIFT (31U) +#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) + +/*! @name SCS_CLR - Software Controllable Signals Register */ +#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) +#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_CLR_SPARE_SHIFT (1U) +#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK) +#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_CLR_LOCK_SHIFT (31U) +#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) + +/*! @name SCS_TOG - Software Controllable Signals Register */ +#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) +#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_TOG_SPARE_SHIFT (1U) +#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK) +#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_TOG_LOCK_SHIFT (31U) +#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) + +/*! @name CRC_ADDR - OTP Controller CRC Test Address */ +#define OCOTP_CRC_ADDR_DATA_START_ADDR_MASK (0xFFU) +#define OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT (0U) +#define OCOTP_CRC_ADDR_DATA_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_START_ADDR_MASK) +#define OCOTP_CRC_ADDR_DATA_END_ADDR_MASK (0xFF00U) +#define OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT (8U) +#define OCOTP_CRC_ADDR_DATA_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_END_ADDR_MASK) +#define OCOTP_CRC_ADDR_CRC_ADDR_MASK (0x70000U) +#define OCOTP_CRC_ADDR_CRC_ADDR_SHIFT (16U) +#define OCOTP_CRC_ADDR_CRC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_CRC_ADDR_SHIFT)) & OCOTP_CRC_ADDR_CRC_ADDR_MASK) +#define OCOTP_CRC_ADDR_OTPMK_CRC_MASK (0x80000U) +#define OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT (19U) +#define OCOTP_CRC_ADDR_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT)) & OCOTP_CRC_ADDR_OTPMK_CRC_MASK) +#define OCOTP_CRC_ADDR_RSVD0_MASK (0xFFF00000U) +#define OCOTP_CRC_ADDR_RSVD0_SHIFT (20U) +#define OCOTP_CRC_ADDR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_RSVD0_SHIFT)) & OCOTP_CRC_ADDR_RSVD0_MASK) + +/*! @name CRC_VALUE - OTP Controller CRC Value Register */ +#define OCOTP_CRC_VALUE_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_CRC_VALUE_DATA_SHIFT (0U) +#define OCOTP_CRC_VALUE_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_VALUE_DATA_SHIFT)) & OCOTP_CRC_VALUE_DATA_MASK) + +/*! @name VERSION - OTP Controller Version Register */ +#define OCOTP_VERSION_STEP_MASK (0xFFFFU) +#define OCOTP_VERSION_STEP_SHIFT (0U) +#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) +#define OCOTP_VERSION_MINOR_MASK (0xFF0000U) +#define OCOTP_VERSION_MINOR_SHIFT (16U) +#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) +#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) +#define OCOTP_VERSION_MAJOR_SHIFT (24U) +#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) + +/*! @name TIMING2 - OTP Controller Timing Register 2 */ +#define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU) +#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U) +#define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK) +#define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U) +#define OCOTP_TIMING2_RELAX_READ_SHIFT (16U) +#define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK) +#define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U) +#define OCOTP_TIMING2_RELAX1_SHIFT (22U) +#define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK) + +/*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ +#define OCOTP_LOCK_TESTER_MASK (0x3U) +#define OCOTP_LOCK_TESTER_SHIFT (0U) +#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) +#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU) +#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U) +#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK) +#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U) +#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U) +#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK) +#define OCOTP_LOCK_SJC_RESP_MASK (0x40U) +#define OCOTP_LOCK_SJC_RESP_SHIFT (6U) +#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK) +#define OCOTP_LOCK_RSVD0_MASK (0x80U) +#define OCOTP_LOCK_RSVD0_SHIFT (7U) +#define OCOTP_LOCK_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_RSVD0_SHIFT)) & OCOTP_LOCK_RSVD0_MASK) +#define OCOTP_LOCK_MAC_ADDR_MASK (0x300U) +#define OCOTP_LOCK_MAC_ADDR_SHIFT (8U) +#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK) +#define OCOTP_LOCK_GP1_MASK (0xC00U) +#define OCOTP_LOCK_GP1_SHIFT (10U) +#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK) +#define OCOTP_LOCK_GP2_MASK (0x3000U) +#define OCOTP_LOCK_GP2_SHIFT (12U) +#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) +#define OCOTP_LOCK_SRK_MASK (0x4000U) +#define OCOTP_LOCK_SRK_SHIFT (14U) +#define OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK) +#define OCOTP_LOCK_GP3_MASK (0x8000U) +#define OCOTP_LOCK_GP3_SHIFT (15U) +#define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK) +#define OCOTP_LOCK_SW_GP_MASK (0x10000U) +#define OCOTP_LOCK_SW_GP_SHIFT (16U) +#define OCOTP_LOCK_SW_GP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP_SHIFT)) & OCOTP_LOCK_SW_GP_MASK) +#define OCOTP_LOCK_OTPMK_MASK (0x20000U) +#define OCOTP_LOCK_OTPMK_SHIFT (17U) +#define OCOTP_LOCK_OTPMK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_SHIFT)) & OCOTP_LOCK_OTPMK_MASK) +#define OCOTP_LOCK_ANALOG_MASK (0xC0000U) +#define OCOTP_LOCK_ANALOG_SHIFT (18U) +#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK) +#define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U) +#define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U) +#define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK) +#define OCOTP_LOCK_ROM_PATCH_MASK (0x200000U) +#define OCOTP_LOCK_ROM_PATCH_SHIFT (21U) +#define OCOTP_LOCK_ROM_PATCH(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ROM_PATCH_SHIFT)) & OCOTP_LOCK_ROM_PATCH_MASK) +#define OCOTP_LOCK_MISC_CONF_MASK (0x400000U) +#define OCOTP_LOCK_MISC_CONF_SHIFT (22U) +#define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK) +#define OCOTP_LOCK_GP4_MASK (0x800000U) +#define OCOTP_LOCK_GP4_SHIFT (23U) +#define OCOTP_LOCK_GP4(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_SHIFT)) & OCOTP_LOCK_GP4_MASK) +#define OCOTP_LOCK_PIN_MASK (0x2000000U) +#define OCOTP_LOCK_PIN_SHIFT (25U) +#define OCOTP_LOCK_PIN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_PIN_SHIFT)) & OCOTP_LOCK_PIN_MASK) +#define OCOTP_LOCK_GP4_RLOCK_MASK (0x40000000U) +#define OCOTP_LOCK_GP4_RLOCK_SHIFT (30U) +#define OCOTP_LOCK_GP4_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_RLOCK_SHIFT)) & OCOTP_LOCK_GP4_RLOCK_MASK) +#define OCOTP_LOCK_GP3_RLOCK_MASK (0x80000000U) +#define OCOTP_LOCK_GP3_RLOCK_SHIFT (31U) +#define OCOTP_LOCK_GP3_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_RLOCK_SHIFT)) & OCOTP_LOCK_GP3_RLOCK_MASK) + +/*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG0_BITS_SHIFT (0U) +#define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK) + +/*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG1_BITS_SHIFT (0U) +#define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK) + +/*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG2_BITS_SHIFT (0U) +#define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK) + +/*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG3_BITS_SHIFT (0U) +#define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK) + +/*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG4_BITS_SHIFT (0U) +#define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK) + +/*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG5_BITS_SHIFT (0U) +#define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK) + +/*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG6_BITS_SHIFT (0U) +#define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK) + +/*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */ +#define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM0_BITS_SHIFT (0U) +#define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK) + +/*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */ +#define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM1_BITS_SHIFT (0U) +#define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK) + +/*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */ +#define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM2_BITS_SHIFT (0U) +#define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK) + +/*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */ +#define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM3_BITS_SHIFT (0U) +#define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK) + +/*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */ +#define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM4_BITS_SHIFT (0U) +#define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) + +/*! @name ANA0 - Value of OTP Bank1 Word5 (Memory Related Info.) */ +#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA0_BITS_SHIFT (0U) +#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) + +/*! @name ANA1 - Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) */ +#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA1_BITS_SHIFT (0U) +#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) + +/*! @name ANA2 - Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) */ +#define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA2_BITS_SHIFT (0U) +#define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK) + +/*! @name OTPMK0 - Value of OTP Bank2 Word0 (OTPMK Key) */ +#define OCOTP_OTPMK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK0_BITS_SHIFT (0U) +#define OCOTP_OTPMK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK0_BITS_SHIFT)) & OCOTP_OTPMK0_BITS_MASK) + +/*! @name OTPMK1 - Value of OTP Bank2 Word1 (OTPMK Key) */ +#define OCOTP_OTPMK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK1_BITS_SHIFT (0U) +#define OCOTP_OTPMK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK1_BITS_SHIFT)) & OCOTP_OTPMK1_BITS_MASK) + +/*! @name OTPMK2 - Value of OTP Bank2 Word2 (OTPMK Key) */ +#define OCOTP_OTPMK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK2_BITS_SHIFT (0U) +#define OCOTP_OTPMK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK2_BITS_SHIFT)) & OCOTP_OTPMK2_BITS_MASK) + +/*! @name OTPMK3 - Value of OTP Bank2 Word3 (OTPMK Key) */ +#define OCOTP_OTPMK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK3_BITS_SHIFT (0U) +#define OCOTP_OTPMK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK3_BITS_SHIFT)) & OCOTP_OTPMK3_BITS_MASK) + +/*! @name OTPMK4 - Value of OTP Bank2 Word4 (OTPMK Key) */ +#define OCOTP_OTPMK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK4_BITS_SHIFT (0U) +#define OCOTP_OTPMK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK4_BITS_SHIFT)) & OCOTP_OTPMK4_BITS_MASK) + +/*! @name OTPMK5 - Value of OTP Bank2 Word5 (OTPMK Key) */ +#define OCOTP_OTPMK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK5_BITS_SHIFT (0U) +#define OCOTP_OTPMK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK5_BITS_SHIFT)) & OCOTP_OTPMK5_BITS_MASK) + +/*! @name OTPMK6 - Value of OTP Bank2 Word6 (OTPMK Key) */ +#define OCOTP_OTPMK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK6_BITS_SHIFT (0U) +#define OCOTP_OTPMK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK6_BITS_SHIFT)) & OCOTP_OTPMK6_BITS_MASK) + +/*! @name OTPMK7 - Value of OTP Bank2 Word7 (OTPMK Key) */ +#define OCOTP_OTPMK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK7_BITS_SHIFT (0U) +#define OCOTP_OTPMK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK7_BITS_SHIFT)) & OCOTP_OTPMK7_BITS_MASK) + +/*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */ +#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK0_BITS_SHIFT (0U) +#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) + +/*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */ +#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK1_BITS_SHIFT (0U) +#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) + +/*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */ +#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK2_BITS_SHIFT (0U) +#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) + +/*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */ +#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK3_BITS_SHIFT (0U) +#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) + +/*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */ +#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK4_BITS_SHIFT (0U) +#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) + +/*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */ +#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK5_BITS_SHIFT (0U) +#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) + +/*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */ +#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK6_BITS_SHIFT (0U) +#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) + +/*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */ +#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK7_BITS_SHIFT (0U) +#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) + +/*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ +#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP0_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) + +/*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ +#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP1_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) + +/*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */ +#define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC0_BITS_SHIFT (0U) +#define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK) + +/*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */ +#define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC1_BITS_SHIFT (0U) +#define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) + +/*! @name MAC - Value of OTP Bank4 Word4 (MAC Address) (OCOTP_RESERVED) */ +#define OCOTP_MAC_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC_BITS_SHIFT (0U) +#define OCOTP_MAC_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC_BITS_SHIFT)) & OCOTP_MAC_BITS_MASK) + +/*! @name CRC - Value of OTP Bank4 Word5 (CRC Key) */ +#define OCOTP_CRC_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CRC_BITS_SHIFT (0U) +#define OCOTP_CRC_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_BITS_SHIFT)) & OCOTP_CRC_BITS_MASK) + +/*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */ +#define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP1_BITS_SHIFT (0U) +#define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK) + +/*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */ +#define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP2_BITS_SHIFT (0U) +#define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK) + +/*! @name SW_GP0 - Value of OTP Bank5 Word0 (SW GP) */ +#define OCOTP_SW_GP0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP0_BITS_SHIFT (0U) +#define OCOTP_SW_GP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP0_BITS_SHIFT)) & OCOTP_SW_GP0_BITS_MASK) + +/*! @name SW_GP1 - Value of OTP Bank5 Word1 (SW GP) */ +#define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP1_BITS_SHIFT (0U) +#define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK) + +/*! @name SW_GP2 - Value of OTP Bank5 Word2 (SW GP) */ +#define OCOTP_SW_GP2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP2_BITS_SHIFT (0U) +#define OCOTP_SW_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP2_BITS_SHIFT)) & OCOTP_SW_GP2_BITS_MASK) + +/*! @name SW_GP3 - Value of OTP Bank5 Word3 (SW GP) */ +#define OCOTP_SW_GP3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP3_BITS_SHIFT (0U) +#define OCOTP_SW_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP3_BITS_SHIFT)) & OCOTP_SW_GP3_BITS_MASK) + +/*! @name SW_GP4 - Value of OTP Bank5 Word4 (SW GP) */ +#define OCOTP_SW_GP4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP4_BITS_SHIFT (0U) +#define OCOTP_SW_GP4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP4_BITS_SHIFT)) & OCOTP_SW_GP4_BITS_MASK) + +/*! @name MISC_CONF - Value of OTP Bank5 Word5 (Misc Conf) */ +#define OCOTP_MISC_CONF_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MISC_CONF_BITS_SHIFT (0U) +#define OCOTP_MISC_CONF_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF_BITS_SHIFT)) & OCOTP_MISC_CONF_BITS_MASK) + +/*! @name FIELD_RETURN - Value of OTP Bank5 Word6 (Field Return) */ +#define OCOTP_FIELD_RETURN_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_FIELD_RETURN_BITS_SHIFT (0U) +#define OCOTP_FIELD_RETURN_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FIELD_RETURN_BITS_SHIFT)) & OCOTP_FIELD_RETURN_BITS_MASK) + +/*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */ +#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) +#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) + +/*! @name ROM_PATCH0 - Value of OTP Bank6 Word0 (ROM Patch) */ +#define OCOTP_ROM_PATCH0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH0_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH0_BITS_SHIFT)) & OCOTP_ROM_PATCH0_BITS_MASK) + +/*! @name ROM_PATCH1 - Value of OTP Bank6 Word1 (ROM Patch) */ +#define OCOTP_ROM_PATCH1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH1_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH1_BITS_SHIFT)) & OCOTP_ROM_PATCH1_BITS_MASK) + +/*! @name ROM_PATCH2 - Value of OTP Bank6 Word2 (ROM Patch) */ +#define OCOTP_ROM_PATCH2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH2_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH2_BITS_SHIFT)) & OCOTP_ROM_PATCH2_BITS_MASK) + +/*! @name ROM_PATCH3 - Value of OTP Bank6 Word3 (ROM Patch) */ +#define OCOTP_ROM_PATCH3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH3_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH3_BITS_SHIFT)) & OCOTP_ROM_PATCH3_BITS_MASK) + +/*! @name ROM_PATCH4 - Value of OTP Bank6 Word4 (ROM Patch) */ +#define OCOTP_ROM_PATCH4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH4_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH4_BITS_SHIFT)) & OCOTP_ROM_PATCH4_BITS_MASK) + +/*! @name ROM_PATCH5 - Value of OTP Bank6 Word5 (ROM Patch) */ +#define OCOTP_ROM_PATCH5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH5_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH5_BITS_SHIFT)) & OCOTP_ROM_PATCH5_BITS_MASK) + +/*! @name ROM_PATCH6 - Value of OTP Bank6 Word6 (ROM Patch) */ +#define OCOTP_ROM_PATCH6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH6_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH6_BITS_SHIFT)) & OCOTP_ROM_PATCH6_BITS_MASK) + +/*! @name ROM_PATCH7 - Value of OTP Bank6 Word7 (ROM Patch) */ +#define OCOTP_ROM_PATCH7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH7_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH7_BITS_SHIFT)) & OCOTP_ROM_PATCH7_BITS_MASK) + +/*! @name GP3_0 - Value of OTP Bank7 Word0 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_0_BITS_SHIFT (0U) +#define OCOTP_GP3_0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_0_BITS_SHIFT)) & OCOTP_GP3_0_BITS_MASK) + +/*! @name GP3_1 - Value of OTP Bank7 Word1 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_1_BITS_SHIFT (0U) +#define OCOTP_GP3_1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_1_BITS_SHIFT)) & OCOTP_GP3_1_BITS_MASK) + +/*! @name GP3_2 - Value of OTP Bank7 Word2 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_2_BITS_SHIFT (0U) +#define OCOTP_GP3_2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_2_BITS_SHIFT)) & OCOTP_GP3_2_BITS_MASK) + +/*! @name GP3_3 - Value of OTP Bank7 Word3 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_3_BITS_SHIFT (0U) +#define OCOTP_GP3_3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_3_BITS_SHIFT)) & OCOTP_GP3_3_BITS_MASK) + +/*! @name GP3_4 - Value of OTP Bank8 Word4 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_4_BITS_SHIFT (0U) +#define OCOTP_GP3_4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_4_BITS_SHIFT)) & OCOTP_GP3_4_BITS_MASK) + +/*! @name GP4_0 - Value of OTP Bank7 Word5 (General Purpose Customer Defined Info) */ +#define OCOTP_GP4_0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP4_0_BITS_SHIFT (0U) +#define OCOTP_GP4_0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP4_0_BITS_SHIFT)) & OCOTP_GP4_0_BITS_MASK) + +/*! @name GP4_1 - Value of OTP Bank7 Word6 (General Purpose Customer Defined Info) */ +#define OCOTP_GP4_1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP4_1_BITS_SHIFT (0U) +#define OCOTP_GP4_1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP4_1_BITS_SHIFT)) & OCOTP_GP4_1_BITS_MASK) + +/*! @name GP4_2 - Value of OTP Bank7 Word7 (General Purpose Customer Defined Info) */ +#define OCOTP_GP4_2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP4_2_BITS_SHIFT (0U) +#define OCOTP_GP4_2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP4_2_BITS_SHIFT)) & OCOTP_GP4_2_BITS_MASK) + + +/*! + * @} + */ /* end of group OCOTP_Register_Masks */ + + +/* OCOTP - Peripheral instance base addresses */ +/** Peripheral OCOTP base address */ +#define OCOTP_BASE (0x21BC000u) +/** Peripheral OCOTP base pointer */ +#define OCOTP ((OCOTP_Type *)OCOTP_BASE) +/** Array initializer of OCOTP peripheral base addresses */ +#define OCOTP_BASE_ADDRS { OCOTP_BASE } +/** Array initializer of OCOTP peripheral base pointers */ +#define OCOTP_BASE_PTRS { OCOTP } + +/*! + * @} + */ /* end of group OCOTP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PGC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer + * @{ + */ + +/** PGC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MEGA_CTRL; /**< PGC Mega Control Register, offset: 0x0 */ + __IO uint32_t MEGA_PUPSCR; /**< PGC Mega Power Up Sequence Control Register, offset: 0x4 */ + __IO uint32_t MEGA_PDNSCR; /**< PGC Mega Pull Down Sequence Control Register, offset: 0x8 */ + __IO uint32_t MEGA_SR; /**< PGC Mega Power Gating Controller Status Register, offset: 0xC */ + uint8_t RESERVED_0[112]; + __IO uint32_t CPU_CTRL; /**< PGC CPU Control Register, offset: 0x80 */ + __IO uint32_t CPU_PUPSCR; /**< PGC CPU Power Up Sequence Control Register, offset: 0x84 */ + __IO uint32_t CPU_PDNSCR; /**< PGC CPU Pull Down Sequence Control Register, offset: 0x88 */ + __IO uint32_t CPU_SR; /**< PGC CPU Power Gating Controller Status Register, offset: 0x8C */ +} PGC_Type; + +/* ---------------------------------------------------------------------------- + -- PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Register_Masks PGC Register Masks + * @{ + */ + +/*! @name MEGA_CTRL - PGC Mega Control Register */ +#define PGC_MEGA_CTRL_PCR_MASK (0x1U) +#define PGC_MEGA_CTRL_PCR_SHIFT (0U) +#define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK) + +/*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */ +#define PGC_MEGA_PUPSCR_SW_MASK (0x3FU) +#define PGC_MEGA_PUPSCR_SW_SHIFT (0U) +#define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK) +#define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK) + +/*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */ +#define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU) +#define PGC_MEGA_PDNSCR_ISO_SHIFT (0U) +#define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK) +#define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK) + +/*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */ +#define PGC_MEGA_SR_PSR_MASK (0x1U) +#define PGC_MEGA_SR_PSR_SHIFT (0U) +#define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK) + +/*! @name CPU_CTRL - PGC CPU Control Register */ +#define PGC_CPU_CTRL_PCR_MASK (0x1U) +#define PGC_CPU_CTRL_PCR_SHIFT (0U) +#define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK) + +/*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */ +#define PGC_CPU_PUPSCR_SW_MASK (0x3FU) +#define PGC_CPU_PUPSCR_SW_SHIFT (0U) +#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK) +#define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK) + +/*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */ +#define PGC_CPU_PDNSCR_ISO_MASK (0x3FU) +#define PGC_CPU_PDNSCR_ISO_SHIFT (0U) +#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK) +#define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK) + +/*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */ +#define PGC_CPU_SR_PSR_MASK (0x1U) +#define PGC_CPU_SR_PSR_SHIFT (0U) +#define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) + + +/*! + * @} + */ /* end of group PGC_Register_Masks */ + + +/* PGC - Peripheral instance base addresses */ +/** Peripheral PGC base address */ +#define PGC_BASE (0x20DC220u) +/** Peripheral PGC base pointer */ +#define PGC ((PGC_Type *)PGC_BASE) +/** Array initializer of PGC peripheral base addresses */ +#define PGC_BASE_ADDRS { PGC_BASE } +/** Array initializer of PGC peripheral base pointers */ +#define PGC_BASE_PTRS { PGC } + +/*! + * @} + */ /* end of group PGC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer + * @{ + */ + +/** PMU - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG_1P1; /**< Regulator 1P1 Register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t REG_CORE; /**< Digital Regulator Core Register, offset: 0x30 */ + uint8_t RESERVED_3[300]; + __IO uint32_t LOWPWR_CTRL; /**< Low Power Control Register, offset: 0x160 */ + __IO uint32_t LOWPWR_CTRL_SET; /**< Low Power Control Register, offset: 0x164 */ + __IO uint32_t LOWPWR_CTRL_CLR; /**< Low Power Control Register, offset: 0x168 */ + __IO uint32_t LOWPWR_CTRL_TOG; /**< Low Power Control Register, offset: 0x16C */ +} PMU_Type; + +/* ---------------------------------------------------------------------------- + -- PMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Masks PMU Register Masks + * @{ + */ + +/*! @name REG_1P1 - Regulator 1P1 Register */ +#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK) +#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK) +#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK) +#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U) +#define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) + +/*! @name REG_3P0 - Regulator 3P0 Register */ +#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK) +#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK) +#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U) +#define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK) +#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK) +#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK) + +/*! @name REG_2P5 - Regulator 2P5 Register */ +#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK) +#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK) +#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK) +#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK) + +/*! @name REG_CORE - Digital Regulator Core Register */ +#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_REG0_TARG_SHIFT (0U) +#define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK) +#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_REG2_TARG_SHIFT (18U) +#define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK) +#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U) +#define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK) +#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK) + +/*! @name LOWPWR_CTRL - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK) + +/*! @name LOWPWR_CTRL_SET - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_SET_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_SET_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_SET_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_SET_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK) + +/*! @name LOWPWR_CTRL_CLR - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_CLR_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_CLR_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_CLR_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK) + +/*! @name LOWPWR_CTRL_TOG - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_TOG_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_TOG_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_TOG_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK) + + +/*! + * @} + */ /* end of group PMU_Register_Masks */ + + +/* PMU - Peripheral instance base addresses */ +/** Peripheral PMU base address */ +#define PMU_BASE (g_pmu_vbase) //(0x20C8110u) +/** Peripheral PMU base pointer */ +#define PMU ((PMU_Type *)PMU_BASE) +/** Array initializer of PMU peripheral base addresses */ +#define PMU_BASE_ADDRS { PMU_BASE } +/** Array initializer of PMU peripheral base pointers */ +#define PMU_BASE_PTRS { PMU } +/** Interrupt vectors for the PMU peripheral type */ +#define PMU_IRQS { PMU_IRQ1_IRQn, PMU_IRQ2_IRQn } + +/*! + * @} + */ /* end of group PMU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWMCR; /**< PWM Control Register, offset: 0x0 */ + __IO uint32_t PWMSR; /**< PWM Status Register, offset: 0x4 */ + __IO uint32_t PWMIR; /**< PWM Interrupt Register, offset: 0x8 */ + __IO uint32_t PWMSAR; /**< PWM Sample Register, offset: 0xC */ + __IO uint32_t PWMPR; /**< PWM Period Register, offset: 0x10 */ + __I uint32_t PWMCNR; /**< PWM Counter Register, offset: 0x14 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name PWMCR - PWM Control Register */ +#define PWM_PWMCR_EN_MASK (0x1U) +#define PWM_PWMCR_EN_SHIFT (0U) +#define PWM_PWMCR_EN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_EN_SHIFT)) & PWM_PWMCR_EN_MASK) +#define PWM_PWMCR_REPEAT_MASK (0x6U) +#define PWM_PWMCR_REPEAT_SHIFT (1U) +#define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_REPEAT_SHIFT)) & PWM_PWMCR_REPEAT_MASK) +#define PWM_PWMCR_SWR_MASK (0x8U) +#define PWM_PWMCR_SWR_SHIFT (3U) +#define PWM_PWMCR_SWR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_SWR_SHIFT)) & PWM_PWMCR_SWR_MASK) +#define PWM_PWMCR_PRESCALER_MASK (0xFFF0U) +#define PWM_PWMCR_PRESCALER_SHIFT (4U) +#define PWM_PWMCR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_PRESCALER_SHIFT)) & PWM_PWMCR_PRESCALER_MASK) +#define PWM_PWMCR_CLKSRC_MASK (0x30000U) +#define PWM_PWMCR_CLKSRC_SHIFT (16U) +#define PWM_PWMCR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_CLKSRC_SHIFT)) & PWM_PWMCR_CLKSRC_MASK) +#define PWM_PWMCR_POUTC_MASK (0xC0000U) +#define PWM_PWMCR_POUTC_SHIFT (18U) +#define PWM_PWMCR_POUTC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_POUTC_SHIFT)) & PWM_PWMCR_POUTC_MASK) +#define PWM_PWMCR_HCTR_MASK (0x100000U) +#define PWM_PWMCR_HCTR_SHIFT (20U) +#define PWM_PWMCR_HCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_HCTR_SHIFT)) & PWM_PWMCR_HCTR_MASK) +#define PWM_PWMCR_BCTR_MASK (0x200000U) +#define PWM_PWMCR_BCTR_SHIFT (21U) +#define PWM_PWMCR_BCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_BCTR_SHIFT)) & PWM_PWMCR_BCTR_MASK) +#define PWM_PWMCR_DBGEN_MASK (0x400000U) +#define PWM_PWMCR_DBGEN_SHIFT (22U) +#define PWM_PWMCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DBGEN_SHIFT)) & PWM_PWMCR_DBGEN_MASK) +#define PWM_PWMCR_WAITEN_MASK (0x800000U) +#define PWM_PWMCR_WAITEN_SHIFT (23U) +#define PWM_PWMCR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_WAITEN_SHIFT)) & PWM_PWMCR_WAITEN_MASK) +#define PWM_PWMCR_DOZEN_MASK (0x1000000U) +#define PWM_PWMCR_DOZEN_SHIFT (24U) +#define PWM_PWMCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DOZEN_SHIFT)) & PWM_PWMCR_DOZEN_MASK) +#define PWM_PWMCR_STOPEN_MASK (0x2000000U) +#define PWM_PWMCR_STOPEN_SHIFT (25U) +#define PWM_PWMCR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_STOPEN_SHIFT)) & PWM_PWMCR_STOPEN_MASK) +#define PWM_PWMCR_FWM_MASK (0xC000000U) +#define PWM_PWMCR_FWM_SHIFT (26U) +#define PWM_PWMCR_FWM(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_FWM_SHIFT)) & PWM_PWMCR_FWM_MASK) + +/*! @name PWMSR - PWM Status Register */ +#define PWM_PWMSR_FIFOAV_MASK (0x7U) +#define PWM_PWMSR_FIFOAV_SHIFT (0U) +#define PWM_PWMSR_FIFOAV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FIFOAV_SHIFT)) & PWM_PWMSR_FIFOAV_MASK) +#define PWM_PWMSR_FE_MASK (0x8U) +#define PWM_PWMSR_FE_SHIFT (3U) +#define PWM_PWMSR_FE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FE_SHIFT)) & PWM_PWMSR_FE_MASK) +#define PWM_PWMSR_ROV_MASK (0x10U) +#define PWM_PWMSR_ROV_SHIFT (4U) +#define PWM_PWMSR_ROV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_ROV_SHIFT)) & PWM_PWMSR_ROV_MASK) +#define PWM_PWMSR_CMP_MASK (0x20U) +#define PWM_PWMSR_CMP_SHIFT (5U) +#define PWM_PWMSR_CMP(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_CMP_SHIFT)) & PWM_PWMSR_CMP_MASK) +#define PWM_PWMSR_FWE_MASK (0x40U) +#define PWM_PWMSR_FWE_SHIFT (6U) +#define PWM_PWMSR_FWE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FWE_SHIFT)) & PWM_PWMSR_FWE_MASK) + +/*! @name PWMIR - PWM Interrupt Register */ +#define PWM_PWMIR_FIE_MASK (0x1U) +#define PWM_PWMIR_FIE_SHIFT (0U) +#define PWM_PWMIR_FIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_FIE_SHIFT)) & PWM_PWMIR_FIE_MASK) +#define PWM_PWMIR_RIE_MASK (0x2U) +#define PWM_PWMIR_RIE_SHIFT (1U) +#define PWM_PWMIR_RIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_RIE_SHIFT)) & PWM_PWMIR_RIE_MASK) +#define PWM_PWMIR_CIE_MASK (0x4U) +#define PWM_PWMIR_CIE_SHIFT (2U) +#define PWM_PWMIR_CIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_CIE_SHIFT)) & PWM_PWMIR_CIE_MASK) + +/*! @name PWMSAR - PWM Sample Register */ +#define PWM_PWMSAR_SAMPLE_MASK (0xFFFFU) +#define PWM_PWMSAR_SAMPLE_SHIFT (0U) +#define PWM_PWMSAR_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSAR_SAMPLE_SHIFT)) & PWM_PWMSAR_SAMPLE_MASK) + +/*! @name PWMPR - PWM Period Register */ +#define PWM_PWMPR_PERIOD_MASK (0xFFFFU) +#define PWM_PWMPR_PERIOD_SHIFT (0U) +#define PWM_PWMPR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMPR_PERIOD_SHIFT)) & PWM_PWMPR_PERIOD_MASK) + +/*! @name PWMCNR - PWM Counter Register */ +#define PWM_PWMCNR_COUNT_MASK (0xFFFFU) +#define PWM_PWMCNR_COUNT_SHIFT (0U) +#define PWM_PWMCNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCNR_COUNT_SHIFT)) & PWM_PWMCNR_COUNT_MASK) + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +/** Peripheral PWM1 base address */ +#define PWM1_BASE (0x2080000u) +/** Peripheral PWM1 base pointer */ +#define PWM1 ((PWM_Type *)PWM1_BASE) +/** Peripheral PWM2 base address */ +#define PWM2_BASE (0x2084000u) +/** Peripheral PWM2 base pointer */ +#define PWM2 ((PWM_Type *)PWM2_BASE) +/** Peripheral PWM3 base address */ +#define PWM3_BASE (0x2088000u) +/** Peripheral PWM3 base pointer */ +#define PWM3 ((PWM_Type *)PWM3_BASE) +/** Peripheral PWM4 base address */ +#define PWM4_BASE (0x208C000u) +/** Peripheral PWM4 base pointer */ +#define PWM4 ((PWM_Type *)PWM4_BASE) +/** Peripheral PWM5 base address */ +#define PWM5_BASE (0x20F0000u) +/** Peripheral PWM5 base pointer */ +#define PWM5 ((PWM_Type *)PWM5_BASE) +/** Peripheral PWM6 base address */ +#define PWM6_BASE (0x20F4000u) +/** Peripheral PWM6 base pointer */ +#define PWM6 ((PWM_Type *)PWM6_BASE) +/** Peripheral PWM7 base address */ +#define PWM7_BASE (0x20F8000u) +/** Peripheral PWM7 base pointer */ +#define PWM7 ((PWM_Type *)PWM7_BASE) +/** Peripheral PWM8 base address */ +#define PWM8_BASE (0x20FC000u) +/** Peripheral PWM8 base pointer */ +#define PWM8 ((PWM_Type *)PWM8_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE, PWM5_BASE, PWM6_BASE, PWM7_BASE, PWM8_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_IRQS { NotAvail_IRQn, PWM1_IRQn, PWM2_IRQn, PWM3_IRQn, PWM4_IRQn, PWM5_IRQn, PWM6_IRQn, PWM7_IRQn, PWM8_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PXP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer + * @{ + */ + +/** PXP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control Register 0, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< Control Register 0, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< Control Register 0, offset: 0xC */ + __IO uint32_t STAT; /**< Status Register, offset: 0x10 */ + __IO uint32_t STAT_SET; /**< Status Register, offset: 0x14 */ + __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ + __IO uint32_t STAT_TOG; /**< Status Register, offset: 0x1C */ + __IO uint32_t OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */ + __IO uint32_t OUT_CTRL_SET; /**< Output Buffer Control Register, offset: 0x24 */ + __IO uint32_t OUT_CTRL_CLR; /**< Output Buffer Control Register, offset: 0x28 */ + __IO uint32_t OUT_CTRL_TOG; /**< Output Buffer Control Register, offset: 0x2C */ + __IO uint32_t OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __IO uint32_t OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __IO uint32_t OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __IO uint32_t OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __IO uint32_t PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */ + __IO uint32_t PS_CTRL_SET; /**< Processed Surface (PS) Control Register, offset: 0xB4 */ + __IO uint32_t PS_CTRL_CLR; /**< Processed Surface (PS) Control Register, offset: 0xB8 */ + __IO uint32_t PS_CTRL_TOG; /**< Processed Surface (PS) Control Register, offset: 0xBC */ + __IO uint32_t PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t PS_BACKGROUND_0; /**< PS Background Color, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */ + uint8_t RESERVED_14[12]; + __IO uint32_t PS_CLRKEYLOW_0; /**< PS Color Key Low, offset: 0x130 */ + uint8_t RESERVED_15[12]; + __IO uint32_t PS_CLRKEYHIGH_0; /**< PS Color Key High, offset: 0x140 */ + uint8_t RESERVED_16[12]; + __IO uint32_t AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */ + uint8_t RESERVED_17[12]; + __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */ + uint8_t RESERVED_18[12]; + __IO uint32_t AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */ + uint8_t RESERVED_19[12]; + __IO uint32_t AS_CLRKEYLOW_0; /**< Overlay Color Key Low, offset: 0x180 */ + uint8_t RESERVED_20[12]; + __IO uint32_t AS_CLRKEYHIGH_0; /**< Overlay Color Key High, offset: 0x190 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */ + uint8_t RESERVED_23[12]; + __IO uint32_t CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CSC2_CTRL; /**< Color Space Conversion Control Register., offset: 0x1D0 */ + uint8_t RESERVED_25[12]; + __IO uint32_t CSC2_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1E0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t CSC2_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1F0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CSC2_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x200 */ + uint8_t RESERVED_28[12]; + __IO uint32_t CSC2_COEF3; /**< Color Space Conversion Coefficient Register 3, offset: 0x210 */ + uint8_t RESERVED_29[12]; + __IO uint32_t CSC2_COEF4; /**< Color Space Conversion Coefficient Register 4, offset: 0x220 */ + uint8_t RESERVED_30[12]; + __IO uint32_t CSC2_COEF5; /**< Color Space Conversion Coefficient Register 5, offset: 0x230 */ + uint8_t RESERVED_31[12]; + __IO uint32_t LUT_CTRL; /**< Lookup Table Control Register., offset: 0x240 */ + uint8_t RESERVED_32[12]; + __IO uint32_t LUT_ADDR; /**< Lookup Table Control Register., offset: 0x250 */ + uint8_t RESERVED_33[12]; + __IO uint32_t LUT_DATA; /**< Lookup Table Data Register., offset: 0x260 */ + uint8_t RESERVED_34[12]; + __IO uint32_t LUT_EXTMEM; /**< Lookup Table External Memory Address Register., offset: 0x270 */ + uint8_t RESERVED_35[12]; + __IO uint32_t CFA; /**< Color Filter Array Register., offset: 0x280 */ + uint8_t RESERVED_36[12]; + __IO uint32_t ALPHA_A_CTRL; /**< PXP Alpha Engine A Control Register., offset: 0x290 */ + uint8_t RESERVED_37[44]; + __IO uint32_t PS_BACKGROUND_1; /**< PS Background Color 1, offset: 0x2C0 */ + uint8_t RESERVED_38[12]; + __IO uint32_t PS_CLRKEYLOW_1; /**< PS Color Key Low 1, offset: 0x2D0 */ + uint8_t RESERVED_39[12]; + __IO uint32_t PS_CLRKEYHIGH_1; /**< PS Color Key High 1, offset: 0x2E0 */ + uint8_t RESERVED_40[12]; + __IO uint32_t AS_CLRKEYLOW_1; /**< Overlay Color Key Low, offset: 0x2F0 */ + uint8_t RESERVED_41[12]; + __IO uint32_t AS_CLRKEYHIGH_1; /**< Overlay Color Key High, offset: 0x300 */ + uint8_t RESERVED_42[12]; + __IO uint32_t CTRL2; /**< Control Register 2, offset: 0x310 */ + __IO uint32_t CTRL2_SET; /**< Control Register 2, offset: 0x314 */ + __IO uint32_t CTRL2_CLR; /**< Control Register 2, offset: 0x318 */ + __IO uint32_t CTRL2_TOG; /**< Control Register 2, offset: 0x31C */ + __IO uint32_t POWER_REG0; /**< PXP Power Control Register., offset: 0x320 */ + uint8_t RESERVED_43[12]; + __IO uint32_t POWER_REG1; /**< PXP Power Control Register 1., offset: 0x330 */ + uint8_t RESERVED_44[12]; + __IO uint32_t DATA_PATH_CTRL0; /**< This register helps decide the data path gthrough the PXP., offset: 0x340 */ + __IO uint32_t DATA_PATH_CTRL0_SET; /**< This register helps decide the data path gthrough the PXP., offset: 0x344 */ + __IO uint32_t DATA_PATH_CTRL0_CLR; /**< This register helps decide the data path gthrough the PXP., offset: 0x348 */ + __IO uint32_t DATA_PATH_CTRL0_TOG; /**< This register helps decide the data path gthrough the PXP., offset: 0x34C */ + __IO uint32_t DATA_PATH_CTRL1; /**< This register helps decide the data path gthrough the PXP., offset: 0x350 */ + __IO uint32_t DATA_PATH_CTRL1_SET; /**< This register helps decide the data path gthrough the PXP., offset: 0x354 */ + __IO uint32_t DATA_PATH_CTRL1_CLR; /**< This register helps decide the data path gthrough the PXP., offset: 0x358 */ + __IO uint32_t DATA_PATH_CTRL1_TOG; /**< This register helps decide the data path gthrough the PXP., offset: 0x35C */ + __IO uint32_t INIT_MEM_CTRL; /**< Initialize memory buffer control Register, offset: 0x360 */ + __IO uint32_t INIT_MEM_CTRL_SET; /**< Initialize memory buffer control Register, offset: 0x364 */ + __IO uint32_t INIT_MEM_CTRL_CLR; /**< Initialize memory buffer control Register, offset: 0x368 */ + __IO uint32_t INIT_MEM_CTRL_TOG; /**< Initialize memory buffer control Register, offset: 0x36C */ + __IO uint32_t INIT_MEM_DATA; /**< Write data Register, offset: 0x370 */ + uint8_t RESERVED_45[12]; + __IO uint32_t INIT_MEM_DATA_HIGH; /**< Write data Register, offset: 0x380 */ + uint8_t RESERVED_46[12]; + __IO uint32_t IRQ_MASK; /**< PXP IRQ Mask Register, offset: 0x390 */ + __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ + __IO uint32_t IRQ_MASK_CLR; /**< PXP IRQ Mask Register, offset: 0x398 */ + __IO uint32_t IRQ_MASK_TOG; /**< PXP IRQ Mask Register, offset: 0x39C */ + __IO uint32_t IRQ; /**< PXP Interrupt Register, offset: 0x3A0 */ + __IO uint32_t IRQ_SET; /**< PXP Interrupt Register, offset: 0x3A4 */ + __IO uint32_t IRQ_CLR; /**< PXP Interrupt Register, offset: 0x3A8 */ + __IO uint32_t IRQ_TOG; /**< PXP Interrupt Register, offset: 0x3AC */ + __IO uint32_t NEXT_EN; /**< PXP NEXT Buffer Enable select Register, offset: 0x3B0 */ + __IO uint32_t NEXT_EN_SET; /**< PXP NEXT Buffer Enable select Register, offset: 0x3B4 */ + __IO uint32_t NEXT_EN_CLR; /**< PXP NEXT Buffer Enable select Register, offset: 0x3B8 */ + __IO uint32_t NEXT_EN_TOG; /**< PXP NEXT Buffer Enable select Register, offset: 0x3BC */ + uint8_t RESERVED_47[64]; + __IO uint32_t NEXT; /**< Next Frame Pointer, offset: 0x400 */ + uint8_t RESERVED_48[12]; + __IO uint32_t DEBUGCTRL; /**< Debug Control Register, offset: 0x410 */ + uint8_t RESERVED_49[12]; + __I uint32_t DEBUGr; /**< Debug Register, offset: 0x420 */ + uint8_t RESERVED_50[12]; + __I uint32_t VERSION; /**< Version Register, offset: 0x430 */ + uint8_t RESERVED_51[1484]; + __IO uint32_t DITHER_STORE_SIZE_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0xA00 */ + uint8_t RESERVED_52[1788]; + __IO uint32_t WFB_FETCH_CTRL; /**< Fetch engine Control for WFE B Register, offset: 0x1100 */ + __IO uint32_t WFB_FETCH_CTRL_SET; /**< Fetch engine Control for WFE B Register, offset: 0x1104 */ + __IO uint32_t WFB_FETCH_CTRL_CLR; /**< Fetch engine Control for WFE B Register, offset: 0x1108 */ + __IO uint32_t WFB_FETCH_CTRL_TOG; /**< Fetch engine Control for WFE B Register, offset: 0x110C */ + __IO uint32_t WFB_FETCH_BUF1_ADDR; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1110 */ + uint8_t RESERVED_53[12]; + __IO uint32_t WFB_FETCH_BUF1_PITCH; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1120 */ + uint8_t RESERVED_54[12]; + __IO uint32_t WFB_FETCH_BUF1_SIZE; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1130 */ + uint8_t RESERVED_55[12]; + __IO uint32_t WFB_FETCH_BUF2_ADDR; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1140 */ + uint8_t RESERVED_56[12]; + __IO uint32_t WFB_FETCH_BUF2_PITCH; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1150 */ + uint8_t RESERVED_57[12]; + __IO uint32_t WFB_FETCH_BUF2_SIZE; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1160 */ + uint8_t RESERVED_58[12]; + __IO uint32_t WFB_ARRAY_PIXEL0_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1170 */ + uint8_t RESERVED_59[12]; + __IO uint32_t WFB_ARRAY_PIXEL1_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1180 */ + uint8_t RESERVED_60[12]; + __IO uint32_t WFB_ARRAY_PIXEL2_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1190 */ + uint8_t RESERVED_61[12]; + __IO uint32_t WFB_ARRAY_PIXEL3_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11A0 */ + uint8_t RESERVED_62[12]; + __IO uint32_t WFB_ARRAY_PIXEL4_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11B0 */ + uint8_t RESERVED_63[12]; + __IO uint32_t WFB_ARRAY_PIXEL5_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11C0 */ + uint8_t RESERVED_64[12]; + __IO uint32_t WFB_ARRAY_PIXEL6_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11D0 */ + uint8_t RESERVED_65[12]; + __IO uint32_t WFB_ARRAY_PIXEL7_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11E0 */ + uint8_t RESERVED_66[12]; + __IO uint32_t WFB_ARRAY_FLAG0_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11F0 */ + uint8_t RESERVED_67[12]; + __IO uint32_t WFB_ARRAY_FLAG1_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1200 */ + uint8_t RESERVED_68[12]; + __IO uint32_t WFB_ARRAY_FLAG2_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1210 */ + uint8_t RESERVED_69[12]; + __IO uint32_t WFB_ARRAY_FLAG3_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1220 */ + uint8_t RESERVED_70[12]; + __IO uint32_t WFB_ARRAY_FLAG4_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1230 */ + uint8_t RESERVED_71[12]; + __IO uint32_t WFB_ARRAY_FLAG5_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1240 */ + uint8_t RESERVED_72[12]; + __IO uint32_t WFB_ARRAY_FLAG6_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1250 */ + uint8_t RESERVED_73[12]; + __IO uint32_t WFB_ARRAY_FLAG7_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1260 */ + uint8_t RESERVED_74[12]; + __IO uint32_t WFB_FETCH_BUF1_CORD; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1270 */ + uint8_t RESERVED_75[12]; + __IO uint32_t WFB_FETCH_BUF2_CORD; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1280 */ + uint8_t RESERVED_76[12]; + __IO uint32_t WFB_ARRAY_FLAG8_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1290 */ + uint8_t RESERVED_77[12]; + __IO uint32_t WFB_ARRAY_FLAG9_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12A0 */ + uint8_t RESERVED_78[12]; + __IO uint32_t WFB_ARRAY_FLAG10_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12B0 */ + uint8_t RESERVED_79[12]; + __IO uint32_t WFB_ARRAY_FLAG11_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12C0 */ + uint8_t RESERVED_80[12]; + __IO uint32_t WFB_ARRAY_FLAG12_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12D0 */ + uint8_t RESERVED_81[12]; + __IO uint32_t WFB_ARRAY_FLAG13_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12E0 */ + uint8_t RESERVED_82[12]; + __IO uint32_t WFB_ARRAY_FLAG14_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12F0 */ + uint8_t RESERVED_83[12]; + __IO uint32_t WFB_ARRAY_FLAG15_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1300 */ + uint8_t RESERVED_84[12]; + __IO uint32_t WFB_ARRAY_REG0; /**< This register defines software define pixels for wfb fetch sub-block., offset: 0x1310 */ + uint8_t RESERVED_85[12]; + __IO uint32_t WFB_ARRAY_REG1; /**< This register defines software define pixels for wfb fetch sub-block., offset: 0x1320 */ + uint8_t RESERVED_86[12]; + __IO uint32_t WFB_ARRAY_REG2; /**< This register defines software define pixels for wfb fetch sub-block., offset: 0x1330 */ + uint8_t RESERVED_87[12]; + __IO uint32_t WFE_B_STORE_CTRL_CH0; /**< Store engine Control Channel 0 Register, offset: 0x1340 */ + __IO uint32_t WFE_B_STORE_CTRL_CH0_SET; /**< Store engine Control Channel 0 Register, offset: 0x1344 */ + __IO uint32_t WFE_B_STORE_CTRL_CH0_CLR; /**< Store engine Control Channel 0 Register, offset: 0x1348 */ + __IO uint32_t WFE_B_STORE_CTRL_CH0_TOG; /**< Store engine Control Channel 0 Register, offset: 0x134C */ + __IO uint32_t WFE_B_STORE_CTRL_CH1; /**< Store engine Control Channel 1 Register, offset: 0x1350 */ + __IO uint32_t WFE_B_STORE_CTRL_CH1_SET; /**< Store engine Control Channel 1 Register, offset: 0x1354 */ + __IO uint32_t WFE_B_STORE_CTRL_CH1_CLR; /**< Store engine Control Channel 1 Register, offset: 0x1358 */ + __IO uint32_t WFE_B_STORE_CTRL_CH1_TOG; /**< Store engine Control Channel 1 Register, offset: 0x135C */ + __I uint32_t WFE_B_STORE_STATUS_CH0; /**< Store engine status Channel 0 Register, offset: 0x1360 */ + uint8_t RESERVED_88[12]; + __I uint32_t WFE_B_STORE_STATUS_CH1; /**< Store engine status Channel 1 Register, offset: 0x1370 */ + uint8_t RESERVED_89[12]; + __IO uint32_t WFE_B_STORE_SIZE_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1380 */ + uint8_t RESERVED_90[12]; + __IO uint32_t WFE_B_STORE_SIZE_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1390 */ + uint8_t RESERVED_91[12]; + __IO uint32_t WFE_B_STORE_PITCH; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13A0 */ + uint8_t RESERVED_92[12]; + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13B0 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_SET; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13B4 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_CLR; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13B8 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_TOG; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13BC */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13C0 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_SET; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13C4 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_CLR; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13C8 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_TOG; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13CC */ + uint8_t RESERVED_93[64]; + __IO uint32_t WFE_B_STORE_ADDR_0_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1410 */ + uint8_t RESERVED_94[12]; + __IO uint32_t WFE_B_STORE_ADDR_1_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1420 */ + uint8_t RESERVED_95[12]; + __IO uint32_t WFE_B_STORE_FILL_DATA_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1430 */ + uint8_t RESERVED_96[12]; + __IO uint32_t WFE_B_STORE_ADDR_0_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1440 */ + uint8_t RESERVED_97[12]; + __IO uint32_t WFE_B_STORE_ADDR_1_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1450 */ + uint8_t RESERVED_98[12]; + __IO uint32_t WFE_B_STORE_D_MASK0_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1460 */ + uint8_t RESERVED_99[12]; + __IO uint32_t WFE_B_STORE_D_MASK0_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1470 */ + uint8_t RESERVED_100[12]; + __IO uint32_t WFE_B_STORE_D_MASK1_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1480 */ + uint8_t RESERVED_101[12]; + __IO uint32_t WFE_B_STORE_D_MASK1_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1490 */ + uint8_t RESERVED_102[12]; + __IO uint32_t WFE_B_STORE_D_MASK2_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14A0 */ + uint8_t RESERVED_103[12]; + __IO uint32_t WFE_B_STORE_D_MASK2_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14B0 */ + uint8_t RESERVED_104[12]; + __IO uint32_t WFE_B_STORE_D_MASK3_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14C0 */ + uint8_t RESERVED_105[12]; + __IO uint32_t WFE_B_STORE_D_MASK3_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14D0 */ + uint8_t RESERVED_106[12]; + __IO uint32_t WFE_B_STORE_D_MASK4_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14E0 */ + uint8_t RESERVED_107[12]; + __IO uint32_t WFE_B_STORE_D_MASK4_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14F0 */ + uint8_t RESERVED_108[12]; + __IO uint32_t WFE_B_STORE_D_MASK5_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1500 */ + uint8_t RESERVED_109[12]; + __IO uint32_t WFE_B_STORE_D_MASK5_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1510 */ + uint8_t RESERVED_110[12]; + __IO uint32_t WFE_B_STORE_D_MASK6_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1520 */ + uint8_t RESERVED_111[12]; + __IO uint32_t WFE_B_STORE_D_MASK6_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1530 */ + uint8_t RESERVED_112[12]; + __IO uint32_t WFE_B_STORE_D_MASK7_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1540 */ + uint8_t RESERVED_113[12]; + __IO uint32_t WFE_B_STORE_D_MASK7_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1550 */ + uint8_t RESERVED_114[12]; + __IO uint32_t WFE_B_STORE_D_SHIFT_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1560 */ + uint8_t RESERVED_115[12]; + __IO uint32_t WFE_B_STORE_D_SHIFT_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1570 */ + uint8_t RESERVED_116[12]; + __IO uint32_t WFE_B_STORE_F_SHIFT_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1580 */ + uint8_t RESERVED_117[12]; + __IO uint32_t WFE_B_STORE_F_SHIFT_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1590 */ + uint8_t RESERVED_118[12]; + __IO uint32_t WFE_B_STORE_F_MASK_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x15A0 */ + uint8_t RESERVED_119[12]; + __IO uint32_t WFE_B_STORE_F_MASK_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x15B0 */ + uint8_t RESERVED_120[28]; + __IO uint32_t FETCH_WFE_B_DEBUG; /**< This register holds the debug bits for the prefetch engine for WFE B., offset: 0x15D0 */ + uint8_t RESERVED_121[156]; + __IO uint32_t DITHER_CTRL; /**< Dither Control Register 0, offset: 0x1670 */ + __IO uint32_t DITHER_CTRL_SET; /**< Dither Control Register 0, offset: 0x1674 */ + __IO uint32_t DITHER_CTRL_CLR; /**< Dither Control Register 0, offset: 0x1678 */ + __IO uint32_t DITHER_CTRL_TOG; /**< Dither Control Register 0, offset: 0x167C */ + __IO uint32_t DITHER_FINAL_LUT_DATA0; /**< Final stage lookup value Register, offset: 0x1680 */ + __IO uint32_t DITHER_FINAL_LUT_DATA0_SET; /**< Final stage lookup value Register, offset: 0x1684 */ + __IO uint32_t DITHER_FINAL_LUT_DATA0_CLR; /**< Final stage lookup value Register, offset: 0x1688 */ + __IO uint32_t DITHER_FINAL_LUT_DATA0_TOG; /**< Final stage lookup value Register, offset: 0x168C */ + __IO uint32_t DITHER_FINAL_LUT_DATA1; /**< Final stage lookup value Register, offset: 0x1690 */ + __IO uint32_t DITHER_FINAL_LUT_DATA1_SET; /**< Final stage lookup value Register, offset: 0x1694 */ + __IO uint32_t DITHER_FINAL_LUT_DATA1_CLR; /**< Final stage lookup value Register, offset: 0x1698 */ + __IO uint32_t DITHER_FINAL_LUT_DATA1_TOG; /**< Final stage lookup value Register, offset: 0x169C */ + __IO uint32_t DITHER_FINAL_LUT_DATA2; /**< Final stage lookup value Register, offset: 0x16A0 */ + __IO uint32_t DITHER_FINAL_LUT_DATA2_SET; /**< Final stage lookup value Register, offset: 0x16A4 */ + __IO uint32_t DITHER_FINAL_LUT_DATA2_CLR; /**< Final stage lookup value Register, offset: 0x16A8 */ + __IO uint32_t DITHER_FINAL_LUT_DATA2_TOG; /**< Final stage lookup value Register, offset: 0x16AC */ + __IO uint32_t DITHER_FINAL_LUT_DATA3; /**< Final stage lookup value Register, offset: 0x16B0 */ + __IO uint32_t DITHER_FINAL_LUT_DATA3_SET; /**< Final stage lookup value Register, offset: 0x16B4 */ + __IO uint32_t DITHER_FINAL_LUT_DATA3_CLR; /**< Final stage lookup value Register, offset: 0x16B8 */ + __IO uint32_t DITHER_FINAL_LUT_DATA3_TOG; /**< Final stage lookup value Register, offset: 0x16BC */ + uint8_t RESERVED_122[1600]; + __IO uint32_t WFE_B_CTRL; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D00 */ + __IO uint32_t WFE_B_CTRL_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D04 */ + __IO uint32_t WFE_B_CTRL_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D08 */ + __IO uint32_t WFE_B_CTRL_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D0C */ + __IO uint32_t WFE_B_DIMENSIONS; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D10 */ + uint8_t RESERVED_123[12]; + __IO uint32_t WFE_B_OFFSET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D20 */ + uint8_t RESERVED_124[12]; + __IO uint32_t WFE_B_SW_DATA_REGS; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D30 */ + uint8_t RESERVED_125[12]; + __IO uint32_t WFE_B_SW_FLAG_REGS; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D40 */ + uint8_t RESERVED_126[12]; + __IO uint32_t WFE_B_STAGE1_MUX0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D50 */ + __IO uint32_t WFE_B_STAGE1_MUX0_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D54 */ + __IO uint32_t WFE_B_STAGE1_MUX0_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D58 */ + __IO uint32_t WFE_B_STAGE1_MUX0_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D5C */ + __IO uint32_t WFE_B_STAGE1_MUX1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D60 */ + __IO uint32_t WFE_B_STAGE1_MUX1_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D64 */ + __IO uint32_t WFE_B_STAGE1_MUX1_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D68 */ + __IO uint32_t WFE_B_STAGE1_MUX1_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D6C */ + __IO uint32_t WFE_B_STAGE1_MUX2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D70 */ + __IO uint32_t WFE_B_STAGE1_MUX2_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D74 */ + __IO uint32_t WFE_B_STAGE1_MUX2_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D78 */ + __IO uint32_t WFE_B_STAGE1_MUX2_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D7C */ + __IO uint32_t WFE_B_STAGE1_MUX3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D80 */ + __IO uint32_t WFE_B_STAGE1_MUX3_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D84 */ + __IO uint32_t WFE_B_STAGE1_MUX3_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D88 */ + __IO uint32_t WFE_B_STAGE1_MUX3_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D8C */ + __IO uint32_t WFE_B_STAGE1_MUX4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D90 */ + __IO uint32_t WFE_B_STAGE1_MUX4_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D94 */ + __IO uint32_t WFE_B_STAGE1_MUX4_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D98 */ + __IO uint32_t WFE_B_STAGE1_MUX4_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D9C */ + __IO uint32_t WFE_B_STAGE1_MUX5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DA0 */ + __IO uint32_t WFE_B_STAGE1_MUX5_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DA4 */ + __IO uint32_t WFE_B_STAGE1_MUX5_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DA8 */ + __IO uint32_t WFE_B_STAGE1_MUX5_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DAC */ + __IO uint32_t WFE_B_STAGE1_MUX6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DB0 */ + __IO uint32_t WFE_B_STAGE1_MUX6_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DB4 */ + __IO uint32_t WFE_B_STAGE1_MUX6_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DB8 */ + __IO uint32_t WFE_B_STAGE1_MUX6_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DBC */ + __IO uint32_t WFE_B_STAGE1_MUX7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DC0 */ + __IO uint32_t WFE_B_STAGE1_MUX7_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DC4 */ + __IO uint32_t WFE_B_STAGE1_MUX7_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DC8 */ + __IO uint32_t WFE_B_STAGE1_MUX7_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DCC */ + __IO uint32_t WFE_B_STAGE1_MUX8; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DD0 */ + __IO uint32_t WFE_B_STAGE1_MUX8_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DD4 */ + __IO uint32_t WFE_B_STAGE1_MUX8_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DD8 */ + __IO uint32_t WFE_B_STAGE1_MUX8_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DDC */ + __IO uint32_t WFE_B_STAGE2_MUX0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DE0 */ + __IO uint32_t WFE_B_STAGE2_MUX0_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DE4 */ + __IO uint32_t WFE_B_STAGE2_MUX0_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DE8 */ + __IO uint32_t WFE_B_STAGE2_MUX0_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DEC */ + __IO uint32_t WFE_B_STAGE2_MUX1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DF0 */ + __IO uint32_t WFE_B_STAGE2_MUX1_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DF4 */ + __IO uint32_t WFE_B_STAGE2_MUX1_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DF8 */ + __IO uint32_t WFE_B_STAGE2_MUX1_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DFC */ + __IO uint32_t WFE_B_STAGE2_MUX2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E00 */ + __IO uint32_t WFE_B_STAGE2_MUX2_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E04 */ + __IO uint32_t WFE_B_STAGE2_MUX2_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E08 */ + __IO uint32_t WFE_B_STAGE2_MUX2_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E0C */ + __IO uint32_t WFE_B_STAGE2_MUX3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E10 */ + __IO uint32_t WFE_B_STAGE2_MUX3_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E14 */ + __IO uint32_t WFE_B_STAGE2_MUX3_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E18 */ + __IO uint32_t WFE_B_STAGE2_MUX3_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E1C */ + __IO uint32_t WFE_B_STAGE2_MUX4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E20 */ + __IO uint32_t WFE_B_STAGE2_MUX4_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E24 */ + __IO uint32_t WFE_B_STAGE2_MUX4_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E28 */ + __IO uint32_t WFE_B_STAGE2_MUX4_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E2C */ + __IO uint32_t WFE_B_STAGE2_MUX5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E30 */ + __IO uint32_t WFE_B_STAGE2_MUX5_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E34 */ + __IO uint32_t WFE_B_STAGE2_MUX5_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E38 */ + __IO uint32_t WFE_B_STAGE2_MUX5_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E3C */ + __IO uint32_t WFE_B_STAGE2_MUX6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E40 */ + __IO uint32_t WFE_B_STAGE2_MUX6_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E44 */ + __IO uint32_t WFE_B_STAGE2_MUX6_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E48 */ + __IO uint32_t WFE_B_STAGE2_MUX6_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E4C */ + __IO uint32_t WFE_B_STAGE2_MUX7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E50 */ + __IO uint32_t WFE_B_STAGE2_MUX7_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E54 */ + __IO uint32_t WFE_B_STAGE2_MUX7_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E58 */ + __IO uint32_t WFE_B_STAGE2_MUX7_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E5C */ + __IO uint32_t WFE_B_STAGE2_MUX8; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E60 */ + __IO uint32_t WFE_B_STAGE2_MUX8_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E64 */ + __IO uint32_t WFE_B_STAGE2_MUX8_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E68 */ + __IO uint32_t WFE_B_STAGE2_MUX8_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E6C */ + __IO uint32_t WFE_B_STAGE2_MUX9; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E70 */ + __IO uint32_t WFE_B_STAGE2_MUX9_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E74 */ + __IO uint32_t WFE_B_STAGE2_MUX9_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E78 */ + __IO uint32_t WFE_B_STAGE2_MUX9_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E7C */ + __IO uint32_t WFE_B_STAGE2_MUX10; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E80 */ + __IO uint32_t WFE_B_STAGE2_MUX10_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E84 */ + __IO uint32_t WFE_B_STAGE2_MUX10_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E88 */ + __IO uint32_t WFE_B_STAGE2_MUX10_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E8C */ + __IO uint32_t WFE_B_STAGE2_MUX11; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E90 */ + __IO uint32_t WFE_B_STAGE2_MUX11_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E94 */ + __IO uint32_t WFE_B_STAGE2_MUX11_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E98 */ + __IO uint32_t WFE_B_STAGE2_MUX11_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E9C */ + __IO uint32_t WFE_B_STAGE2_MUX12; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EA0 */ + __IO uint32_t WFE_B_STAGE2_MUX12_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EA4 */ + __IO uint32_t WFE_B_STAGE2_MUX12_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EA8 */ + __IO uint32_t WFE_B_STAGE2_MUX12_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EAC */ + __IO uint32_t WFE_B_STAGE3_MUX0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EB0 */ + __IO uint32_t WFE_B_STAGE3_MUX0_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EB4 */ + __IO uint32_t WFE_B_STAGE3_MUX0_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EB8 */ + __IO uint32_t WFE_B_STAGE3_MUX0_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EBC */ + __IO uint32_t WFE_B_STAGE3_MUX1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EC0 */ + __IO uint32_t WFE_B_STAGE3_MUX1_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EC4 */ + __IO uint32_t WFE_B_STAGE3_MUX1_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EC8 */ + __IO uint32_t WFE_B_STAGE3_MUX1_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ECC */ + __IO uint32_t WFE_B_STAGE3_MUX2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ED0 */ + __IO uint32_t WFE_B_STAGE3_MUX2_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ED4 */ + __IO uint32_t WFE_B_STAGE3_MUX2_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ED8 */ + __IO uint32_t WFE_B_STAGE3_MUX2_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EDC */ + __IO uint32_t WFE_B_STAGE3_MUX3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EE0 */ + __IO uint32_t WFE_B_STAGE3_MUX3_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EE4 */ + __IO uint32_t WFE_B_STAGE3_MUX3_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EE8 */ + __IO uint32_t WFE_B_STAGE3_MUX3_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EEC */ + __IO uint32_t WFE_B_STAGE3_MUX4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EF0 */ + __IO uint32_t WFE_B_STAGE3_MUX4_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EF4 */ + __IO uint32_t WFE_B_STAGE3_MUX4_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EF8 */ + __IO uint32_t WFE_B_STAGE3_MUX4_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EFC */ + __IO uint32_t WFE_B_STAGE3_MUX5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F00 */ + __IO uint32_t WFE_B_STAGE3_MUX5_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F04 */ + __IO uint32_t WFE_B_STAGE3_MUX5_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F08 */ + __IO uint32_t WFE_B_STAGE3_MUX5_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F0C */ + __IO uint32_t WFE_B_STAGE3_MUX6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F10 */ + __IO uint32_t WFE_B_STAGE3_MUX6_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F14 */ + __IO uint32_t WFE_B_STAGE3_MUX6_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F18 */ + __IO uint32_t WFE_B_STAGE3_MUX6_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F1C */ + __IO uint32_t WFE_B_STAGE3_MUX7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F20 */ + __IO uint32_t WFE_B_STAGE3_MUX7_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F24 */ + __IO uint32_t WFE_B_STAGE3_MUX7_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F28 */ + __IO uint32_t WFE_B_STAGE3_MUX7_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F2C */ + __IO uint32_t WFE_B_STAGE3_MUX8; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F30 */ + __IO uint32_t WFE_B_STAGE3_MUX8_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F34 */ + __IO uint32_t WFE_B_STAGE3_MUX8_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F38 */ + __IO uint32_t WFE_B_STAGE3_MUX8_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F3C */ + __IO uint32_t WFE_B_STAGE3_MUX9; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F40 */ + __IO uint32_t WFE_B_STAGE3_MUX9_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F44 */ + __IO uint32_t WFE_B_STAGE3_MUX9_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F48 */ + __IO uint32_t WFE_B_STAGE3_MUX9_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F4C */ + __IO uint32_t WFE_B_STAGE3_MUX10; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F50 */ + __IO uint32_t WFE_B_STAGE3_MUX10_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F54 */ + __IO uint32_t WFE_B_STAGE3_MUX10_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F58 */ + __IO uint32_t WFE_B_STAGE3_MUX10_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F5C */ + __IO uint32_t WFE_B_STG1_5X8_OUT0_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F60 */ + uint8_t RESERVED_127[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F70 */ + uint8_t RESERVED_128[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F80 */ + uint8_t RESERVED_129[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F90 */ + uint8_t RESERVED_130[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FA0 */ + uint8_t RESERVED_131[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FB0 */ + uint8_t RESERVED_132[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FC0 */ + uint8_t RESERVED_133[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FD0 */ + uint8_t RESERVED_134[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FE0 */ + uint8_t RESERVED_135[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FF0 */ + uint8_t RESERVED_136[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2000 */ + uint8_t RESERVED_137[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2010 */ + uint8_t RESERVED_138[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2020 */ + uint8_t RESERVED_139[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2030 */ + uint8_t RESERVED_140[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2040 */ + uint8_t RESERVED_141[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2050 */ + uint8_t RESERVED_142[12]; + __IO uint32_t WFE_B_STAGE1_5X8_MASKS_0; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x8 LUT., offset: 0x2060 */ + uint8_t RESERVED_143[12]; + __IO uint32_t WFE_B_STG1_5X1_OUT0; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 1., offset: 0x2070 */ + uint8_t RESERVED_144[12]; + __IO uint32_t WFE_B_STG1_5X1_MASKS; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT., offset: 0x2080 */ + uint8_t RESERVED_145[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2090 */ + uint8_t RESERVED_146[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20A0 */ + uint8_t RESERVED_147[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20B0 */ + uint8_t RESERVED_148[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20C0 */ + uint8_t RESERVED_149[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20D0 */ + uint8_t RESERVED_150[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20E0 */ + uint8_t RESERVED_151[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20F0 */ + uint8_t RESERVED_152[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2100 */ + uint8_t RESERVED_153[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2110 */ + uint8_t RESERVED_154[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2120 */ + uint8_t RESERVED_155[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2130 */ + uint8_t RESERVED_156[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2140 */ + uint8_t RESERVED_157[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2150 */ + uint8_t RESERVED_158[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2160 */ + uint8_t RESERVED_159[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2170 */ + uint8_t RESERVED_160[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2180 */ + uint8_t RESERVED_161[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2190 */ + uint8_t RESERVED_162[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21A0 */ + uint8_t RESERVED_163[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21B0 */ + uint8_t RESERVED_164[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21C0 */ + uint8_t RESERVED_165[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21D0 */ + uint8_t RESERVED_166[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21E0 */ + uint8_t RESERVED_167[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21F0 */ + uint8_t RESERVED_168[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2200 */ + uint8_t RESERVED_169[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2210 */ + uint8_t RESERVED_170[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2220 */ + uint8_t RESERVED_171[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2230 */ + uint8_t RESERVED_172[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2240 */ + uint8_t RESERVED_173[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2250 */ + uint8_t RESERVED_174[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2260 */ + uint8_t RESERVED_175[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2270 */ + uint8_t RESERVED_176[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2280 */ + uint8_t RESERVED_177[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2290 */ + uint8_t RESERVED_178[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22A0 */ + uint8_t RESERVED_179[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22B0 */ + uint8_t RESERVED_180[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22C0 */ + uint8_t RESERVED_181[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22D0 */ + uint8_t RESERVED_182[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22E0 */ + uint8_t RESERVED_183[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22F0 */ + uint8_t RESERVED_184[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2300 */ + uint8_t RESERVED_185[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2310 */ + uint8_t RESERVED_186[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2320 */ + uint8_t RESERVED_187[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2330 */ + uint8_t RESERVED_188[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2340 */ + uint8_t RESERVED_189[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2350 */ + uint8_t RESERVED_190[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2360 */ + uint8_t RESERVED_191[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2370 */ + uint8_t RESERVED_192[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2380 */ + uint8_t RESERVED_193[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2390 */ + uint8_t RESERVED_194[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23A0 */ + uint8_t RESERVED_195[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23B0 */ + uint8_t RESERVED_196[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23C0 */ + uint8_t RESERVED_197[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23D0 */ + uint8_t RESERVED_198[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23E0 */ + uint8_t RESERVED_199[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23F0 */ + uint8_t RESERVED_200[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2400 */ + uint8_t RESERVED_201[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2410 */ + uint8_t RESERVED_202[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2420 */ + uint8_t RESERVED_203[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2430 */ + uint8_t RESERVED_204[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2440 */ + uint8_t RESERVED_205[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2450 */ + uint8_t RESERVED_206[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2460 */ + uint8_t RESERVED_207[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2470 */ + uint8_t RESERVED_208[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2480 */ + uint8_t RESERVED_209[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2490 */ + uint8_t RESERVED_210[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24A0 */ + uint8_t RESERVED_211[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24B0 */ + uint8_t RESERVED_212[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24C0 */ + uint8_t RESERVED_213[28]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24E0 */ + uint8_t RESERVED_214[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24F0 */ + uint8_t RESERVED_215[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2500 */ + uint8_t RESERVED_216[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2510 */ + uint8_t RESERVED_217[12]; + __IO uint32_t WFE_B_STAGE2_5X6_MASKS_0; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x6 LUT., offset: 0x2520 */ + uint8_t RESERVED_218[12]; + __IO uint32_t WFE_B_STAGE2_5X6_ADDR_0; /**< Each Address specifies the MUX position in the MUX array. There is one MUXADDR per 5x6 LUT., offset: 0x2530 */ + uint8_t RESERVED_219[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT0; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2540 */ + uint8_t RESERVED_220[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT1; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2550 */ + uint8_t RESERVED_221[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT2; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2560 */ + uint8_t RESERVED_222[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT3; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2570 */ + uint8_t RESERVED_223[12]; + __IO uint32_t WFE_B_STG2_5X1_MASKS; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT., offset: 0x2580 */ + uint8_t RESERVED_224[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2590 */ + uint8_t RESERVED_225[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25A0 */ + uint8_t RESERVED_226[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25B0 */ + uint8_t RESERVED_227[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25C0 */ + uint8_t RESERVED_228[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25D0 */ + uint8_t RESERVED_229[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25E0 */ + uint8_t RESERVED_230[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25F0 */ + uint8_t RESERVED_231[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2600 */ + uint8_t RESERVED_232[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2610 */ + uint8_t RESERVED_233[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2620 */ + uint8_t RESERVED_234[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2630 */ + uint8_t RESERVED_235[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2640 */ + uint8_t RESERVED_236[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2650 */ + uint8_t RESERVED_237[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2660 */ + uint8_t RESERVED_238[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2670 */ + uint8_t RESERVED_239[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2680 */ + uint8_t RESERVED_240[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2690 */ + uint8_t RESERVED_241[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26A0 */ + uint8_t RESERVED_242[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26B0 */ + uint8_t RESERVED_243[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26C0 */ + uint8_t RESERVED_244[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26D0 */ + uint8_t RESERVED_245[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26E0 */ + uint8_t RESERVED_246[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26F0 */ + uint8_t RESERVED_247[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2700 */ + uint8_t RESERVED_248[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2710 */ + uint8_t RESERVED_249[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2720 */ + uint8_t RESERVED_250[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2730 */ + uint8_t RESERVED_251[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2740 */ + uint8_t RESERVED_252[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2750 */ + uint8_t RESERVED_253[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2760 */ + uint8_t RESERVED_254[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2770 */ + uint8_t RESERVED_255[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2780 */ + uint8_t RESERVED_256[12]; + __IO uint32_t WFE_B_STG3_F8X1_MASKS; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 8x1 LUT., offset: 0x2790 */ + uint8_t RESERVED_257[268]; + __IO uint32_t ALU_B_CTRL; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28A0 */ + __IO uint32_t ALU_B_CTRL_SET; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28A4 */ + __IO uint32_t ALU_B_CTRL_CLR; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28A8 */ + __IO uint32_t ALU_B_CTRL_TOG; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28AC */ + __IO uint32_t ALU_B_BUF_SIZE; /**< This register defines the size of the buffer to be processed by the alu engine., offset: 0x28B0 */ + uint8_t RESERVED_258[12]; + __IO uint32_t ALU_B_INST_ENTRY; /**< This register defines the Entry Address for the Instruction Memory of the ALU., offset: 0x28C0 */ + uint8_t RESERVED_259[12]; + __IO uint32_t ALU_B_PARAM; /**< This register defines the parameter used by SW running on ALU., offset: 0x28D0 */ + uint8_t RESERVED_260[12]; + __IO uint32_t ALU_B_CONFIG; /**< This register defines the hw configuration options for the alu core., offset: 0x28E0 */ + uint8_t RESERVED_261[12]; + __IO uint32_t ALU_B_LUT_CONFIG; /**< This register defines the hw configuration options for the LUT, offset: 0x28F0 */ + __IO uint32_t ALU_B_LUT_CONFIG_SET; /**< This register defines the hw configuration options for the LUT, offset: 0x28F4 */ + __IO uint32_t ALU_B_LUT_CONFIG_CLR; /**< This register defines the hw configuration options for the LUT, offset: 0x28F8 */ + __IO uint32_t ALU_B_LUT_CONFIG_TOG; /**< This register defines the hw configuration options for the LUT, offset: 0x28FC */ + __IO uint32_t ALU_B_LUT_DATA0; /**< This register defines the lower 32-bit data for the LUT, offset: 0x2900 */ + uint8_t RESERVED_262[12]; + __IO uint32_t ALU_B_LUT_DATA1; /**< This register defines the higher 32-bit data for the LUT, offset: 0x2910 */ + uint8_t RESERVED_263[12]; + __IO uint32_t ALU_B_DBG; /**< This register is used for debugging alu block, offset: 0x2920 */ + uint8_t RESERVED_264[220]; + __IO uint32_t HIST_A_CTRL; /**< Histogram Control Register., offset: 0x2A00 */ + uint8_t RESERVED_265[12]; + __IO uint32_t HIST_A_MASK; /**< Histogram Pixel Mask Register., offset: 0x2A10 */ + uint8_t RESERVED_266[12]; + __IO uint32_t HIST_A_BUF_SIZE; /**< Histogram Pixel Buffer Size Register., offset: 0x2A20 */ + uint8_t RESERVED_267[12]; + __I uint32_t HIST_A_TOTAL_PIXEL; /**< Total Number of Pixels Used by Histogram Engine., offset: 0x2A30 */ + uint8_t RESERVED_268[12]; + __I uint32_t HIST_A_ACTIVE_AREA_X; /**< The X Coordinate Offset for Active Area., offset: 0x2A40 */ + uint8_t RESERVED_269[12]; + __I uint32_t HIST_A_ACTIVE_AREA_Y; /**< The Y Coordinate Offset for Active Area., offset: 0x2A50 */ + uint8_t RESERVED_270[12]; + __I uint32_t HIST_A_RAW_STAT0; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2A60 */ + uint8_t RESERVED_271[12]; + __I uint32_t HIST_A_RAW_STAT1; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2A70 */ + uint8_t RESERVED_272[12]; + __IO uint32_t HIST_B_CTRL; /**< Histogram Control Register., offset: 0x2A80 */ + uint8_t RESERVED_273[12]; + __IO uint32_t HIST_B_MASK; /**< Histogram Pixel Mask Register., offset: 0x2A90 */ + uint8_t RESERVED_274[12]; + __IO uint32_t HIST_B_BUF_SIZE; /**< Histogram Pixel Buffer Size Register., offset: 0x2AA0 */ + uint8_t RESERVED_275[12]; + __I uint32_t HIST_B_TOTAL_PIXEL; /**< Total Number of Pixels Used by Histogram Engine., offset: 0x2AB0 */ + uint8_t RESERVED_276[12]; + __I uint32_t HIST_B_ACTIVE_AREA_X; /**< The X Coordinate Offset for Active Area., offset: 0x2AC0 */ + uint8_t RESERVED_277[12]; + __I uint32_t HIST_B_ACTIVE_AREA_Y; /**< The Y Coordinate Offset for Active Area., offset: 0x2AD0 */ + uint8_t RESERVED_278[12]; + __I uint32_t HIST_B_RAW_STAT0; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AE0 */ + uint8_t RESERVED_279[12]; + __I uint32_t HIST_B_RAW_STAT1; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AF0 */ + uint8_t RESERVED_280[12]; + __IO uint32_t HIST2_PARAM; /**< 2-level Histogram Parameter Register., offset: 0x2B00 */ + uint8_t RESERVED_281[12]; + __IO uint32_t HIST4_PARAM; /**< 4-level Histogram Parameter Register., offset: 0x2B10 */ + uint8_t RESERVED_282[12]; + __IO uint32_t HIST8_PARAM0; /**< 8-level Histogram Parameter 0 Register., offset: 0x2B20 */ + uint8_t RESERVED_283[12]; + __IO uint32_t HIST8_PARAM1; /**< 8-level Histogram Parameter 1 Register., offset: 0x2B30 */ + uint8_t RESERVED_284[12]; + __IO uint32_t HIST16_PARAM0; /**< 16-level Histogram Parameter 0 Register., offset: 0x2B40 */ + uint8_t RESERVED_285[12]; + __IO uint32_t HIST16_PARAM1; /**< 16-level Histogram Parameter 1 Register., offset: 0x2B50 */ + uint8_t RESERVED_286[12]; + __IO uint32_t HIST16_PARAM2; /**< 16-level Histogram Parameter 2 Register., offset: 0x2B60 */ + uint8_t RESERVED_287[12]; + __IO uint32_t HIST16_PARAM3; /**< 16-level Histogram Parameter 3 Register., offset: 0x2B70 */ + uint8_t RESERVED_288[12]; + __IO uint32_t HIST32_PARAM0; /**< 32-level Histogram Parameter 0 Register., offset: 0x2B80 */ + uint8_t RESERVED_289[12]; + __IO uint32_t HIST32_PARAM1; /**< 32-level Histogram Parameter 1 Register., offset: 0x2B90 */ + uint8_t RESERVED_290[12]; + __IO uint32_t HIST32_PARAM2; /**< 32-level Histogram Parameter 2 Register., offset: 0x2BA0 */ + uint8_t RESERVED_291[12]; + __IO uint32_t HIST32_PARAM3; /**< 32-level Histogram Parameter 3 Register., offset: 0x2BB0 */ + uint8_t RESERVED_292[12]; + __IO uint32_t HIST32_PARAM4; /**< 32-level Histogram Parameter 0 Register., offset: 0x2BC0 */ + uint8_t RESERVED_293[12]; + __IO uint32_t HIST32_PARAM5; /**< 32-level Histogram Parameter 1 Register., offset: 0x2BD0 */ + uint8_t RESERVED_294[12]; + __IO uint32_t HIST32_PARAM6; /**< 32-level Histogram Parameter 2 Register., offset: 0x2BE0 */ + uint8_t RESERVED_295[12]; + __IO uint32_t HIST32_PARAM7; /**< 32-level Histogram Parameter 3 Register., offset: 0x2BF0 */ + uint8_t RESERVED_296[252]; + __IO uint32_t HANDSHAKE_READY_MUX0; /**< This register defines the pxp subblock handshake signals ready mux on top level., offset: 0x2CF0 */ + uint8_t RESERVED_297[12]; + __IO uint32_t HANDSHAKE_READY_MUX1; /**< This register defines the pxp subblock handshake signals ready mux on top level., offset: 0x2D00 */ + uint8_t RESERVED_298[12]; + __IO uint32_t HANDSHAKE_DONE_MUX0; /**< This register defines the pxp subblock handshake signals done mux on top level., offset: 0x2D10 */ + uint8_t RESERVED_299[12]; + __IO uint32_t HANDSHAKE_DONE_MUX1; /**< This register defines the pxp subblock handshake signals done mux on top level., offset: 0x2D20 */ +} PXP_Type; + +/* ---------------------------------------------------------------------------- + -- PXP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Register_Masks PXP Register Masks + * @{ + */ + +/*! @name CTRL - Control Register 0 */ +#define PXP_CTRL_ENABLE_MASK (0x1U) +#define PXP_CTRL_ENABLE_SHIFT (0U) +#define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK) +#define PXP_CTRL_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK) +#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_ROTATE0_MASK (0x300U) +#define PXP_CTRL_ROTATE0_SHIFT (8U) +#define PXP_CTRL_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE0_SHIFT)) & PXP_CTRL_ROTATE0_MASK) +#define PXP_CTRL_HFLIP0_MASK (0x400U) +#define PXP_CTRL_HFLIP0_SHIFT (10U) +#define PXP_CTRL_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP0_SHIFT)) & PXP_CTRL_HFLIP0_MASK) +#define PXP_CTRL_VFLIP0_MASK (0x800U) +#define PXP_CTRL_VFLIP0_SHIFT (11U) +#define PXP_CTRL_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP0_SHIFT)) & PXP_CTRL_VFLIP0_MASK) +#define PXP_CTRL_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_ROTATE1_SHIFT (12U) +#define PXP_CTRL_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE1_SHIFT)) & PXP_CTRL_ROTATE1_MASK) +#define PXP_CTRL_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_HFLIP1_SHIFT (14U) +#define PXP_CTRL_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP1_SHIFT)) & PXP_CTRL_HFLIP1_MASK) +#define PXP_CTRL_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_VFLIP1_SHIFT (15U) +#define PXP_CTRL_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP1_SHIFT)) & PXP_CTRL_VFLIP1_MASK) +#define PXP_CTRL_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_DITHER_SHIFT)) & PXP_CTRL_ENABLE_DITHER_MASK) +#define PXP_CTRL_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_ENABLE_WFE_B_MASK) +#define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK) +#define PXP_CTRL_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_CSC2_SHIFT)) & PXP_CTRL_ENABLE_CSC2_MASK) +#define PXP_CTRL_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LUT_SHIFT)) & PXP_CTRL_ENABLE_LUT_MASK) +#define PXP_CTRL_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK) +#define PXP_CTRL_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLKGATE_SHIFT (30U) +#define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK) +#define PXP_CTRL_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SFTRST_SHIFT (31U) +#define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - Control Register 0 */ +#define PXP_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK) +#define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_SET_ROTATE0_MASK (0x300U) +#define PXP_CTRL_SET_ROTATE0_SHIFT (8U) +#define PXP_CTRL_SET_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE0_SHIFT)) & PXP_CTRL_SET_ROTATE0_MASK) +#define PXP_CTRL_SET_HFLIP0_MASK (0x400U) +#define PXP_CTRL_SET_HFLIP0_SHIFT (10U) +#define PXP_CTRL_SET_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP0_SHIFT)) & PXP_CTRL_SET_HFLIP0_MASK) +#define PXP_CTRL_SET_VFLIP0_MASK (0x800U) +#define PXP_CTRL_SET_VFLIP0_SHIFT (11U) +#define PXP_CTRL_SET_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP0_SHIFT)) & PXP_CTRL_SET_VFLIP0_MASK) +#define PXP_CTRL_SET_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_SET_ROTATE1_SHIFT (12U) +#define PXP_CTRL_SET_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE1_SHIFT)) & PXP_CTRL_SET_ROTATE1_MASK) +#define PXP_CTRL_SET_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_SET_HFLIP1_SHIFT (14U) +#define PXP_CTRL_SET_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP1_SHIFT)) & PXP_CTRL_SET_HFLIP1_MASK) +#define PXP_CTRL_SET_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_SET_VFLIP1_SHIFT (15U) +#define PXP_CTRL_SET_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP1_SHIFT)) & PXP_CTRL_SET_VFLIP1_MASK) +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_SET_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_SET_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_SET_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_SET_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_DITHER_SHIFT)) & PXP_CTRL_SET_ENABLE_DITHER_MASK) +#define PXP_CTRL_SET_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_SET_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_SET_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_SET_ENABLE_WFE_B_MASK) +#define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK) +#define PXP_CTRL_SET_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_SET_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_SET_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_CSC2_SHIFT)) & PXP_CTRL_SET_ENABLE_CSC2_MASK) +#define PXP_CTRL_SET_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_SET_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_SET_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LUT_SHIFT)) & PXP_CTRL_SET_ENABLE_LUT_MASK) +#define PXP_CTRL_SET_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_SET_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_SET_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_SET_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_SET_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_SET_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_SET_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_SET_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK) +#define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_SET_CLKGATE_SHIFT (30U) +#define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK) +#define PXP_CTRL_SET_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SET_SFTRST_SHIFT (31U) +#define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - Control Register 0 */ +#define PXP_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK) +#define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_CLR_ROTATE0_MASK (0x300U) +#define PXP_CTRL_CLR_ROTATE0_SHIFT (8U) +#define PXP_CTRL_CLR_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE0_SHIFT)) & PXP_CTRL_CLR_ROTATE0_MASK) +#define PXP_CTRL_CLR_HFLIP0_MASK (0x400U) +#define PXP_CTRL_CLR_HFLIP0_SHIFT (10U) +#define PXP_CTRL_CLR_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP0_SHIFT)) & PXP_CTRL_CLR_HFLIP0_MASK) +#define PXP_CTRL_CLR_VFLIP0_MASK (0x800U) +#define PXP_CTRL_CLR_VFLIP0_SHIFT (11U) +#define PXP_CTRL_CLR_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP0_SHIFT)) & PXP_CTRL_CLR_VFLIP0_MASK) +#define PXP_CTRL_CLR_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_CLR_ROTATE1_SHIFT (12U) +#define PXP_CTRL_CLR_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE1_SHIFT)) & PXP_CTRL_CLR_ROTATE1_MASK) +#define PXP_CTRL_CLR_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_CLR_HFLIP1_SHIFT (14U) +#define PXP_CTRL_CLR_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP1_SHIFT)) & PXP_CTRL_CLR_HFLIP1_MASK) +#define PXP_CTRL_CLR_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_CLR_VFLIP1_SHIFT (15U) +#define PXP_CTRL_CLR_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP1_SHIFT)) & PXP_CTRL_CLR_VFLIP1_MASK) +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_CLR_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_CLR_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_CLR_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_CLR_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_DITHER_SHIFT)) & PXP_CTRL_CLR_ENABLE_DITHER_MASK) +#define PXP_CTRL_CLR_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_CLR_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_CLR_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_CLR_ENABLE_WFE_B_MASK) +#define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK) +#define PXP_CTRL_CLR_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_CLR_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_CLR_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_CSC2_SHIFT)) & PXP_CTRL_CLR_ENABLE_CSC2_MASK) +#define PXP_CTRL_CLR_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_CLR_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_CLR_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LUT_SHIFT)) & PXP_CTRL_CLR_ENABLE_LUT_MASK) +#define PXP_CTRL_CLR_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_CLR_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_CLR_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_CLR_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_CLR_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_CLR_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_CLR_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_CLR_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK) +#define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLR_CLKGATE_SHIFT (30U) +#define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK) +#define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_CLR_SFTRST_SHIFT (31U) +#define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - Control Register 0 */ +#define PXP_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK) +#define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_TOG_ROTATE0_MASK (0x300U) +#define PXP_CTRL_TOG_ROTATE0_SHIFT (8U) +#define PXP_CTRL_TOG_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE0_SHIFT)) & PXP_CTRL_TOG_ROTATE0_MASK) +#define PXP_CTRL_TOG_HFLIP0_MASK (0x400U) +#define PXP_CTRL_TOG_HFLIP0_SHIFT (10U) +#define PXP_CTRL_TOG_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP0_SHIFT)) & PXP_CTRL_TOG_HFLIP0_MASK) +#define PXP_CTRL_TOG_VFLIP0_MASK (0x800U) +#define PXP_CTRL_TOG_VFLIP0_SHIFT (11U) +#define PXP_CTRL_TOG_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP0_SHIFT)) & PXP_CTRL_TOG_VFLIP0_MASK) +#define PXP_CTRL_TOG_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_TOG_ROTATE1_SHIFT (12U) +#define PXP_CTRL_TOG_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE1_SHIFT)) & PXP_CTRL_TOG_ROTATE1_MASK) +#define PXP_CTRL_TOG_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_TOG_HFLIP1_SHIFT (14U) +#define PXP_CTRL_TOG_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP1_SHIFT)) & PXP_CTRL_TOG_HFLIP1_MASK) +#define PXP_CTRL_TOG_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_TOG_VFLIP1_SHIFT (15U) +#define PXP_CTRL_TOG_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP1_SHIFT)) & PXP_CTRL_TOG_VFLIP1_MASK) +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_TOG_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_TOG_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_TOG_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_TOG_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_DITHER_SHIFT)) & PXP_CTRL_TOG_ENABLE_DITHER_MASK) +#define PXP_CTRL_TOG_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_TOG_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_TOG_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_TOG_ENABLE_WFE_B_MASK) +#define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK) +#define PXP_CTRL_TOG_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_TOG_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_TOG_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_CSC2_SHIFT)) & PXP_CTRL_TOG_ENABLE_CSC2_MASK) +#define PXP_CTRL_TOG_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_TOG_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_TOG_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LUT_SHIFT)) & PXP_CTRL_TOG_ENABLE_LUT_MASK) +#define PXP_CTRL_TOG_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_TOG_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_TOG_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_TOG_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_TOG_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_TOG_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_TOG_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_TOG_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK) +#define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_TOG_CLKGATE_SHIFT (30U) +#define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK) +#define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_TOG_SFTRST_SHIFT (31U) +#define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK) + +/*! @name STAT - Status Register */ +#define PXP_STAT_IRQ0_MASK (0x1U) +#define PXP_STAT_IRQ0_SHIFT (0U) +#define PXP_STAT_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ0_SHIFT)) & PXP_STAT_IRQ0_MASK) +#define PXP_STAT_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK) +#define PXP_STAT_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_BLOCKY_SHIFT (16U) +#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK) +#define PXP_STAT_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_BLOCKX_SHIFT (24U) +#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK) + +/*! @name STAT_SET - Status Register */ +#define PXP_STAT_SET_IRQ0_MASK (0x1U) +#define PXP_STAT_SET_IRQ0_SHIFT (0U) +#define PXP_STAT_SET_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ0_SHIFT)) & PXP_STAT_SET_IRQ0_MASK) +#define PXP_STAT_SET_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_SET_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_SET_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_SET_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK) +#define PXP_STAT_SET_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_SET_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_SET_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_SET_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_SET_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_SET_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_SET_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_SET_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_SET_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_SET_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_SET_BLOCKY_SHIFT (16U) +#define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK) +#define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_SET_BLOCKX_SHIFT (24U) +#define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK) + +/*! @name STAT_CLR - Status Register */ +#define PXP_STAT_CLR_IRQ0_MASK (0x1U) +#define PXP_STAT_CLR_IRQ0_SHIFT (0U) +#define PXP_STAT_CLR_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ0_SHIFT)) & PXP_STAT_CLR_IRQ0_MASK) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_CLR_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_CLR_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_CLR_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK) +#define PXP_STAT_CLR_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_CLR_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_CLR_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_CLR_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_CLR_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_CLR_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_CLR_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_CLR_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_CLR_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_CLR_BLOCKY_SHIFT (16U) +#define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK) +#define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_CLR_BLOCKX_SHIFT (24U) +#define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK) + +/*! @name STAT_TOG - Status Register */ +#define PXP_STAT_TOG_IRQ0_MASK (0x1U) +#define PXP_STAT_TOG_IRQ0_SHIFT (0U) +#define PXP_STAT_TOG_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ0_SHIFT)) & PXP_STAT_TOG_IRQ0_MASK) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_TOG_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_TOG_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_TOG_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK) +#define PXP_STAT_TOG_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_TOG_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_TOG_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_TOG_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_TOG_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_TOG_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_TOG_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_TOG_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_TOG_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_TOG_BLOCKY_SHIFT (16U) +#define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK) +#define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_TOG_BLOCKX_SHIFT (24U) +#define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK) + +/*! @name OUT_CTRL - Output Buffer Control Register */ +#define PXP_OUT_CTRL_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK) + +/*! @name OUT_CTRL_SET - Output Buffer Control Register */ +#define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK) + +/*! @name OUT_CTRL_CLR - Output Buffer Control Register */ +#define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK) + +/*! @name OUT_CTRL_TOG - Output Buffer Control Register */ +#define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK) + +/*! @name OUT_BUF - Output Frame Buffer Pointer */ +#define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_OUT_BUF_ADDR_SHIFT (0U) +#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK) + +/*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */ +#define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU) +#define PXP_OUT_BUF2_ADDR_SHIFT (0U) +#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK) + +/*! @name OUT_PITCH - Output Buffer Pitch */ +#define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_OUT_PITCH_PITCH_SHIFT (0U) +#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK) + +/*! @name OUT_LRC - Output Surface Lower Right Coordinate */ +#define PXP_OUT_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_LRC_Y_SHIFT (0U) +#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK) +#define PXP_OUT_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_LRC_X_SHIFT (16U) +#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK) + +/*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */ +#define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU) +#define PXP_OUT_PS_ULC_Y_SHIFT (0U) +#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK) +#define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U) +#define PXP_OUT_PS_ULC_X_SHIFT (16U) +#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK) + +/*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */ +#define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_PS_LRC_Y_SHIFT (0U) +#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK) +#define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_PS_LRC_X_SHIFT (16U) +#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK) + +/*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */ +#define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU) +#define PXP_OUT_AS_ULC_Y_SHIFT (0U) +#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK) +#define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U) +#define PXP_OUT_AS_ULC_X_SHIFT (16U) +#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK) + +/*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */ +#define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_AS_LRC_Y_SHIFT (0U) +#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK) +#define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_AS_LRC_X_SHIFT (16U) +#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK) + +/*! @name PS_CTRL - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK) +#define PXP_PS_CTRL_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK) +#define PXP_PS_CTRL_DECY_MASK (0x300U) +#define PXP_PS_CTRL_DECY_SHIFT (8U) +#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK) +#define PXP_PS_CTRL_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_DECX_SHIFT (10U) +#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK) + +/*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_SET_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK) +#define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK) +#define PXP_PS_CTRL_SET_DECY_MASK (0x300U) +#define PXP_PS_CTRL_SET_DECY_SHIFT (8U) +#define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK) +#define PXP_PS_CTRL_SET_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_SET_DECX_SHIFT (10U) +#define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK) + +/*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_CLR_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK) +#define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK) +#define PXP_PS_CTRL_CLR_DECY_MASK (0x300U) +#define PXP_PS_CTRL_CLR_DECY_SHIFT (8U) +#define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK) +#define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_CLR_DECX_SHIFT (10U) +#define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK) + +/*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_TOG_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK) +#define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK) +#define PXP_PS_CTRL_TOG_DECY_MASK (0x300U) +#define PXP_PS_CTRL_TOG_DECY_SHIFT (8U) +#define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK) +#define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_TOG_DECX_SHIFT (10U) +#define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK) + +/*! @name PS_BUF - PS Input Buffer Address */ +#define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_BUF_ADDR_SHIFT (0U) +#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK) + +/*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */ +#define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_UBUF_ADDR_SHIFT (0U) +#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK) + +/*! @name PS_VBUF - PS V/Cr Input Buffer Address */ +#define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_VBUF_ADDR_SHIFT (0U) +#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK) + +/*! @name PS_PITCH - Processed Surface Pitch */ +#define PXP_PS_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_PS_PITCH_PITCH_SHIFT (0U) +#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK) + +/*! @name PS_BACKGROUND_0 - PS Background Color */ +#define PXP_PS_BACKGROUND_0_COLOR_MASK (0xFFFFFFU) +#define PXP_PS_BACKGROUND_0_COLOR_SHIFT (0U) +#define PXP_PS_BACKGROUND_0_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_0_COLOR_SHIFT)) & PXP_PS_BACKGROUND_0_COLOR_MASK) + +/*! @name PS_SCALE - PS Scale Factor Register */ +#define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU) +#define PXP_PS_SCALE_XSCALE_SHIFT (0U) +#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK) +#define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U) +#define PXP_PS_SCALE_YSCALE_SHIFT (16U) +#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK) + +/*! @name PS_OFFSET - PS Scale Offset Register */ +#define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU) +#define PXP_PS_OFFSET_XOFFSET_SHIFT (0U) +#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK) +#define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U) +#define PXP_PS_OFFSET_YOFFSET_SHIFT (16U) +#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK) + +/*! @name PS_CLRKEYLOW_0 - PS Color Key Low */ +#define PXP_PS_CLRKEYLOW_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYLOW_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_0_PIXEL_MASK) + +/*! @name PS_CLRKEYHIGH_0 - PS Color Key High */ +#define PXP_PS_CLRKEYHIGH_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYHIGH_0_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYHIGH_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_0_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_0_PIXEL_MASK) + +/*! @name AS_CTRL - Alpha Surface Control */ +#define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U) +#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U) +#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK) +#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) +#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) +#define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK) +#define PXP_AS_CTRL_FORMAT_MASK (0xF0U) +#define PXP_AS_CTRL_FORMAT_SHIFT (4U) +#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK) +#define PXP_AS_CTRL_ALPHA_MASK (0xFF00U) +#define PXP_AS_CTRL_ALPHA_SHIFT (8U) +#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK) +#define PXP_AS_CTRL_ROP_MASK (0xF0000U) +#define PXP_AS_CTRL_ROP_SHIFT (16U) +#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK) +#define PXP_AS_CTRL_ALPHA0_INVERT_MASK (0x100000U) +#define PXP_AS_CTRL_ALPHA0_INVERT_SHIFT (20U) +#define PXP_AS_CTRL_ALPHA0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA0_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA0_INVERT_MASK) +#define PXP_AS_CTRL_ALPHA1_INVERT_MASK (0x200000U) +#define PXP_AS_CTRL_ALPHA1_INVERT_SHIFT (21U) +#define PXP_AS_CTRL_ALPHA1_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA1_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA1_INVERT_MASK) + +/*! @name AS_BUF - Alpha Surface Buffer Pointer */ +#define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_AS_BUF_ADDR_SHIFT (0U) +#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK) + +/*! @name AS_PITCH - Alpha Surface Pitch */ +#define PXP_AS_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_AS_PITCH_PITCH_SHIFT (0U) +#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK) + +/*! @name AS_CLRKEYLOW_0 - Overlay Color Key Low */ +#define PXP_AS_CLRKEYLOW_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYLOW_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_0_PIXEL_MASK) + +/*! @name AS_CLRKEYHIGH_0 - Overlay Color Key High */ +#define PXP_AS_CLRKEYHIGH_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYHIGH_0_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYHIGH_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_0_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_0_PIXEL_MASK) + +/*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */ +#define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU) +#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U) +#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK) +#define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U) +#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U) +#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK) +#define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U) +#define PXP_CSC1_COEF0_C0_SHIFT (18U) +#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK) +#define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U) +#define PXP_CSC1_COEF0_BYPASS_SHIFT (30U) +#define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK) +#define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U) +#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U) +#define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK) + +/*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */ +#define PXP_CSC1_COEF1_C4_MASK (0x7FFU) +#define PXP_CSC1_COEF1_C4_SHIFT (0U) +#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK) +#define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U) +#define PXP_CSC1_COEF1_C1_SHIFT (16U) +#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK) + +/*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */ +#define PXP_CSC1_COEF2_C3_MASK (0x7FFU) +#define PXP_CSC1_COEF2_C3_SHIFT (0U) +#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK) +#define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U) +#define PXP_CSC1_COEF2_C2_SHIFT (16U) +#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK) + +/*! @name CSC2_CTRL - Color Space Conversion Control Register. */ +#define PXP_CSC2_CTRL_BYPASS_MASK (0x1U) +#define PXP_CSC2_CTRL_BYPASS_SHIFT (0U) +#define PXP_CSC2_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_CTRL_BYPASS_SHIFT)) & PXP_CSC2_CTRL_BYPASS_MASK) +#define PXP_CSC2_CTRL_CSC_MODE_MASK (0x6U) +#define PXP_CSC2_CTRL_CSC_MODE_SHIFT (1U) +#define PXP_CSC2_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_CTRL_CSC_MODE_SHIFT)) & PXP_CSC2_CTRL_CSC_MODE_MASK) + +/*! @name CSC2_COEF0 - Color Space Conversion Coefficient Register 0 */ +#define PXP_CSC2_COEF0_A1_MASK (0x7FFU) +#define PXP_CSC2_COEF0_A1_SHIFT (0U) +#define PXP_CSC2_COEF0_A1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF0_A1_SHIFT)) & PXP_CSC2_COEF0_A1_MASK) +#define PXP_CSC2_COEF0_A2_MASK (0x7FF0000U) +#define PXP_CSC2_COEF0_A2_SHIFT (16U) +#define PXP_CSC2_COEF0_A2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF0_A2_SHIFT)) & PXP_CSC2_COEF0_A2_MASK) + +/*! @name CSC2_COEF1 - Color Space Conversion Coefficient Register 1 */ +#define PXP_CSC2_COEF1_A3_MASK (0x7FFU) +#define PXP_CSC2_COEF1_A3_SHIFT (0U) +#define PXP_CSC2_COEF1_A3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF1_A3_SHIFT)) & PXP_CSC2_COEF1_A3_MASK) +#define PXP_CSC2_COEF1_B1_MASK (0x7FF0000U) +#define PXP_CSC2_COEF1_B1_SHIFT (16U) +#define PXP_CSC2_COEF1_B1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF1_B1_SHIFT)) & PXP_CSC2_COEF1_B1_MASK) + +/*! @name CSC2_COEF2 - Color Space Conversion Coefficient Register 2 */ +#define PXP_CSC2_COEF2_B2_MASK (0x7FFU) +#define PXP_CSC2_COEF2_B2_SHIFT (0U) +#define PXP_CSC2_COEF2_B2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF2_B2_SHIFT)) & PXP_CSC2_COEF2_B2_MASK) +#define PXP_CSC2_COEF2_B3_MASK (0x7FF0000U) +#define PXP_CSC2_COEF2_B3_SHIFT (16U) +#define PXP_CSC2_COEF2_B3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF2_B3_SHIFT)) & PXP_CSC2_COEF2_B3_MASK) + +/*! @name CSC2_COEF3 - Color Space Conversion Coefficient Register 3 */ +#define PXP_CSC2_COEF3_C1_MASK (0x7FFU) +#define PXP_CSC2_COEF3_C1_SHIFT (0U) +#define PXP_CSC2_COEF3_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF3_C1_SHIFT)) & PXP_CSC2_COEF3_C1_MASK) +#define PXP_CSC2_COEF3_C2_MASK (0x7FF0000U) +#define PXP_CSC2_COEF3_C2_SHIFT (16U) +#define PXP_CSC2_COEF3_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF3_C2_SHIFT)) & PXP_CSC2_COEF3_C2_MASK) + +/*! @name CSC2_COEF4 - Color Space Conversion Coefficient Register 4 */ +#define PXP_CSC2_COEF4_C3_MASK (0x7FFU) +#define PXP_CSC2_COEF4_C3_SHIFT (0U) +#define PXP_CSC2_COEF4_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF4_C3_SHIFT)) & PXP_CSC2_COEF4_C3_MASK) +#define PXP_CSC2_COEF4_D1_MASK (0x1FF0000U) +#define PXP_CSC2_COEF4_D1_SHIFT (16U) +#define PXP_CSC2_COEF4_D1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF4_D1_SHIFT)) & PXP_CSC2_COEF4_D1_MASK) + +/*! @name CSC2_COEF5 - Color Space Conversion Coefficient Register 5 */ +#define PXP_CSC2_COEF5_D2_MASK (0x1FFU) +#define PXP_CSC2_COEF5_D2_SHIFT (0U) +#define PXP_CSC2_COEF5_D2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF5_D2_SHIFT)) & PXP_CSC2_COEF5_D2_MASK) +#define PXP_CSC2_COEF5_D3_MASK (0x1FF0000U) +#define PXP_CSC2_COEF5_D3_SHIFT (16U) +#define PXP_CSC2_COEF5_D3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF5_D3_SHIFT)) & PXP_CSC2_COEF5_D3_MASK) + +/*! @name LUT_CTRL - Lookup Table Control Register. */ +#define PXP_LUT_CTRL_DMA_START_MASK (0x1U) +#define PXP_LUT_CTRL_DMA_START_SHIFT (0U) +#define PXP_LUT_CTRL_DMA_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_DMA_START_SHIFT)) & PXP_LUT_CTRL_DMA_START_MASK) +#define PXP_LUT_CTRL_INVALID_MASK (0x100U) +#define PXP_LUT_CTRL_INVALID_SHIFT (8U) +#define PXP_LUT_CTRL_INVALID(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_INVALID_SHIFT)) & PXP_LUT_CTRL_INVALID_MASK) +#define PXP_LUT_CTRL_LRU_UPD_MASK (0x200U) +#define PXP_LUT_CTRL_LRU_UPD_SHIFT (9U) +#define PXP_LUT_CTRL_LRU_UPD(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_LRU_UPD_SHIFT)) & PXP_LUT_CTRL_LRU_UPD_MASK) +#define PXP_LUT_CTRL_SEL_8KB_MASK (0x400U) +#define PXP_LUT_CTRL_SEL_8KB_SHIFT (10U) +#define PXP_LUT_CTRL_SEL_8KB(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_SEL_8KB_SHIFT)) & PXP_LUT_CTRL_SEL_8KB_MASK) +#define PXP_LUT_CTRL_OUT_MODE_MASK (0x30000U) +#define PXP_LUT_CTRL_OUT_MODE_SHIFT (16U) +#define PXP_LUT_CTRL_OUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_OUT_MODE_SHIFT)) & PXP_LUT_CTRL_OUT_MODE_MASK) +#define PXP_LUT_CTRL_LOOKUP_MODE_MASK (0x3000000U) +#define PXP_LUT_CTRL_LOOKUP_MODE_SHIFT (24U) +#define PXP_LUT_CTRL_LOOKUP_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_LOOKUP_MODE_SHIFT)) & PXP_LUT_CTRL_LOOKUP_MODE_MASK) +#define PXP_LUT_CTRL_BYPASS_MASK (0x80000000U) +#define PXP_LUT_CTRL_BYPASS_SHIFT (31U) +#define PXP_LUT_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_BYPASS_SHIFT)) & PXP_LUT_CTRL_BYPASS_MASK) + +/*! @name LUT_ADDR - Lookup Table Control Register. */ +#define PXP_LUT_ADDR_ADDR_MASK (0x3FFFU) +#define PXP_LUT_ADDR_ADDR_SHIFT (0U) +#define PXP_LUT_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_ADDR_ADDR_SHIFT)) & PXP_LUT_ADDR_ADDR_MASK) +#define PXP_LUT_ADDR_NUM_BYTES_MASK (0x7FFF0000U) +#define PXP_LUT_ADDR_NUM_BYTES_SHIFT (16U) +#define PXP_LUT_ADDR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_ADDR_NUM_BYTES_SHIFT)) & PXP_LUT_ADDR_NUM_BYTES_MASK) + +/*! @name LUT_DATA - Lookup Table Data Register. */ +#define PXP_LUT_DATA_DATA_MASK (0xFFFFFFFFU) +#define PXP_LUT_DATA_DATA_SHIFT (0U) +#define PXP_LUT_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_DATA_DATA_SHIFT)) & PXP_LUT_DATA_DATA_MASK) + +/*! @name LUT_EXTMEM - Lookup Table External Memory Address Register. */ +#define PXP_LUT_EXTMEM_ADDR_MASK (0xFFFFFFFFU) +#define PXP_LUT_EXTMEM_ADDR_SHIFT (0U) +#define PXP_LUT_EXTMEM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_EXTMEM_ADDR_SHIFT)) & PXP_LUT_EXTMEM_ADDR_MASK) + +/*! @name CFA - Color Filter Array Register. */ +#define PXP_CFA_DATA_MASK (0xFFFFFFFFU) +#define PXP_CFA_DATA_SHIFT (0U) +#define PXP_CFA_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_CFA_DATA_SHIFT)) & PXP_CFA_DATA_MASK) + +/*! @name ALPHA_A_CTRL - PXP Alpha Engine A Control Register. */ +#define PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_MASK (0x1U) +#define PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_SHIFT (0U) +#define PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_MASK) +#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U) +#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U) +#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_MASK (0x20U) +#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_SHIFT (5U) +#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE_MASK (0x40U) +#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE_SHIFT (6U) +#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_COLOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U) +#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U) +#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_MASK (0x1000U) +#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_SHIFT (12U) +#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE_MASK (0x2000U) +#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE_SHIFT (13U) +#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_COLOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MASK) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MASK) + +/*! @name PS_BACKGROUND_1 - PS Background Color 1 */ +#define PXP_PS_BACKGROUND_1_COLOR_MASK (0xFFFFFFU) +#define PXP_PS_BACKGROUND_1_COLOR_SHIFT (0U) +#define PXP_PS_BACKGROUND_1_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_1_COLOR_SHIFT)) & PXP_PS_BACKGROUND_1_COLOR_MASK) + +/*! @name PS_CLRKEYLOW_1 - PS Color Key Low 1 */ +#define PXP_PS_CLRKEYLOW_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYLOW_1_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYLOW_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_1_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_1_PIXEL_MASK) + +/*! @name PS_CLRKEYHIGH_1 - PS Color Key High 1 */ +#define PXP_PS_CLRKEYHIGH_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYHIGH_1_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYHIGH_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_1_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_1_PIXEL_MASK) + +/*! @name AS_CLRKEYLOW_1 - Overlay Color Key Low */ +#define PXP_AS_CLRKEYLOW_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYLOW_1_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYLOW_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_1_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_1_PIXEL_MASK) + +/*! @name AS_CLRKEYHIGH_1 - Overlay Color Key High */ +#define PXP_AS_CLRKEYHIGH_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYHIGH_1_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYHIGH_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_1_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_1_PIXEL_MASK) + +/*! @name CTRL2 - Control Register 2 */ +#define PXP_CTRL2_ENABLE_MASK (0x1U) +#define PXP_CTRL2_ENABLE_SHIFT (0U) +#define PXP_CTRL2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_SHIFT)) & PXP_CTRL2_ENABLE_MASK) +#define PXP_CTRL2_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ROTATE0_SHIFT)) & PXP_CTRL2_ROTATE0_MASK) +#define PXP_CTRL2_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_HFLIP0_SHIFT)) & PXP_CTRL2_HFLIP0_MASK) +#define PXP_CTRL2_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_VFLIP0_SHIFT)) & PXP_CTRL2_VFLIP0_MASK) +#define PXP_CTRL2_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ROTATE1_SHIFT)) & PXP_CTRL2_ROTATE1_MASK) +#define PXP_CTRL2_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_HFLIP1_SHIFT)) & PXP_CTRL2_HFLIP1_MASK) +#define PXP_CTRL2_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_VFLIP1_SHIFT)) & PXP_CTRL2_VFLIP1_MASK) +#define PXP_CTRL2_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_ENABLE_DITHER_MASK) +#define PXP_CTRL2_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_BLOCK_SIZE_MASK) +#define PXP_CTRL2_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_ENABLE_CSC2_MASK) +#define PXP_CTRL2_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_LUT_SHIFT)) & PXP_CTRL2_ENABLE_LUT_MASK) +#define PXP_CTRL2_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_ENABLE_ROTATE1_MASK) + +/*! @name CTRL2_SET - Control Register 2 */ +#define PXP_CTRL2_SET_ENABLE_MASK (0x1U) +#define PXP_CTRL2_SET_ENABLE_SHIFT (0U) +#define PXP_CTRL2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_SHIFT)) & PXP_CTRL2_SET_ENABLE_MASK) +#define PXP_CTRL2_SET_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_SET_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_SET_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ROTATE0_SHIFT)) & PXP_CTRL2_SET_ROTATE0_MASK) +#define PXP_CTRL2_SET_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_SET_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_SET_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_HFLIP0_SHIFT)) & PXP_CTRL2_SET_HFLIP0_MASK) +#define PXP_CTRL2_SET_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_SET_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_SET_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_VFLIP0_SHIFT)) & PXP_CTRL2_SET_VFLIP0_MASK) +#define PXP_CTRL2_SET_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_SET_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_SET_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ROTATE1_SHIFT)) & PXP_CTRL2_SET_ROTATE1_MASK) +#define PXP_CTRL2_SET_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_SET_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_SET_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_HFLIP1_SHIFT)) & PXP_CTRL2_SET_HFLIP1_MASK) +#define PXP_CTRL2_SET_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_SET_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_SET_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_VFLIP1_SHIFT)) & PXP_CTRL2_SET_VFLIP1_MASK) +#define PXP_CTRL2_SET_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_SET_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_SET_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_SET_ENABLE_DITHER_MASK) +#define PXP_CTRL2_SET_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_SET_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_SET_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_SET_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_SET_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_SET_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_SET_BLOCK_SIZE_MASK) +#define PXP_CTRL2_SET_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_SET_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_SET_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_SET_ENABLE_CSC2_MASK) +#define PXP_CTRL2_SET_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_SET_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_SET_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_LUT_SHIFT)) & PXP_CTRL2_SET_ENABLE_LUT_MASK) +#define PXP_CTRL2_SET_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_SET_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_SET_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_SET_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_SET_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_SET_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_SET_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_SET_ENABLE_ROTATE1_MASK) + +/*! @name CTRL2_CLR - Control Register 2 */ +#define PXP_CTRL2_CLR_ENABLE_MASK (0x1U) +#define PXP_CTRL2_CLR_ENABLE_SHIFT (0U) +#define PXP_CTRL2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_SHIFT)) & PXP_CTRL2_CLR_ENABLE_MASK) +#define PXP_CTRL2_CLR_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_CLR_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_CLR_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ROTATE0_SHIFT)) & PXP_CTRL2_CLR_ROTATE0_MASK) +#define PXP_CTRL2_CLR_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_CLR_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_CLR_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_HFLIP0_SHIFT)) & PXP_CTRL2_CLR_HFLIP0_MASK) +#define PXP_CTRL2_CLR_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_CLR_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_CLR_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_VFLIP0_SHIFT)) & PXP_CTRL2_CLR_VFLIP0_MASK) +#define PXP_CTRL2_CLR_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_CLR_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_CLR_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ROTATE1_SHIFT)) & PXP_CTRL2_CLR_ROTATE1_MASK) +#define PXP_CTRL2_CLR_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_CLR_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_CLR_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_HFLIP1_SHIFT)) & PXP_CTRL2_CLR_HFLIP1_MASK) +#define PXP_CTRL2_CLR_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_CLR_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_CLR_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_VFLIP1_SHIFT)) & PXP_CTRL2_CLR_VFLIP1_MASK) +#define PXP_CTRL2_CLR_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_CLR_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_CLR_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_CLR_ENABLE_DITHER_MASK) +#define PXP_CTRL2_CLR_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_CLR_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_CLR_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_CLR_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_CLR_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_CLR_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_CLR_BLOCK_SIZE_MASK) +#define PXP_CTRL2_CLR_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_CLR_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_CLR_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_CLR_ENABLE_CSC2_MASK) +#define PXP_CTRL2_CLR_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_CLR_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_CLR_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_LUT_SHIFT)) & PXP_CTRL2_CLR_ENABLE_LUT_MASK) +#define PXP_CTRL2_CLR_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_CLR_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_CLR_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_CLR_ENABLE_ROTATE1_MASK) + +/*! @name CTRL2_TOG - Control Register 2 */ +#define PXP_CTRL2_TOG_ENABLE_MASK (0x1U) +#define PXP_CTRL2_TOG_ENABLE_SHIFT (0U) +#define PXP_CTRL2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_SHIFT)) & PXP_CTRL2_TOG_ENABLE_MASK) +#define PXP_CTRL2_TOG_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_TOG_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_TOG_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ROTATE0_SHIFT)) & PXP_CTRL2_TOG_ROTATE0_MASK) +#define PXP_CTRL2_TOG_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_TOG_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_TOG_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_HFLIP0_SHIFT)) & PXP_CTRL2_TOG_HFLIP0_MASK) +#define PXP_CTRL2_TOG_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_TOG_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_TOG_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_VFLIP0_SHIFT)) & PXP_CTRL2_TOG_VFLIP0_MASK) +#define PXP_CTRL2_TOG_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_TOG_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_TOG_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ROTATE1_SHIFT)) & PXP_CTRL2_TOG_ROTATE1_MASK) +#define PXP_CTRL2_TOG_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_TOG_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_TOG_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_HFLIP1_SHIFT)) & PXP_CTRL2_TOG_HFLIP1_MASK) +#define PXP_CTRL2_TOG_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_TOG_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_TOG_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_VFLIP1_SHIFT)) & PXP_CTRL2_TOG_VFLIP1_MASK) +#define PXP_CTRL2_TOG_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_TOG_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_TOG_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_TOG_ENABLE_DITHER_MASK) +#define PXP_CTRL2_TOG_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_TOG_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_TOG_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_TOG_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_TOG_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_TOG_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_TOG_BLOCK_SIZE_MASK) +#define PXP_CTRL2_TOG_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_TOG_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_TOG_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_TOG_ENABLE_CSC2_MASK) +#define PXP_CTRL2_TOG_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_TOG_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_TOG_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_LUT_SHIFT)) & PXP_CTRL2_TOG_ENABLE_LUT_MASK) +#define PXP_CTRL2_TOG_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_TOG_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_TOG_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_TOG_ENABLE_ROTATE1_MASK) + +/*! @name POWER_REG0 - PXP Power Control Register. */ +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_MASK (0x7U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_SHIFT (0U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_MASK) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_MASK (0x38U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_SHIFT (3U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_MASK) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_MASK (0x1C0U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_SHIFT (6U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_MASK) +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK (0xE00U) +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT (9U) +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK) +#define PXP_POWER_REG0_CTRL_MASK (0xFFFFF000U) +#define PXP_POWER_REG0_CTRL_SHIFT (12U) +#define PXP_POWER_REG0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_CTRL_SHIFT)) & PXP_POWER_REG0_CTRL_MASK) + +/*! @name POWER_REG1 - PXP Power Control Register 1. */ +#define PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK (0x7U) +#define PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT (0U) +#define PXP_POWER_REG1_ROT1_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_MASK (0x38U) +#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_SHIFT (3U) +#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_MASK (0x1C0U) +#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_SHIFT (6U) +#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_MASK (0xE00U) +#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_SHIFT (9U) +#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_MASK (0x7000U) +#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_SHIFT (12U) +#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_MASK (0x38000U) +#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_SHIFT (15U) +#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE_MASK (0x1C0000U) +#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE_SHIFT (18U) +#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ALU_A_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ALU_A_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE_MASK (0xE00000U) +#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE_SHIFT (21U) +#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ALU_B_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ALU_B_MEM_LP_STATE_MASK) + +/*! @name DATA_PATH_CTRL0 - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL0_SET - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL0_CLR - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL0_TOG - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL1 - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_MUX17_SEL_MASK) + +/*! @name DATA_PATH_CTRL1_SET - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_MASK) + +/*! @name DATA_PATH_CTRL1_CLR - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_MASK) + +/*! @name DATA_PATH_CTRL1_TOG - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_MASK) + +/*! @name INIT_MEM_CTRL - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_START_SHIFT)) & PXP_INIT_MEM_CTRL_START_MASK) + +/*! @name INIT_MEM_CTRL_SET - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_SET_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_SET_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_SET_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_SET_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_SET_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_SET_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_SET_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_SET_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_SET_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_SET_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_START_SHIFT)) & PXP_INIT_MEM_CTRL_SET_START_MASK) + +/*! @name INIT_MEM_CTRL_CLR - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_CLR_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_CLR_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_CLR_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_CLR_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_CLR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_CLR_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_CLR_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_START_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_START_MASK) + +/*! @name INIT_MEM_CTRL_TOG - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_TOG_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_TOG_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_TOG_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_TOG_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_TOG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_TOG_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_TOG_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_START_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_START_MASK) + +/*! @name INIT_MEM_DATA - Write data Register */ +#define PXP_INIT_MEM_DATA_DATA_MASK (0xFFFFFFFFU) +#define PXP_INIT_MEM_DATA_DATA_SHIFT (0U) +#define PXP_INIT_MEM_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_DATA_DATA_SHIFT)) & PXP_INIT_MEM_DATA_DATA_MASK) + +/*! @name INIT_MEM_DATA_HIGH - Write data Register */ +#define PXP_INIT_MEM_DATA_HIGH_DATA_MASK (0xFFFFFFFFU) +#define PXP_INIT_MEM_DATA_HIGH_DATA_SHIFT (0U) +#define PXP_INIT_MEM_DATA_HIGH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_DATA_HIGH_DATA_SHIFT)) & PXP_INIT_MEM_DATA_HIGH_DATA_MASK) + +/*! @name IRQ_MASK - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ_MASK_SET - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ_MASK_CLR - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ_MASK_TOG - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ - PXP Interrupt Register */ +#define PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_STORE_IRQ_MASK) + +/*! @name IRQ_SET - PXP Interrupt Register */ +#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_SET_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_SET_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_SET_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_STORE_IRQ_MASK) + +/*! @name IRQ_CLR - PXP Interrupt Register */ +#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_CLR_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_CLR_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_CLR_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_STORE_IRQ_MASK) + +/*! @name IRQ_TOG - PXP Interrupt Register */ +#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_TOG_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_TOG_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_TOG_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_STORE_IRQ_MASK) + +/*! @name NEXT_EN - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_LEGACY_SHIFT)) & PXP_NEXT_EN_LEGACY_MASK) +#define PXP_NEXT_EN_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_WFEB_SHIFT)) & PXP_NEXT_EN_WFEB_MASK) + +/*! @name NEXT_EN_SET - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_SET_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_SET_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_SET_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_SET_LEGACY_SHIFT)) & PXP_NEXT_EN_SET_LEGACY_MASK) +#define PXP_NEXT_EN_SET_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_SET_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_SET_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_SET_WFEB_SHIFT)) & PXP_NEXT_EN_SET_WFEB_MASK) + +/*! @name NEXT_EN_CLR - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_CLR_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_CLR_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_CLR_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_CLR_LEGACY_SHIFT)) & PXP_NEXT_EN_CLR_LEGACY_MASK) +#define PXP_NEXT_EN_CLR_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_CLR_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_CLR_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_CLR_WFEB_SHIFT)) & PXP_NEXT_EN_CLR_WFEB_MASK) + +/*! @name NEXT_EN_TOG - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_TOG_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_TOG_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_TOG_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_TOG_LEGACY_SHIFT)) & PXP_NEXT_EN_TOG_LEGACY_MASK) +#define PXP_NEXT_EN_TOG_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_TOG_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_TOG_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_TOG_WFEB_SHIFT)) & PXP_NEXT_EN_TOG_WFEB_MASK) + +/*! @name NEXT - Next Frame Pointer */ +#define PXP_NEXT_ENABLED_MASK (0x1U) +#define PXP_NEXT_ENABLED_SHIFT (0U) +#define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK) +#define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU) +#define PXP_NEXT_POINTER_SHIFT (2U) +#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK) + +/*! @name DEBUGCTRL - Debug Control Register */ +#define PXP_DEBUGCTRL_SELECT_MASK (0xFFU) +#define PXP_DEBUGCTRL_SELECT_SHIFT (0U) +#define PXP_DEBUGCTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DEBUGCTRL_SELECT_SHIFT)) & PXP_DEBUGCTRL_SELECT_MASK) +#define PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_MASK (0xF00U) +#define PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_SHIFT (8U) +#define PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_SHIFT)) & PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_MASK) + +/*! @name DEBUG - Debug Register */ +#define PXP_DEBUG_DATA_MASK (0xFFFFFFFFU) +#define PXP_DEBUG_DATA_SHIFT (0U) +#define PXP_DEBUG_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_DEBUG_DATA_SHIFT)) & PXP_DEBUG_DATA_MASK) + +/*! @name VERSION - Version Register */ +#define PXP_VERSION_STEP_MASK (0xFFFFU) +#define PXP_VERSION_STEP_SHIFT (0U) +#define PXP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << PXP_VERSION_STEP_SHIFT)) & PXP_VERSION_STEP_MASK) +#define PXP_VERSION_MINOR_MASK (0xFF0000U) +#define PXP_VERSION_MINOR_SHIFT (16U) +#define PXP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_VERSION_MINOR_SHIFT)) & PXP_VERSION_MINOR_MASK) +#define PXP_VERSION_MAJOR_MASK (0xFF000000U) +#define PXP_VERSION_MAJOR_SHIFT (24U) +#define PXP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_VERSION_MAJOR_SHIFT)) & PXP_VERSION_MAJOR_MASK) + +/*! @name DITHER_STORE_SIZE_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK (0xFFFFU) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_SHIFT (0U) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_SHIFT)) & PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_MASK (0xFFFF0000U) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT (16U) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT)) & PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_MASK) + +/*! @name WFB_FETCH_CTRL - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_CTRL_SET - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_SET_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_CTRL_CLR - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_CLR_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_CTRL_TOG - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_TOG_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_BUF1_ADDR - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_SHIFT)) & PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_MASK) + +/*! @name WFB_FETCH_BUF1_PITCH - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF1_PITCH_PITCH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_PITCH_PITCH_SHIFT)) & PXP_WFB_FETCH_BUF1_PITCH_PITCH_MASK) + +/*! @name WFB_FETCH_BUF1_SIZE - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_SHIFT)) & PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_MASK) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_SHIFT (16U) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_SHIFT)) & PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_MASK) + +/*! @name WFB_FETCH_BUF2_ADDR - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_SHIFT)) & PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_MASK) + +/*! @name WFB_FETCH_BUF2_PITCH - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF2_PITCH_PITCH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_PITCH_PITCH_SHIFT)) & PXP_WFB_FETCH_BUF2_PITCH_PITCH_MASK) + +/*! @name WFB_FETCH_BUF2_SIZE - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_SHIFT)) & PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_MASK) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_SHIFT (16U) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_SHIFT)) & PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_MASK) + +/*! @name WFB_ARRAY_PIXEL0_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL1_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL2_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL3_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL4_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL5_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL6_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL7_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG0_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG1_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG1_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG1_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG2_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG2_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG2_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG3_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG3_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG3_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG4_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG4_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG4_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG5_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG5_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG5_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG6_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG6_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG6_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG7_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG7_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG7_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_MASK) + +/*! @name WFB_FETCH_BUF1_CORD - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_CORD_XCORD_MASK (0x3FFFU) +#define PXP_WFB_FETCH_BUF1_CORD_XCORD_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_CORD_XCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_CORD_XCORD_SHIFT)) & PXP_WFB_FETCH_BUF1_CORD_XCORD_MASK) +#define PXP_WFB_FETCH_BUF1_CORD_YCORD_MASK (0x3FFF0000U) +#define PXP_WFB_FETCH_BUF1_CORD_YCORD_SHIFT (16U) +#define PXP_WFB_FETCH_BUF1_CORD_YCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_CORD_YCORD_SHIFT)) & PXP_WFB_FETCH_BUF1_CORD_YCORD_MASK) + +/*! @name WFB_FETCH_BUF2_CORD - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_CORD_XCORD_MASK (0x3FFFU) +#define PXP_WFB_FETCH_BUF2_CORD_XCORD_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_CORD_XCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_CORD_XCORD_SHIFT)) & PXP_WFB_FETCH_BUF2_CORD_XCORD_MASK) +#define PXP_WFB_FETCH_BUF2_CORD_YCORD_MASK (0x3FFF0000U) +#define PXP_WFB_FETCH_BUF2_CORD_YCORD_SHIFT (16U) +#define PXP_WFB_FETCH_BUF2_CORD_YCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_CORD_YCORD_SHIFT)) & PXP_WFB_FETCH_BUF2_CORD_YCORD_MASK) + +/*! @name WFB_ARRAY_FLAG8_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG8_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG8_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG9_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG9_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG9_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG10_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG10_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG10_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG11_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG11_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG11_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG12_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG12_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG12_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG13_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG13_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG13_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG14_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG14_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG14_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG15_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG15_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG15_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_REG0 - This register defines software define pixels for wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_REG0_SW_PIXLE0_MASK (0xFFU) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE0_SHIFT (0U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE0_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE0_MASK) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE1_MASK (0xFF00U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE1_SHIFT (8U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE1_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE1_MASK) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE2_MASK (0xFF0000U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE2_SHIFT (16U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE2_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE2_MASK) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE3_MASK (0xFF000000U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE3_SHIFT (24U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE3_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE3_MASK) + +/*! @name WFB_ARRAY_REG1 - This register defines software define pixels for wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_REG1_SW_PIXLE4_MASK (0xFFU) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE4_SHIFT (0U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE4_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE4_MASK) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE5_MASK (0xFF00U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE5_SHIFT (8U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE5_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE5_MASK) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE6_MASK (0xFF0000U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE6_SHIFT (16U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE6_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE6_MASK) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE7_MASK (0xFF000000U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE7_SHIFT (24U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE7_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE7_MASK) + +/*! @name WFB_ARRAY_REG2 - This register defines software define pixels for wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_REG2_SW_FLAG0_MASK (0x1U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG0_SHIFT (0U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG0_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG0_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG1_MASK (0x2U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG1_SHIFT (1U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG1_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG1_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG2_MASK (0x4U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG2_SHIFT (2U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG2_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG2_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG3_MASK (0x8U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG3_SHIFT (3U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG3_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG3_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG4_MASK (0x10U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG4_SHIFT (4U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG4_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG4_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG5_MASK (0x20U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG5_SHIFT (5U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG5_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG5_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG6_MASK (0x40U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG6_SHIFT (6U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG6_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG6_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG7_MASK (0x80U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG7_SHIFT (7U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG7_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG7_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG8_MASK (0x100U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG8_SHIFT (8U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG8_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG8_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG9_MASK (0x200U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG9_SHIFT (9U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG9_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG9_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG10_MASK (0x400U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG10_SHIFT (10U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG10_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG10_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG11_MASK (0x800U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG11_SHIFT (11U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG11_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG11_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG12_MASK (0x1000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG12_SHIFT (12U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG12_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG12_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG13_MASK (0x2000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG13_SHIFT (13U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG13_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG13_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG14_MASK (0x4000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG14_SHIFT (14U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG14_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG14_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG15_MASK (0x8000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG15_SHIFT (15U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG15_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG15_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0 - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0_SET - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0_CLR - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0_TOG - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1 - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1_SET - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1_CLR - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1_TOG - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_STATUS_CH0 - Store engine status Channel 0 Register */ +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT (0U) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_MASK) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT (16U) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK) + +/*! @name WFE_B_STORE_STATUS_CH1 - Store engine status Channel 1 Register */ +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT (0U) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_MASK) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT (16U) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK) + +/*! @name WFE_B_STORE_SIZE_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_SHIFT (0U) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_MASK) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT (16U) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_MASK) + +/*! @name WFE_B_STORE_SIZE_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_SHIFT (0U) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_MASK) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT (16U) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_MASK) + +/*! @name WFE_B_STORE_PITCH - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_SHIFT (0U) +#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_SHIFT)) & PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_MASK) +#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_SHIFT (16U) +#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_SHIFT)) & PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_SET - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_CLR - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_TOG - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_SET - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_CLR - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_TOG - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_ADDR_0_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT)) & PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK) + +/*! @name WFE_B_STORE_ADDR_1_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT)) & PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK) + +/*! @name WFE_B_STORE_FILL_DATA_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT)) & PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK) + +/*! @name WFE_B_STORE_ADDR_0_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT)) & PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK) + +/*! @name WFE_B_STORE_ADDR_1_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT)) & PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK) + +/*! @name WFE_B_STORE_D_MASK0_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK0_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK1_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK1_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK2_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK2_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK3_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK3_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK4_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK4_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK5_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK5_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK6_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK6_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK7_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK7_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_SHIFT_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK (0x3FU) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK (0x80U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT (7U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK (0x3F00U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT (8U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK (0x8000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT (15U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT (16U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK (0x800000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT (23U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT (24U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK (0x80000000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT (31U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK) + +/*! @name WFE_B_STORE_D_SHIFT_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK (0x3FU) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT (0U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK (0x80U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT (7U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK (0x3F00U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT (8U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK (0x8000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT (15U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT (16U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK (0x800000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT (23U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT (24U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK (0x80000000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT (31U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK) + +/*! @name WFE_B_STORE_F_SHIFT_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK (0x3FU) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT (0U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK (0x40U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT (6U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK (0x3F00U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT (8U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK (0x4000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT (14U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT (16U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK (0x400000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT (22U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT (24U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK (0x40000000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT (30U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK) + +/*! @name WFE_B_STORE_F_SHIFT_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK (0x3FU) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT (0U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK (0x40U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT (6U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK (0x3F00U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT (8U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK (0x4000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT (14U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT (16U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK (0x400000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT (22U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT (24U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK (0x40000000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT (30U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK) + +/*! @name WFE_B_STORE_F_MASK_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_MASK (0xFFU) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_SHIFT (0U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_MASK) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_MASK (0xFF00U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_SHIFT (8U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_MASK) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_MASK (0xFF0000U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_SHIFT (16U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_MASK) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_MASK (0xFF000000U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_SHIFT (24U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_MASK) + +/*! @name WFE_B_STORE_F_MASK_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_MASK (0xFFU) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_SHIFT (0U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_MASK) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_MASK (0xFF00U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_SHIFT (8U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_MASK) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_MASK (0xFF0000U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_SHIFT (16U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_MASK) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_MASK (0xFF000000U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_SHIFT (24U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_MASK) + +/*! @name FETCH_WFE_B_DEBUG - This register holds the debug bits for the prefetch engine for WFE B. */ +#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_MASK (0xFFFFFFU) +#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_SHIFT (0U) +#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_MASK) +#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_MASK (0xF000000U) +#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_SHIFT (24U) +#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_MASK) +#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL_MASK (0x10000000U) +#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL_SHIFT (28U) +#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_BUF_SEL_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_BUF_SEL_MASK) + +/*! @name DITHER_CTRL - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_ENABLE0_MASK) +#define PXP_DITHER_CTRL_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_ENABLE1_MASK) +#define PXP_DITHER_CTRL_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_ENABLE2_MASK) +#define PXP_DITHER_CTRL_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY2_SHIFT)) & PXP_DITHER_CTRL_BUSY2_MASK) +#define PXP_DITHER_CTRL_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY1_SHIFT)) & PXP_DITHER_CTRL_BUSY1_MASK) +#define PXP_DITHER_CTRL_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY0_SHIFT)) & PXP_DITHER_CTRL_BUSY0_MASK) + +/*! @name DITHER_CTRL_SET - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_SET_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_SET_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_SET_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE0_MASK) +#define PXP_DITHER_CTRL_SET_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_SET_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_SET_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE1_MASK) +#define PXP_DITHER_CTRL_SET_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_SET_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_SET_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE2_MASK) +#define PXP_DITHER_CTRL_SET_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_SET_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_SET_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_SET_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_SET_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_SET_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_SET_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_SET_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_SET_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_SET_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY2_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY2_MASK) +#define PXP_DITHER_CTRL_SET_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_SET_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_SET_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY1_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY1_MASK) +#define PXP_DITHER_CTRL_SET_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_SET_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_SET_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY0_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY0_MASK) + +/*! @name DITHER_CTRL_CLR - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_CLR_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_CLR_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_CLR_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE0_MASK) +#define PXP_DITHER_CTRL_CLR_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_CLR_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_CLR_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE1_MASK) +#define PXP_DITHER_CTRL_CLR_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_CLR_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_CLR_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE2_MASK) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_CLR_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_CLR_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_CLR_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_CLR_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_CLR_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_CLR_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_CLR_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY2_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY2_MASK) +#define PXP_DITHER_CTRL_CLR_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_CLR_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_CLR_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY1_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY1_MASK) +#define PXP_DITHER_CTRL_CLR_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_CLR_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_CLR_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY0_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY0_MASK) + +/*! @name DITHER_CTRL_TOG - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_TOG_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_TOG_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_TOG_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE0_MASK) +#define PXP_DITHER_CTRL_TOG_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_TOG_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_TOG_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE1_MASK) +#define PXP_DITHER_CTRL_TOG_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_TOG_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_TOG_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE2_MASK) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_TOG_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_TOG_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_TOG_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_TOG_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_TOG_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_TOG_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_TOG_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY2_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY2_MASK) +#define PXP_DITHER_CTRL_TOG_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_TOG_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_TOG_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY1_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY1_MASK) +#define PXP_DITHER_CTRL_TOG_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_TOG_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_TOG_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY0_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY0_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA15_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_MASK) + +/*! @name WFE_B_CTRL - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_ENABLE_MASK) +#define PXP_WFE_B_CTRL_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_DONE_SHIFT)) & PXP_WFE_B_CTRL_DONE_MASK) + +/*! @name WFE_B_CTRL_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_SET_ENABLE_MASK) +#define PXP_WFE_B_CTRL_SET_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_SET_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_SET_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_SET_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_SET_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_SET_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_SET_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_DONE_SHIFT)) & PXP_WFE_B_CTRL_SET_DONE_MASK) + +/*! @name WFE_B_CTRL_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_CLR_ENABLE_MASK) +#define PXP_WFE_B_CTRL_CLR_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_CLR_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_CLR_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_CLR_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_CLR_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_CLR_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_CLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_DONE_SHIFT)) & PXP_WFE_B_CTRL_CLR_DONE_MASK) + +/*! @name WFE_B_CTRL_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_TOG_ENABLE_MASK) +#define PXP_WFE_B_CTRL_TOG_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_TOG_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_TOG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_TOG_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_TOG_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_TOG_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_TOG_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_DONE_SHIFT)) & PXP_WFE_B_CTRL_TOG_DONE_MASK) + +/*! @name WFE_B_DIMENSIONS - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_DIMENSIONS_WIDTH_MASK (0xFFFU) +#define PXP_WFE_B_DIMENSIONS_WIDTH_SHIFT (0U) +#define PXP_WFE_B_DIMENSIONS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_DIMENSIONS_WIDTH_SHIFT)) & PXP_WFE_B_DIMENSIONS_WIDTH_MASK) +#define PXP_WFE_B_DIMENSIONS_HEIGHT_MASK (0xFFF0000U) +#define PXP_WFE_B_DIMENSIONS_HEIGHT_SHIFT (16U) +#define PXP_WFE_B_DIMENSIONS_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_DIMENSIONS_HEIGHT_SHIFT)) & PXP_WFE_B_DIMENSIONS_HEIGHT_MASK) + +/*! @name WFE_B_OFFSET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_OFFSET_X_OFFSET_MASK (0xFFFU) +#define PXP_WFE_B_OFFSET_X_OFFSET_SHIFT (0U) +#define PXP_WFE_B_OFFSET_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_OFFSET_X_OFFSET_SHIFT)) & PXP_WFE_B_OFFSET_X_OFFSET_MASK) +#define PXP_WFE_B_OFFSET_Y_OFFSET_MASK (0xFFF0000U) +#define PXP_WFE_B_OFFSET_Y_OFFSET_SHIFT (16U) +#define PXP_WFE_B_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_OFFSET_Y_OFFSET_SHIFT)) & PXP_WFE_B_OFFSET_Y_OFFSET_MASK) + +/*! @name WFE_B_SW_DATA_REGS - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_SW_DATA_REGS_VAL0_MASK (0xFFU) +#define PXP_WFE_B_SW_DATA_REGS_VAL0_SHIFT (0U) +#define PXP_WFE_B_SW_DATA_REGS_VAL0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL0_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL0_MASK) +#define PXP_WFE_B_SW_DATA_REGS_VAL1_MASK (0xFF00U) +#define PXP_WFE_B_SW_DATA_REGS_VAL1_SHIFT (8U) +#define PXP_WFE_B_SW_DATA_REGS_VAL1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL1_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL1_MASK) +#define PXP_WFE_B_SW_DATA_REGS_VAL2_MASK (0xFF0000U) +#define PXP_WFE_B_SW_DATA_REGS_VAL2_SHIFT (16U) +#define PXP_WFE_B_SW_DATA_REGS_VAL2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL2_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL2_MASK) +#define PXP_WFE_B_SW_DATA_REGS_VAL3_MASK (0xFF000000U) +#define PXP_WFE_B_SW_DATA_REGS_VAL3_SHIFT (24U) +#define PXP_WFE_B_SW_DATA_REGS_VAL3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL3_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL3_MASK) + +/*! @name WFE_B_SW_FLAG_REGS - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_SW_FLAG_REGS_VAL0_MASK (0x1U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL0_SHIFT (0U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL0_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL0_MASK) +#define PXP_WFE_B_SW_FLAG_REGS_VAL1_MASK (0x2U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL1_SHIFT (1U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL1_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL1_MASK) +#define PXP_WFE_B_SW_FLAG_REGS_VAL2_MASK (0x4U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL2_SHIFT (2U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL2_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL2_MASK) +#define PXP_WFE_B_SW_FLAG_REGS_VAL3_MASK (0x8U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL3_SHIFT (3U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL3_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL3_MASK) + +/*! @name WFE_B_STAGE1_MUX0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX0_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX0_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX0_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX1_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX1_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX1_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX2_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX2_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX2_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX3_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX3_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX3_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX4_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX4_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX4_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX5_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX5_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX5_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX6_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX6_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX6_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX7_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX7_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX7_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX8 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_MUX32_MASK) + +/*! @name WFE_B_STAGE1_MUX8_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_SET_MUX32_MASK) + +/*! @name WFE_B_STAGE1_MUX8_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_MASK) + +/*! @name WFE_B_STAGE1_MUX8_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_MASK) + +/*! @name WFE_B_STAGE2_MUX0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX0_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX0_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX0_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX1_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX1_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX1_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX2_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX2_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX2_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX3_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX3_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX3_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX4_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX4_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX4_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX5_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX5_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX5_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX6_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX6_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX6_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX7_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX7_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX7_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX8 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX8_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX8_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX8_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX9 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX9_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX9_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX9_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX10 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX10_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX10_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX10_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX11 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX11_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX11_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX11_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX12 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_MUX48_MASK) + +/*! @name WFE_B_STAGE2_MUX12_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_SET_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_SET_MUX48_MASK) + +/*! @name WFE_B_STAGE2_MUX12_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_MASK) + +/*! @name WFE_B_STAGE2_MUX12_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_MASK) + +/*! @name WFE_B_STAGE3_MUX0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX0_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX0_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX0_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX1_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX1_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX1_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX2_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX2_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX2_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX3_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX3_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX3_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX4_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX4_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX4_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX5_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX5_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX5_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX6_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX6_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX6_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX7_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX7_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX7_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX8 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX8_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX8_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX8_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX9 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX9_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX9_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX9_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX10 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX43_MASK) + +/*! @name WFE_B_STAGE3_MUX10_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX43_MASK) + +/*! @name WFE_B_STAGE3_MUX10_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_MASK) + +/*! @name WFE_B_STAGE3_MUX10_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_MASK) + +/*! @name WFE_B_STAGE1_5X8_MASKS_0 - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x8 LUT. */ +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_SHIFT)) & PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_MASK) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_MASK (0x1F00U) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_SHIFT)) & PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_MASK) + +/*! @name WFE_B_STG1_5X1_OUT0 - This register defines the output values (new flag) for the 5x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_5X1_MASKS - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT. */ +#define PXP_WFE_B_STG1_5X1_MASKS_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STG1_5X1_MASKS_MASK0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X1_MASKS_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG1_5X1_MASKS_MASK0_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_MASK) + +/*! @name WFE_B_STAGE2_5X6_MASKS_0 - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x6 LUT. */ +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_MASK) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_MASK (0x1F00U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_MASK) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_MASK (0x1F0000U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_MASK) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_MASK (0x1F000000U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_MASK) + +/*! @name WFE_B_STAGE2_5X6_ADDR_0 - Each Address specifies the MUX position in the MUX array. There is one MUXADDR per 5x6 LUT. */ +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_MASK) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_MASK) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_MASK) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_MASK) + +/*! @name WFE_B_STG2_5X1_OUT0 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_OUT1 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_OUT2 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_OUT3 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_MASKS - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT. */ +#define PXP_WFE_B_STG2_5X1_MASKS_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK0_MASK) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK1_MASK (0x1F00U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK1_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK1_MASK) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK2_MASK (0x1F0000U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK2_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK2_MASK) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK3_MASK (0x1F000000U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK3_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK3_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_MASKS - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 8x1 LUT. */ +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0_MASK (0xFFU) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK0_MASK) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1_MASK (0xFF00U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK1_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK1_MASK) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2_MASK (0xFF0000U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK2_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK2_MASK) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3_MASK (0xFF000000U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK3_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK3_MASK) + +/*! @name ALU_B_CTRL - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_ENABLE_MASK) +#define PXP_ALU_B_CTRL_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_START_SHIFT)) & PXP_ALU_B_CTRL_START_MASK) +#define PXP_ALU_B_CTRL_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_BYPASS_MASK) +#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_SHIFT)) & PXP_ALU_B_CTRL_DONE_MASK) + +/*! @name ALU_B_CTRL_SET - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_SET_ENABLE_MASK) +#define PXP_ALU_B_CTRL_SET_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_SET_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_SET_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_START_SHIFT)) & PXP_ALU_B_CTRL_SET_START_MASK) +#define PXP_ALU_B_CTRL_SET_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_SET_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_SET_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_SET_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_SET_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_SET_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_SET_BYPASS_MASK) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_SET_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_SET_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_SET_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_MASK) + +/*! @name ALU_B_CTRL_CLR - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_CLR_ENABLE_MASK) +#define PXP_ALU_B_CTRL_CLR_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_CLR_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_START_SHIFT)) & PXP_ALU_B_CTRL_CLR_START_MASK) +#define PXP_ALU_B_CTRL_CLR_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_CLR_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_CLR_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_CLR_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_CLR_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_CLR_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_CLR_BYPASS_MASK) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_CLR_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_CLR_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_CLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_MASK) + +/*! @name ALU_B_CTRL_TOG - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_TOG_ENABLE_MASK) +#define PXP_ALU_B_CTRL_TOG_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_TOG_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_START_SHIFT)) & PXP_ALU_B_CTRL_TOG_START_MASK) +#define PXP_ALU_B_CTRL_TOG_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_TOG_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_TOG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_TOG_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_TOG_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_TOG_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_TOG_BYPASS_MASK) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_TOG_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_TOG_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_TOG_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_MASK) + +/*! @name ALU_B_BUF_SIZE - This register defines the size of the buffer to be processed by the alu engine. */ +#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH_MASK (0xFFFU) +#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH_SHIFT (0U) +#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_BUF_SIZE_BUF_WIDTH_SHIFT)) & PXP_ALU_B_BUF_SIZE_BUF_WIDTH_MASK) +#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_MASK (0xFFF0000U) +#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_SHIFT (16U) +#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_SHIFT)) & PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_MASK) + +/*! @name ALU_B_INST_ENTRY - This register defines the Entry Address for the Instruction Memory of the ALU. */ +#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_MASK (0xFFFFU) +#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_SHIFT (0U) +#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_SHIFT)) & PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_MASK) + +/*! @name ALU_B_PARAM - This register defines the parameter used by SW running on ALU. */ +#define PXP_ALU_B_PARAM_PARAM0_MASK (0xFFU) +#define PXP_ALU_B_PARAM_PARAM0_SHIFT (0U) +#define PXP_ALU_B_PARAM_PARAM0(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_PARAM_PARAM0_SHIFT)) & PXP_ALU_B_PARAM_PARAM0_MASK) +#define PXP_ALU_B_PARAM_PARAM1_MASK (0xFF00U) +#define PXP_ALU_B_PARAM_PARAM1_SHIFT (8U) +#define PXP_ALU_B_PARAM_PARAM1(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_PARAM_PARAM1_SHIFT)) & PXP_ALU_B_PARAM_PARAM1_MASK) + +/*! @name ALU_B_CONFIG - This register defines the hw configuration options for the alu core. */ +#define PXP_ALU_B_CONFIG_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_ALU_B_CONFIG_BUF_ADDR_SHIFT (0U) +#define PXP_ALU_B_CONFIG_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CONFIG_BUF_ADDR_SHIFT)) & PXP_ALU_B_CONFIG_BUF_ADDR_MASK) + +/*! @name ALU_B_LUT_CONFIG - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_MODE_MASK) + +/*! @name ALU_B_LUT_CONFIG_SET - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_SET_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_SET_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_SET_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_SET_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_SET_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_SET_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_SET_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_SET_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_SET_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_SET_MODE_MASK) + +/*! @name ALU_B_LUT_CONFIG_CLR - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_CLR_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_CLR_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_CLR_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_CLR_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_CLR_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_CLR_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_CLR_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_CLR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_CLR_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_CLR_MODE_MASK) + +/*! @name ALU_B_LUT_CONFIG_TOG - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_TOG_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_TOG_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_TOG_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_TOG_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_TOG_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_TOG_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_TOG_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_TOG_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_TOG_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_TOG_MODE_MASK) + +/*! @name ALU_B_LUT_DATA0 - This register defines the lower 32-bit data for the LUT */ +#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L_MASK (0xFFFFFFFFU) +#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L_SHIFT (0U) +#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_DATA0_LUT_DATA_L_SHIFT)) & PXP_ALU_B_LUT_DATA0_LUT_DATA_L_MASK) + +/*! @name ALU_B_LUT_DATA1 - This register defines the higher 32-bit data for the LUT */ +#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H_MASK (0xFFFFFFFFU) +#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H_SHIFT (0U) +#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_DATA1_LUT_DATA_H_SHIFT)) & PXP_ALU_B_LUT_DATA1_LUT_DATA_H_MASK) + +/*! @name ALU_B_DBG - This register is used for debugging alu block */ +#define PXP_ALU_B_DBG_DEBUG_VALUE_MASK (0xFFFFFFU) +#define PXP_ALU_B_DBG_DEBUG_VALUE_SHIFT (0U) +#define PXP_ALU_B_DBG_DEBUG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_DBG_DEBUG_VALUE_SHIFT)) & PXP_ALU_B_DBG_DEBUG_VALUE_MASK) +#define PXP_ALU_B_DBG_DEBUG_SEL_MASK (0xFF000000U) +#define PXP_ALU_B_DBG_DEBUG_SEL_SHIFT (24U) +#define PXP_ALU_B_DBG_DEBUG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_DBG_DEBUG_SEL_SHIFT)) & PXP_ALU_B_DBG_DEBUG_SEL_MASK) + +/*! @name HIST_A_CTRL - Histogram Control Register. */ +#define PXP_HIST_A_CTRL_ENABLE_MASK (0x1U) +#define PXP_HIST_A_CTRL_ENABLE_SHIFT (0U) +#define PXP_HIST_A_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_ENABLE_SHIFT)) & PXP_HIST_A_CTRL_ENABLE_MASK) +#define PXP_HIST_A_CTRL_CLEAR_MASK (0x10U) +#define PXP_HIST_A_CTRL_CLEAR_SHIFT (4U) +#define PXP_HIST_A_CTRL_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_CLEAR_SHIFT)) & PXP_HIST_A_CTRL_CLEAR_MASK) +#define PXP_HIST_A_CTRL_STATUS_MASK (0x1F00U) +#define PXP_HIST_A_CTRL_STATUS_SHIFT (8U) +#define PXP_HIST_A_CTRL_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_STATUS_SHIFT)) & PXP_HIST_A_CTRL_STATUS_MASK) +#define PXP_HIST_A_CTRL_PIXEL_OFFSET_MASK (0x7F0000U) +#define PXP_HIST_A_CTRL_PIXEL_OFFSET_SHIFT (16U) +#define PXP_HIST_A_CTRL_PIXEL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_PIXEL_OFFSET_SHIFT)) & PXP_HIST_A_CTRL_PIXEL_OFFSET_MASK) +#define PXP_HIST_A_CTRL_PIXEL_WIDTH_MASK (0x7000000U) +#define PXP_HIST_A_CTRL_PIXEL_WIDTH_SHIFT (24U) +#define PXP_HIST_A_CTRL_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_PIXEL_WIDTH_SHIFT)) & PXP_HIST_A_CTRL_PIXEL_WIDTH_MASK) + +/*! @name HIST_A_MASK - Histogram Pixel Mask Register. */ +#define PXP_HIST_A_MASK_MASK_EN_MASK (0x1U) +#define PXP_HIST_A_MASK_MASK_EN_SHIFT (0U) +#define PXP_HIST_A_MASK_MASK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_EN_SHIFT)) & PXP_HIST_A_MASK_MASK_EN_MASK) +#define PXP_HIST_A_MASK_MASK_MODE_MASK (0x30U) +#define PXP_HIST_A_MASK_MASK_MODE_SHIFT (4U) +#define PXP_HIST_A_MASK_MASK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_MODE_SHIFT)) & PXP_HIST_A_MASK_MASK_MODE_MASK) +#define PXP_HIST_A_MASK_MASK_OFFSET_MASK (0x1FC0U) +#define PXP_HIST_A_MASK_MASK_OFFSET_SHIFT (6U) +#define PXP_HIST_A_MASK_MASK_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_OFFSET_SHIFT)) & PXP_HIST_A_MASK_MASK_OFFSET_MASK) +#define PXP_HIST_A_MASK_MASK_WIDTH_MASK (0xE000U) +#define PXP_HIST_A_MASK_MASK_WIDTH_SHIFT (13U) +#define PXP_HIST_A_MASK_MASK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_WIDTH_SHIFT)) & PXP_HIST_A_MASK_MASK_WIDTH_MASK) +#define PXP_HIST_A_MASK_MASK_VALUE0_MASK (0xFF0000U) +#define PXP_HIST_A_MASK_MASK_VALUE0_SHIFT (16U) +#define PXP_HIST_A_MASK_MASK_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_VALUE0_SHIFT)) & PXP_HIST_A_MASK_MASK_VALUE0_MASK) +#define PXP_HIST_A_MASK_MASK_VALUE1_MASK (0xFF000000U) +#define PXP_HIST_A_MASK_MASK_VALUE1_SHIFT (24U) +#define PXP_HIST_A_MASK_MASK_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_VALUE1_SHIFT)) & PXP_HIST_A_MASK_MASK_VALUE1_MASK) + +/*! @name HIST_A_BUF_SIZE - Histogram Pixel Buffer Size Register. */ +#define PXP_HIST_A_BUF_SIZE_WIDTH_MASK (0xFFFU) +#define PXP_HIST_A_BUF_SIZE_WIDTH_SHIFT (0U) +#define PXP_HIST_A_BUF_SIZE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_BUF_SIZE_WIDTH_SHIFT)) & PXP_HIST_A_BUF_SIZE_WIDTH_MASK) +#define PXP_HIST_A_BUF_SIZE_HEIGHT_MASK (0xFFF0000U) +#define PXP_HIST_A_BUF_SIZE_HEIGHT_SHIFT (16U) +#define PXP_HIST_A_BUF_SIZE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_BUF_SIZE_HEIGHT_SHIFT)) & PXP_HIST_A_BUF_SIZE_HEIGHT_MASK) + +/*! @name HIST_A_TOTAL_PIXEL - Total Number of Pixels Used by Histogram Engine. */ +#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_MASK (0xFFFFFFU) +#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT (0U) +#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT)) & PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_MASK) + +/*! @name HIST_A_ACTIVE_AREA_X - The X Coordinate Offset for Active Area. */ +#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_MASK (0xFFFU) +#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT (0U) +#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_MASK) +#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT (16U) +#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_MASK) + +/*! @name HIST_A_ACTIVE_AREA_Y - The Y Coordinate Offset for Active Area. */ +#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK (0xFFFU) +#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT (0U) +#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK) +#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT (16U) +#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK) + +/*! @name HIST_A_RAW_STAT0 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_A_RAW_STAT0_STAT0_MASK (0xFFFFFFFFU) +#define PXP_HIST_A_RAW_STAT0_STAT0_SHIFT (0U) +#define PXP_HIST_A_RAW_STAT0_STAT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_RAW_STAT0_STAT0_SHIFT)) & PXP_HIST_A_RAW_STAT0_STAT0_MASK) + +/*! @name HIST_A_RAW_STAT1 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_A_RAW_STAT1_STAT1_MASK (0xFFFFFFFFU) +#define PXP_HIST_A_RAW_STAT1_STAT1_SHIFT (0U) +#define PXP_HIST_A_RAW_STAT1_STAT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_RAW_STAT1_STAT1_SHIFT)) & PXP_HIST_A_RAW_STAT1_STAT1_MASK) + +/*! @name HIST_B_CTRL - Histogram Control Register. */ +#define PXP_HIST_B_CTRL_ENABLE_MASK (0x1U) +#define PXP_HIST_B_CTRL_ENABLE_SHIFT (0U) +#define PXP_HIST_B_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_ENABLE_SHIFT)) & PXP_HIST_B_CTRL_ENABLE_MASK) +#define PXP_HIST_B_CTRL_CLEAR_MASK (0x10U) +#define PXP_HIST_B_CTRL_CLEAR_SHIFT (4U) +#define PXP_HIST_B_CTRL_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_CLEAR_SHIFT)) & PXP_HIST_B_CTRL_CLEAR_MASK) +#define PXP_HIST_B_CTRL_STATUS_MASK (0x1F00U) +#define PXP_HIST_B_CTRL_STATUS_SHIFT (8U) +#define PXP_HIST_B_CTRL_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_STATUS_SHIFT)) & PXP_HIST_B_CTRL_STATUS_MASK) +#define PXP_HIST_B_CTRL_PIXEL_OFFSET_MASK (0x7F0000U) +#define PXP_HIST_B_CTRL_PIXEL_OFFSET_SHIFT (16U) +#define PXP_HIST_B_CTRL_PIXEL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_PIXEL_OFFSET_SHIFT)) & PXP_HIST_B_CTRL_PIXEL_OFFSET_MASK) +#define PXP_HIST_B_CTRL_PIXEL_WIDTH_MASK (0x7000000U) +#define PXP_HIST_B_CTRL_PIXEL_WIDTH_SHIFT (24U) +#define PXP_HIST_B_CTRL_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_PIXEL_WIDTH_SHIFT)) & PXP_HIST_B_CTRL_PIXEL_WIDTH_MASK) + +/*! @name HIST_B_MASK - Histogram Pixel Mask Register. */ +#define PXP_HIST_B_MASK_MASK_EN_MASK (0x1U) +#define PXP_HIST_B_MASK_MASK_EN_SHIFT (0U) +#define PXP_HIST_B_MASK_MASK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_EN_SHIFT)) & PXP_HIST_B_MASK_MASK_EN_MASK) +#define PXP_HIST_B_MASK_MASK_MODE_MASK (0x30U) +#define PXP_HIST_B_MASK_MASK_MODE_SHIFT (4U) +#define PXP_HIST_B_MASK_MASK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_MODE_SHIFT)) & PXP_HIST_B_MASK_MASK_MODE_MASK) +#define PXP_HIST_B_MASK_MASK_OFFSET_MASK (0x1FC0U) +#define PXP_HIST_B_MASK_MASK_OFFSET_SHIFT (6U) +#define PXP_HIST_B_MASK_MASK_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_OFFSET_SHIFT)) & PXP_HIST_B_MASK_MASK_OFFSET_MASK) +#define PXP_HIST_B_MASK_MASK_WIDTH_MASK (0xE000U) +#define PXP_HIST_B_MASK_MASK_WIDTH_SHIFT (13U) +#define PXP_HIST_B_MASK_MASK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_WIDTH_SHIFT)) & PXP_HIST_B_MASK_MASK_WIDTH_MASK) +#define PXP_HIST_B_MASK_MASK_VALUE0_MASK (0xFF0000U) +#define PXP_HIST_B_MASK_MASK_VALUE0_SHIFT (16U) +#define PXP_HIST_B_MASK_MASK_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_VALUE0_SHIFT)) & PXP_HIST_B_MASK_MASK_VALUE0_MASK) +#define PXP_HIST_B_MASK_MASK_VALUE1_MASK (0xFF000000U) +#define PXP_HIST_B_MASK_MASK_VALUE1_SHIFT (24U) +#define PXP_HIST_B_MASK_MASK_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_VALUE1_SHIFT)) & PXP_HIST_B_MASK_MASK_VALUE1_MASK) + +/*! @name HIST_B_BUF_SIZE - Histogram Pixel Buffer Size Register. */ +#define PXP_HIST_B_BUF_SIZE_WIDTH_MASK (0xFFFU) +#define PXP_HIST_B_BUF_SIZE_WIDTH_SHIFT (0U) +#define PXP_HIST_B_BUF_SIZE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_BUF_SIZE_WIDTH_SHIFT)) & PXP_HIST_B_BUF_SIZE_WIDTH_MASK) +#define PXP_HIST_B_BUF_SIZE_HEIGHT_MASK (0xFFF0000U) +#define PXP_HIST_B_BUF_SIZE_HEIGHT_SHIFT (16U) +#define PXP_HIST_B_BUF_SIZE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_BUF_SIZE_HEIGHT_SHIFT)) & PXP_HIST_B_BUF_SIZE_HEIGHT_MASK) + +/*! @name HIST_B_TOTAL_PIXEL - Total Number of Pixels Used by Histogram Engine. */ +#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_MASK (0xFFFFFFU) +#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT (0U) +#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT)) & PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_MASK) + +/*! @name HIST_B_ACTIVE_AREA_X - The X Coordinate Offset for Active Area. */ +#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_MASK (0xFFFU) +#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT (0U) +#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_MASK) +#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT (16U) +#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_MASK) + +/*! @name HIST_B_ACTIVE_AREA_Y - The Y Coordinate Offset for Active Area. */ +#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK (0xFFFU) +#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT (0U) +#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK) +#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT (16U) +#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK) + +/*! @name HIST_B_RAW_STAT0 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_B_RAW_STAT0_STAT0_MASK (0xFFFFFFFFU) +#define PXP_HIST_B_RAW_STAT0_STAT0_SHIFT (0U) +#define PXP_HIST_B_RAW_STAT0_STAT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_RAW_STAT0_STAT0_SHIFT)) & PXP_HIST_B_RAW_STAT0_STAT0_MASK) + +/*! @name HIST_B_RAW_STAT1 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_B_RAW_STAT1_STAT1_MASK (0xFFFFFFFFU) +#define PXP_HIST_B_RAW_STAT1_STAT1_SHIFT (0U) +#define PXP_HIST_B_RAW_STAT1_STAT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_RAW_STAT1_STAT1_SHIFT)) & PXP_HIST_B_RAW_STAT1_STAT1_MASK) + +/*! @name HIST2_PARAM - 2-level Histogram Parameter Register. */ +#define PXP_HIST2_PARAM_VALUE0_MASK (0x3FU) +#define PXP_HIST2_PARAM_VALUE0_SHIFT (0U) +#define PXP_HIST2_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST2_PARAM_VALUE0_SHIFT)) & PXP_HIST2_PARAM_VALUE0_MASK) +#define PXP_HIST2_PARAM_VALUE1_MASK (0x3F00U) +#define PXP_HIST2_PARAM_VALUE1_SHIFT (8U) +#define PXP_HIST2_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST2_PARAM_VALUE1_SHIFT)) & PXP_HIST2_PARAM_VALUE1_MASK) + +/*! @name HIST4_PARAM - 4-level Histogram Parameter Register. */ +#define PXP_HIST4_PARAM_VALUE0_MASK (0x3FU) +#define PXP_HIST4_PARAM_VALUE0_SHIFT (0U) +#define PXP_HIST4_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE0_SHIFT)) & PXP_HIST4_PARAM_VALUE0_MASK) +#define PXP_HIST4_PARAM_VALUE1_MASK (0x3F00U) +#define PXP_HIST4_PARAM_VALUE1_SHIFT (8U) +#define PXP_HIST4_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE1_SHIFT)) & PXP_HIST4_PARAM_VALUE1_MASK) +#define PXP_HIST4_PARAM_VALUE2_MASK (0x3F0000U) +#define PXP_HIST4_PARAM_VALUE2_SHIFT (16U) +#define PXP_HIST4_PARAM_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE2_SHIFT)) & PXP_HIST4_PARAM_VALUE2_MASK) +#define PXP_HIST4_PARAM_VALUE3_MASK (0x3F000000U) +#define PXP_HIST4_PARAM_VALUE3_SHIFT (24U) +#define PXP_HIST4_PARAM_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE3_SHIFT)) & PXP_HIST4_PARAM_VALUE3_MASK) + +/*! @name HIST8_PARAM0 - 8-level Histogram Parameter 0 Register. */ +#define PXP_HIST8_PARAM0_VALUE0_MASK (0x3FU) +#define PXP_HIST8_PARAM0_VALUE0_SHIFT (0U) +#define PXP_HIST8_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE0_SHIFT)) & PXP_HIST8_PARAM0_VALUE0_MASK) +#define PXP_HIST8_PARAM0_VALUE1_MASK (0x3F00U) +#define PXP_HIST8_PARAM0_VALUE1_SHIFT (8U) +#define PXP_HIST8_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE1_SHIFT)) & PXP_HIST8_PARAM0_VALUE1_MASK) +#define PXP_HIST8_PARAM0_VALUE2_MASK (0x3F0000U) +#define PXP_HIST8_PARAM0_VALUE2_SHIFT (16U) +#define PXP_HIST8_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE2_SHIFT)) & PXP_HIST8_PARAM0_VALUE2_MASK) +#define PXP_HIST8_PARAM0_VALUE3_MASK (0x3F000000U) +#define PXP_HIST8_PARAM0_VALUE3_SHIFT (24U) +#define PXP_HIST8_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE3_SHIFT)) & PXP_HIST8_PARAM0_VALUE3_MASK) + +/*! @name HIST8_PARAM1 - 8-level Histogram Parameter 1 Register. */ +#define PXP_HIST8_PARAM1_VALUE4_MASK (0x3FU) +#define PXP_HIST8_PARAM1_VALUE4_SHIFT (0U) +#define PXP_HIST8_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE4_SHIFT)) & PXP_HIST8_PARAM1_VALUE4_MASK) +#define PXP_HIST8_PARAM1_VALUE5_MASK (0x3F00U) +#define PXP_HIST8_PARAM1_VALUE5_SHIFT (8U) +#define PXP_HIST8_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE5_SHIFT)) & PXP_HIST8_PARAM1_VALUE5_MASK) +#define PXP_HIST8_PARAM1_VALUE6_MASK (0x3F0000U) +#define PXP_HIST8_PARAM1_VALUE6_SHIFT (16U) +#define PXP_HIST8_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE6_SHIFT)) & PXP_HIST8_PARAM1_VALUE6_MASK) +#define PXP_HIST8_PARAM1_VALUE7_MASK (0x3F000000U) +#define PXP_HIST8_PARAM1_VALUE7_SHIFT (24U) +#define PXP_HIST8_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE7_SHIFT)) & PXP_HIST8_PARAM1_VALUE7_MASK) + +/*! @name HIST16_PARAM0 - 16-level Histogram Parameter 0 Register. */ +#define PXP_HIST16_PARAM0_VALUE0_MASK (0x3FU) +#define PXP_HIST16_PARAM0_VALUE0_SHIFT (0U) +#define PXP_HIST16_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE0_SHIFT)) & PXP_HIST16_PARAM0_VALUE0_MASK) +#define PXP_HIST16_PARAM0_VALUE1_MASK (0x3F00U) +#define PXP_HIST16_PARAM0_VALUE1_SHIFT (8U) +#define PXP_HIST16_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE1_SHIFT)) & PXP_HIST16_PARAM0_VALUE1_MASK) +#define PXP_HIST16_PARAM0_VALUE2_MASK (0x3F0000U) +#define PXP_HIST16_PARAM0_VALUE2_SHIFT (16U) +#define PXP_HIST16_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE2_SHIFT)) & PXP_HIST16_PARAM0_VALUE2_MASK) +#define PXP_HIST16_PARAM0_VALUE3_MASK (0x3F000000U) +#define PXP_HIST16_PARAM0_VALUE3_SHIFT (24U) +#define PXP_HIST16_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE3_SHIFT)) & PXP_HIST16_PARAM0_VALUE3_MASK) + +/*! @name HIST16_PARAM1 - 16-level Histogram Parameter 1 Register. */ +#define PXP_HIST16_PARAM1_VALUE4_MASK (0x3FU) +#define PXP_HIST16_PARAM1_VALUE4_SHIFT (0U) +#define PXP_HIST16_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE4_SHIFT)) & PXP_HIST16_PARAM1_VALUE4_MASK) +#define PXP_HIST16_PARAM1_VALUE5_MASK (0x3F00U) +#define PXP_HIST16_PARAM1_VALUE5_SHIFT (8U) +#define PXP_HIST16_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE5_SHIFT)) & PXP_HIST16_PARAM1_VALUE5_MASK) +#define PXP_HIST16_PARAM1_VALUE6_MASK (0x3F0000U) +#define PXP_HIST16_PARAM1_VALUE6_SHIFT (16U) +#define PXP_HIST16_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE6_SHIFT)) & PXP_HIST16_PARAM1_VALUE6_MASK) +#define PXP_HIST16_PARAM1_VALUE7_MASK (0x3F000000U) +#define PXP_HIST16_PARAM1_VALUE7_SHIFT (24U) +#define PXP_HIST16_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE7_SHIFT)) & PXP_HIST16_PARAM1_VALUE7_MASK) + +/*! @name HIST16_PARAM2 - 16-level Histogram Parameter 2 Register. */ +#define PXP_HIST16_PARAM2_VALUE8_MASK (0x3FU) +#define PXP_HIST16_PARAM2_VALUE8_SHIFT (0U) +#define PXP_HIST16_PARAM2_VALUE8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE8_SHIFT)) & PXP_HIST16_PARAM2_VALUE8_MASK) +#define PXP_HIST16_PARAM2_VALUE9_MASK (0x3F00U) +#define PXP_HIST16_PARAM2_VALUE9_SHIFT (8U) +#define PXP_HIST16_PARAM2_VALUE9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE9_SHIFT)) & PXP_HIST16_PARAM2_VALUE9_MASK) +#define PXP_HIST16_PARAM2_VALUE10_MASK (0x3F0000U) +#define PXP_HIST16_PARAM2_VALUE10_SHIFT (16U) +#define PXP_HIST16_PARAM2_VALUE10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE10_SHIFT)) & PXP_HIST16_PARAM2_VALUE10_MASK) +#define PXP_HIST16_PARAM2_VALUE11_MASK (0x3F000000U) +#define PXP_HIST16_PARAM2_VALUE11_SHIFT (24U) +#define PXP_HIST16_PARAM2_VALUE11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE11_SHIFT)) & PXP_HIST16_PARAM2_VALUE11_MASK) + +/*! @name HIST16_PARAM3 - 16-level Histogram Parameter 3 Register. */ +#define PXP_HIST16_PARAM3_VALUE12_MASK (0x3FU) +#define PXP_HIST16_PARAM3_VALUE12_SHIFT (0U) +#define PXP_HIST16_PARAM3_VALUE12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE12_SHIFT)) & PXP_HIST16_PARAM3_VALUE12_MASK) +#define PXP_HIST16_PARAM3_VALUE13_MASK (0x3F00U) +#define PXP_HIST16_PARAM3_VALUE13_SHIFT (8U) +#define PXP_HIST16_PARAM3_VALUE13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE13_SHIFT)) & PXP_HIST16_PARAM3_VALUE13_MASK) +#define PXP_HIST16_PARAM3_VALUE14_MASK (0x3F0000U) +#define PXP_HIST16_PARAM3_VALUE14_SHIFT (16U) +#define PXP_HIST16_PARAM3_VALUE14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE14_SHIFT)) & PXP_HIST16_PARAM3_VALUE14_MASK) +#define PXP_HIST16_PARAM3_VALUE15_MASK (0x3F000000U) +#define PXP_HIST16_PARAM3_VALUE15_SHIFT (24U) +#define PXP_HIST16_PARAM3_VALUE15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE15_SHIFT)) & PXP_HIST16_PARAM3_VALUE15_MASK) + +/*! @name HIST32_PARAM0 - 32-level Histogram Parameter 0 Register. */ +#define PXP_HIST32_PARAM0_VALUE0_MASK (0x3FU) +#define PXP_HIST32_PARAM0_VALUE0_SHIFT (0U) +#define PXP_HIST32_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE0_SHIFT)) & PXP_HIST32_PARAM0_VALUE0_MASK) +#define PXP_HIST32_PARAM0_VALUE1_MASK (0x3F00U) +#define PXP_HIST32_PARAM0_VALUE1_SHIFT (8U) +#define PXP_HIST32_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE1_SHIFT)) & PXP_HIST32_PARAM0_VALUE1_MASK) +#define PXP_HIST32_PARAM0_VALUE2_MASK (0x3F0000U) +#define PXP_HIST32_PARAM0_VALUE2_SHIFT (16U) +#define PXP_HIST32_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE2_SHIFT)) & PXP_HIST32_PARAM0_VALUE2_MASK) +#define PXP_HIST32_PARAM0_VALUE3_MASK (0x3F000000U) +#define PXP_HIST32_PARAM0_VALUE3_SHIFT (24U) +#define PXP_HIST32_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE3_SHIFT)) & PXP_HIST32_PARAM0_VALUE3_MASK) + +/*! @name HIST32_PARAM1 - 32-level Histogram Parameter 1 Register. */ +#define PXP_HIST32_PARAM1_VALUE4_MASK (0x3FU) +#define PXP_HIST32_PARAM1_VALUE4_SHIFT (0U) +#define PXP_HIST32_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE4_SHIFT)) & PXP_HIST32_PARAM1_VALUE4_MASK) +#define PXP_HIST32_PARAM1_VALUE5_MASK (0x3F00U) +#define PXP_HIST32_PARAM1_VALUE5_SHIFT (8U) +#define PXP_HIST32_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE5_SHIFT)) & PXP_HIST32_PARAM1_VALUE5_MASK) +#define PXP_HIST32_PARAM1_VALUE6_MASK (0x3F0000U) +#define PXP_HIST32_PARAM1_VALUE6_SHIFT (16U) +#define PXP_HIST32_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE6_SHIFT)) & PXP_HIST32_PARAM1_VALUE6_MASK) +#define PXP_HIST32_PARAM1_VALUE7_MASK (0x3F000000U) +#define PXP_HIST32_PARAM1_VALUE7_SHIFT (24U) +#define PXP_HIST32_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE7_SHIFT)) & PXP_HIST32_PARAM1_VALUE7_MASK) + +/*! @name HIST32_PARAM2 - 32-level Histogram Parameter 2 Register. */ +#define PXP_HIST32_PARAM2_VALUE8_MASK (0x3FU) +#define PXP_HIST32_PARAM2_VALUE8_SHIFT (0U) +#define PXP_HIST32_PARAM2_VALUE8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE8_SHIFT)) & PXP_HIST32_PARAM2_VALUE8_MASK) +#define PXP_HIST32_PARAM2_VALUE9_MASK (0x3F00U) +#define PXP_HIST32_PARAM2_VALUE9_SHIFT (8U) +#define PXP_HIST32_PARAM2_VALUE9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE9_SHIFT)) & PXP_HIST32_PARAM2_VALUE9_MASK) +#define PXP_HIST32_PARAM2_VALUE10_MASK (0x3F0000U) +#define PXP_HIST32_PARAM2_VALUE10_SHIFT (16U) +#define PXP_HIST32_PARAM2_VALUE10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE10_SHIFT)) & PXP_HIST32_PARAM2_VALUE10_MASK) +#define PXP_HIST32_PARAM2_VALUE11_MASK (0x3F000000U) +#define PXP_HIST32_PARAM2_VALUE11_SHIFT (24U) +#define PXP_HIST32_PARAM2_VALUE11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE11_SHIFT)) & PXP_HIST32_PARAM2_VALUE11_MASK) + +/*! @name HIST32_PARAM3 - 32-level Histogram Parameter 3 Register. */ +#define PXP_HIST32_PARAM3_VALUE12_MASK (0x3FU) +#define PXP_HIST32_PARAM3_VALUE12_SHIFT (0U) +#define PXP_HIST32_PARAM3_VALUE12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE12_SHIFT)) & PXP_HIST32_PARAM3_VALUE12_MASK) +#define PXP_HIST32_PARAM3_VALUE13_MASK (0x3F00U) +#define PXP_HIST32_PARAM3_VALUE13_SHIFT (8U) +#define PXP_HIST32_PARAM3_VALUE13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE13_SHIFT)) & PXP_HIST32_PARAM3_VALUE13_MASK) +#define PXP_HIST32_PARAM3_VALUE14_MASK (0x3F0000U) +#define PXP_HIST32_PARAM3_VALUE14_SHIFT (16U) +#define PXP_HIST32_PARAM3_VALUE14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE14_SHIFT)) & PXP_HIST32_PARAM3_VALUE14_MASK) +#define PXP_HIST32_PARAM3_VALUE15_MASK (0x3F000000U) +#define PXP_HIST32_PARAM3_VALUE15_SHIFT (24U) +#define PXP_HIST32_PARAM3_VALUE15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE15_SHIFT)) & PXP_HIST32_PARAM3_VALUE15_MASK) + +/*! @name HIST32_PARAM4 - 32-level Histogram Parameter 0 Register. */ +#define PXP_HIST32_PARAM4_VALUE16_MASK (0x3FU) +#define PXP_HIST32_PARAM4_VALUE16_SHIFT (0U) +#define PXP_HIST32_PARAM4_VALUE16(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE16_SHIFT)) & PXP_HIST32_PARAM4_VALUE16_MASK) +#define PXP_HIST32_PARAM4_VALUE17_MASK (0x3F00U) +#define PXP_HIST32_PARAM4_VALUE17_SHIFT (8U) +#define PXP_HIST32_PARAM4_VALUE17(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE17_SHIFT)) & PXP_HIST32_PARAM4_VALUE17_MASK) +#define PXP_HIST32_PARAM4_VALUE18_MASK (0x3F0000U) +#define PXP_HIST32_PARAM4_VALUE18_SHIFT (16U) +#define PXP_HIST32_PARAM4_VALUE18(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE18_SHIFT)) & PXP_HIST32_PARAM4_VALUE18_MASK) +#define PXP_HIST32_PARAM4_VALUE19_MASK (0x3F000000U) +#define PXP_HIST32_PARAM4_VALUE19_SHIFT (24U) +#define PXP_HIST32_PARAM4_VALUE19(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE19_SHIFT)) & PXP_HIST32_PARAM4_VALUE19_MASK) + +/*! @name HIST32_PARAM5 - 32-level Histogram Parameter 1 Register. */ +#define PXP_HIST32_PARAM5_VALUE20_MASK (0x3FU) +#define PXP_HIST32_PARAM5_VALUE20_SHIFT (0U) +#define PXP_HIST32_PARAM5_VALUE20(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE20_SHIFT)) & PXP_HIST32_PARAM5_VALUE20_MASK) +#define PXP_HIST32_PARAM5_VALUE21_MASK (0x3F00U) +#define PXP_HIST32_PARAM5_VALUE21_SHIFT (8U) +#define PXP_HIST32_PARAM5_VALUE21(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE21_SHIFT)) & PXP_HIST32_PARAM5_VALUE21_MASK) +#define PXP_HIST32_PARAM5_VALUE22_MASK (0x3F0000U) +#define PXP_HIST32_PARAM5_VALUE22_SHIFT (16U) +#define PXP_HIST32_PARAM5_VALUE22(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE22_SHIFT)) & PXP_HIST32_PARAM5_VALUE22_MASK) +#define PXP_HIST32_PARAM5_VALUE23_MASK (0x3F000000U) +#define PXP_HIST32_PARAM5_VALUE23_SHIFT (24U) +#define PXP_HIST32_PARAM5_VALUE23(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE23_SHIFT)) & PXP_HIST32_PARAM5_VALUE23_MASK) + +/*! @name HIST32_PARAM6 - 32-level Histogram Parameter 2 Register. */ +#define PXP_HIST32_PARAM6_VALUE24_MASK (0x3FU) +#define PXP_HIST32_PARAM6_VALUE24_SHIFT (0U) +#define PXP_HIST32_PARAM6_VALUE24(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE24_SHIFT)) & PXP_HIST32_PARAM6_VALUE24_MASK) +#define PXP_HIST32_PARAM6_VALUE25_MASK (0x3F00U) +#define PXP_HIST32_PARAM6_VALUE25_SHIFT (8U) +#define PXP_HIST32_PARAM6_VALUE25(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE25_SHIFT)) & PXP_HIST32_PARAM6_VALUE25_MASK) +#define PXP_HIST32_PARAM6_VALUE26_MASK (0x3F0000U) +#define PXP_HIST32_PARAM6_VALUE26_SHIFT (16U) +#define PXP_HIST32_PARAM6_VALUE26(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE26_SHIFT)) & PXP_HIST32_PARAM6_VALUE26_MASK) +#define PXP_HIST32_PARAM6_VALUE27_MASK (0x3F000000U) +#define PXP_HIST32_PARAM6_VALUE27_SHIFT (24U) +#define PXP_HIST32_PARAM6_VALUE27(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE27_SHIFT)) & PXP_HIST32_PARAM6_VALUE27_MASK) + +/*! @name HIST32_PARAM7 - 32-level Histogram Parameter 3 Register. */ +#define PXP_HIST32_PARAM7_VALUE28_MASK (0x3FU) +#define PXP_HIST32_PARAM7_VALUE28_SHIFT (0U) +#define PXP_HIST32_PARAM7_VALUE28(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE28_SHIFT)) & PXP_HIST32_PARAM7_VALUE28_MASK) +#define PXP_HIST32_PARAM7_VALUE29_MASK (0x3F00U) +#define PXP_HIST32_PARAM7_VALUE29_SHIFT (8U) +#define PXP_HIST32_PARAM7_VALUE29(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE29_SHIFT)) & PXP_HIST32_PARAM7_VALUE29_MASK) +#define PXP_HIST32_PARAM7_VALUE30_MASK (0x3F0000U) +#define PXP_HIST32_PARAM7_VALUE30_SHIFT (16U) +#define PXP_HIST32_PARAM7_VALUE30(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE30_SHIFT)) & PXP_HIST32_PARAM7_VALUE30_MASK) +#define PXP_HIST32_PARAM7_VALUE31_MASK (0x3F000000U) +#define PXP_HIST32_PARAM7_VALUE31_SHIFT (24U) +#define PXP_HIST32_PARAM7_VALUE31(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE31_SHIFT)) & PXP_HIST32_PARAM7_VALUE31_MASK) + +/*! @name HANDSHAKE_READY_MUX0 - This register defines the pxp subblock handshake signals ready mux on top level. */ +#define PXP_HANDSHAKE_READY_MUX0_HSK0_MASK (0xFU) +#define PXP_HANDSHAKE_READY_MUX0_HSK0_SHIFT (0U) +#define PXP_HANDSHAKE_READY_MUX0_HSK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK0_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK0_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK1_MASK (0xF0U) +#define PXP_HANDSHAKE_READY_MUX0_HSK1_SHIFT (4U) +#define PXP_HANDSHAKE_READY_MUX0_HSK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK1_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK1_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK2_MASK (0xF00U) +#define PXP_HANDSHAKE_READY_MUX0_HSK2_SHIFT (8U) +#define PXP_HANDSHAKE_READY_MUX0_HSK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK2_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK2_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK3_MASK (0xF000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK3_SHIFT (12U) +#define PXP_HANDSHAKE_READY_MUX0_HSK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK3_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK3_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK4_MASK (0xF0000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK4_SHIFT (16U) +#define PXP_HANDSHAKE_READY_MUX0_HSK4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK4_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK4_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK5_MASK (0xF00000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK5_SHIFT (20U) +#define PXP_HANDSHAKE_READY_MUX0_HSK5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK5_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK5_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK6_MASK (0xF000000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK6_SHIFT (24U) +#define PXP_HANDSHAKE_READY_MUX0_HSK6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK6_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK6_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK7_MASK (0xF0000000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK7_SHIFT (28U) +#define PXP_HANDSHAKE_READY_MUX0_HSK7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK7_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK7_MASK) + +/*! @name HANDSHAKE_READY_MUX1 - This register defines the pxp subblock handshake signals ready mux on top level. */ +#define PXP_HANDSHAKE_READY_MUX1_HSK8_MASK (0xFU) +#define PXP_HANDSHAKE_READY_MUX1_HSK8_SHIFT (0U) +#define PXP_HANDSHAKE_READY_MUX1_HSK8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK8_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK8_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK9_MASK (0xF0U) +#define PXP_HANDSHAKE_READY_MUX1_HSK9_SHIFT (4U) +#define PXP_HANDSHAKE_READY_MUX1_HSK9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK9_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK9_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK10_MASK (0xF00U) +#define PXP_HANDSHAKE_READY_MUX1_HSK10_SHIFT (8U) +#define PXP_HANDSHAKE_READY_MUX1_HSK10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK10_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK10_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK11_MASK (0xF000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK11_SHIFT (12U) +#define PXP_HANDSHAKE_READY_MUX1_HSK11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK11_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK11_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK12_MASK (0xF0000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK12_SHIFT (16U) +#define PXP_HANDSHAKE_READY_MUX1_HSK12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK12_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK12_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK13_MASK (0xF00000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK13_SHIFT (20U) +#define PXP_HANDSHAKE_READY_MUX1_HSK13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK13_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK13_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK14_MASK (0xF000000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK14_SHIFT (24U) +#define PXP_HANDSHAKE_READY_MUX1_HSK14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK14_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK14_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK15_MASK (0xF0000000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK15_SHIFT (28U) +#define PXP_HANDSHAKE_READY_MUX1_HSK15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK15_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK15_MASK) + +/*! @name HANDSHAKE_DONE_MUX0 - This register defines the pxp subblock handshake signals done mux on top level. */ +#define PXP_HANDSHAKE_DONE_MUX0_HSK0_MASK (0xFU) +#define PXP_HANDSHAKE_DONE_MUX0_HSK0_SHIFT (0U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK0_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK0_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK1_MASK (0xF0U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK1_SHIFT (4U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK1_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK1_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK2_MASK (0xF00U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK2_SHIFT (8U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK2_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK2_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK3_MASK (0xF000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK3_SHIFT (12U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK3_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK3_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK4_MASK (0xF0000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK4_SHIFT (16U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK4_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK4_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK5_MASK (0xF00000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK5_SHIFT (20U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK5_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK5_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK6_MASK (0xF000000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK6_SHIFT (24U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK6_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK6_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK7_MASK (0xF0000000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK7_SHIFT (28U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK7_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK7_MASK) + +/*! @name HANDSHAKE_DONE_MUX1 - This register defines the pxp subblock handshake signals done mux on top level. */ +#define PXP_HANDSHAKE_DONE_MUX1_HSK8_MASK (0xFU) +#define PXP_HANDSHAKE_DONE_MUX1_HSK8_SHIFT (0U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK8_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK8_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK9_MASK (0xF0U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK9_SHIFT (4U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK9_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK9_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK10_MASK (0xF00U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK10_SHIFT (8U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK10_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK10_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK11_MASK (0xF000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK11_SHIFT (12U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK11_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK11_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK12_MASK (0xF0000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK12_SHIFT (16U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK12_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK12_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK13_MASK (0xF00000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK13_SHIFT (20U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK13_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK13_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK14_MASK (0xF000000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK14_SHIFT (24U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK14_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK14_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK15_MASK (0xF0000000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK15_SHIFT (28U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK15_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK15_MASK) + + +/*! + * @} + */ /* end of group PXP_Register_Masks */ + + +/* PXP - Peripheral instance base addresses */ +/** Peripheral PXP base address */ +#define PXP_BASE (0x21CC000u) +/** Peripheral PXP base pointer */ +#define PXP ((PXP_Type *)PXP_BASE) +/** Array initializer of PXP peripheral base addresses */ +#define PXP_BASE_ADDRS { PXP_BASE } +/** Array initializer of PXP peripheral base pointers */ +#define PXP_BASE_PTRS { PXP } +/** Interrupt vectors for the PXP peripheral type */ +#define PXP_IRQ0_IRQS { PXP_IRQ0_IRQn } +#define PXP_IRQ1_IRQS { PXP_IRQ1_IRQn } + +/*! + * @} + */ /* end of group PXP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- QuadSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer + * @{ + */ + +/** QuadSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ + __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */ + __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */ + __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */ + __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */ + __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */ + __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ + __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */ + __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */ + uint8_t RESERVED_2[196]; + __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */ + uint8_t RESERVED_3[4]; + __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */ + __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */ + __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */ + uint8_t RESERVED_4[60]; + __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ + __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ + uint8_t RESERVED_5[4]; + __I uint32_t SR; /**< Status Register, offset: 0x15C */ + __IO uint32_t FR; /**< Flag Register, offset: 0x160 */ + __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */ + __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */ + __IO uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */ + uint8_t RESERVED_6[16]; + __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */ + __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */ + __IO uint32_t SFB1AD; /**< Serial Flash B1Top Address, offset: 0x188 */ + __IO uint32_t SFB2AD; /**< Serial Flash B2Top Address, offset: 0x18C */ + uint8_t RESERVED_7[112]; + __IO uint32_t RBDR[32]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[128]; + __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */ + __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */ + uint8_t RESERVED_9[8]; + __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */ +} QuadSPI_Type; + +/* ---------------------------------------------------------------------------- + -- QuadSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +#define QuadSPI_MCR_SWRSTSD_MASK (0x1U) +#define QuadSPI_MCR_SWRSTSD_SHIFT (0U) +#define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK) +#define QuadSPI_MCR_SWRSTHD_MASK (0x2U) +#define QuadSPI_MCR_SWRSTHD_SHIFT (1U) +#define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK) +#define QuadSPI_MCR_END_CFG_MASK (0xCU) +#define QuadSPI_MCR_END_CFG_SHIFT (2U) +#define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_END_CFG_SHIFT)) & QuadSPI_MCR_END_CFG_MASK) +#define QuadSPI_MCR_DQS_EN_MASK (0x40U) +#define QuadSPI_MCR_DQS_EN_SHIFT (6U) +#define QuadSPI_MCR_DQS_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK) +#define QuadSPI_MCR_DDR_EN_MASK (0x80U) +#define QuadSPI_MCR_DDR_EN_SHIFT (7U) +#define QuadSPI_MCR_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK) +#define QuadSPI_MCR_CLR_RXF_MASK (0x400U) +#define QuadSPI_MCR_CLR_RXF_SHIFT (10U) +#define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK) +#define QuadSPI_MCR_CLR_TXF_MASK (0x800U) +#define QuadSPI_MCR_CLR_TXF_SHIFT (11U) +#define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK) +#define QuadSPI_MCR_MDIS_MASK (0x4000U) +#define QuadSPI_MCR_MDIS_SHIFT (14U) +#define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK) +#define QuadSPI_MCR_DQS_LOOPBACK_EN_MASK (0x1000000U) +#define QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT (24U) +#define QuadSPI_MCR_DQS_LOOPBACK_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT)) & QuadSPI_MCR_DQS_LOOPBACK_EN_MASK) +#define QuadSPI_MCR_DQS_PHASE_EN_MASK (0x40000000U) +#define QuadSPI_MCR_DQS_PHASE_EN_SHIFT (30U) +#define QuadSPI_MCR_DQS_PHASE_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_PHASE_EN_SHIFT)) & QuadSPI_MCR_DQS_PHASE_EN_MASK) + +/*! @name IPCR - IP Configuration Register */ +#define QuadSPI_IPCR_IDATSZ_MASK (0xFFFFU) +#define QuadSPI_IPCR_IDATSZ_SHIFT (0U) +#define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK) +#define QuadSPI_IPCR_PAR_EN_MASK (0x10000U) +#define QuadSPI_IPCR_PAR_EN_SHIFT (16U) +#define QuadSPI_IPCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_PAR_EN_SHIFT)) & QuadSPI_IPCR_PAR_EN_MASK) +#define QuadSPI_IPCR_SEQID_MASK (0xF000000U) +#define QuadSPI_IPCR_SEQID_SHIFT (24U) +#define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK) + +/*! @name FLSHCR - Flash Configuration Register */ +#define QuadSPI_FLSHCR_TCSS_MASK (0xFU) +#define QuadSPI_FLSHCR_TCSS_SHIFT (0U) +#define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK) +#define QuadSPI_FLSHCR_TCSH_MASK (0xF00U) +#define QuadSPI_FLSHCR_TCSH_SHIFT (8U) +#define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK) + +/*! @name BUF0CR - Buffer0 Configuration Register */ +#define QuadSPI_BUF0CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF0CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK) +#define QuadSPI_BUF0CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF0CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK) +#define QuadSPI_BUF0CR_HP_EN_MASK (0x80000000U) +#define QuadSPI_BUF0CR_HP_EN_SHIFT (31U) +#define QuadSPI_BUF0CR_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_HP_EN_SHIFT)) & QuadSPI_BUF0CR_HP_EN_MASK) + +/*! @name BUF1CR - Buffer1 Configuration Register */ +#define QuadSPI_BUF1CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF1CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK) +#define QuadSPI_BUF1CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF1CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK) + +/*! @name BUF2CR - Buffer2 Configuration Register */ +#define QuadSPI_BUF2CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF2CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK) +#define QuadSPI_BUF2CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF2CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK) + +/*! @name BUF3CR - Buffer3 Configuration Register */ +#define QuadSPI_BUF3CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF3CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK) +#define QuadSPI_BUF3CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF3CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK) +#define QuadSPI_BUF3CR_ALLMST_MASK (0x80000000U) +#define QuadSPI_BUF3CR_ALLMST_SHIFT (31U) +#define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK) + +/*! @name BFGENCR - Buffer Generic Configuration Register */ +#define QuadSPI_BFGENCR_SEQID_MASK (0xF000U) +#define QuadSPI_BFGENCR_SEQID_SHIFT (12U) +#define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK) +#define QuadSPI_BFGENCR_PAR_EN_MASK (0x10000U) +#define QuadSPI_BFGENCR_PAR_EN_SHIFT (16U) +#define QuadSPI_BFGENCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_PAR_EN_SHIFT)) & QuadSPI_BFGENCR_PAR_EN_MASK) + +/*! @name BUF0IND - Buffer0 Top Index Register */ +#define QuadSPI_BUF0IND_TPINDX0_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF0IND_TPINDX0_SHIFT (3U) +#define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK) + +/*! @name BUF1IND - Buffer1 Top Index Register */ +#define QuadSPI_BUF1IND_TPINDX1_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF1IND_TPINDX1_SHIFT (3U) +#define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK) + +/*! @name BUF2IND - Buffer2 Top Index Register */ +#define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF2IND_TPINDX2_SHIFT (3U) +#define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK) + +/*! @name SFAR - Serial Flash Address Register */ +#define QuadSPI_SFAR_SFADR_MASK (0xFFFFFFFFU) +#define QuadSPI_SFAR_SFADR_SHIFT (0U) +#define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK) + +/*! @name SMPR - Sampling Register */ +#define QuadSPI_SMPR_SDRSMP_MASK (0x60U) +#define QuadSPI_SMPR_SDRSMP_SHIFT (5U) +#define QuadSPI_SMPR_SDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_SDRSMP_SHIFT)) & QuadSPI_SMPR_SDRSMP_MASK) +#define QuadSPI_SMPR_DDRSMP_MASK (0x70000U) +#define QuadSPI_SMPR_DDRSMP_SHIFT (16U) +#define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DDRSMP_SHIFT)) & QuadSPI_SMPR_DDRSMP_MASK) + +/*! @name RBSR - RX Buffer Status Register */ +#define QuadSPI_RBSR_RDBFL_MASK (0x3F00U) +#define QuadSPI_RBSR_RDBFL_SHIFT (8U) +#define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK) +#define QuadSPI_RBSR_RDCTR_MASK (0xFFFF0000U) +#define QuadSPI_RBSR_RDCTR_SHIFT (16U) +#define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK) + +/*! @name RBCT - RX Buffer Control Register */ +#define QuadSPI_RBCT_WMRK_MASK (0x1FU) +#define QuadSPI_RBCT_WMRK_SHIFT (0U) +#define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK) +#define QuadSPI_RBCT_RXBRD_MASK (0x100U) +#define QuadSPI_RBCT_RXBRD_SHIFT (8U) +#define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK) + +/*! @name TBSR - TX Buffer Status Register */ +#define QuadSPI_TBSR_TRBFL_MASK (0x1F00U) +#define QuadSPI_TBSR_TRBFL_SHIFT (8U) +#define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK) +#define QuadSPI_TBSR_TRCTR_MASK (0xFFFF0000U) +#define QuadSPI_TBSR_TRCTR_SHIFT (16U) +#define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK) + +/*! @name TBDR - TX Buffer Data Register */ +#define QuadSPI_TBDR_TXDATA_MASK (0xFFFFFFFFU) +#define QuadSPI_TBDR_TXDATA_SHIFT (0U) +#define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK) + +/*! @name SR - Status Register */ +#define QuadSPI_SR_BUSY_MASK (0x1U) +#define QuadSPI_SR_BUSY_SHIFT (0U) +#define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK) +#define QuadSPI_SR_IP_ACC_MASK (0x2U) +#define QuadSPI_SR_IP_ACC_SHIFT (1U) +#define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK) +#define QuadSPI_SR_AHB_ACC_MASK (0x4U) +#define QuadSPI_SR_AHB_ACC_SHIFT (2U) +#define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK) +#define QuadSPI_SR_AHBGNT_MASK (0x20U) +#define QuadSPI_SR_AHBGNT_SHIFT (5U) +#define QuadSPI_SR_AHBGNT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBGNT_SHIFT)) & QuadSPI_SR_AHBGNT_MASK) +#define QuadSPI_SR_AHBTRN_MASK (0x40U) +#define QuadSPI_SR_AHBTRN_SHIFT (6U) +#define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK) +#define QuadSPI_SR_AHB0NE_MASK (0x80U) +#define QuadSPI_SR_AHB0NE_SHIFT (7U) +#define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK) +#define QuadSPI_SR_AHB1NE_MASK (0x100U) +#define QuadSPI_SR_AHB1NE_SHIFT (8U) +#define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK) +#define QuadSPI_SR_AHB2NE_MASK (0x200U) +#define QuadSPI_SR_AHB2NE_SHIFT (9U) +#define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK) +#define QuadSPI_SR_AHB3NE_MASK (0x400U) +#define QuadSPI_SR_AHB3NE_SHIFT (10U) +#define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK) +#define QuadSPI_SR_AHB0FUL_MASK (0x800U) +#define QuadSPI_SR_AHB0FUL_SHIFT (11U) +#define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK) +#define QuadSPI_SR_AHB1FUL_MASK (0x1000U) +#define QuadSPI_SR_AHB1FUL_SHIFT (12U) +#define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK) +#define QuadSPI_SR_AHB2FUL_MASK (0x2000U) +#define QuadSPI_SR_AHB2FUL_SHIFT (13U) +#define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK) +#define QuadSPI_SR_AHB3FUL_MASK (0x4000U) +#define QuadSPI_SR_AHB3FUL_SHIFT (14U) +#define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK) +#define QuadSPI_SR_RXWE_MASK (0x10000U) +#define QuadSPI_SR_RXWE_SHIFT (16U) +#define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK) +#define QuadSPI_SR_RXFULL_MASK (0x80000U) +#define QuadSPI_SR_RXFULL_SHIFT (19U) +#define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK) +#define QuadSPI_SR_RXDMA_MASK (0x800000U) +#define QuadSPI_SR_RXDMA_SHIFT (23U) +#define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK) +#define QuadSPI_SR_TXEDA_MASK (0x1000000U) +#define QuadSPI_SR_TXEDA_SHIFT (24U) +#define QuadSPI_SR_TXEDA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK) +#define QuadSPI_SR_TXFULL_MASK (0x8000000U) +#define QuadSPI_SR_TXFULL_SHIFT (27U) +#define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK) +#define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) +#define QuadSPI_SR_DLPSMP_SHIFT (29U) +#define QuadSPI_SR_DLPSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK) + +/*! @name FR - Flag Register */ +#define QuadSPI_FR_TFF_MASK (0x1U) +#define QuadSPI_FR_TFF_SHIFT (0U) +#define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK) +#define QuadSPI_FR_IPGEF_MASK (0x10U) +#define QuadSPI_FR_IPGEF_SHIFT (4U) +#define QuadSPI_FR_IPGEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPGEF_SHIFT)) & QuadSPI_FR_IPGEF_MASK) +#define QuadSPI_FR_IPIEF_MASK (0x40U) +#define QuadSPI_FR_IPIEF_SHIFT (6U) +#define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK) +#define QuadSPI_FR_IPAEF_MASK (0x80U) +#define QuadSPI_FR_IPAEF_SHIFT (7U) +#define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK) +#define QuadSPI_FR_IUEF_MASK (0x800U) +#define QuadSPI_FR_IUEF_SHIFT (11U) +#define QuadSPI_FR_IUEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IUEF_SHIFT)) & QuadSPI_FR_IUEF_MASK) +#define QuadSPI_FR_ABOF_MASK (0x1000U) +#define QuadSPI_FR_ABOF_SHIFT (12U) +#define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK) +#define QuadSPI_FR_ABSEF_MASK (0x8000U) +#define QuadSPI_FR_ABSEF_SHIFT (15U) +#define QuadSPI_FR_ABSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK) +#define QuadSPI_FR_RBDF_MASK (0x10000U) +#define QuadSPI_FR_RBDF_SHIFT (16U) +#define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK) +#define QuadSPI_FR_RBOF_MASK (0x20000U) +#define QuadSPI_FR_RBOF_SHIFT (17U) +#define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK) +#define QuadSPI_FR_ILLINE_MASK (0x800000U) +#define QuadSPI_FR_ILLINE_SHIFT (23U) +#define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK) +#define QuadSPI_FR_TBUF_MASK (0x4000000U) +#define QuadSPI_FR_TBUF_SHIFT (26U) +#define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK) +#define QuadSPI_FR_TBFF_MASK (0x8000000U) +#define QuadSPI_FR_TBFF_SHIFT (27U) +#define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK) +#define QuadSPI_FR_DLPFF_MASK (0x80000000U) +#define QuadSPI_FR_DLPFF_SHIFT (31U) +#define QuadSPI_FR_DLPFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLPFF_SHIFT)) & QuadSPI_FR_DLPFF_MASK) + +/*! @name RSER - Interrupt and DMA Request Select and Enable Register */ +#define QuadSPI_RSER_TFIE_MASK (0x1U) +#define QuadSPI_RSER_TFIE_SHIFT (0U) +#define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK) +#define QuadSPI_RSER_IPGEIE_MASK (0x10U) +#define QuadSPI_RSER_IPGEIE_SHIFT (4U) +#define QuadSPI_RSER_IPGEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPGEIE_SHIFT)) & QuadSPI_RSER_IPGEIE_MASK) +#define QuadSPI_RSER_IPIEIE_MASK (0x40U) +#define QuadSPI_RSER_IPIEIE_SHIFT (6U) +#define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK) +#define QuadSPI_RSER_IPAEIE_MASK (0x80U) +#define QuadSPI_RSER_IPAEIE_SHIFT (7U) +#define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK) +#define QuadSPI_RSER_IUEIE_MASK (0x800U) +#define QuadSPI_RSER_IUEIE_SHIFT (11U) +#define QuadSPI_RSER_IUEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IUEIE_SHIFT)) & QuadSPI_RSER_IUEIE_MASK) +#define QuadSPI_RSER_ABOIE_MASK (0x1000U) +#define QuadSPI_RSER_ABOIE_SHIFT (12U) +#define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK) +#define QuadSPI_RSER_ABSEIE_MASK (0x8000U) +#define QuadSPI_RSER_ABSEIE_SHIFT (15U) +#define QuadSPI_RSER_ABSEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABSEIE_SHIFT)) & QuadSPI_RSER_ABSEIE_MASK) +#define QuadSPI_RSER_RBDIE_MASK (0x10000U) +#define QuadSPI_RSER_RBDIE_SHIFT (16U) +#define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK) +#define QuadSPI_RSER_RBOIE_MASK (0x20000U) +#define QuadSPI_RSER_RBOIE_SHIFT (17U) +#define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK) +#define QuadSPI_RSER_RBDDE_MASK (0x200000U) +#define QuadSPI_RSER_RBDDE_SHIFT (21U) +#define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK) +#define QuadSPI_RSER_ILLINIE_MASK (0x800000U) +#define QuadSPI_RSER_ILLINIE_SHIFT (23U) +#define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK) +#define QuadSPI_RSER_TBUIE_MASK (0x4000000U) +#define QuadSPI_RSER_TBUIE_SHIFT (26U) +#define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK) +#define QuadSPI_RSER_TBFIE_MASK (0x8000000U) +#define QuadSPI_RSER_TBFIE_SHIFT (27U) +#define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK) +#define QuadSPI_RSER_DLPFIE_MASK (0x80000000U) +#define QuadSPI_RSER_DLPFIE_SHIFT (31U) +#define QuadSPI_RSER_DLPFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLPFIE_SHIFT)) & QuadSPI_RSER_DLPFIE_MASK) + +/*! @name SPNDST - Sequence Suspend Status Register */ +#define QuadSPI_SPNDST_SUSPND_MASK (0x1U) +#define QuadSPI_SPNDST_SUSPND_SHIFT (0U) +#define QuadSPI_SPNDST_SUSPND(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SUSPND_SHIFT)) & QuadSPI_SPNDST_SUSPND_MASK) +#define QuadSPI_SPNDST_SPDBUF_MASK (0xC0U) +#define QuadSPI_SPNDST_SPDBUF_SHIFT (6U) +#define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SPDBUF_SHIFT)) & QuadSPI_SPNDST_SPDBUF_MASK) +#define QuadSPI_SPNDST_DATLFT_MASK (0xFE00U) +#define QuadSPI_SPNDST_DATLFT_SHIFT (9U) +#define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_DATLFT_SHIFT)) & QuadSPI_SPNDST_DATLFT_MASK) + +/*! @name SPTRCLR - Sequence Pointer Clear Register */ +#define QuadSPI_SPTRCLR_BFPTRC_MASK (0x1U) +#define QuadSPI_SPTRCLR_BFPTRC_SHIFT (0U) +#define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK) +#define QuadSPI_SPTRCLR_IPPTRC_MASK (0x100U) +#define QuadSPI_SPTRCLR_IPPTRC_SHIFT (8U) +#define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK) + +/*! @name SFA1AD - Serial Flash A1 Top Address */ +#define QuadSPI_SFA1AD_TPADA1_MASK (0xFFFFFC00U) +#define QuadSPI_SFA1AD_TPADA1_SHIFT (10U) +#define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK) + +/*! @name SFA2AD - Serial Flash A2 Top Address */ +#define QuadSPI_SFA2AD_TPADA2_MASK (0xFFFFFC00U) +#define QuadSPI_SFA2AD_TPADA2_SHIFT (10U) +#define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK) + +/*! @name SFB1AD - Serial Flash B1Top Address */ +#define QuadSPI_SFB1AD_TPADB1_MASK (0xFFFFFC00U) +#define QuadSPI_SFB1AD_TPADB1_SHIFT (10U) +#define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK) + +/*! @name SFB2AD - Serial Flash B2Top Address */ +#define QuadSPI_SFB2AD_TPADB2_MASK (0xFFFFFC00U) +#define QuadSPI_SFB2AD_TPADB2_SHIFT (10U) +#define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK) + +/*! @name RBDR - RX Buffer Data Register */ +#define QuadSPI_RBDR_RXDATA_MASK (0xFFFFFFFFU) +#define QuadSPI_RBDR_RXDATA_SHIFT (0U) +#define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK) + +/* The count of QuadSPI_RBDR */ +#define QuadSPI_RBDR_COUNT (32U) + +/*! @name LUTKEY - LUT Key Register */ +#define QuadSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define QuadSPI_LUTKEY_KEY_SHIFT (0U) +#define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK) + +/*! @name LCKCR - LUT Lock Configuration Register */ +#define QuadSPI_LCKCR_LOCK_MASK (0x1U) +#define QuadSPI_LCKCR_LOCK_SHIFT (0U) +#define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK) +#define QuadSPI_LCKCR_UNLOCK_MASK (0x2U) +#define QuadSPI_LCKCR_UNLOCK_SHIFT (1U) +#define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK) + +/*! @name LUT - Look-up Table register */ +#define QuadSPI_LUT_OPRND0_MASK (0xFFU) +#define QuadSPI_LUT_OPRND0_SHIFT (0U) +#define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK) +#define QuadSPI_LUT_PAD0_MASK (0x300U) +#define QuadSPI_LUT_PAD0_SHIFT (8U) +#define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK) +#define QuadSPI_LUT_INSTR0_MASK (0xFC00U) +#define QuadSPI_LUT_INSTR0_SHIFT (10U) +#define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK) +#define QuadSPI_LUT_OPRND1_MASK (0xFF0000U) +#define QuadSPI_LUT_OPRND1_SHIFT (16U) +#define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK) +#define QuadSPI_LUT_PAD1_MASK (0x3000000U) +#define QuadSPI_LUT_PAD1_SHIFT (24U) +#define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK) +#define QuadSPI_LUT_INSTR1_MASK (0xFC000000U) +#define QuadSPI_LUT_INSTR1_SHIFT (26U) +#define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK) + +/* The count of QuadSPI_LUT */ +#define QuadSPI_LUT_COUNT (64U) + + +/*! + * @} + */ /* end of group QuadSPI_Register_Masks */ + + +/* QuadSPI - Peripheral instance base addresses */ +/** Peripheral QuadSPI base address */ +#define QuadSPI_BASE (0x21E0000u) +/** Peripheral QuadSPI base pointer */ +#define QuadSPI ((QuadSPI_Type *)QuadSPI_BASE) +/** Array initializer of QuadSPI peripheral base addresses */ +#define QuadSPI_BASE_ADDRS { QuadSPI_BASE } +/** Array initializer of QuadSPI peripheral base pointers */ +#define QuadSPI_BASE_PTRS { QuadSPI } +/** Interrupt vectors for the QuadSPI peripheral type */ +#define QuadSPI_IRQS { QSPI_IRQn } + +/*! + * @} + */ /* end of group QuadSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer + * @{ + */ + +/** RNG - Register Layout Typedef */ +typedef struct { + __I uint32_t VER; /**< RNGB version ID register, offset: 0x0 */ + __IO uint32_t CMD; /**< RNGB command register, offset: 0x4 */ + __IO uint32_t CR; /**< RNGB control register, offset: 0x8 */ + __I uint32_t SR; /**< RNGB status register, offset: 0xC */ + __I uint32_t ESR; /**< RNGB error status register, offset: 0x10 */ + __I uint32_t OUT; /**< RNGB Output FIFO, offset: 0x14 */ +} RNG_Type; + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/*! @name VER - RNGB version ID register */ +#define RNG_VER_MINOR_MASK (0xFFU) +#define RNG_VER_MINOR_SHIFT (0U) +#define RNG_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << RNG_VER_MINOR_SHIFT)) & RNG_VER_MINOR_MASK) +#define RNG_VER_MAJOR_MASK (0xFF00U) +#define RNG_VER_MAJOR_SHIFT (8U) +#define RNG_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << RNG_VER_MAJOR_SHIFT)) & RNG_VER_MAJOR_MASK) +#define RNG_VER_TYPE_MASK (0xF0000000U) +#define RNG_VER_TYPE_SHIFT (28U) +#define RNG_VER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << RNG_VER_TYPE_SHIFT)) & RNG_VER_TYPE_MASK) + +/*! @name CMD - RNGB command register */ +#define RNG_CMD_ST_MASK (0x1U) +#define RNG_CMD_ST_SHIFT (0U) +#define RNG_CMD_ST(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_ST_SHIFT)) & RNG_CMD_ST_MASK) +#define RNG_CMD_GS_MASK (0x2U) +#define RNG_CMD_GS_SHIFT (1U) +#define RNG_CMD_GS(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_GS_SHIFT)) & RNG_CMD_GS_MASK) +#define RNG_CMD_CI_MASK (0x10U) +#define RNG_CMD_CI_SHIFT (4U) +#define RNG_CMD_CI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_CI_SHIFT)) & RNG_CMD_CI_MASK) +#define RNG_CMD_CE_MASK (0x20U) +#define RNG_CMD_CE_SHIFT (5U) +#define RNG_CMD_CE(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_CE_SHIFT)) & RNG_CMD_CE_MASK) +#define RNG_CMD_SR_MASK (0x40U) +#define RNG_CMD_SR_SHIFT (6U) +#define RNG_CMD_SR(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_SR_SHIFT)) & RNG_CMD_SR_MASK) + +/*! @name CR - RNGB control register */ +#define RNG_CR_FUFMOD_MASK (0x3U) +#define RNG_CR_FUFMOD_SHIFT (0U) +#define RNG_CR_FUFMOD(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_FUFMOD_SHIFT)) & RNG_CR_FUFMOD_MASK) +#define RNG_CR_AR_MASK (0x10U) +#define RNG_CR_AR_SHIFT (4U) +#define RNG_CR_AR(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_AR_SHIFT)) & RNG_CR_AR_MASK) +#define RNG_CR_MASKDONE_MASK (0x20U) +#define RNG_CR_MASKDONE_SHIFT (5U) +#define RNG_CR_MASKDONE(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_MASKDONE_SHIFT)) & RNG_CR_MASKDONE_MASK) +#define RNG_CR_MASKERR_MASK (0x40U) +#define RNG_CR_MASKERR_SHIFT (6U) +#define RNG_CR_MASKERR(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_MASKERR_SHIFT)) & RNG_CR_MASKERR_MASK) + +/*! @name SR - RNGB status register */ +#define RNG_SR_BUSY_MASK (0x2U) +#define RNG_SR_BUSY_SHIFT (1U) +#define RNG_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_BUSY_SHIFT)) & RNG_SR_BUSY_MASK) +#define RNG_SR_SLP_MASK (0x4U) +#define RNG_SR_SLP_SHIFT (2U) +#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK) +#define RNG_SR_RS_MASK (0x8U) +#define RNG_SR_RS_SHIFT (3U) +#define RNG_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_RS_SHIFT)) & RNG_SR_RS_MASK) +#define RNG_SR_STDN_MASK (0x10U) +#define RNG_SR_STDN_SHIFT (4U) +#define RNG_SR_STDN(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_STDN_SHIFT)) & RNG_SR_STDN_MASK) +#define RNG_SR_SDN_MASK (0x20U) +#define RNG_SR_SDN_SHIFT (5U) +#define RNG_SR_SDN(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SDN_SHIFT)) & RNG_SR_SDN_MASK) +#define RNG_SR_NSDN_MASK (0x40U) +#define RNG_SR_NSDN_SHIFT (6U) +#define RNG_SR_NSDN(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_NSDN_SHIFT)) & RNG_SR_NSDN_MASK) +#define RNG_SR_FIFO_LVL_MASK (0xF00U) +#define RNG_SR_FIFO_LVL_SHIFT (8U) +#define RNG_SR_FIFO_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_FIFO_LVL_SHIFT)) & RNG_SR_FIFO_LVL_MASK) +#define RNG_SR_FIFO_SIZE_MASK (0xF000U) +#define RNG_SR_FIFO_SIZE_SHIFT (12U) +#define RNG_SR_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_FIFO_SIZE_SHIFT)) & RNG_SR_FIFO_SIZE_MASK) +#define RNG_SR_ERR_MASK (0x10000U) +#define RNG_SR_ERR_SHIFT (16U) +#define RNG_SR_ERR(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERR_SHIFT)) & RNG_SR_ERR_MASK) +#define RNG_SR_ST_PF_MASK (0xE00000U) +#define RNG_SR_ST_PF_SHIFT (21U) +#define RNG_SR_ST_PF(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ST_PF_SHIFT)) & RNG_SR_ST_PF_MASK) +#define RNG_SR_STATPF_MASK (0xFF000000U) +#define RNG_SR_STATPF_SHIFT (24U) +#define RNG_SR_STATPF(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_STATPF_SHIFT)) & RNG_SR_STATPF_MASK) + +/*! @name ESR - RNGB error status register */ +#define RNG_ESR_LFE_MASK (0x1U) +#define RNG_ESR_LFE_SHIFT (0U) +#define RNG_ESR_LFE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_LFE_SHIFT)) & RNG_ESR_LFE_MASK) +#define RNG_ESR_OSCE_MASK (0x2U) +#define RNG_ESR_OSCE_SHIFT (1U) +#define RNG_ESR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_OSCE_SHIFT)) & RNG_ESR_OSCE_MASK) +#define RNG_ESR_STE_MASK (0x4U) +#define RNG_ESR_STE_SHIFT (2U) +#define RNG_ESR_STE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_STE_SHIFT)) & RNG_ESR_STE_MASK) +#define RNG_ESR_SATE_MASK (0x8U) +#define RNG_ESR_SATE_SHIFT (3U) +#define RNG_ESR_SATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_SATE_SHIFT)) & RNG_ESR_SATE_MASK) +#define RNG_ESR_FUFE_MASK (0x10U) +#define RNG_ESR_FUFE_SHIFT (4U) +#define RNG_ESR_FUFE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_FUFE_SHIFT)) & RNG_ESR_FUFE_MASK) + +/*! @name OUT - RNGB Output FIFO */ +#define RNG_OUT_RANDOUT_MASK (0xFFFFFFFFU) +#define RNG_OUT_RANDOUT_SHIFT (0U) +#define RNG_OUT_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OUT_RANDOUT_SHIFT)) & RNG_OUT_RANDOUT_MASK) + + +/*! + * @} + */ /* end of group RNG_Register_Masks */ + + +/* RNG - Peripheral instance base addresses */ +/** Peripheral RNG base address */ +#define RNG_BASE (0x2284000u) +/** Peripheral RNG base pointer */ +#define RNG ((RNG_Type *)RNG_BASE) +/** Array initializer of RNG peripheral base addresses */ +#define RNG_BASE_ADDRS { RNG_BASE } +/** Array initializer of RNG peripheral base pointers */ +#define RNG_BASE_PTRS { RNG } + +/*! + * @} + */ /* end of group RNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ROMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer + * @{ + */ + +/** ROMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[212]; + __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ + __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ + __I uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ + __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ + __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_1[200]; + __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ +} ROMC_Type; + +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/*! @name ROMPATCHD - ROMC Data Registers */ +#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) +#define ROMC_ROMPATCHD_DATAX_SHIFT (0U) +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) + +/* The count of ROMC_ROMPATCHD */ +#define ROMC_ROMPATCHD_COUNT (8U) + +/*! @name ROMPATCHCNTL - ROMC Control Register */ +#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) +#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) +#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) +#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) +#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) +#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) + +/*! @name ROMPATCHENL - ROMC Enable Register Low */ +#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) +#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) +#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) + +/*! @name ROMPATCHA - ROMC Address Registers */ +#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) +#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) +#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) +#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) +#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) +#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) + +/* The count of ROMC_ROMPATCHA */ +#define ROMC_ROMPATCHA_COUNT (16U) + +/*! @name ROMPATCHSR - ROMC Status Register */ +#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) +#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) +#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) +#define ROMC_ROMPATCHSR_SW_MASK (0x20000U) +#define ROMC_ROMPATCHSR_SW_SHIFT (17U) +#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) + + +/*! + * @} + */ /* end of group ROMC_Register_Masks */ + + +/* ROMC - Peripheral instance base addresses */ +/** Peripheral ROMC base address */ +#define ROMC_BASE (0x21AC000u) +/** Peripheral ROMC base pointer */ +#define ROMC ((ROMC_Type *)ROMC_BASE) +/** Array initializer of ROMC peripheral base addresses */ +#define ROMC_BASE_ADDRS { ROMC_BASE } +/** Array initializer of ROMC peripheral base pointers */ +#define ROMC_BASE_PTRS { ROMC } + +/*! + * @} + */ /* end of group ROMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SDMAARM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer + * @{ + */ + +/** SDMAARM - Register Layout Typedef */ +typedef struct { + __IO uint32_t MC0PTR; /**< ARM platform Channel 0 Pointer, offset: 0x0 */ + __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ + __IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */ + __IO uint32_t HSTART; /**< Channel Start, offset: 0xC */ + __IO uint32_t EVTOVR; /**< Channel Event Override, offset: 0x10 */ + __IO uint32_t DSPOVR; /**< Channel BP Override, offset: 0x14 */ + __IO uint32_t HOSTOVR; /**< Channel ARM platform Override, offset: 0x18 */ + __IO uint32_t EVTPEND; /**< Channel Event Pending, offset: 0x1C */ + uint8_t RESERVED_0[4]; + __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ + __I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */ + __IO uint32_t INTRMASK; /**< Channel ARM platform Interrupt Mask, offset: 0x2C */ + __I uint32_t PSW; /**< Schedule Status, offset: 0x30 */ + __I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */ + __IO uint32_t CONFIG; /**< Configuration Register, offset: 0x38 */ + __IO uint32_t SDMA_LOCK; /**< SDMA LOCK, offset: 0x3C */ + __IO uint32_t ONCE_ENB; /**< OnCE Enable, offset: 0x40 */ + __IO uint32_t ONCE_DATA; /**< OnCE Data Register, offset: 0x44 */ + __IO uint32_t ONCE_INSTR; /**< OnCE Instruction Register, offset: 0x48 */ + __I uint32_t ONCE_STAT; /**< OnCE Status Register, offset: 0x4C */ + __IO uint32_t ONCE_CMD; /**< OnCE Command Register, offset: 0x50 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ILLINSTADDR; /**< Illegal Instruction Trap Address, offset: 0x58 */ + __IO uint32_t CHN0ADDR; /**< Channel 0 Boot Address, offset: 0x5C */ + __I uint32_t EVT_MIRROR; /**< DMA Requests, offset: 0x60 */ + __I uint32_t EVT_MIRROR2; /**< DMA Requests 2, offset: 0x64 */ + uint8_t RESERVED_2[8]; + __IO uint32_t XTRIG_CONF1; /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */ + __IO uint32_t XTRIG_CONF2; /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */ + uint8_t RESERVED_3[136]; + __IO uint32_t SDMA_CHNPRI[32]; /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_4[128]; + __IO uint32_t CHNENBL[48]; /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */ +} SDMAARM_Type; + +/* ---------------------------------------------------------------------------- + -- SDMAARM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks + * @{ + */ + +/*! @name MC0PTR - ARM platform Channel 0 Pointer */ +#define SDMAARM_MC0PTR_MC0PTR_MASK (0xFFFFFFFFU) +#define SDMAARM_MC0PTR_MC0PTR_SHIFT (0U) +#define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_MC0PTR_MC0PTR_SHIFT)) & SDMAARM_MC0PTR_MC0PTR_MASK) + +/*! @name INTR - Channel Interrupts */ +#define SDMAARM_INTR_HI_MASK (0xFFFFFFFFU) +#define SDMAARM_INTR_HI_SHIFT (0U) +#define SDMAARM_INTR_HI(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTR_HI_SHIFT)) & SDMAARM_INTR_HI_MASK) + +/*! @name STOP_STAT - Channel Stop/Channel Status */ +#define SDMAARM_STOP_STAT_HE_MASK (0xFFFFFFFFU) +#define SDMAARM_STOP_STAT_HE_SHIFT (0U) +#define SDMAARM_STOP_STAT_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_STOP_STAT_HE_SHIFT)) & SDMAARM_STOP_STAT_HE_MASK) + +/*! @name HSTART - Channel Start */ +#define SDMAARM_HSTART_HSTART_HE_MASK (0xFFFFFFFFU) +#define SDMAARM_HSTART_HSTART_HE_SHIFT (0U) +#define SDMAARM_HSTART_HSTART_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HSTART_HSTART_HE_SHIFT)) & SDMAARM_HSTART_HSTART_HE_MASK) + +/*! @name EVTOVR - Channel Event Override */ +#define SDMAARM_EVTOVR_EO_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTOVR_EO_SHIFT (0U) +#define SDMAARM_EVTOVR_EO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTOVR_EO_SHIFT)) & SDMAARM_EVTOVR_EO_MASK) + +/*! @name DSPOVR - Channel BP Override */ +#define SDMAARM_DSPOVR_DO_MASK (0xFFFFFFFFU) +#define SDMAARM_DSPOVR_DO_SHIFT (0U) +#define SDMAARM_DSPOVR_DO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DSPOVR_DO_SHIFT)) & SDMAARM_DSPOVR_DO_MASK) + +/*! @name HOSTOVR - Channel ARM platform Override */ +#define SDMAARM_HOSTOVR_HO_MASK (0xFFFFFFFFU) +#define SDMAARM_HOSTOVR_HO_SHIFT (0U) +#define SDMAARM_HOSTOVR_HO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HOSTOVR_HO_SHIFT)) & SDMAARM_HOSTOVR_HO_MASK) + +/*! @name EVTPEND - Channel Event Pending */ +#define SDMAARM_EVTPEND_EP_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTPEND_EP_SHIFT (0U) +#define SDMAARM_EVTPEND_EP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTPEND_EP_SHIFT)) & SDMAARM_EVTPEND_EP_MASK) + +/*! @name RESET - Reset Register */ +#define SDMAARM_RESET_RESET_MASK (0x1U) +#define SDMAARM_RESET_RESET_SHIFT (0U) +#define SDMAARM_RESET_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESET_SHIFT)) & SDMAARM_RESET_RESET_MASK) +#define SDMAARM_RESET_RESCHED_MASK (0x2U) +#define SDMAARM_RESET_RESCHED_SHIFT (1U) +#define SDMAARM_RESET_RESCHED(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESCHED_SHIFT)) & SDMAARM_RESET_RESCHED_MASK) + +/*! @name EVTERR - DMA Request Error Register */ +#define SDMAARM_EVTERR_CHNERR_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTERR_CHNERR_SHIFT (0U) +#define SDMAARM_EVTERR_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERR_CHNERR_SHIFT)) & SDMAARM_EVTERR_CHNERR_MASK) + +/*! @name INTRMASK - Channel ARM platform Interrupt Mask */ +#define SDMAARM_INTRMASK_HIMASK_MASK (0xFFFFFFFFU) +#define SDMAARM_INTRMASK_HIMASK_SHIFT (0U) +#define SDMAARM_INTRMASK_HIMASK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTRMASK_HIMASK_SHIFT)) & SDMAARM_INTRMASK_HIMASK_MASK) + +/*! @name PSW - Schedule Status */ +#define SDMAARM_PSW_CCR_MASK (0xFU) +#define SDMAARM_PSW_CCR_SHIFT (0U) +#define SDMAARM_PSW_CCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCR_SHIFT)) & SDMAARM_PSW_CCR_MASK) +#define SDMAARM_PSW_CCP_MASK (0xF0U) +#define SDMAARM_PSW_CCP_SHIFT (4U) +#define SDMAARM_PSW_CCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCP_SHIFT)) & SDMAARM_PSW_CCP_MASK) +#define SDMAARM_PSW_NCR_MASK (0x1F00U) +#define SDMAARM_PSW_NCR_SHIFT (8U) +#define SDMAARM_PSW_NCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCR_SHIFT)) & SDMAARM_PSW_NCR_MASK) +#define SDMAARM_PSW_NCP_MASK (0xE000U) +#define SDMAARM_PSW_NCP_SHIFT (13U) +#define SDMAARM_PSW_NCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCP_SHIFT)) & SDMAARM_PSW_NCP_MASK) + +/*! @name EVTERRDBG - DMA Request Error Register */ +#define SDMAARM_EVTERRDBG_CHNERR_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTERRDBG_CHNERR_SHIFT (0U) +#define SDMAARM_EVTERRDBG_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERRDBG_CHNERR_SHIFT)) & SDMAARM_EVTERRDBG_CHNERR_MASK) + +/*! @name CONFIG - Configuration Register */ +#define SDMAARM_CONFIG_CSM_MASK (0x3U) +#define SDMAARM_CONFIG_CSM_SHIFT (0U) +#define SDMAARM_CONFIG_CSM(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_CSM_SHIFT)) & SDMAARM_CONFIG_CSM_MASK) +#define SDMAARM_CONFIG_ACR_MASK (0x10U) +#define SDMAARM_CONFIG_ACR_SHIFT (4U) +#define SDMAARM_CONFIG_ACR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_ACR_SHIFT)) & SDMAARM_CONFIG_ACR_MASK) +#define SDMAARM_CONFIG_RTDOBS_MASK (0x800U) +#define SDMAARM_CONFIG_RTDOBS_SHIFT (11U) +#define SDMAARM_CONFIG_RTDOBS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_RTDOBS_SHIFT)) & SDMAARM_CONFIG_RTDOBS_MASK) +#define SDMAARM_CONFIG_DSPDMA_MASK (0x1000U) +#define SDMAARM_CONFIG_DSPDMA_SHIFT (12U) +#define SDMAARM_CONFIG_DSPDMA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_DSPDMA_SHIFT)) & SDMAARM_CONFIG_DSPDMA_MASK) + +/*! @name SDMA_LOCK - SDMA LOCK */ +#define SDMAARM_SDMA_LOCK_LOCK_MASK (0x1U) +#define SDMAARM_SDMA_LOCK_LOCK_SHIFT (0U) +#define SDMAARM_SDMA_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_LOCK_SHIFT)) & SDMAARM_SDMA_LOCK_LOCK_MASK) +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK (0x2U) +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT (1U) +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT)) & SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK) + +/*! @name ONCE_ENB - OnCE Enable */ +#define SDMAARM_ONCE_ENB_ENB_MASK (0x1U) +#define SDMAARM_ONCE_ENB_ENB_SHIFT (0U) +#define SDMAARM_ONCE_ENB_ENB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_ENB_ENB_SHIFT)) & SDMAARM_ONCE_ENB_ENB_MASK) + +/*! @name ONCE_DATA - OnCE Data Register */ +#define SDMAARM_ONCE_DATA_DATA_MASK (0xFFFFFFFFU) +#define SDMAARM_ONCE_DATA_DATA_SHIFT (0U) +#define SDMAARM_ONCE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_DATA_DATA_SHIFT)) & SDMAARM_ONCE_DATA_DATA_MASK) + +/*! @name ONCE_INSTR - OnCE Instruction Register */ +#define SDMAARM_ONCE_INSTR_INSTR_MASK (0xFFFFU) +#define SDMAARM_ONCE_INSTR_INSTR_SHIFT (0U) +#define SDMAARM_ONCE_INSTR_INSTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_INSTR_INSTR_SHIFT)) & SDMAARM_ONCE_INSTR_INSTR_MASK) + +/*! @name ONCE_STAT - OnCE Status Register */ +#define SDMAARM_ONCE_STAT_ECDR_MASK (0x7U) +#define SDMAARM_ONCE_STAT_ECDR_SHIFT (0U) +#define SDMAARM_ONCE_STAT_ECDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ECDR_SHIFT)) & SDMAARM_ONCE_STAT_ECDR_MASK) +#define SDMAARM_ONCE_STAT_MST_MASK (0x80U) +#define SDMAARM_ONCE_STAT_MST_SHIFT (7U) +#define SDMAARM_ONCE_STAT_MST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_MST_SHIFT)) & SDMAARM_ONCE_STAT_MST_MASK) +#define SDMAARM_ONCE_STAT_SWB_MASK (0x100U) +#define SDMAARM_ONCE_STAT_SWB_SHIFT (8U) +#define SDMAARM_ONCE_STAT_SWB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_SWB_SHIFT)) & SDMAARM_ONCE_STAT_SWB_MASK) +#define SDMAARM_ONCE_STAT_ODR_MASK (0x200U) +#define SDMAARM_ONCE_STAT_ODR_SHIFT (9U) +#define SDMAARM_ONCE_STAT_ODR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ODR_SHIFT)) & SDMAARM_ONCE_STAT_ODR_MASK) +#define SDMAARM_ONCE_STAT_EDR_MASK (0x400U) +#define SDMAARM_ONCE_STAT_EDR_SHIFT (10U) +#define SDMAARM_ONCE_STAT_EDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_EDR_SHIFT)) & SDMAARM_ONCE_STAT_EDR_MASK) +#define SDMAARM_ONCE_STAT_RCV_MASK (0x800U) +#define SDMAARM_ONCE_STAT_RCV_SHIFT (11U) +#define SDMAARM_ONCE_STAT_RCV(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_RCV_SHIFT)) & SDMAARM_ONCE_STAT_RCV_MASK) +#define SDMAARM_ONCE_STAT_PST_MASK (0xF000U) +#define SDMAARM_ONCE_STAT_PST_SHIFT (12U) +#define SDMAARM_ONCE_STAT_PST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_PST_SHIFT)) & SDMAARM_ONCE_STAT_PST_MASK) + +/*! @name ONCE_CMD - OnCE Command Register */ +#define SDMAARM_ONCE_CMD_CMD_MASK (0xFU) +#define SDMAARM_ONCE_CMD_CMD_SHIFT (0U) +#define SDMAARM_ONCE_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_CMD_CMD_SHIFT)) & SDMAARM_ONCE_CMD_CMD_MASK) + +/*! @name ILLINSTADDR - Illegal Instruction Trap Address */ +#define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK (0x3FFFU) +#define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT (0U) +#define SDMAARM_ILLINSTADDR_ILLINSTADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT)) & SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK) + +/*! @name CHN0ADDR - Channel 0 Boot Address */ +#define SDMAARM_CHN0ADDR_CHN0ADDR_MASK (0x3FFFU) +#define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT (0U) +#define SDMAARM_CHN0ADDR_CHN0ADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT)) & SDMAARM_CHN0ADDR_CHN0ADDR_MASK) +#define SDMAARM_CHN0ADDR_SMSZ_MASK (0x4000U) +#define SDMAARM_CHN0ADDR_SMSZ_SHIFT (14U) +#define SDMAARM_CHN0ADDR_SMSZ(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_SMSZ_SHIFT)) & SDMAARM_CHN0ADDR_SMSZ_MASK) + +/*! @name EVT_MIRROR - DMA Requests */ +#define SDMAARM_EVT_MIRROR_EVENTS_MASK (0xFFFFFFFFU) +#define SDMAARM_EVT_MIRROR_EVENTS_SHIFT (0U) +#define SDMAARM_EVT_MIRROR_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR_EVENTS_MASK) + +/*! @name EVT_MIRROR2 - DMA Requests 2 */ +#define SDMAARM_EVT_MIRROR2_EVENTS_MASK (0xFFFFU) +#define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT (0U) +#define SDMAARM_EVT_MIRROR2_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR2_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR2_EVENTS_MASK) + +/*! @name XTRIG_CONF1 - Cross-Trigger Events Configuration Register 1 */ +#define SDMAARM_XTRIG_CONF1_NUM0_MASK (0x3FU) +#define SDMAARM_XTRIG_CONF1_NUM0_SHIFT (0U) +#define SDMAARM_XTRIG_CONF1_NUM0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM0_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM0_MASK) +#define SDMAARM_XTRIG_CONF1_CNF0_MASK (0x40U) +#define SDMAARM_XTRIG_CONF1_CNF0_SHIFT (6U) +#define SDMAARM_XTRIG_CONF1_CNF0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF0_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF0_MASK) +#define SDMAARM_XTRIG_CONF1_NUM1_MASK (0x3F00U) +#define SDMAARM_XTRIG_CONF1_NUM1_SHIFT (8U) +#define SDMAARM_XTRIG_CONF1_NUM1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM1_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM1_MASK) +#define SDMAARM_XTRIG_CONF1_CNF1_MASK (0x4000U) +#define SDMAARM_XTRIG_CONF1_CNF1_SHIFT (14U) +#define SDMAARM_XTRIG_CONF1_CNF1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF1_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF1_MASK) +#define SDMAARM_XTRIG_CONF1_NUM2_MASK (0x3F0000U) +#define SDMAARM_XTRIG_CONF1_NUM2_SHIFT (16U) +#define SDMAARM_XTRIG_CONF1_NUM2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM2_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM2_MASK) +#define SDMAARM_XTRIG_CONF1_CNF2_MASK (0x400000U) +#define SDMAARM_XTRIG_CONF1_CNF2_SHIFT (22U) +#define SDMAARM_XTRIG_CONF1_CNF2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF2_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF2_MASK) +#define SDMAARM_XTRIG_CONF1_NUM3_MASK (0x3F000000U) +#define SDMAARM_XTRIG_CONF1_NUM3_SHIFT (24U) +#define SDMAARM_XTRIG_CONF1_NUM3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM3_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM3_MASK) +#define SDMAARM_XTRIG_CONF1_CNF3_MASK (0x40000000U) +#define SDMAARM_XTRIG_CONF1_CNF3_SHIFT (30U) +#define SDMAARM_XTRIG_CONF1_CNF3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF3_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF3_MASK) + +/*! @name XTRIG_CONF2 - Cross-Trigger Events Configuration Register 2 */ +#define SDMAARM_XTRIG_CONF2_NUM4_MASK (0x3FU) +#define SDMAARM_XTRIG_CONF2_NUM4_SHIFT (0U) +#define SDMAARM_XTRIG_CONF2_NUM4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM4_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM4_MASK) +#define SDMAARM_XTRIG_CONF2_CNF4_MASK (0x40U) +#define SDMAARM_XTRIG_CONF2_CNF4_SHIFT (6U) +#define SDMAARM_XTRIG_CONF2_CNF4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF4_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF4_MASK) +#define SDMAARM_XTRIG_CONF2_NUM5_MASK (0x3F00U) +#define SDMAARM_XTRIG_CONF2_NUM5_SHIFT (8U) +#define SDMAARM_XTRIG_CONF2_NUM5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM5_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM5_MASK) +#define SDMAARM_XTRIG_CONF2_CNF5_MASK (0x4000U) +#define SDMAARM_XTRIG_CONF2_CNF5_SHIFT (14U) +#define SDMAARM_XTRIG_CONF2_CNF5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF5_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF5_MASK) +#define SDMAARM_XTRIG_CONF2_NUM6_MASK (0x3F0000U) +#define SDMAARM_XTRIG_CONF2_NUM6_SHIFT (16U) +#define SDMAARM_XTRIG_CONF2_NUM6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM6_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM6_MASK) +#define SDMAARM_XTRIG_CONF2_CNF6_MASK (0x400000U) +#define SDMAARM_XTRIG_CONF2_CNF6_SHIFT (22U) +#define SDMAARM_XTRIG_CONF2_CNF6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF6_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF6_MASK) +#define SDMAARM_XTRIG_CONF2_NUM7_MASK (0x3F000000U) +#define SDMAARM_XTRIG_CONF2_NUM7_SHIFT (24U) +#define SDMAARM_XTRIG_CONF2_NUM7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM7_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM7_MASK) +#define SDMAARM_XTRIG_CONF2_CNF7_MASK (0x40000000U) +#define SDMAARM_XTRIG_CONF2_CNF7_SHIFT (30U) +#define SDMAARM_XTRIG_CONF2_CNF7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF7_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF7_MASK) + +/*! @name SDMA_CHNPRI - Channel Priority Registers */ +#define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK (0x7U) +#define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT (0U) +#define SDMAARM_SDMA_CHNPRI_CHNPRIn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT)) & SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK) + +/* The count of SDMAARM_SDMA_CHNPRI */ +#define SDMAARM_SDMA_CHNPRI_COUNT (32U) + +/*! @name CHNENBL - Channel Enable RAM */ +#define SDMAARM_CHNENBL_ENBLn_MASK (0xFFFFFFFFU) +#define SDMAARM_CHNENBL_ENBLn_SHIFT (0U) +#define SDMAARM_CHNENBL_ENBLn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHNENBL_ENBLn_SHIFT)) & SDMAARM_CHNENBL_ENBLn_MASK) + +/* The count of SDMAARM_CHNENBL */ +#define SDMAARM_CHNENBL_COUNT (48U) + + +/*! + * @} + */ /* end of group SDMAARM_Register_Masks */ + + +/* SDMAARM - Peripheral instance base addresses */ +/** Peripheral SDMAARM base address */ +#define SDMAARM_BASE (0x20EC000u) +/** Peripheral SDMAARM base pointer */ +#define SDMAARM ((SDMAARM_Type *)SDMAARM_BASE) +/** Array initializer of SDMAARM peripheral base addresses */ +#define SDMAARM_BASE_ADDRS { SDMAARM_BASE } +/** Array initializer of SDMAARM peripheral base pointers */ +#define SDMAARM_BASE_PTRS { SDMAARM } +/** Interrupt vectors for the SDMAARM peripheral type */ +#define SDMAARM_IRQS { SDMA_IRQn } + +/*! + * @} + */ /* end of group SDMAARM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer + * @{ + */ + +/** SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t HPLR; /**< SNVS_HP Lock register, offset: 0x0 */ + __IO uint32_t HPCOMR; /**< SNVS_HP Command register, offset: 0x4 */ + __IO uint32_t HPCR; /**< SNVS_HP Control register, offset: 0x8 */ + uint8_t RESERVED_0[8]; + __IO uint32_t HPSR; /**< SNVS_HP Status register, offset: 0x14 */ + uint8_t RESERVED_1[12]; + __IO uint32_t HPRTCMR; /**< SNVS_HP Real-Time Counter MSB Register, offset: 0x24 */ + __IO uint32_t HPRTCLR; /**< SNVS_HP Real-Time Counter LSB Register, offset: 0x28 */ + __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ + __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ + __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ + __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ + uint8_t RESERVED_2[16]; + __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ + uint8_t RESERVED_3[12]; + __IO uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ + __IO uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ + uint8_t RESERVED_4[4]; + __IO uint32_t LPGPR; /**< SNVS_LP General-Purpose Register, offset: 0x68 */ + uint8_t RESERVED_5[2956]; + __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ + __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ +} SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/*! @name HPLR - SNVS_HP Lock register */ +#define SNVS_HPLR_MC_SL_MASK (0x10U) +#define SNVS_HPLR_MC_SL_SHIFT (4U) +#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) +#define SNVS_HPLR_GPR_SL_MASK (0x20U) +#define SNVS_HPLR_GPR_SL_SHIFT (5U) +#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) + +/*! @name HPCOMR - SNVS_HP Command register */ +#define SNVS_HPCOMR_LP_SWR_MASK (0x10U) +#define SNVS_HPCOMR_LP_SWR_SHIFT (4U) +#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) +#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) +#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) +#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) +#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) +#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) + +/*! @name HPCR - SNVS_HP Control register */ +#define SNVS_HPCR_RTC_EN_MASK (0x1U) +#define SNVS_HPCR_RTC_EN_SHIFT (0U) +#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) +#define SNVS_HPCR_HPTA_EN_MASK (0x2U) +#define SNVS_HPCR_HPTA_EN_SHIFT (1U) +#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) +#define SNVS_HPCR_PI_EN_MASK (0x8U) +#define SNVS_HPCR_PI_EN_SHIFT (3U) +#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) +#define SNVS_HPCR_PI_FREQ_MASK (0xF0U) +#define SNVS_HPCR_PI_FREQ_SHIFT (4U) +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) +#define SNVS_HPCR_HPCALB_EN_MASK (0x100U) +#define SNVS_HPCR_HPCALB_EN_SHIFT (8U) +#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) +#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) +#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) +#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) +#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) +#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) +#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) +#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) +#define SNVS_HPCR_BTN_MASK_SHIFT (27U) +#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) + +/*! @name HPSR - SNVS_HP Status register */ +#define SNVS_HPSR_BTN_MASK (0x40U) +#define SNVS_HPSR_BTN_SHIFT (6U) +#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) +#define SNVS_HPSR_BI_MASK (0x80U) +#define SNVS_HPSR_BI_SHIFT (7U) +#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) + +/*! @name HPRTCMR - SNVS_HP Real-Time Counter MSB Register */ +#define SNVS_HPRTCMR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCMR_RTC_SHIFT (0U) +#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) + +/*! @name HPRTCLR - SNVS_HP Real-Time Counter LSB Register */ +#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCLR_RTC_SHIFT (0U) +#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) + +/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ +#define SNVS_HPTAMR_HPTA_MASK (0x7FFFU) +#define SNVS_HPTAMR_HPTA_SHIFT (0U) +#define SNVS_HPTAMR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_SHIFT)) & SNVS_HPTAMR_HPTA_MASK) + +/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ +#define SNVS_HPTALR_HPTA_MASK (0xFFFFFFFFU) +#define SNVS_HPTALR_HPTA_SHIFT (0U) +#define SNVS_HPTALR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_SHIFT)) & SNVS_HPTALR_HPTA_MASK) + +/*! @name LPLR - SNVS_LP Lock Register */ +#define SNVS_LPLR_MC_HL_MASK (0x10U) +#define SNVS_LPLR_MC_HL_SHIFT (4U) +#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) +#define SNVS_LPLR_GPR_HL_MASK (0x20U) +#define SNVS_LPLR_GPR_HL_SHIFT (5U) +#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) + +/*! @name LPCR - SNVS_LP Control Register */ +#define SNVS_LPCR_MC_ENV_MASK (0x4U) +#define SNVS_LPCR_MC_ENV_SHIFT (2U) +#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) +#define SNVS_LPCR_DP_EN_MASK (0x20U) +#define SNVS_LPCR_DP_EN_SHIFT (5U) +#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) +#define SNVS_LPCR_TOP_MASK (0x40U) +#define SNVS_LPCR_TOP_SHIFT (6U) +#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) +#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) +#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) +#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) +#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) +#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) +#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) +#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) +#define SNVS_LPCR_DEBOUNCE_SHIFT (18U) +#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) +#define SNVS_LPCR_ON_TIME_MASK (0x300000U) +#define SNVS_LPCR_ON_TIME_SHIFT (20U) +#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) +#define SNVS_LPCR_PK_EN_MASK (0x400000U) +#define SNVS_LPCR_PK_EN_SHIFT (22U) +#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) +#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) +#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) +#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) + +/*! @name LPSR - SNVS_LP Status Register */ +#define SNVS_LPSR_MCR_MASK (0x4U) +#define SNVS_LPSR_MCR_SHIFT (2U) +#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) +#define SNVS_LPSR_EO_MASK (0x20000U) +#define SNVS_LPSR_EO_SHIFT (17U) +#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) +#define SNVS_LPSR_SPO_MASK (0x40000U) +#define SNVS_LPSR_SPO_SHIFT (18U) +#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) + +/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ +#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) +#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) +#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) +#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) +#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) + +/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ +#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) + +/*! @name LPGPR - SNVS_LP General-Purpose Register */ +#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_GPR_SHIFT (0U) +#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) + +/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ +#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) +#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) +#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) +#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) +#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) +#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) +#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) +#define SNVS_HPVIDR1_IP_ID_SHIFT (16U) +#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) + +/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ +#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) +#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) +#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) +#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) +#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) +#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) +#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) +#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) +#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) +#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) +#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) +#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) + + +/*! + * @} + */ /* end of group SNVS_Register_Masks */ + + +/* SNVS - Peripheral instance base addresses */ +/** Peripheral SNVS base address */ +#define SNVS_BASE (0x20CC000u) +/** Peripheral SNVS base pointer */ +#define SNVS ((SNVS_Type *)SNVS_BASE) +/** Array initializer of SNVS peripheral base addresses */ +#define SNVS_BASE_ADDRS { SNVS_BASE } +/** Array initializer of SNVS peripheral base pointers */ +#define SNVS_BASE_PTRS { SNVS } +/** Interrupt vectors for the SNVS peripheral type */ +#define SNVS_IRQS { SNVS_IRQn } +#define SNVS_CONSOLIDATED_IRQS { SNVS_Consolidated_IRQn } +#define SNVS_SECURITY_IRQS { SNVS_Security_IRQn } + +/*! + * @} + */ /* end of group SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPBA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer + * @{ + */ + +/** SPBA - Register Layout Typedef */ +typedef struct { + __IO uint32_t PRR[32]; /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */ +} SPBA_Type; + +/* ---------------------------------------------------------------------------- + -- SPBA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Register_Masks SPBA Register Masks + * @{ + */ + +/*! @name PRR - Peripheral Rights Register */ +#define SPBA_PRR_RARA_MASK (0x1U) +#define SPBA_PRR_RARA_SHIFT (0U) +#define SPBA_PRR_RARA(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARA_SHIFT)) & SPBA_PRR_RARA_MASK) +#define SPBA_PRR_RARB_MASK (0x2U) +#define SPBA_PRR_RARB_SHIFT (1U) +#define SPBA_PRR_RARB(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARB_SHIFT)) & SPBA_PRR_RARB_MASK) +#define SPBA_PRR_RARC_MASK (0x4U) +#define SPBA_PRR_RARC_SHIFT (2U) +#define SPBA_PRR_RARC(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARC_SHIFT)) & SPBA_PRR_RARC_MASK) +#define SPBA_PRR_ROI_MASK (0x30000U) +#define SPBA_PRR_ROI_SHIFT (16U) +#define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_ROI_SHIFT)) & SPBA_PRR_ROI_MASK) +#define SPBA_PRR_RMO_MASK (0xC0000000U) +#define SPBA_PRR_RMO_SHIFT (30U) +#define SPBA_PRR_RMO(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RMO_SHIFT)) & SPBA_PRR_RMO_MASK) + +/* The count of SPBA_PRR */ +#define SPBA_PRR_COUNT (32U) + + +/*! + * @} + */ /* end of group SPBA_Register_Masks */ + + +/* SPBA - Peripheral instance base addresses */ +/** Peripheral SPBA base address */ +#define SPBA_BASE (0x203C000u) +/** Peripheral SPBA base pointer */ +#define SPBA ((SPBA_Type *)SPBA_BASE) +/** Array initializer of SPBA peripheral base addresses */ +#define SPBA_BASE_ADDRS { SPBA_BASE } +/** Array initializer of SPBA peripheral base pointers */ +#define SPBA_BASE_PTRS { SPBA } + +/*! + * @} + */ /* end of group SPBA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer + * @{ + */ + +/** SPDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ + __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ + __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ + __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ + union { /* offset: 0x10 */ + __IO uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */ + __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ + }; + __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */ + __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */ + __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */ + __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */ + __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */ + __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */ + __IO uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */ + __IO uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */ + __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */ + __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */ + uint8_t RESERVED_0[8]; + __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ + uint8_t RESERVED_1[8]; + __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ +} SPDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SPDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Register_Masks SPDIF Register Masks + * @{ + */ + +/*! @name SCR - SPDIF Configuration Register */ +#define SPDIF_SCR_USRC_SEL_MASK (0x3U) +#define SPDIF_SCR_USRC_SEL_SHIFT (0U) +#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) +#define SPDIF_SCR_TXSEL_MASK (0x1CU) +#define SPDIF_SCR_TXSEL_SHIFT (2U) +#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) +#define SPDIF_SCR_VALCTRL_MASK (0x20U) +#define SPDIF_SCR_VALCTRL_SHIFT (5U) +#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) +#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) +#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) +#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) +#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) +#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) +#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) +#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) +#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) +#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) +#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) +#define SPDIF_SCR_SOFT_RESET_SHIFT (12U) +#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) +#define SPDIF_SCR_LOW_POWER_MASK (0x2000U) +#define SPDIF_SCR_LOW_POWER_SHIFT (13U) +#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) +#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) +#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) +#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) +#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) +#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) +#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) +#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) +#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) +#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) +#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) +#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) +#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) +#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) +#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) +#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) +#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) +#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) +#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) + +/*! @name SRCD - CDText Control Register */ +#define SPDIF_SRCD_USYNCMODE_MASK (0x2U) +#define SPDIF_SRCD_USYNCMODE_SHIFT (1U) +#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) + +/*! @name SRPC - PhaseConfig Register */ +#define SPDIF_SRPC_GAINSEL_MASK (0x38U) +#define SPDIF_SRPC_GAINSEL_SHIFT (3U) +#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) +#define SPDIF_SRPC_LOCK_MASK (0x40U) +#define SPDIF_SRPC_LOCK_SHIFT (6U) +#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) +#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) +#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) +#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) + +/*! @name SIE - InterruptEn Register */ +#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) +#define SPDIF_SIE_TXEM_MASK (0x2U) +#define SPDIF_SIE_TXEM_SHIFT (1U) +#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) +#define SPDIF_SIE_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIE_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) +#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) +#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) +#define SPDIF_SIE_UQERR_MASK (0x20U) +#define SPDIF_SIE_UQERR_SHIFT (5U) +#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) +#define SPDIF_SIE_UQSYNC_MASK (0x40U) +#define SPDIF_SIE_UQSYNC_SHIFT (6U) +#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) +#define SPDIF_SIE_QRXOV_MASK (0x80U) +#define SPDIF_SIE_QRXOV_SHIFT (7U) +#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) +#define SPDIF_SIE_QRXFUL_MASK (0x100U) +#define SPDIF_SIE_QRXFUL_SHIFT (8U) +#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) +#define SPDIF_SIE_URXOV_MASK (0x200U) +#define SPDIF_SIE_URXOV_SHIFT (9U) +#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) +#define SPDIF_SIE_URXFUL_MASK (0x400U) +#define SPDIF_SIE_URXFUL_SHIFT (10U) +#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) +#define SPDIF_SIE_BITERR_MASK (0x4000U) +#define SPDIF_SIE_BITERR_SHIFT (14U) +#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) +#define SPDIF_SIE_SYMERR_MASK (0x8000U) +#define SPDIF_SIE_SYMERR_SHIFT (15U) +#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) +#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIE_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) +#define SPDIF_SIE_CNEW_MASK (0x20000U) +#define SPDIF_SIE_CNEW_SHIFT (17U) +#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) +#define SPDIF_SIE_TXRESYN_MASK (0x40000U) +#define SPDIF_SIE_TXRESYN_SHIFT (18U) +#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) +#define SPDIF_SIE_TXUNOV_MASK (0x80000U) +#define SPDIF_SIE_TXUNOV_SHIFT (19U) +#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) +#define SPDIF_SIE_LOCK_MASK (0x100000U) +#define SPDIF_SIE_LOCK_SHIFT (20U) +#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) + +/*! @name SIC - InterruptClear Register */ +#define SPDIF_SIC_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIC_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) +#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) +#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) +#define SPDIF_SIC_UQERR_MASK (0x20U) +#define SPDIF_SIC_UQERR_SHIFT (5U) +#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) +#define SPDIF_SIC_UQSYNC_MASK (0x40U) +#define SPDIF_SIC_UQSYNC_SHIFT (6U) +#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) +#define SPDIF_SIC_QRXOV_MASK (0x80U) +#define SPDIF_SIC_QRXOV_SHIFT (7U) +#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) +#define SPDIF_SIC_URXOV_MASK (0x200U) +#define SPDIF_SIC_URXOV_SHIFT (9U) +#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) +#define SPDIF_SIC_BITERR_MASK (0x4000U) +#define SPDIF_SIC_BITERR_SHIFT (14U) +#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) +#define SPDIF_SIC_SYMERR_MASK (0x8000U) +#define SPDIF_SIC_SYMERR_SHIFT (15U) +#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) +#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIC_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) +#define SPDIF_SIC_CNEW_MASK (0x20000U) +#define SPDIF_SIC_CNEW_SHIFT (17U) +#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) +#define SPDIF_SIC_TXRESYN_MASK (0x40000U) +#define SPDIF_SIC_TXRESYN_SHIFT (18U) +#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) +#define SPDIF_SIC_TXUNOV_MASK (0x80000U) +#define SPDIF_SIC_TXUNOV_SHIFT (19U) +#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) +#define SPDIF_SIC_LOCK_MASK (0x100000U) +#define SPDIF_SIC_LOCK_SHIFT (20U) +#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) + +/*! @name SIS - InterruptStat Register */ +#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) +#define SPDIF_SIS_TXEM_MASK (0x2U) +#define SPDIF_SIS_TXEM_SHIFT (1U) +#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) +#define SPDIF_SIS_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIS_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) +#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) +#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) +#define SPDIF_SIS_UQERR_MASK (0x20U) +#define SPDIF_SIS_UQERR_SHIFT (5U) +#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) +#define SPDIF_SIS_UQSYNC_MASK (0x40U) +#define SPDIF_SIS_UQSYNC_SHIFT (6U) +#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) +#define SPDIF_SIS_QRXOV_MASK (0x80U) +#define SPDIF_SIS_QRXOV_SHIFT (7U) +#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) +#define SPDIF_SIS_QRXFUL_MASK (0x100U) +#define SPDIF_SIS_QRXFUL_SHIFT (8U) +#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) +#define SPDIF_SIS_URXOV_MASK (0x200U) +#define SPDIF_SIS_URXOV_SHIFT (9U) +#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) +#define SPDIF_SIS_URXFUL_MASK (0x400U) +#define SPDIF_SIS_URXFUL_SHIFT (10U) +#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) +#define SPDIF_SIS_BITERR_MASK (0x4000U) +#define SPDIF_SIS_BITERR_SHIFT (14U) +#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) +#define SPDIF_SIS_SYMERR_MASK (0x8000U) +#define SPDIF_SIS_SYMERR_SHIFT (15U) +#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) +#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIS_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) +#define SPDIF_SIS_CNEW_MASK (0x20000U) +#define SPDIF_SIS_CNEW_SHIFT (17U) +#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) +#define SPDIF_SIS_TXRESYN_MASK (0x40000U) +#define SPDIF_SIS_TXRESYN_SHIFT (18U) +#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) +#define SPDIF_SIS_TXUNOV_MASK (0x80000U) +#define SPDIF_SIS_TXUNOV_SHIFT (19U) +#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) +#define SPDIF_SIS_LOCK_MASK (0x100000U) +#define SPDIF_SIS_LOCK_SHIFT (20U) +#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) + +/*! @name SRL - SPDIFRxLeft Register */ +#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_SRL_RXDATALEFT_SHIFT (0U) +#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) + +/*! @name SRR - SPDIFRxRight Register */ +#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) +#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) + +/*! @name SRCSH - SPDIFRxCChannel_h Register */ +#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) +#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) +#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) + +/*! @name SRCSL - SPDIFRxCChannel_l Register */ +#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) +#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) +#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) + +/*! @name SRU - UchannelRx Register */ +#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) +#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) + +/*! @name SRQ - QchannelRx Register */ +#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) +#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) + +/*! @name STL - SPDIFTxLeft Register */ +#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_STL_TXDATALEFT_SHIFT (0U) +#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) + +/*! @name STR - SPDIFTxRight Register */ +#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_STR_TXDATARIGHT_SHIFT (0U) +#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) + +/*! @name STCSCH - SPDIFTxCChannelCons_h Register */ +#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) +#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) +#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) + +/*! @name STCSCL - SPDIFTxCChannelCons_l Register */ +#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) +#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) +#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) + +/*! @name SRFM - FreqMeas Register */ +#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) +#define SPDIF_SRFM_FREQMEAS_SHIFT (0U) +#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) + +/*! @name STC - SPDIFTxClk Register */ +#define SPDIF_STC_TXCLK_DF_MASK (0x7FU) +#define SPDIF_STC_TXCLK_DF_SHIFT (0U) +#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) +#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) +#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) +#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) +#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) +#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) +#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) +#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) +#define SPDIF_STC_SYSCLK_DF_SHIFT (11U) +#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) + + +/*! + * @} + */ /* end of group SPDIF_Register_Masks */ + + +/* SPDIF - Peripheral instance base addresses */ +/** Peripheral SPDIF base address */ +#define SPDIF_BASE (0x2004000u) +/** Peripheral SPDIF base pointer */ +#define SPDIF ((SPDIF_Type *)SPDIF_BASE) +/** Array initializer of SPDIF peripheral base addresses */ +#define SPDIF_BASE_ADDRS { SPDIF_BASE } +/** Array initializer of SPDIF peripheral base pointers */ +#define SPDIF_BASE_PTRS { SPDIF } +/** Interrupt vectors for the SPDIF peripheral type */ +#define SPDIF_IRQS { SPDIF_IRQn } + +/*! + * @} + */ /* end of group SPDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer + * @{ + */ + +/** SRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ + __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x4 */ + __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x8 */ + uint8_t RESERVED_0[8]; + __I uint32_t SISR; /**< SRC Interrupt Status Register, offset: 0x14 */ + uint8_t RESERVED_1[4]; + __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x1C */ + __IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4 */ +} SRC_Type; + +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/*! @name SCR - SRC Control Register */ +#define SRC_SCR_WARM_RESET_ENABLE_MASK (0x1U) +#define SRC_SCR_WARM_RESET_ENABLE_SHIFT (0U) +#define SRC_SCR_WARM_RESET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_WARM_RESET_ENABLE_SHIFT)) & SRC_SCR_WARM_RESET_ENABLE_MASK) +#define SRC_SCR_WARM_RST_BYPASS_COUNT_MASK (0x60U) +#define SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT (5U) +#define SRC_SCR_WARM_RST_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT)) & SRC_SCR_WARM_RST_BYPASS_COUNT_MASK) +#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U) +#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U) +#define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK) +#define SRC_SCR_EIM_RST_MASK (0x800U) +#define SRC_SCR_EIM_RST_SHIFT (11U) +#define SRC_SCR_EIM_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_EIM_RST_SHIFT)) & SRC_SCR_EIM_RST_MASK) +#define SRC_SCR_CORE0_RST_MASK (0x2000U) +#define SRC_SCR_CORE0_RST_SHIFT (13U) +#define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK) +#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U) +#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U) +#define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK) +#define SRC_SCR_CORES_DBG_RST_MASK (0x200000U) +#define SRC_SCR_CORES_DBG_RST_SHIFT (21U) +#define SRC_SCR_CORES_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORES_DBG_RST_SHIFT)) & SRC_SCR_CORES_DBG_RST_MASK) +#define SRC_SCR_WDOG3_RST_OPTN_MASK (0x1000000U) +#define SRC_SCR_WDOG3_RST_OPTN_SHIFT (24U) +#define SRC_SCR_WDOG3_RST_OPTN(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_WDOG3_RST_OPTN_SHIFT)) & SRC_SCR_WDOG3_RST_OPTN_MASK) +#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U) +#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U) +#define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK) +#define SRC_SCR_MIX_RST_STRCH_MASK (0xC000000U) +#define SRC_SCR_MIX_RST_STRCH_SHIFT (26U) +#define SRC_SCR_MIX_RST_STRCH(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MIX_RST_STRCH_SHIFT)) & SRC_SCR_MIX_RST_STRCH_MASK) +#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U) +#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U) +#define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK) + +/*! @name SBMR1 - SRC Boot Mode Register 1 */ +#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) +#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) +#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) +#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U) +#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U) +#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK) +#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U) +#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U) +#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK) +#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) +#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) +#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) + +/*! @name SRSR - SRC Reset Status Register */ +#define SRC_SRSR_IPP_RESET_B_MASK (0x1U) +#define SRC_SRSR_IPP_RESET_B_SHIFT (0U) +#define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK) +#define SRC_SRSR_CSU_RESET_B_MASK (0x4U) +#define SRC_SRSR_CSU_RESET_B_SHIFT (2U) +#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) +#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) +#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) +#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) +#define SRC_SRSR_WDOG_RST_B_MASK (0x10U) +#define SRC_SRSR_WDOG_RST_B_SHIFT (4U) +#define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK) +#define SRC_SRSR_JTAG_RST_B_MASK (0x20U) +#define SRC_SRSR_JTAG_RST_B_SHIFT (5U) +#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) +#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) +#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) +#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) +#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) +#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) +#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) +#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U) +#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U) +#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) +#define SRC_SRSR_WARM_BOOT_MASK (0x10000U) +#define SRC_SRSR_WARM_BOOT_SHIFT (16U) +#define SRC_SRSR_WARM_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WARM_BOOT_SHIFT)) & SRC_SRSR_WARM_BOOT_MASK) + +/*! @name SISR - SRC Interrupt Status Register */ +#define SRC_SISR_CORE0_WDOG_RST_REQ_MASK (0x20U) +#define SRC_SISR_CORE0_WDOG_RST_REQ_SHIFT (5U) +#define SRC_SISR_CORE0_WDOG_RST_REQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_CORE0_WDOG_RST_REQ_SHIFT)) & SRC_SISR_CORE0_WDOG_RST_REQ_MASK) + +/*! @name SBMR2 - SRC Boot Mode Register 2 */ +#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) +#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) +#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) +#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) +#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) +#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) +#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) +#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) +#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) +#define SRC_SBMR2_BMOD_MASK (0x3000000U) +#define SRC_SBMR2_BMOD_SHIFT (24U) +#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) + +/*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ +#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) + +/* The count of SRC_GPR */ +#define SRC_GPR_COUNT (10U) + + +/*! + * @} + */ /* end of group SRC_Register_Masks */ + + +/* SRC - Peripheral instance base addresses */ +/** Peripheral SRC base address */ +#define SRC_BASE (0x20D8000u) +/** Peripheral SRC base pointer */ +#define SRC ((SRC_Type *)SRC_BASE) +/** Array initializer of SRC peripheral base addresses */ +#define SRC_BASE_ADDRS { SRC_BASE } +/** Array initializer of SRC peripheral base pointers */ +#define SRC_BASE_PTRS { SRC } +/** Interrupt vectors for the SRC peripheral type */ +#define SRC_IRQS { SRC_IRQn } +#define SRC_COMBINED_IRQS { SRC_Combined_IRQn } +/* Backward compatibility */ +#define SRC_SCR_WRE_MASK SRC_SCR_WARM_RESET_ENABLE_MASK +#define SRC_SCR_WRE_SHIFT SRC_SCR_WARM_RESET_ENABLE_SHIFT +#define SRC_SCR_WRE(x) SRC_SCR_WARM_RESET_ENABLE(x) +#define SRC_SCR_WRBC_MASK SRC_SCR_WARM_RST_BYPASS_COUNT_MASK +#define SRC_SCR_WRBC_SHIFT SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT +#define SRC_SCR_WRBC(x) SRC_SCR_WARM_RST_BYPASS_COUNT(x) +#define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK +#define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT +#define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x) +#define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK +#define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT +#define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x) +#define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK +#define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT +#define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x) +#define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK +#define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT +#define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x) +#define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK +#define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT +#define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x) +#define SRC_SRSR_WBI_MASK SRC_SRSR_WARM_BOOT_MASK +#define SRC_SRSR_WBI_SHIFT SRC_SRSR_WARM_BOOT_SHIFT +#define SRC_SRSR_WBI(x) SRC_SRSR_WARM_BOOT(x) +/* Extra definition */ +#define SRC_SRSR_W1C_BITS_MASK (SRC_SRSR_WDOG3_RST_B_MASK \ + | SRC_SRSR_JTAG_SW_RST_MASK \ + | SRC_SRSR_JTAG_RST_B_MASK \ + | SRC_SRSR_WDOG_RST_B_MASK \ + | SRC_SRSR_IPP_USER_RESET_B_MASK \ + | SRC_SRSR_CSU_RESET_B_MASK \ + | SRC_SRSR_IPP_RESET_B_MASK) + + +/*! + * @} + */ /* end of group SRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TEMPMON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer + * @{ + */ + +/** TEMPMON - Register Layout Typedef */ +typedef struct { + __IO uint32_t TEMPSENSE0; /**< Tempsensor Control Register 0, offset: 0x0 */ + __IO uint32_t TEMPSENSE0_SET; /**< Tempsensor Control Register 0, offset: 0x4 */ + __IO uint32_t TEMPSENSE0_CLR; /**< Tempsensor Control Register 0, offset: 0x8 */ + __IO uint32_t TEMPSENSE0_TOG; /**< Tempsensor Control Register 0, offset: 0xC */ + __IO uint32_t TEMPSENSE1; /**< Tempsensor Control Register 1, offset: 0x10 */ + __IO uint32_t TEMPSENSE1_SET; /**< Tempsensor Control Register 1, offset: 0x14 */ + __IO uint32_t TEMPSENSE1_CLR; /**< Tempsensor Control Register 1, offset: 0x18 */ + __IO uint32_t TEMPSENSE1_TOG; /**< Tempsensor Control Register 1, offset: 0x1C */ + uint8_t RESERVED_0[240]; + __IO uint32_t TEMPSENSE2; /**< Tempsensor Control Register 2, offset: 0x110 */ + __IO uint32_t TEMPSENSE2_SET; /**< Tempsensor Control Register 2, offset: 0x114 */ + __IO uint32_t TEMPSENSE2_CLR; /**< Tempsensor Control Register 2, offset: 0x118 */ + __IO uint32_t TEMPSENSE2_TOG; /**< Tempsensor Control Register 2, offset: 0x11C */ +} TEMPMON_Type; + +/* ---------------------------------------------------------------------------- + -- TEMPMON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks + * @{ + */ + +/*! @name TEMPSENSE0 - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE1 - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE2 - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) + + +/*! + * @} + */ /* end of group TEMPMON_Register_Masks */ + + +/* TEMPMON - Peripheral instance base addresses */ +/** Peripheral TEMPMON base address */ +#define TEMPMON_BASE (0x20C8180u) +/** Peripheral TEMPMON base pointer */ +#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE) +/** Array initializer of TEMPMON peripheral base addresses */ +#define TEMPMON_BASE_ADDRS { TEMPMON_BASE } +/** Array initializer of TEMPMON peripheral base pointers */ +#define TEMPMON_BASE_PTRS { TEMPMON } +/** Interrupt vectors for the TEMPMON peripheral type */ +#define TEMPMON_IRQS { TEMPMON_IRQn } + +/*! + * @} + */ /* end of group TEMPMON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Peripheral_Access_Layer TSC Peripheral Access Layer + * @{ + */ + +/** TSC - Register Layout Typedef */ +typedef struct { + __IO uint32_t BASIC_SETTING; /**< PS Input Buffer Address, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PS_INPUT_BUFFER_ADDR; /**< PS Input Buffer Address, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FLOW_CONTROL; /**< Flow Control, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __I uint32_t MEASEURE_VALUE; /**< Measure Value, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t INT_SIG_EN; /**< Interrupt Signal Enable, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DEBUG_MODE; /**< , offset: 0x70 */ + uint8_t RESERVED_7[12]; + __IO uint32_t DEBUG_MODE2; /**< , offset: 0x80 */ +} TSC_Type; + +/* ---------------------------------------------------------------------------- + -- TSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Register_Masks TSC Register Masks + * @{ + */ + +/*! @name BASIC_SETTING - PS Input Buffer Address */ +#define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U) +#define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U) +#define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK) +#define TSC_BASIC_SETTING__4_5_WIRE_MASK (0x10U) +#define TSC_BASIC_SETTING__4_5_WIRE_SHIFT (4U) +#define TSC_BASIC_SETTING__4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING__4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING__4_5_WIRE_MASK) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK) + +/*! @name PS_INPUT_BUFFER_ADDR - PS Input Buffer Address */ +#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) +#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT (0U) +#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT)) & TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK) + +/*! @name FLOW_CONTROL - Flow Control */ +#define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U) +#define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U) +#define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK) +#define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U) +#define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U) +#define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK) +#define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U) +#define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U) +#define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK) +#define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U) +#define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U) +#define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK) +#define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U) +#define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U) +#define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK) + +/*! @name MEASEURE_VALUE - Measure Value */ +#define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU) +#define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U) +#define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) +#define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U) +#define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U) +#define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK) + +/*! @name INT_EN - Interrupt Enable */ +#define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U) +#define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U) +#define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK) +#define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U) +#define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U) +#define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK) +#define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U) +#define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U) +#define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK) + +/*! @name INT_SIG_EN - Interrupt Signal Enable */ +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U) +#define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK) +#define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U) +#define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U) +#define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK) + +/*! @name INT_STATUS - Intterrupt Status */ +#define TSC_INT_STATUS_MEASURE_MASK (0x1U) +#define TSC_INT_STATUS_MEASURE_SHIFT (0U) +#define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK) +#define TSC_INT_STATUS_DETECT_MASK (0x10U) +#define TSC_INT_STATUS_DETECT_SHIFT (4U) +#define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK) +#define TSC_INT_STATUS_VALID_MASK (0x100U) +#define TSC_INT_STATUS_VALID_SHIFT (8U) +#define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK) +#define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U) +#define TSC_INT_STATUS_IDLE_SW_SHIFT (12U) +#define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK) + +/*! @name DEBUG_MODE - */ +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U) +#define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U) +#define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK) +#define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U) +#define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U) +#define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK) +#define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U) +#define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U) +#define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK) +#define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U) +#define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U) +#define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK) + +/*! @name DEBUG_MODE2 - */ +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U) +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U) +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U) +#define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U) +#define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK) +#define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U) +#define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U) +#define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U) +#define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U) +#define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK) + + +/*! + * @} + */ /* end of group TSC_Register_Masks */ + + +/* TSC - Peripheral instance base addresses */ +/** Peripheral TSC base address */ +#define TSC_BASE (0x2040000u) +/** Peripheral TSC base pointer */ +#define TSC ((TSC_Type *)TSC_BASE) +/** Array initializer of TSC peripheral base addresses */ +#define TSC_BASE_ADDRS { TSC_BASE } +/** Array initializer of TSC peripheral base pointers */ +#define TSC_BASE_PTRS { TSC } +/** Interrupt vectors for the TSC peripheral type */ +#define TSC_IRQS { TSC_IRQn } + +/*! + * @} + */ /* end of group TSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer + * @{ + */ + +/** UART - Register Layout Typedef */ +typedef struct { + __I uint32_t URXD; /**< UART Receiver Register, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t UTXD; /**< UART Transmitter Register, offset: 0x40 */ + uint8_t RESERVED_1[60]; + __IO uint32_t UCR1; /**< UART Control Register 1, offset: 0x80 */ + __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ + __IO uint32_t UCR3; /**< UART Control Register 3, offset: 0x88 */ + __IO uint32_t UCR4; /**< UART Control Register 4, offset: 0x8C */ + __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ + __IO uint32_t USR1; /**< UART Status Register 1, offset: 0x94 */ + __IO uint32_t USR2; /**< UART Status Register 2, offset: 0x98 */ + __IO uint32_t UESC; /**< UART Escape Character Register, offset: 0x9C */ + __IO uint32_t UTIM; /**< UART Escape Timer Register, offset: 0xA0 */ + __IO uint32_t UBIR; /**< UART BRM Incremental Register, offset: 0xA4 */ + __IO uint32_t UBMR; /**< UART BRM Modulator Register, offset: 0xA8 */ + __I uint32_t UBRC; /**< UART Baud Rate Count Register, offset: 0xAC */ + __IO uint32_t ONEMS; /**< UART One Millisecond Register, offset: 0xB0 */ + __IO uint32_t UTS; /**< UART Test Register, offset: 0xB4 */ + __IO uint32_t UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 */ +} UART_Type; + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/*! @name URXD - UART Receiver Register */ +#define UART_URXD_RX_DATA_MASK (0xFFU) +#define UART_URXD_RX_DATA_SHIFT (0U) +#define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_RX_DATA_SHIFT)) & UART_URXD_RX_DATA_MASK) +#define UART_URXD_PRERR_MASK (0x400U) +#define UART_URXD_PRERR_SHIFT (10U) +#define UART_URXD_PRERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_PRERR_SHIFT)) & UART_URXD_PRERR_MASK) +#define UART_URXD_BRK_MASK (0x800U) +#define UART_URXD_BRK_SHIFT (11U) +#define UART_URXD_BRK(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_BRK_SHIFT)) & UART_URXD_BRK_MASK) +#define UART_URXD_FRMERR_MASK (0x1000U) +#define UART_URXD_FRMERR_SHIFT (12U) +#define UART_URXD_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_FRMERR_SHIFT)) & UART_URXD_FRMERR_MASK) +#define UART_URXD_OVRRUN_MASK (0x2000U) +#define UART_URXD_OVRRUN_SHIFT (13U) +#define UART_URXD_OVRRUN(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_OVRRUN_SHIFT)) & UART_URXD_OVRRUN_MASK) +#define UART_URXD_ERR_MASK (0x4000U) +#define UART_URXD_ERR_SHIFT (14U) +#define UART_URXD_ERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_ERR_SHIFT)) & UART_URXD_ERR_MASK) +#define UART_URXD_CHARRDY_MASK (0x8000U) +#define UART_URXD_CHARRDY_SHIFT (15U) +#define UART_URXD_CHARRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_CHARRDY_SHIFT)) & UART_URXD_CHARRDY_MASK) + +/*! @name UTXD - UART Transmitter Register */ +#define UART_UTXD_TX_DATA_MASK (0xFFU) +#define UART_UTXD_TX_DATA_SHIFT (0U) +#define UART_UTXD_TX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_UTXD_TX_DATA_SHIFT)) & UART_UTXD_TX_DATA_MASK) + +/*! @name UCR1 - UART Control Register 1 */ +#define UART_UCR1_UARTEN_MASK (0x1U) +#define UART_UCR1_UARTEN_SHIFT (0U) +#define UART_UCR1_UARTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_UARTEN_SHIFT)) & UART_UCR1_UARTEN_MASK) +#define UART_UCR1_DOZE_MASK (0x2U) +#define UART_UCR1_DOZE_SHIFT (1U) +#define UART_UCR1_DOZE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_DOZE_SHIFT)) & UART_UCR1_DOZE_MASK) +#define UART_UCR1_ATDMAEN_MASK (0x4U) +#define UART_UCR1_ATDMAEN_SHIFT (2U) +#define UART_UCR1_ATDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ATDMAEN_SHIFT)) & UART_UCR1_ATDMAEN_MASK) +#define UART_UCR1_TXDMAEN_MASK (0x8U) +#define UART_UCR1_TXDMAEN_SHIFT (3U) +#define UART_UCR1_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXDMAEN_SHIFT)) & UART_UCR1_TXDMAEN_MASK) +#define UART_UCR1_SNDBRK_MASK (0x10U) +#define UART_UCR1_SNDBRK_SHIFT (4U) +#define UART_UCR1_SNDBRK(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_SNDBRK_SHIFT)) & UART_UCR1_SNDBRK_MASK) +#define UART_UCR1_RTSDEN_MASK (0x20U) +#define UART_UCR1_RTSDEN_SHIFT (5U) +#define UART_UCR1_RTSDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RTSDEN_SHIFT)) & UART_UCR1_RTSDEN_MASK) +#define UART_UCR1_TXMPTYEN_MASK (0x40U) +#define UART_UCR1_TXMPTYEN_SHIFT (6U) +#define UART_UCR1_TXMPTYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXMPTYEN_SHIFT)) & UART_UCR1_TXMPTYEN_MASK) +#define UART_UCR1_IREN_MASK (0x80U) +#define UART_UCR1_IREN_SHIFT (7U) +#define UART_UCR1_IREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IREN_SHIFT)) & UART_UCR1_IREN_MASK) +#define UART_UCR1_RXDMAEN_MASK (0x100U) +#define UART_UCR1_RXDMAEN_SHIFT (8U) +#define UART_UCR1_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RXDMAEN_SHIFT)) & UART_UCR1_RXDMAEN_MASK) +#define UART_UCR1_RRDYEN_MASK (0x200U) +#define UART_UCR1_RRDYEN_SHIFT (9U) +#define UART_UCR1_RRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RRDYEN_SHIFT)) & UART_UCR1_RRDYEN_MASK) +#define UART_UCR1_ICD_MASK (0xC00U) +#define UART_UCR1_ICD_SHIFT (10U) +#define UART_UCR1_ICD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ICD_SHIFT)) & UART_UCR1_ICD_MASK) +#define UART_UCR1_IDEN_MASK (0x1000U) +#define UART_UCR1_IDEN_SHIFT (12U) +#define UART_UCR1_IDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IDEN_SHIFT)) & UART_UCR1_IDEN_MASK) +#define UART_UCR1_TRDYEN_MASK (0x2000U) +#define UART_UCR1_TRDYEN_SHIFT (13U) +#define UART_UCR1_TRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TRDYEN_SHIFT)) & UART_UCR1_TRDYEN_MASK) +#define UART_UCR1_ADBR_MASK (0x4000U) +#define UART_UCR1_ADBR_SHIFT (14U) +#define UART_UCR1_ADBR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADBR_SHIFT)) & UART_UCR1_ADBR_MASK) +#define UART_UCR1_ADEN_MASK (0x8000U) +#define UART_UCR1_ADEN_SHIFT (15U) +#define UART_UCR1_ADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADEN_SHIFT)) & UART_UCR1_ADEN_MASK) + +/*! @name UCR2 - UART Control Register 2 */ +#define UART_UCR2_SRST_MASK (0x1U) +#define UART_UCR2_SRST_SHIFT (0U) +#define UART_UCR2_SRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_SRST_SHIFT)) & UART_UCR2_SRST_MASK) +#define UART_UCR2_RXEN_MASK (0x2U) +#define UART_UCR2_RXEN_SHIFT (1U) +#define UART_UCR2_RXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RXEN_SHIFT)) & UART_UCR2_RXEN_MASK) +#define UART_UCR2_TXEN_MASK (0x4U) +#define UART_UCR2_TXEN_SHIFT (2U) +#define UART_UCR2_TXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_TXEN_SHIFT)) & UART_UCR2_TXEN_MASK) +#define UART_UCR2_ATEN_MASK (0x8U) +#define UART_UCR2_ATEN_SHIFT (3U) +#define UART_UCR2_ATEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ATEN_SHIFT)) & UART_UCR2_ATEN_MASK) +#define UART_UCR2_RTSEN_MASK (0x10U) +#define UART_UCR2_RTSEN_SHIFT (4U) +#define UART_UCR2_RTSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTSEN_SHIFT)) & UART_UCR2_RTSEN_MASK) +#define UART_UCR2_WS_MASK (0x20U) +#define UART_UCR2_WS_SHIFT (5U) +#define UART_UCR2_WS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_WS_SHIFT)) & UART_UCR2_WS_MASK) +#define UART_UCR2_STPB_MASK (0x40U) +#define UART_UCR2_STPB_SHIFT (6U) +#define UART_UCR2_STPB(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_STPB_SHIFT)) & UART_UCR2_STPB_MASK) +#define UART_UCR2_PROE_MASK (0x80U) +#define UART_UCR2_PROE_SHIFT (7U) +#define UART_UCR2_PROE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PROE_SHIFT)) & UART_UCR2_PROE_MASK) +#define UART_UCR2_PREN_MASK (0x100U) +#define UART_UCR2_PREN_SHIFT (8U) +#define UART_UCR2_PREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PREN_SHIFT)) & UART_UCR2_PREN_MASK) +#define UART_UCR2_RTEC_MASK (0x600U) +#define UART_UCR2_RTEC_SHIFT (9U) +#define UART_UCR2_RTEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTEC_SHIFT)) & UART_UCR2_RTEC_MASK) +#define UART_UCR2_ESCEN_MASK (0x800U) +#define UART_UCR2_ESCEN_SHIFT (11U) +#define UART_UCR2_ESCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCEN_SHIFT)) & UART_UCR2_ESCEN_MASK) +#define UART_UCR2_CTS_MASK (0x1000U) +#define UART_UCR2_CTS_SHIFT (12U) +#define UART_UCR2_CTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTS_SHIFT)) & UART_UCR2_CTS_MASK) +#define UART_UCR2_CTSC_MASK (0x2000U) +#define UART_UCR2_CTSC_SHIFT (13U) +#define UART_UCR2_CTSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTSC_SHIFT)) & UART_UCR2_CTSC_MASK) +#define UART_UCR2_IRTS_MASK (0x4000U) +#define UART_UCR2_IRTS_SHIFT (14U) +#define UART_UCR2_IRTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_IRTS_SHIFT)) & UART_UCR2_IRTS_MASK) +#define UART_UCR2_ESCI_MASK (0x8000U) +#define UART_UCR2_ESCI_SHIFT (15U) +#define UART_UCR2_ESCI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCI_SHIFT)) & UART_UCR2_ESCI_MASK) + +/*! @name UCR3 - UART Control Register 3 */ +#define UART_UCR3_ACIEN_MASK (0x1U) +#define UART_UCR3_ACIEN_SHIFT (0U) +#define UART_UCR3_ACIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ACIEN_SHIFT)) & UART_UCR3_ACIEN_MASK) +#define UART_UCR3_INVT_MASK (0x2U) +#define UART_UCR3_INVT_SHIFT (1U) +#define UART_UCR3_INVT(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_INVT_SHIFT)) & UART_UCR3_INVT_MASK) +#define UART_UCR3_RXDMUXSEL_MASK (0x4U) +#define UART_UCR3_RXDMUXSEL_SHIFT (2U) +#define UART_UCR3_RXDMUXSEL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDMUXSEL_SHIFT)) & UART_UCR3_RXDMUXSEL_MASK) +#define UART_UCR3_DTRDEN_MASK (0x8U) +#define UART_UCR3_DTRDEN_SHIFT (3U) +#define UART_UCR3_DTRDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTRDEN_SHIFT)) & UART_UCR3_DTRDEN_MASK) +#define UART_UCR3_AWAKEN_MASK (0x10U) +#define UART_UCR3_AWAKEN_SHIFT (4U) +#define UART_UCR3_AWAKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AWAKEN_SHIFT)) & UART_UCR3_AWAKEN_MASK) +#define UART_UCR3_AIRINTEN_MASK (0x20U) +#define UART_UCR3_AIRINTEN_SHIFT (5U) +#define UART_UCR3_AIRINTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AIRINTEN_SHIFT)) & UART_UCR3_AIRINTEN_MASK) +#define UART_UCR3_RXDSEN_MASK (0x40U) +#define UART_UCR3_RXDSEN_SHIFT (6U) +#define UART_UCR3_RXDSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDSEN_SHIFT)) & UART_UCR3_RXDSEN_MASK) +#define UART_UCR3_ADNIMP_MASK (0x80U) +#define UART_UCR3_ADNIMP_SHIFT (7U) +#define UART_UCR3_ADNIMP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ADNIMP_SHIFT)) & UART_UCR3_ADNIMP_MASK) +#define UART_UCR3_RI_MASK (0x100U) +#define UART_UCR3_RI_SHIFT (8U) +#define UART_UCR3_RI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RI_SHIFT)) & UART_UCR3_RI_MASK) +#define UART_UCR3_DCD_MASK (0x200U) +#define UART_UCR3_DCD_SHIFT (9U) +#define UART_UCR3_DCD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DCD_SHIFT)) & UART_UCR3_DCD_MASK) +#define UART_UCR3_DSR_MASK (0x400U) +#define UART_UCR3_DSR_SHIFT (10U) +#define UART_UCR3_DSR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DSR_SHIFT)) & UART_UCR3_DSR_MASK) +#define UART_UCR3_FRAERREN_MASK (0x800U) +#define UART_UCR3_FRAERREN_SHIFT (11U) +#define UART_UCR3_FRAERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_FRAERREN_SHIFT)) & UART_UCR3_FRAERREN_MASK) +#define UART_UCR3_PARERREN_MASK (0x1000U) +#define UART_UCR3_PARERREN_SHIFT (12U) +#define UART_UCR3_PARERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_PARERREN_SHIFT)) & UART_UCR3_PARERREN_MASK) +#define UART_UCR3_DTREN_MASK (0x2000U) +#define UART_UCR3_DTREN_SHIFT (13U) +#define UART_UCR3_DTREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTREN_SHIFT)) & UART_UCR3_DTREN_MASK) +#define UART_UCR3_DPEC_MASK (0xC000U) +#define UART_UCR3_DPEC_SHIFT (14U) +#define UART_UCR3_DPEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DPEC_SHIFT)) & UART_UCR3_DPEC_MASK) + +/*! @name UCR4 - UART Control Register 4 */ +#define UART_UCR4_DREN_MASK (0x1U) +#define UART_UCR4_DREN_SHIFT (0U) +#define UART_UCR4_DREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_DREN_SHIFT)) & UART_UCR4_DREN_MASK) +#define UART_UCR4_OREN_MASK (0x2U) +#define UART_UCR4_OREN_SHIFT (1U) +#define UART_UCR4_OREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_OREN_SHIFT)) & UART_UCR4_OREN_MASK) +#define UART_UCR4_BKEN_MASK (0x4U) +#define UART_UCR4_BKEN_SHIFT (2U) +#define UART_UCR4_BKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_BKEN_SHIFT)) & UART_UCR4_BKEN_MASK) +#define UART_UCR4_TCEN_MASK (0x8U) +#define UART_UCR4_TCEN_SHIFT (3U) +#define UART_UCR4_TCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_TCEN_SHIFT)) & UART_UCR4_TCEN_MASK) +#define UART_UCR4_LPBYP_MASK (0x10U) +#define UART_UCR4_LPBYP_SHIFT (4U) +#define UART_UCR4_LPBYP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_LPBYP_SHIFT)) & UART_UCR4_LPBYP_MASK) +#define UART_UCR4_IRSC_MASK (0x20U) +#define UART_UCR4_IRSC_SHIFT (5U) +#define UART_UCR4_IRSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IRSC_SHIFT)) & UART_UCR4_IRSC_MASK) +#define UART_UCR4_IDDMAEN_MASK (0x40U) +#define UART_UCR4_IDDMAEN_SHIFT (6U) +#define UART_UCR4_IDDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IDDMAEN_SHIFT)) & UART_UCR4_IDDMAEN_MASK) +#define UART_UCR4_WKEN_MASK (0x80U) +#define UART_UCR4_WKEN_SHIFT (7U) +#define UART_UCR4_WKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_WKEN_SHIFT)) & UART_UCR4_WKEN_MASK) +#define UART_UCR4_ENIRI_MASK (0x100U) +#define UART_UCR4_ENIRI_SHIFT (8U) +#define UART_UCR4_ENIRI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_ENIRI_SHIFT)) & UART_UCR4_ENIRI_MASK) +#define UART_UCR4_INVR_MASK (0x200U) +#define UART_UCR4_INVR_SHIFT (9U) +#define UART_UCR4_INVR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_INVR_SHIFT)) & UART_UCR4_INVR_MASK) +#define UART_UCR4_CTSTL_MASK (0xFC00U) +#define UART_UCR4_CTSTL_SHIFT (10U) +#define UART_UCR4_CTSTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_CTSTL_SHIFT)) & UART_UCR4_CTSTL_MASK) + +/*! @name UFCR - UART FIFO Control Register */ +#define UART_UFCR_RXTL_MASK (0x3FU) +#define UART_UFCR_RXTL_SHIFT (0U) +#define UART_UFCR_RXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RXTL_SHIFT)) & UART_UFCR_RXTL_MASK) +#define UART_UFCR_DCEDTE_MASK (0x40U) +#define UART_UFCR_DCEDTE_SHIFT (6U) +#define UART_UFCR_DCEDTE(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_DCEDTE_SHIFT)) & UART_UFCR_DCEDTE_MASK) +#define UART_UFCR_RFDIV_MASK (0x380U) +#define UART_UFCR_RFDIV_SHIFT (7U) +#define UART_UFCR_RFDIV(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RFDIV_SHIFT)) & UART_UFCR_RFDIV_MASK) +#define UART_UFCR_TXTL_MASK (0xFC00U) +#define UART_UFCR_TXTL_SHIFT (10U) +#define UART_UFCR_TXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_TXTL_SHIFT)) & UART_UFCR_TXTL_MASK) + +/*! @name USR1 - UART Status Register 1 */ +#define UART_USR1_SAD_MASK (0x8U) +#define UART_USR1_SAD_SHIFT (3U) +#define UART_USR1_SAD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_SAD_SHIFT)) & UART_USR1_SAD_MASK) +#define UART_USR1_AWAKE_MASK (0x10U) +#define UART_USR1_AWAKE_SHIFT (4U) +#define UART_USR1_AWAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AWAKE_SHIFT)) & UART_USR1_AWAKE_MASK) +#define UART_USR1_AIRINT_MASK (0x20U) +#define UART_USR1_AIRINT_SHIFT (5U) +#define UART_USR1_AIRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AIRINT_SHIFT)) & UART_USR1_AIRINT_MASK) +#define UART_USR1_RXDS_MASK (0x40U) +#define UART_USR1_RXDS_SHIFT (6U) +#define UART_USR1_RXDS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RXDS_SHIFT)) & UART_USR1_RXDS_MASK) +#define UART_USR1_DTRD_MASK (0x80U) +#define UART_USR1_DTRD_SHIFT (7U) +#define UART_USR1_DTRD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_DTRD_SHIFT)) & UART_USR1_DTRD_MASK) +#define UART_USR1_AGTIM_MASK (0x100U) +#define UART_USR1_AGTIM_SHIFT (8U) +#define UART_USR1_AGTIM(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AGTIM_SHIFT)) & UART_USR1_AGTIM_MASK) +#define UART_USR1_RRDY_MASK (0x200U) +#define UART_USR1_RRDY_SHIFT (9U) +#define UART_USR1_RRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RRDY_SHIFT)) & UART_USR1_RRDY_MASK) +#define UART_USR1_FRAMERR_MASK (0x400U) +#define UART_USR1_FRAMERR_SHIFT (10U) +#define UART_USR1_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_FRAMERR_SHIFT)) & UART_USR1_FRAMERR_MASK) +#define UART_USR1_ESCF_MASK (0x800U) +#define UART_USR1_ESCF_SHIFT (11U) +#define UART_USR1_ESCF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_ESCF_SHIFT)) & UART_USR1_ESCF_MASK) +#define UART_USR1_RTSD_MASK (0x1000U) +#define UART_USR1_RTSD_SHIFT (12U) +#define UART_USR1_RTSD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSD_SHIFT)) & UART_USR1_RTSD_MASK) +#define UART_USR1_TRDY_MASK (0x2000U) +#define UART_USR1_TRDY_SHIFT (13U) +#define UART_USR1_TRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_TRDY_SHIFT)) & UART_USR1_TRDY_MASK) +#define UART_USR1_RTSS_MASK (0x4000U) +#define UART_USR1_RTSS_SHIFT (14U) +#define UART_USR1_RTSS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSS_SHIFT)) & UART_USR1_RTSS_MASK) +#define UART_USR1_PARITYERR_MASK (0x8000U) +#define UART_USR1_PARITYERR_SHIFT (15U) +#define UART_USR1_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_PARITYERR_SHIFT)) & UART_USR1_PARITYERR_MASK) + +/*! @name USR2 - UART Status Register 2 */ +#define UART_USR2_RDR_MASK (0x1U) +#define UART_USR2_RDR_SHIFT (0U) +#define UART_USR2_RDR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RDR_SHIFT)) & UART_USR2_RDR_MASK) +#define UART_USR2_ORE_MASK (0x2U) +#define UART_USR2_ORE_SHIFT (1U) +#define UART_USR2_ORE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ORE_SHIFT)) & UART_USR2_ORE_MASK) +#define UART_USR2_BRCD_MASK (0x4U) +#define UART_USR2_BRCD_SHIFT (2U) +#define UART_USR2_BRCD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_BRCD_SHIFT)) & UART_USR2_BRCD_MASK) +#define UART_USR2_TXDC_MASK (0x8U) +#define UART_USR2_TXDC_SHIFT (3U) +#define UART_USR2_TXDC(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXDC_SHIFT)) & UART_USR2_TXDC_MASK) +#define UART_USR2_RTSF_MASK (0x10U) +#define UART_USR2_RTSF_SHIFT (4U) +#define UART_USR2_RTSF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RTSF_SHIFT)) & UART_USR2_RTSF_MASK) +#define UART_USR2_DCDIN_MASK (0x20U) +#define UART_USR2_DCDIN_SHIFT (5U) +#define UART_USR2_DCDIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDIN_SHIFT)) & UART_USR2_DCDIN_MASK) +#define UART_USR2_DCDDELT_MASK (0x40U) +#define UART_USR2_DCDDELT_SHIFT (6U) +#define UART_USR2_DCDDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDDELT_SHIFT)) & UART_USR2_DCDDELT_MASK) +#define UART_USR2_WAKE_MASK (0x80U) +#define UART_USR2_WAKE_SHIFT (7U) +#define UART_USR2_WAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_WAKE_SHIFT)) & UART_USR2_WAKE_MASK) +#define UART_USR2_IRINT_MASK (0x100U) +#define UART_USR2_IRINT_SHIFT (8U) +#define UART_USR2_IRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IRINT_SHIFT)) & UART_USR2_IRINT_MASK) +#define UART_USR2_RIIN_MASK (0x200U) +#define UART_USR2_RIIN_SHIFT (9U) +#define UART_USR2_RIIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIIN_SHIFT)) & UART_USR2_RIIN_MASK) +#define UART_USR2_RIDELT_MASK (0x400U) +#define UART_USR2_RIDELT_SHIFT (10U) +#define UART_USR2_RIDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIDELT_SHIFT)) & UART_USR2_RIDELT_MASK) +#define UART_USR2_ACST_MASK (0x800U) +#define UART_USR2_ACST_SHIFT (11U) +#define UART_USR2_ACST(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ACST_SHIFT)) & UART_USR2_ACST_MASK) +#define UART_USR2_IDLE_MASK (0x1000U) +#define UART_USR2_IDLE_SHIFT (12U) +#define UART_USR2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IDLE_SHIFT)) & UART_USR2_IDLE_MASK) +#define UART_USR2_DTRF_MASK (0x2000U) +#define UART_USR2_DTRF_SHIFT (13U) +#define UART_USR2_DTRF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DTRF_SHIFT)) & UART_USR2_DTRF_MASK) +#define UART_USR2_TXFE_MASK (0x4000U) +#define UART_USR2_TXFE_SHIFT (14U) +#define UART_USR2_TXFE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXFE_SHIFT)) & UART_USR2_TXFE_MASK) +#define UART_USR2_ADET_MASK (0x8000U) +#define UART_USR2_ADET_SHIFT (15U) +#define UART_USR2_ADET(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ADET_SHIFT)) & UART_USR2_ADET_MASK) + +/*! @name UESC - UART Escape Character Register */ +#define UART_UESC_ESC_CHAR_MASK (0xFFU) +#define UART_UESC_ESC_CHAR_SHIFT (0U) +#define UART_UESC_ESC_CHAR(x) (((uint32_t)(((uint32_t)(x)) << UART_UESC_ESC_CHAR_SHIFT)) & UART_UESC_ESC_CHAR_MASK) + +/*! @name UTIM - UART Escape Timer Register */ +#define UART_UTIM_TIM_MASK (0xFFFU) +#define UART_UTIM_TIM_SHIFT (0U) +#define UART_UTIM_TIM(x) (((uint32_t)(((uint32_t)(x)) << UART_UTIM_TIM_SHIFT)) & UART_UTIM_TIM_MASK) + +/*! @name UBIR - UART BRM Incremental Register */ +#define UART_UBIR_INC_MASK (0xFFFFU) +#define UART_UBIR_INC_SHIFT (0U) +#define UART_UBIR_INC(x) (((uint32_t)(((uint32_t)(x)) << UART_UBIR_INC_SHIFT)) & UART_UBIR_INC_MASK) + +/*! @name UBMR - UART BRM Modulator Register */ +#define UART_UBMR_MOD_MASK (0xFFFFU) +#define UART_UBMR_MOD_SHIFT (0U) +#define UART_UBMR_MOD(x) (((uint32_t)(((uint32_t)(x)) << UART_UBMR_MOD_SHIFT)) & UART_UBMR_MOD_MASK) + +/*! @name UBRC - UART Baud Rate Count Register */ +#define UART_UBRC_BCNT_MASK (0xFFFFU) +#define UART_UBRC_BCNT_SHIFT (0U) +#define UART_UBRC_BCNT(x) (((uint32_t)(((uint32_t)(x)) << UART_UBRC_BCNT_SHIFT)) & UART_UBRC_BCNT_MASK) + +/*! @name ONEMS - UART One Millisecond Register */ +#define UART_ONEMS_ONEMS_MASK (0xFFFFFFU) +#define UART_ONEMS_ONEMS_SHIFT (0U) +#define UART_ONEMS_ONEMS(x) (((uint32_t)(((uint32_t)(x)) << UART_ONEMS_ONEMS_SHIFT)) & UART_ONEMS_ONEMS_MASK) + +/*! @name UTS - UART Test Register */ +#define UART_UTS_SOFTRST_MASK (0x1U) +#define UART_UTS_SOFTRST_SHIFT (0U) +#define UART_UTS_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_SOFTRST_SHIFT)) & UART_UTS_SOFTRST_MASK) +#define UART_UTS_RXFULL_MASK (0x8U) +#define UART_UTS_RXFULL_SHIFT (3U) +#define UART_UTS_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXFULL_SHIFT)) & UART_UTS_RXFULL_MASK) +#define UART_UTS_TXFULL_MASK (0x10U) +#define UART_UTS_TXFULL_SHIFT (4U) +#define UART_UTS_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXFULL_SHIFT)) & UART_UTS_TXFULL_MASK) +#define UART_UTS_RXEMPTY_MASK (0x20U) +#define UART_UTS_RXEMPTY_SHIFT (5U) +#define UART_UTS_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXEMPTY_SHIFT)) & UART_UTS_RXEMPTY_MASK) +#define UART_UTS_TXEMPTY_MASK (0x40U) +#define UART_UTS_TXEMPTY_SHIFT (6U) +#define UART_UTS_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXEMPTY_SHIFT)) & UART_UTS_TXEMPTY_MASK) +#define UART_UTS_RXDBG_MASK (0x200U) +#define UART_UTS_RXDBG_SHIFT (9U) +#define UART_UTS_RXDBG(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXDBG_SHIFT)) & UART_UTS_RXDBG_MASK) +#define UART_UTS_LOOPIR_MASK (0x400U) +#define UART_UTS_LOOPIR_SHIFT (10U) +#define UART_UTS_LOOPIR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOPIR_SHIFT)) & UART_UTS_LOOPIR_MASK) +#define UART_UTS_DBGEN_MASK (0x800U) +#define UART_UTS_DBGEN_SHIFT (11U) +#define UART_UTS_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_DBGEN_SHIFT)) & UART_UTS_DBGEN_MASK) +#define UART_UTS_LOOP_MASK (0x1000U) +#define UART_UTS_LOOP_SHIFT (12U) +#define UART_UTS_LOOP(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOP_SHIFT)) & UART_UTS_LOOP_MASK) +#define UART_UTS_FRCPERR_MASK (0x2000U) +#define UART_UTS_FRCPERR_SHIFT (13U) +#define UART_UTS_FRCPERR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_FRCPERR_SHIFT)) & UART_UTS_FRCPERR_MASK) + +/*! @name UMCR - UART RS-485 Mode Control Register */ +#define UART_UMCR_MDEN_MASK (0x1U) +#define UART_UMCR_MDEN_SHIFT (0U) +#define UART_UMCR_MDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_MDEN_SHIFT)) & UART_UMCR_MDEN_MASK) +#define UART_UMCR_SLAM_MASK (0x2U) +#define UART_UMCR_SLAM_SHIFT (1U) +#define UART_UMCR_SLAM(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLAM_SHIFT)) & UART_UMCR_SLAM_MASK) +#define UART_UMCR_TXB8_MASK (0x4U) +#define UART_UMCR_TXB8_SHIFT (2U) +#define UART_UMCR_TXB8(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_TXB8_SHIFT)) & UART_UMCR_TXB8_MASK) +#define UART_UMCR_SADEN_MASK (0x8U) +#define UART_UMCR_SADEN_SHIFT (3U) +#define UART_UMCR_SADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SADEN_SHIFT)) & UART_UMCR_SADEN_MASK) +#define UART_UMCR_SLADDR_MASK (0xFF00U) +#define UART_UMCR_SLADDR_SHIFT (8U) +#define UART_UMCR_SLADDR(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLADDR_SHIFT)) & UART_UMCR_SLADDR_MASK) + + +/*! + * @} + */ /* end of group UART_Register_Masks */ + + +/* UART - Peripheral instance base addresses */ +/** Peripheral UART1 base address */ +#define UART1_BASE (0x2020000u) +/** Peripheral UART1 base pointer */ +#define UART1 ((UART_Type *)UART1_BASE) +/** Peripheral UART2 base address */ +#define UART2_BASE (0x21E8000u) +/** Peripheral UART2 base pointer */ +#define UART2 ((UART_Type *)UART2_BASE) +/** Peripheral UART3 base address */ +#define UART3_BASE (0x21EC000u) +/** Peripheral UART3 base pointer */ +#define UART3 ((UART_Type *)UART3_BASE) +/** Peripheral UART4 base address */ +#define UART4_BASE (0x21F0000u) +/** Peripheral UART4 base pointer */ +#define UART4 ((UART_Type *)UART4_BASE) +/** Peripheral UART5 base address */ +#define UART5_BASE (0x21F4000u) +/** Peripheral UART5 base pointer */ +#define UART5 ((UART_Type *)UART5_BASE) +/** Peripheral UART6 base address */ +#define UART6_BASE (0x21FC000u) +/** Peripheral UART6 base pointer */ +#define UART6 ((UART_Type *)UART6_BASE) +/** Peripheral UART7 base address */ +#define UART7_BASE (0x2018000u) +/** Peripheral UART7 base pointer */ +#define UART7 ((UART_Type *)UART7_BASE) +/** Peripheral UART8 base address */ +#define UART8_BASE (0x2288000u) +/** Peripheral UART8 base pointer */ +#define UART8 ((UART_Type *)UART8_BASE) +/** Array initializer of UART peripheral base addresses */ +#define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE, UART6_BASE, UART7_BASE, UART8_BASE } +/** Array initializer of UART peripheral base pointers */ +#define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2, UART3, UART4, UART5, UART6, UART7, UART8 } +/** Interrupt vectors for the UART peripheral type */ +#define UART_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn, UART5_IRQn, UART6_IRQn, UART7_IRQn, UART8_IRQn } + +/*! + * @} + */ /* end of group UART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification register, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + }; + union { /* offset: 0x158 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name ID - Identification register */ +#define USB_ID_ID_MASK (0x3FU) +#define USB_ID_ID_SHIFT (0U) +#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) +#define USB_ID_NID_MASK (0x3F00U) +#define USB_ID_NID_SHIFT (8U) +#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) +#define USB_ID_REVISION_MASK (0xFF0000U) +#define USB_ID_REVISION_SHIFT (16U) +#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) + +/*! @name HWGENERAL - Hardware General */ +#define USB_HWGENERAL_PHYW_MASK (0x30U) +#define USB_HWGENERAL_PHYW_SHIFT (4U) +#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) +#define USB_HWGENERAL_PHYM_MASK (0x1C0U) +#define USB_HWGENERAL_PHYM_SHIFT (6U) +#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) +#define USB_HWGENERAL_SM_MASK (0x600U) +#define USB_HWGENERAL_SM_SHIFT (9U) +#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) + +/*! @name HWHOST - Host Hardware Parameters */ +#define USB_HWHOST_HC_MASK (0x1U) +#define USB_HWHOST_HC_SHIFT (0U) +#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) +#define USB_HWHOST_NPORT_MASK (0xEU) +#define USB_HWHOST_NPORT_SHIFT (1U) +#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) + +/*! @name HWDEVICE - Device Hardware Parameters */ +#define USB_HWDEVICE_DC_MASK (0x1U) +#define USB_HWDEVICE_DC_SHIFT (0U) +#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) +#define USB_HWDEVICE_DEVEP_MASK (0x3EU) +#define USB_HWDEVICE_DEVEP_SHIFT (1U) +#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) + +/*! @name HWTXBUF - TX Buffer Hardware Parameters */ +#define USB_HWTXBUF_TXBURST_MASK (0xFFU) +#define USB_HWTXBUF_TXBURST_SHIFT (0U) +#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) +#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) +#define USB_HWTXBUF_TXCHANADD_SHIFT (16U) +#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) + +/*! @name HWRXBUF - RX Buffer Hardware Parameters */ +#define USB_HWRXBUF_RXBURST_MASK (0xFFU) +#define USB_HWRXBUF_RXBURST_SHIFT (0U) +#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) +#define USB_HWRXBUF_RXADD_MASK (0xFF00U) +#define USB_HWRXBUF_RXADD_SHIFT (8U) +#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) + +/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) + +/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) +#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) +#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) +#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) + +/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) + +/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) +#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) +#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) +#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) + +/*! @name SBUSCFG - System Bus Config */ +#define USB_SBUSCFG_AHBBRST_MASK (0x7U) +#define USB_SBUSCFG_AHBBRST_SHIFT (0U) +#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) + +/*! @name CAPLENGTH - Capability Registers Length */ +#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) +#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) +#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) + +/*! @name HCIVERSION - Host Controller Interface Version */ +#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) +#define USB_HCIVERSION_HCIVERSION_SHIFT (0U) +#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +#define USB_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USB_HCSPARAMS_N_PORTS_SHIFT (0U) +#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) +#define USB_HCSPARAMS_PPC_MASK (0x10U) +#define USB_HCSPARAMS_PPC_SHIFT (4U) +#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) +#define USB_HCSPARAMS_N_PCC_MASK (0xF00U) +#define USB_HCSPARAMS_N_PCC_SHIFT (8U) +#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) +#define USB_HCSPARAMS_N_CC_MASK (0xF000U) +#define USB_HCSPARAMS_N_CC_SHIFT (12U) +#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) +#define USB_HCSPARAMS_PI_MASK (0x10000U) +#define USB_HCSPARAMS_PI_SHIFT (16U) +#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) +#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) +#define USB_HCSPARAMS_N_PTT_SHIFT (20U) +#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) +#define USB_HCSPARAMS_N_TT_MASK (0xF000000U) +#define USB_HCSPARAMS_N_TT_SHIFT (24U) +#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +#define USB_HCCPARAMS_ADC_MASK (0x1U) +#define USB_HCCPARAMS_ADC_SHIFT (0U) +#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) +#define USB_HCCPARAMS_PFL_MASK (0x2U) +#define USB_HCCPARAMS_PFL_SHIFT (1U) +#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) +#define USB_HCCPARAMS_ASP_MASK (0x4U) +#define USB_HCCPARAMS_ASP_SHIFT (2U) +#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) +#define USB_HCCPARAMS_IST_MASK (0xF0U) +#define USB_HCCPARAMS_IST_SHIFT (4U) +#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) +#define USB_HCCPARAMS_EECP_MASK (0xFF00U) +#define USB_HCCPARAMS_EECP_SHIFT (8U) +#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) + +/*! @name DCIVERSION - Device Controller Interface Version */ +#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) +#define USB_DCIVERSION_DCIVERSION_SHIFT (0U) +#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) + +/*! @name DCCPARAMS - Device Controller Capability Parameters */ +#define USB_DCCPARAMS_DEN_MASK (0x1FU) +#define USB_DCCPARAMS_DEN_SHIFT (0U) +#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) +#define USB_DCCPARAMS_DC_MASK (0x80U) +#define USB_DCCPARAMS_DC_SHIFT (7U) +#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) +#define USB_DCCPARAMS_HC_MASK (0x100U) +#define USB_DCCPARAMS_HC_SHIFT (8U) +#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) + +/*! @name USBCMD - USB Command Register */ +#define USB_USBCMD_RS_MASK (0x1U) +#define USB_USBCMD_RS_SHIFT (0U) +#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) +#define USB_USBCMD_RST_MASK (0x2U) +#define USB_USBCMD_RST_SHIFT (1U) +#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) +#define USB_USBCMD_FS_1_MASK (0xCU) +#define USB_USBCMD_FS_1_SHIFT (2U) +#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) +#define USB_USBCMD_PSE_MASK (0x10U) +#define USB_USBCMD_PSE_SHIFT (4U) +#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) +#define USB_USBCMD_ASE_MASK (0x20U) +#define USB_USBCMD_ASE_SHIFT (5U) +#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) +#define USB_USBCMD_IAA_MASK (0x40U) +#define USB_USBCMD_IAA_SHIFT (6U) +#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) +#define USB_USBCMD_ASP_MASK (0x300U) +#define USB_USBCMD_ASP_SHIFT (8U) +#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) +#define USB_USBCMD_ASPE_MASK (0x800U) +#define USB_USBCMD_ASPE_SHIFT (11U) +#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) +#define USB_USBCMD_ATDTW_MASK (0x1000U) +#define USB_USBCMD_ATDTW_SHIFT (12U) +#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) +#define USB_USBCMD_SUTW_MASK (0x2000U) +#define USB_USBCMD_SUTW_SHIFT (13U) +#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) +#define USB_USBCMD_FS_2_MASK (0x8000U) +#define USB_USBCMD_FS_2_SHIFT (15U) +#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) +#define USB_USBCMD_ITC_MASK (0xFF0000U) +#define USB_USBCMD_ITC_SHIFT (16U) +#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) + +/*! @name USBSTS - USB Status Register */ +#define USB_USBSTS_UI_MASK (0x1U) +#define USB_USBSTS_UI_SHIFT (0U) +#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) +#define USB_USBSTS_UEI_MASK (0x2U) +#define USB_USBSTS_UEI_SHIFT (1U) +#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) +#define USB_USBSTS_PCI_MASK (0x4U) +#define USB_USBSTS_PCI_SHIFT (2U) +#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) +#define USB_USBSTS_FRI_MASK (0x8U) +#define USB_USBSTS_FRI_SHIFT (3U) +#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) +#define USB_USBSTS_SEI_MASK (0x10U) +#define USB_USBSTS_SEI_SHIFT (4U) +#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) +#define USB_USBSTS_AAI_MASK (0x20U) +#define USB_USBSTS_AAI_SHIFT (5U) +#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) +#define USB_USBSTS_URI_MASK (0x40U) +#define USB_USBSTS_URI_SHIFT (6U) +#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) +#define USB_USBSTS_SRI_MASK (0x80U) +#define USB_USBSTS_SRI_SHIFT (7U) +#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) +#define USB_USBSTS_SLI_MASK (0x100U) +#define USB_USBSTS_SLI_SHIFT (8U) +#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) +#define USB_USBSTS_ULPII_MASK (0x400U) +#define USB_USBSTS_ULPII_SHIFT (10U) +#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) +#define USB_USBSTS_HCH_MASK (0x1000U) +#define USB_USBSTS_HCH_SHIFT (12U) +#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) +#define USB_USBSTS_RCL_MASK (0x2000U) +#define USB_USBSTS_RCL_SHIFT (13U) +#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) +#define USB_USBSTS_PS_MASK (0x4000U) +#define USB_USBSTS_PS_SHIFT (14U) +#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) +#define USB_USBSTS_AS_MASK (0x8000U) +#define USB_USBSTS_AS_SHIFT (15U) +#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) +#define USB_USBSTS_NAKI_MASK (0x10000U) +#define USB_USBSTS_NAKI_SHIFT (16U) +#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) +#define USB_USBSTS_TI0_MASK (0x1000000U) +#define USB_USBSTS_TI0_SHIFT (24U) +#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) +#define USB_USBSTS_TI1_MASK (0x2000000U) +#define USB_USBSTS_TI1_SHIFT (25U) +#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) + +/*! @name USBINTR - Interrupt Enable Register */ +#define USB_USBINTR_UE_MASK (0x1U) +#define USB_USBINTR_UE_SHIFT (0U) +#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) +#define USB_USBINTR_UEE_MASK (0x2U) +#define USB_USBINTR_UEE_SHIFT (1U) +#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) +#define USB_USBINTR_PCE_MASK (0x4U) +#define USB_USBINTR_PCE_SHIFT (2U) +#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) +#define USB_USBINTR_FRE_MASK (0x8U) +#define USB_USBINTR_FRE_SHIFT (3U) +#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) +#define USB_USBINTR_SEE_MASK (0x10U) +#define USB_USBINTR_SEE_SHIFT (4U) +#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) +#define USB_USBINTR_AAE_MASK (0x20U) +#define USB_USBINTR_AAE_SHIFT (5U) +#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) +#define USB_USBINTR_URE_MASK (0x40U) +#define USB_USBINTR_URE_SHIFT (6U) +#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) +#define USB_USBINTR_SRE_MASK (0x80U) +#define USB_USBINTR_SRE_SHIFT (7U) +#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) +#define USB_USBINTR_SLE_MASK (0x100U) +#define USB_USBINTR_SLE_SHIFT (8U) +#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) +#define USB_USBINTR_ULPIE_MASK (0x400U) +#define USB_USBINTR_ULPIE_SHIFT (10U) +#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) +#define USB_USBINTR_NAKE_MASK (0x10000U) +#define USB_USBINTR_NAKE_SHIFT (16U) +#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) +#define USB_USBINTR_UAIE_MASK (0x40000U) +#define USB_USBINTR_UAIE_SHIFT (18U) +#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) +#define USB_USBINTR_UPIE_MASK (0x80000U) +#define USB_USBINTR_UPIE_SHIFT (19U) +#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) +#define USB_USBINTR_TIE0_MASK (0x1000000U) +#define USB_USBINTR_TIE0_SHIFT (24U) +#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) +#define USB_USBINTR_TIE1_MASK (0x2000000U) +#define USB_USBINTR_TIE1_SHIFT (25U) +#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) + +/*! @name FRINDEX - USB Frame Index */ +#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USB_FRINDEX_FRINDEX_SHIFT (0U) +#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) + +/*! @name DEVICEADDR - Device Address */ +#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) +#define USB_DEVICEADDR_USBADRA_SHIFT (24U) +#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) +#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) +#define USB_DEVICEADDR_USBADR_SHIFT (25U) +#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) + +/*! @name PERIODICLISTBASE - Frame List Base Address */ +#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) +#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) + +/*! @name ASYNCLISTADDR - Next Asynch. Address */ +#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) + +/*! @name ENDPTLISTADDR - Endpoint List Address */ +#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) +#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) + +/*! @name BURSTSIZE - Programmable Burst Size */ +#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) +#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) +#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) + +/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) +#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) + +/*! @name ENDPTNAK - Endpoint NAK */ +#define USB_ENDPTNAK_EPRN_MASK (0xFFU) +#define USB_ENDPTNAK_EPRN_SHIFT (0U) +#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) +#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) +#define USB_ENDPTNAK_EPTN_SHIFT (16U) +#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) + +/*! @name ENDPTNAKEN - Endpoint NAK Enable */ +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) +#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) + +/*! @name CONFIGFLAG - Configure Flag Register */ +#define USB_CONFIGFLAG_CF_MASK (0x1U) +#define USB_CONFIGFLAG_CF_SHIFT (0U) +#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) + +/*! @name PORTSC1 - Port Status & Control */ +#define USB_PORTSC1_CCS_MASK (0x1U) +#define USB_PORTSC1_CCS_SHIFT (0U) +#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) +#define USB_PORTSC1_CSC_MASK (0x2U) +#define USB_PORTSC1_CSC_SHIFT (1U) +#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) +#define USB_PORTSC1_PE_MASK (0x4U) +#define USB_PORTSC1_PE_SHIFT (2U) +#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) +#define USB_PORTSC1_PEC_MASK (0x8U) +#define USB_PORTSC1_PEC_SHIFT (3U) +#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) +#define USB_PORTSC1_OCA_MASK (0x10U) +#define USB_PORTSC1_OCA_SHIFT (4U) +#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) +#define USB_PORTSC1_OCC_MASK (0x20U) +#define USB_PORTSC1_OCC_SHIFT (5U) +#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) +#define USB_PORTSC1_FPR_MASK (0x40U) +#define USB_PORTSC1_FPR_SHIFT (6U) +#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) +#define USB_PORTSC1_SUSP_MASK (0x80U) +#define USB_PORTSC1_SUSP_SHIFT (7U) +#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) +#define USB_PORTSC1_PR_MASK (0x100U) +#define USB_PORTSC1_PR_SHIFT (8U) +#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) +#define USB_PORTSC1_HSP_MASK (0x200U) +#define USB_PORTSC1_HSP_SHIFT (9U) +#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) +#define USB_PORTSC1_LS_MASK (0xC00U) +#define USB_PORTSC1_LS_SHIFT (10U) +#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) +#define USB_PORTSC1_PP_MASK (0x1000U) +#define USB_PORTSC1_PP_SHIFT (12U) +#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) +#define USB_PORTSC1_PO_MASK (0x2000U) +#define USB_PORTSC1_PO_SHIFT (13U) +#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) +#define USB_PORTSC1_PIC_MASK (0xC000U) +#define USB_PORTSC1_PIC_SHIFT (14U) +#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) +#define USB_PORTSC1_PTC_MASK (0xF0000U) +#define USB_PORTSC1_PTC_SHIFT (16U) +#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) +#define USB_PORTSC1_WKCN_MASK (0x100000U) +#define USB_PORTSC1_WKCN_SHIFT (20U) +#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) +#define USB_PORTSC1_WKDC_MASK (0x200000U) +#define USB_PORTSC1_WKDC_SHIFT (21U) +#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) +#define USB_PORTSC1_WKOC_MASK (0x400000U) +#define USB_PORTSC1_WKOC_SHIFT (22U) +#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) +#define USB_PORTSC1_PHCD_MASK (0x800000U) +#define USB_PORTSC1_PHCD_SHIFT (23U) +#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) +#define USB_PORTSC1_PFSC_MASK (0x1000000U) +#define USB_PORTSC1_PFSC_SHIFT (24U) +#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) +#define USB_PORTSC1_PTS_2_MASK (0x2000000U) +#define USB_PORTSC1_PTS_2_SHIFT (25U) +#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) +#define USB_PORTSC1_PSPD_MASK (0xC000000U) +#define USB_PORTSC1_PSPD_SHIFT (26U) +#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) +#define USB_PORTSC1_PTW_MASK (0x10000000U) +#define USB_PORTSC1_PTW_SHIFT (28U) +#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) +#define USB_PORTSC1_STS_MASK (0x20000000U) +#define USB_PORTSC1_STS_SHIFT (29U) +#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) +#define USB_PORTSC1_PTS_1_MASK (0xC0000000U) +#define USB_PORTSC1_PTS_1_SHIFT (30U) +#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) + +/*! @name OTGSC - On-The-Go Status & control */ +#define USB_OTGSC_VD_MASK (0x1U) +#define USB_OTGSC_VD_SHIFT (0U) +#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) +#define USB_OTGSC_VC_MASK (0x2U) +#define USB_OTGSC_VC_SHIFT (1U) +#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) +#define USB_OTGSC_OT_MASK (0x8U) +#define USB_OTGSC_OT_SHIFT (3U) +#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) +#define USB_OTGSC_DP_MASK (0x10U) +#define USB_OTGSC_DP_SHIFT (4U) +#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) +#define USB_OTGSC_IDPU_MASK (0x20U) +#define USB_OTGSC_IDPU_SHIFT (5U) +#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) +#define USB_OTGSC_ID_MASK (0x100U) +#define USB_OTGSC_ID_SHIFT (8U) +#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) +#define USB_OTGSC_AVV_MASK (0x200U) +#define USB_OTGSC_AVV_SHIFT (9U) +#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) +#define USB_OTGSC_ASV_MASK (0x400U) +#define USB_OTGSC_ASV_SHIFT (10U) +#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) +#define USB_OTGSC_BSV_MASK (0x800U) +#define USB_OTGSC_BSV_SHIFT (11U) +#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) +#define USB_OTGSC_BSE_MASK (0x1000U) +#define USB_OTGSC_BSE_SHIFT (12U) +#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) +#define USB_OTGSC_TOG_1MS_MASK (0x2000U) +#define USB_OTGSC_TOG_1MS_SHIFT (13U) +#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) +#define USB_OTGSC_DPS_MASK (0x4000U) +#define USB_OTGSC_DPS_SHIFT (14U) +#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) +#define USB_OTGSC_IDIS_MASK (0x10000U) +#define USB_OTGSC_IDIS_SHIFT (16U) +#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) +#define USB_OTGSC_AVVIS_MASK (0x20000U) +#define USB_OTGSC_AVVIS_SHIFT (17U) +#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) +#define USB_OTGSC_ASVIS_MASK (0x40000U) +#define USB_OTGSC_ASVIS_SHIFT (18U) +#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) +#define USB_OTGSC_BSVIS_MASK (0x80000U) +#define USB_OTGSC_BSVIS_SHIFT (19U) +#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) +#define USB_OTGSC_BSEIS_MASK (0x100000U) +#define USB_OTGSC_BSEIS_SHIFT (20U) +#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) +#define USB_OTGSC_STATUS_1MS_MASK (0x200000U) +#define USB_OTGSC_STATUS_1MS_SHIFT (21U) +#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) +#define USB_OTGSC_DPIS_MASK (0x400000U) +#define USB_OTGSC_DPIS_SHIFT (22U) +#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) +#define USB_OTGSC_IDIE_MASK (0x1000000U) +#define USB_OTGSC_IDIE_SHIFT (24U) +#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) +#define USB_OTGSC_AVVIE_MASK (0x2000000U) +#define USB_OTGSC_AVVIE_SHIFT (25U) +#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) +#define USB_OTGSC_ASVIE_MASK (0x4000000U) +#define USB_OTGSC_ASVIE_SHIFT (26U) +#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) +#define USB_OTGSC_BSVIE_MASK (0x8000000U) +#define USB_OTGSC_BSVIE_SHIFT (27U) +#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) +#define USB_OTGSC_BSEIE_MASK (0x10000000U) +#define USB_OTGSC_BSEIE_SHIFT (28U) +#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) +#define USB_OTGSC_EN_1MS_MASK (0x20000000U) +#define USB_OTGSC_EN_1MS_SHIFT (29U) +#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) +#define USB_OTGSC_DPIE_MASK (0x40000000U) +#define USB_OTGSC_DPIE_SHIFT (30U) +#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) + +/*! @name USBMODE - USB Device Mode */ +#define USB_USBMODE_CM_MASK (0x3U) +#define USB_USBMODE_CM_SHIFT (0U) +#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) +#define USB_USBMODE_ES_MASK (0x4U) +#define USB_USBMODE_ES_SHIFT (2U) +#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) +#define USB_USBMODE_SLOM_MASK (0x8U) +#define USB_USBMODE_SLOM_SHIFT (3U) +#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) +#define USB_USBMODE_SDIS_MASK (0x10U) +#define USB_USBMODE_SDIS_SHIFT (4U) +#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) + +/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) + +/*! @name ENDPTPRIME - Endpoint Prime */ +#define USB_ENDPTPRIME_PERB_MASK (0xFFU) +#define USB_ENDPTPRIME_PERB_SHIFT (0U) +#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) +#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) +#define USB_ENDPTPRIME_PETB_SHIFT (16U) +#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) + +/*! @name ENDPTFLUSH - Endpoint Flush */ +#define USB_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USB_ENDPTFLUSH_FERB_SHIFT (0U) +#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) +#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) +#define USB_ENDPTFLUSH_FETB_SHIFT (16U) +#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) + +/*! @name ENDPTSTAT - Endpoint Status */ +#define USB_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USB_ENDPTSTAT_ERBR_SHIFT (0U) +#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) +#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) +#define USB_ENDPTSTAT_ETBR_SHIFT (16U) +#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) + +/*! @name ENDPTCOMPLETE - Endpoint Complete */ +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) +#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) + +/*! @name ENDPTCTRL0 - Endpoint Control0 */ +#define USB_ENDPTCTRL0_RXS_MASK (0x1U) +#define USB_ENDPTCTRL0_RXS_SHIFT (0U) +#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) +#define USB_ENDPTCTRL0_RXT_MASK (0xCU) +#define USB_ENDPTCTRL0_RXT_SHIFT (2U) +#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) +#define USB_ENDPTCTRL0_RXE_MASK (0x80U) +#define USB_ENDPTCTRL0_RXE_SHIFT (7U) +#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) +#define USB_ENDPTCTRL0_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL0_TXS_SHIFT (16U) +#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) +#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL0_TXT_SHIFT (18U) +#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) +#define USB_ENDPTCTRL0_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL0_TXE_SHIFT (23U) +#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) + +/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +#define USB_ENDPTCTRL_RXS_MASK (0x1U) +#define USB_ENDPTCTRL_RXS_SHIFT (0U) +#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) +#define USB_ENDPTCTRL_RXD_MASK (0x2U) +#define USB_ENDPTCTRL_RXD_SHIFT (1U) +#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) +#define USB_ENDPTCTRL_RXT_MASK (0xCU) +#define USB_ENDPTCTRL_RXT_SHIFT (2U) +#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) +#define USB_ENDPTCTRL_RXI_MASK (0x20U) +#define USB_ENDPTCTRL_RXI_SHIFT (5U) +#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) +#define USB_ENDPTCTRL_RXR_MASK (0x40U) +#define USB_ENDPTCTRL_RXR_SHIFT (6U) +#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) +#define USB_ENDPTCTRL_RXE_MASK (0x80U) +#define USB_ENDPTCTRL_RXE_SHIFT (7U) +#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) +#define USB_ENDPTCTRL_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL_TXS_SHIFT (16U) +#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) +#define USB_ENDPTCTRL_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL_TXD_SHIFT (17U) +#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) +#define USB_ENDPTCTRL_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL_TXT_SHIFT (18U) +#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) +#define USB_ENDPTCTRL_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL_TXI_SHIFT (21U) +#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) +#define USB_ENDPTCTRL_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL_TXR_SHIFT (22U) +#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) +#define USB_ENDPTCTRL_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL_TXE_SHIFT (23U) +#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) + +/* The count of USB_ENDPTCTRL */ +#define USB_ENDPTCTRL_COUNT (7U) + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB1 base address */ +#define USB1_BASE (0x2184000u) +/** Peripheral USB1 base pointer */ +#define USB1 ((USB_Type *)USB1_BASE) +/** Peripheral USB2 base address */ +#define USB2_BASE (0x2184200u) +/** Peripheral USB2 base pointer */ +#define USB2 ((USB_Type *)USB2_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn } +/* Backward compatibility */ +#define GPTIMER0CTL GPTIMER0CTRL +#define GPTIMER1CTL GPTIMER1CTRL +#define USB_SBUSCFG SBUSCFG +#define EPLISTADDR ENDPTLISTADDR +#define EPSETUPSR ENDPTSETUPSTAT +#define EPPRIME ENDPTPRIME +#define EPFLUSH ENDPTFLUSH +#define EPSR ENDPTSTAT +#define EPCOMPLETE ENDPTCOMPLETE +#define EPCR ENDPTCTRL +#define EPCR0 ENDPTCTRL0 +#define USBHS_ID_ID_MASK USB_ID_ID_MASK +#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT +#define USBHS_ID_ID(x) USB_ID_ID(x) +#define USBHS_ID_NID_MASK USB_ID_NID_MASK +#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT +#define USBHS_ID_NID(x) USB_ID_NID(x) +#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK +#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT +#define USBHS_ID_REVISION(x) USB_ID_REVISION(x) +#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK +#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT +#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x) +#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK +#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT +#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x) +#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK +#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT +#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x) +#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK +#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT +#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x) +#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK +#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT +#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x) +#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK +#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT +#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x) +#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK +#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT +#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x) +#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK +#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT +#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x) +#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK +#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT +#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x) +#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK +#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT +#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x) +#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK +#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT +#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x) +#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK +#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT +#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x) +#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK +#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x) +#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK +#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x) +#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK +#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x) +#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK +#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x) +#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK +#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT +#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x) +#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK +#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x) +#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK +#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x) +#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK +#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x) +#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK +#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x) +#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK +#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT +#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x) +#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x) +#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK +#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT +#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x) +#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK +#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT +#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x) +#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK +#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT +#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x) +#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK +#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT +#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x) +#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK +#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT +#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x) +#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK +#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT +#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x) +#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK +#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT +#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x) +#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK +#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT +#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x) +#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK +#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT +#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x) +#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK +#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT +#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x) +#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK +#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT +#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x) +#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK +#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT +#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x) +#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK +#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT +#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x) +#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK +#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT +#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x) +#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK +#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT +#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x) +#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK +#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT +#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x) +#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK +#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT +#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x) +#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK +#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT +#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x) +#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK +#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT +#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x) +#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK +#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT +#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x) +#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK +#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT +#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x) +#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK +#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT +#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x) +#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK +#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT +#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x) +#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK +#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT +#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x) +#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK +#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT +#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x) +#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK +#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT +#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x) +#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK +#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT +#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x) +#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK +#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT +#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x) +#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK +#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT +#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x) +#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK +#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT +#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x) +#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK +#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT +#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x) +#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK +#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT +#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x) +#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK +#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT +#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x) +#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK +#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT +#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x) +#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK +#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT +#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x) +#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK +#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT +#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x) +#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK +#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT +#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x) +#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK +#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT +#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x) +#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK +#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT +#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x) +#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK +#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT +#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x) +#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK +#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT +#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x) +#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK +#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT +#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x) +#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK +#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT +#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x) +#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK +#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT +#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x) +#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK +#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT +#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x) +#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK +#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT +#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x) +#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK +#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT +#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x) +#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK +#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT +#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x) +#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK +#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT +#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x) +#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK +#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT +#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x) +#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK +#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT +#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x) +#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK +#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT +#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x) +#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK +#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT +#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x) +#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK +#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT +#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x) +#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK +#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT +#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x) +#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK +#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT +#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x) +#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK +#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT +#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x) +#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK +#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT +#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x) +#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK +#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT +#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x) +#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK +#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT +#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x) +#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK +#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT +#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x) +#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK +#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT +#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x) +#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK +#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT +#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x) +#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK +#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT +#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x) +#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK +#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT +#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x) +#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK +#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT +#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x) +#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK +#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT +#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x) +#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK +#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT +#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x) +#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK +#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT +#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x) +#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK +#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x) +#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK +#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x) +#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK +#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT +#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x) +#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK +#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT +#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x) +#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK +#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT +#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x) +#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK +#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT +#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x) +#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK +#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT +#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x) +#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK +#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT +#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x) +#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK +#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT +#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x) +#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK +#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT +#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x) +#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK +#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT +#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x) +#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK +#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT +#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x) +#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK +#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT +#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x) +#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK +#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT +#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x) +#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK +#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT +#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x) +#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK +#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT +#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x) +#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK +#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT +#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x) +#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK +#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT +#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x) +#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK +#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT +#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x) +#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK +#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT +#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x) +#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK +#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT +#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x) +#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK +#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT +#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x) +#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK +#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT +#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x) +#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK +#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT +#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x) +#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK +#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT +#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x) +#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK +#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT +#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x) +#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK +#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT +#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x) +#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK +#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT +#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x) +#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK +#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT +#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x) +#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK +#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT +#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x) +#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK +#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT +#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x) +#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK +#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT +#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x) +#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK +#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT +#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x) +#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK +#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT +#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x) +#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK +#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT +#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x) +#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK +#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT +#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x) +#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK +#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT +#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x) +#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK +#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT +#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x) +#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK +#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT +#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x) +#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK +#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT +#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x) +#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK +#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT +#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x) +#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK +#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT +#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x) +#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK +#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT +#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x) +#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK +#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT +#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x) +#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK +#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT +#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x) +#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK +#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT +#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x) +#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK +#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT +#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x) +#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK +#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT +#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x) +#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK +#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT +#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x) +#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK +#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT +#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x) +#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK +#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT +#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x) +#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK +#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT +#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x) +#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK +#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT +#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x) +#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK +#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT +#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x) +#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK +#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT +#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x) +#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK +#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT +#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x) +#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK +#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT +#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x) +#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK +#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT +#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x) +#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK +#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT +#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x) +#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK +#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT +#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x) +#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK +#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT +#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x) +#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK +#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT +#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x) +#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK +#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT +#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x) +#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK +#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT +#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) +#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK +#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT +#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x) +#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK +#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT +#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x) +#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK +#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT +#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x) +#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK +#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT +#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x) +#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK +#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT +#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x) +#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK +#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT +#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x) +#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK +#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT +#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x) +#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK +#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT +#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x) +#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK +#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT +#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x) +#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK +#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT +#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x) +#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK +#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT +#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x) +#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK +#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT +#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x) +#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK +#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT +#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x) +#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK +#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT +#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x) +#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK +#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT +#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x) +#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK +#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT +#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x) +#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK +#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT +#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x) +#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK +#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT +#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x) +#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK +#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT +#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x) +#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK +#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT +#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x) +#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK +#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT +#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x) +#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK +#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT +#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x) +#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK +#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT +#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x) +#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK +#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT +#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x) +#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK +#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT +#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x) +#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK +#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT +#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x) +#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT +#define USBHS_Type USB_Type +#define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE } +#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn } + + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + __IO uint32_t USB_OTGn_CTRL; /**< USB OTGn Control Register, offset: 0x0 */ + uint8_t RESERVED_0[20]; + __IO uint32_t USB_OTGn_PHY_CTRL_0; /**< OTGn UTMI PHY Control 0 Register, offset: 0x18 */ +} USBNC_Type; + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/*! @name USB_OTGn_CTRL - USB OTGn Control Register */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U) +#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U) +#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U) +#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U) +#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U) +#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U) +#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK) + +/*! @name USB_OTGn_PHY_CTRL_0 - OTGn UTMI PHY Control 0 Register */ +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U) +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) + + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +/** Peripheral USBNC1 base address */ +#define USBNC1_BASE (0x2184800u) +/** Peripheral USBNC1 base pointer */ +#define USBNC1 ((USBNC_Type *)USBNC1_BASE) +/** Peripheral USBNC2 base address */ +#define USBNC2_BASE (0x2184804u) +/** Peripheral USBNC2 base pointer */ +#define USBNC2 ((USBNC_Type *)USBNC2_BASE) +/** Array initializer of USBNC peripheral base addresses */ +#define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE } +/** Array initializer of USBNC peripheral base pointers */ +#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 } + +/*! + * @} + */ /* end of group USBNC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */ + __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ + __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ + __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ + __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ + __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ + __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ + __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ + __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +#define USBPHY_PWD_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_RSVD0_SHIFT (0U) +#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK) +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) +#define USBPHY_PWD_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_RSVD1_SHIFT (13U) +#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK) +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +#define USBPHY_PWD_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_RSVD2_SHIFT (21U) +#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK) + +/*! @name PWD_SET - USB PHY Power-Down Register */ +#define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_SET_RSVD0_SHIFT (0U) +#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK) +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) +#define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_SET_RSVD1_SHIFT (13U) +#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK) +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +#define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_SET_RSVD2_SHIFT (21U) +#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK) + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +#define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_CLR_RSVD0_SHIFT (0U) +#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK) +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) +#define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_CLR_RSVD1_SHIFT (13U) +#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK) +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +#define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_CLR_RSVD2_SHIFT (21U) +#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK) + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +#define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_TOG_RSVD0_SHIFT (0U) +#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK) +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) +#define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_TOG_RSVD1_SHIFT (13U) +#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK) +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +#define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_TOG_RSVD2_SHIFT (21U) +#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK) + +/*! @name TX - USB PHY Transmitter Control Register */ +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) +#define USBPHY_TX_RSVD0_MASK (0xF0U) +#define USBPHY_TX_RSVD0_SHIFT (4U) +#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK) +#define USBPHY_TX_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) +#define USBPHY_TX_RSVD1_MASK (0xF000U) +#define USBPHY_TX_RSVD1_SHIFT (12U) +#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK) +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +#define USBPHY_TX_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_RSVD2_SHIFT (20U) +#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_RSVD5_SHIFT (29U) +#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK) + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) +#define USBPHY_TX_SET_RSVD0_MASK (0xF0U) +#define USBPHY_TX_SET_RSVD0_SHIFT (4U) +#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK) +#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) +#define USBPHY_TX_SET_RSVD1_MASK (0xF000U) +#define USBPHY_TX_SET_RSVD1_SHIFT (12U) +#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK) +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +#define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_SET_RSVD2_SHIFT (20U) +#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_SET_RSVD5_SHIFT (29U) +#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK) + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) +#define USBPHY_TX_CLR_RSVD0_MASK (0xF0U) +#define USBPHY_TX_CLR_RSVD0_SHIFT (4U) +#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK) +#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) +#define USBPHY_TX_CLR_RSVD1_MASK (0xF000U) +#define USBPHY_TX_CLR_RSVD1_SHIFT (12U) +#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK) +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +#define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_CLR_RSVD2_SHIFT (20U) +#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_CLR_RSVD5_SHIFT (29U) +#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK) + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) +#define USBPHY_TX_TOG_RSVD0_MASK (0xF0U) +#define USBPHY_TX_TOG_RSVD0_SHIFT (4U) +#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK) +#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) +#define USBPHY_TX_TOG_RSVD1_MASK (0xF000U) +#define USBPHY_TX_TOG_RSVD1_SHIFT (12U) +#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK) +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +#define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_TOG_RSVD2_SHIFT (20U) +#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_TOG_RSVD5_SHIFT (29U) +#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK) + +/*! @name RX - USB PHY Receiver Control Register */ +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) +#define USBPHY_RX_RSVD0_MASK (0x8U) +#define USBPHY_RX_RSVD0_SHIFT (3U) +#define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK) +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +#define USBPHY_RX_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_RSVD1_SHIFT (7U) +#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK) +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +#define USBPHY_RX_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_RSVD2_SHIFT (23U) +#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK) + +/*! @name RX_SET - USB PHY Receiver Control Register */ +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) +#define USBPHY_RX_SET_RSVD0_MASK (0x8U) +#define USBPHY_RX_SET_RSVD0_SHIFT (3U) +#define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK) +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +#define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_SET_RSVD1_SHIFT (7U) +#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK) +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +#define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_SET_RSVD2_SHIFT (23U) +#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK) + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) +#define USBPHY_RX_CLR_RSVD0_MASK (0x8U) +#define USBPHY_RX_CLR_RSVD0_SHIFT (3U) +#define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK) +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +#define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_CLR_RSVD1_SHIFT (7U) +#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK) +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +#define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_CLR_RSVD2_SHIFT (23U) +#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK) + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) +#define USBPHY_RX_TOG_RSVD0_MASK (0x8U) +#define USBPHY_RX_TOG_RSVD0_SHIFT (3U) +#define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK) +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +#define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_TOG_RSVD1_SHIFT (7U) +#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK) +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +#define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_TOG_RSVD2_SHIFT (23U) +#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK) + +/*! @name CTRL - USB PHY General Control Register */ +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK) +#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - USB PHY General Control Register */ +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_SET_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - USB PHY General Control Register */ +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - USB PHY General Control Register */ +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) + +/*! @name STATUS - USB PHY Status Register */ +#define USBPHY_STATUS_RSVD0_MASK (0x7U) +#define USBPHY_STATUS_RSVD0_SHIFT (0U) +#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) +#define USBPHY_STATUS_RSVD1_MASK (0x30U) +#define USBPHY_STATUS_RSVD1_SHIFT (4U) +#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) +#define USBPHY_STATUS_RSVD2_MASK (0x80U) +#define USBPHY_STATUS_RSVD2_SHIFT (7U) +#define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK) +#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) +#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) +#define USBPHY_STATUS_RSVD3_MASK (0x200U) +#define USBPHY_STATUS_RSVD3_SHIFT (9U) +#define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK) +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +#define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U) +#define USBPHY_STATUS_RSVD4_SHIFT (11U) +#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK) + +/*! @name DEBUG - USB PHY Debug Register */ +#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK) +#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK) +#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK) +#define USBPHY_DEBUG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK) + +/*! @name DEBUG_SET - USB PHY Debug Register */ +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK) +#define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK) + +/*! @name DEBUG_CLR - USB PHY Debug Register */ +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK) +#define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK) + +/*! @name DEBUG_TOG - USB PHY Debug Register */ +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK) +#define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK) + +/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */ +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) + +/*! @name DEBUG1 - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK) +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK) + +/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK) + +/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK) + +/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK) + +/*! @name VERSION - UTMI RTL Version */ +#define USBPHY_VERSION_STEP_MASK (0xFFFFU) +#define USBPHY_VERSION_STEP_SHIFT (0U) +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) +#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) +#define USBPHY_VERSION_MINOR_SHIFT (16U) +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) +#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) +#define USBPHY_VERSION_MAJOR_SHIFT (24U) +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +/** Peripheral USBPHY1 base address */ +#define USBPHY1_BASE (0x20C9000u) +/** Peripheral USBPHY1 base pointer */ +#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) +/** Peripheral USBPHY2 base address */ +#define USBPHY2_BASE (0x20CA000u) +/** Peripheral USBPHY2 base pointer */ +#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) +/** Array initializer of USBPHY peripheral base addresses */ +#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE } +/** Array initializer of USBPHY peripheral base pointers */ +#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 } +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer + * @{ + */ + +/** USB_ANALOG - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT; /**< USB VBUS Detect Register, array offset: 0x0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_SET; /**< USB VBUS Detect Register, array offset: 0x4, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_CLR; /**< USB VBUS Detect Register, array offset: 0x8, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_TOG; /**< USB VBUS Detect Register, array offset: 0xC, array step: 0x60 */ + __IO uint32_t CHRG_DETECT; /**< USB Charger Detect Register, array offset: 0x10, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_SET; /**< USB Charger Detect Register, array offset: 0x14, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_CLR; /**< USB Charger Detect Register, array offset: 0x18, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_TOG; /**< USB Charger Detect Register, array offset: 0x1C, array step: 0x60 */ + __I uint32_t VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, array offset: 0x20, array step: 0x60 */ + uint8_t RESERVED_0[12]; + __I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x30, array step: 0x60 */ + uint8_t RESERVED_1[28]; + __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x50, array step: 0x60 */ + __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x54, array step: 0x60 */ + __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x58, array step: 0x60 */ + __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x5C, array step: 0x60 */ + } INSTANCE[2]; + __I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0xC0 */ +} USB_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks + * @{ + */ + +/*! @name VBUS_DETECT - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT */ +#define USB_ANALOG_VBUS_DETECT_COUNT (2U) + +/*! @name VBUS_DETECT_SET - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_SET */ +#define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U) + +/*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_CLR */ +#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U) + +/*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_TOG */ +#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U) + +/*! @name CHRG_DETECT - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT */ +#define USB_ANALOG_CHRG_DETECT_COUNT (2U) + +/*! @name CHRG_DETECT_SET - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_SET */ +#define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U) + +/*! @name CHRG_DETECT_CLR - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_CLR */ +#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U) + +/*! @name CHRG_DETECT_TOG - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_TOG */ +#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U) + +/*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */ +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_STAT */ +#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U) + +/*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */ +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U) +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U) +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_STAT */ +#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U) + +/*! @name MISC - USB Misc Register */ +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC */ +#define USB_ANALOG_MISC_COUNT (2U) + +/*! @name MISC_SET - USB Misc Register */ +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC_SET */ +#define USB_ANALOG_MISC_SET_COUNT (2U) + +/*! @name MISC_CLR - USB Misc Register */ +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC_CLR */ +#define USB_ANALOG_MISC_CLR_COUNT (2U) + +/*! @name MISC_TOG - USB Misc Register */ +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC_TOG */ +#define USB_ANALOG_MISC_TOG_COUNT (2U) + +/*! @name DIGPROG - Chip Silicon Version */ +#define USB_ANALOG_DIGPROG_MINOR_MASK (0xFFU) +#define USB_ANALOG_DIGPROG_MINOR_SHIFT (0U) +#define USB_ANALOG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MINOR_SHIFT)) & USB_ANALOG_DIGPROG_MINOR_MASK) +#define USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U) +#define USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT (8U) +#define USB_ANALOG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK) +#define USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U) +#define USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT (16U) +#define USB_ANALOG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK) + + +/*! + * @} + */ /* end of group USB_ANALOG_Register_Masks */ + + +/* USB_ANALOG - Peripheral instance base addresses */ +/** Peripheral USB_ANALOG base address */ +#define USB_ANALOG_BASE (0x20C81A0u) +/** Peripheral USB_ANALOG base pointer */ +#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE) +/** Array initializer of USB_ANALOG peripheral base addresses */ +#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE } +/** Array initializer of USB_ANALOG peripheral base pointers */ +#define USB_ANALOG_BASE_PTRS { USB_ANALOG } + +/*! + * @} + */ /* end of group USB_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USDHC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer + * @{ + */ + +/** USDHC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ + __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ + __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ + __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ + __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ + __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ + __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ + __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ + __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ + __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ + __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ + __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ + __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ + __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ + __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ + __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ + __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ + __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ + __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ + __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ + __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ + __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ + __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ + uint8_t RESERVED_2[84]; + __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ + __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ + __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ + __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ +} USDHC_Type; + +/* ---------------------------------------------------------------------------- + -- USDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Register_Masks USDHC Register Masks + * @{ + */ + +/*! @name DS_ADDR - DMA System Address */ +#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) +#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) +#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) + +/*! @name BLK_ATT - Block Attributes */ +#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) +#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) +#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) +#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) +#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) +#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) + +/*! @name CMD_ARG - Command Argument */ +#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) +#define USDHC_CMD_ARG_CMDARG_SHIFT (0U) +#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) + +/*! @name CMD_XFR_TYP - Command Transfer Type */ +#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) +#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) +#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) +#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) +#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) +#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) +#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) +#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) +#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) +#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) +#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) +#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) +#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) +#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) +#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) +#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) +#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) +#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) + +/*! @name CMD_RSP0 - Command Response0 */ +#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) +#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) + +/*! @name CMD_RSP1 - Command Response1 */ +#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) +#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) + +/*! @name CMD_RSP2 - Command Response2 */ +#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) +#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) + +/*! @name CMD_RSP3 - Command Response3 */ +#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) +#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) + +/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) + +/*! @name PRES_STATE - Present State */ +#define USDHC_PRES_STATE_CIHB_MASK (0x1U) +#define USDHC_PRES_STATE_CIHB_SHIFT (0U) +#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) +#define USDHC_PRES_STATE_CDIHB_MASK (0x2U) +#define USDHC_PRES_STATE_CDIHB_SHIFT (1U) +#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) +#define USDHC_PRES_STATE_DLA_MASK (0x4U) +#define USDHC_PRES_STATE_DLA_SHIFT (2U) +#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) +#define USDHC_PRES_STATE_SDSTB_MASK (0x8U) +#define USDHC_PRES_STATE_SDSTB_SHIFT (3U) +#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) +#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) +#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) +#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) +#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) +#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) +#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) +#define USDHC_PRES_STATE_PEROFF_MASK (0x40U) +#define USDHC_PRES_STATE_PEROFF_SHIFT (6U) +#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) +#define USDHC_PRES_STATE_SDOFF_MASK (0x80U) +#define USDHC_PRES_STATE_SDOFF_SHIFT (7U) +#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) +#define USDHC_PRES_STATE_WTA_MASK (0x100U) +#define USDHC_PRES_STATE_WTA_SHIFT (8U) +#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) +#define USDHC_PRES_STATE_RTA_MASK (0x200U) +#define USDHC_PRES_STATE_RTA_SHIFT (9U) +#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) +#define USDHC_PRES_STATE_BWEN_MASK (0x400U) +#define USDHC_PRES_STATE_BWEN_SHIFT (10U) +#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) +#define USDHC_PRES_STATE_BREN_MASK (0x800U) +#define USDHC_PRES_STATE_BREN_SHIFT (11U) +#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) +#define USDHC_PRES_STATE_RTR_MASK (0x1000U) +#define USDHC_PRES_STATE_RTR_SHIFT (12U) +#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) +#define USDHC_PRES_STATE_TSCD_MASK (0x8000U) +#define USDHC_PRES_STATE_TSCD_SHIFT (15U) +#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) +#define USDHC_PRES_STATE_CINST_MASK (0x10000U) +#define USDHC_PRES_STATE_CINST_SHIFT (16U) +#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) +#define USDHC_PRES_STATE_CDPL_MASK (0x40000U) +#define USDHC_PRES_STATE_CDPL_SHIFT (18U) +#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) +#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) +#define USDHC_PRES_STATE_WPSPL_SHIFT (19U) +#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) +#define USDHC_PRES_STATE_CLSL_MASK (0x800000U) +#define USDHC_PRES_STATE_CLSL_SHIFT (23U) +#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) +#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) +#define USDHC_PRES_STATE_DLSL_SHIFT (24U) +#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) + +/*! @name PROT_CTRL - Protocol Control */ +#define USDHC_PROT_CTRL_LCTL_MASK (0x1U) +#define USDHC_PROT_CTRL_LCTL_SHIFT (0U) +#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) +#define USDHC_PROT_CTRL_DTW_MASK (0x6U) +#define USDHC_PROT_CTRL_DTW_SHIFT (1U) +#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) +#define USDHC_PROT_CTRL_D3CD_MASK (0x8U) +#define USDHC_PROT_CTRL_D3CD_SHIFT (3U) +#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) +#define USDHC_PROT_CTRL_EMODE_MASK (0x30U) +#define USDHC_PROT_CTRL_EMODE_SHIFT (4U) +#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) +#define USDHC_PROT_CTRL_CDTL_MASK (0x40U) +#define USDHC_PROT_CTRL_CDTL_SHIFT (6U) +#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) +#define USDHC_PROT_CTRL_CDSS_MASK (0x80U) +#define USDHC_PROT_CTRL_CDSS_SHIFT (7U) +#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) +#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) +#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) +#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) +#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) +#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) +#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) +#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) +#define USDHC_PROT_CTRL_CREQ_SHIFT (17U) +#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) +#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) +#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) +#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) +#define USDHC_PROT_CTRL_IABG_MASK (0x80000U) +#define USDHC_PROT_CTRL_IABG_SHIFT (19U) +#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) +#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) +#define USDHC_PROT_CTRL_WECINT_SHIFT (24U) +#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) +#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) +#define USDHC_PROT_CTRL_WECINS_SHIFT (25U) +#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) +#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) +#define USDHC_PROT_CTRL_WECRM_SHIFT (26U) +#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) +#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) +#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) +#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) + +/*! @name SYS_CTRL - System Control */ +#define USDHC_SYS_CTRL_DVS_MASK (0xF0U) +#define USDHC_SYS_CTRL_DVS_SHIFT (4U) +#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) +#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) +#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) +#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) +#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) +#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) +#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) +#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) +#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) +#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) +#define USDHC_SYS_CTRL_RSTA_SHIFT (24U) +#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) +#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) +#define USDHC_SYS_CTRL_RSTC_SHIFT (25U) +#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) +#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) +#define USDHC_SYS_CTRL_RSTD_SHIFT (26U) +#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) +#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) +#define USDHC_SYS_CTRL_INITA_SHIFT (27U) +#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) +#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) +#define USDHC_SYS_CTRL_RSTT_SHIFT (28U) +#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) + +/*! @name INT_STATUS - Interrupt Status */ +#define USDHC_INT_STATUS_CC_MASK (0x1U) +#define USDHC_INT_STATUS_CC_SHIFT (0U) +#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) +#define USDHC_INT_STATUS_TC_MASK (0x2U) +#define USDHC_INT_STATUS_TC_SHIFT (1U) +#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) +#define USDHC_INT_STATUS_BGE_MASK (0x4U) +#define USDHC_INT_STATUS_BGE_SHIFT (2U) +#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) +#define USDHC_INT_STATUS_DINT_MASK (0x8U) +#define USDHC_INT_STATUS_DINT_SHIFT (3U) +#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) +#define USDHC_INT_STATUS_BWR_MASK (0x10U) +#define USDHC_INT_STATUS_BWR_SHIFT (4U) +#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) +#define USDHC_INT_STATUS_BRR_MASK (0x20U) +#define USDHC_INT_STATUS_BRR_SHIFT (5U) +#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) +#define USDHC_INT_STATUS_CINS_MASK (0x40U) +#define USDHC_INT_STATUS_CINS_SHIFT (6U) +#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) +#define USDHC_INT_STATUS_CRM_MASK (0x80U) +#define USDHC_INT_STATUS_CRM_SHIFT (7U) +#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) +#define USDHC_INT_STATUS_CINT_MASK (0x100U) +#define USDHC_INT_STATUS_CINT_SHIFT (8U) +#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) +#define USDHC_INT_STATUS_RTE_MASK (0x1000U) +#define USDHC_INT_STATUS_RTE_SHIFT (12U) +#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) +#define USDHC_INT_STATUS_TP_MASK (0x4000U) +#define USDHC_INT_STATUS_TP_SHIFT (14U) +#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) +#define USDHC_INT_STATUS_CTOE_MASK (0x10000U) +#define USDHC_INT_STATUS_CTOE_SHIFT (16U) +#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) +#define USDHC_INT_STATUS_CCE_MASK (0x20000U) +#define USDHC_INT_STATUS_CCE_SHIFT (17U) +#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) +#define USDHC_INT_STATUS_CEBE_MASK (0x40000U) +#define USDHC_INT_STATUS_CEBE_SHIFT (18U) +#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) +#define USDHC_INT_STATUS_CIE_MASK (0x80000U) +#define USDHC_INT_STATUS_CIE_SHIFT (19U) +#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) +#define USDHC_INT_STATUS_DTOE_MASK (0x100000U) +#define USDHC_INT_STATUS_DTOE_SHIFT (20U) +#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) +#define USDHC_INT_STATUS_DCE_MASK (0x200000U) +#define USDHC_INT_STATUS_DCE_SHIFT (21U) +#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) +#define USDHC_INT_STATUS_DEBE_MASK (0x400000U) +#define USDHC_INT_STATUS_DEBE_SHIFT (22U) +#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) +#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) +#define USDHC_INT_STATUS_AC12E_SHIFT (24U) +#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) +#define USDHC_INT_STATUS_TNE_MASK (0x4000000U) +#define USDHC_INT_STATUS_TNE_SHIFT (26U) +#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) +#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) +#define USDHC_INT_STATUS_DMAE_SHIFT (28U) +#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) + +/*! @name INT_STATUS_EN - Interrupt Status Enable */ +#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) +#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) +#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) +#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) +#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) +#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) +#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) +#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) +#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) +#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) +#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) +#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) +#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) +#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) +#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) +#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) +#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) +#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) +#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) +#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) +#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) +#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) +#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) +#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) +#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) +#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) +#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) +#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) +#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) +#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) +#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) +#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) +#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) +#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) +#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) +#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) +#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) +#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) +#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) +#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) +#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) +#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) +#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) +#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) +#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) +#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) +#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) +#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) +#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) +#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) +#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) +#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) +#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) +#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) +#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) +#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) +#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) +#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) +#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) +#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) +#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) +#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) +#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) + +/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ +#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) +#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) +#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) +#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) +#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) +#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) +#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) +#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) +#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) +#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) +#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) +#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) +#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) +#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) +#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) +#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) +#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) +#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) +#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) +#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) +#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) +#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) +#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) +#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) +#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) +#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) +#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) +#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) +#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) +#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) +#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) + +/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) + +/*! @name HOST_CTRL_CAP - Host Controller Capabilities */ +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) +#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) +#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) +#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) +#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) +#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) +#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) +#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) +#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) +#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) +#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) +#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) +#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) +#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) +#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) +#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) +#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) +#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) +#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) +#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) +#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) +#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) +#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) +#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) +#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) + +/*! @name WTMK_LVL - Watermark Level */ +#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) +#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) +#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) +#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) +#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) +#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) +#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) +#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) +#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) +#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) +#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) +#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) + +/*! @name MIX_CTRL - Mixer Control */ +#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) +#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) +#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) +#define USDHC_MIX_CTRL_BCEN_MASK (0x2U) +#define USDHC_MIX_CTRL_BCEN_SHIFT (1U) +#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) +#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) +#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) +#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) +#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) +#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) +#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) +#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) +#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) +#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) +#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) +#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) +#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) +#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) +#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) +#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) +#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) +#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) +#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) +#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) +#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) +#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) +#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) +#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) +#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) + +/*! @name FORCE_EVENT - Force Event */ +#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) +#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) +#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) +#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) +#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) +#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) +#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) +#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) +#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) +#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) +#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) +#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) +#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) +#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) +#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) +#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) +#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) +#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) +#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) +#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) +#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) +#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) +#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) +#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) +#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) +#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) +#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) +#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) +#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) +#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) +#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) +#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) +#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) +#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) + +/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ +#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) +#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) +#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) +#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) +#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) + +/*! @name ADMA_SYS_ADDR - ADMA System Address */ +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) + +/*! @name DLL_CTRL - DLL (Delay Line) Control */ +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) + +/*! @name DLL_STATUS - DLL Status */ +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) + +/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) + +/*! @name VEND_SPEC - Vendor Specific Register */ +#define USDHC_VEND_SPEC_EXT_DMA_EN_MASK (0x1U) +#define USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT (0U) +#define USDHC_VEND_SPEC_EXT_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT)) & USDHC_VEND_SPEC_EXT_DMA_EN_MASK) +#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) +#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) +#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) +#define USDHC_VEND_SPEC_DAT3_CD_POL_MASK (0x10U) +#define USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT (4U) +#define USDHC_VEND_SPEC_DAT3_CD_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT)) & USDHC_VEND_SPEC_DAT3_CD_POL_MASK) +#define USDHC_VEND_SPEC_CD_POL_MASK (0x20U) +#define USDHC_VEND_SPEC_CD_POL_SHIFT (5U) +#define USDHC_VEND_SPEC_CD_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CD_POL_SHIFT)) & USDHC_VEND_SPEC_CD_POL_MASK) +#define USDHC_VEND_SPEC_WP_POL_MASK (0x40U) +#define USDHC_VEND_SPEC_WP_POL_SHIFT (6U) +#define USDHC_VEND_SPEC_WP_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_WP_POL_SHIFT)) & USDHC_VEND_SPEC_WP_POL_MASK) +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK (0x80U) +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT (7U) +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT)) & USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK (0x800U) +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT (11U) +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK (0x1000U) +#define USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT (12U) +#define USDHC_VEND_SPEC_HCLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK (0x2000U) +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT (13U) +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK (0x4000U) +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT (14U) +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) +#define USDHC_VEND_SPEC_INT_ST_VAL_MASK (0xFF0000U) +#define USDHC_VEND_SPEC_INT_ST_VAL_SHIFT (16U) +#define USDHC_VEND_SPEC_INT_ST_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_INT_ST_VAL_SHIFT)) & USDHC_VEND_SPEC_INT_ST_VAL_MASK) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) + +/*! @name MMC_BOOT - MMC Boot Register */ +#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) +#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) +#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) +#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) +#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) +#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) +#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) +#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) +#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) +#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) + +/*! @name VEND_SPEC2 - Vendor Specific 2 Register */ +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK (0x1U) +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT (0U) +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK) +#define USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK (0x2U) +#define USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT (1U) +#define USDHC_VEND_SPEC2_SDR104_OE_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK) +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK (0x4U) +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT (2U) +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK (0x80U) +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT (7U) +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x800000U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (23U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) + +/*! @name TUNING_CTRL - Tuning Control Register */ +#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) +#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) +#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) +#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) +#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) +#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) + + +/*! + * @} + */ /* end of group USDHC_Register_Masks */ + + +/* USDHC - Peripheral instance base addresses */ +/** Peripheral USDHC1 base address */ +#define USDHC1_BASE (0x2190000u) +/** Peripheral USDHC1 base pointer */ +#define USDHC1 ((USDHC_Type *)USDHC1_BASE) +/** Peripheral USDHC2 base address */ +#define USDHC2_BASE (0x2194000u) +/** Peripheral USDHC2 base pointer */ +#define USDHC2 ((USDHC_Type *)USDHC2_BASE) +/** Array initializer of USDHC peripheral base addresses */ +#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE } +/** Array initializer of USDHC peripheral base pointers */ +#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 } +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn } + +/*! + * @} + */ /* end of group USDHC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ + __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ + __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ + __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ + __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name WCR - Watchdog Control Register */ +#define WDOG_WCR_WDZST_MASK (0x1U) +#define WDOG_WCR_WDZST_SHIFT (0U) +#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) +#define WDOG_WCR_WDBG_MASK (0x2U) +#define WDOG_WCR_WDBG_SHIFT (1U) +#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) +#define WDOG_WCR_WDE_MASK (0x4U) +#define WDOG_WCR_WDE_SHIFT (2U) +#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) +#define WDOG_WCR_WDT_MASK (0x8U) +#define WDOG_WCR_WDT_SHIFT (3U) +#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) +#define WDOG_WCR_SRS_MASK (0x10U) +#define WDOG_WCR_SRS_SHIFT (4U) +#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) +#define WDOG_WCR_WDA_MASK (0x20U) +#define WDOG_WCR_WDA_SHIFT (5U) +#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) +#define WDOG_WCR_SRE_MASK (0x40U) +#define WDOG_WCR_SRE_SHIFT (6U) +#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) +#define WDOG_WCR_WDW_MASK (0x80U) +#define WDOG_WCR_WDW_SHIFT (7U) +#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) +#define WDOG_WCR_WT_MASK (0xFF00U) +#define WDOG_WCR_WT_SHIFT (8U) +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) + +/*! @name WSR - Watchdog Service Register */ +#define WDOG_WSR_WSR_MASK (0xFFFFU) +#define WDOG_WSR_WSR_SHIFT (0U) +#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) + +/*! @name WRSR - Watchdog Reset Status Register */ +#define WDOG_WRSR_SFTW_MASK (0x1U) +#define WDOG_WRSR_SFTW_SHIFT (0U) +#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) +#define WDOG_WRSR_TOUT_MASK (0x2U) +#define WDOG_WRSR_TOUT_SHIFT (1U) +#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) +#define WDOG_WRSR_POR_MASK (0x10U) +#define WDOG_WRSR_POR_SHIFT (4U) +#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) + +/*! @name WICR - Watchdog Interrupt Control Register */ +#define WDOG_WICR_WICT_MASK (0xFFU) +#define WDOG_WICR_WICT_SHIFT (0U) +#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) +#define WDOG_WICR_WTIS_MASK (0x4000U) +#define WDOG_WICR_WTIS_SHIFT (14U) +#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) +#define WDOG_WICR_WIE_MASK (0x8000U) +#define WDOG_WICR_WIE_SHIFT (15U) +#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) + +/*! @name WMCR - Watchdog Miscellaneous Control Register */ +#define WDOG_WMCR_PDE_MASK (0x1U) +#define WDOG_WMCR_PDE_SHIFT (0U) +#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG1 base address */ +#define WDOG1_BASE (0x20BC000u) +/** Peripheral WDOG1 base pointer */ +#define WDOG1 ((WDOG_Type *)WDOG1_BASE) +/** Peripheral WDOG2 base address */ +#define WDOG2_BASE (0x20C0000u) +/** Peripheral WDOG2 base pointer */ +#define WDOG2 ((WDOG_Type *)WDOG2_BASE) +/** Peripheral WDOG3 base address */ +#define WDOG3_BASE (0x21E4000u) +/** Peripheral WDOG3 base pointer */ +#define WDOG3 ((WDOG_Type *)WDOG3_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE, WDOG3_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2, WDOG3 } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn } + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer + * @{ + */ + +/** XTALOSC24M - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[336]; + __IO uint32_t OSC_CONFIG0; /**< XTAL OSC Configuration 0 Register, offset: 0x150 */ + __IO uint32_t OSC_CONFIG0_SET; /**< XTAL OSC Configuration 0 Register, offset: 0x154 */ + __IO uint32_t OSC_CONFIG0_CLR; /**< XTAL OSC Configuration 0 Register, offset: 0x158 */ + __IO uint32_t OSC_CONFIG0_TOG; /**< XTAL OSC Configuration 0 Register, offset: 0x15C */ + __IO uint32_t OSC_CONFIG1; /**< XTAL OSC Configuration 1 Register, offset: 0x160 */ + __IO uint32_t OSC_CONFIG1_SET; /**< XTAL OSC Configuration 1 Register, offset: 0x164 */ + __IO uint32_t OSC_CONFIG1_CLR; /**< XTAL OSC Configuration 1 Register, offset: 0x168 */ + __IO uint32_t OSC_CONFIG1_TOG; /**< XTAL OSC Configuration 1 Register, offset: 0x16C */ + __IO uint32_t OSC_CONFIG2; /**< XTAL OSC Configuration 2 Register, offset: 0x170 */ + __IO uint32_t OSC_CONFIG2_SET; /**< XTAL OSC Configuration 2 Register, offset: 0x174 */ + __IO uint32_t OSC_CONFIG2_CLR; /**< XTAL OSC Configuration 2 Register, offset: 0x178 */ + __IO uint32_t OSC_CONFIG2_TOG; /**< XTAL OSC Configuration 2 Register, offset: 0x17C */ +} XTALOSC24M_Type; + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks + * @{ + */ + +/*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK) + +/*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK) + +/*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK) + +/*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) + + +/*! + * @} + */ /* end of group XTALOSC24M_Register_Masks */ + + +/* XTALOSC24M - Peripheral instance base addresses */ +/** Peripheral XTALOSC24M base address */ +#define XTALOSC24M_BASE (0x20C8150u) +/** Peripheral XTALOSC24M base pointer */ +#define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) +/** Array initializer of XTALOSC24M peripheral base addresses */ +#define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE } +/** Array initializer of XTALOSC24M peripheral base pointers */ +#define XTALOSC24M_BASE_PTRS { XTALOSC24M } + +/*! + * @} + */ /* end of group XTALOSC24M_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _MCIMX6Y2_H_ */ + diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.xml b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.xml new file mode 100644 index 0000000000..6f0991e335 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2.xml @@ -0,0 +1,162023 @@ + + + nxp.com + MCIMX6Y2 + 1.0 + MCIMX6Y0DVM05, MCIMX6Y0CVM05, MCIMX6Y1DVM05, MCIMX6Y1DVK05, MCIMX6Y1CVM05, MCIMX6Y1CVK05, MCIMX6Y2DVM05, MCIMX6Y7DVK05 + + other + r2p0 + little + false + false + true + 0 + false + + 8 + 32 + + + APBH + APBH Register Reference Index + APBH + APBH_ + 0x1804000 + + 0 + 0x804 + registers + + + APBH + 45 + + + + CTRL0 + AHB to APBH Bridge Control and Status Register 0 + 0 + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + These bits must be set to zero for normal operation of each channel + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + APB_BURST_EN + Set this bit to one to enable apb master do a continous transfers when a device request a burst dma + 0x1C + 1 + read-write + + + AHB_BURST8_EN + Set this bit to one (default) to enable AHB 8-beat burst + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal APBH DMA operation + 0x1F + 1 + read-write + + + + + CTRL0_SET + AHB to APBH Bridge Control and Status Register 0 + 0x4 + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + These bits must be set to zero for normal operation of each channel + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + APB_BURST_EN + Set this bit to one to enable apb master do a continous transfers when a device request a burst dma + 0x1C + 1 + read-write + + + AHB_BURST8_EN + Set this bit to one (default) to enable AHB 8-beat burst + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal APBH DMA operation + 0x1F + 1 + read-write + + + + + CTRL0_CLR + AHB to APBH Bridge Control and Status Register 0 + 0x8 + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + These bits must be set to zero for normal operation of each channel + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + APB_BURST_EN + Set this bit to one to enable apb master do a continous transfers when a device request a burst dma + 0x1C + 1 + read-write + + + AHB_BURST8_EN + Set this bit to one (default) to enable AHB 8-beat burst + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal APBH DMA operation + 0x1F + 1 + read-write + + + + + CTRL0_TOG + AHB to APBH Bridge Control and Status Register 0 + 0xC + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + These bits must be set to zero for normal operation of each channel + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + APB_BURST_EN + Set this bit to one to enable apb master do a continous transfers when a device request a burst dma + 0x1C + 1 + read-write + + + AHB_BURST8_EN + Set this bit to one (default) to enable AHB 8-beat burst + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal APBH DMA operation + 0x1F + 1 + read-write + + + + + CTRL1 + AHB to APBH Bridge Control and Status Register 1 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 0 + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 1 + 0x1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 2 + 0x2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 3 + 0x3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 4 + 0x4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 5 + 0x5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 6 + 0x6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 7 + 0x7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 0. + 0x10 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 1. + 0x11 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 2. + 0x12 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 3. + 0x13 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 4. + 0x14 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 5. + 0x15 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 6. + 0x16 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 7. + 0x17 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 8. + 0x18 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 9. + 0x19 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 10. + 0x1A + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 11. + 0x1B + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 12. + 0x1C + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 13. + 0x1D + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 14. + 0x1E + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 15. + 0x1F + 1 + read-write + + + + + CTRL1_SET + AHB to APBH Bridge Control and Status Register 1 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 0 + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 1 + 0x1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 2 + 0x2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 3 + 0x3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 4 + 0x4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 5 + 0x5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 6 + 0x6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 7 + 0x7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 0. + 0x10 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 1. + 0x11 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 2. + 0x12 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 3. + 0x13 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 4. + 0x14 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 5. + 0x15 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 6. + 0x16 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 7. + 0x17 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 8. + 0x18 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 9. + 0x19 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 10. + 0x1A + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 11. + 0x1B + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 12. + 0x1C + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 13. + 0x1D + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 14. + 0x1E + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 15. + 0x1F + 1 + read-write + + + + + CTRL1_CLR + AHB to APBH Bridge Control and Status Register 1 + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 0 + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 1 + 0x1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 2 + 0x2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 3 + 0x3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 4 + 0x4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 5 + 0x5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 6 + 0x6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 7 + 0x7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 0. + 0x10 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 1. + 0x11 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 2. + 0x12 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 3. + 0x13 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 4. + 0x14 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 5. + 0x15 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 6. + 0x16 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 7. + 0x17 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 8. + 0x18 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 9. + 0x19 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 10. + 0x1A + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 11. + 0x1B + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 12. + 0x1C + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 13. + 0x1D + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 14. + 0x1E + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 15. + 0x1F + 1 + read-write + + + + + CTRL1_TOG + AHB to APBH Bridge Control and Status Register 1 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 0 + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 1 + 0x1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 2 + 0x2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 3 + 0x3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 4 + 0x4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 5 + 0x5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 6 + 0x6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA channel 7 + 0x7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_CMDCMPLT_IRQ + Interrupt request status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 0. + 0x10 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 1. + 0x11 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 2. + 0x12 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 3. + 0x13 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 4. + 0x14 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 5. + 0x15 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 6. + 0x16 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 7. + 0x17 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 8. + 0x18 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 9. + 0x19 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 10. + 0x1A + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 11. + 0x1B + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 12. + 0x1C + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 13. + 0x1D + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 14. + 0x1E + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + Setting this bit enables the generation of an interrupt request for APBH DMA channel 15. + 0x1F + 1 + read-write + + + + + CTRL2 + AHB to APBH Bridge Control and Status Register 2 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 0 + 0 + 1 + read-write + + + CH1_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 1 + 0x1 + 1 + read-write + + + CH2_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 2 + 0x2 + 1 + read-write + + + CH3_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 3 + 0x3 + 1 + read-write + + + CH4_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 4 + 0x4 + 1 + read-write + + + CH5_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 5 + 0x5 + 1 + read-write + + + CH6_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 6 + 0x6 + 1 + read-write + + + CH7_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 7 + 0x7 + 1 + read-write + + + CH8_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_ERROR_STATUS + Error status bit for APBX DMA Channel 0 + 0x10 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH1_ERROR_STATUS + Error status bit for APBX DMA Channel 1 + 0x11 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH2_ERROR_STATUS + Error status bit for APBX DMA Channel 2 + 0x12 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH3_ERROR_STATUS + Error status bit for APBX DMA Channel 3 + 0x13 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH4_ERROR_STATUS + Error status bit for APBX DMA Channel 4 + 0x14 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH5_ERROR_STATUS + Error status bit for APBX DMA Channel 5 + 0x15 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH6_ERROR_STATUS + Error status bit for APBX DMA Channel 6 + 0x16 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH7_ERROR_STATUS + Error status bit for APBX DMA Channel 7 + 0x17 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH8_ERROR_STATUS + Error status bit for APBH DMA Channel 8 + 0x18 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH9_ERROR_STATUS + Error status bit for APBH DMA Channel 9 + 0x19 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH10_ERROR_STATUS + Error status bit for APBH DMA Channel 10 + 0x1A + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH11_ERROR_STATUS + Error status bit for APBH DMA Channel 11 + 0x1B + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH12_ERROR_STATUS + Error status bit for APBH DMA Channel 12 + 0x1C + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH13_ERROR_STATUS + Error status bit for APBH DMA Channel 13 + 0x1D + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH14_ERROR_STATUS + Error status bit for APBH DMA Channel 14 + 0x1E + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH15_ERROR_STATUS + Error status bit for APBH DMA Channel 15 + 0x1F + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + + + CTRL2_SET + AHB to APBH Bridge Control and Status Register 2 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 0 + 0 + 1 + read-write + + + CH1_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 1 + 0x1 + 1 + read-write + + + CH2_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 2 + 0x2 + 1 + read-write + + + CH3_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 3 + 0x3 + 1 + read-write + + + CH4_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 4 + 0x4 + 1 + read-write + + + CH5_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 5 + 0x5 + 1 + read-write + + + CH6_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 6 + 0x6 + 1 + read-write + + + CH7_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 7 + 0x7 + 1 + read-write + + + CH8_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_ERROR_STATUS + Error status bit for APBX DMA Channel 0 + 0x10 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH1_ERROR_STATUS + Error status bit for APBX DMA Channel 1 + 0x11 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH2_ERROR_STATUS + Error status bit for APBX DMA Channel 2 + 0x12 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH3_ERROR_STATUS + Error status bit for APBX DMA Channel 3 + 0x13 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH4_ERROR_STATUS + Error status bit for APBX DMA Channel 4 + 0x14 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH5_ERROR_STATUS + Error status bit for APBX DMA Channel 5 + 0x15 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH6_ERROR_STATUS + Error status bit for APBX DMA Channel 6 + 0x16 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH7_ERROR_STATUS + Error status bit for APBX DMA Channel 7 + 0x17 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH8_ERROR_STATUS + Error status bit for APBH DMA Channel 8 + 0x18 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH9_ERROR_STATUS + Error status bit for APBH DMA Channel 9 + 0x19 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH10_ERROR_STATUS + Error status bit for APBH DMA Channel 10 + 0x1A + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH11_ERROR_STATUS + Error status bit for APBH DMA Channel 11 + 0x1B + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH12_ERROR_STATUS + Error status bit for APBH DMA Channel 12 + 0x1C + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH13_ERROR_STATUS + Error status bit for APBH DMA Channel 13 + 0x1D + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH14_ERROR_STATUS + Error status bit for APBH DMA Channel 14 + 0x1E + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH15_ERROR_STATUS + Error status bit for APBH DMA Channel 15 + 0x1F + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + + + CTRL2_CLR + AHB to APBH Bridge Control and Status Register 2 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 0 + 0 + 1 + read-write + + + CH1_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 1 + 0x1 + 1 + read-write + + + CH2_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 2 + 0x2 + 1 + read-write + + + CH3_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 3 + 0x3 + 1 + read-write + + + CH4_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 4 + 0x4 + 1 + read-write + + + CH5_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 5 + 0x5 + 1 + read-write + + + CH6_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 6 + 0x6 + 1 + read-write + + + CH7_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 7 + 0x7 + 1 + read-write + + + CH8_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_ERROR_STATUS + Error status bit for APBX DMA Channel 0 + 0x10 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH1_ERROR_STATUS + Error status bit for APBX DMA Channel 1 + 0x11 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH2_ERROR_STATUS + Error status bit for APBX DMA Channel 2 + 0x12 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH3_ERROR_STATUS + Error status bit for APBX DMA Channel 3 + 0x13 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH4_ERROR_STATUS + Error status bit for APBX DMA Channel 4 + 0x14 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH5_ERROR_STATUS + Error status bit for APBX DMA Channel 5 + 0x15 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH6_ERROR_STATUS + Error status bit for APBX DMA Channel 6 + 0x16 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH7_ERROR_STATUS + Error status bit for APBX DMA Channel 7 + 0x17 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH8_ERROR_STATUS + Error status bit for APBH DMA Channel 8 + 0x18 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH9_ERROR_STATUS + Error status bit for APBH DMA Channel 9 + 0x19 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH10_ERROR_STATUS + Error status bit for APBH DMA Channel 10 + 0x1A + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH11_ERROR_STATUS + Error status bit for APBH DMA Channel 11 + 0x1B + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH12_ERROR_STATUS + Error status bit for APBH DMA Channel 12 + 0x1C + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH13_ERROR_STATUS + Error status bit for APBH DMA Channel 13 + 0x1D + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH14_ERROR_STATUS + Error status bit for APBH DMA Channel 14 + 0x1E + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH15_ERROR_STATUS + Error status bit for APBH DMA Channel 15 + 0x1F + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + + + CTRL2_TOG + AHB to APBH Bridge Control and Status Register 2 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 0 + 0 + 1 + read-write + + + CH1_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 1 + 0x1 + 1 + read-write + + + CH2_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 2 + 0x2 + 1 + read-write + + + CH3_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 3 + 0x3 + 1 + read-write + + + CH4_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 4 + 0x4 + 1 + read-write + + + CH5_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 5 + 0x5 + 1 + read-write + + + CH6_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 6 + 0x6 + 1 + read-write + + + CH7_ERROR_IRQ + Error interrupt status bit for APBX DMA Channel 7 + 0x7 + 1 + read-write + + + CH8_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 8 + 0x8 + 1 + read-write + + + CH9_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 9 + 0x9 + 1 + read-write + + + CH10_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 10 + 0xA + 1 + read-write + + + CH11_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 11 + 0xB + 1 + read-write + + + CH12_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 12 + 0xC + 1 + read-write + + + CH13_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 13 + 0xD + 1 + read-write + + + CH14_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 14 + 0xE + 1 + read-write + + + CH15_ERROR_IRQ + Error interrupt status bit for APBH DMA Channel 15 + 0xF + 1 + read-write + + + CH0_ERROR_STATUS + Error status bit for APBX DMA Channel 0 + 0x10 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH1_ERROR_STATUS + Error status bit for APBX DMA Channel 1 + 0x11 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH2_ERROR_STATUS + Error status bit for APBX DMA Channel 2 + 0x12 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH3_ERROR_STATUS + Error status bit for APBX DMA Channel 3 + 0x13 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH4_ERROR_STATUS + Error status bit for APBX DMA Channel 4 + 0x14 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH5_ERROR_STATUS + Error status bit for APBX DMA Channel 5 + 0x15 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH6_ERROR_STATUS + Error status bit for APBX DMA Channel 6 + 0x16 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH7_ERROR_STATUS + Error status bit for APBX DMA Channel 7 + 0x17 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH8_ERROR_STATUS + Error status bit for APBH DMA Channel 8 + 0x18 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH9_ERROR_STATUS + Error status bit for APBH DMA Channel 9 + 0x19 + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH10_ERROR_STATUS + Error status bit for APBH DMA Channel 10 + 0x1A + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH11_ERROR_STATUS + Error status bit for APBH DMA Channel 11 + 0x1B + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH12_ERROR_STATUS + Error status bit for APBH DMA Channel 12 + 0x1C + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH13_ERROR_STATUS + Error status bit for APBH DMA Channel 13 + 0x1D + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH14_ERROR_STATUS + Error status bit for APBH DMA Channel 14 + 0x1E + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + CH15_ERROR_STATUS + Error status bit for APBH DMA Channel 15 + 0x1F + 1 + read-only + + + TERMINATION + An early termination from the device causes error IRQ. + 0 + + + BUS_ERROR + An AHB bus error causes error IRQ. + 0x1 + + + + + + + CHANNEL_CTRL + AHB to APBH Bridge Channel Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FREEZE_CHANNEL + Setting a bit in this field will freeze the DMA channel associated with it + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + RESET_CHANNEL + Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state + 0x10 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + + + CHANNEL_CTRL_SET + AHB to APBH Bridge Channel Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + FREEZE_CHANNEL + Setting a bit in this field will freeze the DMA channel associated with it + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + RESET_CHANNEL + Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state + 0x10 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + + + CHANNEL_CTRL_CLR + AHB to APBH Bridge Channel Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FREEZE_CHANNEL + Setting a bit in this field will freeze the DMA channel associated with it + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + RESET_CHANNEL + Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state + 0x10 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + + + CHANNEL_CTRL_TOG + AHB to APBH Bridge Channel Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + FREEZE_CHANNEL + Setting a bit in this field will freeze the DMA channel associated with it + 0 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + RESET_CHANNEL + Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state + 0x10 + 16 + read-write + + + NAND0 + no description available + 0x1 + + + NAND1 + no description available + 0x2 + + + NAND2 + no description available + 0x4 + + + NAND3 + no description available + 0x8 + + + NAND4 + no description available + 0x10 + + + NAND5 + no description available + 0x20 + + + NAND6 + no description available + 0x40 + + + NAND7 + no description available + 0x80 + + + SSP + no description available + 0x100 + + + + + + + DEVSEL + AHB to APBH DMA Device Assignment Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + DMA_BURST_SIZE + AHB to APBH DMA burst size + 0x50 + 32 + read-write + 0x555555 + 0xFFFFFFFF + + + CH0 + DMA burst size for GPMI channel 0. Do not change. GPMI only support burst size 4. + 0 + 2 + read-write + + + CH1 + DMA burst size for GPMI channel 1. Do not change. GPMI only support burst size 4. + 0x2 + 2 + read-write + + + CH2 + DMA burst size for GPMI channel 2. Do not change. GPMI only support burst size 4. + 0x4 + 2 + read-write + + + CH3 + DMA burst size for GPMI channel 3. Do not change. GPMI only support burst size 4. + 0x6 + 2 + read-write + + + CH4 + DMA burst size for GPMI channel 4. Do not change. GPMI only support burst size 4. + 0x8 + 2 + read-write + + + CH5 + DMA burst size for GPMI channel 5. Do not change. GPMI only support burst size 4. + 0xA + 2 + read-write + + + CH6 + DMA burst size for GPMI channel 6. Do not change. GPMI only support burst size 4. + 0xC + 2 + read-write + + + CH7 + DMA burst size for GPMI channel 7. Do not change. GPMI only support burst size 4. + 0xE + 2 + read-write + + + CH8 + DMA burst size for SSP. + 0x10 + 2 + read-write + + + BURST0 + no description available + 0 + + + BURST4 + no description available + 0x1 + + + BURST8 + no description available + 0x2 + + + + + + + DEBUG + AHB to APBH DMA Debug Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPMI_ONE_FIFO + Set to 0ne and the 8 GPMI channels will share the DMA FIFO, and when set to zero, the 8 GPMI channels will use its own DMA FIFO + 0 + 1 + read-write + + + + + 16 + 0x70 + CH%s_CURCMDAR + APBH DMA Channel n Current Command Address Register + 0x100 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMD_ADDR + Pointer to command structure currently being processed for channel n. + 0 + 32 + read-only + + + + + 16 + 0x70 + CH%s_NXTCMDAR + APBH DMA Channel n Next Command Address Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD_ADDR + Pointer to next command structure for channel n. + 0 + 32 + read-write + + + + + 16 + 0x70 + CH%s_CMD + APBH DMA Channel n Command Register + 0x120 + 32 + read-only + 0 + 0xFFFFFFFF + + + COMMAND + This bitfield indicates the type of current command: + 0 + 2 + read-only + + + NO_DMA_XFER + Perform any requested PIO word transfers but terminate command before any DMA transfer. + 0 + + + DMA_WRITE + Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. + 0x1 + + + DMA_READ + Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. + 0x2 + + + DMA_SENSE + Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. + 0x3 + + + + + CHAIN + A value of one indicates that another command is chained onto the end of the current command structure + 0x2 + 1 + read-only + + + IRQONCMPLT + A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i + 0x3 + 1 + read-only + + + NANDLOCK + A value of one indicates that the NAND DMA channel will remain "locked" in the arbiter at the expense of other NAND DMA channels + 0x4 + 1 + read-only + + + NANDWAIT4READY + A value of one indicates that the NAND DMA channel will will wait until the NAND device reports "ready" before executing the command + 0x5 + 1 + read-only + + + SEMAPHORE + A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure + 0x6 + 1 + read-only + + + WAIT4ENDCMD + A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command + 0x7 + 1 + read-only + + + HALTONTERMINATE + A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set + 0x8 + 1 + read-only + + + CMDWORDS + This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there + 0xC + 4 + read-only + + + XFER_COUNT + This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device + 0x10 + 16 + read-only + + + + + 16 + 0x70 + CH%s_BAR + APBH DMA Channel n Buffer Address Register + 0x130 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDRESS + Address of system memory buffer to be read or written over the AHB bus. + 0 + 32 + read-only + + + + + 16 + 0x70 + CH%s_SEMA + APBH DMA Channel n Semaphore Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT_SEMA + The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + PHORE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 0x10 + 8 + read-only + + + + + 16 + 0x70 + CH%s_DEBUG1 + AHB to APBH DMA Channel n Debug Information + 0x150 + 32 + read-only + 0xA00000 + 0xFFFFFFFF + + + STATEMACHINE + PIO Display of the DMA Channel n state machine state. + 0 + 5 + read-only + + + IDLE + This is the idle state of the DMA state machine. + 0 + + + REQ_CMD1 + State in which the DMA is waiting to receive the first word of a command. + 0x1 + + + REQ_CMD3 + State in which the DMA is waiting to receive the third word of a command. + 0x2 + + + REQ_CMD2 + State in which the DMA is waiting to receive the second word of a command. + 0x3 + + + XFER_DECODE + The state machine processes the descriptor command field in this state and branches accordingly. + 0x4 + + + REQ_WAIT + The state machine waits in this state for the PIO APB cycles to complete. + 0x5 + + + REQ_CMD4 + State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. + 0x6 + + + PIO_REQ + This state determines whether another PIO cycle needs to occur before starting DMA transfers. + 0x7 + + + READ_FLUSH + During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. + 0x8 + + + READ_WAIT + When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. + 0x9 + + + WRITE + During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + 0xC + + + READ_REQ + During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. + 0xD + + + CHECK_CHAIN + Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. + 0xE + + + XFER_COMPLETE + The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. + 0xF + + + TERMINATE + When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. + 0x14 + + + WAIT_END + When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. + 0x15 + + + WRITE_WAIT + During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. + 0x1C + + + HALT_AFTER_TERM + If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state + 0x1D + + + CHECK_WAIT + If the Chain bit is a 0, the state machine enters this state and effectively halts. + 0x1E + + + WAIT_READY + When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. + 0x1F + + + + + WR_FIFO_FULL + This bit reflects the current state of the DMA Channel's Write FIFO Full signal. + 0x14 + 1 + read-only + + + WR_FIFO_EMPTY + This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. + 0x15 + 1 + read-only + + + RD_FIFO_FULL + This bit reflects the current state of the DMA Channel's Read FIFO Full signal. + 0x16 + 1 + read-only + + + RD_FIFO_EMPTY + This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. + 0x17 + 1 + read-only + + + NEXTCMDADDRVALID + This bit reflects the internal bit which indicates whether the channel's next command address is valid + 0x18 + 1 + read-only + + + READY + This bit is reserved for this DMA Channel and always reads 0. + 0x1A + 1 + read-only + + + END + This bit reflects the current state of the DMA End Command Signal sent from the APB Device + 0x1C + 1 + read-only + + + KICK + This bit reflects the current state of the DMA Kick Signal sent to the APB Device + 0x1D + 1 + read-only + + + BURST + This bit reflects the current state of the DMA Burst Signal from the APB device + 0x1E + 1 + read-only + + + REQ + This bit reflects the current state of the DMA Request Signal from the APB device + 0x1F + 1 + read-only + + + + + 16 + 0x70 + CH%s_DEBUG2 + AHB to APBH DMA Channel n Debug Information + 0x160 + 32 + read-only + 0 + 0xFFFFFFFF + + + AHB_BYTES + This value reflects the current number of AHB bytes remaining to be transfered in the current transfer + 0 + 16 + read-only + + + APB_BYTES + This value reflects the current number of APB bytes remaining to be transfered in the current transfer + 0x10 + 16 + read-only + + + + + VERSION + APBH Bridge Version Register + 0x800 + 32 + read-only + 0x3010000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + + + GPMI + GPMI + GPMI + GPMI_ + 0x1806000 + + 0 + 0x134 + registers + + + RAWNAND_GPMI + 48 + + + + CTRL0 + GPMI Control Register 0 Description + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + Number of bytes to transfer for this command. A value of zero will transfer 64K bytes. + 0 + 16 + read-write + + + ADDRESS_INCREMENT + In ATA mode, the address will increment with each cycle + 0x10 + 1 + read-write + + + ADDRESS_INCREMENT_0 + Address does not increment. + 0 + + + ADDRESS_INCREMENT_1 + Increment address. + 0x1 + + + + + ADDRESS + Specifies the three address lines for ATA mode + 0x11 + 3 + read-write + + + CS + Selects which chip select is active for this command + 0x14 + 3 + read-write + + + WORD_LENGTH + This bit should only be changed when RUN==0 + 0x17 + 1 + read-write + + + WORD_LENGTH_1 + 8-bit Data Bus mode. + 0x1 + + + + + COMMAND_MODE + WRITE = 0x0 Write mode + 0x18 + 2 + read-write + + + COMMAND_MODE_0 + Write mode. + 0 + + + COMMAND_MODE_1 + Read Mode. + 0x1 + + + COMMAND_MODE_2 + Read and Compare Mode (setting sense flop). + 0x2 + + + COMMAND_MODE_3 + Wait for Ready. + 0x3 + + + + + UDMA + DISABLED = 0x0 Use ATA-PIO mode on the external bus + 0x1A + 1 + read-write + + + UDMA_0 + Use ATA-PIO mode on the external bus. + 0 + + + UDMA_1 + Use ATA-Ultra DMA mode on the external bus. + 0x1 + + + + + LOCK_CS + For ATA/NAND mode: 0= Deassert chip select (CS) after RUN is complete + 0x1B + 1 + read-write + + + DEV_IRQ_EN + When set to '1' and ATA_IRQ pin is asserted, the GPMI_IRQ output will assert. + 0x1C + 1 + read-write + + + RUN + The GPMI is busy running a command whenever this bit is set to '1' + 0x1D + 1 + read-write + + + CLKGATE + Set this bit zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set to zero for normal operation + 0x1F + 1 + read-write + + + + + CTRL0_SET + GPMI Control Register 0 Description + 0x4 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + Number of bytes to transfer for this command. A value of zero will transfer 64K bytes. + 0 + 16 + read-write + + + ADDRESS_INCREMENT + In ATA mode, the address will increment with each cycle + 0x10 + 1 + read-write + + + ADDRESS_INCREMENT_0 + Address does not increment. + 0 + + + ADDRESS_INCREMENT_1 + Increment address. + 0x1 + + + + + ADDRESS + Specifies the three address lines for ATA mode + 0x11 + 3 + read-write + + + CS + Selects which chip select is active for this command + 0x14 + 3 + read-write + + + WORD_LENGTH + This bit should only be changed when RUN==0 + 0x17 + 1 + read-write + + + WORD_LENGTH_1 + 8-bit Data Bus mode. + 0x1 + + + + + COMMAND_MODE + WRITE = 0x0 Write mode + 0x18 + 2 + read-write + + + COMMAND_MODE_0 + Write mode. + 0 + + + COMMAND_MODE_1 + Read Mode. + 0x1 + + + COMMAND_MODE_2 + Read and Compare Mode (setting sense flop). + 0x2 + + + COMMAND_MODE_3 + Wait for Ready. + 0x3 + + + + + UDMA + DISABLED = 0x0 Use ATA-PIO mode on the external bus + 0x1A + 1 + read-write + + + UDMA_0 + Use ATA-PIO mode on the external bus. + 0 + + + UDMA_1 + Use ATA-Ultra DMA mode on the external bus. + 0x1 + + + + + LOCK_CS + For ATA/NAND mode: 0= Deassert chip select (CS) after RUN is complete + 0x1B + 1 + read-write + + + DEV_IRQ_EN + When set to '1' and ATA_IRQ pin is asserted, the GPMI_IRQ output will assert. + 0x1C + 1 + read-write + + + RUN + The GPMI is busy running a command whenever this bit is set to '1' + 0x1D + 1 + read-write + + + CLKGATE + Set this bit zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set to zero for normal operation + 0x1F + 1 + read-write + + + + + CTRL0_CLR + GPMI Control Register 0 Description + 0x8 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + Number of bytes to transfer for this command. A value of zero will transfer 64K bytes. + 0 + 16 + read-write + + + ADDRESS_INCREMENT + In ATA mode, the address will increment with each cycle + 0x10 + 1 + read-write + + + ADDRESS_INCREMENT_0 + Address does not increment. + 0 + + + ADDRESS_INCREMENT_1 + Increment address. + 0x1 + + + + + ADDRESS + Specifies the three address lines for ATA mode + 0x11 + 3 + read-write + + + CS + Selects which chip select is active for this command + 0x14 + 3 + read-write + + + WORD_LENGTH + This bit should only be changed when RUN==0 + 0x17 + 1 + read-write + + + WORD_LENGTH_1 + 8-bit Data Bus mode. + 0x1 + + + + + COMMAND_MODE + WRITE = 0x0 Write mode + 0x18 + 2 + read-write + + + COMMAND_MODE_0 + Write mode. + 0 + + + COMMAND_MODE_1 + Read Mode. + 0x1 + + + COMMAND_MODE_2 + Read and Compare Mode (setting sense flop). + 0x2 + + + COMMAND_MODE_3 + Wait for Ready. + 0x3 + + + + + UDMA + DISABLED = 0x0 Use ATA-PIO mode on the external bus + 0x1A + 1 + read-write + + + UDMA_0 + Use ATA-PIO mode on the external bus. + 0 + + + UDMA_1 + Use ATA-Ultra DMA mode on the external bus. + 0x1 + + + + + LOCK_CS + For ATA/NAND mode: 0= Deassert chip select (CS) after RUN is complete + 0x1B + 1 + read-write + + + DEV_IRQ_EN + When set to '1' and ATA_IRQ pin is asserted, the GPMI_IRQ output will assert. + 0x1C + 1 + read-write + + + RUN + The GPMI is busy running a command whenever this bit is set to '1' + 0x1D + 1 + read-write + + + CLKGATE + Set this bit zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set to zero for normal operation + 0x1F + 1 + read-write + + + + + CTRL0_TOG + GPMI Control Register 0 Description + 0xC + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + Number of bytes to transfer for this command. A value of zero will transfer 64K bytes. + 0 + 16 + read-write + + + ADDRESS_INCREMENT + In ATA mode, the address will increment with each cycle + 0x10 + 1 + read-write + + + ADDRESS_INCREMENT_0 + Address does not increment. + 0 + + + ADDRESS_INCREMENT_1 + Increment address. + 0x1 + + + + + ADDRESS + Specifies the three address lines for ATA mode + 0x11 + 3 + read-write + + + CS + Selects which chip select is active for this command + 0x14 + 3 + read-write + + + WORD_LENGTH + This bit should only be changed when RUN==0 + 0x17 + 1 + read-write + + + WORD_LENGTH_1 + 8-bit Data Bus mode. + 0x1 + + + + + COMMAND_MODE + WRITE = 0x0 Write mode + 0x18 + 2 + read-write + + + COMMAND_MODE_0 + Write mode. + 0 + + + COMMAND_MODE_1 + Read Mode. + 0x1 + + + COMMAND_MODE_2 + Read and Compare Mode (setting sense flop). + 0x2 + + + COMMAND_MODE_3 + Wait for Ready. + 0x3 + + + + + UDMA + DISABLED = 0x0 Use ATA-PIO mode on the external bus + 0x1A + 1 + read-write + + + UDMA_0 + Use ATA-PIO mode on the external bus. + 0 + + + UDMA_1 + Use ATA-Ultra DMA mode on the external bus. + 0x1 + + + + + LOCK_CS + For ATA/NAND mode: 0= Deassert chip select (CS) after RUN is complete + 0x1B + 1 + read-write + + + DEV_IRQ_EN + When set to '1' and ATA_IRQ pin is asserted, the GPMI_IRQ output will assert. + 0x1C + 1 + read-write + + + RUN + The GPMI is busy running a command whenever this bit is set to '1' + 0x1D + 1 + read-write + + + CLKGATE + Set this bit zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set to zero for normal operation + 0x1F + 1 + read-write + + + + + COMPARE + GPMI Compare Register Description + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + REFERENCE + 16-bit value which is XORed with data read from the NAND device. + 0 + 16 + read-write + + + MASK + 16-bit mask which is applied after the read data is XORed with the REFERENCE bit field. + 0x10 + 16 + read-write + + + + + ECCCTRL + GPMI Integrated ECC Control Register Description + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + ECC buffer information + 0 + 9 + read-write + + + RSVD1 + Always write zeroes to this bit field. + 0x9 + 3 + read-only + + + ENABLE_ECC + Enable ECC processing of GPMI transfers + 0xC + 1 + read-write + + + ECC_CMD + ECC Command information + 0xD + 2 + read-write + + + RSVD2 + Always write zeroes to this bit field. + 0xF + 1 + read-write + + + HANDLE + This is a register available to software to attach an identifier to a transaction in progress + 0x10 + 16 + read-write + + + + + ECCCTRL_SET + GPMI Integrated ECC Control Register Description + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + ECC buffer information + 0 + 9 + read-write + + + RSVD1 + Always write zeroes to this bit field. + 0x9 + 3 + read-only + + + ENABLE_ECC + Enable ECC processing of GPMI transfers + 0xC + 1 + read-write + + + ECC_CMD + ECC Command information + 0xD + 2 + read-write + + + RSVD2 + Always write zeroes to this bit field. + 0xF + 1 + read-write + + + HANDLE + This is a register available to software to attach an identifier to a transaction in progress + 0x10 + 16 + read-write + + + + + ECCCTRL_CLR + GPMI Integrated ECC Control Register Description + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + ECC buffer information + 0 + 9 + read-write + + + RSVD1 + Always write zeroes to this bit field. + 0x9 + 3 + read-only + + + ENABLE_ECC + Enable ECC processing of GPMI transfers + 0xC + 1 + read-write + + + ECC_CMD + ECC Command information + 0xD + 2 + read-write + + + RSVD2 + Always write zeroes to this bit field. + 0xF + 1 + read-write + + + HANDLE + This is a register available to software to attach an identifier to a transaction in progress + 0x10 + 16 + read-write + + + + + ECCCTRL_TOG + GPMI Integrated ECC Control Register Description + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + ECC buffer information + 0 + 9 + read-write + + + RSVD1 + Always write zeroes to this bit field. + 0x9 + 3 + read-only + + + ENABLE_ECC + Enable ECC processing of GPMI transfers + 0xC + 1 + read-write + + + ECC_CMD + ECC Command information + 0xD + 2 + read-write + + + RSVD2 + Always write zeroes to this bit field. + 0xF + 1 + read-write + + + HANDLE + This is a register available to software to attach an identifier to a transaction in progress + 0x10 + 16 + read-write + + + + + ECCCOUNT + GPMI Integrated ECC Transfer Count Register Description + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + COUNT + Number of bytes to pass through ECC + 0 + 16 + read-write + + + RSVD2 + Always write zeroes to this bit field. + 0x10 + 16 + read-write + + + + + PAYLOAD + GPMI Payload Address Register Description + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Always write zeroes to this bit field. + 0 + 2 + read-only + + + ADDRESS + Pointer to an array of one or more 512 byte payload buffers. + 0x2 + 30 + read-write + + + + + AUXILIARY + GPMI Auxiliary Address Register Description + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Always write zeroes to this bit field. + 0 + 2 + read-only + + + ADDRESS + Pointer to ECC control structure and meta-data storage. + 0x2 + 30 + read-write + + + + + CTRL1 + GPMI Control Register 1 Description + 0x60 + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + ATA mode is only supported on channel zero + 0 + 1 + read-write + + + GPMI_MODE_0 + NAND mode. + 0 + + + GPMI_MODE_1 + ATA mode. + 0x1 + + + + + CAMERA_MODE + When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface. + 0x1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit + 0x2 + 1 + read-write + + + ATA_IRQRDY_POLARITY_0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + 0 + + + ATA_IRQRDY_POLARITY_1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + 0x1 + + + + + DEV_RESET + ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted) + 0x3 + 1 + read-write + + + DEV_RESET_0 + NANDF_WP_B pin is held low (asserted). + 0 + + + DEV_RESET_1 + NANDF_WP_B pin is held high (de-asserted). + 0x1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + Abort a wait for ready command on selected channel + 0x4 + 3 + read-write + + + ABORT_WAIT_REQUEST + Request to abort "wait for ready" command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL + 0x7 + 1 + read-write + + + BURST_EN + When set to 1 each DMA request will generate a 4-transfer burst on the APB bus. + 0x8 + 1 + read-write + + + TIMEOUT_IRQ + This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear. + 0x9 + 1 + read-write + + + DEV_IRQ + This bit is set when an Interrupt is received from the ATA device. Write 0 to clear. + 0xA + 1 + read-write + + + DMA2ECC_MODE + This is mainly for testing HWECC without involving the Nand device + 0xB + 1 + read-write + + + RDN_DELAY + This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling + 0xC + 4 + read-write + + + HALF_PERIOD + Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation + 0x10 + 1 + read-write + + + DLL_ENABLE + Set this bit to 1 to enable the GPMI DLL + 0x11 + 1 + read-write + + + BCH_MODE + This bit selects which error correction unit will access GPMI + 0x12 + 1 + read-write + + + GANGED_RDYBUSY + Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0 + 0x13 + 1 + read-write + + + TIMEOUT_IRQ_EN + Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only, and for WAIT_FOR_READY commands in both ATA and Nand mode + 0x14 + 1 + read-write + + + TEST_TRIGGER + Test Trigger Enable + 0x15 + 1 + read-write + + + TEST_TRIGGER_0 + Disable + 0 + + + TEST_TRIGGER_1 + Enable + 0x1 + + + + + WRN_DLY_SEL + Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to match the load on this pin + 0x16 + 2 + read-write + + + DECOUPLE_CS + Decouple Chip Select from DMA Channel + 0x18 + 1 + read-write + + + SSYNCMODE + source synchronouse mode 1 or asynchrous mode 0 + 0x19 + 1 + read-write + + + UPDATE_CS + force the CS value is be updated to external chip select pin, even GPMI is idle. + 0x1A + 1 + read-write + + + GPMI_CLK_DIV2_EN + This bit should be reset to 0 in asynchronous mode + 0x1B + 1 + read-write + + + GPMI_CLK_DIV2_EN_0 + internal factor-2 clock divider is disabled + 0 + + + GPMI_CLK_DIV2_EN_1 + internal factor-2 clock divider is enabled. + 0x1 + + + + + TOGGLE_MODE + enable samsung toggle mode. + 0x1C + 1 + read-write + + + WRITE_CLK_STOP + In onfi source synchronous mode, host may save power during the data write cycles by holding the CLK signal high (i + 0x1D + 1 + read-write + + + SSYNC_CLK_STOP + set this bit to 1 will stop the source synchronous mode clk. + 0x1E + 1 + read-write + + + DEV_CLK_STOP + set this bit to 1 will stop gpmi io working clk. + 0x1F + 1 + read-write + + + + + CTRL1_SET + GPMI Control Register 1 Description + 0x64 + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + ATA mode is only supported on channel zero + 0 + 1 + read-write + + + GPMI_MODE_0 + NAND mode. + 0 + + + GPMI_MODE_1 + ATA mode. + 0x1 + + + + + CAMERA_MODE + When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface. + 0x1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit + 0x2 + 1 + read-write + + + ATA_IRQRDY_POLARITY_0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + 0 + + + ATA_IRQRDY_POLARITY_1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + 0x1 + + + + + DEV_RESET + ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted) + 0x3 + 1 + read-write + + + DEV_RESET_0 + NANDF_WP_B pin is held low (asserted). + 0 + + + DEV_RESET_1 + NANDF_WP_B pin is held high (de-asserted). + 0x1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + Abort a wait for ready command on selected channel + 0x4 + 3 + read-write + + + ABORT_WAIT_REQUEST + Request to abort "wait for ready" command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL + 0x7 + 1 + read-write + + + BURST_EN + When set to 1 each DMA request will generate a 4-transfer burst on the APB bus. + 0x8 + 1 + read-write + + + TIMEOUT_IRQ + This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear. + 0x9 + 1 + read-write + + + DEV_IRQ + This bit is set when an Interrupt is received from the ATA device. Write 0 to clear. + 0xA + 1 + read-write + + + DMA2ECC_MODE + This is mainly for testing HWECC without involving the Nand device + 0xB + 1 + read-write + + + RDN_DELAY + This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling + 0xC + 4 + read-write + + + HALF_PERIOD + Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation + 0x10 + 1 + read-write + + + DLL_ENABLE + Set this bit to 1 to enable the GPMI DLL + 0x11 + 1 + read-write + + + BCH_MODE + This bit selects which error correction unit will access GPMI + 0x12 + 1 + read-write + + + GANGED_RDYBUSY + Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0 + 0x13 + 1 + read-write + + + TIMEOUT_IRQ_EN + Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only, and for WAIT_FOR_READY commands in both ATA and Nand mode + 0x14 + 1 + read-write + + + TEST_TRIGGER + Test Trigger Enable + 0x15 + 1 + read-write + + + TEST_TRIGGER_0 + Disable + 0 + + + TEST_TRIGGER_1 + Enable + 0x1 + + + + + WRN_DLY_SEL + Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to match the load on this pin + 0x16 + 2 + read-write + + + DECOUPLE_CS + Decouple Chip Select from DMA Channel + 0x18 + 1 + read-write + + + SSYNCMODE + source synchronouse mode 1 or asynchrous mode 0 + 0x19 + 1 + read-write + + + UPDATE_CS + force the CS value is be updated to external chip select pin, even GPMI is idle. + 0x1A + 1 + read-write + + + GPMI_CLK_DIV2_EN + This bit should be reset to 0 in asynchronous mode + 0x1B + 1 + read-write + + + GPMI_CLK_DIV2_EN_0 + internal factor-2 clock divider is disabled + 0 + + + GPMI_CLK_DIV2_EN_1 + internal factor-2 clock divider is enabled. + 0x1 + + + + + TOGGLE_MODE + enable samsung toggle mode. + 0x1C + 1 + read-write + + + WRITE_CLK_STOP + In onfi source synchronous mode, host may save power during the data write cycles by holding the CLK signal high (i + 0x1D + 1 + read-write + + + SSYNC_CLK_STOP + set this bit to 1 will stop the source synchronous mode clk. + 0x1E + 1 + read-write + + + DEV_CLK_STOP + set this bit to 1 will stop gpmi io working clk. + 0x1F + 1 + read-write + + + + + CTRL1_CLR + GPMI Control Register 1 Description + 0x68 + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + ATA mode is only supported on channel zero + 0 + 1 + read-write + + + GPMI_MODE_0 + NAND mode. + 0 + + + GPMI_MODE_1 + ATA mode. + 0x1 + + + + + CAMERA_MODE + When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface. + 0x1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit + 0x2 + 1 + read-write + + + ATA_IRQRDY_POLARITY_0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + 0 + + + ATA_IRQRDY_POLARITY_1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + 0x1 + + + + + DEV_RESET + ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted) + 0x3 + 1 + read-write + + + DEV_RESET_0 + NANDF_WP_B pin is held low (asserted). + 0 + + + DEV_RESET_1 + NANDF_WP_B pin is held high (de-asserted). + 0x1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + Abort a wait for ready command on selected channel + 0x4 + 3 + read-write + + + ABORT_WAIT_REQUEST + Request to abort "wait for ready" command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL + 0x7 + 1 + read-write + + + BURST_EN + When set to 1 each DMA request will generate a 4-transfer burst on the APB bus. + 0x8 + 1 + read-write + + + TIMEOUT_IRQ + This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear. + 0x9 + 1 + read-write + + + DEV_IRQ + This bit is set when an Interrupt is received from the ATA device. Write 0 to clear. + 0xA + 1 + read-write + + + DMA2ECC_MODE + This is mainly for testing HWECC without involving the Nand device + 0xB + 1 + read-write + + + RDN_DELAY + This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling + 0xC + 4 + read-write + + + HALF_PERIOD + Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation + 0x10 + 1 + read-write + + + DLL_ENABLE + Set this bit to 1 to enable the GPMI DLL + 0x11 + 1 + read-write + + + BCH_MODE + This bit selects which error correction unit will access GPMI + 0x12 + 1 + read-write + + + GANGED_RDYBUSY + Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0 + 0x13 + 1 + read-write + + + TIMEOUT_IRQ_EN + Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only, and for WAIT_FOR_READY commands in both ATA and Nand mode + 0x14 + 1 + read-write + + + TEST_TRIGGER + Test Trigger Enable + 0x15 + 1 + read-write + + + TEST_TRIGGER_0 + Disable + 0 + + + TEST_TRIGGER_1 + Enable + 0x1 + + + + + WRN_DLY_SEL + Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to match the load on this pin + 0x16 + 2 + read-write + + + DECOUPLE_CS + Decouple Chip Select from DMA Channel + 0x18 + 1 + read-write + + + SSYNCMODE + source synchronouse mode 1 or asynchrous mode 0 + 0x19 + 1 + read-write + + + UPDATE_CS + force the CS value is be updated to external chip select pin, even GPMI is idle. + 0x1A + 1 + read-write + + + GPMI_CLK_DIV2_EN + This bit should be reset to 0 in asynchronous mode + 0x1B + 1 + read-write + + + GPMI_CLK_DIV2_EN_0 + internal factor-2 clock divider is disabled + 0 + + + GPMI_CLK_DIV2_EN_1 + internal factor-2 clock divider is enabled. + 0x1 + + + + + TOGGLE_MODE + enable samsung toggle mode. + 0x1C + 1 + read-write + + + WRITE_CLK_STOP + In onfi source synchronous mode, host may save power during the data write cycles by holding the CLK signal high (i + 0x1D + 1 + read-write + + + SSYNC_CLK_STOP + set this bit to 1 will stop the source synchronous mode clk. + 0x1E + 1 + read-write + + + DEV_CLK_STOP + set this bit to 1 will stop gpmi io working clk. + 0x1F + 1 + read-write + + + + + CTRL1_TOG + GPMI Control Register 1 Description + 0x6C + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + ATA mode is only supported on channel zero + 0 + 1 + read-write + + + GPMI_MODE_0 + NAND mode. + 0 + + + GPMI_MODE_1 + ATA mode. + 0x1 + + + + + CAMERA_MODE + When set to 1 and ATA UDMA is enabled the UDMA interface becomes a camera interface. + 0x1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + For ATA MODE: Note NAND_RDY_BUSY[3:2] are not affected by this bit + 0x2 + 1 + read-write + + + ATA_IRQRDY_POLARITY_0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + 0 + + + ATA_IRQRDY_POLARITY_1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + 0x1 + + + + + DEV_RESET + ENABLED = 0x0 NANDF_WP_B(WPN) pin is held low (asserted) + 0x3 + 1 + read-write + + + DEV_RESET_0 + NANDF_WP_B pin is held low (asserted). + 0 + + + DEV_RESET_1 + NANDF_WP_B pin is held high (de-asserted). + 0x1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + Abort a wait for ready command on selected channel + 0x4 + 3 + read-write + + + ABORT_WAIT_REQUEST + Request to abort "wait for ready" command on channel indicated by ABORT_WAIT_FOR_READY_CHANNEL + 0x7 + 1 + read-write + + + BURST_EN + When set to 1 each DMA request will generate a 4-transfer burst on the APB bus. + 0x8 + 1 + read-write + + + TIMEOUT_IRQ + This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear. + 0x9 + 1 + read-write + + + DEV_IRQ + This bit is set when an Interrupt is received from the ATA device. Write 0 to clear. + 0xA + 1 + read-write + + + DMA2ECC_MODE + This is mainly for testing HWECC without involving the Nand device + 0xB + 1 + read-write + + + RDN_DELAY + This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling + 0xC + 4 + read-write + + + HALF_PERIOD + Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation + 0x10 + 1 + read-write + + + DLL_ENABLE + Set this bit to 1 to enable the GPMI DLL + 0x11 + 1 + read-write + + + BCH_MODE + This bit selects which error correction unit will access GPMI + 0x12 + 1 + read-write + + + GANGED_RDYBUSY + Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0 + 0x13 + 1 + read-write + + + TIMEOUT_IRQ_EN + Setting this bit to '1' will enable timeout IRQ for transfers in ATA mode only, and for WAIT_FOR_READY commands in both ATA and Nand mode + 0x14 + 1 + read-write + + + TEST_TRIGGER + Test Trigger Enable + 0x15 + 1 + read-write + + + TEST_TRIGGER_0 + Disable + 0 + + + TEST_TRIGGER_1 + Enable + 0x1 + + + + + WRN_DLY_SEL + Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to match the load on this pin + 0x16 + 2 + read-write + + + DECOUPLE_CS + Decouple Chip Select from DMA Channel + 0x18 + 1 + read-write + + + SSYNCMODE + source synchronouse mode 1 or asynchrous mode 0 + 0x19 + 1 + read-write + + + UPDATE_CS + force the CS value is be updated to external chip select pin, even GPMI is idle. + 0x1A + 1 + read-write + + + GPMI_CLK_DIV2_EN + This bit should be reset to 0 in asynchronous mode + 0x1B + 1 + read-write + + + GPMI_CLK_DIV2_EN_0 + internal factor-2 clock divider is disabled + 0 + + + GPMI_CLK_DIV2_EN_1 + internal factor-2 clock divider is enabled. + 0x1 + + + + + TOGGLE_MODE + enable samsung toggle mode. + 0x1C + 1 + read-write + + + WRITE_CLK_STOP + In onfi source synchronous mode, host may save power during the data write cycles by holding the CLK signal high (i + 0x1D + 1 + read-write + + + SSYNC_CLK_STOP + set this bit to 1 will stop the source synchronous mode clk. + 0x1E + 1 + read-write + + + DEV_CLK_STOP + set this bit to 1 will stop gpmi io working clk. + 0x1F + 1 + read-write + + + + + TIMING0 + GPMI Timing Register 0 Description + 0x70 + 32 + read-write + 0x10203 + 0xFFFFFFFF + + + DATA_SETUP + Data bus setup time in GPMICLK cycles + 0 + 8 + read-write + + + DATA_HOLD + Data bus hold time in GPMICLK cycles + 0x8 + 8 + read-write + + + ADDRESS_SETUP + Number of GPMICLK cycles that the CE/ADDR signals are active before a strobe is asserted + 0x10 + 8 + read-write + + + RSVD1 + Always write zeroes to this bit field. + 0x18 + 8 + write-only + + + + + TIMING1 + GPMI Timing Register 1 Description + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD1 + Always write zeroes to this bit field. + 0 + 16 + read-only + + + DEVICE_BUSY_TIMEOUT + Timeout waiting for NAND Ready/Busy or ATA IRQ + 0x10 + 16 + read-write + + + + + TIMING2 + GPMI Timing Register 2 Description + 0x90 + 32 + read-write + 0x3023336 + 0xFFFFFFFF + + + DATA_PAUSE + GPMI delay time from data pause to data resume in GPMICLK cycles + 0 + 4 + read-write + + + CMDADD_PAUSE + GPMI delay time from command or addres pause to command or address resume in GPMICLK cycles + 0x4 + 4 + read-write + + + POSTAMBLE_DELAY + GPMI post-amble delay in GPMICLK cycles. A value of zero is interpreted as 16. + 0x8 + 4 + read-write + + + PREAMBLE_DELAY + GPMI pre-amble delay in GPMICLK cycles. A value of zero is interpreted as 16. + 0xC + 4 + read-write + + + CE_DELAY + GPMI dealy from CEn assert to W/Rn changing edge. value of zero is interpreted as 32. + 0x10 + 5 + read-write + + + RSVD0 + Always write zeroes to this bit field. + 0x15 + 3 + read-only + + + READ_LATENCY + This field is for double data rate read latency configuration. others READ LATENCY is 3 + 0x18 + 3 + read-write + + + READ_LATENCY_0 + READ LATENCY is 0 + 0 + + + READ_LATENCY_1 + READ LATENCY is 1 + 0x1 + + + READ_LATENCY_2 + READ LATENCY is 2 + 0x2 + + + READ_LATENCY_3 + READ LATENCY is 3 + 0x3 + + + READ_LATENCY_4 + READ LATENCY is 4 + 0x4 + + + READ_LATENCY_5 + READ LATENCY is 5 + 0x5 + + + + + TCR + Only for Toggle NAND timing control delay (TCR+1) GPMICLK cycles for CEn_B low to RE_B low, 0 is less than or equal to TCR, which is less than the PREAMBLE_DELAY + 0x1B + 2 + read-write + + + TRPSTH + Only for Toggle NAND timing control delay TRPSTH GPMICLK cycles for CEn_B high to RE_B high, A value of zero is interpreted as 8 + 0x1D + 3 + read-write + + + + + DATA + GPMI DMA Data Transfer Register Description + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + In 8-bit mode, one, two, three or four bytes can can be accessed to send the same number of bus cycles + 0 + 32 + read-write + + + + + STAT + GPMI Status Register Description + 0xB0 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + PRESENT + UNAVAILABLE = 0x0 GPMI is not present in this product + 0 + 1 + read-only + + + PRESENT_0 + GPMI is not present in this product. + 0 + + + PRESENT_1 + GPMI is present is in this product. + 0x1 + + + + + FIFO_FULL + NOT_FULL = 0x0 FIFO is not full. FULL = 0x1 FIFO is full. + 0x1 + 1 + read-only + + + FIFO_FULL_0 + FIFO is not full. + 0 + + + FIFO_FULL_1 + FIFO is full. + 0x1 + + + + + FIFO_EMPTY + NOT_EMPTY = 0x0 FIFO is not empty. EMPTY = 0x1 FIFO is empty. + 0x2 + 1 + read-only + + + FIFO_EMPTY_0 + FIFO is not empty. + 0 + + + FIFO_EMPTY_1 + FIFO is empty. + 0x1 + + + + + INVALID_BUFFER_MASK + Buffer Mask Validity bit. + 0x3 + 1 + read-only + + + INVALID_BUFFER_MASK_0 + ECC Buffer Mask is not invalid. + 0 + + + INVALID_BUFFER_MASK_1 + ECC Buffer Mask is invalid. + 0x1 + + + + + ATA_IRQ + Status of the ATA_IRQ input pin. + 0x4 + 1 + read-only + + + RSVD1 + Always write zeroes to this bit field. + 0x5 + 3 + read-only + + + DEV0_ERROR + DMA channel 0 (Timeout or compare failure, depending on COMMAND_MODE). + 0x8 + 1 + read-only + + + DEV0_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 0. + 0 + + + DEV0_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV1_ERROR + DMA channel 1 (Timeout or compare failure, depending on COMMAND_MODE). + 0x9 + 1 + read-only + + + DEV1_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 1. + 0 + + + DEV1_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV2_ERROR + DMA channel 2 (Timeout or compare failure, depending on COMMAND_MODE). + 0xA + 1 + read-only + + + DEV2_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 2. + 0 + + + DEV2_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV3_ERROR + DMA channel 3 (Timeout or compare failure, depending on COMMAND_MODE). + 0xB + 1 + read-only + + + DEV3_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 3. + 0 + + + DEV3_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV4_ERROR + DMA channel 4 (Timeout or compare failure, depending on COMMAND_MODE). + 0xC + 1 + read-only + + + DEV4_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 4. + 0 + + + DEV4_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV5_ERROR + DMA channel 5 (Timeout or compare failure, depending on COMMAND_MODE). + 0xD + 1 + read-only + + + DEV5_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 5. + 0 + + + DEV5_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV6_ERROR + DMA channel 6 (Timeout or compare failure, depending on COMMAND_MODE). + 0xE + 1 + read-only + + + DEV6_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 6. + 0 + + + DEV6_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + DEV7_ERROR + DMA channel 7 (Timeout or compare failure, depending on COMMAND_MODE). + 0xF + 1 + read-only + + + DEV7_ERROR_0 + No error condition present on ATA/NAND Device accessed by DMA channel 7. + 0 + + + DEV7_ERROR_1 + An Error has occurred on ATA/NAND Device accessed by + 0x1 + + + + + RDY_TIMEOUT + State of the RDY/BUSY Timeout Flags + 0x10 + 8 + read-only + + + READY_BUSY + Read-only view of NAND Ready_Busy Input pins. + 0x18 + 8 + read-only + + + + + DEBUG + GPMI Debug Information Register Description + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMD_END + Read Only view of the Command End toggle signals to DMA. One per channel + 0 + 8 + read-only + + + DMAREQ + Read-only view of DMA request line for 8 DMA channels + 0x8 + 8 + read-only + + + DMA_SENSE + Read-only view of sense state of the 8 DMA channels + 0x10 + 8 + read-only + + + WAIT_FOR_READY_END + Read Only view of the Wait_For_Ready End toggle signals to DMA. One per channel + 0x18 + 8 + read-only + + + + + VERSION + GPMI Version Register Description + 0xD0 + 32 + read-only + 0x5020000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + DEBUG2 + GPMI Debug2 Information Register Description + 0xE0 + 32 + read-write + 0xF100 + 0xFFFFFFFF + + + RDN_TAP + This is the DLL tap calculated by the DLL controller + 0 + 6 + read-only + + + UPDATE_WINDOW + A 1 indicates that the DLL is busy generating the required delay. + 0x6 + 1 + read-only + + + VIEW_DELAYED_RDN + Set to a 1 to select the delayed feedback RE_B to drive the GPMI_ADDR[0] (Nand CLE) pin + 0x7 + 1 + read-write + + + SYND2GPMI_READY + Data handshake Input from BCH. + 0x8 + 1 + read-only + + + SYND2GPMI_VALID + Data handshake Input from BCH. + 0x9 + 1 + read-only + + + GPMI2SYND_READY + Data handshake output to BCH. + 0xA + 1 + read-only + + + GPMI2SYND_VALID + Data handshake output to BCH. + 0xB + 1 + read-only + + + SYND2GPMI_BE + Data byte enable Input from BCH. + 0xC + 4 + read-only + + + MAIN_STATE + parameter MSM_IDLE = 4'h0, MSM_BYTCNT = 4'h1, MSM_WAITFE = 4'h2, MSM_WAITFR = 4'h3, MSM_DMAREQ = 4'h4, MSM_DMAACK = 4'h5, MSM_WAITFF = 4'h6, MSM_LDFIFO = 4'h7, MSM_LDDMAR = 4'h8, MSM_RDCMP = 4'h9, MSM_DONE = 4'hA + 0x10 + 4 + read-only + + + PIN_STATE + parameter PSM_IDLE = 3'h0, PSM_BYTCNT = 3'h1, PSM_ADDR = 3'h2, PSM_STALL = 3'h3, PSM_STROBE = 3'h4, PSM_ATARDY = 3'h5, PSM_DHOLD = 3'h6, PSM_DONE = 3'h7 + 0x14 + 3 + read-only + + + BUSY + When asserted the GPMI is busy + 0x17 + 1 + read-only + + + UDMA_STATE + USM_IDLE = 4'h0, idle USM_DMARQ = 4'h1, DMA req USM_ACK = 4'h2, DMA ACK USM_FIFO_E = 4'h3, Fifo empty USM_WPAUSE = 4'h4, WR DMA Paused by device USM_TSTRB = 4'h5, Toggle HSTROBE USM_CAPTUR = 4'h6, Capture Stage, (data sampled with DSTROBE is valid) USM_DATOUT = 4'h7, Change Burst DATAOUT USM_CRC = 4'h8, Source CRC to Device USM_WAIT_R = 4'h9, Waiting for DDMARDY- USM_END = 4'ha; Negate DMAACK (end of DMA) USM_WAIT_S = 4'hb, Waiting for DSTROBE USM_RPAUSE = 4'hc, Rd DMA Paused by Host USM_RSTOP = 4'hd, Rd DMA Stopped by Host USM_WTERM = 4'he, Wr DMA Termination State USM_RTERM = 4'hf, Rd DMA Termination state + 0x18 + 4 + read-only + + + RSVD1 + Always write zeroes to this bit field. + 0x1C + 4 + read-write + + + + + DEBUG3 + GPMI Debug3 Information Register Description + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DEV_WORD_CNTR + Reflects the number of bytes remains to be transferred on the ATA/Nand bus. + 0 + 16 + read-only + + + APB_WORD_CNTR + Reflects the number of bytes remains to be transferred on the APB bus. + 0x10 + 16 + read-only + + + + + READ_DDR_DLL_CTRL + GPMI Double Rate Read DLL Control Register Description + 0x100 + 32 + read-write + 0x38 + 0xFFFFFFFF + + + ENABLE + Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL + 0 + 1 + read-write + + + RESET + Setting this bit to 1 force a reset on DLL + 0x1 + 1 + read-write + + + SLV_FORCE_UPD + Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately + 0x2 + 1 + read-write + + + SLV_DLY_TARGET + The delay target for the read clock is can be programmed in 1/16th increments of an GPMICLK half-period + 0x3 + 4 + read-write + + + GATE_UPDATE + Setting this bit to 1, forces the slave delay line not update + 0x7 + 1 + read-write + + + REFCLK_ON + set this bit to 1 will turn on the reference clock + 0x8 + 1 + read-write + + + SLV_OVERRIDE + Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to disable manual override + 0x9 + 1 + read-write + + + SLV_OVERRIDE_VAL + When SLV_OVERRIDE=1 This field is used to select 1 of 256 physical taps manually + 0xA + 8 + read-write + + + RSVD1 + Reserved + 0x12 + 2 + read-only + + + SLV_UPDATE_INT + Setting a value greater than 0 in this field, shall over-ride the default slave delay-line update interval of 256 GPMICLK cycles + 0x14 + 8 + read-write + + + REF_UPDATE_INT + This field allows the user to add additional delay cycles to the DLL control loop (reference delay line control) + 0x1C + 4 + read-write + + + + + WRITE_DDR_DLL_CTRL + GPMI Double Rate Write DLL Control Register Description + 0x110 + 32 + read-write + 0x38 + 0xFFFFFFFF + + + ENABLE + Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL + 0 + 1 + read-write + + + RESET + Setting this bit to 1 force a reset on DLL + 0x1 + 1 + read-write + + + SLV_FORCE_UPD + Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately + 0x2 + 1 + read-write + + + SLV_DLY_TARGET + The delay target for the read clock can be programmed in 1/16th increments of an GPMICLK half-period + 0x3 + 4 + read-write + + + GATE_UPDATE + Setting this bit to 1, forces the slave delay line not update + 0x7 + 1 + read-write + + + REFCLK_ON + set this bit to 1 will turn on the reference clock + 0x8 + 1 + read-write + + + SLV_OVERRIDE + Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to disable manual override + 0x9 + 1 + read-write + + + SLV_OVERRIDE_VAL + When SLV_OVERRIDE=1 This field is used to select 1 of 256 physical taps manually + 0xA + 8 + read-write + + + RSVD1 + Reserved + 0x12 + 2 + read-only + + + SLV_UPDATE_INT + Setting a value greater than 0 in this field, shall over-ride the default slave delay-line update interval of 256 GPMICLK cycles + 0x14 + 8 + read-write + + + REF_UPDATE_INT + This field allows the user to add additional delay cycles to the DLL control loop (reference delay line control) + 0x1C + 4 + read-write + + + + + READ_DDR_DLL_STS + GPMI Double Rate Read DLL Status Register Description + 0x120 + 32 + read-only + 0 + 0xFFFFFFFF + + + SLV_LOCK + Slave delay-line lock status + 0 + 1 + read-only + + + SLV_SEL + Slave delay line select status + 0x1 + 8 + read-only + + + RSVD0 + Reserved + 0x9 + 7 + read-only + + + REF_LOCK + Reference DLL lock status + 0x10 + 1 + read-only + + + REF_SEL + Reference delay line select status. + 0x11 + 8 + read-only + + + RSVD1 + Reserved + 0x19 + 7 + read-only + + + + + WRITE_DDR_DLL_STS + GPMI Double Rate Write DLL Status Register Description + 0x130 + 32 + read-only + 0 + 0xFFFFFFFF + + + SLV_LOCK + Slave delay-line lock status + 0 + 1 + read-only + + + SLV_SEL + Slave delay line select status + 0x1 + 8 + read-only + + + RSVD0 + Reserved + 0x9 + 7 + read-only + + + REF_LOCK + Reference DLL lock status + 0x10 + 1 + read-only + + + REF_SEL + Reference delay line select status. + 0x11 + 8 + read-only + + + RSVD1 + Reserved + 0x19 + 7 + read-only + + + + + + + BCH + BCH Register Reference Index + BCH + BCH_ + 0x1808000 + + 0 + 0x180 + registers + + + RAWNAND_BCH + 47 + + + + CTRL + Hardware BCH ECC Accelerator Control Register + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + COMPLETE_IRQ + This bit indicates the state of the external interrupt line + 0 + 1 + read-write + + + RSVD0 + This field is reserved. + 0x1 + 1 + read-only + + + DEBUG_STALL_IRQ + DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. + 0x2 + 1 + read-write + + + BM_ERROR_IRQ + AHB Bus interface Error Interrupt Status + 0x3 + 1 + read-write + + + RSVD1 + This field is reserved. + 0x4 + 4 + read-only + + + COMPLETE_IRQ_EN + 1 = interrupt on completion of correction is enabled. + 0x8 + 1 + read-write + + + RSVD2 + This field is reserved. + 0x9 + 1 + read-only + + + DEBUG_STALL_IRQ_EN + 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block + 0xA + 1 + read-write + + + RSVD3 + This field is reserved. + 0xB + 5 + read-only + + + M2M_ENABLE + NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION + 0x10 + 1 + read-write + + + M2M_ENCODE + Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations. + 0x11 + 1 + read-write + + + M2M_LAYOUT + Selects the flash page format for memory-to-memory operations. + 0x12 + 2 + read-write + + + RSVD4 + This field is reserved. + 0x14 + 2 + read-only + + + DEBUGSYNDROME + (For debug purposes only) + 0x16 + 1 + read-write + + + RSVD5 + This field is reserved. + 0x17 + 7 + read-only + + + CLKGATE + This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block. + 0x1E + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + NO_CLKS + Do not clock BCH gates in order to minimize power consumption. + 0x1 + + + + + SFTRST + Set this bit to 0 to enable normal BCH operation + 0x1F + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + RESET + Hold BCH in reset. + 0x1 + + + + + + + CTRL_SET + Hardware BCH ECC Accelerator Control Register + 0x4 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + COMPLETE_IRQ + This bit indicates the state of the external interrupt line + 0 + 1 + read-write + + + RSVD0 + This field is reserved. + 0x1 + 1 + read-only + + + DEBUG_STALL_IRQ + DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. + 0x2 + 1 + read-write + + + BM_ERROR_IRQ + AHB Bus interface Error Interrupt Status + 0x3 + 1 + read-write + + + RSVD1 + This field is reserved. + 0x4 + 4 + read-only + + + COMPLETE_IRQ_EN + 1 = interrupt on completion of correction is enabled. + 0x8 + 1 + read-write + + + RSVD2 + This field is reserved. + 0x9 + 1 + read-only + + + DEBUG_STALL_IRQ_EN + 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block + 0xA + 1 + read-write + + + RSVD3 + This field is reserved. + 0xB + 5 + read-only + + + M2M_ENABLE + NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION + 0x10 + 1 + read-write + + + M2M_ENCODE + Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations. + 0x11 + 1 + read-write + + + M2M_LAYOUT + Selects the flash page format for memory-to-memory operations. + 0x12 + 2 + read-write + + + RSVD4 + This field is reserved. + 0x14 + 2 + read-only + + + DEBUGSYNDROME + (For debug purposes only) + 0x16 + 1 + read-write + + + RSVD5 + This field is reserved. + 0x17 + 7 + read-only + + + CLKGATE + This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block. + 0x1E + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + NO_CLKS + Do not clock BCH gates in order to minimize power consumption. + 0x1 + + + + + SFTRST + Set this bit to 0 to enable normal BCH operation + 0x1F + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + RESET + Hold BCH in reset. + 0x1 + + + + + + + CTRL_CLR + Hardware BCH ECC Accelerator Control Register + 0x8 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + COMPLETE_IRQ + This bit indicates the state of the external interrupt line + 0 + 1 + read-write + + + RSVD0 + This field is reserved. + 0x1 + 1 + read-only + + + DEBUG_STALL_IRQ + DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. + 0x2 + 1 + read-write + + + BM_ERROR_IRQ + AHB Bus interface Error Interrupt Status + 0x3 + 1 + read-write + + + RSVD1 + This field is reserved. + 0x4 + 4 + read-only + + + COMPLETE_IRQ_EN + 1 = interrupt on completion of correction is enabled. + 0x8 + 1 + read-write + + + RSVD2 + This field is reserved. + 0x9 + 1 + read-only + + + DEBUG_STALL_IRQ_EN + 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block + 0xA + 1 + read-write + + + RSVD3 + This field is reserved. + 0xB + 5 + read-only + + + M2M_ENABLE + NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION + 0x10 + 1 + read-write + + + M2M_ENCODE + Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations. + 0x11 + 1 + read-write + + + M2M_LAYOUT + Selects the flash page format for memory-to-memory operations. + 0x12 + 2 + read-write + + + RSVD4 + This field is reserved. + 0x14 + 2 + read-only + + + DEBUGSYNDROME + (For debug purposes only) + 0x16 + 1 + read-write + + + RSVD5 + This field is reserved. + 0x17 + 7 + read-only + + + CLKGATE + This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block. + 0x1E + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + NO_CLKS + Do not clock BCH gates in order to minimize power consumption. + 0x1 + + + + + SFTRST + Set this bit to 0 to enable normal BCH operation + 0x1F + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + RESET + Hold BCH in reset. + 0x1 + + + + + + + CTRL_TOG + Hardware BCH ECC Accelerator Control Register + 0xC + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + COMPLETE_IRQ + This bit indicates the state of the external interrupt line + 0 + 1 + read-write + + + RSVD0 + This field is reserved. + 0x1 + 1 + read-only + + + DEBUG_STALL_IRQ + DEBUG STALL Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. + 0x2 + 1 + read-write + + + BM_ERROR_IRQ + AHB Bus interface Error Interrupt Status + 0x3 + 1 + read-write + + + RSVD1 + This field is reserved. + 0x4 + 4 + read-only + + + COMPLETE_IRQ_EN + 1 = interrupt on completion of correction is enabled. + 0x8 + 1 + read-write + + + RSVD2 + This field is reserved. + 0x9 + 1 + read-only + + + DEBUG_STALL_IRQ_EN + 1 = interrupt on debug stall mode is enabled. The IRQ is raised on every block + 0xA + 1 + read-write + + + RSVD3 + This field is reserved. + 0xB + 5 + read-only + + + M2M_ENABLE + NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION + 0x10 + 1 + read-write + + + M2M_ENCODE + Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations. + 0x11 + 1 + read-write + + + M2M_LAYOUT + Selects the flash page format for memory-to-memory operations. + 0x12 + 2 + read-write + + + RSVD4 + This field is reserved. + 0x14 + 2 + read-only + + + DEBUGSYNDROME + (For debug purposes only) + 0x16 + 1 + read-write + + + RSVD5 + This field is reserved. + 0x17 + 7 + read-only + + + CLKGATE + This bit must be set to 0 for normal operation. When set to 1 it gates off the clocks to the block. + 0x1E + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + NO_CLKS + Do not clock BCH gates in order to minimize power consumption. + 0x1 + + + + + SFTRST + Set this bit to 0 to enable normal BCH operation + 0x1F + 1 + read-write + + + RUN + Allow BCH to operate normally. + 0 + + + RESET + Hold BCH in reset. + 0x1 + + + + + + + STATUS0 + Hardware ECC Accelerator Status Register 0 + 0x10 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + RSVD0 + This field is reserved. + 0 + 2 + read-only + + + UNCORRECTABLE + 1 = Uncorrectable error encountered during last processing cycle. + 0x2 + 1 + read-only + + + CORRECTED + 1 = At least one correctable error encountered during last processing cycle. + 0x3 + 1 + read-only + + + ALLONES + 1 = All data bits of this transaction are ONE. + 0x4 + 1 + read-only + + + RSVD1 + This field is reserved. + 0x5 + 3 + read-only + + + STATUS_BLK0 + Count of symbols in error during processing of first block of flash (metadata block) + 0x8 + 8 + read-only + + + ZERO + No errors found on block. + 0 + + + ERROR1 + One error found on block. + 0x1 + + + ERROR2 + One errors found on block. + 0x2 + + + ERROR3 + One errors found on block. + 0x3 + + + ERROR4 + One errors found on block. + 0x4 + + + UNCORRECTABLE + Block exhibited uncorrectable errors. + 0xFE + + + ERASED + Page is erased. + 0xFF + + + + + COMPLETED_CE + This is the chip enable number corresponding to the NAND device from which this data came. + 0x10 + 4 + read-only + + + HANDLE + Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction + 0x14 + 12 + read-only + + + + + STATUS0_SET + Hardware ECC Accelerator Status Register 0 + 0x14 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + RSVD0 + This field is reserved. + 0 + 2 + read-only + + + UNCORRECTABLE + 1 = Uncorrectable error encountered during last processing cycle. + 0x2 + 1 + read-only + + + CORRECTED + 1 = At least one correctable error encountered during last processing cycle. + 0x3 + 1 + read-only + + + ALLONES + 1 = All data bits of this transaction are ONE. + 0x4 + 1 + read-only + + + RSVD1 + This field is reserved. + 0x5 + 3 + read-only + + + STATUS_BLK0 + Count of symbols in error during processing of first block of flash (metadata block) + 0x8 + 8 + read-only + + + ZERO + No errors found on block. + 0 + + + ERROR1 + One error found on block. + 0x1 + + + ERROR2 + One errors found on block. + 0x2 + + + ERROR3 + One errors found on block. + 0x3 + + + ERROR4 + One errors found on block. + 0x4 + + + UNCORRECTABLE + Block exhibited uncorrectable errors. + 0xFE + + + ERASED + Page is erased. + 0xFF + + + + + COMPLETED_CE + This is the chip enable number corresponding to the NAND device from which this data came. + 0x10 + 4 + read-only + + + HANDLE + Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction + 0x14 + 12 + read-only + + + + + STATUS0_CLR + Hardware ECC Accelerator Status Register 0 + 0x18 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + RSVD0 + This field is reserved. + 0 + 2 + read-only + + + UNCORRECTABLE + 1 = Uncorrectable error encountered during last processing cycle. + 0x2 + 1 + read-only + + + CORRECTED + 1 = At least one correctable error encountered during last processing cycle. + 0x3 + 1 + read-only + + + ALLONES + 1 = All data bits of this transaction are ONE. + 0x4 + 1 + read-only + + + RSVD1 + This field is reserved. + 0x5 + 3 + read-only + + + STATUS_BLK0 + Count of symbols in error during processing of first block of flash (metadata block) + 0x8 + 8 + read-only + + + ZERO + No errors found on block. + 0 + + + ERROR1 + One error found on block. + 0x1 + + + ERROR2 + One errors found on block. + 0x2 + + + ERROR3 + One errors found on block. + 0x3 + + + ERROR4 + One errors found on block. + 0x4 + + + UNCORRECTABLE + Block exhibited uncorrectable errors. + 0xFE + + + ERASED + Page is erased. + 0xFF + + + + + COMPLETED_CE + This is the chip enable number corresponding to the NAND device from which this data came. + 0x10 + 4 + read-only + + + HANDLE + Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction + 0x14 + 12 + read-only + + + + + STATUS0_TOG + Hardware ECC Accelerator Status Register 0 + 0x1C + 32 + read-only + 0x10 + 0xFFFFFFFF + + + RSVD0 + This field is reserved. + 0 + 2 + read-only + + + UNCORRECTABLE + 1 = Uncorrectable error encountered during last processing cycle. + 0x2 + 1 + read-only + + + CORRECTED + 1 = At least one correctable error encountered during last processing cycle. + 0x3 + 1 + read-only + + + ALLONES + 1 = All data bits of this transaction are ONE. + 0x4 + 1 + read-only + + + RSVD1 + This field is reserved. + 0x5 + 3 + read-only + + + STATUS_BLK0 + Count of symbols in error during processing of first block of flash (metadata block) + 0x8 + 8 + read-only + + + ZERO + No errors found on block. + 0 + + + ERROR1 + One error found on block. + 0x1 + + + ERROR2 + One errors found on block. + 0x2 + + + ERROR3 + One errors found on block. + 0x3 + + + ERROR4 + One errors found on block. + 0x4 + + + UNCORRECTABLE + Block exhibited uncorrectable errors. + 0xFE + + + ERASED + Page is erased. + 0xFF + + + + + COMPLETED_CE + This is the chip enable number corresponding to the NAND device from which this data came. + 0x10 + 4 + read-only + + + HANDLE + Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction + 0x14 + 12 + read-only + + + + + MODE + Hardware ECC Accelerator Mode Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASE_THRESHOLD + This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased + 0 + 8 + read-write + + + RSVD + This field is reserved. + 0x8 + 24 + read-only + + + + + MODE_SET + Hardware ECC Accelerator Mode Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASE_THRESHOLD + This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased + 0 + 8 + read-write + + + RSVD + This field is reserved. + 0x8 + 24 + read-only + + + + + MODE_CLR + Hardware ECC Accelerator Mode Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASE_THRESHOLD + This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased + 0 + 8 + read-write + + + RSVD + This field is reserved. + 0x8 + 24 + read-only + + + + + MODE_TOG + Hardware ECC Accelerator Mode Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASE_THRESHOLD + This value indicates the maximum number of zero bits on a flash subpage for it to be considered erased + 0 + 8 + read-write + + + RSVD + This field is reserved. + 0x8 + 24 + read-only + + + + + ENCODEPTR + Hardware BCH ECC Loopback Encode Buffer Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to encode buffer + 0 + 32 + read-write + + + + + ENCODEPTR_SET + Hardware BCH ECC Loopback Encode Buffer Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to encode buffer + 0 + 32 + read-write + + + + + ENCODEPTR_CLR + Hardware BCH ECC Loopback Encode Buffer Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to encode buffer + 0 + 32 + read-write + + + + + ENCODEPTR_TOG + Hardware BCH ECC Loopback Encode Buffer Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to encode buffer + 0 + 32 + read-write + + + + + DATAPTR + Hardware BCH ECC Loopback Data Buffer Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to data buffer + 0 + 32 + read-write + + + + + DATAPTR_SET + Hardware BCH ECC Loopback Data Buffer Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to data buffer + 0 + 32 + read-write + + + + + DATAPTR_CLR + Hardware BCH ECC Loopback Data Buffer Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to data buffer + 0 + 32 + read-write + + + + + DATAPTR_TOG + Hardware BCH ECC Loopback Data Buffer Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to data buffer + 0 + 32 + read-write + + + + + METAPTR + Hardware BCH ECC Loopback Metadata Buffer Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to metadata buffer + 0 + 32 + read-write + + + + + METAPTR_SET + Hardware BCH ECC Loopback Metadata Buffer Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to metadata buffer + 0 + 32 + read-write + + + + + METAPTR_CLR + Hardware BCH ECC Loopback Metadata Buffer Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to metadata buffer + 0 + 32 + read-write + + + + + METAPTR_TOG + Hardware BCH ECC Loopback Metadata Buffer Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer to metadata buffer + 0 + 32 + read-write + + + + + LAYOUTSELECT + Hardware ECC Accelerator Layout Select Register + 0x70 + 32 + read-write + 0xE4E4E4E4 + 0xFFFFFFFF + + + CS0_SELECT + Selects which layout is used for chip select 0. + 0 + 2 + read-write + + + CS1_SELECT + Selects which layout is used for chip select 1. + 0x2 + 2 + read-write + + + CS2_SELECT + Selects which layout is used for chip select 2. + 0x4 + 2 + read-write + + + CS3_SELECT + Selects which layout is used for chip select 3. + 0x6 + 2 + read-write + + + CS4_SELECT + Selects which layout is used for chip select 4. + 0x8 + 2 + read-write + + + CS5_SELECT + Selects which layout is used for chip select 5. + 0xA + 2 + read-write + + + CS6_SELECT + Selects which layout is used for chip select 6. + 0xC + 2 + read-write + + + CS7_SELECT + Selects which layout is used for chip select 7. + 0xE + 2 + read-write + + + CS8_SELECT + Selects which layout is used for chip select 8. + 0x10 + 2 + read-write + + + CS9_SELECT + Selects which layout is used for chip select 9. + 0x12 + 2 + read-write + + + CS10_SELECT + Selects which layout is used for chip select 10. + 0x14 + 2 + read-write + + + CS11_SELECT + Selects which layout is used for chip select 11. + 0x16 + 2 + read-write + + + CS12_SELECT + Selects which layout is used for chip select 12. + 0x18 + 2 + read-write + + + CS13_SELECT + Selects which layout is used for chip select 13. + 0x1A + 2 + read-write + + + CS14_SELECT + Selects which layout is used for chip select 14. + 0x1C + 2 + read-write + + + CS15_SELECT + Selects which layout is used for chip select 15. + 0x1E + 2 + read-write + + + + + LAYOUTSELECT_SET + Hardware ECC Accelerator Layout Select Register + 0x74 + 32 + read-write + 0xE4E4E4E4 + 0xFFFFFFFF + + + CS0_SELECT + Selects which layout is used for chip select 0. + 0 + 2 + read-write + + + CS1_SELECT + Selects which layout is used for chip select 1. + 0x2 + 2 + read-write + + + CS2_SELECT + Selects which layout is used for chip select 2. + 0x4 + 2 + read-write + + + CS3_SELECT + Selects which layout is used for chip select 3. + 0x6 + 2 + read-write + + + CS4_SELECT + Selects which layout is used for chip select 4. + 0x8 + 2 + read-write + + + CS5_SELECT + Selects which layout is used for chip select 5. + 0xA + 2 + read-write + + + CS6_SELECT + Selects which layout is used for chip select 6. + 0xC + 2 + read-write + + + CS7_SELECT + Selects which layout is used for chip select 7. + 0xE + 2 + read-write + + + CS8_SELECT + Selects which layout is used for chip select 8. + 0x10 + 2 + read-write + + + CS9_SELECT + Selects which layout is used for chip select 9. + 0x12 + 2 + read-write + + + CS10_SELECT + Selects which layout is used for chip select 10. + 0x14 + 2 + read-write + + + CS11_SELECT + Selects which layout is used for chip select 11. + 0x16 + 2 + read-write + + + CS12_SELECT + Selects which layout is used for chip select 12. + 0x18 + 2 + read-write + + + CS13_SELECT + Selects which layout is used for chip select 13. + 0x1A + 2 + read-write + + + CS14_SELECT + Selects which layout is used for chip select 14. + 0x1C + 2 + read-write + + + CS15_SELECT + Selects which layout is used for chip select 15. + 0x1E + 2 + read-write + + + + + LAYOUTSELECT_CLR + Hardware ECC Accelerator Layout Select Register + 0x78 + 32 + read-write + 0xE4E4E4E4 + 0xFFFFFFFF + + + CS0_SELECT + Selects which layout is used for chip select 0. + 0 + 2 + read-write + + + CS1_SELECT + Selects which layout is used for chip select 1. + 0x2 + 2 + read-write + + + CS2_SELECT + Selects which layout is used for chip select 2. + 0x4 + 2 + read-write + + + CS3_SELECT + Selects which layout is used for chip select 3. + 0x6 + 2 + read-write + + + CS4_SELECT + Selects which layout is used for chip select 4. + 0x8 + 2 + read-write + + + CS5_SELECT + Selects which layout is used for chip select 5. + 0xA + 2 + read-write + + + CS6_SELECT + Selects which layout is used for chip select 6. + 0xC + 2 + read-write + + + CS7_SELECT + Selects which layout is used for chip select 7. + 0xE + 2 + read-write + + + CS8_SELECT + Selects which layout is used for chip select 8. + 0x10 + 2 + read-write + + + CS9_SELECT + Selects which layout is used for chip select 9. + 0x12 + 2 + read-write + + + CS10_SELECT + Selects which layout is used for chip select 10. + 0x14 + 2 + read-write + + + CS11_SELECT + Selects which layout is used for chip select 11. + 0x16 + 2 + read-write + + + CS12_SELECT + Selects which layout is used for chip select 12. + 0x18 + 2 + read-write + + + CS13_SELECT + Selects which layout is used for chip select 13. + 0x1A + 2 + read-write + + + CS14_SELECT + Selects which layout is used for chip select 14. + 0x1C + 2 + read-write + + + CS15_SELECT + Selects which layout is used for chip select 15. + 0x1E + 2 + read-write + + + + + LAYOUTSELECT_TOG + Hardware ECC Accelerator Layout Select Register + 0x7C + 32 + read-write + 0xE4E4E4E4 + 0xFFFFFFFF + + + CS0_SELECT + Selects which layout is used for chip select 0. + 0 + 2 + read-write + + + CS1_SELECT + Selects which layout is used for chip select 1. + 0x2 + 2 + read-write + + + CS2_SELECT + Selects which layout is used for chip select 2. + 0x4 + 2 + read-write + + + CS3_SELECT + Selects which layout is used for chip select 3. + 0x6 + 2 + read-write + + + CS4_SELECT + Selects which layout is used for chip select 4. + 0x8 + 2 + read-write + + + CS5_SELECT + Selects which layout is used for chip select 5. + 0xA + 2 + read-write + + + CS6_SELECT + Selects which layout is used for chip select 6. + 0xC + 2 + read-write + + + CS7_SELECT + Selects which layout is used for chip select 7. + 0xE + 2 + read-write + + + CS8_SELECT + Selects which layout is used for chip select 8. + 0x10 + 2 + read-write + + + CS9_SELECT + Selects which layout is used for chip select 9. + 0x12 + 2 + read-write + + + CS10_SELECT + Selects which layout is used for chip select 10. + 0x14 + 2 + read-write + + + CS11_SELECT + Selects which layout is used for chip select 11. + 0x16 + 2 + read-write + + + CS12_SELECT + Selects which layout is used for chip select 12. + 0x18 + 2 + read-write + + + CS13_SELECT + Selects which layout is used for chip select 13. + 0x1A + 2 + read-write + + + CS14_SELECT + Selects which layout is used for chip select 14. + 0x1C + 2 + read-write + + + CS15_SELECT + Selects which layout is used for chip select 15. + 0x1E + 2 + read-write + + + + + FLASH0LAYOUT0 + Hardware BCH ECC Flash 0 Layout 0 Register + 0x80 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH0LAYOUT0_SET + Hardware BCH ECC Flash 0 Layout 0 Register + 0x84 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH0LAYOUT0_CLR + Hardware BCH ECC Flash 0 Layout 0 Register + 0x88 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH0LAYOUT0_TOG + Hardware BCH ECC Flash 0 Layout 0 Register + 0x8C + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH0LAYOUT1 + Hardware BCH ECC Flash 0 Layout 1 Register + 0x90 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH0LAYOUT1_SET + Hardware BCH ECC Flash 0 Layout 1 Register + 0x94 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH0LAYOUT1_CLR + Hardware BCH ECC Flash 0 Layout 1 Register + 0x98 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH0LAYOUT1_TOG + Hardware BCH ECC Flash 0 Layout 1 Register + 0x9C + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH1LAYOUT0 + Hardware BCH ECC Flash 1 Layout 0 Register + 0xA0 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH1LAYOUT0_SET + Hardware BCH ECC Flash 1 Layout 0 Register + 0xA4 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH1LAYOUT0_CLR + Hardware BCH ECC Flash 1 Layout 0 Register + 0xA8 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH1LAYOUT0_TOG + Hardware BCH ECC Flash 1 Layout 0 Register + 0xAC + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH1LAYOUT1 + Hardware BCH ECC Flash 1 Layout 1 Register + 0xB0 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH1LAYOUT1_SET + Hardware BCH ECC Flash 1 Layout 1 Register + 0xB4 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH1LAYOUT1_CLR + Hardware BCH ECC Flash 1 Layout 1 Register + 0xB8 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH1LAYOUT1_TOG + Hardware BCH ECC Flash 1 Layout 1 Register + 0xBC + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH2LAYOUT0 + Hardware BCH ECC Flash 2 Layout 0 Register + 0xC0 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH2LAYOUT0_SET + Hardware BCH ECC Flash 2 Layout 0 Register + 0xC4 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH2LAYOUT0_CLR + Hardware BCH ECC Flash 2 Layout 0 Register + 0xC8 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH2LAYOUT0_TOG + Hardware BCH ECC Flash 2 Layout 0 Register + 0xCC + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH2LAYOUT1 + Hardware BCH ECC Flash 2 Layout 1 Register + 0xD0 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH2LAYOUT1_SET + Hardware BCH ECC Flash 2 Layout 1 Register + 0xD4 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH2LAYOUT1_CLR + Hardware BCH ECC Flash 2 Layout 1 Register + 0xD8 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH2LAYOUT1_TOG + Hardware BCH ECC Flash 2 Layout 1 Register + 0xDC + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH3LAYOUT0 + Hardware BCH ECC Flash 3 Layout 0 Register + 0xE0 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH3LAYOUT0_SET + Hardware BCH ECC Flash 3 Layout 0 Register + 0xE4 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH3LAYOUT0_CLR + Hardware BCH ECC Flash 3 Layout 0 Register + 0xE8 + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH3LAYOUT0_TOG + Hardware BCH ECC Flash 3 Layout 0 Register + 0xEC + 32 + read-write + 0x70A4080 + 0xFFFFFFFF + + + DATA0_SIZE + Indicates the size of the data 0 block (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECC0 + Indicates the ECC level for the first block on the flash page + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + META_SIZE + Indicates the size of the metadata (in bytes) to be stored on a flash page + 0x10 + 8 + read-write + + + NBLOCKS + Number of subsequent blocks on the flash page (excluding the data0 block) + 0x18 + 8 + read-write + + + + + FLASH3LAYOUT1 + Hardware BCH ECC Flash 3 Layout 1 Register + 0xF0 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH3LAYOUT1_SET + Hardware BCH ECC Flash 3 Layout 1 Register + 0xF4 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH3LAYOUT1_CLR + Hardware BCH ECC Flash 3 Layout 1 Register + 0xF8 + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + FLASH3LAYOUT1_TOG + Hardware BCH ECC Flash 3 Layout 1 Register + 0xFC + 32 + read-write + 0x10DA4080 + 0xFFFFFFFF + + + DATAN_SIZE + Indicates the size of the subsequent data blocks (in DWORDS / four bytes) to be stored on the flash page + 0 + 10 + read-write + + + GF13_0_GF14_1 + Select GF13 or GF14: 0-GF13; 1-GF14 + 0xA + 1 + read-write + + + ECCN + Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n) + 0xB + 5 + read-write + + + NONE + No ECC to be performed + 0 + + + ECC2 + ECC 2 to be performed + 0x1 + + + ECC4 + ECC 4 to be performed + 0x2 + + + ECC6 + ECC 6 to be performed + 0x3 + + + ECC8 + ECC 8 to be performed + 0x4 + + + ECC10 + ECC 10 to be performed + 0x5 + + + ECC12 + ECC 12 to be performed + 0x6 + + + ECC14 + ECC 14 to be performed + 0x7 + + + ECC16 + ECC 16 to be performed + 0x8 + + + ECC18 + ECC 18 to be performed + 0x9 + + + ECC20 + ECC 20 to be performed + 0xA + + + ECC22 + ECC 22 to be performed + 0xB + + + ECC24 + ECC 24 to be performed + 0xC + + + ECC26 + ECC 26 to be performed + 0xD + + + ECC28 + ECC 28 to be performed + 0xE + + + ECC30 + ECC 30 to be performed + 0xF + + + ECC32 + ECC 32 to be performed + 0x10 + + + ECC34 + ECC 34 to be performed + 0x11 + + + ECC36 + ECC 36 to be performed + 0x12 + + + ECC38 + ECC 38 to be performed + 0x13 + + + ECC40 + ECC 40 to be performed + 0x14 + + + + + PAGE_SIZE + Indicates the total size of the flash page (in bytes) + 0x10 + 16 + read-write + + + + + DEBUG0 + Hardware BCH ECC Debug Register0 + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEBUG_REG_SELECT + The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine + 0 + 6 + read-write + + + RSVD0 + This field is reserved. + 0x6 + 2 + read-only + + + BM_KES_TEST_BYPASS + 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine + 0x8 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_STALL + Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete + 0x9 + 1 + read-write + + + NORMAL + KES FSM proceeds to next block supplied by bus master. + 0 + + + WAIT + KES FSM waits after current equations are solved and the search engine is started. + 0x1 + + + + + KES_DEBUG_STEP + Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block + 0xA + 1 + read-write + + + KES_STANDALONE + Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine + 0xB + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_KICK + Toggling causes KES engine FSM to start as if kick by the Bus Master + 0xC + 1 + read-write + + + KES_DEBUG_MODE4K + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages) + 0xD + 1 + read-write + + + 4k + Mode is set for 4K NAND pages. + 0x1 + + + + + KES_DEBUG_PAYLOAD_FLAG + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag + 0xE + 1 + read-write + + + DATA + Payload is set for 512 bytes data block. + 0x1 + + + + + KES_DEBUG_SHIFT_SYND + Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine + 0xF + 1 + read-write + + + KES_DEBUG_SYNDROME_SYMBOL + The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled + 0x10 + 9 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + RSVD1 + This field is reserved. + 0x19 + 7 + read-only + + + + + DEBUG0_SET + Hardware BCH ECC Debug Register0 + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEBUG_REG_SELECT + The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine + 0 + 6 + read-write + + + RSVD0 + This field is reserved. + 0x6 + 2 + read-only + + + BM_KES_TEST_BYPASS + 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine + 0x8 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_STALL + Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete + 0x9 + 1 + read-write + + + NORMAL + KES FSM proceeds to next block supplied by bus master. + 0 + + + WAIT + KES FSM waits after current equations are solved and the search engine is started. + 0x1 + + + + + KES_DEBUG_STEP + Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block + 0xA + 1 + read-write + + + KES_STANDALONE + Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine + 0xB + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_KICK + Toggling causes KES engine FSM to start as if kick by the Bus Master + 0xC + 1 + read-write + + + KES_DEBUG_MODE4K + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages) + 0xD + 1 + read-write + + + 4k + Mode is set for 4K NAND pages. + 0x1 + + + + + KES_DEBUG_PAYLOAD_FLAG + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag + 0xE + 1 + read-write + + + DATA + Payload is set for 512 bytes data block. + 0x1 + + + + + KES_DEBUG_SHIFT_SYND + Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine + 0xF + 1 + read-write + + + KES_DEBUG_SYNDROME_SYMBOL + The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled + 0x10 + 9 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + RSVD1 + This field is reserved. + 0x19 + 7 + read-only + + + + + DEBUG0_CLR + Hardware BCH ECC Debug Register0 + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEBUG_REG_SELECT + The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine + 0 + 6 + read-write + + + RSVD0 + This field is reserved. + 0x6 + 2 + read-only + + + BM_KES_TEST_BYPASS + 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine + 0x8 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_STALL + Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete + 0x9 + 1 + read-write + + + NORMAL + KES FSM proceeds to next block supplied by bus master. + 0 + + + WAIT + KES FSM waits after current equations are solved and the search engine is started. + 0x1 + + + + + KES_DEBUG_STEP + Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block + 0xA + 1 + read-write + + + KES_STANDALONE + Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine + 0xB + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_KICK + Toggling causes KES engine FSM to start as if kick by the Bus Master + 0xC + 1 + read-write + + + KES_DEBUG_MODE4K + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages) + 0xD + 1 + read-write + + + 4k + Mode is set for 4K NAND pages. + 0x1 + + + + + KES_DEBUG_PAYLOAD_FLAG + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag + 0xE + 1 + read-write + + + DATA + Payload is set for 512 bytes data block. + 0x1 + + + + + KES_DEBUG_SHIFT_SYND + Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine + 0xF + 1 + read-write + + + KES_DEBUG_SYNDROME_SYMBOL + The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled + 0x10 + 9 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + RSVD1 + This field is reserved. + 0x19 + 7 + read-only + + + + + DEBUG0_TOG + Hardware BCH ECC Debug Register0 + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DEBUG_REG_SELECT + The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine + 0 + 6 + read-write + + + RSVD0 + This field is reserved. + 0x6 + 2 + read-only + + + BM_KES_TEST_BYPASS + 1 = Point all SYND_GEN writes to dummy area at the end of the AUXILLIARY block so that diagnostics can preload all payload, parity bytes and computed syndrome bytes for test the KES engine + 0x8 + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_STALL + Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete + 0x9 + 1 + read-write + + + NORMAL + KES FSM proceeds to next block supplied by bus master. + 0 + + + WAIT + KES FSM waits after current equations are solved and the search engine is started. + 0x1 + + + + + KES_DEBUG_STEP + Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and completed processing a block + 0xA + 1 + read-write + + + KES_STANDALONE + Set to one, cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and suppress toggling the CF_BM_DONE signal by the CF engine + 0xB + 1 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + KES_DEBUG_KICK + Toggling causes KES engine FSM to start as if kick by the Bus Master + 0xC + 1 + read-write + + + KES_DEBUG_MODE4K + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages) + 0xD + 1 + read-write + + + 4k + Mode is set for 4K NAND pages. + 0x1 + + + + + KES_DEBUG_PAYLOAD_FLAG + When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag + 0xE + 1 + read-write + + + DATA + Payload is set for 512 bytes data block. + 0x1 + + + + + KES_DEBUG_SHIFT_SYND + Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine + 0xF + 1 + read-write + + + KES_DEBUG_SYNDROME_SYMBOL + The 9 bit value in this bit field shifts into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled + 0x10 + 9 + read-write + + + NORMAL + Bus master address generator for SYND_GEN writes operates normally. + 0 + + + TEST_MODE + Bus master address generator always addresses last four bytes in Auxiliary block. + 0x1 + + + + + RSVD1 + This field is reserved. + 0x19 + 7 + read-only + + + + + DBGKESREAD + KES Debug Read Register + 0x110 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + This register returns the ROM BIST CRC value after a BIST test. + 0 + 32 + read-only + + + + + DBGKESREAD_SET + KES Debug Read Register + 0x114 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + This register returns the ROM BIST CRC value after a BIST test. + 0 + 32 + read-only + + + + + DBGKESREAD_CLR + KES Debug Read Register + 0x118 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + This register returns the ROM BIST CRC value after a BIST test. + 0 + 32 + read-only + + + + + DBGKESREAD_TOG + KES Debug Read Register + 0x11C + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + This register returns the ROM BIST CRC value after a BIST test. + 0 + 32 + read-only + + + + + DBGCSFEREAD + Chien Search Debug Read Register + 0x120 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGCSFEREAD_SET + Chien Search Debug Read Register + 0x124 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGCSFEREAD_CLR + Chien Search Debug Read Register + 0x128 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGCSFEREAD_TOG + Chien Search Debug Read Register + 0x12C + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGSYNDGENREAD + Syndrome Generator Debug Read Register + 0x130 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGSYNDGENREAD_SET + Syndrome Generator Debug Read Register + 0x134 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGSYNDGENREAD_CLR + Syndrome Generator Debug Read Register + 0x138 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGSYNDGENREAD_TOG + Syndrome Generator Debug Read Register + 0x13C + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGAHBMREAD + Bus Master and ECC Controller Debug Read Register + 0x140 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGAHBMREAD_SET + Bus Master and ECC Controller Debug Read Register + 0x144 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGAHBMREAD_CLR + Bus Master and ECC Controller Debug Read Register + 0x148 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + DBGAHBMREAD_TOG + Bus Master and ECC Controller Debug Read Register + 0x14C + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUES + Reserved + 0 + 32 + read-only + + + + + BLOCKNAME + Block Name Register + 0x150 + 32 + read-only + 0x20484342 + 0xFFFFFFFF + + + NAME + The name is in the ASCII characters BCH (0x20, H, C, B). + 0 + 32 + read-only + + + + + BLOCKNAME_SET + Block Name Register + 0x154 + 32 + read-only + 0x20484342 + 0xFFFFFFFF + + + NAME + The name is in the ASCII characters BCH (0x20, H, C, B). + 0 + 32 + read-only + + + + + BLOCKNAME_CLR + Block Name Register + 0x158 + 32 + read-only + 0x20484342 + 0xFFFFFFFF + + + NAME + The name is in the ASCII characters BCH (0x20, H, C, B). + 0 + 32 + read-only + + + + + BLOCKNAME_TOG + Block Name Register + 0x15C + 32 + read-only + 0x20484342 + 0xFFFFFFFF + + + NAME + The name is in the ASCII characters BCH (0x20, H, C, B). + 0 + 32 + read-only + + + + + VERSION + BCH Version Register + 0x160 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value indicates the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value indicates the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + VERSION_SET + BCH Version Register + 0x164 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value indicates the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value indicates the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + VERSION_CLR + BCH Version Register + 0x168 + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value indicates the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value indicates the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + VERSION_TOG + BCH Version Register + 0x16C + 32 + read-only + 0x1000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value indicates the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value indicates the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + DEBUG1 + Hardware BCH ECC Debug Register 1 + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASED_ZERO_COUNT + The zero counts on one page. + 0 + 9 + read-only + + + RSVD + This field is reserved. + 0x9 + 22 + read-only + + + DEBUG1_PREERASECHK + Blank page enables pre-erase check. + 0x1F + 1 + read-write + + + DEBUG1_PREERASECHK_0 + Turn off pre-erase check + 0 + + + DEBUG1_PREERASECHK_1 + Turn on pre-erase check + 0x1 + + + + + + + DEBUG1_SET + Hardware BCH ECC Debug Register 1 + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASED_ZERO_COUNT + The zero counts on one page. + 0 + 9 + read-only + + + RSVD + This field is reserved. + 0x9 + 22 + read-only + + + DEBUG1_PREERASECHK + Blank page enables pre-erase check. + 0x1F + 1 + read-write + + + DEBUG1_PREERASECHK_0 + Turn off pre-erase check + 0 + + + DEBUG1_PREERASECHK_1 + Turn on pre-erase check + 0x1 + + + + + + + DEBUG1_CLR + Hardware BCH ECC Debug Register 1 + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASED_ZERO_COUNT + The zero counts on one page. + 0 + 9 + read-only + + + RSVD + This field is reserved. + 0x9 + 22 + read-only + + + DEBUG1_PREERASECHK + Blank page enables pre-erase check. + 0x1F + 1 + read-write + + + DEBUG1_PREERASECHK_0 + Turn off pre-erase check + 0 + + + DEBUG1_PREERASECHK_1 + Turn on pre-erase check + 0x1 + + + + + + + DEBUG1_TOG + Hardware BCH ECC Debug Register 1 + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + ERASED_ZERO_COUNT + The zero counts on one page. + 0 + 9 + read-only + + + RSVD + This field is reserved. + 0x9 + 22 + read-only + + + DEBUG1_PREERASECHK + Blank page enables pre-erase check. + 0x1F + 1 + read-write + + + DEBUG1_PREERASECHK_0 + Turn off pre-erase check + 0 + + + DEBUG1_PREERASECHK_1 + Turn on pre-erase check + 0x1 + + + + + + + + + SPDIF + SPDIF + SPDIF + SPDIF_ + 0x2004000 + + 0 + 0x54 + registers + + + SPDIF + 84 + + + + SCR + SPDIF Configuration Register + 0 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + USrc_Sel + no description available + 0 + 2 + read-write + + + USrc_Sel_0 + No embedded U channel + 0 + + + USrc_Sel_1 + U channel from SPDIF receive block (CD mode) + 0x1 + + + USrc_Sel_3 + U channel from on chip transmitter + 0x3 + + + + + TxSel + no description available + 0x2 + 3 + read-write + + + TxSel_0 + Off and output 0 + 0 + + + TxSel_1 + Feed-through SPDIFIN + 0x1 + + + TxSel_5 + Tx Normal operation + 0x5 + + + + + ValCtrl + no description available + 0x5 + 1 + read-write + + + ValCtrl_0 + Outgoing Validity always set + 0 + + + ValCtrl_1 + Outgoing Validity always clear + 0x1 + + + + + DMA_TX_En + DMA Transmit Request Enable (Tx FIFO empty) + 0x8 + 1 + read-write + + + DMA_Rx_En + DMA Receive Request Enable (RX FIFO full) + 0x9 + 1 + read-write + + + TxFIFO_Ctrl + no description available + 0xA + 2 + read-write + + + TxFIFO_Ctrl_0 + Send out digital zero on SPDIF Tx + 0 + + + TxFIFO_Ctrl_1 + Tx Normal operation + 0x1 + + + TxFIFO_Ctrl_2 + Reset to 1 sample remaining + 0x2 + + + + + soft_reset + When write 1 to this bit, it will cause SPDIF software reset + 0xC + 1 + read-write + + + LOW_POWER + When write 1 to this bit, it will cause SPDIF enter low-power mode + 0xD + 1 + read-write + + + TxFIFOEmpty_Sel + no description available + 0xF + 2 + read-write + + + TxFIFOEmpty_Sel_0 + Empty interrupt if 0 sample in Tx left and right FIFOs + 0 + + + TxFIFOEmpty_Sel_1 + Empty interrupt if at most 4 sample in Tx left and right FIFOs + 0x1 + + + TxFIFOEmpty_Sel_2 + Empty interrupt if at most 8 sample in Tx left and right FIFOs + 0x2 + + + TxFIFOEmpty_Sel_3 + Empty interrupt if at most 12 sample in Tx left and right FIFOs + 0x3 + + + + + TxAutoSync + no description available + 0x11 + 1 + read-write + + + TxAutoSync_0 + Tx FIFO auto sync off + 0 + + + TxAutoSync_1 + Tx FIFO auto sync on + 0x1 + + + + + RxAutoSync + no description available + 0x12 + 1 + read-write + + + RxAutoSync_0 + Rx FIFO auto sync off + 0 + + + RxAutoSync_1 + RxFIFO auto sync on + 0x1 + + + + + RxFIFOFull_Sel + no description available + 0x13 + 2 + read-write + + + RxFIFOFull_Sel_0 + Full interrupt if at least 1 sample in Rx left and right FIFOs + 0 + + + RxFIFOFull_Sel_1 + Full interrupt if at least 4 sample in Rx left and right FIFOs + 0x1 + + + RxFIFOFull_Sel_2 + Full interrupt if at least 8 sample in Rx left and right FIFOs + 0x2 + + + RxFIFOFull_Sel_3 + Full interrupt if at least 16 sample in Rx left and right FIFO + 0x3 + + + + + RxFIFO_Rst + no description available + 0x15 + 1 + read-write + + + RxFIFO_Rst_0 + Normal operation + 0 + + + RxFIFO_Rst_1 + Reset register to 1 sample remaining + 0x1 + + + + + RxFIFO_Off_On + no description available + 0x16 + 1 + read-write + + + RxFIFO_Off_On_0 + SPDIF Rx FIFO is on + 0 + + + RxFIFO_Off_On_1 + SPDIF Rx FIFO is off. Does not accept data from interface + 0x1 + + + + + RxFIFO_Ctrl + no description available + 0x17 + 1 + read-write + + + RxFIFO_Ctrl_0 + Normal operation + 0 + + + RxFIFO_Ctrl_1 + Always read zero from Rx data register + 0x1 + + + + + + + SRCD + CDText Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + USyncMode + no description available + 0x1 + 1 + read-write + + + USyncMode_0 + Non-CD data + 0 + + + USyncMode_1 + CD user channel subcode + 0x1 + + + + + + + SRPC + PhaseConfig Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + GainSel + Gain selection: + 0x3 + 3 + read-write + + + GainSel_0 + 24*(2**10) + 0 + + + GainSel_1 + 16*(2**10) + 0x1 + + + GainSel_2 + 12*(2**10) + 0x2 + + + GainSel_3 + 8*(2**10) + 0x3 + + + GainSel_4 + 6*(2**10) + 0x4 + + + GainSel_5 + 4*(2**10) + 0x5 + + + GainSel_6 + 3*(2**10) + 0x6 + + + + + LOCK + LOCK bit to show that the internal DPLL is locked, read only + 0x6 + 1 + read-only + + + ClkSrc_Sel + Clock source selection, all other settings not shown are reserved: + 0x7 + 4 + read-write + + + ClkSrc_Sel_0 + if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + 0 + + + ClkSrc_Sel_1 + if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + 0x1 + + + ClkSrc_Sel_3 + if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + 0x3 + + + ClkSrc_Sel_5 + REF_CLK_32K (XTALOSC) + 0x5 + + + ClkSrc_Sel_6 + tx_clk (SPDIF0_CLK_ROOT) + 0x6 + + + ClkSrc_Sel_8 + SPDIF_EXT_CLK + 0x8 + + + + + + + SIE + InterruptEn Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RxFIFOFul + SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. + 0 + 1 + read-write + + + TxEm + SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. + 0x1 + 1 + read-write + + + LockLoss + SPDIF receiver loss of lock + 0x2 + 1 + read-write + + + RxFIFOResyn + Rx FIFO resync + 0x3 + 1 + read-write + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 0x4 + 1 + read-write + + + UQErr + U/Q Channel framing error + 0x5 + 1 + read-write + + + UQSync + U/Q Channel sync found + 0x6 + 1 + read-write + + + QRxOv + Q Channel receive register overrun + 0x7 + 1 + read-write + + + QRxFul + Q Channel receive register full, can't be cleared with reg + 0x8 + 1 + read-write + + + URxOv + U Channel receive register overrun + 0x9 + 1 + read-write + + + URxFul + U Channel receive register full, can't be cleared with reg + 0xA + 1 + read-write + + + BitErr + SPDIF receiver found parity bit error + 0xE + 1 + read-write + + + SymErr + SPDIF receiver found illegal symbol + 0xF + 1 + read-write + + + ValNoGood + SPDIF validity flag no good + 0x10 + 1 + read-write + + + CNew + SPDIF receive change in value of control channel + 0x11 + 1 + read-write + + + TxResyn + SPDIF Tx FIFO resync + 0x12 + 1 + read-write + + + TxUnOv + SPDIF Tx FIFO under/overrun + 0x13 + 1 + read-write + + + Lock + SPDIF receiver's DPLL is locked + 0x14 + 1 + read-write + + + + + SIC + InterruptClear Register + SIC_SIS + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + LockLoss + SPDIF receiver loss of lock + 0x2 + 1 + write-only + + + RxFIFOResyn + Rx FIFO resync + 0x3 + 1 + write-only + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 0x4 + 1 + write-only + + + UQErr + U/Q Channel framing error + 0x5 + 1 + write-only + + + UQSync + U/Q Channel sync found + 0x6 + 1 + write-only + + + QRxOv + Q Channel receive register overrun + 0x7 + 1 + write-only + + + URxOv + U Channel receive register overrun + 0x9 + 1 + write-only + + + BitErr + SPDIF receiver found parity bit error + 0xE + 1 + write-only + + + SymErr + SPDIF receiver found illegal symbol + 0xF + 1 + write-only + + + ValNoGood + SPDIF validity flag no good + 0x10 + 1 + write-only + + + CNew + SPDIF receive change in value of control channel + 0x11 + 1 + write-only + + + TxResyn + SPDIF Tx FIFO resync + 0x12 + 1 + write-only + + + TxUnOv + SPDIF Tx FIFO under/overrun + 0x13 + 1 + write-only + + + Lock + SPDIF receiver's DPLL is locked + 0x14 + 1 + write-only + + + + + SIS + InterruptStat Register + SIC_SIS + 0x10 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + RxFIFOFul + SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. + 0 + 1 + read-only + + + TxEm + SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. + 0x1 + 1 + read-only + + + LockLoss + SPDIF receiver loss of lock + 0x2 + 1 + read-only + + + RxFIFOResyn + Rx FIFO resync + 0x3 + 1 + read-only + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 0x4 + 1 + read-only + + + UQErr + U/Q Channel framing error + 0x5 + 1 + read-only + + + UQSync + U/Q Channel sync found + 0x6 + 1 + read-only + + + QRxOv + Q Channel receive register overrun + 0x7 + 1 + read-only + + + QRxFul + Q Channel receive register full, can't be cleared with reg + 0x8 + 1 + read-only + + + URxOv + U Channel receive register overrun + 0x9 + 1 + read-only + + + URxFul + U Channel receive register full, can't be cleared with reg + 0xA + 1 + read-only + + + BitErr + SPDIF receiver found parity bit error + 0xE + 1 + read-only + + + SymErr + SPDIF receiver found illegal symbol + 0xF + 1 + read-only + + + ValNoGood + SPDIF validity flag no good + 0x10 + 1 + read-only + + + CNew + SPDIF receive change in value of control channel + 0x11 + 1 + read-only + + + TxResyn + SPDIF Tx FIFO resync + 0x12 + 1 + read-only + + + TxUnOv + SPDIF Tx FIFO under/overrun + 0x13 + 1 + read-only + + + Lock + SPDIF receiver's DPLL is locked + 0x14 + 1 + read-only + + + + + SRL + SPDIFRxLeft Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataLeft + Processor receive SPDIF data left + 0 + 24 + read-only + + + + + SRR + SPDIFRxRight Register + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataRight + Processor receive SPDIF data right + 0 + 24 + read-only + + + + + SRCSH + SPDIFRxCChannel_h Register + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_h + SPDIF receive C channel register, contains first 24 bits of C channel without interpretation + 0 + 24 + read-only + + + + + SRCSL + SPDIFRxCChannel_l Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_l + SPDIF receive C channel register, contains next 24 bits of C channel without interpretation + 0 + 24 + read-only + + + + + SRU + UchannelRx Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxUChannel + SPDIF receive U channel register, contains next 3 U channel bytes + 0 + 24 + read-only + + + + + SRQ + QchannelRx Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxQChannel + SPDIF receive Q channel register, contains next 3 Q channel bytes + 0 + 24 + read-only + + + + + STL + SPDIFTxLeft Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + TxDataLeft + SPDIF transmit left channel data. It is write-only, and always returns zeros when read + 0 + 24 + write-only + + + + + STR + SPDIFTxRight Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxDataRight + SPDIF transmit right channel data. It is write-only, and always returns zeros when read + 0 + 24 + write-only + + + + + STCSCH + SPDIFTxCChannelCons_h Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_h + SPDIF transmit Cons + 0 + 24 + read-write + + + + + STCSCL + SPDIFTxCChannelCons_l Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_l + SPDIF transmit Cons + 0 + 24 + read-write + + + + + SRFM + FreqMeas Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + FreqMeas + Frequency measurement data + 0 + 24 + read-only + + + + + STC + SPDIFTxClk Register + 0x50 + 32 + read-write + 0x20F00 + 0xFFFFFFFF + + + TxClk_DF + Divider factor (1-128) + 0 + 7 + read-write + + + TxClk_DF_0 + divider factor is 1 + 0 + + + TxClk_DF_1 + divider factor is 2 + 0x1 + + + TxClk_DF_127 + divider factor is 128 + 0x7F + + + + + tx_all_clk_en + Spdif transfer clock enable.When data is going to be transfered, this bit should be set to1. + 0x7 + 1 + read-write + + + tx_all_clk_en_0 + disable transfer clock. + 0 + + + tx_all_clk_en_1 + enable transfer clock. + 0x1 + + + + + TxClk_Source + no description available + 0x8 + 3 + read-write + + + TxClk_Source_0 + REF_CLK_32K input (XTALOSC 32 kHz clock) + 0 + + + TxClk_Source_1 + tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + 0x1 + + + TxClk_Source_3 + SPDIF_EXT_CLK, from pads + 0x3 + + + TxClk_Source_5 + ipg_clk input (frequency divided) + 0x5 + + + + + SYSCLK_DF + system clock divider factor, 2~512. + 0xB + 9 + read-write + + + SYSCLK_DF_0 + no clock signal + 0 + + + SYSCLK_DF_1 + divider factor is 2 + 0x1 + + + SYSCLK_DF_511 + divider factor is 512 + 0x1FF + + + + + + + + + ECSPI1 + ECSPI + ECSPI + ECSPI1_ + 0x2008000 + ECSPI + + 0 + 0x44 + registers + + + eCSPI1 + 63 + + + + RXDATA + Receive Data Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ECSPI_RXDATA + Receive Data + 0 + 32 + read-only + + + + + TXDATA + Transmit Data Register + 0x4 + 32 + write-only + 0 + 0xFFFFFFFF + + + ECSPI_TXDATA + Transmit Data + 0 + 32 + write-only + + + + + CONREG + Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + SPI Block Enable Control + 0 + 1 + read-write + + + EN_0 + Disable the block. + 0 + + + EN_1 + Enable the block. + 0x1 + + + + + HT + Hardware Trigger Enable + 0x1 + 1 + read-write + + + HT_0 + Disable HT mode. + 0 + + + HT_1 + Enable HT mode. + 0x1 + + + + + XCH + SPI Exchange Bit + 0x2 + 1 + read-write + + + XCH_0 + Idle. + 0 + + + XCH_1 + Initiates exchange (write) or busy (read). + 0x1 + + + + + SMC + Start Mode Control + 0x3 + 1 + read-write + + + SMC_0 + SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL descriptions. + 0 + + + SMC_1 + Immediately starts a SPI burst when data is written in TXFIFO. + 0x1 + + + + + CHANNEL_MODE + SPI CHANNEL MODE selects the mode for each SPI channel + 0x4 + 4 + read-write + + + CHANNEL_MODE_0 + Slave mode. + 0 + + + CHANNEL_MODE_1 + Master mode. + 0x1 + + + + + POST_DIVIDER + SPI Post Divider + 0x8 + 4 + read-write + + + POST_DIVIDER_0 + Divide by 1. + 0 + + + POST_DIVIDER_1 + Divide by 2. + 0x1 + + + POST_DIVIDER_2 + Divide by 4. + 0x2 + + + POST_DIVIDER_14 + Divide by 2 14 . + 0xE + + + POST_DIVIDER_15 + Divide by 2 15 . + 0xF + + + + + PRE_DIVIDER + SPI Pre Divider + 0xC + 4 + read-write + + + PRE_DIVIDER_0 + Divide by 1. + 0 + + + PRE_DIVIDER_1 + Divide by 2. + 0x1 + + + PRE_DIVIDER_2 + Divide by 3. + 0x2 + + + PRE_DIVIDER_13 + Divide by 14. + 0xD + + + PRE_DIVIDER_14 + Divide by 15. + 0xE + + + PRE_DIVIDER_15 + Divide by 16. + 0xF + + + + + DRCTL + SPI Data Ready Control + 0x10 + 2 + read-write + + + DRCTL_0 + The SPI_RDY signal is a don't care. + 0 + + + DRCTL_1 + Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered). + 0x1 + + + DRCTL_2 + Burst will be triggered by a low level of the SPI_RDY signal (level-triggered). + 0x2 + + + + + CHANNEL_SELECT + SPI CHANNEL SELECT bits + 0x12 + 2 + read-write + + + CHANNEL_SELECT_0 + Channel 0 is selected. Chip Select 0 (SS0) will be asserted. + 0 + + + CHANNEL_SELECT_1 + Channel 1 is selected. Chip Select 1 (SS1) will be asserted. + 0x1 + + + CHANNEL_SELECT_2 + Channel 2 is selected. Chip Select 2 (SS2) will be asserted. + 0x2 + + + CHANNEL_SELECT_3 + Channel 3 is selected. Chip Select 3 (SS3) will be asserted. + 0x3 + + + + + BURST_LENGTH + Burst Length + 0x14 + 12 + read-write + + + BURST_LENGTH_0 + A SPI burst contains the 1 LSB in a word. + 0 + + + BURST_LENGTH_1 + A SPI burst contains the 2 LSB in a word. + 0x1 + + + BURST_LENGTH_2 + A SPI burst contains the 3 LSB in a word. + 0x2 + + + BURST_LENGTH_31 + A SPI burst contains all 32 bits in a word. + 0x1F + + + BURST_LENGTH_32 + A SPI burst contains the 1 LSB in first word and all 32 bits in second word. + 0x20 + + + BURST_LENGTH_33 + A SPI burst contains the 2 LSB in first word and all 32 bits in second word. + 0x21 + + + BURST_LENGTH_4094 + A SPI burst contains the 31 LSB in first word and 2^7 -1 words. + 0xFFE + + + BURST_LENGTH_4095 + A SPI burst contains 2^7 words. + 0xFFF + + + + + + + CONFIGREG + Config Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SCLK_PHA + SPI Clock/Data Phase Control + 0 + 4 + read-write + + + SCLK_PHA_0 + Phase 0 operation. + 0 + + + SCLK_PHA_1 + Phase 1 operation. + 0x1 + + + + + SCLK_POL + SPI Clock Polarity Control + 0x4 + 4 + read-write + + + SCLK_POL_0 + Active high polarity (0 = Idle). + 0 + + + SCLK_POL_1 + Active low polarity (1 = Idle). + 0x1 + + + + + SS_CTL + SPI SS Wave Form Select + 0x8 + 4 + read-write + + + SS_CTL_0 + In master mode - only one SPI burst will be transmitted. + 0 + + + SS_CTL_1 + In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be transmitted. The SPI transfer will automatically stop when the TXFIFO is empty. + 0x1 + + + + + SS_POL + SPI SS Polarity Select + 0xC + 4 + read-write + + + SS_POL_0 + Active low. + 0 + + + SS_POL_1 + Active high. + 0x1 + + + + + DATA_CTL + DATA CTL + 0x10 + 4 + read-write + + + DATA_CTL_0 + Stay high. + 0 + + + DATA_CTL_1 + Stay low. + 0x1 + + + + + SCLK_CTL + SCLK CTL + 0x14 + 4 + read-write + + + SCLK_CTL_0 + Stay low. + 0 + + + SCLK_CTL_1 + Stay high. + 0x1 + + + + + HT_LENGTH + HT LENGTH + 0x18 + 5 + read-write + + + + + INTREG + Interrupt Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEEN + TXFIFO Empty Interrupt enable. This bit enables the TXFIFO Empty Interrupt. + 0 + 1 + read-write + + + TEEN_0 + Disable + 0 + + + TEEN_1 + Enable + 0x1 + + + + + TDREN + TXFIFO Data Request Interrupt enable + 0x1 + 1 + read-write + + + TDREN_0 + Disable + 0 + + + TDREN_1 + Enable + 0x1 + + + + + TFEN + TXFIFO Full Interrupt enable. This bit enables the TXFIFO Full Interrupt. + 0x2 + 1 + read-write + + + TFEN_0 + Disable + 0 + + + TFEN_1 + Enable + 0x1 + + + + + RREN + RXFIFO Ready Interrupt enable. This bit enables the RXFIFO Ready Interrupt. + 0x3 + 1 + read-write + + + RREN_0 + Disable + 0 + + + RREN_1 + Enable + 0x1 + + + + + RDREN + RXFIFO Data Request Interrupt enable + 0x4 + 1 + read-write + + + RDREN_0 + Disable + 0 + + + RDREN_1 + Enable + 0x1 + + + + + RFEN + RXFIFO Full Interrupt enable. This bit enables the RXFIFO Full Interrupt. + 0x5 + 1 + read-write + + + RFEN_0 + Disable + 0 + + + RFEN_1 + Enable + 0x1 + + + + + ROEN + RXFIFO Overflow Interrupt enable. This bit enables the RXFIFO Overflow Interrupt. + 0x6 + 1 + read-write + + + ROEN_0 + Disable + 0 + + + ROEN_1 + Enable + 0x1 + + + + + TCEN + Transfer Completed Interrupt enable. This bit enables the Transfer Completed Interrupt. + 0x7 + 1 + read-write + + + TCEN_0 + Disable + 0 + + + TCEN_1 + Enable + 0x1 + + + + + + + DMAREG + DMA Control Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_THRESHOLD + TX THRESHOLD + 0 + 6 + read-write + + + TEDEN + TXFIFO Empty DMA Request Enable. This bit enables/disables the TXFIFO Empty DMA Request. + 0x7 + 1 + read-write + + + TEDEN_0 + Disable + 0 + + + TEDEN_1 + Enable + 0x1 + + + + + RX_THRESHOLD + RX THRESHOLD + 0x10 + 6 + read-write + + + RXDEN + RXFIFO DMA Request Enable. This bit enables/disables the RXFIFO DMA Request. + 0x17 + 1 + read-write + + + RXDEN_0 + Disable + 0 + + + RXDEN_1 + Enable + 0x1 + + + + + RX_DMA_LENGTH + RX DMA LENGTH + 0x18 + 6 + read-write + + + RXTDEN + RXFIFO TAIL DMA Request/Interrupt Enable + 0x1F + 1 + read-write + + + RXTDEN_0 + Disable + 0 + + + RXTDEN_1 + Enable + 0x1 + + + + + + + STATREG + Status Register + 0x18 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + TE + TXFIFO Empty. This bit is set if the TXFIFO is empty. + 0 + 1 + read-only + + + TE_0 + TXFIFO contains one or more words. + 0 + + + TE_1 + TXFIFO is empty. + 0x1 + + + + + TDR + TXFIFO Data Request. + 0x1 + 1 + read-only + + + TDR_0 + Number of valid data slots in TXFIFO is greater than TX_THRESHOLD. + 0 + + + TDR_1 + Number of valid data slots in TXFIFO is not greater than TX_THRESHOLD. + 0x1 + + + + + TF + TXFIFO Full. This bit is set when if the TXFIFO is full. + 0x2 + 1 + read-only + + + TF_0 + TXFIFO is not Full. + 0 + + + TF_1 + TXFIFO is Full. + 0x1 + + + + + RR + RXFIFO Ready. This bit is set when one or more words are stored in the RXFIFO. + 0x3 + 1 + read-only + + + RR_0 + No valid data in RXFIFO. + 0 + + + RR_1 + More than 1 word in RXFIFO. + 0x1 + + + + + RDR + RXFIFO Data Request. + 0x4 + 1 + read-only + + + RDR_0 + When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + 0 + + + RDR_1 + When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists. + 0x1 + + + + + RF + RXFIFO Full. This bit is set when the RXFIFO is full. + 0x5 + 1 + read-only + + + RF_0 + Not Full. + 0 + + + RF_1 + Full. + 0x1 + + + + + RO + RXFIFO Overflow + 0x6 + 1 + read-write + oneToClear + + + RO_0 + RXFIFO has no overflow. + 0 + + + RO_1 + RXFIFO has overflowed. + 0x1 + + + + + TC + Transfer Completed Status bit. Writing 1 to this bit clears it. + 0x7 + 1 + read-write + oneToClear + + + TC_0 + Transfer in progress. + 0 + + + TC_1 + Transfer completed. + 0x1 + + + + + + + PERIODREG + Sample Period Control Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + SAMPLE_PERIOD + Sample Period Control + 0 + 15 + read-write + + + SAMPLE_PERIOD_0 + 0 wait states inserted + 0 + + + SAMPLE_PERIOD_1 + 1 wait state inserted + 0x1 + + + SAMPLE_PERIOD_32766 + 32766 wait states inserted + 0x7FFE + + + SAMPLE_PERIOD_32767 + 32767 wait states inserted + 0x7FFF + + + + + CSRC + Clock Source Control. This bit selects the clock source for the sample period counter. + 0xF + 1 + read-write + + + CSRC_0 + SPI Clock (SCLK) + 0 + + + CSRC_1 + Low-Frequency Reference Clock (32.768 KHz) + 0x1 + + + + + CSD_CTL + Chip Select Delay Control bits + 0x10 + 6 + read-write + + + + + TESTREG + Test Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXCNT + TXFIFO Counter. This field indicates the number of words in the TXFIFO. + 0 + 7 + read-write + + + RXCNT + RXFIFO Counter. This field indicates the number of words in the RXFIFO. + 0x8 + 7 + read-write + + + LBC + Loop Back Control + 0x1F + 1 + read-write + + + LBC_0 + Not connected. + 0 + + + LBC_1 + Transmitter and receiver sections internally connected for Loopback. + 0x1 + + + + + + + MSGDATA + Message Data Register + 0x40 + 32 + write-only + 0 + 0xFFFFFFFF + + + ECSPI_MSGDATA + ECSPI_MSGDATA holds the top word of MSG Data FIFO + 0 + 32 + write-only + + + + + + + ECSPI2 + ECSPI + ECSPI + ECSPI2_ + 0x200C000 + + 0 + 0x44 + registers + + + eCSPI2 + 64 + + + + ECSPI3 + ECSPI + ECSPI + ECSPI3_ + 0x2010000 + + 0 + 0x44 + registers + + + eCSPI3 + 65 + + + + ECSPI4 + ECSPI + ECSPI + ECSPI4_ + 0x2014000 + + 0 + 0x44 + registers + + + eCSPI4 + 66 + + + + UART1 + UARTv2 + UART + UART1_ + 0x2020000 + UART + + 0 + 0xBC + registers + + + UART1 + 58 + + + + URXD + UART Receiver Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RX_DATA + Received Data + 0 + 8 + read-only + + + PRERR + In RS-485 mode, it holds the ninth data bit (bit [8]) of received 9-bit RS-485 data In RS232/IrDA mode, it is the Parity Error flag + 0xA + 1 + read-only + + + PRERR_0 + = No parity error was detected for data in the RX_DATA field + 0 + + + PRERR_1 + = A parity error was detected for data in the RX_DATA field + 0x1 + + + + + BRK + BREAK Detect + 0xB + 1 + read-only + + + BRK_0 + The current character is not a BREAK character + 0 + + + BRK_1 + The current character is a BREAK character + 0x1 + + + + + FRMERR + Frame Error + 0xC + 1 + read-only + + + FRMERR_0 + The current character has no framing error + 0 + + + FRMERR_1 + The current character has a framing error + 0x1 + + + + + OVRRUN + Receiver Overrun + 0xD + 1 + read-only + + + OVRRUN_0 + No RxFIFO overrun was detected + 0 + + + OVRRUN_1 + A RxFIFO overrun was detected + 0x1 + + + + + ERR + Error Detect + 0xE + 1 + read-only + + + ERR_0 + No error status was detected + 0 + + + ERR_1 + An error status was detected + 0x1 + + + + + CHARRDY + Character Ready + 0xF + 1 + read-only + + + CHARRDY_0 + Character in RX_DATA field and associated flags are invalid. + 0 + + + CHARRDY_1 + Character in RX_DATA field and associated flags valid and ready for reading. + 0x1 + + + + + + + UTXD + UART Transmitter Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_DATA + Transmit Data + 0 + 8 + write-only + + + + + UCR1 + UART Control Register 1 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + UARTEN + UART Enable + 0 + 1 + read-write + + + UARTEN_0 + Disable the UART + 0 + + + UARTEN_1 + Enable the UART + 0x1 + + + + + DOZE + DOZE + 0x1 + 1 + read-write + + + DOZE_0 + The UART is enabled when in DOZE state + 0 + + + DOZE_1 + The UART is disabled when in DOZE state + 0x1 + + + + + ATDMAEN + Aging DMA Timer Enable + 0x2 + 1 + read-write + + + ATDMAEN_0 + Disable AGTIM DMA request + 0 + + + ATDMAEN_1 + Enable AGTIM DMA request + 0x1 + + + + + TXDMAEN + Transmitter Ready DMA Enable + 0x3 + 1 + read-write + + + TXDMAEN_0 + Disable transmit DMA request + 0 + + + TXDMAEN_1 + Enable transmit DMA request + 0x1 + + + + + SNDBRK + Send BREAK + 0x4 + 1 + read-write + + + SNDBRK_0 + Do not send a BREAK character + 0 + + + SNDBRK_1 + Send a BREAK character (continuous 0s) + 0x1 + + + + + RTSDEN + RTS Delta Interrupt Enable + 0x5 + 1 + read-write + + + RTSDEN_0 + Disable RTSD interrupt + 0 + + + RTSDEN_1 + Enable RTSD interrupt + 0x1 + + + + + TXMPTYEN + Transmitter Empty Interrupt Enable + 0x6 + 1 + read-write + + + TXMPTYEN_0 + Disable the transmitter FIFO empty interrupt + 0 + + + TXMPTYEN_1 + Enable the transmitter FIFO empty interrupt + 0x1 + + + + + IREN + Infrared Interface Enable + 0x7 + 1 + read-write + + + IREN_0 + Disable the IR interface + 0 + + + IREN_1 + Enable the IR interface + 0x1 + + + + + RXDMAEN + Receive Ready DMA Enable + 0x8 + 1 + read-write + + + RXDMAEN_0 + Disable DMA request + 0 + + + RXDMAEN_1 + Enable DMA request + 0x1 + + + + + RRDYEN + Receiver Ready Interrupt Enable + 0x9 + 1 + read-write + + + RRDYEN_0 + Disables the RRDY interrupt + 0 + + + RRDYEN_1 + Enables the RRDY interrupt + 0x1 + + + + + ICD + Idle Condition Detect + 0xA + 2 + read-write + + + ICD_0 + Idle for more than 4 frames + 0 + + + ICD_1 + Idle for more than 8 frames + 0x1 + + + ICD_2 + Idle for more than 16 frames + 0x2 + + + ICD_3 + Idle for more than 32 frames + 0x3 + + + + + IDEN + Idle Condition Detected Interrupt Enable + 0xC + 1 + read-write + + + IDEN_0 + Disable the IDLE interrupt + 0 + + + IDEN_1 + Enable the IDLE interrupt + 0x1 + + + + + TRDYEN + Transmitter Ready Interrupt Enable + 0xD + 1 + read-write + + + TRDYEN_0 + Disable the transmitter ready interrupt + 0 + + + TRDYEN_1 + Enable the transmitter ready interrupt + 0x1 + + + + + ADBR + Automatic Detection of Baud Rate + 0xE + 1 + read-write + + + ADBR_0 + Disable automatic detection of baud rate + 0 + + + ADBR_1 + Enable automatic detection of baud rate + 0x1 + + + + + ADEN + Automatic Baud Rate Detection Interrupt Enable + 0xF + 1 + read-write + + + ADEN_0 + Disable the automatic baud rate detection interrupt + 0 + + + ADEN_1 + Enable the automatic baud rate detection interrupt + 0x1 + + + + + + + UCR2 + UART Control Register 2 + 0x84 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + SRST + Software Reset + 0 + 1 + read-write + + + SRST_0 + Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3]. + 0 + + + SRST_1 + No reset + 0x1 + + + + + RXEN + Receiver Enable + 0x1 + 1 + read-write + + + RXEN_0 + Disable the receiver + 0 + + + RXEN_1 + Enable the receiver + 0x1 + + + + + TXEN + Transmitter Enable + 0x2 + 1 + read-write + + + TXEN_0 + Disable the transmitter + 0 + + + TXEN_1 + Enable the transmitter + 0x1 + + + + + ATEN + Aging Timer Enable. This bit is used to enable the aging timer interrupt (triggered with AGTIM) + 0x3 + 1 + read-write + + + ATEN_0 + AGTIM interrupt disabled + 0 + + + ATEN_1 + AGTIM interrupt enabled + 0x1 + + + + + RTSEN + Request to Send Interrupt Enable + 0x4 + 1 + read-write + + + RTSEN_0 + Disable request to send interrupt + 0 + + + RTSEN_1 + Enable request to send interrupt + 0x1 + + + + + WS + Word Size + 0x5 + 1 + read-write + + + WS_0 + 7-bit transmit and receive character length (not including START, STOP or PARITY bits) + 0 + + + WS_1 + 8-bit transmit and receive character length (not including START, STOP or PARITY bits) + 0x1 + + + + + STPB + Stop + 0x6 + 1 + read-write + + + STPB_0 + The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits. + 0 + + + STPB_1 + The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits. + 0x1 + + + + + PROE + Parity Odd/Even + 0x7 + 1 + read-write + + + PROE_0 + Even parity + 0 + + + PROE_1 + Odd parity + 0x1 + + + + + PREN + Parity Enable + 0x8 + 1 + read-write + + + PREN_0 + Disable parity generator and checker + 0 + + + PREN_1 + Enable parity generator and checker + 0x1 + + + + + RTEC + Request to Send Edge Control + 0x9 + 2 + read-write + + + RTEC_0 + Trigger interrupt on a rising edge + 0 + + + RTEC_1 + Trigger interrupt on a falling edge + 0x1 + + + + + ESCEN + Escape Enable. Enables/Disables the escape sequence detection logic. + 0xB + 1 + read-write + + + ESCEN_0 + Disable escape sequence detection + 0 + + + ESCEN_1 + Enable escape sequence detection + 0x1 + + + + + CTS + Clear to Send + 0xC + 1 + read-write + + + CTS_0 + The CTS_B pin is high (inactive) + 0 + + + CTS_1 + The CTS_B pin is low (active) + 0x1 + + + + + CTSC + CTS Pin Control + 0xD + 1 + read-write + + + CTSC_0 + The CTS_B pin is controlled by the CTS bit + 0 + + + CTSC_1 + The CTS_B pin is controlled by the receiver + 0x1 + + + + + IRTS + Ignore RTS Pin + 0xE + 1 + read-write + + + IRTS_0 + Transmit only when the RTS pin is asserted + 0 + + + IRTS_1 + Ignore the RTS pin + 0x1 + + + + + ESCI + Escape Sequence Interrupt Enable. Enables/Disables the ESCF bit to generate an interrupt. + 0xF + 1 + read-write + + + ESCI_0 + Disable the escape sequence interrupt + 0 + + + ESCI_1 + Enable the escape sequence interrupt + 0x1 + + + + + + + UCR3 + UART Control Register 3 + 0x88 + 32 + read-write + 0x700 + 0xFFFFFFFF + + + ACIEN + Autobaud Counter Interrupt Enable + 0 + 1 + read-write + + + ACIEN_0 + ACST interrupt disabled + 0 + + + ACIEN_1 + ACST interrupt enabled + 0x1 + + + + + INVT + Invert TXD output in RS-232/RS-485 mode, set TXD active level in IrDA mode + 0x1 + 1 + read-write + + + INVT_0 + TXD is not inverted + 0 + + + INVT_1 + TXD is inverted + 0x1 + + + + + RXDMUXSEL + RXD Muxed Input Selected + 0x2 + 1 + read-write + + + DTRDEN + Data Terminal Ready Delta Enable + 0x3 + 1 + read-write + + + DTRDEN_0 + Disable DTRD interrupt + 0 + + + DTRDEN_1 + Enable DTRD interrupt + 0x1 + + + + + AWAKEN + Asynchronous WAKE Interrupt Enable + 0x4 + 1 + read-write + + + AWAKEN_0 + Disable the AWAKE interrupt + 0 + + + AWAKEN_1 + Enable the AWAKE interrupt + 0x1 + + + + + AIRINTEN + Asynchronous IR WAKE Interrupt Enable + 0x5 + 1 + read-write + + + AIRINTEN_0 + Disable the AIRINT interrupt + 0 + + + AIRINTEN_1 + Enable the AIRINT interrupt + 0x1 + + + + + RXDSEN + Receive Status Interrupt Enable + 0x6 + 1 + read-write + + + RXDSEN_0 + Disable the RXDS interrupt + 0 + + + RXDSEN_1 + Enable the RXDS interrupt + 0x1 + + + + + ADNIMP + Autobaud Detection Not Improved- + 0x7 + 1 + read-write + + + ADNIMP_0 + Autobaud detection new features selected + 0 + + + ADNIMP_1 + Keep old autobaud detection mechanism + 0x1 + + + + + RI + Ring Indicator + 0x8 + 1 + read-write + + + RI_0 + RI_B pin is logic zero (DCE mode) + 0 + + + RI_1 + RI_B pin is logic one (DCE mode) + 0x1 + + + + + DCD + Data Carrier Detect + 0x9 + 1 + read-write + + + DCD_0 + DCD_B pin is logic zero (DCE mode) + 0 + + + DCD_1 + DCD_B pin is logic one (DCE mode) + 0x1 + + + + + DSR + Data Set Ready + 0xA + 1 + read-write + + + DSR_0 + DSR/ DTR pin is logic zero + 0 + + + DSR_1 + DSR/ DTR pin is logic one + 0x1 + + + + + FRAERREN + Frame Error Interrupt Enable + 0xB + 1 + read-write + + + FRAERREN_0 + Disable the frame error interrupt + 0 + + + FRAERREN_1 + Enable the frame error interrupt + 0x1 + + + + + PARERREN + Parity Error Interrupt Enable + 0xC + 1 + read-write + + + PARERREN_0 + Disable the parity error interrupt + 0 + + + PARERREN_1 + Enable the parity error interrupt + 0x1 + + + + + DTREN + Data Terminal Ready Interrupt Enable + 0xD + 1 + read-write + + + DTREN_0 + Data Terminal Ready Interrupt Disabled + 0 + + + DTREN_1 + Data Terminal Ready Interrupt Enabled + 0x1 + + + + + DPEC + DTR/DSR Interrupt Edge Control + 0xE + 2 + read-write + + + DPEC_0 + interrupt generated on rising edge + 0 + + + DPEC_1 + interrupt generated on falling edge + 0x1 + + + + + + + UCR4 + UART Control Register 4 + 0x8C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DREN + Receive Data Ready Interrupt Enable. Enables/Disables the RDR bit to generate an interrupt. + 0 + 1 + read-write + + + DREN_0 + Disable RDR interrupt + 0 + + + DREN_1 + Enable RDR interrupt + 0x1 + + + + + OREN + Receiver Overrun Interrupt Enable. Enables/Disables the ORE bit to generate an interrupt. + 0x1 + 1 + read-write + + + OREN_0 + Disable ORE interrupt + 0 + + + OREN_1 + Enable ORE interrupt + 0x1 + + + + + BKEN + BREAK Condition Detected Interrupt Enable. Enables/Disables the BRCD bit to generate an interrupt. + 0x2 + 1 + read-write + + + BKEN_0 + Disable the BRCD interrupt + 0 + + + BKEN_1 + Enable the BRCD interrupt + 0x1 + + + + + TCEN + Transmit Complete Interrupt Enable + 0x3 + 1 + read-write + + + TCEN_0 + Disable TXDC interrupt + 0 + + + TCEN_1 + Enable TXDC interrupt + 0x1 + + + + + LPBYP + Low Power Bypass. Allows to bypass the low power new features in UART. To use during debug phase. + 0x4 + 1 + read-write + + + LPBYP_0 + Low power features enabled + 0 + + + LPBYP_1 + Low power features disabled + 0x1 + + + + + IRSC + IR Special Case + 0x5 + 1 + read-write + + + IRSC_0 + The vote logic uses the sampling clock (16x baud rate) for normal operation + 0 + + + IRSC_1 + The vote logic uses the UART reference clock + 0x1 + + + + + IDDMAEN + DMA IDLE Condition Detected Interrupt Enable Enables/Disables the receive DMA request dma_req_rx for the IDLE interrupt (triggered with IDLE flag in USR2[12]) + 0x6 + 1 + read-write + + + IDDMAEN_0 + DMA IDLE interrupt disabled + 0 + + + IDDMAEN_1 + DMA IDLE interrupt enabled + 0x1 + + + + + WKEN + WAKE Interrupt Enable + 0x7 + 1 + read-write + + + WKEN_0 + Disable the WAKE interrupt + 0 + + + WKEN_1 + Enable the WAKE interrupt + 0x1 + + + + + ENIRI + Serial Infrared Interrupt Enable. Enables/Disables the serial infrared interrupt. + 0x8 + 1 + read-write + + + ENIRI_0 + Serial infrared Interrupt disabled + 0 + + + ENIRI_1 + Serial infrared Interrupt enabled + 0x1 + + + + + INVR + Invert RXD input in RS-232/RS-485 Mode, determine RXD input logic level being sampled in In IrDA mode + 0x9 + 1 + read-write + + + INVR_0 + RXD input is not inverted + 0 + + + INVR_1 + RXD input is inverted + 0x1 + + + + + CTSTL + CTS Trigger Level + 0xA + 6 + read-write + + + CTSTL_0 + 0 characters received + 0 + + + CTSTL_1 + 1 characters in the RxFIFO + 0x1 + + + CTSTL_32 + 32 characters in the RxFIFO (maximum) + 0x20 + + + + + + + UFCR + UART FIFO Control Register + 0x90 + 32 + read-write + 0x801 + 0xFFFFFFFF + + + RXTL + Receiver Trigger Level + 0 + 6 + read-write + + + RXTL_0 + 0 characters received + 0 + + + RXTL_1 + RxFIFO has 1 character + 0x1 + + + RXTL_31 + RxFIFO has 31 characters + 0x1F + + + RXTL_32 + RxFIFO has 32 characters (maximum) + 0x20 + + + + + DCEDTE + DCE/DTE mode select + 0x6 + 1 + read-write + + + DCEDTE_0 + DCE mode selected + 0 + + + DCEDTE_1 + DTE mode selected + 0x1 + + + + + RFDIV + Reference Frequency Divider + 0x7 + 3 + read-write + + + RFDIV_0 + Divide input clock by 6 + 0 + + + RFDIV_1 + Divide input clock by 5 + 0x1 + + + RFDIV_2 + Divide input clock by 4 + 0x2 + + + RFDIV_3 + Divide input clock by 3 + 0x3 + + + RFDIV_4 + Divide input clock by 2 + 0x4 + + + RFDIV_5 + Divide input clock by 1 + 0x5 + + + RFDIV_6 + Divide input clock by 7 + 0x6 + + + + + TXTL + Transmitter Trigger Level + 0xA + 6 + read-write + + + TXTL_2 + TxFIFO has 2 or fewer characters + 0x2 + + + TXTL_31 + TxFIFO has 31 or fewer characters + 0x1F + + + TXTL_32 + TxFIFO has 32 characters (maximum) + 0x20 + + + + + + + USR1 + UART Status Register 1 + 0x94 + 32 + read-write + 0x2040 + 0xFFFFFFFF + + + SAD + RS-485 Slave Address Detected Interrupt Flag + 0x3 + 1 + read-write + oneToClear + + + SAD_0 + No slave address detected + 0 + + + SAD_1 + Slave address detected + 0x1 + + + + + AWAKE + Asynchronous WAKE Interrupt Flag + 0x4 + 1 + read-write + oneToClear + + + AWAKE_0 + No falling edge was detected on the RXD Serial pin + 0 + + + AWAKE_1 + A falling edge was detected on the RXD Serial pin + 0x1 + + + + + AIRINT + Asynchronous IR WAKE Interrupt Flag + 0x5 + 1 + read-write + oneToClear + + + AIRINT_0 + No pulse was detected on the RXD IrDA pin + 0 + + + AIRINT_1 + A pulse was detected on the RXD IrDA pin + 0x1 + + + + + RXDS + Receiver IDLE Interrupt Flag + 0x6 + 1 + read-only + + + RXDS_0 + Receive in progress + 0 + + + RXDS_1 + Receiver is IDLE + 0x1 + + + + + DTRD + DTR Delta + 0x7 + 1 + read-write + oneToClear + + + DTRD_0 + DTR_B (DCE) or DSR_B (DTE) pin did not change state since last cleared + 0 + + + DTRD_1 + DTR_B (DCE) or DSR_B (DTE) pin changed state (write 1 to clear) + 0x1 + + + + + AGTIM + Ageing Timer Interrupt Flag + 0x8 + 1 + read-write + oneToClear + + + AGTIM_0 + AGTIM is not active + 0 + + + AGTIM_1 + AGTIM is active (write 1 to clear) + 0x1 + + + + + RRDY + Receiver Ready Interrupt / DMA Flag + 0x9 + 1 + read-only + + + RRDY_0 + No character ready + 0 + + + RRDY_1 + Character(s) ready (interrupt posted) + 0x1 + + + + + FRAMERR + Frame Error Interrupt Flag + 0xA + 1 + read-write + oneToClear + + + FRAMERR_0 + No frame error detected + 0 + + + FRAMERR_1 + Frame error detected (write 1 to clear) + 0x1 + + + + + ESCF + Escape Sequence Interrupt Flag + 0xB + 1 + read-write + oneToClear + + + ESCF_0 + No escape sequence detected + 0 + + + ESCF_1 + Escape sequence detected (write 1 to clear). + 0x1 + + + + + RTSD + RTS Delta + 0xC + 1 + read-write + oneToClear + + + RTSD_0 + RTS_B pin did not change state since last cleared + 0 + + + RTSD_1 + RTS_B pin changed state (write 1 to clear) + 0x1 + + + + + TRDY + Transmitter Ready Interrupt / DMA Flag + 0xD + 1 + read-only + + + TRDY_0 + The transmitter does not require data + 0 + + + TRDY_1 + The transmitter requires data (interrupt posted) + 0x1 + + + + + RTSS + RTS_B Pin Status + 0xE + 1 + read-only + + + RTSS_0 + The RTS_B module input is high (inactive) + 0 + + + RTSS_1 + The RTS_B module input is low (active) + 0x1 + + + + + PARITYERR + Parity Error Interrupt Flag + 0xF + 1 + read-write + oneToClear + + + PARITYERR_0 + No parity error detected + 0 + + + PARITYERR_1 + Parity error detected (write 1 to clear) + 0x1 + + + + + + + USR2 + UART Status Register 2 + 0x98 + 32 + read-write + 0x4028 + 0xFFFFFFFF + + + RDR + Receive Data Ready-Indicates that at least 1 character is received and written to the RxFIFO + 0 + 1 + read-only + + + RDR_0 + No receive data ready + 0 + + + RDR_1 + Receive data ready + 0x1 + + + + + ORE + Overrun Error + 0x1 + 1 + read-write + oneToClear + + + ORE_0 + No overrun error + 0 + + + ORE_1 + Overrun error (write 1 to clear) + 0x1 + + + + + BRCD + BREAK Condition Detected + 0x2 + 1 + read-write + oneToClear + + + BRCD_0 + No BREAK condition was detected + 0 + + + BRCD_1 + A BREAK condition was detected (write 1 to clear) + 0x1 + + + + + TXDC + Transmitter Complete + 0x3 + 1 + read-only + + + TXDC_0 + Transmit is incomplete + 0 + + + TXDC_1 + Transmit is complete + 0x1 + + + + + RTSF + RTS Edge Triggered Interrupt Flag + 0x4 + 1 + read-write + oneToClear + + + RTSF_0 + Programmed edge not detected on RTS_B + 0 + + + RTSF_1 + Programmed edge detected on RTS_B (write 1 to clear) + 0x1 + + + + + DCDIN + Data Carrier Detect Input + 0x5 + 1 + read-only + + + DCDIN_0 + Carrier signal Detected + 0 + + + DCDIN_1 + No Carrier signal Detected + 0x1 + + + + + DCDDELT + Data Carrier Detect Delta + 0x6 + 1 + read-write + oneToClear + + + DCDDELT_0 + Data Carrier Detect input has not changed state + 0 + + + DCDDELT_1 + Data Carrier Detect input has changed state (write 1 to clear) + 0x1 + + + + + WAKE + Wake + 0x7 + 1 + read-write + oneToClear + + + WAKE_0 + start bit not detected + 0 + + + WAKE_1 + start bit detected (write 1 to clear) + 0x1 + + + + + IRINT + Serial Infrared Interrupt Flag + 0x8 + 1 + read-write + oneToClear + + + IRINT_0 + no edge detected + 0 + + + IRINT_1 + valid edge detected (write 1 to clear) + 0x1 + + + + + RIIN + Ring Indicator Input + 0x9 + 1 + read-only + + + RIIN_0 + Ring Detected + 0 + + + RIIN_1 + No Ring Detected + 0x1 + + + + + RIDELT + Ring Indicator Delta + 0xA + 1 + read-write + oneToClear + + + RIDELT_0 + Ring Indicator input has not changed state + 0 + + + RIDELT_1 + Ring Indicator input has changed state (write 1 to clear) + 0x1 + + + + + ACST + Autobaud Counter Stopped + 0xB + 1 + read-write + oneToClear + + + ACST_0 + Measurement of bit length not finished (in autobaud) + 0 + + + ACST_1 + Measurement of bit length finished (in autobaud). (write 1 to clear) + 0x1 + + + + + IDLE + Idle Condition + 0xC + 1 + read-write + oneToClear + + + IDLE_0 + No idle condition detected + 0 + + + IDLE_1 + Idle condition detected (write 1 to clear) + 0x1 + + + + + DTRF + DTR edge triggered interrupt flag + 0xD + 1 + read-write + oneToClear + + + DTRF_0 + Programmed edge not detected on DTR/DSR + 0 + + + DTRF_1 + Programmed edge detected on DTR/DSR (write 1 to clear) + 0x1 + + + + + TXFE + Transmit Buffer FIFO Empty + 0xE + 1 + read-only + + + TXFE_0 + The transmit buffer (TxFIFO) is not empty + 0 + + + TXFE_1 + The transmit buffer (TxFIFO) is empty + 0x1 + + + + + ADET + Automatic Baud Rate Detect Complete + 0xF + 1 + read-write + oneToClear + + + ADET_0 + ASCII "A" or "a" was not received + 0 + + + ADET_1 + ASCII "A" or "a" was received (write 1 to clear) + 0x1 + + + + + + + UESC + UART Escape Character Register + 0x9C + 32 + read-write + 0x2B + 0xFFFFFFFF + + + ESC_CHAR + UART Escape Character + 0 + 8 + read-write + + + + + UTIM + UART Escape Timer Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIM + UART Escape Timer + 0 + 12 + read-write + + + + + UBIR + UART BRM Incremental Register + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + Incremental Numerator + 0 + 16 + read-write + + + + + UBMR + UART BRM Modulator Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MOD + Modulator Denominator + 0 + 16 + read-write + + + + + UBRC + UART Baud Rate Count Register + 0xAC + 32 + read-only + 0x4 + 0xFFFFFFFF + + + BCNT + Baud Rate Count Register + 0 + 16 + read-only + + + + + ONEMS + UART One Millisecond Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ONEMS + One Millisecond Register + 0 + 24 + read-write + + + + + UTS + UART Test Register + 0xB4 + 32 + read-write + 0x60 + 0xFFFFFFFF + + + SOFTRST + Software Reset. Indicates the status of the software reset (SRST_B bit of UCR2). + 0 + 1 + read-write + + + SOFTRST_0 + Software reset inactive + 0 + + + SOFTRST_1 + Software reset active + 0x1 + + + + + RXFULL + RxFIFO FULL. Indicates the RxFIFO is full. + 0x3 + 1 + read-write + + + RXFULL_0 + The RxFIFO is not full + 0 + + + RXFULL_1 + The RxFIFO is full + 0x1 + + + + + TXFULL + TxFIFO FULL. Indicates the TxFIFO is full. + 0x4 + 1 + read-write + + + TXFULL_0 + The TxFIFO is not full + 0 + + + TXFULL_1 + The TxFIFO is full + 0x1 + + + + + RXEMPTY + RxFIFO Empty. Indicates the RxFIFO is empty. + 0x5 + 1 + read-write + + + RXEMPTY_0 + The RxFIFO is not empty + 0 + + + RXEMPTY_1 + The RxFIFO is empty + 0x1 + + + + + TXEMPTY + TxFIFO Empty. Indicates that the TxFIFO is empty. + 0x6 + 1 + read-write + + + TXEMPTY_0 + The TxFIFO is not empty + 0 + + + TXEMPTY_1 + The TxFIFO is empty + 0x1 + + + + + RXDBG + RX_fifo_debug_mode. This bit controls the operation of the RX fifo read counter when in debug mode. + 0x9 + 1 + read-write + + + RXDBG_0 + rx fifo read pointer does not increment + 0 + + + RXDBG_1 + rx_fifo read pointer increments as normal + 0x1 + + + + + LOOPIR + Loop TX and RX for IR Test (LOOPIR) + 0xA + 1 + read-write + + + LOOPIR_0 + No IR loop + 0 + + + LOOPIR_1 + Connect IR transmitter to IR receiver + 0x1 + + + + + DBGEN + debug_enable_B. This bit controls whether to respond to the debug_req input signal. + 0xB + 1 + read-write + + + DBGEN_0 + UART will go into debug mode when debug_req is HIGH + 0 + + + DBGEN_1 + UART will not go into debug mode even if debug_req is HIGH + 0x1 + + + + + LOOP + Loop TX and RX for Test + 0xC + 1 + read-write + + + LOOP_0 + Normal receiver operation + 0 + + + LOOP_1 + Internally connect the transmitter output to the receiver input + 0x1 + + + + + FRCPERR + Force Parity Error + 0xD + 1 + read-write + + + FRCPERR_0 + Generate normal parity + 0 + + + FRCPERR_1 + Generate inverted parity (error) + 0x1 + + + + + + + UMCR + UART RS-485 Mode Control Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MDEN + 9-bit data or Multidrop Mode (RS-485) Enable. + 0 + 1 + read-write + + + MDEN_0 + Normal RS-232 or IrDA mode, see for detail. + 0 + + + MDEN_1 + Enable RS-485 mode, see for detail + 0x1 + + + + + SLAM + RS-485 Slave Address Detect Mode Selection. + 0x1 + 1 + read-write + + + SLAM_0 + Select Normal Address Detect mode + 0 + + + SLAM_1 + Select Automatic Address Detect mode + 0x1 + + + + + TXB8 + Transmit RS-485 bit 8 (the ninth bit or 9th bit) + 0x2 + 1 + read-write + + + TXB8_0 + 0 will be transmitted as the RS485 9th data bit + 0 + + + TXB8_1 + 1 will be transmitted as the RS485 9th data bit + 0x1 + + + + + SADEN + RS-485 Slave Address Detected Interrupt Enable. + 0x3 + 1 + read-write + + + SADEN_0 + Disable RS-485 Slave Address Detected Interrupt + 0 + + + SADEN_1 + Enable RS-485 Slave Address Detected Interrupt + 0x1 + + + + + SLADDR + RS-485 Slave Address Character + 0x8 + 8 + read-write + + + + + + + UART7 + UARTv2 + UART + UART7_ + 0x2018000 + + 0 + 0xBC + registers + + + UART7 + 71 + + + + UART2 + UARTv2 + UART + UART2_ + 0x21E8000 + + 0 + 0xBC + registers + + + UART2 + 59 + + + + UART3 + UARTv2 + UART + UART3_ + 0x21EC000 + + 0 + 0xBC + registers + + + UART3 + 60 + + + + UART4 + UARTv2 + UART + UART4_ + 0x21F0000 + + 0 + 0xBC + registers + + + UART4 + 61 + + + + UART5 + UARTv2 + UART + UART5_ + 0x21F4000 + + 0 + 0xBC + registers + + + UART5 + 62 + + + + UART6 + UARTv2 + UART + UART6_ + 0x21FC000 + + 0 + 0xBC + registers + + + UART6 + 49 + + + + UART8 + UARTv2 + UART + UART8_ + 0x2288000 + + 0 + 0xBC + registers + + + UART8 + 72 + + + + ESAI + Enhanced Serial Audio Interface + ESAI + ESAI_ + 0x2024000 + + 0 + 0x100 + registers + + + ESAI + 83 + + + + ETDR + ESAI Transmit Data Register + 0 + 32 + write-only + 0 + 0xFFFFFFFF + + + ETDR + ESAI Transmit Data Register + 0 + 32 + write-only + + + + + ERDR + ESAI Receive Data Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + ERDR + ESAI Receive Data Register + 0 + 32 + read-only + + + + + ECR + ESAI Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ESAIEN + ESAI Enable + 0 + 1 + read-write + + + ESAIEN_0 + ESAI disabled. + 0 + + + ESAIEN_1 + ESAI enabled. + 0x1 + + + + + ERST + ESAI Reset. Reset the ESAI core logic (including configuration registers) but not the ESAI FIFOs. + 0x1 + 1 + read-write + + + ERST_0 + ESAI not reset. + 0 + + + ERST_1 + ESAI reset. + 0x1 + + + + + ERO + EXTAL Receiver Out. Drive the EXTAL input on the High Frequency Receiver Clock pin. + 0x10 + 1 + read-write + + + ERO_0 + HCKR pin has normal function. + 0 + + + ERO_1 + EXTAL driven onto HCKR pin. + 0x1 + + + + + ERI + EXTAL Receiver In + 0x11 + 1 + read-write + + + ERI_0 + HCKR pin has normal function. + 0 + + + ERI_1 + EXTAL muxed into HCKR input. + 0x1 + + + + + ETO + EXTAL Transmitter Out. Drive the EXTAL input on the High Frequency Transmitter Clock pin. + 0x12 + 1 + read-write + + + ETO_0 + HCKT pin has normal function. + 0 + + + ETO_1 + EXTAL driven onto HCKT pin. + 0x1 + + + + + ETI + EXTAL Transmitter In + 0x13 + 1 + read-write + + + ETI_0 + HCKT pin has normal function. + 0 + + + ETI_1 + EXTAL muxed into HCKT input. + 0x1 + + + + + + + ESR + ESAI Status Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + RD + Receive Data. + 0 + 1 + read-only + + + RD_0 + RD is not the highest priority active interrupt. + 0 + + + RD_1 + RD is the highest priority active interrupt. + 0x1 + + + + + RED + Receive Even Data. + 0x1 + 1 + read-only + + + RED_0 + RED is not the highest priority active interrupt. + 0 + + + RED_1 + RED is the highest priority active interrupt. + 0x1 + + + + + RDE + Receive Data Exception. + 0x2 + 1 + read-only + + + RDE_0 + RDE is not the highest priority active interrupt. + 0 + + + RDE_1 + RDE is the highest priority active interrupt. + 0x1 + + + + + RLS + Receive Last Slot + 0x3 + 1 + read-only + + + RLS_0 + RLS is not the highest priority active interrupt. + 0 + + + RLS_1 + RLS is the highest priority active interrupt. + 0x1 + + + + + TD + Transmit Data. + 0x4 + 1 + read-only + + + TD_0 + TD is not the highest priority active interrupt. + 0 + + + TD_1 + TD is the highest priority active interrupt. + 0x1 + + + + + TED + Transmit Even Data. + 0x5 + 1 + read-only + + + TED_0 + TED is not the highest priority active interrupt. + 0 + + + TED_1 + TED is the highest priority active interrupt. + 0x1 + + + + + TDE + Transmit Data Exception. + 0x6 + 1 + read-only + + + TDE_0 + TDE is not the highest priority active interrupt. + 0 + + + TDE_1 + TDE is the highest priority active interrupt. + 0x1 + + + + + TLS + Transmit Last Slot + 0x7 + 1 + read-only + + + TLS_0 + TLS is not the highest priority active interrupt. + 0 + + + TLS_1 + TLS is the highest priority active interrupt. + 0x1 + + + + + TFE + Transmit FIFO Empty + 0x8 + 1 + read-only + + + TFE_0 + Number of empty slots in Transmit FIFO less than Transmit FIFO watermark. + 0 + + + TFE_1 + Number of empty slots in Transmit FIFO is equal to or greater than Transmit FIFO watermark. + 0x1 + + + + + RFF + Receive FIFO Full + 0x9 + 1 + read-only + + + RFF_0 + Number of words in Receive FIFO less than Receive FIFO watermark. + 0 + + + RFF_1 + Number of words in Receive FIFO is equal to or greater than Receive FIFO watermark. + 0x1 + + + + + TINIT + Transmit Initialization + 0xA + 1 + read-only + + + TINIT_0 + Transmitter has finished initializing the Transmit Data Registers (or Transmit FIFO is not enabled or Transmit Initialization is not enabled). + 0 + + + TINIT_1 + Transmitter has not finished initializing the Transmit Data Registers. + 0x1 + + + + + + + TFCR + Transmit FIFO Configuration Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFE + Transmit FIFO Enable. This bit enables the use of the Transmit FIFO. + 0 + 1 + read-write + + + TFE_0 + Transmit FIFO disabled. + 0 + + + TFE_1 + Transmit FIFO enabled. + 0x1 + + + + + TFR + Transmit FIFO Reset. This bit resets the Transmit FIFO pointers. + 0x1 + 1 + read-write + + + TFR_0 + Transmit FIFO not reset. + 0 + + + TFR_1 + Transmit FIFO reset. + 0x1 + + + + + TE0 + Transmitter #0 FIFO Enable + 0x2 + 1 + read-write + + + TE0_0 + Transmitter #0 is not using the Transmit FIFO. + 0 + + + TE0_1 + Transmitter #0 is using the Transmit FIFO. + 0x1 + + + + + TE1 + Transmitter #1 FIFO Enable + 0x3 + 1 + read-write + + + TE1_0 + Transmitter #1 is not using the Transmit FIFO. + 0 + + + TE1_1 + Transmitter #1 is using the Transmit FIFO. + 0x1 + + + + + TE2 + Transmitter #2 FIFO Enable + 0x4 + 1 + read-write + + + TE2_0 + Transmitter #2 is not using the Transmit FIFO. + 0 + + + TE2_1 + Transmitter #2 is using the Transmit FIFO. + 0x1 + + + + + TE3 + Transmitter #3 FIFO Enable + 0x5 + 1 + read-write + + + TE3_0 + Transmitter #3 is not using the Transmit FIFO. + 0 + + + TE3_1 + Transmitter #3 is using the Transmit FIFO. + 0x1 + + + + + TE4 + Transmitter #4 FIFO Enable + 0x6 + 1 + read-write + + + TE4_0 + Transmitter #4 is not using the Transmit FIFO. + 0 + + + TE4_1 + Transmitter #4 is using the Transmit FIFO. + 0x1 + + + + + TE5 + Transmitter #5 FIFO Enable + 0x7 + 1 + read-write + + + TE5_0 + Transmitter #5 is not using the Transmit FIFO. + 0 + + + TE5_1 + Transmitter #5 is using the Transmit FIFO. + 0x1 + + + + + TFWM + Transmit FIFO Watermark + 0x8 + 8 + read-write + + + TWA + Transmit Word Alignment + 0x10 + 3 + read-write + + + TWA_0 + MSB of data is bit 31. Data bits 7-0 are ignored when passed to transmit shift register. + 0 + + + TWA_1 + MSB of data is bit 27. Data bits 3-0 are ignored when passed to transmit shift register. + 0x1 + + + TWA_2 + MSB of data is bit 23. + 0x2 + + + TWA_3 + MSB of data is bit 19. Bottom 4 bits of transmit shift register are zeroed. + 0x3 + + + TWA_4 + MSB of data is bit 15. Bottom 8 bits of transmit shift register are zeroed. + 0x4 + + + TWA_5 + MSB of data is bit 11. Bottom 12 bits of transmit shift register are zeroed. + 0x5 + + + TWA_6 + MSB of data is bit 7. Bottom 16 bits of transmit shift register are zeroed. + 0x6 + + + TWA_7 + MSB of data is bit 3. Bottom 20 bits of transmit shift register are zeroed. + 0x7 + + + + + TIEN + Transmitter Initialization Enable + 0x13 + 1 + read-write + + + TIEN_0 + Transmit Data Registers are not initialized from the FIFO once the Transmit FIFO is enabled. Software must manually initialize the Transmit Data Registers separately. + 0 + + + TIEN_1 + Transmit Data Registers are initialized from the FIFO once the Transmit FIFO is enabled. + 0x1 + + + + + TAENB + Tx FIFO Align Enable + 0x14 + 1 + read-write + + + TFIN + Tx FIFO Interrupt Enable + 0x15 + 1 + read-write + + + + + TFSR + Transmit FIFO Status Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + TFCNT + Transmit FIFO Counter. These bits indicate the number of data words stored in the Transmit FIFO. + 0 + 8 + read-only + + + NTFI + Next Transmitter FIFO In. Indicates which transmitter receives the next word written to the FIFO. + 0x8 + 3 + read-only + + + NTFI_0 + Transmitter #0 receives next word written to the Transmit FIFO. + 0 + + + NTFI_1 + Transmitter #1 receives next word written to the Transmit FIFO. + 0x1 + + + NTFI_2 + Transmitter #2 receives next word written to the Transmit FIFO. + 0x2 + + + NTFI_3 + Transmitter #3 receives next word written to the Transmit FIFO. + 0x3 + + + NTFI_4 + Transmitter #4 receives next word written to the Transmit FIFO. + 0x4 + + + NTFI_5 + Transmitter #5 receives next word written to the Transmit FIFO. + 0x5 + + + + + NTFO + Next Transmitter FIFO Out + 0xC + 3 + read-only + + + NTFO_0 + Transmitter #0 receives next word from the Transmit FIFO. + 0 + + + NTFO_1 + Transmitter #1 receives next word from the Transmit FIFO. + 0x1 + + + NTFO_2 + Transmitter #2 receives next word from the Transmit FIFO. + 0x2 + + + NTFO_3 + Transmitter #3 receives next word from the Transmit FIFO. + 0x3 + + + NTFO_4 + Transmitter #4 receives next word from the Transmit FIFO. + 0x4 + + + NTFO_5 + Transmitter #5 receives next word from the Transmit FIFO. + 0x5 + + + + + + + RFCR + Receive FIFO Configuration Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + RFE + Receive FIFO Enable. This bit enables the use of the Receive FIFO. + 0 + 1 + read-write + + + RFE_0 + Receive FIFO disabled. + 0 + + + RFE_1 + Receive FIFO enabled. + 0x1 + + + + + RFR + Receive FIFO Reset. This bit resets the Receive FIFO pointers. + 0x1 + 1 + read-write + + + RFR_0 + Receive FIFO not reset. + 0 + + + RFR_1 + Receive FIFO reset. + 0x1 + + + + + RE0 + Receiver #0 FIFO Enable + 0x2 + 1 + read-write + + + RE0_0 + Receiver #0 is not using the Receive FIFO. + 0 + + + RE0_1 + Receiver #0 is using the Receive FIFO. + 0x1 + + + + + RE1 + Receiver #1 FIFO Enable + 0x3 + 1 + read-write + + + RE1_0 + Receiver #1 is not using the Receive FIFO. + 0 + + + RE1_1 + Receiver #1 is using the Receive FIFO. + 0x1 + + + + + RE2 + Receiver #2 FIFO Enable + 0x4 + 1 + read-write + + + RE2_0 + Receiver #2 is not using the Receive FIFO. + 0 + + + RE2_1 + Receiver #2 is using the Receive FIFO. + 0x1 + + + + + RE3 + Receiver #3 FIFO Enable + 0x5 + 1 + read-write + + + RE3_0 + Receiver #3 is not using the Receive FIFO. + 0 + + + RE3_1 + Receiver #3 is using the Receive FIFO. + 0x1 + + + + + RFWM + Receive FIFO Watermark + 0x8 + 8 + read-write + + + RWA + Receive Word Alignment + 0x10 + 3 + read-write + + + RWA_0 + MSB of data is at bit 31. Data bits 7-0 are zeroed. + 0 + + + RWA_1 + MSB of data is at bit 27. Data bits 3-0 are zeroed. + 0x1 + + + RWA_2 + MSB of data is at bit 23. + 0x2 + + + RWA_3 + MSB of data is at bit 19. Data bits 3-0 from receive shift register are ignored. + 0x3 + + + RWA_4 + MSB of data is at bit 15. Data bits 7-0 from receive shift register are ignored. + 0x4 + + + RWA_5 + MSB of data is at bit 11. Data bits 11-0 from receive shift register are ignored. + 0x5 + + + RWA_6 + MSB of data is at bit 7. Data bits 15-0 from receive shift register are ignored. + 0x6 + + + RWA_7 + MSB of data is at bit 3. Data bits 19-0 from receive shift register are ignored. + 0x7 + + + + + REXT + Receive Extension + 0x13 + 1 + read-write + + + REXT_0 + Receive data is zero extended. + 0 + + + REXT_1 + Receive data is sign extended. + 0x1 + + + + + RAENB + Rx FIFO Align Enable + 0x14 + 1 + read-write + + + RFIN + Rx FIFO Interrupt Enable + 0x15 + 1 + read-write + + + + + RFSR + Receive FIFO Status Register + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + RFCNT + Receive FIFO Counter. These bits indicate the number of data words stored in the Receive FIFO. + 0 + 8 + read-only + + + NRFO + Next Receiver FIFO Out. Indicates which receiver returns the top word of the Receive FIFO. + 0x8 + 2 + read-only + + + NRFO_0 + Receiver #0 returns next word from the Receive FIFO. + 0 + + + NRFO_1 + Receiver #1 returns next word from the Receive FIFO. + 0x1 + + + NRFO_2 + Receiver #2 returns next word from the Receive FIFO. + 0x2 + + + NRFO_3 + Receiver #3 returns next word from the Receive FIFO. + 0x3 + + + + + NRFI + Next Receiver FIFO In + 0xC + 2 + read-only + + + NRFI_0 + Receiver #0 returns next word to the Receive FIFO. + 0 + + + NRFI_1 + Receiver #1 returns next word to the Receive FIFO. + 0x1 + + + NRFI_2 + Receiver #2 returns next word to the Receive FIFO. + 0x2 + + + NRFI_3 + Receiver #3 returns next word to the Receive FIFO. + 0x3 + + + + + + + 6 + 0x4 + TX%s + Transmit Data Register n + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXn + Stores the data to be transmitted and is automatically transferred to the transmit shift registers + 0 + 24 + write-only + + + + + TSR + ESAI Transmit Slot Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSR + The write-only Transmit Slot Register (ESAI_TSR) is effectively a null data register that is used when the data is not to be transmitted in the available transmit time slot + 0 + 24 + write-only + + + + + 4 + 0x4 + RX%s + Receive Data Register n + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RXn + Accept data from the receive shift registers when they become full See ESAI Receive Shift Registers + 0 + 24 + read-only + + + + + SAISR + Serial Audio Interface Status Register + 0xCC + 32 + read-only + 0 + 0xFFFFFFFF + + + IF0 + ESAI_SAISR Serial Input Flag 0 + 0 + 1 + read-only + + + IF1 + ESAI_SAISR Serial Inout Flag 1 + 0x1 + 1 + read-only + + + IF2 + ESAI_SAISR Serial Input Flag 2 + 0x2 + 1 + read-only + + + RFS + ESAI_SAISR Receive Frame Sync Flag + 0x6 + 1 + read-only + + + ROE + ESAI_SAISR Receive Overrun Error Flag + 0x7 + 1 + read-only + + + RDF + ESAI_SAISR Receive Data Register Full + 0x8 + 1 + read-only + + + REDF + ESAI_SAISR Receive Even-Data Register Full + 0x9 + 1 + read-only + + + RODF + ESAI_SAISR Receive Odd-Data Register Full + 0xA + 1 + read-only + + + TFS + ESAI_SAISR Transmit Frame Sync Flag + 0xD + 1 + read-only + + + TUE + ESAI_SAISR Transmit Underrun Error Flag + 0xE + 1 + read-only + + + TDE + ESAI_SAISR Transmit Data Register Empty + 0xF + 1 + read-only + + + TEDE + ESAI_SAISR Transmit Even-DataRegister Empty + 0x10 + 1 + read-only + + + TODFE + ESAI_SAISR Transmit Odd-Data Register Empty + 0x11 + 1 + read-only + + + + + SAICR + Serial Audio Interface Control Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OF0 + ESAI_SAICR Serial Output Flag 0 + 0 + 1 + read-write + + + OF1 + ESAI_SAICR Serial Output Flag 1 + 0x1 + 1 + read-write + + + OF2 + ESAI_SAICR Serial Output Flag 2 + 0x2 + 1 + read-write + + + SYN + ESAI_SAICR Synchronous Mode Selection + 0x6 + 1 + read-write + + + TEBE + ESAI_SAICR Transmit External Buffer Enable + 0x7 + 1 + read-write + + + ALC + ESAI_SAICR Alignment Control + 0x8 + 1 + read-write + + + + + TCR + Transmit Control Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TE0 + ESAI_TCR ESAI Transmit 0 Enable + 0 + 1 + read-write + + + TE1 + ESAI_TCR ESAI Transmit 1 Enable + 0x1 + 1 + read-write + + + TE2 + ESAI_TCR ESAI Transmit 2 Enable + 0x2 + 1 + read-write + + + TE3 + ESAI_TCR ESAI Transmit 3 Enable + 0x3 + 1 + read-write + + + TE4 + ESAI_TCR ESAI Transmit 4 Enable + 0x4 + 1 + read-write + + + TE5 + ESAI_TCR ESAI Transmit 5 Enable + 0x5 + 1 + read-write + + + TSHFD + ESAI_TCR Transmit Shift Direction + 0x6 + 1 + read-write + + + TWA + ESAI_TCR Transmit Word Alignment Control + 0x7 + 1 + read-write + + + TMOD + ESAI_TCR Transmit Network Mode Control (TMOD1-TMOD0) + 0x8 + 2 + read-write + + + TSWS + ESAI_TCR Tx Slot and Word Length Select (TSWS4-TSWS0) + 0xA + 5 + read-write + + + TFSL + ESAI_TCR Transmit Frame Sync Length + 0xF + 1 + read-write + + + TFSR + ESAI_TCR Transmit Frame Sync Relative Timing + 0x10 + 1 + read-write + + + PADC + ESAI_TCR Transmit Zero Padding Control + 0x11 + 1 + read-write + + + TPR + ESAI_TCR Transmit Section Personal Reset + 0x13 + 1 + read-write + + + TEIE + ESAI_TCR Transmit Exception Interrupt Enable + 0x14 + 1 + read-write + + + TEDIE + ESAI_TCR Transmit Even Slot Data Interrupt Enable + 0x15 + 1 + read-write + + + TIE + ESAI_TCR Transmit Interrupt Enable + 0x16 + 1 + read-write + + + TLIE + ESAI_TCR Transmit Last Slot Interrupt Enable + 0x17 + 1 + read-write + + + + + TCCR + Transmit Clock Control Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPM + ESAI_TCCR Transmit Prescale Modulus Select + 0 + 8 + read-write + + + TPSR + ESAI_TCCR Transmit Prescaler Range + 0x8 + 1 + read-write + + + TDC + ESAI_TCCR Tx Frame Rate Divider Control + 0x9 + 5 + read-write + + + TFP + ESAI_TCCR Tx High Frequency Clock Divider + 0xE + 4 + read-write + + + TCKP + ESAI_TCCR Transmit Clock Polarity + 0x12 + 1 + read-write + + + TFSP + ESAI_TCCR Transmit Frame Sync Polarity + 0x13 + 1 + read-write + + + THCKP + ESAI_TCCR Transmit High Frequency Clock Polarity The Transmitter High Frequency Clock Polarity (THCKP) bit controls the polarity of the HCKT + 0x14 + 1 + read-write + + + TCKD + ESAI_TCCR Transmit Clock Source Direction + 0x15 + 1 + read-write + + + TFSD + ESAI_TCCR Transmit Frame Sync Signal Direction + 0x16 + 1 + read-write + + + THCKD + ESAI_TCCR Transmit High Frequency Clock Direction + 0x17 + 1 + read-write + + + + + RCR + Receive Control Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + RE0 + ESAI_RCR ESAI Receiver 0 Enable + 0 + 1 + read-write + + + RE1 + ESAI_RCR ESAI Receiver 1 Enable + 0x1 + 1 + read-write + + + RE2 + ESAI_RCR ESAI Receiver 2 Enable + 0x2 + 1 + read-write + + + RE3 + ESAI_RCR ESAI Receiver 3 Enable + 0x3 + 1 + read-write + + + RSHFD + ESAI_RCR Receiver Shift Direction + 0x6 + 1 + read-write + + + RWA + ESAI_RCR Receiver Word Alignment Control + 0x7 + 1 + read-write + + + RMOD + ESAI_RCR Receiver Network Mode Control + 0x8 + 2 + read-write + + + RSWS + ESAI_RCR Receiver Slot and Word Select + 0xA + 5 + read-write + + + RFSL + ESAI_RCR Receiver Frame Sync Length + 0xF + 1 + read-write + + + RFSR + ESAI_RCR Receiver Frame Sync Relative Timing + 0x10 + 1 + read-write + + + RPR + ESAI_RCR Receiver Section Personal Reset + 0x13 + 1 + read-write + + + REIE + ESAI_RCR Receive Exception Interrupt Enable + 0x14 + 1 + read-write + + + REDIE + ESAI_RCR Receive Even Slot Data Interrupt Enable + 0x15 + 1 + read-write + + + RIE + ESAI_RCR Receive Interrupt Enable + 0x16 + 1 + read-write + + + RLIE + ESAI_RCR Receive Last Slot Interrupt Enable + 0x17 + 1 + read-write + + + + + RCCR + Receive Clock Control Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RPM + ESAI_RCCR Receiver Prescale Modulus Select + 0 + 8 + read-write + + + RPSR + ESAI_RCCR Receiver Prescaler Range + 0x8 + 1 + read-write + + + RDC + ESAI_RCCR Rx Frame Rate Divider Control + 0x9 + 5 + read-write + + + RFP + ESAI_RCCR Rx High Frequency Clock Divider + 0xE + 4 + read-write + + + RCKP + The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in + 0x12 + 1 + read-write + + + RFSP + ESAI_RCCR Receiver Frame Sync Polarity + 0x13 + 1 + read-write + + + RHCKP + ESAI_RCCR Receiver High Frequency Clock Polarity + 0x14 + 1 + read-write + + + RCKD + ESAI_RCCR Receiver Clock Source Direction + 0x15 + 1 + read-write + + + RFSD + ESAI_RCCR Receiver Frame Sync Signal Direction + 0x16 + 1 + read-write + + + RHCKD + ESAI_RCCR Receiver High Frequency Clock Direction + 0x17 + 1 + read-write + + + + + TSMA + Transmit Slot Mask Register A + 0xE4 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + TS + Lower 16 bits of TS + 0 + 16 + read-write + + + + + TSMB + Transmit Slot Mask Register B + 0xE8 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + TS + When bit number N in ESAI_TSMB is cleared, all the transmit data pins of the enabled transmitters are tri-stated during transmit time slot number N + 0 + 16 + read-write + + + + + RSMA + Receive Slot Mask Register A + 0xEC + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + RS + When bit number N in the ESAI_RSMA register is cleared, the data from the enabled receivers input pins are shifted into their receive shift registers during slot number N + 0 + 16 + read-write + + + + + RSMB + Receive Slot Mask Register B + 0xF0 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + RS + When bit number N in the ESAI_RSMB register is cleared, the data from the enabled receivers input pins are shifted into their receive shift registers during slot number N + 0 + 16 + read-write + + + + + PRRC + Port C Direction Register + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDC + See . + 0 + 12 + read-write + + + + + PCRC + Port C Control Register + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + PC + See . + 0 + 12 + read-write + + + + + + + I2S1 + Inter-IC Sound / Synchronous Audio Interface + I2S + I2S1_ + 0x2028000 + I2S + + 0 + 0xE4 + registers + + + SAI1 + 129 + + + + TCSR + SAI Transmit Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 0x1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 0x8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 0x9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 0xA + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 0xB + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 0xC + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 0x10 + 1 + read-only + + + FRF_0 + Transmit FIFO watermark has not been reached. + 0 + + + FRF_1 + Transmit FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 0x11 + 1 + read-only + + + FWF_0 + No enabled transmit FIFO is empty. + 0 + + + FWF_1 + Enabled transmit FIFO is empty. + 0x1 + + + + + FEF + FIFO Error Flag + 0x12 + 1 + read-write + oneToClear + + + FEF_0 + Transmit underrun not detected. + 0 + + + FEF_1 + Transmit underrun detected. + 0x1 + + + + + SEF + Sync Error Flag + 0x13 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 0x14 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 0x18 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 0x19 + 1 + write-only + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 0x1C + 1 + read-write + + + BCE_0 + Transmit bit clock is disabled. + 0 + + + BCE_1 + Transmit bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 0x1D + 1 + read-write + + + DBGE_0 + Transmitter is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Transmitter is enabled in Debug mode. + 0x1 + + + + + STOPE + Stop Enable + 0x1E + 1 + read-write + + + STOPE_0 + Transmitter disabled in Stop mode. + 0 + + + STOPE_1 + Transmitter enabled in Stop mode. + 0x1 + + + + + TE + Transmitter Enable + 0x1F + 1 + read-write + + + TE_0 + Transmitter is disabled. + 0 + + + TE_1 + Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + TCR1 + SAI Transmit Configuration 1 Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFW + Transmit FIFO Watermark + 0 + 5 + read-write + + + + + TCR2 + SAI Transmit Configuration 2 Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 0x18 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 0x19 + 1 + read-write + + + BCP_0 + Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 0x1A + 2 + read-write + + + MSEL_0 + Master Clock (MCLK) 1 option selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 0x1C + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 0x1D + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 0x1E + 2 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with receiver. + 0x1 + + + + + + + TCR3 + SAI Transmit Configuration 3 Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + TCE + Transmit Channel Enable + 0x10 + 1 + read-write + + + TCE_0 + Transmit data channel N is disabled. + 0 + + + TCE_1 + Transmit data channel N is enabled. + 0x1 + + + + + + + TCR4 + SAI Transmit Configuration 4 Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 0x1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + FSE + Frame Sync Early + 0x3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 0x4 + 1 + read-write + + + MF_0 + LSB is transmitted first. + 0 + + + MF_1 + MSB is transmitted first. + 0x1 + + + + + SYWD + Sync Width + 0x8 + 5 + read-write + + + FRSZ + Frame size + 0x10 + 5 + read-write + + + + + TCR5 + SAI Transmit Configuration 5 Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 0x8 + 5 + read-write + + + W0W + Word 0 Width + 0x10 + 5 + read-write + + + WNW + Word N Width + 0x18 + 5 + read-write + + + + + TDR + SAI Transmit Data Register + 0x20 + 32 + write-only + 0 + 0xFFFFFFFF + + + TDR + Transmit Data Register + 0 + 32 + write-only + + + + + TFR + SAI Transmit FIFO Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 6 + read-only + + + WFP + Write FIFO Pointer + 0x10 + 6 + read-only + + + + + TMR + SAI Transmit Mask Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + TWM + Transmit Word Mask + 0 + 32 + read-write + + + TWM_0 + Word N is enabled. + 0 + + + TWM_1 + Word N is masked. The transmit data pins are tri-stated when masked. + 0x1 + + + + + + + RCSR + SAI Receive Control Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 0x1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 0x8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 0x9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 0xA + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 0xB + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 0xC + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 0x10 + 1 + read-only + + + FRF_0 + Receive FIFO watermark not reached. + 0 + + + FRF_1 + Receive FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 0x11 + 1 + read-only + + + FWF_0 + No enabled receive FIFO is full. + 0 + + + FWF_1 + Enabled receive FIFO is full. + 0x1 + + + + + FEF + FIFO Error Flag + 0x12 + 1 + read-write + oneToClear + + + FEF_0 + Receive overflow not detected. + 0 + + + FEF_1 + Receive overflow detected. + 0x1 + + + + + SEF + Sync Error Flag + 0x13 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 0x14 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 0x18 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 0x19 + 1 + write-only + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 0x1C + 1 + read-write + + + BCE_0 + Receive bit clock is disabled. + 0 + + + BCE_1 + Receive bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 0x1D + 1 + read-write + + + DBGE_0 + Receiver is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Receiver is enabled in Debug mode. + 0x1 + + + + + STOPE + Stop Enable + 0x1E + 1 + read-write + + + STOPE_0 + Receiver disabled in Stop mode. + 0 + + + STOPE_1 + Receiver enabled in Stop mode. + 0x1 + + + + + RE + Receiver Enable + 0x1F + 1 + read-write + + + RE_0 + Receiver is disabled. + 0 + + + RE_1 + Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + RCR1 + SAI Receive Configuration 1 Register + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + RFW + Receive FIFO Watermark + 0 + 5 + read-write + + + + + RCR2 + SAI Receive Configuration 2 Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 0x18 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 0x19 + 1 + read-write + + + BCP_0 + Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 0x1A + 2 + read-write + + + MSEL_0 + Bus Clock selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 0x1C + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 0x1D + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 0x1E + 2 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with transmitter. + 0x1 + + + + + + + RCR3 + SAI Receive Configuration 3 Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + RCE + Receive Channel Enable + 0x10 + 1 + read-write + + + RCE_0 + Receive data channel N is disabled. + 0 + + + RCE_1 + Receive data channel N is enabled. + 0x1 + + + + + + + RCR4 + SAI Receive Configuration 4 Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame Sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame Sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 0x1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + FSE + Frame Sync Early + 0x3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 0x4 + 1 + read-write + + + MF_0 + LSB is received first. + 0 + + + MF_1 + MSB is received first. + 0x1 + + + + + SYWD + Sync Width + 0x8 + 5 + read-write + + + FRSZ + Frame Size + 0x10 + 5 + read-write + + + + + RCR5 + SAI Receive Configuration 5 Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 0x8 + 5 + read-write + + + W0W + Word 0 Width + 0x10 + 5 + read-write + + + WNW + Word N Width + 0x18 + 5 + read-write + + + + + RDR + SAI Receive Data Register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDR + Receive Data Register + 0 + 32 + read-only + + + + + RFR + SAI Receive FIFO Register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 6 + read-only + + + WFP + Write FIFO Pointer + 0x10 + 6 + read-only + + + + + RMR + SAI Receive Mask Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RWM + Receive Word Mask + 0 + 32 + read-write + + + RWM_0 + Word N is enabled. + 0 + + + RWM_1 + Word N is masked. + 0x1 + + + + + + + + + I2S2 + Inter-IC Sound / Synchronous Audio Interface + I2S + I2S2_ + 0x202C000 + + 0 + 0xE4 + registers + + + SAI2 + 130 + + + + I2S3 + Inter-IC Sound / Synchronous Audio Interface + I2S + I2S3_ + 0x2030000 + + 0 + 0xE4 + registers + + + SAI3_RX + 56 + + + SAI3_TX + 57 + + + + ASRC + ASRC Registers + ASRC + ASRC_ + 0x2034000 + + 0 + 0xCC + registers + + + ASRC + 82 + + + + ASRCTR + ASRC Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ASRCEN + ASRC Enable Enable the operation of ASRC. + 0 + 1 + read-write + + + ASREA + ASRC Enable A Enable the operation of the conversion A of ASRC + 0x1 + 1 + read-write + + + ASREB + ASRC Enable B Enable the operation of the conversion B of ASRC + 0x2 + 1 + read-write + + + ASREC + ASRC Enable C Enable the operation of the conversion C of ASRC + 0x3 + 1 + read-write + + + SRST + Software Reset This bit is self-clear bit + 0x4 + 1 + write-only + + + IDRA + Use Ideal Ratio for Pair A When USRA=0, this bit has no usage + 0xD + 1 + read-write + + + USRA + Use Ratio for Pair A Use ratio as the input to ASRC + 0xE + 1 + read-write + + + IDRB + Use Ideal Ratio for Pair B When USRB=0, this bit has no usage + 0xF + 1 + read-write + + + USRB + Use Ratio for Pair B Use ratio as the input to ASRC + 0x10 + 1 + read-write + + + IDRC + Use Ideal Ratio for Pair C When USRC=0, this bit has no usage + 0x11 + 1 + read-write + + + USRC + Use Ratio for Pair C Use ratio as the input to ASRC + 0x12 + 1 + read-write + + + ATSA + ASRC Pair A Automatic Selection For Processing Options When this bit is 1, pair A will automatic update its pre-processing and post-processing options (ASRCFG: PREMODA, ASRCFG:POSTMODA see ASRC Misc Control Register 1 for Pair CASRC Filter Configuration Status Register ) based on the frequencies it detected + 0x14 + 1 + read-write + + + ATSB + ASRC Pair B Automatic Selection For Processing Options When this bit is 1, pair B will automatic update its pre-processing and post-processing options (ASRCFG: PREMODB, ASRCFG:POSTMODB see ASRC Misc Control Register 1 for Pair CASRC Filter Configuration Status Register ) based on the frequencies it detected + 0x15 + 1 + read-write + + + ATSC + ASRC Pair C Automatic Selection For Processing Options When this bit is 1, pair C will automatic update its pre-processing and post-processing options (ASRCFG: PREMODC, ASRCFG:POSTMODC see ASRC Misc Control Register 1 for Pair CASRC Filter Configuration Status Register ) based on the frequencies it detected + 0x16 + 1 + read-write + + + + + ASRIER + ASRC Interrupt Enable Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADIEA + Data Input A Interrupt Enable Enables the data input A Interrupt. + 0 + 1 + read-write + + + ADIEA_0 + interrupt disabled + 0 + + + ADIEA_1 + interrupt enabled + 0x1 + + + + + ADIEB + Data Input B Interrupt Enable Enables the data input B interrupt. + 0x1 + 1 + read-write + + + ADIEB_0 + interrupt disabled + 0 + + + ADIEB_1 + interrupt enabled + 0x1 + + + + + ADIEC + Data Input C Interrupt Enable Enables the data input C interrupt. + 0x2 + 1 + read-write + + + ADIEC_0 + interrupt disabled + 0 + + + ADIEC_1 + interrupt enabled + 0x1 + + + + + ADOEA + Data Output A Interrupt Enable Enables the data output A interrupt. + 0x3 + 1 + read-write + + + ADOEA_0 + interrupt disabled + 0 + + + ADOEA_1 + interrupt enabled + 0x1 + + + + + ADOEB + Data Output B Interrupt Enable Enables the data output B interrupt. + 0x4 + 1 + read-write + + + ADOEB_0 + interrupt disabled + 0 + + + ADOEB_1 + interrupt enabled + 0x1 + + + + + ADOEC + Data Output C Interrupt Enable Enables the data output C interrupt. + 0x5 + 1 + read-write + + + ADOEC_0 + interrupt disabled + 0 + + + ADOEC_1 + interrupt enabled + 0x1 + + + + + AOLIE + Overload Interrupt Enable Enables the overload interrupt. + 0x6 + 1 + read-write + + + AOLIE_0 + interrupt disabled + 0 + + + AOLIE_1 + interrupt enabled + 0x1 + + + + + AFPWE + FP in Wait State Interrupt Enable Enables the FP in wait state interrupt. + 0x7 + 1 + read-write + + + AFPWE_0 + interrupt disabled + 0 + + + AFPWE_1 + interrupt enabled + 0x1 + + + + + + + ASRCNCR + ASRC Channel Number Configuration Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ANCA + Number of A Channels + 0 + 4 + read-write + + + ANCA_0 + 0 channels in A (Pair A is disabled) + 0 + + + ANCA_1 + 1 channel in A + 0x1 + + + ANCA_2 + 2 channels in A + 0x2 + + + ANCA_3 + 3 channels in A + 0x3 + + + ANCA_4 + 4 channels in A + 0x4 + + + ANCA_5 + 5 channels in A + 0x5 + + + ANCA_6 + 6 channels in A + 0x6 + + + ANCA_7 + 7 channels in A + 0x7 + + + ANCA_8 + 8 channels in A + 0x8 + + + ANCA_9 + 9 channels in A + 0x9 + + + ANCA_10 + 10 channels in A + 0xA + + + + + ANCB + Number of B Channels + 0x4 + 4 + read-write + + + ANCB_0 + 0 channels in B (Pair B is disabled) + 0 + + + ANCB_1 + 1 channel in B + 0x1 + + + ANCB_2 + 2 channels in B + 0x2 + + + ANCB_3 + 3 channels in B + 0x3 + + + ANCB_4 + 4 channels in B + 0x4 + + + ANCB_5 + 5 channels in B + 0x5 + + + ANCB_6 + 6 channels in B + 0x6 + + + ANCB_7 + 7 channels in B + 0x7 + + + ANCB_8 + 8 channels in B + 0x8 + + + ANCB_9 + 9 channels in B + 0x9 + + + ANCB_10 + 10 channels in B + 0xA + + + + + ANCC + Number of C ChannelsANCC+ANCB+ANCA<=10 + 0x8 + 4 + read-write + + + ANCC_0 + 0 channels in C (Pair C is disabled) + 0 + + + ANCC_1 + 1 channel in C + 0x1 + + + ANCC_2 + 2 channels in C + 0x2 + + + ANCC_3 + 3 channels in C + 0x3 + + + ANCC_4 + 4 channels in C + 0x4 + + + ANCC_5 + 5 channels in C + 0x5 + + + ANCC_6 + 6 channels in C + 0x6 + + + ANCC_7 + 7 channels in C + 0x7 + + + ANCC_8 + 8 channels in C + 0x8 + + + ANCC_9 + 9 channels in C + 0x9 + + + ANCC_10 + 10 channels in C + 0xA + + + + + + + ASRCFG + ASRC Filter Configuration Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + PREMODA + Pre-Processing Configuration for Conversion Pair A These bits will be read/write by user if ASRCTR:ATSA=0, and can also be automatically updated by the ASRC internal logic if ASRCTR:ATSA=1 (see ASRC Misc Control Register 1 for Pair CASRC Control Register ) + 0x6 + 2 + read-write + + + PREMODA_0 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0 + + + PREMODA_1 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x1 + + + PREMODA_2 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x2 + + + PREMODA_3 + Select passthrough mode. In this case, POSTMODA[1-0] have no use. + 0x3 + + + + + POSTMODA + Post-Processing Configuration for Conversion Pair A These bits will be read/write by user if ASRCTR:ATSA=0, and can also be automatically updated by the ASRC internal logic if ASRCTR:ATSA=1 (see ASRC Misc Control Register 1 for Pair CASRC Control Register ) + 0x8 + 2 + read-write + + + POSTMODA_0 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0 + + + POSTMODA_1 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x1 + + + POSTMODA_2 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x2 + + + + + PREMODB + Pre-Processing Configuration for Conversion Pair B These bits will be read/write by user if ASRCTR:ATSB=0, and can also be automatically updated by the ASRC internal logic if ASRCTR:ATSB=1 (see ASRC Misc Control Register 1 for Pair CASRC Control Register ) + 0xA + 2 + read-write + + + PREMODB_0 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0 + + + PREMODB_1 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x1 + + + PREMODB_2 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x2 + + + PREMODB_3 + Select passthrough mode. In this case, POSTMODB[1-0] have no use. + 0x3 + + + + + POSTMODB + Post-Processing Configuration for Conversion Pair B These bits will be read/write by user if ASRCTR:ATSB=0, and can also be automatically updated by the ASRC internal logic if ASRCTR:ATSB=1 (see ASRC Misc Control Register 1 for Pair CASRC Control Register ) + 0xC + 2 + read-write + + + POSTMODB_0 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0 + + + POSTMODB_1 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x1 + + + POSTMODB_2 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x2 + + + + + PREMODC + Pre-Processing Configuration for Conversion Pair C These bits will be read/write by user if ASRCTR:ATSC=0, and can also be automatically updated by the ASRC internal logic if ASRCTR:ATSC=1 (see ASRC Misc Control Register 1 for Pair CASRC Control Register ) + 0xE + 2 + read-write + + + PREMODC_0 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0 + + + PREMODC_1 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x1 + + + PREMODC_2 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + 0x2 + + + PREMODC_3 + Select passthrough mode. In this case, POSTMODC[1-0] have no use. + 0x3 + + + + + POSTMODC + Post-Processing Configuration for Conversion Pair C These bits will be read/write by user if ASRCTR:ATSC=0, and can also be automatically updated by the ASRC internal logic if ASRCTR:ATSC=1 (see ASRC Misc Control Register 1 for Pair CASRC Control Register ) + 0x10 + 2 + read-write + + + POSTMODC_0 + Select Upsampling-by-2 as defined in Signal Processing Flow. + 0 + + + POSTMODC_1 + Select Direct-Connection as defined in Signal Processing Flow. + 0x1 + + + POSTMODC_2 + Select Downsampling-by-2 as defined in Signal Processing Flow. + 0x2 + + + + + NDPRA + Not Use Default Parameters for RAM-stored Parameters For Conversion Pair A + 0x12 + 1 + read-write + + + NDPRA_0 + Use default parameters for RAM-stored parameters. Override any parameters already in RAM. + 0 + + + NDPRA_1 + Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM. + 0x1 + + + + + NDPRB + Not Use Default Parameters for RAM-stored Parameters For Conversion Pair B + 0x13 + 1 + read-write + + + NDPRB_0 + Use default parameters for RAM-stored parameters. Override any parameters already in RAM. + 0 + + + NDPRB_1 + Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM. + 0x1 + + + + + NDPRC + Not Use Default Parameters for RAM-stored Parameters For Conversion Pair C + 0x14 + 1 + read-write + + + NDPRC_0 + Use default parameters for RAM-stored parameters. Override any parameters already in RAM. + 0 + + + NDPRC_1 + Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM. + 0x1 + + + + + INIRQA + Initialization for Conversion Pair A is served When this bit is 1, it means the initialization for conversion pair A is served + 0x15 + 1 + read-only + + + INIRQB + Initialization for Conversion Pair B is served When this bit is 1, it means the initialization for conversion pair B is served + 0x16 + 1 + read-only + + + INIRQC + Initialization for Conversion Pair C is served When this bit is 1, it means the initialization for conversion pair C is served + 0x17 + 1 + read-only + + + + + ASRCSR + ASRC Clock Source Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AICSA + Input Clock Source A + 0 + 4 + read-write + + + AICSA_0 + bit clock 0 + 0 + + + AICSA_1 + bit clock 1 + 0x1 + + + AICSA_2 + bit clock 2 + 0x2 + + + AICSA_3 + bit clock 3 + 0x3 + + + AICSA_4 + bit clock 4 + 0x4 + + + AICSA_5 + bit clock 5 + 0x5 + + + AICSA_6 + bit clock 6 + 0x6 + + + AICSA_7 + bit clock 7 + 0x7 + + + AICSA_8 + bit clock 8 + 0x8 + + + AICSA_9 + bit clock 9 + 0x9 + + + AICSA_10 + bit clock A + 0xA + + + AICSA_11 + bit clock B + 0xB + + + AICSA_12 + bit clock C + 0xC + + + AICSA_13 + bit clock D + 0xD + + + AICSA_14 + bit clock E + 0xE + + + AICSA_15 + clock disabled, connected to zero + 0xF + + + + + AICSB + Input Clock Source B + 0x4 + 4 + read-write + + + AICSB_0 + bit clock 0 + 0 + + + AICSB_1 + bit clock 1 + 0x1 + + + AICSB_2 + bit clock 2 + 0x2 + + + AICSB_3 + bit clock 3 + 0x3 + + + AICSB_4 + bit clock 4 + 0x4 + + + AICSB_5 + bit clock 5 + 0x5 + + + AICSB_6 + bit clock 6 + 0x6 + + + AICSB_7 + bit clock 7 + 0x7 + + + AICSB_8 + bit clock 8 + 0x8 + + + AICSB_9 + bit clock 9 + 0x9 + + + AICSB_10 + bit clock A + 0xA + + + AICSB_11 + bit clock B + 0xB + + + AICSB_12 + bit clock C + 0xC + + + AICSB_13 + bit clock D + 0xD + + + AICSB_14 + bit clock E + 0xE + + + AICSB_15 + clock disabled, connected to zero + 0xF + + + + + AICSC + Input Clock Source C + 0x8 + 4 + read-write + + + AICSC_0 + bit clock 0 + 0 + + + AICSC_1 + bit clock 1 + 0x1 + + + AICSC_2 + bit clock 2 + 0x2 + + + AICSC_3 + bit clock 3 + 0x3 + + + AICSC_4 + bit clock 4 + 0x4 + + + AICSC_5 + bit clock 5 + 0x5 + + + AICSC_6 + bit clock 6 + 0x6 + + + AICSC_7 + bit clock 7 + 0x7 + + + AICSC_8 + bit clock 8 + 0x8 + + + AICSC_9 + bit clock 9 + 0x9 + + + AICSC_10 + bit clock A + 0xA + + + AICSC_11 + bit clock B + 0xB + + + AICSC_12 + bit clock C + 0xC + + + AICSC_13 + bit clock D + 0xD + + + AICSC_14 + bit clock E + 0xE + + + AICSC_15 + clock disabled, connected to zero + 0xF + + + + + AOCSA + Output Clock Source A + 0xC + 4 + read-write + + + AOCSA_0 + bit clock 0 + 0 + + + AOCSA_1 + bit clock 1 + 0x1 + + + AOCSA_2 + bit clock 2 + 0x2 + + + AOCSA_3 + bit clock 3 + 0x3 + + + AOCSA_4 + bit clock 4 + 0x4 + + + AOCSA_5 + bit clock 5 + 0x5 + + + AOCSA_6 + bit clock 6 + 0x6 + + + AOCSA_7 + bit clock 7 + 0x7 + + + AOCSA_8 + bit clock 8 + 0x8 + + + AOCSA_9 + bit clock 9 + 0x9 + + + AOCSA_10 + bit clock A + 0xA + + + AOCSA_11 + bit clock B + 0xB + + + AOCSA_12 + bit clock C + 0xC + + + AOCSA_13 + bit clock D + 0xD + + + AOCSA_14 + bit clock E + 0xE + + + AOCSA_15 + clock disabled, connected to zero + 0xF + + + + + AOCSB + Output Clock Source B + 0x10 + 4 + read-write + + + AOCSB_0 + bit clock 0 + 0 + + + AOCSB_1 + bit clock 1 + 0x1 + + + AOCSB_2 + bit clock 2 + 0x2 + + + AOCSB_3 + bit clock 3 + 0x3 + + + AOCSB_4 + bit clock 4 + 0x4 + + + AOCSB_5 + bit clock 5 + 0x5 + + + AOCSB_6 + bit clock 6 + 0x6 + + + AOCSB_7 + bit clock 7 + 0x7 + + + AOCSB_8 + bit clock 8 + 0x8 + + + AOCSB_9 + bit clock 9 + 0x9 + + + AOCSB_10 + bit clock A + 0xA + + + AOCSB_11 + bit clock B + 0xB + + + AOCSB_12 + bit clock C + 0xC + + + AOCSB_13 + bit clock D + 0xD + + + AOCSB_14 + bit clock E + 0xE + + + AOCSB_15 + clock disabled, connected to zero + 0xF + + + + + AOCSC + Output Clock Source C + 0x14 + 4 + read-write + + + AOCSC_0 + bit clock 0 + 0 + + + AOCSC_1 + bit clock 1 + 0x1 + + + AOCSC_2 + bit clock 2 + 0x2 + + + AOCSC_3 + bit clock 3 + 0x3 + + + AOCSC_4 + bit clock 4 + 0x4 + + + AOCSC_5 + bit clock 5 + 0x5 + + + AOCSC_6 + bit clock 6 + 0x6 + + + AOCSC_7 + bit clock 7 + 0x7 + + + AOCSC_8 + bit clock 8 + 0x8 + + + AOCSC_9 + bit clock 9 + 0x9 + + + AOCSC_10 + bit clock A + 0xA + + + AOCSC_11 + bit clock B + 0xB + + + AOCSC_12 + bit clock C + 0xC + + + AOCSC_13 + bit clock D + 0xD + + + AOCSC_14 + bit clock E + 0xE + + + AOCSC_15 + clock disabled, connected to zero + 0xF + + + + + + + ASRCDR1 + ASRC Clock Divider Register 1 + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AICPA + Input Clock Prescaler A Specify the prescaling factor of the input prescaler A + 0 + 3 + read-write + + + AICDA + Input Clock Divider A Specify the divide ratio of the input clock divider A + 0x3 + 3 + read-write + + + AICPB + Input Clock Prescaler B Specify the prescaling factor of the input prescaler B + 0x6 + 3 + read-write + + + AICDB + Input Clock Divider B Specify the divide ratio of the input clock divider B + 0x9 + 3 + read-write + + + AOCPA + Output Clock Prescaler A Specify the prescaling factor of the output prescaler A + 0xC + 3 + read-write + + + AOCDA + Output Clock Divider A Specify the divide ratio of the output clock divider A + 0xF + 3 + read-write + + + AOCPB + Output Clock Prescaler B Specify the prescaling factor of the output prescaler B + 0x12 + 3 + read-write + + + AOCDB + Output Clock Divider B Specify the divide ratio of the output clock divider B + 0x15 + 3 + read-write + + + + + ASRCDR2 + ASRC Clock Divider Register 2 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AICPC + Input Clock Prescaler C Specify the prescaling factor of the input prescaler C + 0 + 3 + read-write + + + AICDC + Input Clock Divider C Specify the divide ratio of the input clock divider C + 0x3 + 3 + read-write + + + AOCPC + Output Clock Prescaler C Specify the prescaling factor of the output prescaler C + 0x6 + 3 + read-write + + + AOCDC + Output Clock Divider C Specify the divide ratio of the output clock divider C + 0x9 + 3 + read-write + + + + + ASRSTR + ASRC Status Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + AIDEA + Number of data in Input Data Buffer A is less than threshold When set, this bit indicates that number of data still available in ASRDIRA is less than threshold and the processor can write data to ASRDIRA + 0 + 1 + read-only + + + AIDEB + Number of data in Input Data Buffer B is less than threshold When set, this bit indicates that number of data still available in ASRDIRB is less than threshold and the processor can write data to ASRDIRB + 0x1 + 1 + read-only + + + AIDEC + Number of data in Input Data Buffer C is less than threshold When set, this bit indicates that number of data still available in ASRDIRC is less than threshold and the processor can write data to ASRDIRC + 0x2 + 1 + read-only + + + AODFA + Number of data in Output Data Buffer A is greater than threshold When set, this bit indicates that number of data already existing in ASRDORA is greater than threshold and the processor can read data from ASRDORA + 0x3 + 1 + read-only + + + AODFB + Number of data in Output Data Buffer B is greater than threshold When set, this bit indicates that number of data already existing in ASRDORB is greater than threshold and the processor can read data from ASRDORB + 0x4 + 1 + read-only + + + AODFC + Number of data in Output Data Buffer C is greater than threshold When set, this bit indicates that number of data already existing in ASRDORC is greater than threshold and the processor can read data from ASRDORC + 0x5 + 1 + read-only + + + AOLE + Overload Error Flag When set, this bit indicates that the task rate is too high for the ASRC to handle + 0x6 + 1 + read-only + + + FPWT + FP is in wait states This bit is for debug only + 0x7 + 1 + read-only + + + AIDUA + Input Data Buffer A has underflowed When set, this bit indicates that input data buffer A has underflowed + 0x8 + 1 + read-only + + + AIDUB + Input Data Buffer B has underflowed When set, this bit indicates that input data buffer B has underflowed + 0x9 + 1 + read-only + + + AIDUC + Input Data Buffer C has underflowed When set, this bit indicates that input data buffer C has underflowed + 0xA + 1 + read-only + + + AODOA + Output Data Buffer A has overflowed When set, this bit indicates that output data buffer A has overflowed + 0xB + 1 + read-only + + + AODOB + Output Data Buffer B has overflowed When set, this bit indicates that output data buffer B has overflowed + 0xC + 1 + read-only + + + AODOC + Output Data Buffer C has overflowed When set, this bit indicates that output data buffer C has overflowed + 0xD + 1 + read-only + + + AIOLA + Pair A Input Task Overload When set, this bit indicates that pair A input task is oveloaded + 0xE + 1 + read-only + + + AIOLB + Pair B Input Task Overload When set, this bit indicates that pair B input task is oveloaded + 0xF + 1 + read-only + + + AIOLC + Pair C Input Task Overload When set, this bit indicates that pair C input task is oveloaded + 0x10 + 1 + read-only + + + AOOLA + Pair A Output Task Overload When set, this bit indicates that pair A output task is oveloaded + 0x11 + 1 + read-only + + + AOOLB + Pair B Output Task Overload When set, this bit indicates that pair B output task is oveloaded + 0x12 + 1 + read-only + + + AOOLC + Pair C Output Task Overload When set, this bit indicates that pair C output task is oveloaded + 0x13 + 1 + read-only + + + ATQOL + Task Queue FIFO overload When set, this bit indicates that task queue FIFO logic is oveloaded + 0x14 + 1 + read-only + + + DSLCNT + DSL Counter Input to FIFO ready When set, this bit indicates that new DSL counter information is stored in the internal ASRC FIFO + 0x15 + 1 + read-only + + + + + 5 + 0x4 + 1,2,3,4,5 + ASRPMn%s + ASRC Parameter Register n + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + PARAMETER_VALUE + See recommended values table. + 0 + 24 + read-write + + + + + ASRTFR1 + ASRC ASRC Task Queue FIFO Register 1 + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + TF_BASE + Base address for task queue FIFO. Set to 0x7C. + 0x6 + 7 + read-write + + + TF_FILL + Current number of entries in task queue FIFO. + 0xD + 7 + read-only + + + + + ASRCCR + ASRC Channel Counter Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + ACIA + The channel counter for Pair A's input FIFO These bits stand for the current channel being accessed through shared peripheral bus for Pair A's input FIFO's usage + 0 + 4 + read-write + + + ACIB + The channel counter for Pair B's input FIFO These bits stand for the current channel being accessed through shared peripheral bus for Pair B's input FIFO's usage + 0x4 + 4 + read-write + + + ACIC + The channel counter for Pair C's input FIFO These bits stand for the current channel being accessed through shared peripheral bus for Pair C's input FIFO's usage + 0x8 + 4 + read-write + + + ACOA + The channel counter for Pair A's output FIFO These bits stand for the current channel being accessed through shared peripheral bus for Pair A's output FIFO's usage + 0xC + 4 + read-write + + + ACOB + The channel counter for Pair B's output FIFO These bits stand for the current channel being accessed through shared peripheral bus for Pair B's output FIFO's usage + 0x10 + 4 + read-write + + + ACOC + The channel counter for Pair C's output FIFO These bits stand for the current channel being accessed through shared peripheral bus for Pair C's output FIFO's usage + 0x14 + 4 + read-write + + + + + 3 + 0x8 + A,B,C + ASRDI%s + ASRC Data Input Register for Pair x + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Audio data input + 0 + 24 + write-only + + + + + 3 + 0x8 + A,B,C + ASRDO%s + ASRC Data Output Register for Pair x + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Audio data output + 0 + 24 + read-only + + + + + ASRIDRHA + ASRC Ideal Ratio for Pair A-High Part + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOA + IDRATIOA[31:24]. High part of ideal ratio value for pair A + 0 + 8 + read-write + + + + + ASRIDRLA + ASRC Ideal Ratio for Pair A -Low Part + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOA + IDRATIOA[23:0]. Low part of ideal ratio value for pair A + 0 + 24 + read-write + + + + + ASRIDRHB + ASRC Ideal Ratio for Pair B-High Part + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOB + IDRATIOB[31:24]. High part of ideal ratio value for pair B. + 0 + 8 + read-write + + + + + ASRIDRLB + ASRC Ideal Ratio for Pair B-Low Part + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOB + IDRATIOB[23:0]. Low part of ideal ratio value for pair B. + 0 + 24 + read-write + + + + + ASRIDRHC + ASRC Ideal Ratio for Pair C-High Part + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOC + IDRATIOC[31:24]. High part of ideal ratio value for pair C. + 0 + 8 + read-write + + + + + ASRIDRLC + ASRC Ideal Ratio for Pair C-Low Part + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOC + IDRATIOC[23:0]. Low part of ideal ratio value for pair C. + 0 + 24 + read-write + + + + + ASR76K + ASRC 76 kHz Period in terms of ASRC processing clock + 0x98 + 32 + read-write + 0xA47 + 0xFFFFFFFF + + + ASR76K + Value for the period of the 76 kHz sampling clock. + 0 + 17 + read-write + + + + + ASR56K + ASRC 56 kHz Period in terms of ASRC processing clock + 0x9C + 32 + read-write + 0xDF3 + 0xFFFFFFFF + + + ASR56K + Value for the period of the 56 kHz sampling clock + 0 + 17 + read-write + + + + + ASRMCRA + ASRC Misc Control Register for Pair A + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INFIFO_THRESHOLDA + The threshold for Pair A's input FIFO per channel These bits stand for the threshold for Pair A's input FIFO per channel + 0 + 6 + read-write + + + RSYNOFA + Re-sync Output FIFO Channel Counter If bit set, force ASRCCR:ACOA=0 + 0xA + 1 + read-write + + + RSYNIFA + Re-sync Input FIFO Channel Counter If bit set, force ASRCCR:ACIA=0 + 0xB + 1 + read-write + + + OUTFIFO_THRESHOLDA + The threshold for Pair A's output FIFO per channel These bits stand for the threshold for Pair A's output FIFO per channel + 0xC + 6 + read-write + + + BYPASSPOLYA + Bypass Polyphase Filtering for Pair A This bit will determine whether the polyphase filtering part of Pair A conversion will be bypassed + 0x14 + 1 + read-write + + + BYPASSPOLYA_0 + Don't bypass polyphase filtering. + 0 + + + BYPASSPOLYA_1 + Bypass polyphase filtering. + 0x1 + + + + + BUFSTALLA + Stall Pair A conversion in case of Buffer Near Empty/Full Condition This bit will determine whether the near empty/full FIFO condition will stall the rate conversion for pair A + 0x15 + 1 + read-write + + + BUFSTALLA_0 + Don't stall Pair A conversion even in case of near empty/full FIFO conditions. + 0 + + + BUFSTALLA_1 + Stall Pair A conversion in case of near empty/full FIFO conditions. + 0x1 + + + + + EXTTHRSHA + Use external thresholds for FIFO control of Pair A This bit will determine whether the FIFO thresholds externally defined in this register is used to control ASRC internal FIFO logic for pair A + 0x16 + 1 + read-write + + + EXTTHRSHA_0 + Use default thresholds. + 0 + + + EXTTHRSHA_1 + Use external defined thresholds. + 0x1 + + + + + ZEROBUFA + Initialize buf of Pair A when pair A is enabled + 0x17 + 1 + read-write + + + ZEROBUFA_0 + Zeroize the buffer + 0 + + + ZEROBUFA_1 + Don't zeroize the buffer + 0x1 + + + + + + + ASRFSTA + ASRC FIFO Status Register for Pair A + 0xA4 + 32 + read-only + 0 + 0xFFFFFFFF + + + INFIFO_FILLA + The fillings for Pair A's input FIFO per channel These bits stand for the fillings for Pair A's input FIFO per channel + 0 + 7 + read-only + + + IAEA + Input FIFO is near Empty for Pair A This bit is to indicate whether the input FIFO of Pair A is near empty + 0xB + 1 + read-only + + + OUTFIFO_FILLA + The fillings for Pair A's output FIFO per channel These bits stand for the fillings for Pair A's output FIFO per channel + 0xC + 7 + read-only + + + OAFA + Output FIFO is near Full for Pair A This bit is to indicate whether the output FIFO of Pair A is near full + 0x17 + 1 + read-only + + + + + ASRMCRB + ASRC Misc Control Register for Pair B + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + INFIFO_THRESHOLDB + The threshold for Pair B's input FIFO per channel These bits stand for the threshold for Pair B's input FIFO per channel + 0 + 6 + read-write + + + RSYNOFB + Re-sync Output FIFO Channel Counter If bit set, force ASRCCR:ACOB=0 + 0xA + 1 + read-write + + + RSYNIFB + Re-sync Input FIFO Channel Counter If bit set, force ASRCCR:ACIB=0 + 0xB + 1 + read-write + + + OUTFIFO_THRESHOLDB + The threshold for Pair B's output FIFO per channel These bits stand for the threshold for Pair B's output FIFO per channel + 0xC + 6 + read-write + + + BYPASSPOLYB + Bypass Polyphase Filtering for Pair B This bit will determine whether the polyphase filtering part of Pair B conversion will be bypassed + 0x14 + 1 + read-write + + + BYPASSPOLYB_0 + Don't bypass polyphase filtering. + 0 + + + BYPASSPOLYB_1 + Bypass polyphase filtering. + 0x1 + + + + + BUFSTALLB + Stall Pair B conversion in case of Buffer Near Empty/Full Condition This bit will determine whether the near empty/full FIFO condition will stall the rate conversion for pair B + 0x15 + 1 + read-write + + + BUFSTALLB_0 + Don't stall Pair B conversion even in case of near empty/full FIFO conditions. + 0 + + + BUFSTALLB_1 + Stall Pair B conversion in case of near empty/full FIFO conditions. + 0x1 + + + + + EXTTHRSHB + Use external thresholds for FIFO control of Pair B This bit will determine whether the FIFO thresholds externally defined in this register is used to control ASRC internal FIFO logic for pair B + 0x16 + 1 + read-write + + + EXTTHRSHB_0 + Use default thresholds. + 0 + + + EXTTHRSHB_1 + Use external defined thresholds. + 0x1 + + + + + ZEROBUFB + Initialize buf of Pair B when pair B is enabled This bit is used to control whether the buffer is to be zeroized when pair B is enabled + 0x17 + 1 + read-write + + + ZEROBUFB_0 + Zeroize the buffer + 0 + + + ZEROBUFB_1 + Don't zeroize the buffer + 0x1 + + + + + + + ASRFSTB + ASRC FIFO Status Register for Pair B + 0xAC + 32 + read-only + 0 + 0xFFFFFFFF + + + INFIFO_FILLB + The fillings for Pair B's input FIFO per channel These bits stand for the fillings for Pair B's input FIFO per channel + 0 + 7 + read-only + + + IAEB + Input FIFO is near Empty for Pair B This bit is to indicate whether the input FIFO of Pair B is near empty + 0xB + 1 + read-only + + + OUTFIFO_FILLB + The fillings for Pair B's output FIFO per channel These bits stand for the fillings for Pair B's output FIFO per channel + 0xC + 7 + read-only + + + OAFB + Output FIFO is near Full for Pair B This bit is to indicate whether the output FIFO of Pair B is near full + 0x17 + 1 + read-only + + + + + ASRMCRC + ASRC Misc Control Register for Pair C + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INFIFO_THRESHOLDC + The threshold for Pair C's input FIFO per channel These bits stand for the threshold for Pair C's input FIFO per channel + 0 + 6 + read-write + + + RSYNOFC + Re-sync Output FIFO Channel Counter If bit set, force ASRCCR:ACOC=0 + 0xA + 1 + read-write + + + RSYNIFC + Re-sync Input FIFO Channel Counter If bit set, force ASRCCR:ACIC=0 + 0xB + 1 + read-write + + + OUTFIFO_THRESHOLDC + The threshold for Pair C's output FIFO per channel These bits stand for the threshold for Pair C's output FIFO per channel + 0xC + 6 + read-write + + + BYPASSPOLYC + Bypass Polyphase Filtering for Pair C This bit will determine whether the polyphase filtering part of Pair C conversion will be bypassed + 0x14 + 1 + read-write + + + BYPASSPOLYC_0 + Don't bypass polyphase filtering. + 0 + + + BYPASSPOLYC_1 + Bypass polyphase filtering. + 0x1 + + + + + BUFSTALLC + Stall Pair C conversion in case of Buffer Near Empty/Full Condition This bit will determine whether the near empty/full FIFO condition will stall the rate conversion for pair C + 0x15 + 1 + read-write + + + BUFSTALLC_0 + Don't stall Pair C conversion even in case of near empty/full FIFO conditions. + 0 + + + BUFSTALLC_1 + Stall Pair C conversion in case of near empty/full FIFO conditions. + 0x1 + + + + + EXTTHRSHC + Use external thresholds for FIFO control of Pair C This bit will determine whether the FIFO thresholds externally defined in this register is used to control ASRC internal FIFO logic for pair C + 0x16 + 1 + read-write + + + EXTTHRSHC_0 + Use default thresholds. + 0 + + + EXTTHRSHC_1 + Use external defined thresholds. + 0x1 + + + + + ZEROBUFC + Initialize buf of Pair C when pair C is enabled This bit is used to control whether the buffer is to be zeroized when pair C is enabled + 0x17 + 1 + read-write + + + ZEROBUFC_0 + Zeroize the buffer + 0 + + + ZEROBUFC_1 + Don't zeroize the buffer + 0x1 + + + + + + + ASRFSTC + ASRC FIFO Status Register for Pair C + 0xB4 + 32 + read-only + 0 + 0xFFFFFFFF + + + INFIFO_FILLC + The fillings for Pair C's input FIFO per channel These bits stand for the fillings for Pair C's input FIFO per channel + 0 + 7 + read-only + + + IAEC + Input FIFO is near Empty for Pair C This bit is to indicate whether the input FIFO of Pair C is near empty + 0xB + 1 + read-only + + + OUTFIFO_FILLC + The fillings for Pair C's output FIFO per channel These bits stand for the fillings for Pair C's output FIFO per channel + 0xC + 7 + read-only + + + OAFC + Output FIFO is near Full for Pair C This bit is to indicate whether the output FIFO of Pair C is near full + 0x17 + 1 + read-only + + + + + 3 + 0x4 + A,B,C + ASRMCR1%s + ASRC Misc Control Register 1 for Pair X + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OW16 + Bit Width Option of the output FIFO This bit will determine the bit width option of the output FIFO + 0 + 1 + read-write + + + OW16_0 + 24-bit output data. + 0 + + + OW16_1 + 16-bit output data + 0x1 + + + + + OSGN + Sign Extension Option of the output FIFO This bit will determine the sign extension option of the output FIFO + 0x1 + 1 + read-write + + + OSGN_0 + No sign extension. + 0 + + + OSGN_1 + Sign extension. + 0x1 + + + + + OMSB + Data Alignment of the output FIFO This bit will determine the data alignment of the output FIFO. + 0x2 + 1 + read-write + + + OMSB_0 + LSB aligned. + 0 + + + OMSB_1 + MSB aligned. + 0x1 + + + + + IMSB + Data Alignment of the input FIFO This bit will determine the data alignment of the input FIFO. + 0x8 + 1 + read-write + + + IMSB_0 + LSB aligned. + 0 + + + IMSB_1 + MSB aligned. + 0x1 + + + + + IWD + Data Width of the input FIFO These three bits will determine the bitwidth for the audio data into ASRC All other settings not shown are reserved + 0x9 + 3 + read-write + + + + + + + SPBA + Temperature Monitor + SPBA + SPBA_ + 0x203C000 + + 0 + 0x80 + registers + + + + 32 + 0x4 + PRR%s + Peripheral Rights Register + 0 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + RARA + Resource Access Right + 0 + 1 + read-write + + + PROHIBITED + Access to peripheral is not allowed. + 0 + + + ALLOWED + Access to peripheral is granted. + 0x1 + + + + + RARB + Resource Access Right + 0x1 + 1 + read-write + + + PROHIBITED + Access to peripheral is not allowed. + 0 + + + ALLOWED + Access to peripheral is granted. + 0x1 + + + + + RARC + Resource Access Right + 0x2 + 1 + read-write + + + PROHIBITED + Access to peripheral is not allowed. + 0 + + + ALLOWED + Access to peripheral is granted. + 0x1 + + + + + ROI + Resource Owner ID + 0x10 + 2 + read-only + + + UNOWNED + Unowned resource. + 0 + + + MASTER_A + The resource is owned by master A port. + 0x1 + + + MASTER_B + The resource is owned by master B port. + 0x2 + + + MASTER_C + The resource is owned by master C port. + 0x3 + + + + + RMO + Requesting Master Owner + 0x1E + 2 + read-only + + + UNOWNED + The resource is unowned. + 0 + + + ANOTHER_MASTER + The resource is owned by another master. + 0x2 + + + REQUESTING_MASTER + The resource is owned by the requesting master. + 0x3 + + + + + + + + + TSC + Touch Screen Controller + TSC + TSC_ + 0x2040000 + + 0 + 0x84 + registers + + + TSC + 35 + + + + BASIC_SETTING + PS Input Buffer Address + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTO_MEASURE + Auto Measure + 0 + 1 + read-write + + + AUTO_MEASURE_0 + Disable Auto Measure + 0 + + + AUTO_MEASURE_1 + Auto Measure + 0x1 + + + + + _4_5_WIRE + 4/5 Wire detection + 0x4 + 1 + read-write + + + _4_5_WIRE_0 + 4-Wire Detection Mode + 0 + + + _4_5_WIRE_1 + 5-Wire Detection Mode + 0x1 + + + + + MEASURE_DELAY_TIME + Measure Delay Time + 0x8 + 24 + read-write + + + + + PS_INPUT_BUFFER_ADDR + PS Input Buffer Address + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_CHARGE_TIME + Auto Measure + 0 + 32 + read-write + + + PRE_CHARGE_TIME_0 + Disable Auto Measure + 0 + + + PRE_CHARGE_TIME_1 + Auto Measure + 0x1 + + + + + + + FLOW_CONTROL + Flow Control + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_RST + Soft Reset + 0 + 1 + read-write + + + START_MEASURE + Start Measure + 0x4 + 1 + read-write + + + START_MEASURE_0 + Do not start measure for now + 0 + + + START_MEASURE_1 + Start measure the X/Y coordinate value + 0x1 + + + + + DROP_MEASURE + Drop Measure + 0x8 + 1 + read-write + + + DROP_MEASURE_0 + Do not drop measure for now + 0 + + + DROP_MEASURE_1 + Drop the measure and controller return to idle status + 0x1 + + + + + START_SENSE + Start Sense + 0xC + 1 + read-write + + + START_SENSE_0 + Stay at idle status + 0 + + + START_SENSE_1 + Start sense detection and (if auto_measure set to 1) measure after detect a touch + 0x1 + + + + + DISABLE + This bit is for SW disable registers + 0x10 + 1 + read-write + + + DISABLE_0 + Leave HW state machine control + 0 + + + DISABLE_1 + SW set to idle status + 0x1 + + + + + + + MEASEURE_VALUE + Measure Value + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + Y_VALUE + Y Value + 0 + 12 + read-only + + + X_VALUE + X Value + 0x10 + 12 + read-only + + + + + INT_EN + Interrupt Enable + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE_INT_EN + Measure Interrupt Enable + 0 + 1 + read-write + + + MEASURE_INT_EN_0 + Disable measure + 0 + + + + + DETECT_INT_EN + Detect Interrupt Enable + 0x4 + 1 + read-write + + + DETECT_INT_EN_0 + Disable detect interrupt + 0 + + + DETECT_INT_EN_1 + Enable detect interrupt + 0x1 + + + + + IDLE_SW_INT_EN + Idle Software Interrupt Enable + 0xC + 1 + read-write + + + IDLE_SW_INT_EN_0 + Disable idle software interrupt + 0 + + + IDLE_SW_INT_EN_1 + Enable idle software interrupt + 0x1 + + + + + + + INT_SIG_EN + Interrupt Signal Enable + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE_SIG_EN + Measure Signal Enable + 0 + 1 + read-write + + + DETECT_SIG_EN + Detect Signal Enable + 0x4 + 1 + read-write + + + DETECT_SIG_EN_0 + Disable detect signal + 0 + + + DETECT_SIG_EN_1 + Enable detect signal + 0x1 + + + + + VALID_SIG_EN + Valid Signal Enable + 0x8 + 1 + read-write + + + VALID_SIG_EN_0 + Disable valid signal + 0 + + + VALID_SIG_EN_1 + Enable valid signal + 0x1 + + + + + IDLE_SW_SIG_EN + Idle Software Signal Enable + 0xC + 1 + read-write + + + IDLE_SW_SIG_EN_0 + Disable idle software signal + 0 + + + IDLE_SW_SIG_EN_1 + Enable idle software signal + 0x1 + + + + + + + INT_STATUS + Intterrupt Status + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE + Measure Signal + 0 + 1 + read-write + + + MEASURE_0 + Does not exist a measure signal + 0 + + + MEASURE_1 + Exist a measure signal + 0x1 + + + + + DETECT + Detect Signal + 0x4 + 1 + read-write + + + DETECT_0 + Does not exist a detect signal + 0 + + + DETECT_1 + Exist detect signal + 0x1 + + + + + VALID + Valid Signal + 0x8 + 1 + read-write + + + VALID_0 + There is no touch detected after measurement, indicates that the measured value is not valid + 0 + + + VALID_1 + There is touch detection after measurement, indicates that the measure is valid + 0x1 + + + + + IDLE_SW + Idle Software + 0xC + 1 + read-write + + + IDLE_SW_0 + Haven't return to idle status + 0 + + + IDLE_SW_1 + Already return to idle status + 0x1 + + + + + + + DEBUG_MODE + no description available + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADC_CONV_VALUE + ADC Conversion Value + 0 + 12 + read-only + + + ADC_COCO + ADC COCO Signal + 0xC + 1 + read-only + + + EXT_HWTS + Hardware Trigger Select Signal + 0x10 + 5 + read-write + + + TRIGGER + Trigger + 0x18 + 1 + read-write + + + TRIGGER_0 + No hardware trigger signal + 0 + + + TRIGGER_1 + Hardware trigger signal, the signal must last at least 1 ips clock period + 0x1 + + + + + ADC_COCO_CLEAR + ADC Coco Clear + 0x19 + 1 + read-write + + + ADC_COCO_CLEAR_0 + No ADC COCO clear + 0 + + + ADC_COCO_CLEAR_1 + Set ADC COCO clear + 0x1 + + + + + ADC_COCO_CLEAR_DISABLE + ADC COCO Clear Disable + 0x1A + 1 + read-write + + + ADC_COCO_CLEAR_DISABLE_0 + Allow TSC hardware generates ADC COCO clear + 0 + + + ADC_COCO_CLEAR_DISABLE_1 + Prevent TSC from generate ADC COCO clear signal + 0x1 + + + + + DEBUG_EN + Debug Enable + 0x1C + 1 + read-write + + + DEBUG_EN_0 + Enable debug mode + 0 + + + DEBUG_EN_1 + Disable debug mode + 0x1 + + + + + + + DEBUG_MODE2 + no description available + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + XPUL_PULL_DOWN + XPUL Wire Pull Down Switch + 0 + 1 + read-write + + + XPUL_PULL_DOWN_0 + Close the switch + 0 + + + XPUL_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + XPUL_PULL_UP + XPUL Wire Pull Up Switch + 0x1 + 1 + read-write + + + XPUL_PULL_UP_0 + Close the switch + 0 + + + XPUL_PULL_UP_1 + Open up the switch + 0x1 + + + + + XPUL_200K_PULL_UP + XPUL Wire 200K Pull Up Switch + 0x2 + 1 + read-write + + + XPUL_200K_PULL_UP_0 + Close the switch + 0 + + + XPUL_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + XNUR_PULL_DOWN + XNUR Wire Pull Down Switch + 0x3 + 1 + read-write + + + XNUR_PULL_DOWN_0 + Close the switch + 0 + + + XNUR_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + XNUR_PULL_UP + XNUR Wire Pull Up Switch + 0x4 + 1 + read-write + + + XNUR_PULL_UP_0 + Close the switch + 0 + + + XNUR_PULL_UP_1 + Open up the switch + 0x1 + + + + + XNUR_200K_PULL_UP + XNUR Wire 200K Pull Up Switch + 0x5 + 1 + read-write + + + XNUR_200K_PULL_UP_0 + Close the switch + 0 + + + XNUR_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + YPLL_PULL_DOWN + YPLL Wire Pull Down Switch + 0x6 + 1 + read-write + + + YPLL_PULL_DOWN_0 + Close the switch + 0 + + + YPLL_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + YPLL_PULL_UP + YPLL Wire Pull Up Switch + 0x7 + 1 + read-write + + + YPLL_PULL_UP_0 + Close the switch + 0 + + + YPLL_PULL_UP_1 + Open the switch + 0x1 + + + + + YPLL_200K_PULL_UP + YPLL Wire 200K Pull Up Switch + 0x8 + 1 + read-write + + + YPLL_200K_PULL_UP_0 + Close the switch + 0 + + + YPLL_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + YNLR_PULL_DOWN + YNLR Wire Pull Down Switch + 0x9 + 1 + read-write + + + YNLR_PULL_DOWN_0 + Close the switch + 0 + + + YNLR_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + YNLR_PULL_UP + YNLR Wire Pull Up Switch + 0xA + 1 + read-write + + + YNLR_PULL_UP_0 + Close the switch + 0 + + + YNLR_PULL_UP_1 + Open up the switch + 0x1 + + + + + YNLR_200K_PULL_UP + YNLR Wire 200K Pull Up Switch + 0xB + 1 + read-write + + + YNLR_200K_PULL_UP_0 + Close the switch + 0 + + + YNLR_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + WIPER_PULL_DOWN + Wiper Wire Pull Down Switch + 0xC + 1 + read-write + + + WIPER_PULL_DOWN_0 + Close the switch + 0 + + + WIPER_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + WIPER_PULL_UP + Wiper Wire Pull Up Switch + 0xD + 1 + read-write + + + WIPER_PULL_UP_0 + Close the switch + 0 + + + WIPER_PULL_UP_1 + Open up the switch + 0x1 + + + + + WIPER_200K_PULL_UP + Wiper Wire 200K Pull Up Switch + 0xE + 1 + read-write + + + WIPER_200K_PULL_UP_0 + Close the switch + 0 + + + WIPER_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + DETECT_FOUR_WIRE + Detect Four Wire + 0x10 + 1 + read-only + + + DETECT_FOUR_WIRE_0 + No detect signal + 0 + + + DETECT_FOUR_WIRE_1 + Yes, there is a detect on the touch screen. + 0x1 + + + + + DETECT_FIVE_WIRE + Detect Five Wire + 0x11 + 1 + read-only + + + DETECT_FIVE_WIRE_0 + No detect signal + 0 + + + DETECT_FIVE_WIRE_1 + Yes, there is a detect on the touch screen. + 0x1 + + + + + STATE_MACHINE + State Machine + 0x14 + 3 + read-only + + + STATE_MACHINE_0 + Idle + 0 + + + STATE_MACHINE_1 + Pre-charge + 0x1 + + + STATE_MACHINE_2 + Detect + 0x2 + + + STATE_MACHINE_3 + X-measure + 0x3 + + + STATE_MACHINE_4 + Y-measure + 0x4 + + + STATE_MACHINE_5 + Pre-charge + 0x5 + + + STATE_MACHINE_6 + Detect + 0x6 + + + + + INTERMEDIATE + Intermediate State + 0x17 + 1 + read-only + + + INTERMEDIATE_0 + Not in intermedia + 0 + + + INTERMEDIATE_1 + Intermedia + 0x1 + + + + + DETECT_ENABLE_FOUR_WIRE + Detect Enable Four Wire + 0x18 + 1 + read-write + + + DETECT_ENABLE_FOUR_WIRE_0 + Do not read four wire detect value, read default value from analogue + 0 + + + DETECT_ENABLE_FOUR_WIRE_1 + Read four wire detect status from analogue + 0x1 + + + + + DETECT_ENABLE_FIVE_WIRE + Detect Enable Five Wire + 0x1C + 1 + read-write + + + DETECT_ENABLE_FIVE_WIRE_0 + Do not read five wire detect value, read default value from analogue + 0 + + + DETECT_ENABLE_FIVE_WIRE_1 + Read five wire detect status from analogue + 0x1 + + + + + DE_GLITCH + This field indicates glitch threshold + 0x1D + 2 + read-only + + + DE_GLITCH_0 + Normal function: 0x1fff ipg clock cycles; Low power mode: 0x9 low power clock cycles + 0 + + + DE_GLITCH_1 + Normal function: 0xfff ipg clock cycles; Low power mode: :0x7 low power clock cycles + 0x1 + + + DE_GLITCH_2 + Normal function: 0x7ff ipg clock cycles; Low power mode:0x5 low power clock cycles + 0x2 + + + DE_GLITCH_3 + Normal function: 0x3 ipg clock cycles; Low power mode:0x3 low power clock cycles + 0x3 + + + + + + + + + AIPSTZ1 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ1_ + 0x207C000 + AIPSTZ + + 0 + 0x54 + registers + + + + MPR + Master Priviledge Registers + 0 + 32 + read-write + 0x77000000 + 0xFFFFFFFF + + + MPROT5 + Master 5 Priviledge, Buffer, Read, Write Control. + 0x8 + 4 + read-write + + + MPROT3 + Master 3 Priviledge, Buffer, Read, Write Control. + 0x10 + 4 + read-write + + + MPROT2 + Master 2 Priviledge, Buffer, Read, Write Control + 0x14 + 4 + read-write + + + MPROT1 + Master 1 Priviledge, Buffer, Read, Write Control + 0x18 + 4 + read-write + + + MPROT0 + Master 0 Priviledge, Buffer, Read, Write Control + 0x1C + 4 + read-write + + + + + OPACR + Off-Platform Peripheral Access Control Registers + 0x40 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC7 + Off-platform Peripheral Access Control 7 + 0 + 4 + read-write + + + OPAC6 + Off-platform Peripheral Access Control 6 + 0x4 + 4 + read-write + + + OPAC5 + Off-platform Peripheral Access Control 5 + 0x8 + 4 + read-write + + + OPAC4 + Off-platform Peripheral Access Control 4 + 0xC + 4 + read-write + + + OPAC3 + Off-platform Peripheral Access Control 3 + 0x10 + 4 + read-write + + + OPAC2 + Off-platform Peripheral Access Control 2 + 0x14 + 4 + read-write + + + OPAC1 + Off-platform Peripheral Access Control 1 + 0x18 + 4 + read-write + + + OPAC0 + Off-platform Peripheral Access Control 0 + 0x1C + 4 + read-write + + + + + OPACR1 + Off-Platform Peripheral Access Control Registers + 0x44 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC15 + Off-platform Peripheral Access Control 15 + 0 + 4 + read-write + + + OPAC14 + Off-platform Peripheral Access Control 14 + 0x4 + 4 + read-write + + + OPAC13 + Off-platform Peripheral Access Control 13 + 0x8 + 4 + read-write + + + OPAC12 + Off-platform Peripheral Access Control 12 + 0xC + 4 + read-write + + + OPAC11 + Off-platform Peripheral Access Control 11 + 0x10 + 4 + read-write + + + OPAC10 + Off-platform Peripheral Access Control 10 + 0x14 + 4 + read-write + + + OPAC9 + Off-platform Peripheral Access Control 9 + 0x18 + 4 + read-write + + + OPAC8 + Off-platform Peripheral Access Control 8 + 0x1C + 4 + read-write + + + + + OPACR2 + Off-Platform Peripheral Access Control Registers + 0x48 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC23 + Off-platform Peripheral Access Control 23 + 0 + 4 + read-write + + + OPAC22 + Off-platform Peripheral Access Control 22 + 0x4 + 4 + read-write + + + OPAC21 + Off-platform Peripheral Access Control 21 + 0x8 + 4 + read-write + + + OPAC20 + Off-platform Peripheral Access Control 20 + 0xC + 4 + read-write + + + OPAC19 + Off-platform Peripheral Access Control 19 + 0x10 + 4 + read-write + + + OPAC18 + Off-platform Peripheral Access Control 18 + 0x14 + 4 + read-write + + + OPAC17 + Off-platform Peripheral Access Control 17 + 0x18 + 4 + read-write + + + OPAC16 + Off-platform Peripheral Access Control 16 + 0x1C + 4 + read-write + + + + + OPACR3 + Off-Platform Peripheral Access Control Registers + 0x4C + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC31 + Off-platform Peripheral Access Control 31 + 0 + 4 + read-write + + + OPAC30 + Off-platform Peripheral Access Control 30 + 0x4 + 4 + read-write + + + OPAC29 + Off-platform Peripheral Access Control 29 + 0x8 + 4 + read-write + + + OPAC28 + Off-platform Peripheral Access Control 28 + 0xC + 4 + read-write + + + OPAC27 + Off-platform Peripheral Access Control 27 + 0x10 + 4 + read-write + + + OPAC26 + Off-platform Peripheral Access Control 26 + 0x14 + 4 + read-write + + + OPAC25 + Off-platform Peripheral Access Control 25 + 0x18 + 4 + read-write + + + OPAC24 + Off-platform Peripheral Access Control 24 + 0x1C + 4 + read-write + + + + + OPACR4 + Off-Platform Peripheral Access Control Registers + 0x50 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC33 + Off-platform Peripheral Access Control 33 + 0x18 + 4 + read-write + + + OPAC32 + Off-platform Peripheral Access Control 32 + 0x1C + 4 + read-write + + + + + + + AIPSTZ2 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ2_ + 0x217C000 + + 0 + 0x54 + registers + + + + AIPSTZ3 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ3_ + 0x227C000 + + 0 + 0x54 + registers + + + + PWM1 + PWM + PWM + PWM1_ + 0x2080000 + PWM + + 0 + 0x18 + registers + + + PWM1 + 115 + + + + PWMCR + PWM Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + PWM Enable + 0 + 1 + read-write + + + EN_0 + PWM disabled + 0 + + + EN_1 + PWM enabled + 0x1 + + + + + REPEAT + Sample Repeat + 0x1 + 2 + read-write + + + REPEAT_0 + Use each sample once + 0 + + + REPEAT_1 + Use each sample twice + 0x1 + + + REPEAT_2 + Use each sample four times + 0x2 + + + REPEAT_3 + Use each sample eight times + 0x3 + + + + + SWR + Software Reset + 0x3 + 1 + read-write + + + SWR_0 + PWM is out of reset + 0 + + + SWR_1 + PWM is undergoing reset + 0x1 + + + + + PRESCALER + Counter Clock Prescaler Value + 0x4 + 12 + read-write + + + PRESCALER_0 + Divide by 1 + 0 + + + PRESCALER_1 + Divide by 2 + 0x1 + + + PRESCALER_4095 + Divide by 4096 + 0xFFF + + + + + CLKSRC + Select Clock Source + 0x10 + 2 + read-write + + + CLKSRC_0 + Clock is off + 0 + + + CLKSRC_1 + ipg_clk + 0x1 + + + CLKSRC_2 + ipg_clk_highfreq + 0x2 + + + CLKSRC_3 + ipg_clk_32k + 0x3 + + + + + POUTC + PWM Output Configuration. This bit field determines the mode of PWM output on the output pin. + 0x12 + 2 + read-write + + + POUTC_0 + Output pin is set at rollover and cleared at comparison + 0 + + + POUTC_1 + Output pin is cleared at rollover and set at comparison + 0x1 + + + POUTC_2 + PWM output is disconnected + 0x2 + + + POUTC_3 + PWM output is disconnected + 0x3 + + + + + HCTR + Half-word Data Swap Control + 0x14 + 1 + read-write + + + HCTR_0 + Half word swapping does not take place + 0 + + + HCTR_1 + Half words from write data bus are swapped + 0x1 + + + + + BCTR + Byte Data Swap Control + 0x15 + 1 + read-write + + + BCTR_0 + byte ordering remains the same + 0 + + + BCTR_1 + byte ordering is reversed + 0x1 + + + + + DBGEN + Debug Mode Enable + 0x16 + 1 + read-write + + + DBGEN_0 + Inactive in debug mode + 0 + + + DBGEN_1 + Active in debug mode + 0x1 + + + + + WAITEN + Wait Mode Enable + 0x17 + 1 + read-write + + + WAITEN_0 + Inactive in wait mode + 0 + + + WAITEN_1 + Active in wait mode + 0x1 + + + + + DOZEN + Doze Mode Enable + 0x18 + 1 + read-write + + + DOZEN_0 + Inactive in doze mode + 0 + + + DOZEN_1 + Active in doze mode + 0x1 + + + + + STOPEN + Stop Mode Enable + 0x19 + 1 + read-write + + + STOPEN_0 + Inactive in stop mode + 0 + + + STOPEN_1 + Active in stop mode + 0x1 + + + + + FWM + FIFO Water Mark + 0x1A + 2 + read-write + + + FWM_0 + FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO + 0 + + + FWM_1 + FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO + 0x1 + + + FWM_2 + FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO + 0x2 + + + FWM_3 + FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO + 0x3 + + + + + + + PWMSR + PWM Status Register + 0x4 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOAV + FIFO Available + 0 + 3 + read-only + + + FIFOAV_0 + No data available + 0 + + + FIFOAV_1 + 1 word of data in FIFO + 0x1 + + + FIFOAV_2 + 2 words of data in FIFO + 0x2 + + + FIFOAV_3 + 3 words of data in FIFO + 0x3 + + + FIFOAV_4 + 4 words of data in FIFO + 0x4 + + + FIFOAV_5 + unused + 0x5 + + + FIFOAV_6 + unused + 0x6 + + + FIFOAV_7 + unused + 0x7 + + + + + FE + FIFO Empty Status Bit + 0x3 + 1 + read-write + oneToClear + + + FE_0 + Data level is above water mark + 0 + + + FE_1 + When the data level falls below the mark set by FWM field + 0x1 + + + + + ROV + Roll-over Status. This bit shows that a roll-over event has occurred. + 0x4 + 1 + read-write + oneToClear + + + ROV_0 + Roll-over event not occurred + 0 + + + ROV_1 + Roll-over event occurred + 0x1 + + + + + CMP + Compare Status. This bit shows that a compare event has occurred. + 0x5 + 1 + read-write + oneToClear + + + CMP_0 + Compare event not occurred + 0 + + + CMP_1 + Compare event occurred + 0x1 + + + + + FWE + FIFO Write Error Status + 0x6 + 1 + read-write + oneToClear + + + FWE_0 + FIFO write error not occurred + 0 + + + FWE_1 + FIFO write error occurred + 0x1 + + + + + + + PWMIR + PWM Interrupt Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIE + FIFO Empty Interrupt Enable. This bit controls the generation of the FIFO Empty interrupt. + 0 + 1 + read-write + + + FIE_0 + FIFO Empty interrupt disabled + 0 + + + FIE_1 + FIFO Empty interrupt enabled + 0x1 + + + + + RIE + Roll-over Interrupt Enable. This bit controls the generation of the Rollover interrupt. + 0x1 + 1 + read-write + + + RIE_0 + Roll-over interrupt not enabled + 0 + + + RIE_1 + Roll-over Interrupt enabled + 0x1 + + + + + CIE + Compare Interrupt Enable. This bit controls the generation of the Compare interrupt. + 0x2 + 1 + read-write + + + CIE_0 + Compare Interrupt not enabled + 0 + + + CIE_1 + Compare Interrupt enabled + 0x1 + + + + + + + PWMSAR + PWM Sample Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SAMPLE + Sample Value + 0 + 16 + read-write + + + + + PWMPR + PWM Period Register + 0x10 + 32 + read-write + 0xFFFE + 0xFFFFFFFF + + + PERIOD + Period Value + 0 + 16 + read-write + + + + + PWMCNR + PWM Counter Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Counter Value + 0 + 16 + read-only + + + + + + + PWM2 + PWM + PWM + PWM2_ + 0x2084000 + + 0 + 0x18 + registers + + + PWM2 + 116 + + + + PWM3 + PWM + PWM + PWM3_ + 0x2088000 + + 0 + 0x18 + registers + + + PWM3 + 117 + + + + PWM4 + PWM + PWM + PWM4_ + 0x208C000 + + 0 + 0x18 + registers + + + PWM4 + 118 + + + + PWM5 + PWM + PWM + PWM5_ + 0x20F0000 + + 0 + 0x18 + registers + + + PWM5 + 146 + + + + PWM6 + PWM + PWM + PWM6_ + 0x20F4000 + + 0 + 0x18 + registers + + + PWM6 + 147 + + + + PWM7 + PWM + PWM + PWM7_ + 0x20F8000 + + 0 + 0x18 + registers + + + PWM7 + 148 + + + + PWM8 + PWM + PWM + PWM8_ + 0x20FC000 + + 0 + 0x18 + registers + + + PWM8 + 149 + + + + CAN1 + CAN + CAN + CAN1_ + 0x2090000 + CAN + + 0 + 0x9E4 + registers + + + CAN1 + 142 + + + + MCR + Module Configuration Register + 0 + 32 + read-write + 0x5980000F + 0xFFFFFFFF + + + MAXMB + This 7-bit field defines the number of the last Message Buffers that will take part in the matching and arbitration processes + 0 + 7 + read-write + + + IDAM + This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown below + 0x8 + 2 + read-write + + + IDAM_0 + Format A One full ID (standard or extended) per ID filter Table element. + 0 + + + IDAM_1 + Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. + 0x1 + + + IDAM_2 + Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. + 0x2 + + + IDAM_3 + Format D All frames rejected. + 0x3 + + + + + AEN + This bit is supplied for backwards compatibility reasons + 0xC + 1 + read-write + + + AEN_0 + Abort disabled + 0 + + + AEN_1 + Abort enabled + 0x1 + + + + + LPRIOEN + This bit is provided for backwards compatibility reasons + 0xD + 1 + read-write + + + LPRIOEN_0 + Local Priority disabled + 0 + + + LPRIOEN_1 + Local Priority enabled + 0x1 + + + + + IRMQ + This bit indicates whether Rx matching process will be based either on individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK + 0x10 + 1 + read-write + + + IRMQ_0 + Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. + 0 + + + IRMQ_1 + Individual Rx masking and queue feature are enabled. + 0x1 + + + + + SRXDIS + This bit defines whether FlexCAN is allowed to receive frames transmitted by itself + 0x11 + 1 + read-write + + + SRXDIS_0 + Self reception enabled + 0 + + + SRXDIS_1 + Self reception disabled + 0x1 + + + + + WAKSRC + This bit defines whether the integrated low-pass filter is applied to protect the CAN_RX input from spurious wake up + 0x13 + 1 + read-write + + + WAKSRC_0 + CAN uses the unfiltered CAN_RX input to detect recessive to dominant edges on the CAN bus. + 0 + + + WAKSRC_1 + CAN uses the filtered CAN_RX input to detect recessive to dominant edges on the CAN bus + 0x1 + + + + + LPMACK + This read-only bit indicates that CAN is either in Disable Mode or Stop Mode + 0x14 + 1 + read-only + + + LPMACK_0 + CAN not in any of the low power modes + 0 + + + LPMACK_1 + CAN is either in Disable Mode, or Stop mode + 0x1 + + + + + WRNEN + When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register + 0x15 + 1 + read-write + + + WRNEN_0 + TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. + 0 + + + WRNEN_1 + TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. + 0x1 + + + + + SLFWAK + This bit enables the Self Wake Up feature when CAN is in Stop Mode + 0x16 + 1 + read-write + + + SLFWAK_0 + CAN Self Wake Up feature is disabled + 0 + + + SLFWAK_1 + CAN Self Wake Up feature is enabled + 0x1 + + + + + SUPV + This bit configures some of the CAN registers to be either in Supervisor or User Mode + 0x17 + 1 + read-write + + + SUPV_0 + FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + 0 + + + SUPV_1 + FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location + 0x1 + + + + + FRZACK + This read-only bit indicates that CAN is in Freeze Mode and its prescaler is stopped + 0x18 + 1 + read-only + + + FRZACK_0 + CAN not in Freeze Mode, prescaler running + 0 + + + FRZACK_1 + CAN in Freeze Mode, prescaler stopped + 0x1 + + + + + SOFTRST + When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers + 0x19 + 1 + read-write + + + SOFTRST_0 + No reset request + 0 + + + SOFTRST_1 + Reset the registers + 0x1 + + + + + WAKMSK + This bit enables the Wake Up Interrupt generation. + 0x1A + 1 + read-write + + + WAKMSK_0 + Wake Up Interrupt is disabled + 0 + + + WAKMSK_1 + Wake Up Interrupt is enabled + 0x1 + + + + + NOTRDY + This read-only bit indicates that CAN is either in Disable Mode, Stop Mode or Freeze Mode + 0x1B + 1 + read-only + + + NOTRDY_0 + CAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode + 0 + + + NOTRDY_1 + CAN module is either in Disable Mode, Stop Mode or Freeze Mode + 0x1 + + + + + HALT + Assertion of this bit puts the CAN module into Freeze Mode + 0x1C + 1 + read-write + + + HALT_0 + No Freeze Mode request. + 0 + + + HALT_1 + Enters Freeze Mode if the FRZ bit is asserted. + 0x1 + + + + + RFEN + This bit controls whether the Rx FIFO feature is enabled or not + 0x1D + 1 + read-write + + + RFEN_0 + FIFO not enabled + 0 + + + RFEN_1 + FIFO enabled + 0x1 + + + + + FRZ + The FRZ bit specifies the CAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at ARM level + 0x1E + 1 + read-write + + + FRZ_0 + Not enabled to enter Freeze Mode + 0 + + + FRZ_1 + Enabled to enter Freeze Mode + 0x1 + + + + + MDIS + This bit controls whether CAN is enabled or not + 0x1F + 1 + read-write + + + MDIS_0 + Enable the CAN module + 0 + + + MDIS_1 + Disable the CAN module + 0x1 + + + + + + + CTRL1 + Control 1 Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PROPSEG + This 3-bit field defines the length of the Propagation Segment in the bit time + 0 + 3 + read-write + + + LOM + This bit configures CAN to operate in Listen Only Mode + 0x3 + 1 + read-write + + + LOM_0 + Listen Only Mode is deactivated + 0 + + + LOM_1 + CAN module operates in Listen Only Mode + 0x1 + + + + + LBUF + This bit defines the ordering mechanism for Message Buffer transmission + 0x4 + 1 + read-write + + + LBUF_0 + Buffer with highest priority is transmitted first + 0 + + + LBUF_1 + Lowest number buffer is transmitted first + 0x1 + + + + + TSYN + This bit enables a mechanism that resets the free-running timer each time a message is received in Message Buffer 0 + 0x5 + 1 + read-write + + + TSYN_0 + Timer Sync feature disabled + 0 + + + TSYN_1 + Timer Sync feature enabled + 0x1 + + + + + BOFFREC + This bit defines how CAN recovers from Bus Off state + 0x6 + 1 + read-write + + + BOFFREC_0 + Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B + 0 + + + BOFFREC_1 + Automatic recovering from Bus Off state disabled + 0x1 + + + + + SMP + This bit defines the sampling mode of CAN bits at the CAN_RX + 0x7 + 1 + read-write + + + SMP_0 + Just one sample is used to determine the bit value + 0 + + + SMP_1 + Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used + 0x1 + + + + + RWRNMSK + This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error and Status Register + 0xA + 1 + read-write + + + RWRNMSK_0 + Rx Warning Interrupt disabled + 0 + + + RWRNMSK_1 + Rx Warning Interrupt enabled + 0x1 + + + + + TWRNMSK + This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the Error and Status Register + 0xB + 1 + read-write + + + TWRNMSK_0 + Tx Warning Interrupt disabled + 0 + + + TWRNMSK_1 + Tx Warning Interrupt enabled + 0x1 + + + + + LPB + This bit configures FlexCAN to operate in Loop-Back Mode + 0xC + 1 + read-write + + + LPB_0 + Loop Back disabled + 0 + + + LPB_1 + Loop Back enabled + 0x1 + + + + + ERRMSK + This bit provides a mask for the Error Interrupt. + 0xE + 1 + read-write + + + ERRMSK_0 + Error interrupt disabled + 0 + + + ERRMSK_1 + Error interrupt enabled + 0x1 + + + + + BOFFMSK + This bit provides a mask for the Bus Off Interrupt. + 0xF + 1 + read-write + + + BOFFMSK_0 + Bus Off interrupt disabled + 0 + + + BOFFMSK_1 + Bus Off interrupt enabled + 0x1 + + + + + PSEG2 + This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time + 0x10 + 3 + read-write + + + PSEG1 + This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time + 0x13 + 3 + read-write + + + RJW + This 2-bit field defines the maximum number of time quanta One time quantum is equal to the Sclock period + 0x16 + 2 + read-write + + + PRESDIV + This 8-bit field defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency + 0x18 + 8 + read-write + + + + + TIMER + Free Running Timer Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMER + TIMER + 0 + 16 + read-write + + + + + RXMGMASK + Rx Mailboxes Global Mask Register + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MG + These bits mask the Mailbox filter bits as shown in the figure above + 0 + 32 + read-write + + + MG_0 + the corresponding bit in the filter is "don't care" + 0 + + + MG_1 + The corresponding bit in the filter is checked against the one received + 0x1 + + + + + + + RX14MASK + Rx Buffer 14 Mask Register + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RX14M + These bits mask Mailbox 14 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters (see RXMGMASKRx Mailboxes Global Mask Register ) + 0 + 32 + read-write + + + RX14M_0 + the corresponding bit in the filter is "don't care" + 0 + + + RX14M_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + RX15MASK + Rx Buffer 15 Mask Register + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RX15M + These bits mask Mailbox 15 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters (see RXMGMASKRx Mailboxes Global Mask Register ) + 0 + 32 + read-write + + + RX15M_0 + the corresponding bit in the filter is "don't care" + 0 + + + RX15M_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + ECR + Error Counter Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_ERR_COUNTER + Tx_Err_Counter + 0 + 8 + read-write + + + RX_ERR_COUNTER + Rx_Err_Counter + 0x8 + 8 + read-write + + + + + ESR1 + Error and Status 1 Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAKINT + When CAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the ARM + 0 + 1 + read-write + + + WAKINT_0 + No such occurrence + 0 + + + WAKINT_1 + Indicates a recessive to dominant transition received on the CAN bus when the CAN module is in Stop Mode + 0x1 + + + + + ERRINT + This bit indicates that at least one of the Error Bits (bits 15-10) is set + 0x1 + 1 + read-write + + + ERRINT_0 + No such occurrence + 0 + + + ERRINT_1 + Indicates setting of any Error Bit in the Error and Status Register + 0x1 + + + + + BOFFINT + This bit is set when CAN enters 'Bus Off' state + 0x2 + 1 + read-write + + + BOFFINT_0 + No such occurrence + 0 + + + BOFFINT_1 + CAN module entered 'Bus Off' state + 0x1 + + + + + RX + This bit indicates if FlexCAN is receiving a message. Refer to . + 0x3 + 1 + read-only + + + RX_0 + CAN is receiving a message + 0 + + + RX_1 + CAN is transmitting a message + 0x1 + + + + + FLTCONF + If the LOM bit in the Control Register is asserted, after some delay that depends on the CAN bit timing the FLT_CONF field will indicate "Error Passive" + 0x4 + 2 + read-only + + + FLTCONF_0 + Error Active + 0 + + + FLTCONF_1 + Error Passive + 0x1 + + + + + TX + This bit indicates if CAN is transmitting a message.Refer to . + 0x6 + 1 + read-only + + + TX_0 + CAN is receiving a message + 0 + + + TX_1 + CAN is transmitting a message + 0x1 + + + + + IDLE + This bit indicates when CAN bus is in IDLE state.Refer to . + 0x7 + 1 + read-only + + + IDLE_0 + No such occurrence + 0 + + + IDLE_1 + CAN bus is now IDLE + 0x1 + + + + + RXWRN + This bit indicates when repetitive errors are occurring during message reception. + 0x8 + 1 + read-only + + + RXWRN_0 + No such occurrence + 0 + + + RXWRN_1 + Rx_Err_Counter >= 96 + 0x1 + + + + + TXWRN + This bit indicates when repetitive errors are occurring during message transmission. + 0x9 + 1 + read-only + + + TXWRN_0 + No such occurrence + 0 + + + TXWRN_1 + TX_Err_Counter >= 96 + 0x1 + + + + + STFERR + This bit indicates that a Stuffing Error has been detected. + 0xA + 1 + read-only + + + STFERR_0 + No such occurrence. + 0 + + + STFERR_1 + A Stuffing Error occurred since last read of this register. + 0x1 + + + + + FRMERR + This bit indicates that a Form Error has been detected by the receiver node, i + 0xB + 1 + read-only + + + FRMERR_0 + No such occurrence + 0 + + + FRMERR_1 + A Form Error occurred since last read of this register + 0x1 + + + + + CRCERR + This bit indicates that a CRC Error has been detected by the receiver node, i + 0xC + 1 + read-only + + + CRCERR_0 + No such occurrence + 0 + + + CRCERR_1 + A CRC error occurred since last read of this register. + 0x1 + + + + + ACKERR + This bit indicates that an Acknowledge Error has been detected by the transmitter node, i + 0xD + 1 + read-only + + + ACKERR_0 + No such occurrence + 0 + + + ACKERR_1 + An ACK error occurred since last read of this register + 0x1 + + + + + BIT0ERR + This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message + 0xE + 1 + read-only + + + BIT0ERR_0 + No such occurrence + 0 + + + BIT0ERR_1 + At least one bit sent as dominant is received as recessive + 0x1 + + + + + BIT1ERR + This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message + 0xF + 1 + read-only + + + BIT1ERR_0 + No such occurrence + 0 + + + BIT1ERR_1 + At least one bit sent as recessive is received as dominant + 0x1 + + + + + RWRNINT + If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from '0' to '1', meaning that the Rx error counters reached 96 + 0x10 + 1 + read-write + + + RWRNINT_0 + No such occurrence + 0 + + + RWRNINT_1 + The Rx error counter transition from < 96 to >= 96 + 0x1 + + + + + TWRNINT + If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from '0' to '1', meaning that the Tx error counter reached 96 + 0x11 + 1 + read-write + + + TWRNINT_0 + No such occurrence + 0 + + + TWRNINT_1 + The Tx error counter transition from < 96 to >= 96 + 0x1 + + + + + SYNCH + This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the communication process + 0x12 + 1 + read-only + + + SYNCH_0 + FlexCAN is not synchronized to the CAN bus + 0 + + + SYNCH_1 + FlexCAN is synchronized to the CAN bus + 0x1 + + + + + + + IMASK2 + Interrupt Masks 2 Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFHM + Each bit enables or disables the respective CAN Message Buffer (MB32 to MB63) Interrupt + 0 + 32 + read-write + + + BUFHM_0 + The corresponding buffer Interrupt is disabled + 0 + + + BUFHM_1 + The corresponding buffer Interrupt is enabled + 0x1 + + + + + + + IMASK1 + Interrupt Masks 1 Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFLM + Each bit enables or disables the respective CAN Message Buffer (MB0 to MB31) Interrupt + 0 + 32 + read-write + + + BUFLM_0 + The corresponding buffer Interrupt is disabled + 0 + + + BUFLM_1 + The corresponding buffer Interrupt is enabled + 0x1 + + + + + + + IFLAG2 + Interrupt Flags 2 Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFHI + Each bit flags the respective CAN Message Buffer (MB32 to MB63) interrupt. + 0 + 32 + read-write + + + BUFHI_0 + No such occurrence + 0 + + + BUFHI_1 + The corresponding buffer has successfully completed transmission or reception + 0x1 + + + + + + + IFLAG1 + Interrupt Flags 1 Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF4TO0I + If the Rx FIFO is not enabled, these bits flag the interrupts for MB0 to MB4 + 0 + 5 + read-write + + + BUF4TO0I_0 + No such occurrence + 0 + + + BUF4TO0I_1 + Corresponding MB completed transmission/reception + 0x1 + + + + + BUF5I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB5 + 0x5 + 1 + read-write + + + BUF5I_0 + No such occurrence + 0 + + + BUF5I_1 + MB5 completed transmission/reception or frames available in the FIFO + 0x1 + + + + + BUF6I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB6 + 0x6 + 1 + read-write + + + BUF6I_0 + No such occurrence + 0 + + + BUF6I_1 + MB6 completed transmission/reception or FIFO almost full + 0x1 + + + + + BUF7I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB7 + 0x7 + 1 + read-write + + + BUF7I_0 + No such occurrence + 0 + + + BUF7I_1 + MB7 completed transmission/reception or FIFO overflow + 0x1 + + + + + BUF31TO8I + Each bit flags the respective CAN Message Buffer (MB8 to MB31) interrupt. + 0x8 + 24 + read-write + + + BUF31TO8I_0 + No such occurrence + 0 + + + BUF31TO8I_1 + The corresponding MB has successfully completed transmission or reception + 0x1 + + + + + + + CTRL2 + Control 2 Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + EACEN + This bit controls the comparison of IDE and RTR bits within Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process + 0x10 + 1 + read-write + + + EACEN_0 + Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + 0 + + + EACEN_1 + Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. + 0x1 + + + + + RRS + If this bit is asserted Remote Request Frame is submitted to a matching process and stored in the corresponding Message Buffer in the same fashion of a Data Frame + 0x11 + 1 + read-write + + + RRS_0 + Remote Response Frame is generated + 0 + + + RRS_1 + Remote Request Frame is stored + 0x1 + + + + + MRP + If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching continues on the Rx FIFO + 0x12 + 1 + read-write + + + MRP_0 + Matching starts from Rx FIFO and continues on Mailboxes + 0 + + + MRP_1 + Matching starts from Mailboxes and continues on Rx FIFO + 0x1 + + + + + TASD + This 5-bit field indicates how many CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus + 0x13 + 5 + read-write + + + RFFN + This 4-bit field defines the number of Rx FIFO filters according to + 0x18 + 4 + read-write + + + WRMFRZ + Enable unrestricted write access to FlexCAN memory in Freeze mode + 0x1C + 1 + read-write + + + WRMFRZ_0 + Keep the write access restricted in some regions of FlexCAN memory + 0 + + + WRMFRZ_1 + Enable unrestricted write access to FlexCAN memory + 0x1 + + + + + + + ESR2 + Error and Status 2 Register + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + IMB + If ESR2[VPS] is asserted, this bit indicates whether there is any inactive Mailbox (CODE field is either 0b1000 or 0b0000) + 0xD + 1 + read-only + + + IMB_0 + If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. + 0 + + + IMB_1 + If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. + 0x1 + + + + + VPS + This bit indicates whether IMB and LPTM contents are currently valid or not + 0xE + 1 + read-only + + + VPS_0 + Contents of IMB and LPTM are invalid + 0 + + + VPS_1 + Contents of IMB and LPTM are valid + 0x1 + + + + + LPTM + If ESR2[VPS] is asserted, his 7-bit field indicates the lowest number inactive Mailbox (refer to IMB bit description) + 0x10 + 7 + read-only + + + + + CRCR + CRC Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCRC + This field indicates the CRC value of the last message transmitted + 0 + 15 + read-only + + + MBCRC + This field indicates the number of the Mailbox corresponding to the value in TXCRC field. + 0x10 + 7 + read-only + + + + + RXFGMASK + Rx FIFO Global Mask Register + 0x48 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + FGM + These bits mask the ID Filter Table elements bits in a perfect alignment + 0 + 32 + read-write + + + FGM_0 + The corresponding bit in the filter is "don't care" + 0 + + + FGM_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + RXFIR + Rx FIFO Information Register + 0x4C + 32 + read-only + 0 + 0xFFFFFFFF + + + IDHIT + This 9-bit field indicates which Identifier Acceptance Filter (see Rx FIFO Structure) was hit by the received message that is in the output of the Rx FIFO + 0 + 9 + read-only + + + + + CS0 + Message Buffer 0 CS Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID0 + Message Buffer 0 ID Register + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD00 + Message Buffer 0 WORD0 Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD10 + Message Buffer 0 WORD1 Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS1 + Message Buffer 1 CS Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID1 + Message Buffer 1 ID Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD01 + Message Buffer 1 WORD0 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD11 + Message Buffer 1 WORD1 Register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS2 + Message Buffer 2 CS Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID2 + Message Buffer 2 ID Register + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD02 + Message Buffer 2 WORD0 Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD12 + Message Buffer 2 WORD1 Register + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS3 + Message Buffer 3 CS Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID3 + Message Buffer 3 ID Register + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD03 + Message Buffer 3 WORD0 Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD13 + Message Buffer 3 WORD1 Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS4 + Message Buffer 4 CS Register + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID4 + Message Buffer 4 ID Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD04 + Message Buffer 4 WORD0 Register + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD14 + Message Buffer 4 WORD1 Register + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS5 + Message Buffer 5 CS Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID5 + Message Buffer 5 ID Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD05 + Message Buffer 5 WORD0 Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD15 + Message Buffer 5 WORD1 Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS6 + Message Buffer 6 CS Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID6 + Message Buffer 6 ID Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD06 + Message Buffer 6 WORD0 Register + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD16 + Message Buffer 6 WORD1 Register + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS7 + Message Buffer 7 CS Register + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID7 + Message Buffer 7 ID Register + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD07 + Message Buffer 7 WORD0 Register + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD17 + Message Buffer 7 WORD1 Register + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS8 + Message Buffer 8 CS Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID8 + Message Buffer 8 ID Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD08 + Message Buffer 8 WORD0 Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD18 + Message Buffer 8 WORD1 Register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS9 + Message Buffer 9 CS Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID9 + Message Buffer 9 ID Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD09 + Message Buffer 9 WORD0 Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD19 + Message Buffer 9 WORD1 Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS10 + Message Buffer 10 CS Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID10 + Message Buffer 10 ID Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD010 + Message Buffer 10 WORD0 Register + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD110 + Message Buffer 10 WORD1 Register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS11 + Message Buffer 11 CS Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID11 + Message Buffer 11 ID Register + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD011 + Message Buffer 11 WORD0 Register + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD111 + Message Buffer 11 WORD1 Register + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS12 + Message Buffer 12 CS Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID12 + Message Buffer 12 ID Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD012 + Message Buffer 12 WORD0 Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD112 + Message Buffer 12 WORD1 Register + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS13 + Message Buffer 13 CS Register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID13 + Message Buffer 13 ID Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD013 + Message Buffer 13 WORD0 Register + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD113 + Message Buffer 13 WORD1 Register + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS14 + Message Buffer 14 CS Register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID14 + Message Buffer 14 ID Register + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD014 + Message Buffer 14 WORD0 Register + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD114 + Message Buffer 14 WORD1 Register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS15 + Message Buffer 15 CS Register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID15 + Message Buffer 15 ID Register + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD015 + Message Buffer 15 WORD0 Register + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD115 + Message Buffer 15 WORD1 Register + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS16 + Message Buffer 16 CS Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID16 + Message Buffer 16 ID Register + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD016 + Message Buffer 16 WORD0 Register + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD116 + Message Buffer 16 WORD1 Register + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS17 + Message Buffer 17 CS Register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID17 + Message Buffer 17 ID Register + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD017 + Message Buffer 17 WORD0 Register + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD117 + Message Buffer 17 WORD1 Register + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS18 + Message Buffer 18 CS Register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID18 + Message Buffer 18 ID Register + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD018 + Message Buffer 18 WORD0 Register + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD118 + Message Buffer 18 WORD1 Register + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS19 + Message Buffer 19 CS Register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID19 + Message Buffer 19 ID Register + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD019 + Message Buffer 19 WORD0 Register + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD119 + Message Buffer 19 WORD1 Register + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS20 + Message Buffer 20 CS Register + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID20 + Message Buffer 20 ID Register + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD020 + Message Buffer 20 WORD0 Register + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD120 + Message Buffer 20 WORD1 Register + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS21 + Message Buffer 21 CS Register + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID21 + Message Buffer 21 ID Register + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD021 + Message Buffer 21 WORD0 Register + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD121 + Message Buffer 21 WORD1 Register + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS22 + Message Buffer 22 CS Register + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID22 + Message Buffer 22 ID Register + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD022 + Message Buffer 22 WORD0 Register + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD122 + Message Buffer 22 WORD1 Register + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS23 + Message Buffer 23 CS Register + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID23 + Message Buffer 23 ID Register + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD023 + Message Buffer 23 WORD0 Register + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD123 + Message Buffer 23 WORD1 Register + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS24 + Message Buffer 24 CS Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID24 + Message Buffer 24 ID Register + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD024 + Message Buffer 24 WORD0 Register + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD124 + Message Buffer 24 WORD1 Register + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS25 + Message Buffer 25 CS Register + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID25 + Message Buffer 25 ID Register + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD025 + Message Buffer 25 WORD0 Register + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD125 + Message Buffer 25 WORD1 Register + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS26 + Message Buffer 26 CS Register + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID26 + Message Buffer 26 ID Register + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD026 + Message Buffer 26 WORD0 Register + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD126 + Message Buffer 26 WORD1 Register + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS27 + Message Buffer 27 CS Register + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID27 + Message Buffer 27 ID Register + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD027 + Message Buffer 27 WORD0 Register + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD127 + Message Buffer 27 WORD1 Register + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS28 + Message Buffer 28 CS Register + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID28 + Message Buffer 28 ID Register + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD028 + Message Buffer 28 WORD0 Register + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD128 + Message Buffer 28 WORD1 Register + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS29 + Message Buffer 29 CS Register + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID29 + Message Buffer 29 ID Register + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD029 + Message Buffer 29 WORD0 Register + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD129 + Message Buffer 29 WORD1 Register + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS30 + Message Buffer 30 CS Register + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID30 + Message Buffer 30 ID Register + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD030 + Message Buffer 30 WORD0 Register + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD130 + Message Buffer 30 WORD1 Register + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS31 + Message Buffer 31 CS Register + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID31 + Message Buffer 31 ID Register + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD031 + Message Buffer 31 WORD0 Register + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD131 + Message Buffer 31 WORD1 Register + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS32 + Message Buffer 32 CS Register + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID32 + Message Buffer 32 ID Register + 0x284 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD032 + Message Buffer 32 WORD0 Register + 0x288 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD132 + Message Buffer 32 WORD1 Register + 0x28C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS33 + Message Buffer 33 CS Register + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID33 + Message Buffer 33 ID Register + 0x294 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD033 + Message Buffer 33 WORD0 Register + 0x298 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD133 + Message Buffer 33 WORD1 Register + 0x29C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS34 + Message Buffer 34 CS Register + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID34 + Message Buffer 34 ID Register + 0x2A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD034 + Message Buffer 34 WORD0 Register + 0x2A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD134 + Message Buffer 34 WORD1 Register + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS35 + Message Buffer 35 CS Register + 0x2B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID35 + Message Buffer 35 ID Register + 0x2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD035 + Message Buffer 35 WORD0 Register + 0x2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD135 + Message Buffer 35 WORD1 Register + 0x2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS36 + Message Buffer 36 CS Register + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID36 + Message Buffer 36 ID Register + 0x2C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD036 + Message Buffer 36 WORD0 Register + 0x2C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD136 + Message Buffer 36 WORD1 Register + 0x2CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS37 + Message Buffer 37 CS Register + 0x2D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID37 + Message Buffer 37 ID Register + 0x2D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD037 + Message Buffer 37 WORD0 Register + 0x2D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD137 + Message Buffer 37 WORD1 Register + 0x2DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS38 + Message Buffer 38 CS Register + 0x2E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID38 + Message Buffer 38 ID Register + 0x2E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD038 + Message Buffer 38 WORD0 Register + 0x2E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD138 + Message Buffer 38 WORD1 Register + 0x2EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS39 + Message Buffer 39 CS Register + 0x2F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID39 + Message Buffer 39 ID Register + 0x2F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD039 + Message Buffer 39 WORD0 Register + 0x2F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD139 + Message Buffer 39 WORD1 Register + 0x2FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS40 + Message Buffer 40 CS Register + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID40 + Message Buffer 40 ID Register + 0x304 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD040 + Message Buffer 40 WORD0 Register + 0x308 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD140 + Message Buffer 40 WORD1 Register + 0x30C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS41 + Message Buffer 41 CS Register + 0x310 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID41 + Message Buffer 41 ID Register + 0x314 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD041 + Message Buffer 41 WORD0 Register + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD141 + Message Buffer 41 WORD1 Register + 0x31C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS42 + Message Buffer 42 CS Register + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID42 + Message Buffer 42 ID Register + 0x324 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD042 + Message Buffer 42 WORD0 Register + 0x328 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD142 + Message Buffer 42 WORD1 Register + 0x32C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS43 + Message Buffer 43 CS Register + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID43 + Message Buffer 43 ID Register + 0x334 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD043 + Message Buffer 43 WORD0 Register + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD143 + Message Buffer 43 WORD1 Register + 0x33C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS44 + Message Buffer 44 CS Register + 0x340 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID44 + Message Buffer 44 ID Register + 0x344 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD044 + Message Buffer 44 WORD0 Register + 0x348 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD144 + Message Buffer 44 WORD1 Register + 0x34C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS45 + Message Buffer 45 CS Register + 0x350 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID45 + Message Buffer 45 ID Register + 0x354 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD045 + Message Buffer 45 WORD0 Register + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD145 + Message Buffer 45 WORD1 Register + 0x35C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS46 + Message Buffer 46 CS Register + 0x360 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID46 + Message Buffer 46 ID Register + 0x364 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD046 + Message Buffer 46 WORD0 Register + 0x368 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD146 + Message Buffer 46 WORD1 Register + 0x36C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS47 + Message Buffer 47 CS Register + 0x370 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID47 + Message Buffer 47 ID Register + 0x374 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD047 + Message Buffer 47 WORD0 Register + 0x378 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD147 + Message Buffer 47 WORD1 Register + 0x37C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS48 + Message Buffer 48 CS Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID48 + Message Buffer 48 ID Register + 0x384 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD048 + Message Buffer 48 WORD0 Register + 0x388 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD148 + Message Buffer 48 WORD1 Register + 0x38C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS49 + Message Buffer 49 CS Register + 0x390 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID49 + Message Buffer 49 ID Register + 0x394 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD049 + Message Buffer 49 WORD0 Register + 0x398 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD149 + Message Buffer 49 WORD1 Register + 0x39C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS50 + Message Buffer 50 CS Register + 0x3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID50 + Message Buffer 50 ID Register + 0x3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD050 + Message Buffer 50 WORD0 Register + 0x3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD150 + Message Buffer 50 WORD1 Register + 0x3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS51 + Message Buffer 51 CS Register + 0x3B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID51 + Message Buffer 51 ID Register + 0x3B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD051 + Message Buffer 51 WORD0 Register + 0x3B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD151 + Message Buffer 51 WORD1 Register + 0x3BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS52 + Message Buffer 52 CS Register + 0x3C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID52 + Message Buffer 52 ID Register + 0x3C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD052 + Message Buffer 52 WORD0 Register + 0x3C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD152 + Message Buffer 52 WORD1 Register + 0x3CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS53 + Message Buffer 53 CS Register + 0x3D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID53 + Message Buffer 53 ID Register + 0x3D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD053 + Message Buffer 53 WORD0 Register + 0x3D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD153 + Message Buffer 53 WORD1 Register + 0x3DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS54 + Message Buffer 54 CS Register + 0x3E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID54 + Message Buffer 54 ID Register + 0x3E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD054 + Message Buffer 54 WORD0 Register + 0x3E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD154 + Message Buffer 54 WORD1 Register + 0x3EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS55 + Message Buffer 55 CS Register + 0x3F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID55 + Message Buffer 55 ID Register + 0x3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD055 + Message Buffer 55 WORD0 Register + 0x3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD155 + Message Buffer 55 WORD1 Register + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS56 + Message Buffer 56 CS Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID56 + Message Buffer 56 ID Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD056 + Message Buffer 56 WORD0 Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD156 + Message Buffer 56 WORD1 Register + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS57 + Message Buffer 57 CS Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID57 + Message Buffer 57 ID Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD057 + Message Buffer 57 WORD0 Register + 0x418 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD157 + Message Buffer 57 WORD1 Register + 0x41C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS58 + Message Buffer 58 CS Register + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID58 + Message Buffer 58 ID Register + 0x424 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD058 + Message Buffer 58 WORD0 Register + 0x428 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD158 + Message Buffer 58 WORD1 Register + 0x42C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS59 + Message Buffer 59 CS Register + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID59 + Message Buffer 59 ID Register + 0x434 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD059 + Message Buffer 59 WORD0 Register + 0x438 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD159 + Message Buffer 59 WORD1 Register + 0x43C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS60 + Message Buffer 60 CS Register + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID60 + Message Buffer 60 ID Register + 0x444 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD060 + Message Buffer 60 WORD0 Register + 0x448 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD160 + Message Buffer 60 WORD1 Register + 0x44C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS61 + Message Buffer 61 CS Register + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID61 + Message Buffer 61 ID Register + 0x454 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD061 + Message Buffer 61 WORD0 Register + 0x458 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD161 + Message Buffer 61 WORD1 Register + 0x45C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS62 + Message Buffer 62 CS Register + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID62 + Message Buffer 62 ID Register + 0x464 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD062 + Message Buffer 62 WORD0 Register + 0x468 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD162 + Message Buffer 62 WORD1 Register + 0x46C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + CS63 + Message Buffer 63 CS Register + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 0x10 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 0x14 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 0x15 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 0x16 + 1 + read-write + + + CODE + Reserved + 0x18 + 4 + read-write + + + + + ID63 + Message Buffer 63 ID Register + 0x474 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 0x12 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 0x1D + 3 + read-write + + + + + WORD063 + Message Buffer 63 WORD0 Register + 0x478 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 3 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 2 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 1 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_0 + Data byte 0 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + WORD163 + Message Buffer 63 WORD1 Register + 0x47C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 7 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 6 of Rx/Tx frame. + 0x8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 5 of Rx/Tx frame. + 0x10 + 8 + read-write + + + DATA_BYTE_4 + Data byte 4 of Rx/Tx frame. + 0x18 + 8 + read-write + + + + + 64 + 0x4 + RXIMR%s + Rx Individual Mask Registers + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + MI + These bits mask both Mailbox filter and Rx FIFO ID Filter Table element in distinct ways + 0 + 32 + read-write + + + MI_0 + the corresponding bit in the filter is "don't care" + 0 + + + MI_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + GFWR + Glitch Filter Width Registers + 0x9E0 + 32 + read-write + 0x7F + 0xFFFFFFFF + + + GFWR + It determines the Glitch Filter Width + 0 + 8 + read-write + + + + + + + CAN2 + CAN + CAN + CAN2_ + 0x2094000 + + 0 + 0x9E4 + registers + + + CAN2 + 143 + + + + GPT1 + GPT + GPT + GPT1_ + 0x2098000 + GPT + + 0 + 0x28 + registers + + + GPT1 + 87 + + + + CR + GPT Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + GPT Enable + 0 + 1 + read-write + + + EN_0 + GPT is disabled. + 0 + + + EN_1 + GPT is enabled. + 0x1 + + + + + ENMOD + GPT Enable mode + 0x1 + 1 + read-write + + + ENMOD_0 + GPT counter will retain its value when it is disabled. + 0 + + + ENMOD_1 + GPT counter value is reset to 0 when it is disabled. + 0x1 + + + + + DBGEN + GPT debug mode enable + 0x2 + 1 + read-write + + + DBGEN_0 + GPT is disabled in debug mode. + 0 + + + DBGEN_1 + GPT is enabled in debug mode. + 0x1 + + + + + WAITEN + GPT Wait Mode enable + 0x3 + 1 + read-write + + + WAITEN_0 + GPT is disabled in wait mode. + 0 + + + WAITEN_1 + GPT is enabled in wait mode. + 0x1 + + + + + DOZEEN + GPT Doze Mode Enable + 0x4 + 1 + read-write + + + DOZEEN_0 + GPT is disabled in doze mode. + 0 + + + DOZEEN_1 + GPT is enabled in doze mode. + 0x1 + + + + + STOPEN + GPT Stop Mode enable + 0x5 + 1 + read-write + + + STOPEN_0 + GPT is disabled in Stop mode. + 0 + + + STOPEN_1 + GPT is enabled in Stop mode. + 0x1 + + + + + CLKSRC + Clock Source select + 0x6 + 3 + read-write + + + CLKSRC_0 + No clock + 0 + + + CLKSRC_1 + Peripheral Clock (ipg_clk) + 0x1 + + + CLKSRC_2 + High Frequency Reference Clock (ipg_clk_highfreq) + 0x2 + + + CLKSRC_3 + External Clock + 0x3 + + + CLKSRC_4 + Low Frequency Reference Clock (ipg_clk_32k) + 0x4 + + + CLKSRC_5 + Crystal oscillator as Reference Clock (ipg_clk_24M) + 0x5 + + + + + FRR + Free-Run or Restart mode + 0x9 + 1 + read-write + + + FRR_0 + Restart mode + 0 + + + FRR_1 + Free-Run mode + 0x1 + + + + + EN_24M + Enable 24 MHz clock input from crystal + 0xA + 1 + read-write + + + EN_24M_0 + 24M clock disabled + 0 + + + EN_24M_1 + 24M clock enabled + 0x1 + + + + + SWR + Software reset + 0xF + 1 + read-write + + + SWR_0 + GPT is not in reset state + 0 + + + SWR_1 + GPT is in reset state + 0x1 + + + + + IM1 + See IM2 + 0x10 + 2 + read-write + + + IM2 + IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event + 0x12 + 2 + read-write + + + IM2_0 + capture disabled + 0 + + + IM2_1 + capture on rising edge only + 0x1 + + + IM2_2 + capture on falling edge only + 0x2 + + + IM2_3 + capture on both edges + 0x3 + + + + + OM1 + See OM3 + 0x14 + 3 + read-write + + + OM2 + See OM3 + 0x17 + 3 + read-write + + + OM3 + OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode + 0x1A + 3 + read-write + + + OM3_0 + Output disconnected. No response on pin. + 0 + + + OM3_1 + Toggle output pin + 0x1 + + + OM3_2 + Clear output pin + 0x2 + + + OM3_3 + Set output pin + 0x3 + + + + + FO1 + See F03 + 0x1D + 1 + write-only + + + FO2 + See F03 + 0x1E + 1 + write-only + + + FO3 + FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register) + 0x1F + 1 + write-only + + + FO3_0 + Writing a 0 has no effect. + 0 + + + FO3_1 + Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + 0x1 + + + + + + + PR + GPT Prescaler Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESCALER + Prescaler bits + 0 + 12 + read-write + + + PRESCALER_0 + Divide by 1 + 0 + + + PRESCALER_1 + Divide by 2 + 0x1 + + + PRESCALER_4095 + Divide by 4096 + 0xFFF + + + + + PRESCALER24M + Prescaler bits + 0xC + 4 + read-write + + + PRESCALER24M_0 + Divide by 1 + 0 + + + PRESCALER24M_1 + Divide by 2 + 0x1 + + + PRESCALER24M_15 + Divide by 16 + 0xF + + + + + + + SR + GPT Status Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1 + See OF3 + 0 + 1 + read-write + oneToClear + + + OF2 + See OF3 + 0x1 + 1 + read-write + oneToClear + + + OF3 + OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n + 0x2 + 1 + read-write + oneToClear + + + OF3_0 + Compare event has not occurred. + 0 + + + OF3_1 + Compare event has occurred. + 0x1 + + + + + IF1 + See IF2 + 0x3 + 1 + read-write + oneToClear + + + IF2 + IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n + 0x4 + 1 + read-write + oneToClear + + + IF2_0 + Capture event has not occurred. + 0 + + + IF2_1 + Capture event has occurred. + 0x1 + + + + + ROV + Rollover Flag + 0x5 + 1 + read-write + oneToClear + + + ROV_0 + Rollover has not occurred. + 0 + + + ROV_1 + Rollover has occurred. + 0x1 + + + + + + + IR + GPT Interrupt Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1IE + See OF3IE + 0 + 1 + read-write + + + OF2IE + See OF3IE + 0x1 + 1 + read-write + + + OF3IE + OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt + 0x2 + 1 + read-write + + + OF3IE_0 + Output Compare Channel n interrupt is disabled. + 0 + + + OF3IE_1 + Output Compare Channel n interrupt is enabled. + 0x1 + + + + + IF1IE + See IF2IE + 0x3 + 1 + read-write + + + IF2IE + IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable + 0x4 + 1 + read-write + + + IF2IE_0 + IF2IE Input Capture n Interrupt Enable is disabled. + 0 + + + IF2IE_1 + IF2IE Input Capture n Interrupt Enable is enabled. + 0x1 + + + + + ROVIE + Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt. + 0x5 + 1 + read-write + + + ROVIE_0 + Rollover interrupt is disabled. + 0 + + + ROVIE_1 + Rollover interrupt enabled. + 0x1 + + + + + + + OCR1 + GPT Output Compare Register 1 + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + OCR2 + GPT Output Compare Register 2 + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + OCR3 + GPT Output Compare Register 3 + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + ICR1 + GPT Input Capture Register 1 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + Capture Value + 0 + 32 + read-only + + + + + ICR2 + GPT Input Capture Register 2 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + Capture Value + 0 + 32 + read-only + + + + + CNT + GPT Counter Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Counter Value. The COUNT bits show the current count value of the GPT counter. + 0 + 32 + read-only + + + + + + + GPT2 + GPT + GPT + GPT2_ + 0x20E8000 + + 0 + 0x28 + registers + + + GPT2 + 141 + + + + GPIO1 + GPIO + GPIO + GPIO1_ + 0x209C000 + GPIO + + 0 + 0x20 + registers + + + GPIO1_INT7 + 90 + + + GPIO1_INT6 + 91 + + + GPIO1_INT5 + 92 + + + GPIO1_INT4 + 93 + + + GPIO1_INT3 + 94 + + + GPIO1_INT2 + 95 + + + GPIO1_INT1 + 96 + + + GPIO1_INT0 + 97 + + + GPIO1_Combined_0_15 + 98 + + + GPIO1_Combined_16_31 + 99 + + + + DR + GPIO data register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DR + Data bits + 0 + 32 + read-write + + + + + GDIR + GPIO direction register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GDIR + GPIO direction bits + 0 + 32 + read-write + + + INPUT + GPIO is configured as input. + 0 + + + OUTPUT + GPIO is configured as output. + 0x1 + + + + + + + PSR + GPIO pad status register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PSR + GPIO pad status bits (status bits) + 0 + 32 + read-only + + + + + ICR1 + GPIO interrupt configuration register1 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR0 + Interrupt configuration 1 fields + 0 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR1 + Interrupt configuration 1 fields + 0x2 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR2 + Interrupt configuration 1 fields + 0x4 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR3 + Interrupt configuration 1 fields + 0x6 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR4 + Interrupt configuration 1 fields + 0x8 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR5 + Interrupt configuration 1 fields + 0xA + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR6 + Interrupt configuration 1 fields + 0xC + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR7 + Interrupt configuration 1 fields + 0xE + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR8 + Interrupt configuration 1 fields + 0x10 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR9 + Interrupt configuration 1 fields + 0x12 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR10 + Interrupt configuration 1 fields + 0x14 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR11 + Interrupt configuration 1 fields + 0x16 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR12 + Interrupt configuration 1 fields + 0x18 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR13 + Interrupt configuration 1 fields + 0x1A + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR14 + Interrupt configuration 1 fields + 0x1C + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR15 + Interrupt configuration 1 fields + 0x1E + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + + + ICR2 + GPIO interrupt configuration register2 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR16 + Interrupt configuration 2 fields + 0 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR17 + Interrupt configuration 2 fields + 0x2 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR18 + Interrupt configuration 2 fields + 0x4 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR19 + Interrupt configuration 2 fields + 0x6 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR20 + Interrupt configuration 2 fields + 0x8 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR21 + Interrupt configuration 2 fields + 0xA + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR22 + Interrupt configuration 2 fields + 0xC + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR23 + Interrupt configuration 2 fields + 0xE + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR24 + Interrupt configuration 2 fields + 0x10 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR25 + Interrupt configuration 2 fields + 0x12 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR26 + Interrupt configuration 2 fields + 0x14 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR27 + Interrupt configuration 2 fields + 0x16 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR28 + Interrupt configuration 2 fields + 0x18 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR29 + Interrupt configuration 2 fields + 0x1A + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR30 + Interrupt configuration 2 fields + 0x1C + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR31 + Interrupt configuration 2 fields + 0x1E + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + + + IMR + GPIO interrupt mask register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR + Interrupt Mask bits + 0 + 32 + read-write + + + UNMASKED + Interrupt n is disabled. + 0 + + + MASKED + Interrupt n is enabled. + 0x1 + + + + + + + ISR + GPIO interrupt status register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISR + Interrupt status bits - Bit n of this register is asserted (active high) when the active condition (as determined by the corresponding ICR bit) is detected on the GPIO input and is waiting for service + 0 + 32 + read-write + oneToClear + + + + + EDGE_SEL + GPIO edge select register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO_EDGE_SEL + Edge select + 0 + 32 + read-write + + + + + + + GPIO2 + GPIO + GPIO + GPIO2_ + 0x20A0000 + + 0 + 0x20 + registers + + + GPIO2_Combined_0_15 + 100 + + + GPIO2_Combined_16_31 + 101 + + + + GPIO3 + GPIO + GPIO + GPIO3_ + 0x20A4000 + + 0 + 0x20 + registers + + + GPIO3_Combined_0_15 + 102 + + + GPIO3_Combined_16_31 + 103 + + + + GPIO4 + GPIO + GPIO + GPIO4_ + 0x20A8000 + + 0 + 0x20 + registers + + + GPIO4_Combined_0_15 + 104 + + + GPIO4_Combined_16_31 + 105 + + + + GPIO5 + GPIO + GPIO + GPIO5_ + 0x20AC000 + + 0 + 0x20 + registers + + + GPIO5_Combined_0_15 + 106 + + + GPIO5_Combined_16_31 + 107 + + + + SNVS + SNVS + SNVS + SNVS_ + 0x20B0000 + + 0 + 0xC00 + registers + + + SNVS + 36 + + + SNVS_Consolidated + 51 + + + SNVS_Security + 52 + + + + HPLR + SNVS_HP Lock register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MC_SL + Monotonic Counter Soft Lock When set, it prevents any writes (increments) to the MC registers and the MC_ENV bit + 0x4 + 1 + read-write + + + MC_SL_0 + Write access (increment) is allowed. + 0 + + + MC_SL_1 + Write access (increment) is not allowed. + 0x1 + + + + + GPR_SL + General-Purpose Register Soft Lock When set, it prevents any writes to the GPR + 0x5 + 1 + read-write + + + GPR_SL_0 + Write access is allowed. + 0 + + + GPR_SL_1 + Write access is not allowed. + 0x1 + + + + + + + HPCOMR + SNVS_HP Command register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + LP_SWR + LP Software Reset When set, it resets the SNVS_LP section + 0x4 + 1 + write-only + + + LP_SWR_0 + No action + 0 + + + LP_SWR_1 + Reset LP section + 0x1 + + + + + LP_SWR_DIS + LP Software Reset Disable When set, it disables the LP software reset + 0x5 + 1 + read-write + + + LP_SWR_DIS_0 + LP software reset is enabled. + 0 + + + LP_SWR_DIS_1 + LP software reset is disabled. + 0x1 + + + + + NPSWA_EN + Non-Privileged Software Access Enable When set, it allows non-privileged software to access all SNVS registers, including those that are privileged-software read/write access only + 0x1F + 1 + read-write + + + + + HPCR + SNVS_HP Control register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC_EN + HP Real-Time Counter Enable + 0 + 1 + read-write + + + RTC_EN_0 + RTC is disabled. + 0 + + + RTC_EN_1 + RTC is enabled. + 0x1 + + + + + HPTA_EN + HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP time alarm registers is equal to the value of the HP real-time counter + 0x1 + 1 + read-write + + + HPTA_EN_0 + HP time alarm interrupt is disabled. + 0 + + + HPTA_EN_1 + HP time alarm interrupt is enabled. + 0x1 + + + + + PI_EN + HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP real-time counter is enabled + 0x3 + 1 + read-write + + + PI_EN_0 + HP periodic interrupt is disabled. + 0 + + + PI_EN_1 + HP periodic interrupt is enabled. + 0x1 + + + + + PI_FREQ + Periodic Interrupt Frequency Defines the frequency of the periodic interrupt + 0x4 + 4 + read-write + + + PI_FREQ_0 + - Bit 0 of the RTC is selected as the source of the periodic interrupt. + 0 + + + PI_FREQ_1 + - Bit 1 of the RTC is selected as the source of the periodic interrupt. + 0x1 + + + PI_FREQ_2 + - Bit 2 of the RTC is selected as the source of the periodic interrupt. + 0x2 + + + PI_FREQ_3 + - Bit 3 of the RTC is selected as the source of the periodic interrupt. + 0x3 + + + PI_FREQ_4 + - Bit 4 of the RTC is selected as the source of the periodic interrupt. + 0x4 + + + PI_FREQ_5 + - Bit 5 of the RTC is selected as the source of the periodic interrupt. + 0x5 + + + PI_FREQ_6 + - Bit 6 of the RTC is selected as the source of the periodic interrupt. + 0x6 + + + PI_FREQ_7 + - Bit 7 of the RTC is selected as the source of the periodic interrupt. + 0x7 + + + PI_FREQ_8 + - Bit 8 of the RTC is selected as the source of the periodic interrupt. + 0x8 + + + PI_FREQ_9 + - Bit 9 of the RTC is selected as the source of the periodic interrupt. + 0x9 + + + PI_FREQ_10 + - Bit 10 of the RTC is selected as the source of the periodic interrupt. + 0xA + + + PI_FREQ_11 + - Bit 11 of the RTC is selected as the source of the periodic interrupt. + 0xB + + + PI_FREQ_12 + - Bit 12 of the RTC is selected as the source of the periodic interrupt. + 0xC + + + PI_FREQ_13 + - Bit 13 of the RTC is selected as the source of the periodic interrupt. + 0xD + + + PI_FREQ_14 + - Bit 14 of the RTC is selected as the source of the periodic interrupt. + 0xE + + + PI_FREQ_15 + - Bit 15 of the RTC is selected as the source of the periodic interrupt. + 0xF + + + + + HPCALB_EN + HP Real-Time Counter Calibration Enabled Indicates that the time-calibration mechanism is enabled. + 0x8 + 1 + read-write + + + HPCALB_EN_0 + HP timer calibration is disabled. + 0 + + + HPCALB_EN_1 + HP timer calibration is enabled. + 0x1 + + + + + HPCALB_VAL + HP Calibration Value Defines the signed calibration value for the HP real-time counter + 0xA + 5 + read-write + + + HPCALB_VAL_0 + +0 counts per each 32768 ticks of the counter + 0 + + + HPCALB_VAL_1 + +1 counts per each 32768 ticks of the counter + 0x1 + + + HPCALB_VAL_2 + +2 counts per each 32768 ticks of the counter + 0x2 + + + HPCALB_VAL_15 + +15 counts per each 32768 ticks of the counter + 0xF + + + HPCALB_VAL_16 + -16 counts per each 32768 ticks of the counter + 0x10 + + + HPCALB_VAL_17 + -15 counts per each 32768 ticks of the counter + 0x11 + + + HPCALB_VAL_30 + -2 counts per each 32768 ticks of the counter + 0x1E + + + HPCALB_VAL_31 + -1 counts per each 32768 ticks of the counter + 0x1F + + + + + BTN_CONFIG + Button configuration + 0x18 + 3 + read-write + + + BTN_MASK + Button interrupt mask + 0x1B + 1 + read-write + + + + + HPSR + SNVS_HP Status register + 0x14 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + BTN + Value of the BTN input + 0x6 + 1 + read-only + + + BI + Button interrupt. The ipi_snvs_btn_int_b signal was asserted. + 0x7 + 1 + read-write + oneToClear + + + + + HPRTCMR + SNVS_HP Real-Time Counter MSB Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + HP Real-Time Counter Most significant 32 bits + 0 + 32 + read-write + + + + + HPRTCLR + SNVS_HP Real-Time Counter LSB Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + HP Real-Time Counter Least significant 32 bits + 0 + 32 + read-write + + + + + HPTAMR + SNVS_HP Time Alarm MSB Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA + HP Time Alarm Most significant 15 bits + 0 + 15 + read-write + + + + + HPTALR + SNVS_HP Time Alarm LSB Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA + HP Time Alarm The least significant bits + 0 + 32 + read-write + + + + + LPLR + SNVS_LP Lock Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + MC_HL + Monotonic Counter Hard Lock When set, it blocks any writes (increments) to the MC registers and the MC_ENV bit + 0x4 + 1 + read-write + + + MC_HL_0 + Write access (increment) is allowed. + 0 + + + MC_HL_1 + Write access (increment) is not allowed. + 0x1 + + + + + GPR_HL + General-Purpose Register Hard Lock When set, it blocks any writes to the GPR + 0x5 + 1 + read-write + + + GPR_HL_0 + Write access is allowed. + 0 + + + GPR_HL_1 + Write access is not allowed. + 0x1 + + + + + + + LPCR + SNVS_LP Control Register + 0x38 + 32 + read-write + 0x20 + 0xFFFFFFFF + + + MC_ENV + Monotonic Counter Enable and Valid When set, the MC can be incremented (by a write transaction to the LPSMCMR or LPSMCLR) + 0x2 + 1 + read-write + + + MC_ENV_0 + MC is disabled or invalid. + 0 + + + MC_ENV_1 + MC is enabled and valid. + 0x1 + + + + + DP_EN + Dumb PMIC Enabled When set, the software can control the system power + 0x5 + 1 + read-write + + + DP_EN_0 + Smart PMIC is enabled. + 0 + + + DP_EN_1 + Dumb PMIC is enabled. + 0x1 + + + + + TOP + Turn off System Power Asserting this bit causes a signal to be sent to the power management IC to turn the system power off + 0x6 + 1 + read-write + + + TOP_0 + Leave the system power on. + 0 + + + TOP_1 + Turn the system power off. + 0x1 + + + + + PWR_GLITCH_EN + By default, the detection of a power glitch does not cause the pmic_en_b signal to be asserted + 0x7 + 1 + read-write + + + BTN_PRESS_TIME + Button press timeout values for the PMIC logic + 0x10 + 2 + read-write + + + DEBOUNCE + This field configures the amount of debounce time for the BTN input signal + 0x12 + 2 + read-write + + + ON_TIME + The ON_TIME field is used to configure the period of time after the BTN is asserted before the pmic_en_b is asserted to turn on the SoC power + 0x14 + 2 + read-write + + + PK_EN + PMIC On Request Enable + 0x16 + 1 + read-write + + + PK_OVERRIDE + PMIC On Request Override + 0x17 + 1 + read-write + + + + + LPSR + SNVS_LP Status Register + 0x4C + 32 + read-write + 0x8 + 0xFFFFFFFF + + + MCR + Monotonic Counter Rollover + 0x2 + 1 + read-write + oneToClear + + + MCR_0 + MC did not reach its maximum value. + 0 + + + MCR_1 + MC reached its maximum value. + 0x1 + + + + + EO + Emergency Off This bit is set when a power off is requested. + 0x11 + 1 + read-write + oneToClear + + + EO_0 + Emergency off is not detected. + 0 + + + EO_1 + Emergency off is detected. + 0x1 + + + + + SPO + Set Power Off The SPO bit is set when the set_pwr_off_irq interrupt is triggered, which happens when the software writes a 1 to the TOP bit in the LPCR or when the power button is pressed longer than the configured debounce time + 0x12 + 1 + read-write + oneToClear + + + SPO_0 + Emergency off is not detected. + 0 + + + SPO_1 + Emergency off is detected. + 0x1 + + + + + + + LPSMCMR + SNVS_LP Secure Monotonic Counter MSB Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + MON_COUNTER + Monotonic Counter Most-Significant 16 Bits The MC is incremented by one when: A write transaction to the LPSMCMR register or the LPSMCLR register is detected + 0 + 16 + read-write + + + MC_ERA_BITS + Monotonic Counter Era Bits These bits are the inputs to the module and are typically connected to the fuses + 0x10 + 16 + read-write + + + + + LPSMCLR + SNVS_LP Secure Monotonic Counter LSB Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + MON_COUNTER + Monotonic Counter bits The MC is incremented by one when: A write transaction to the LPSMCMR register or the LPSMCLR register is detected + 0 + 32 + read-write + + + + + LPGPR + SNVS_LP General-Purpose Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General-Purpose Register When the GPR_SL or GPR_HL bit is set, the register can't be programmed. + 0 + 32 + read-write + + + + + HPVIDR1 + SNVS_HP Version ID Register 1 + 0xBF8 + 32 + read-only + 0x3E0300 + 0xFFFFFFFF + + + MINOR_REV + SNVS block minor version number + 0 + 8 + read-only + + + MAJOR_REV + SNVS block major version number + 0x8 + 8 + read-only + + + IP_ID + SNVS block ID + 0x10 + 16 + read-only + + + + + HPVIDR2 + SNVS_HP Version ID Register 2 + 0xBFC + 32 + read-only + 0x3000000 + 0xFFFFFFFF + + + CONFIG_OPT + SNVS Configuration Option + 0 + 8 + read-only + + + ECO_REV + SNVS ECO Revision + 0x8 + 8 + read-only + + + INTG_OPT + SNVS Integration Option + 0x10 + 8 + read-only + + + IP_ERA + Era of the IP design + 0x18 + 8 + read-only + + + + + + + KPP + KPP Registers + KPP + KPP_ + 0x20B8000 + + 0 + 0x8 + registers + + + KPP + 114 + + + + KPCR + Keypad Control Register + 0 + 16 + read-write + 0 + 0xFFFF + + + KRE + Keypad Row Enable + 0 + 8 + read-write + + + KRE_0 + Row is not included in the keypad key press detect. + 0 + + + KRE_1 + Row is included in the keypad key press detect. + 0x1 + + + + + KCO + Keypad Column Strobe Open-Drain Enable + 0x8 + 8 + read-write + + + TOTEM_POLE + Column strobe output is totem pole drive. + 0 + + + OPEN_DRAIN + Column strobe output is open drain. + 0x1 + + + + + + + KPSR + Keypad Status Register + 0x2 + 16 + read-write + 0x400 + 0xFFFF + + + KPKD + Keypad Key Depress + 0 + 1 + read-write + oneToClear + + + KPKD_0 + No key presses detected + 0 + + + KPKD_1 + A key has been depressed + 0x1 + + + + + KPKR + Keypad Key Release + 0x1 + 1 + read-write + oneToClear + + + KPKR_0 + No key release detected + 0 + + + KPKR_1 + All keys have been released + 0x1 + + + + + KDSC + Key Depress Synchronizer Clear + 0x2 + 1 + write-only + + + KDSC_0 + No effect + 0 + + + KDSC_1 + Set bits that clear the keypad depress synchronizer chain + 0x1 + + + + + KRSS + Key Release Synchronizer Set + 0x3 + 1 + write-only + + + KRSS_0 + No effect + 0 + + + KRSS_1 + Set bits which sets keypad release synchronizer chain + 0x1 + + + + + KDIE + Keypad Key Depress Interrupt Enable + 0x8 + 1 + read-write + + + KDIE_0 + No interrupt request is generated when KPKD is set. + 0 + + + KDIE_1 + An interrupt request is generated when KPKD is set. + 0x1 + + + + + KRIE + Keypad Release Interrupt Enable + 0x9 + 1 + read-write + + + KRIE_0 + No interrupt request is generated when KPKR is set. + 0 + + + KRIE_1 + An interrupt request is generated when KPKR is set. + 0x1 + + + + + + + KDDR + Keypad Data Direction Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + KRDD + Keypad Row Data Direction + 0 + 8 + read-write + + + INPUT + ROWn pin configured as an input. + 0 + + + OUTPUT + ROWn pin configured as an output. + 0x1 + + + + + KCDD + Keypad Column Data Direction Register + 0x8 + 8 + read-write + + + INPUT + COLn pin is configured as an input. + 0 + + + OUTPUT + COLn pin is configured as an output. + 0x1 + + + + + + + KPDR + Keypad Data Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + KRD + Keypad Row Data + 0 + 8 + read-write + + + KCD + Keypad Column Data + 0x8 + 8 + read-write + + + + + + + WDOG1 + WDOG + WDOG + WDOG1_ + 0x20BC000 + WDOG + + 0 + 0xA + registers + + + WDOG1 + 112 + + + + WCR + Watchdog Control Register + 0 + 16 + read-write + 0x30 + 0xFFFF + + + WDZST + Watchdog Low Power + 0 + 1 + read-write + + + WDZST_0 + Continue timer operation (Default). + 0 + + + WDZST_1 + Suspend the watchdog timer. + 0x1 + + + + + WDBG + Watchdog DEBUG Enable + 0x1 + 1 + read-write + + + WDBG_0 + Continue WDOG timer operation (Default). + 0 + + + WDBG_1 + Suspend the watchdog timer. + 0x1 + + + + + WDE + Watchdog Enable + 0x2 + 1 + read-write + + + WDE_0 + Disable the Watchdog (Default). + 0 + + + WDE_1 + Enable the Watchdog. + 0x1 + + + + + WDT + WDOG_B Time-out assertion + 0x3 + 1 + read-write + + + WDT_0 + No effect on WDOG_B (Default). + 0 + + + WDT_1 + Assert WDOG_B upon a Watchdog Time-out event. + 0x1 + + + + + SRS + Software Reset Signal + 0x4 + 1 + read-write + + + SRS_0 + Assert system reset signal. + 0 + + + SRS_1 + No effect on the system (Default). + 0x1 + + + + + WDA + WDOG_B assertion. Controls the software assertion of the WDOG_B signal. + 0x5 + 1 + read-write + + + WDA_0 + Assert WDOG_B output. + 0 + + + WDA_1 + No effect on system (Default). + 0x1 + + + + + SRE + software reset extension, an option way to generate software reset + 0x6 + 1 + read-write + + + SRE_0 + using original way to generate software reset (default) + 0 + + + SRE_1 + using new way to generate software reset. + 0x1 + + + + + WDW + Watchdog Disable for Wait + 0x7 + 1 + read-write + + + WDW_0 + Continue WDOG timer operation (Default). + 0 + + + WDW_1 + Suspend WDOG timer operation. + 0x1 + + + + + WT + Watchdog Time-out Field + 0x8 + 8 + read-write + + + WT_0 + - 0.5 Seconds (Default). + 0 + + + WT_1 + - 1.0 Seconds. + 0x1 + + + WT_2 + - 1.5 Seconds. + 0x2 + + + WT_3 + - 2.0 Seconds. + 0x3 + + + WT_255 + - 128 Seconds. + 0xFF + + + + + + + WSR + Watchdog Service Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + WSR + Watchdog Service Register + 0 + 16 + read-write + + + WSR_21845 + Write to the Watchdog Service Register (WDOG_WSR). + 0x5555 + + + WSR_43690 + Write to the Watchdog Service Register (WDOG_WSR). + 0xAAAA + + + + + + + WRSR + Watchdog Reset Status Register + 0x4 + 16 + read-only + 0 + 0xFFFF + + + SFTW + Software Reset + 0 + 1 + read-only + + + SFTW_0 + Reset is not the result of a software reset. + 0 + + + SFTW_1 + Reset is the result of a software reset. + 0x1 + + + + + TOUT + Timeout. Indicates whether the reset is the result of a WDOG timeout. + 0x1 + 1 + read-only + + + TOUT_0 + Reset is not the result of a WDOG timeout. + 0 + + + TOUT_1 + Reset is the result of a WDOG timeout. + 0x1 + + + + + POR + Power On Reset. Indicates whether the reset is the result of a power on reset. + 0x4 + 1 + read-only + + + POR_0 + Reset is not the result of a power on reset. + 0 + + + POR_1 + Reset is the result of a power on reset. + 0x1 + + + + + + + WICR + Watchdog Interrupt Control Register + 0x6 + 16 + read-write + 0x4 + 0xFFFF + + + WICT + Watchdog Interrupt Count Time-out (WICT) field determines, how long before the counter time-out must the interrupt occur + 0 + 8 + read-write + + + WICT_0 + WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + 0 + + + WICT_1 + WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + 0x1 + + + WICT_4 + WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + 0x4 + + + WICT_255 + WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + 0xFF + + + + + WTIS + Watchdog TImer Interrupt Status bit will reflect the timer interrupt status, whether interrupt has occurred or not + 0xE + 1 + read-write + oneToClear + + + WTIS_0 + No interrupt has occurred (Default). + 0 + + + WTIS_1 + Interrupt has occurred + 0x1 + + + + + WIE + Watchdog Timer Interrupt enable bit + 0xF + 1 + read-write + + + WIE_0 + Disable Interrupt (Default). + 0 + + + WIE_1 + Enable Interrupt. + 0x1 + + + + + + + WMCR + Watchdog Miscellaneous Control Register + 0x8 + 16 + read-write + 0x1 + 0xFFFF + + + PDE + Power Down Enable bit + 0 + 1 + read-write + + + PDE_0 + Power Down Counter of WDOG is disabled. + 0 + + + PDE_1 + Power Down Counter of WDOG is enabled (Default). + 0x1 + + + + + + + + + WDOG2 + WDOG + WDOG + WDOG2_ + 0x20C0000 + + 0 + 0xA + registers + + + WDOG2 + 113 + + + + WDOG3 + WDOG + WDOG + WDOG3_ + 0x21E4000 + + 0 + 0xA + registers + + + WDOG3 + 43 + + + + CCM + CCM + CCM + CCM_ + 0x20C4000 + + 0 + 0x8C + registers + + + CCM_IRQ1 + 119 + + + CCM_IRQ2 + 120 + + + + CCR + CCM Control Register + 0 + 32 + read-write + 0x401167F + 0xFFFFFFFF + + + OSCNT + Oscillator ready counter value + 0 + 7 + read-write + + + OSCNT_0 + count 1 ckil + 0 + + + OSCNT_127 + count 128 ckil's + 0x7F + + + + + COSC_EN + On chip oscillator enable bit - this bit value is reflected on the output cosc_en + 0xC + 1 + read-write + + + COSC_EN_0 + disable on chip oscillator + 0 + + + COSC_EN_1 + enable on chip oscillator + 0x1 + + + + + REG_BYPASS_COUNT + Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ + 0x15 + 6 + read-write + + + REG_BYPASS_COUNT_0 + no delay + 0 + + + REG_BYPASS_COUNT_1 + 1 CKIL clock period delay + 0x1 + + + REG_BYPASS_COUNT_63 + 63 CKIL clock periods delay + 0x3F + + + + + RBC_EN + Enable for REG_BYPASS_COUNTER + 0x1B + 1 + read-write + + + RBC_EN_0 + REG_BYPASS_COUNTER disabled + 0 + + + RBC_EN_1 + REG_BYPASS_COUNTER enabled. + 0x1 + + + + + + + CCDR + CCM Control Divider Register + 0x4 + 32 + read-write + 0x20000 + 0xFFFFFFFF + + + MMDC_MASK + During divider ratio mmdc_axi_podf change or sync mux periph2_clk_sel change (but not jtag) or SRC request during warm reset, mask handshake with mmdc module + 0x10 + 1 + read-write + + + MMDC_MASK_0 + Allow handshake with mmdc module. + 0 + + + MMDC_MASK_1 + Mask handshake with mmdc. Request signal will not be generated. + 0x1 + + + + + + + CSR + CCM Status Register + 0x8 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + REF_EN_B + Status of the value of CCM_REF_EN_B output of ccm + 0 + 1 + read-only + + + REF_EN_B_0 + value of CCM_REF_EN_B is '0' + 0 + + + REF_EN_B_1 + value of CCM_REF_EN_B is '1' + 0x1 + + + + + COSC_READY + Status indication of on board oscillator + 0x5 + 1 + read-only + + + COSC_READY_0 + on board oscillator is not ready. + 0 + + + COSC_READY_1 + on board oscillator is ready. + 0x1 + + + + + + + CCSR + CCM Clock Switcher Register + 0xC + 32 + read-write + 0x100 + 0xFFFFFFFF + + + PLL3_SW_CLK_SEL + Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes. + 0 + 1 + read-write + + + PLL3_SW_CLK_SEL_0 + pll3_main_clk + 0 + + + PLL3_SW_CLK_SEL_1 + pll3 bypass clock + 0x1 + + + + + PLL1_SW_CLK_SEL + Selects source to generate pll1_sw_clk. + 0x2 + 1 + read-write + + + PLL1_SW_CLK_SEL_0 + pll1_main_clk + 0 + + + PLL1_SW_CLK_SEL_1 + step_clk + 0x1 + + + + + SECONDARY_CLK_SEL + Select source to generate secondary_clk + 0x3 + 1 + read-write + + + SECONDARY_CLK_SEL_0 + PLL2 PFD2 (400 M) + 0 + + + SECONDARY_CLK_SEL_1 + PLL2 (528 M) + 0x1 + + + + + STEP_SEL + Selects the option to be chosen for the step frequency when shifting ARM frequency + 0x8 + 1 + read-write + + + STEP_SEL_0 + derive clock from osc_clk (24M) - source for lp_apm. + 0 + + + STEP_SEL_1 + derive clock from secondary_clk + 0x1 + + + + + + + CACRR + CCM Arm Clock Root Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ARM_PODF + Divider for ARM clock root + 0 + 3 + read-write + + + ARM_PODF_0 + divide by 1 + 0 + + + ARM_PODF_1 + divide by 2 + 0x1 + + + ARM_PODF_2 + divide by 3 + 0x2 + + + ARM_PODF_3 + divide by 4 + 0x3 + + + ARM_PODF_4 + divide by 5 + 0x4 + + + ARM_PODF_5 + divide by 6 + 0x5 + + + ARM_PODF_6 + divide by 7 + 0x6 + + + ARM_PODF_7 + divide by 8 + 0x7 + + + + + + + CBCDR + CCM Bus Clock Divider Register + 0x14 + 32 + read-write + 0x18D00 + 0xFFFFFFFF + + + PERIPH2_CLK2_PODF + Divider for periph2_clk2 podf. Divider should be updated when output clock is gated. + 0 + 3 + read-write + + + PERIPH2_CLK2_PODF_0 + divide by 1 + 0 + + + PERIPH2_CLK2_PODF_1 + divide by 2 + 0x1 + + + PERIPH2_CLK2_PODF_2 + divide by 3 + 0x2 + + + PERIPH2_CLK2_PODF_3 + divide by 4 + 0x3 + + + PERIPH2_CLK2_PODF_4 + divide by 5 + 0x4 + + + PERIPH2_CLK2_PODF_5 + divide by 6 + 0x5 + + + PERIPH2_CLK2_PODF_6 + divide by 7 + 0x6 + + + PERIPH2_CLK2_PODF_7 + divide by 8 + 0x7 + + + + + FABRIC_MMDC_PODF + Post divider for fabric / mmdc clock. + 0x3 + 3 + read-write + + + FABRIC_MMDC_PODF_0 + divide by 1 + 0 + + + FABRIC_MMDC_PODF_1 + divide by 2 + 0x1 + + + FABRIC_MMDC_PODF_2 + divide by 3 + 0x2 + + + FABRIC_MMDC_PODF_3 + divide by 4 + 0x3 + + + FABRIC_MMDC_PODF_4 + divide by 5 + 0x4 + + + FABRIC_MMDC_PODF_5 + divide by 6 + 0x5 + + + FABRIC_MMDC_PODF_6 + divide by 7 + 0x6 + + + FABRIC_MMDC_PODF_7 + divide by 8 + 0x7 + + + + + AXI_CLK_SEL + AXI clock source select + 0x6 + 1 + read-write + + + AXI_CLK_SEL_0 + Periph_clk output will be used as AXI clock root + 0 + + + AXI_CLK_SEL_1 + AXI alternative clock will be used as AXI clock root + 0x1 + + + + + AXI_ALT_CLK_SEL + AXI alternative clock select + 0x7 + 1 + read-write + + + AXI_ALT_CLK_SEL_0 + PLL2 PFD2 will be selected as alternative clock for AXI root clock + 0 + + + AXI_ALT_CLK_SEL_1 + PLL3 PFD1 will be selected as alternative clock for AXI root clock + 0x1 + + + + + IPG_PODF + Divider for ipg podf + 0x8 + 2 + read-write + + + IPG_PODF_0 + divide by 1 + 0 + + + IPG_PODF_1 + divide by 2 + 0x1 + + + IPG_PODF_2 + divide by 3 + 0x2 + + + IPG_PODF_3 + divide by 4 + 0x3 + + + + + AHB_PODF + Divider for AHB PODF + 0xA + 3 + read-write + + + AHB_PODF_0 + divide by 1 + 0 + + + AHB_PODF_1 + divide by 2 + 0x1 + + + AHB_PODF_2 + divide by 3 + 0x2 + + + AHB_PODF_3 + divide by 4 + 0x3 + + + AHB_PODF_4 + divide by 5 + 0x4 + + + AHB_PODF_5 + divide by 6 + 0x5 + + + AHB_PODF_6 + divide by 7 + 0x6 + + + AHB_PODF_7 + divide by 8 + 0x7 + + + + + AXI_PODF + Post divider for axi clock + 0x10 + 3 + read-write + + + AXI_PODF_0 + Divide by 1 + 0 + + + AXI_PODF_1 + Divide by 2 + 0x1 + + + AXI_PODF_2 + Divide by 3 + 0x2 + + + AXI_PODF_3 + Divide by 4 + 0x3 + + + AXI_PODF_4 + Divide by 5 + 0x4 + + + AXI_PODF_5 + Divide by 6 + 0x5 + + + AXI_PODF_6 + Divide by 7 + 0x6 + + + AXI_PODF_7 + Divide by 8 + 0x7 + + + + + PERIPH_CLK_SEL + Selector for peripheral main clock) + 0x19 + 1 + read-write + + + PERIPH_CLK_SEL_0 + PLL2 (pll2_main_clk) + 0 + + + PERIPH_CLK_SEL_1 + derive clock from periph_clk2_clk clock source. + 0x1 + + + + + PERIPH2_CLK_SEL + Selector for peripheral2 main clock (source of mmdc_clk_root ) + 0x1A + 1 + read-write + + + PERIPH2_CLK_SEL_0 + PLL2 (pll2_main_clk) + 0 + + + PERIPH2_CLK_SEL_1 + derive clock from periph2_clk2_clk clock source. + 0x1 + + + + + PERIPH_CLK2_PODF + Divider for periph_clk2_podf. + 0x1B + 3 + read-write + + + PERIPH_CLK2_PODF_0 + divide by 1 + 0 + + + PERIPH_CLK2_PODF_1 + divide by 2 + 0x1 + + + PERIPH_CLK2_PODF_2 + divide by 3 + 0x2 + + + PERIPH_CLK2_PODF_3 + divide by 4 + 0x3 + + + PERIPH_CLK2_PODF_4 + divide by 5 + 0x4 + + + PERIPH_CLK2_PODF_5 + divide by 6 + 0x5 + + + PERIPH_CLK2_PODF_6 + divide by 7 + 0x6 + + + PERIPH_CLK2_PODF_7 + divide by 8 + 0x7 + + + + + + + CBCMR + CCM Bus Clock Multiplexer Register + 0x18 + 32 + read-write + 0x24860324 + 0xFFFFFFFF + + + PERIPH_CLK2_SEL + Selector for peripheral clk2 clock multiplexer + 0xC + 2 + read-write + + + PERIPH_CLK2_SEL_0 + derive clock from pll3_sw_clk + 0 + + + PERIPH_CLK2_SEL_1 + derive clock from osc_clk (pll1_ref_clk) + 0x1 + + + PERIPH_CLK2_SEL_2 + derive clock from pll2_bypass_clk + 0x2 + + + + + PRE_PERIPH_CLK_SEL + Selector for pre_periph clock multiplexer + 0x12 + 2 + read-write + + + PRE_PERIPH_CLK_SEL_0 + derive clock from PLL2 + 0 + + + PRE_PERIPH_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + PRE_PERIPH_CLK_SEL_2 + derive clock from PLL2 PFD0 + 0x2 + + + PRE_PERIPH_CLK_SEL_3 + derive clock from divided (/2) PLL2 PFD2 + 0x3 + + + + + PERIPH2_CLK2_SEL + Selector for periph2_clk2 clock multiplexer + 0x14 + 1 + read-write + + + PERIPH2_CLK2_SEL_0 + derive clock from pll3_sw_clk + 0 + + + PERIPH2_CLK2_SEL_1 + derive clock fromOSC + 0x1 + + + + + PRE_PERIPH2_CLK_SEL + Selector for pre_periph2 clock multiplexer + 0x15 + 2 + read-write + + + PRE_PERIPH2_CLK_SEL_0 + derive clock from PLL2 + 0 + + + PRE_PERIPH2_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + PRE_PERIPH2_CLK_SEL_2 + derive clock from PLL2 PFD0 + 0x2 + + + PRE_PERIPH2_CLK_SEL_3 + derive clock from PLL4 + 0x3 + + + + + LCDIF1_PODF + Post-divider for lcdif1 clock. + 0x17 + 3 + read-write + + + LCDIF1_PODF_0 + divide by 1 + 0 + + + LCDIF1_PODF_1 + divide by 2 + 0x1 + + + LCDIF1_PODF_2 + divide by 3 + 0x2 + + + LCDIF1_PODF_3 + divide by 4 + 0x3 + + + LCDIF1_PODF_4 + divide by 5 + 0x4 + + + LCDIF1_PODF_5 + divide by 6 + 0x5 + + + LCDIF1_PODF_6 + divide by 7 + 0x6 + + + LCDIF1_PODF_7 + divide by 8 + 0x7 + + + + + + + CSCMR1 + CCM Serial Clock Multiplexer Register 1 + 0x1C + 32 + read-write + 0x4900080 + 0xFFFFFFFF + + + PERCLK_PODF + Divider for perclk podf. + 0 + 6 + read-write + + + PERCLK_PODF_0 + divide by 1 + 0 + + + PERCLK_PODF_1 + divide by 2 + 0x1 + + + PERCLK_PODF_2 + divide by 3 + 0x2 + + + PERCLK_PODF_3 + divide by 4 + 0x3 + + + PERCLK_PODF_4 + divide by 5 + 0x4 + + + PERCLK_PODF_5 + divide by 6 + 0x5 + + + PERCLK_PODF_6 + divide by 7 + 0x6 + + + PERCLK_PODF_7 + divide by 8 + 0x7 + + + + + PERCLK_CLK_SEL + Selector for the perclk clock multiplexor + 0x6 + 1 + read-write + + + PERCLK_CLK_SEL_0 + derive clock from ipg clk root + 0 + + + PERCLK_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + QSPI1_CLK_SEL + QSPI1 clock select + 0x7 + 3 + read-write + + + QSPI1_CLK_SEL_0 + Derive clock from PLL3 + 0 + + + QSPI1_CLK_SEL_1 + Derive clock from PLL2 PFD0 + 0x1 + + + QSPI1_CLK_SEL_2 + Derive clock from PLL2 PFD2 + 0x2 + + + QSPI1_CLK_SEL_3 + Derive clock from PLL2 + 0x3 + + + QSPI1_CLK_SEL_4 + Derive clock from PLL3 PFD3 + 0x4 + + + QSPI1_CLK_SEL_5 + Derive clock from PLL3 PFD2 + 0x5 + + + + + SAI1_CLK_SEL + Selector for sai1 clock multiplexer + 0xA + 2 + read-write + + + SAI1_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI1_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI1_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + SAI2_CLK_SEL + Selector for sai2 clock multiplexer + 0xC + 2 + read-write + + + SAI2_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI2_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI2_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + SAI3_CLK_SEL + Selector for sai3 clock multiplexer + 0xE + 2 + read-write + + + SAI3_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI3_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI3_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + USDHC1_CLK_SEL + Selector for usdhc1 clock multiplexer + 0x10 + 1 + read-write + + + USDHC1_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + USDHC1_CLK_SEL_1 + derive clock from PLL2 PFD0 + 0x1 + + + + + USDHC2_CLK_SEL + Selector for usdhc2 clock multiplexer + 0x11 + 1 + read-write + + + USDHC2_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + USDHC2_CLK_SEL_1 + derive clock from PLL2 PFD0 + 0x1 + + + + + BCH_CLK_SEL + Selector for bch clock multiplexer + 0x12 + 1 + read-write + + + BCH_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + BCH_CLK_SEL_1 + derive clock from PLL2 PFD0 + 0x1 + + + + + GPMI_CLK_SEL + Selector for gpmi clock multiplexer + 0x13 + 1 + read-write + + + GPMI_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + GPMI_CLK_SEL_1 + derive clock from PLL2 PFD0 + 0x1 + + + + + ACLK_EIM_SLOW_PODF + Divider for aclk_eim_slow clock root. + 0x17 + 3 + read-write + + + ACLK_EIM_SLOW_PODF_0 + divide by 1 + 0 + + + ACLK_EIM_SLOW_PODF_1 + divide by 2 + 0x1 + + + ACLK_EIM_SLOW_PODF_2 + divide by 3 + 0x2 + + + ACLK_EIM_SLOW_PODF_3 + divide by 4 + 0x3 + + + ACLK_EIM_SLOW_PODF_4 + divide by 5 + 0x4 + + + ACLK_EIM_SLOW_PODF_5 + divide by 6 + 0x5 + + + ACLK_EIM_SLOW_PODF_6 + divide by 7 + 0x6 + + + ACLK_EIM_SLOW_PODF_7 + divide by 8 + 0x7 + + + + + QSPI1_PODF + Divider for QSPI1 clock root + 0x1A + 3 + read-write + + + QSPI1_PODF_0 + divide by 1 + 0 + + + QSPI1_PODF_1 + divide by 2 + 0x1 + + + QSPI1_PODF_7 + divide by 8 + 0x7 + + + + + ACLK_EIM_SLOW_SEL + Selector for aclk_eim_slow root clock multiplexer + 0x1D + 2 + read-write + + + ACLK_EIM_SLOW_SEL_0 + derive clock from AXI + 0 + + + ACLK_EIM_SLOW_SEL_1 + derive clock from pll3_sw_clk + 0x1 + + + ACLK_EIM_SLOW_SEL_2 + derive clock from PLL2 PFD2 + 0x2 + + + ACLK_EIM_SLOW_SEL_3 + derive clock from PLL3 PFD0 + 0x3 + + + + + + + CSCMR2 + CCM Serial Clock Multiplexer Register 2 + 0x20 + 32 + read-write + 0x3192F06 + 0xFFFFFFFF + + + CAN_CLK_PODF + Divider for can clock podf. + 0x2 + 6 + read-write + + + CAN_CLK_PODF_0 + divide by 1 + 0 + + + CAN_CLK_PODF_7 + divide by 8 + 0x7 + + + CAN_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + CAN_CLK_SEL + Selector for FlexCAN clock multiplexer + 0x8 + 2 + read-write + + + CAN_CLK_SEL_0 + derive clock from pll3_sw_clk divided clock (60M) + 0 + + + CAN_CLK_SEL_1 + derive clock from osc_clk (24M) + 0x1 + + + CAN_CLK_SEL_2 + derive clock from pll3_sw_clk divided clock (80M) + 0x2 + + + CAN_CLK_SEL_3 + Disable FlexCAN clock + 0x3 + + + + + LDB_DI0_DIV + Control for divider of ldb clock for di0 + 0xA + 1 + read-write + + + LDB_DI0_DIV_0 + divide by 3.5 + 0 + + + LDB_DI0_DIV_1 + divide by 7 + 0x1 + + + + + LDB_DI1_DIV + Control for divider of ldb clock for di1 + 0xB + 1 + read-write + + + LDB_DI1_DIV_0 + divide by 3.5 + 0 + + + LDB_DI1_DIV_1 + divide by 7 + 0x1 + + + + + ESAI_CLK_SEL + Selector for the ESAI clock + 0x13 + 2 + read-write + + + VID_CLK_SEL + Selector for vid clock multiplexer + 0x15 + 3 + read-write + + + VID_CLK_SEL_0 + PLL3 PFD1 + 0 + + + VID_CLK_SEL_1 + PLL3 + 0x1 + + + VID_CLK_SEL_2 + PLL3 PFD3 + 0x2 + + + VID_CLK_SEL_3 + PLL4 + 0x3 + + + VID_CLK_SEL_4 + PLL5 + 0x4 + + + + + VID_CLK_PRE_PODF + Post-divider for vid clock root + 0x18 + 2 + read-write + + + VID_CLK_PRE_PODF_0 + divide by 1 + 0 + + + VID_CLK_PRE_PODF_1 + divide by 2 + 0x1 + + + VID_CLK_PRE_PODF_2 + divide by 3 + 0x2 + + + VID_CLK_PRE_PODF_3 + divide by 4 + 0x3 + + + + + VID_CLK_PODF + Post-divider for vid clock root + 0x1A + 3 + read-write + + + VID_CLK_PODF_0 + divide by 1 + 0 + + + VID_CLK_PODF_1 + divide by 2 + 0x1 + + + VID_CLK_PODF_2 + divide by 3 + 0x2 + + + VID_CLK_PODF_3 + divide by 4 + 0x3 + + + VID_CLK_PODF_4 + divide by 5 + 0x4 + + + VID_CLK_PODF_5 + divide by 6 + 0x5 + + + VID_CLK_PODF_6 + divide by 7 + 0x6 + + + VID_CLK_PODF_7 + divide by 8 + 0x7 + + + + + + + CSCDR1 + CCM Serial Clock Divider Register 1 + 0x24 + 32 + read-write + 0x490B00 + 0xFFFFFFFF + + + UART_CLK_PODF + Divider for uart clock podf. + 0 + 6 + read-write + + + UART_CLK_PODF_0 + divide by 1 + 0 + + + UART_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + UART_CLK_SEL + Selector for the UART clock multiplexor + 0x6 + 1 + read-write + + + UART_CLK_SEL_0 + derive clock from pll3_80m + 0 + + + UART_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + USDHC1_PODF + Divider for usdhc1 clock podf. Divider should be updated when output clock is gated. + 0xB + 3 + read-write + + + USDHC1_PODF_0 + divide by 1 + 0 + + + USDHC1_PODF_1 + divide by 2 + 0x1 + + + USDHC1_PODF_2 + divide by 3 + 0x2 + + + USDHC1_PODF_3 + divide by 4 + 0x3 + + + USDHC1_PODF_4 + divide by 5 + 0x4 + + + USDHC1_PODF_5 + divide by 6 + 0x5 + + + USDHC1_PODF_6 + divide by 7 + 0x6 + + + USDHC1_PODF_7 + divide by 8 + 0x7 + + + + + USDHC2_PODF + Divider for usdhc2 clock. Divider should be updated when output clock is gated. + 0x10 + 3 + read-write + + + USDHC2_PODF_0 + divide by 1 + 0 + + + USDHC2_PODF_1 + divide by 2 + 0x1 + + + USDHC2_PODF_2 + divide by 3 + 0x2 + + + USDHC2_PODF_3 + divide by 4 + 0x3 + + + USDHC2_PODF_4 + divide by 5 + 0x4 + + + USDHC2_PODF_5 + divide by 6 + 0x5 + + + USDHC2_PODF_6 + divide by 7 + 0x6 + + + USDHC2_PODF_7 + divide by 8 + 0x7 + + + + + BCH_PODF + Divider for bch clock podf. Divider should be updated when output clock is gated. + 0x13 + 3 + read-write + + + BCH_PODF_0 + divide by 1 + 0 + + + BCH_PODF_1 + divide by 2 + 0x1 + + + BCH_PODF_2 + divide by 3 + 0x2 + + + BCH_PODF_3 + divide by 4 + 0x3 + + + BCH_PODF_4 + divide by 5 + 0x4 + + + BCH_PODF_5 + divide by 6 + 0x5 + + + BCH_PODF_6 + divide by 7 + 0x6 + + + BCH_PODF_7 + divide by 8 + 0x7 + + + + + GPMI_PODF + Divider for gpmi clock pred. Divider should be updated when output clock is gated. + 0x16 + 3 + read-write + + + GPMI_PODF_0 + divide by 1 + 0 + + + GPMI_PODF_1 + divide by 2 + 0x1 + + + GPMI_PODF_2 + divide by 3 + 0x2 + + + GPMI_PODF_3 + divide by 4 + 0x3 + + + GPMI_PODF_4 + divide by 5 + 0x4 + + + GPMI_PODF_5 + divide by 6 + 0x5 + + + GPMI_PODF_6 + divide by 7 + 0x6 + + + GPMI_PODF_7 + divide by 8 + 0x7 + + + + + + + CS1CDR + CCM SAI1 Clock Divider Register + 0x28 + 32 + read-write + 0xEC102C1 + 0xFFFFFFFF + + + SAI1_CLK_PODF + Divider for sai1 clock podf + 0 + 6 + read-write + + + SAI1_CLK_PODF_0 + divide by 1 + 0 + + + SAI1_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + SAI1_CLK_PRED + Divider for sai1 clock pred. + 0x6 + 3 + read-write + + + SAI1_CLK_PRED_0 + divide by 1 + 0 + + + SAI1_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI1_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI1_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI1_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI1_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI1_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI1_CLK_PRED_7 + divide by 8 + 0x7 + + + + + ESAI_CLK_PRED + Divider for ESAI clock pred + 0x9 + 3 + read-write + + + ESAI_CLK_PRED_0 + Divide by 1 + 0 + + + ESAI_CLK_PRED_1 + Divide by 2 + 0x1 + + + ESAI_CLK_PRED_2 + Divide by 3 + 0x2 + + + ESAI_CLK_PRED_3 + Divide by 4 + 0x3 + + + ESAI_CLK_PRED_4 + Divide by 5 + 0x4 + + + ESAI_CLK_PRED_5 + Divide by 6 + 0x5 + + + ESAI_CLK_PRED_6 + Divide by 7 + 0x6 + + + ESAI_CLK_PRED_7 + Divide by 8 + 0x7 + + + + + SAI3_CLK_PODF + Divider for sai3 clock podf + 0x10 + 6 + read-write + + + SAI3_CLK_PODF_0 + divide by 1 + 0 + + + SAI3_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + SAI3_CLK_PRED + Divider for sai3 clock pred. + 0x16 + 3 + read-write + + + SAI3_CLK_PRED_0 + divide by 1 + 0 + + + SAI3_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI3_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI3_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI3_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI3_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI3_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI3_CLK_PRED_7 + divide by 8 + 0x7 + + + + + ESAI_CLK_PODF + Divider for ESAI clock + 0x19 + 3 + read-write + + + ESAI_CLK_PODF_0 + Divide by 1 + 0 + + + ESAI_CLK_PODF_1 + Divide by 2 + 0x1 + + + ESAI_CLK_PODF_2 + Divide by 3 + 0x2 + + + ESAI_CLK_PODF_3 + Divide by 4 + 0x3 + + + ESAI_CLK_PODF_4 + Divide by 5 + 0x4 + + + ESAI_CLK_PODF_5 + Divide by 6 + 0x5 + + + ESAI_CLK_PODF_6 + Divide by 7 + 0x6 + + + ESAI_CLK_PODF_7 + Divide by 8 + 0x7 + + + + + + + CS2CDR + CCM SAI2 Clock Divider Register + 0x2C + 32 + read-write + 0x336C1 + 0xFFFFFFFF + + + SAI2_CLK_PODF + Divider for sai2 clock podf + 0 + 6 + read-write + + + SAI2_CLK_PODF_0 + divide by 1 + 0 + + + SAI2_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + SAI2_CLK_PRED + Divider for sai2 clock pred.Divider should be updated when output clock is gated. + 0x6 + 3 + read-write + + + SAI2_CLK_PRED_0 + divide by 1 + 0 + + + SAI2_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI2_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI2_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI2_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI2_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI2_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI2_CLK_PRED_7 + divide by 8 + 0x7 + + + + + LDB_DI0_CLK_SEL + Selector for ldb_di0 clock multiplexerMultiplexor should be updated when both input and output clocks are gated + 0x9 + 3 + read-write + + + LDB_DI0_CLK_SEL_0 + PLL5 clock + 0 + + + LDB_DI0_CLK_SEL_1 + PLL2 PFD0 + 0x1 + + + LDB_DI0_CLK_SEL_2 + PLL2 PFD2 + 0x2 + + + LDB_DI0_CLK_SEL_3 + PLL2 PFD3 + 0x3 + + + LDB_DI0_CLK_SEL_4 + PLL2 PFD1 + 0x4 + + + LDB_DI0_CLK_SEL_5 + PLL3 PFD3 + 0x5 + + + + + ENFC_CLK_SEL + Selector for enfc clock multiplexer Multiplexor should be updated when output clock is gated. + 0xF + 3 + read-write + + + ENFC_CLK_SEL_0 + derive clock from PLL2 PFD0 + 0 + + + ENFC_CLK_SEL_1 + derive clock from PLL2 + 0x1 + + + ENFC_CLK_SEL_2 + derive clock from pll3_sw_clk + 0x2 + + + ENFC_CLK_SEL_3 + derive clock from PLL2 PFD2 + 0x3 + + + ENFC_CLK_SEL_4 + derive clock from PLL3 PFD3 + 0x4 + + + + + ENFC_CLK_PRED + Divider for enfc clock pred divider.Divider should be updated when output clock is gated. + 0x12 + 3 + read-write + + + ENFC_CLK_PRED_0 + divide by 1 + 0 + + + ENFC_CLK_PRED_1 + divide by 2 + 0x1 + + + ENFC_CLK_PRED_2 + divide by 3 + 0x2 + + + ENFC_CLK_PRED_3 + divide by 4 + 0x3 + + + ENFC_CLK_PRED_4 + divide by 5 + 0x4 + + + ENFC_CLK_PRED_5 + divide by 6 + 0x5 + + + ENFC_CLK_PRED_6 + divide by 7 + 0x6 + + + ENFC_CLK_PRED_7 + divide by 8 + 0x7 + + + + + ENFC_CLK_PODF + Divider for enfc clock divider. + 0x15 + 6 + read-write + + + ENFC_CLK_PODF_0 + divide by 1 + 0 + + + ENFC_CLK_PODF_1 + divide by 2 + 0x1 + + + ENFC_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + + + CDCDR + CCM D1 Clock Divider Register + 0x30 + 32 + read-write + 0x33F71F92 + 0xFFFFFFFF + + + SPDIF0_CLK_SEL + Selector for spdif0 clock multiplexer + 0x14 + 2 + read-write + + + SPDIF0_CLK_SEL_0 + derive clock from PLL4 + 0 + + + SPDIF0_CLK_SEL_1 + derive clock from PLL3 PFD2 + 0x1 + + + SPDIF0_CLK_SEL_2 + derive clock from PLL5 + 0x2 + + + SPDIF0_CLK_SEL_3 + derive clock from pll3_sw_clk + 0x3 + + + + + SPDIF0_CLK_PODF + Divider for spdif0 clock podf. Divider should be updated when output clock is gated. + 0x16 + 3 + read-write + + + SPDIF0_CLK_PODF_0 + divide by 1 + 0 + + + SPDIF0_CLK_PODF_7 + divide by 8 + 0x7 + + + + + SPDIF0_CLK_PRED + Divider for spdif0 clock pred. Divider should be updated when output clock is gated. + 0x19 + 3 + read-write + + + SPDIF0_CLK_PRED_0 + divide by 1 (do not use with high input frequencies) + 0 + + + SPDIF0_CLK_PRED_1 + divide by 2 + 0x1 + + + SPDIF0_CLK_PRED_2 + divide by 3 + 0x2 + + + SPDIF0_CLK_PRED_7 + divide by 8 + 0x7 + + + + + + + CHSCCDR + CCM HSC Clock Divider Register + 0x34 + 32 + read-write + 0x29148 + 0xFFFFFFFF + + + EPDC_CLK_SEL + Selector for EPDC root clock multiplexer + 0x9 + 3 + read-write + + + EPDC_CLK_SEL_0 + Derive clock from divided pre-muxed EPDC clock + 0 + + + EPDC_CLK_SEL_1 + Derive clock from ipp_di0_clk + 0x1 + + + EPDC_CLK_SEL_2 + Derive clock from ipp_di1_clk + 0x2 + + + EPDC_CLK_SEL_3 + Derive clock from ldb_di0_clk + 0x3 + + + EPDC_CLK_SEL_4 + Derive clock from ldb_di1_clk + 0x4 + + + + + EPDC_PODF + Divider for EPDC clock divider. Divider should be updated when output clock is gated. + 0xC + 3 + read-write + + + EPDC_PODF_0 + Divide by 1 + 0 + + + EPDC_PODF_1 + Divide by 2 + 0x1 + + + EPDC_PODF_2 + Divide by 3 + 0x2 + + + EPDC_PODF_3 + Divide by 4 + 0x3 + + + EPDC_PODF_4 + Divide by 5 + 0x4 + + + EPDC_PODF_5 + Divide by 6 + 0x5 + + + EPDC_PODF_6 + Divide by 7 + 0x6 + + + EPDC_PODF_7 + Divide by 8 + 0x7 + + + + + EPDC_PRE_CLK_SEL + Selector for EPDC root clock pre-multiplexer + 0xF + 3 + read-write + + + EPDC_PRE_CLK_SEL_0 + Derive clock from PLL2 + 0 + + + EPDC_PRE_CLK_SEL_1 + Derive clock from PLL3_SW_CLK + 0x1 + + + EPDC_PRE_CLK_SEL_2 + Derive clock from PLL5 + 0x2 + + + EPDC_PRE_CLK_SEL_3 + Derive clock from PLL2 PFD0 + 0x3 + + + EPDC_PRE_CLK_SEL_4 + Derive clock from PLL2 PFD2 + 0x4 + + + EPDC_PRE_CLK_SEL_5 + Derive clock from PLL3 PFD2 + 0x5 + + + + + + + CSCDR2 + CCM Serial Clock Divider Register 2 + 0x38 + 32 + read-write + 0x29B48 + 0xFFFFFFFF + + + LCDIF1_CLK_SEL + Selector for lcdif1 root clock multiplexer + 0x9 + 3 + read-write + + + LCDIF1_CLK_SEL_0 + derive clock from divided pre-muxed lcdif1 clock + 0 + + + LCDIF1_CLK_SEL_1 + derive clock from ipp_di0_clk + 0x1 + + + LCDIF1_CLK_SEL_2 + derive clock from ipp_di1_clk + 0x2 + + + LCDIF1_CLK_SEL_3 + derive clock from ldb_di0_clk + 0x3 + + + LCDIF1_CLK_SEL_4 + derive clock from ldb_di1_clk + 0x4 + + + + + LCDIF1_PRED + Pre-divider for lcdif1 clock. Divider should be updated when output clock is gated. + 0xC + 3 + read-write + + + LCDIF1_PRED_0 + divide by 1 + 0 + + + LCDIF1_PRED_1 + divide by 2 + 0x1 + + + LCDIF1_PRED_2 + divide by 3 + 0x2 + + + LCDIF1_PRED_3 + divide by 4 + 0x3 + + + LCDIF1_PRED_4 + divide by 5 + 0x4 + + + LCDIF1_PRED_5 + divide by 6 + 0x5 + + + LCDIF1_PRED_6 + divide by 7 + 0x6 + + + LCDIF1_PRED_7 + divide by 8 + 0x7 + + + + + LCDIF1_PRE_CLK_SEL + Selector for lcdif1 root clock pre-multiplexer + 0xF + 3 + read-write + + + LCDIF1_PRE_CLK_SEL_0 + derive clock from PLL2 + 0 + + + LCDIF1_PRE_CLK_SEL_1 + derive clock from PLL3 PFD3 + 0x1 + + + LCDIF1_PRE_CLK_SEL_2 + derive clock from PLL5 + 0x2 + + + LCDIF1_PRE_CLK_SEL_3 + derive clock from PLL2 PFD0 + 0x3 + + + LCDIF1_PRE_CLK_SEL_4 + derive clock from PLL2 PFD1 + 0x4 + + + LCDIF1_PRE_CLK_SEL_5 + derive clock from PLL3 PFD1 + 0x5 + + + + + ECSPI_CLK_SEL + Selector for the ECSPI clock multiplexor + 0x12 + 1 + read-write + + + ECSPI_CLK_SEL_0 + derive clock from pll3_60m + 0 + + + ECSPI_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + ECSPI_CLK_PODF + Divider for ecspi clock podf + 0x13 + 6 + read-write + + + ECSPI_CLK_PODF_0 + divide by 1 + 0 + + + ECSPI_CLK_PODF_63 + divide by 2^6 + 0x3F + + + + + + + CSCDR3 + CCM Serial Clock Divider Register 3 + 0x3C + 32 + read-write + 0x14841 + 0xFFFFFFFF + + + CSI_CLK_SEL + Selector for csi clock multiplexer + 0x9 + 2 + read-write + + + CSI_CLK_SEL_0 + derive clock from osc_clk (24M) + 0 + + + CSI_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + CSI_CLK_SEL_2 + derive clock from pll3_120M + 0x2 + + + CSI_CLK_SEL_3 + derive clock from PLL3 PFD1 + 0x3 + + + + + CSI_PODF + Post divider for csi_core clock. Divider should be updated when output clock is gated. + 0xB + 3 + read-write + + + CSI_PODF_0 + divide by 1 + 0 + + + CSI_PODF_1 + divide by 2 + 0x1 + + + CSI_PODF_2 + divide by 3 + 0x2 + + + CSI_PODF_3 + divide by 4 + 0x3 + + + CSI_PODF_4 + divide by 5 + 0x4 + + + CSI_PODF_5 + divide by 6 + 0x5 + + + CSI_PODF_6 + divide by 7 + 0x6 + + + CSI_PODF_7 + divide by 8 + 0x7 + + + + + + + CWDR + CCM Wakeup Detector Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + CDHIPR + CCM Divider Handshake In-Process Register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + AXI_PODF_BUSY + Busy indicator for axi_podf. + 0 + 1 + read-only + + + AXI_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + AXI_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the axi_podf will be applied. + 0x1 + + + + + AHB_PODF_BUSY + Busy indicator for ahb_podf. + 0x1 + 1 + read-only + + + AHB_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + AHB_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied. + 0x1 + + + + + MMDC_PODF_BUSY + Busy indicator for mmdc_axi_podf. + 0x2 + 1 + read-only + + + MMDC_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + MMDC_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the mmdc_axi_podf will be applied. + 0x1 + + + + + PERIPH2_CLK_SEL_BUSY + Busy indicator for periph2_clk_sel mux control. + 0x3 + 1 + read-only + + + PERIPH2_CLK_SEL_BUSY_0 + mux is not busy and its value represents the actual division. + 0 + + + PERIPH2_CLK_SEL_BUSY_1 + mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied. + 0x1 + + + + + PERIPH_CLK_SEL_BUSY + Busy indicator for periph_clk_sel mux control. + 0x5 + 1 + read-only + + + PERIPH_CLK_SEL_BUSY_0 + mux is not busy and its value represents the actual division. + 0 + + + PERIPH_CLK_SEL_BUSY_1 + mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied. + 0x1 + + + + + ARM_PODF_BUSY + Busy indicator for arm_podf. + 0x10 + 1 + read-only + + + ARM_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + ARM_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied. + 0x1 + + + + + + + CLPCR + CCM Low Power Control Register + 0x54 + 32 + read-write + 0x79 + 0xFFFFFFFF + + + LPM + Setting the low power mode that system will enter on next assertion of dsm_request signal. + 0 + 2 + read-write + + + LPM_0 + Remain in run mode + 0 + + + LPM_1 + Transfer to wait mode + 0x1 + + + LPM_2 + Transfer to stop mode + 0x2 + + + + + ARM_CLK_DIS_ON_LPM + Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode + 0x5 + 1 + read-write + + + ARM_CLK_DIS_ON_LPM_0 + ARM clock enabled on wait mode. + 0 + + + ARM_CLK_DIS_ON_LPM_1 + ARM clock disabled on wait mode. . + 0x1 + + + + + SBYOS + Standby clock oscillator bit + 0x6 + 1 + read-write + + + SBYOS_0 + On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0') + 0 + + + SBYOS_1 + On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process. + 0x1 + + + + + DIS_REF_OSC + dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i + 0x7 + 1 + read-write + + + DIS_REF_OSC_0 + external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. + 0 + + + DIS_REF_OSC_1 + external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' + 0x1 + + + + + VSTBY + Voltage standby request bit + 0x8 + 1 + read-write + + + VSTBY_0 + Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') + 0 + + + VSTBY_1 + Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1'). + 0x1 + + + + + STBY_COUNT + Standby counter definition + 0x9 + 2 + read-write + + + STBY_COUNT_0 + CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles + 0 + + + STBY_COUNT_1 + CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles + 0x1 + + + STBY_COUNT_2 + CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles + 0x2 + + + STBY_COUNT_3 + CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles + 0x3 + + + + + COSC_PWRDOWN + In run mode, software can manually control powering down of on chip oscillator, i + 0xB + 1 + read-write + + + COSC_PWRDOWN_0 + On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. + 0 + + + COSC_PWRDOWN_1 + On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. + 0x1 + + + + + BYPASS_MMDC_LPM_HS + Bypass handshake with mmdc on next entrance to low power mode (STOP or WAIT) + 0x15 + 1 + read-write + + + BYPASS_MMDC_LPM_HS_0 + handshake with mmdc on next entrance to low power mode will be performed. . + 0 + + + BYPASS_MMDC_LPM_HS_1 + handshake with mmdc on next entrance to low power mode will be bypassed. + 0x1 + + + + + MASK_CORE0_WFI + Mask WFI of core0 for entering low power mode Assertion of all bits[27:22] will generate low power mode request + 0x16 + 1 + read-write + + + MASK_CORE0_WFI_0 + WFI of core0 is not masked + 0 + + + MASK_CORE0_WFI_1 + WFI of core0 is masked + 0x1 + + + + + MASK_SCU_IDLE + Mask SCU IDLE for entering low power mode Assertion of all bits[27:22] will generate low power mode request + 0x1A + 1 + read-write + + + MASK_SCU_IDLE_0 + SCU IDLE is not masked + 0 + + + MASK_SCU_IDLE_1 + SCU IDLE is masked + 0x1 + + + + + MASK_L2CC_IDLE + Mask L2CC IDLE for entering low power mode + 0x1B + 1 + read-write + + + MASK_L2CC_IDLE_0 + L2CC IDLE is not masked + 0 + + + MASK_L2CC_IDLE_1 + L2CC IDLE is masked + 0x1 + + + + + + + CISR + CCM Interrupt Status Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LRF_PLL + CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs + 0 + 1 + read-write + oneToClear + + + LRF_PLL_0 + interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs + 0 + + + LRF_PLL_1 + interrupt generated due to lock ready of all enabled and not bypaseed PLLs + 0x1 + + + + + COSC_READY + CCM interrupt request 2 generated due to on board oscillator ready, i + 0x6 + 1 + read-write + oneToClear + + + COSC_READY_0 + interrupt is not generated due to on board oscillator ready + 0 + + + COSC_READY_1 + interrupt generated due to on board oscillator ready + 0x1 + + + + + AXI_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of axi_podf + 0x11 + 1 + read-write + oneToClear + + + AXI_PODF_LOADED_0 + interrupt is not generated due to frequency change of axi_podf + 0 + + + AXI_PODF_LOADED_1 + interrupt generated due to frequency change of axi_podf + 0x1 + + + + + PERIPH2_CLK_SEL_LOADED + CCM interrupt request 1 generated due to frequency change of periph2_clk_sel + 0x13 + 1 + read-write + oneToClear + + + PERIPH2_CLK_SEL_LOADED_0 + interrupt is not generated due to frequency change of periph2_clk_sel + 0 + + + PERIPH2_CLK_SEL_LOADED_1 + interrupt generated due to frequency change of periph2_clk_sel + 0x1 + + + + + AHB_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of ahb_podf + 0x14 + 1 + read-write + oneToClear + + + AHB_PODF_LOADED_0 + interrupt is not generated due to frequency change of ahb_podf + 0 + + + AHB_PODF_LOADED_1 + interrupt generated due to frequency change of ahb_podf + 0x1 + + + + + MMDC_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of mmdc_podf_ loaded + 0x15 + 1 + read-write + oneToClear + + + MMDC_PODF_LOADED_0 + interrupt is not generated due to frequency change of mmdc_podf_ loaded + 0 + + + MMDC_PODF_LOADED_1 + interrupt generated due to frequency change of mmdc_podf_ loaded + 0x1 + + + + + PERIPH_CLK_SEL_LOADED + CCM interrupt request 1 generated due to update of periph_clk_sel. + 0x16 + 1 + read-write + oneToClear + + + PERIPH_CLK_SEL_LOADED_0 + interrupt is not generated due to update of periph_clk_sel. + 0 + + + PERIPH_CLK_SEL_LOADED_1 + interrupt generated due to update of periph_clk_sel. + 0x1 + + + + + ARM_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of arm_podf + 0x1A + 1 + read-write + oneToClear + + + ARM_PODF_LOADED_0 + interrupt is not generated due to frequency change of arm_podf + 0 + + + ARM_PODF_LOADED_1 + interrupt generated due to frequency change of arm_podf + 0x1 + + + + + + + CIMR + CCM Interrupt Mask Register + 0x5C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MASK_LRF_PLL + mask interrupt generation due to lrf of PLLs + 0 + 1 + read-write + + + MASK_LRF_PLL_0 + don't mask interrupt due to lrf of PLLs - interrupt will be created + 0 + + + MASK_LRF_PLL_1 + mask interrupt due to lrf of PLLs + 0x1 + + + + + MASK_COSC_READY + mask interrupt generation due to on board oscillator ready + 0x6 + 1 + read-write + + + MASK_COSC_READY_0 + don't mask interrupt due to on board oscillator ready - interrupt will be created + 0 + + + MASK_COSC_READY_1 + mask interrupt due to on board oscillator ready + 0x1 + + + + + MASK_AXI_PODF_LOADED + mask interrupt generation due to frequency change of axi_podf + 0x11 + 1 + read-write + + + MASK_AXI_PODF_LOADED_0 + don't mask interrupt due to frequency change of axi_podf - interrupt will be created + 0 + + + MASK_AXI_PODF_LOADED_1 + mask interrupt due to frequency change of axi_podf + 0x1 + + + + + MASK_PERIPH2_CLK_SEL_LOADED + mask interrupt generation due to update of periph2_clk_sel. + 0x13 + 1 + read-write + + + MASK_PERIPH2_CLK_SEL_LOADED_0 + don't mask interrupt due to update of periph2_clk_sel - interrupt will be created + 0 + + + MASK_PERIPH2_CLK_SEL_LOADED_1 + mask interrupt due to update of periph2_clk_sel + 0x1 + + + + + MASK_AHB_PODF_LOADED + mask interrupt generation due to frequency change of ahb_podf + 0x14 + 1 + read-write + + + MASK_AHB_PODF_LOADED_0 + don't mask interrupt due to frequency change of ahb_podf - interrupt will be created + 0 + + + MASK_AHB_PODF_LOADED_1 + mask interrupt due to frequency change of ahb_podf + 0x1 + + + + + MASK_MMDC_PODF_LOADED + mask interrupt generation due to update of mask_mmdc_podf + 0x15 + 1 + read-write + + + MASK_MMDC_PODF_LOADED_0 + don't mask interrupt due to update of mask_mmdc_podf - interrupt will be created + 0 + + + MASK_MMDC_PODF_LOADED_1 + mask interrupt due to update of mask_mmdc_podf + 0x1 + + + + + MASK_PERIPH_CLK_SEL_LOADED + mask interrupt generation due to update of periph_clk_sel. + 0x16 + 1 + read-write + + + MASK_PERIPH_CLK_SEL_LOADED_0 + don't mask interrupt due to update of periph_clk_sel - interrupt will be created + 0 + + + MASK_PERIPH_CLK_SEL_LOADED_1 + mask interrupt due to update of periph_clk_sel + 0x1 + + + + + ARM_PODF_LOADED + mask interrupt generation due to frequency change of arm_podf + 0x1A + 1 + read-write + + + ARM_PODF_LOADED_0 + don't mask interrupt due to frequency change of arm_podf - interrupt will be created + 0 + + + ARM_PODF_LOADED_1 + mask interrupt due to frequency change of arm_podf + 0x1 + + + + + + + CCOSR + CCM Clock Output Source Register + 0x60 + 32 + read-write + 0xA0001 + 0xFFFFFFFF + + + CLKO_SEL + Selection of the clock to be generated on CCM_CLKO1 + 0 + 4 + read-write + + + CLKO_SEL_5 + axi_clk_root + 0x5 + + + CLKO_SEL_6 + enfc_clk_root + 0x6 + + + CLKO_SEL_7 + no description available + 0x7 + + + CLKO_SEL_8 + epdc_clk_root + 0x8 + + + CLKO_SEL_9 + no description available + 0x9 + + + CLKO_SEL_10 + lcdif_pix_clk_root + 0xA + + + CLKO_SEL_11 + ahb_clk_root + 0xB + + + CLKO_SEL_12 + ipg_clk_root + 0xC + + + CLKO_SEL_13 + perclk_root + 0xD + + + CLKO_SEL_14 + ckil_sync_clk_root + 0xE + + + CLKO_SEL_15 + pll4_main_clk + 0xF + + + + + CLKO1_DIV + Setting the divider of CCM_CLKO1 + 0x4 + 3 + read-write + + + CLKO1_DIV_0 + divide by 1 + 0 + + + CLKO1_DIV_1 + divide by 2 + 0x1 + + + CLKO1_DIV_2 + divide by 3 + 0x2 + + + CLKO1_DIV_3 + divide by 4 + 0x3 + + + CLKO1_DIV_4 + divide by 5 + 0x4 + + + CLKO1_DIV_5 + divide by 6 + 0x5 + + + CLKO1_DIV_6 + divide by 7 + 0x6 + + + CLKO1_DIV_7 + divide by 8 + 0x7 + + + + + CLKO1_EN + Enable of CCM_CLKO1 clock + 0x7 + 1 + read-write + + + CLKO1_EN_0 + CCM_CLKO1 disabled. + 0 + + + CLKO1_EN_1 + CCM_CLKO1 enabled. + 0x1 + + + + + CLK_OUT_SEL + CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks + 0x8 + 1 + read-write + + + CLK_OUT_SEL_0 + CCM_CLKO1 output drives CCM_CLKO1 clock + 0 + + + CLK_OUT_SEL_1 + CCM_CLKO1 output drives CCM_CLKO2 clock + 0x1 + + + + + CLKO2_SEL + Selection of the clock to be generated on CCM_CLKO2 + 0x10 + 5 + read-write + + + CLKO2_SEL_1 + mmdc_clk_root + 0x1 + + + CLKO2_SEL_2 + gpmi_clk_root + 0x2 + + + CLKO2_SEL_3 + usdhc1_clk_root + 0x3 + + + CLKO2_SEL_5 + wrck_clk_root + 0x5 + + + CLKO2_SEL_6 + ecspi_clk_root + 0x6 + + + CLKO2_SEL_8 + bch_clk_root + 0x8 + + + CLKO2_SEL_10 + arm_clk_root + 0xA + + + CLKO2_SEL_11 + csi_core + 0xB + + + CLKO2_SEL_14 + osc_clk + 0xE + + + CLKO2_SEL_17 + usdhc2_clk_root + 0x11 + + + CLKO2_SEL_18 + sai1_clk_root + 0x12 + + + CLKO2_SEL_19 + sai2_clk_root + 0x13 + + + CLKO2_SEL_20 + sai3_clk_root + 0x14 + + + CLKO2_SEL_23 + can_clk_root + 0x17 + + + CLKO2_SEL_25 + qspi1_clk_root + 0x19 + + + CLKO2_SEL_27 + aclk_eim_slow_clk_root + 0x1B + + + CLKO2_SEL_28 + uart_clk_root + 0x1C + + + CLKO2_SEL_29 + spdif0_clk_root + 0x1D + + + + + CLKO2_DIV + Setting the divider of CCM_CLKO2 + 0x15 + 3 + read-write + + + CLKO2_DIV_0 + divide by 1 + 0 + + + CLKO2_DIV_1 + divide by 2 + 0x1 + + + CLKO2_DIV_2 + divide by 3 + 0x2 + + + CLKO2_DIV_3 + divide by 4 + 0x3 + + + CLKO2_DIV_4 + divide by 5 + 0x4 + + + CLKO2_DIV_5 + divide by 6 + 0x5 + + + CLKO2_DIV_6 + divide by 7 + 0x6 + + + CLKO2_DIV_7 + divide by 8 + 0x7 + + + + + CLKO2_EN + Enable of CCM_CLKO2 clock + 0x18 + 1 + read-write + + + CLKO2_EN_0 + CCM_CLKO2 disabled. + 0 + + + CLKO2_EN_1 + CCM_CLKO2 enabled. + 0x1 + + + + + + + CGPR + CCM General Purpose Register + 0x64 + 32 + read-write + 0xFE62 + 0xFFFFFFFF + + + PMIC_DELAY_SCALER + Defines clock dividion of clock for stby_count (pmic delay counter) + 0 + 1 + read-write + + + PMIC_DELAY_SCALER_0 + clock is not divided + 0 + + + PMIC_DELAY_SCALER_1 + clock is divided /8 + 0x1 + + + + + MMDC_EXT_CLK_DIS + Disable external clock driver of MMDC during STOP mode + 0x2 + 1 + read-write + + + MMDC_EXT_CLK_DIS_0 + don't disable during stop mode. + 0 + + + MMDC_EXT_CLK_DIS_1 + disable during stop mode + 0x1 + + + + + EFUSE_PROG_SUPPLY_GATE + Defines the value of the output signal cgpr_dout[4]. Gate of program supply for efuse programing + 0x4 + 1 + read-write + + + EFUSE_PROG_SUPPLY_GATE_0 + fuse programing supply voltage is gated off to the efuse module + 0 + + + EFUSE_PROG_SUPPLY_GATE_1 + allow fuse programing. + 0x1 + + + + + SYS_MEM_DS_CTRL + System memory DS control + 0xE + 2 + read-write + + + SYS_MEM_DS_CTRL_0 + Disable memory DS mode always + 0 + + + SYS_MEM_DS_CTRL_1 + Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled + 0x1 + + + + + FPL + Fast PLL enable. + 0x10 + 1 + read-write + + + FPL_0 + Engage PLL enable default way. + 0 + + + FPL_1 + Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. + 0x1 + + + + + INT_MEM_CLK_LPM + Control for the Deep Sleep signal to the ARM Platform memories with additional control logic based on the ARM WFI signal + 0x11 + 1 + read-write + + + INT_MEM_CLK_LPM_0 + Disable the clock to the ARM platform memories when entering Low Power Mode + 0 + + + INT_MEM_CLK_LPM_1 + Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating) + 0x1 + + + + + + + CCGR0 + CCM Clock Gating Register 0 + 0x68 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + aips_tz1 clocks (aips_tz1_clk_enable) + 0 + 2 + read-write + + + CG1 + aips_tz2 clocks (aips_tz2_clk_enable) + 0x2 + 2 + read-write + + + CG2 + apbhdma hclk clock (apbhdma_hclk_enable) + 0x4 + 2 + read-write + + + CG3 + asrc clock (asrc_clk_enable) + 0x6 + 2 + read-write + + + CG4 + Reserved + 0x8 + 2 + read-write + + + CG5 + dcp clock (dcp_clk_enable) + 0xA + 2 + read-write + + + CG6 + enet clock (enet_clk_enable) + 0xC + 2 + read-write + + + CG7 + can1 clock (can1_clk_enable) + 0xE + 2 + read-write + + + CG8 + can1_serial clock (can1_serial_clk_enable) + 0x10 + 2 + read-write + + + CG9 + can2 clock (can2_clk_enable) + 0x12 + 2 + read-write + + + CG10 + can2_serial clock (can2_serial_clk_enable) + 0x14 + 2 + read-write + + + CG11 + CPU debug clocks (arm_dbg_clk_enable) + 0x16 + 2 + read-write + + + CG12 + dcic1 clocks (dcic1_clk_enable) gpt2 bus clocks (gpt2_bus_clk_enable) + 0x18 + 2 + read-write + + + CG13 + gpt2 serial clocks (gpt2_serial_clk_enable) + 0x1A + 2 + read-write + + + CG14 + uart2 clock (uart2_clk_enable) + 0x1C + 2 + read-write + + + CG15 + gpio2_clocks (gpio2_clk_enable) + 0x1E + 2 + read-write + + + + + CCGR1 + CCM Clock Gating Register 1 + 0x6C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + ecspi1 clocks (ecspi1_clk_enable) + 0 + 2 + read-write + + + CG1 + ecspi2 clocks (ecspi2_clk_enable) + 0x2 + 2 + read-write + + + CG2 + ecspi3 clocks (ecspi3_clk_enable) + 0x4 + 2 + read-write + + + CG3 + ecspi4 clocks (ecspi4_clk_enable) + 0x6 + 2 + read-write + + + CG4 + adc2 clock (adc2_clk_enable) + 0x8 + 2 + read-write + + + CG5 + uart3 clock (uart3_clk_enable) + 0xA + 2 + read-write + + + CG6 + epit1 clocks (epit1_clk_enable) + 0xC + 2 + read-write + + + CG7 + epit2 clocks (epit2_clk_enable) + 0xE + 2 + read-write + + + CG8 + adc1 clock (adc1_clk_enable) + 0x10 + 2 + read-write + + + CG9 + sim_s clock (sim_s_clk_enable) + 0x12 + 2 + read-write + + + CG10 + gpt bus clock (gpt_clk_enable) + 0x14 + 2 + read-write + + + CG11 + gpt serial clock (gpt_serial_clk_enable) + 0x16 + 2 + read-write + + + CG12 + uart4 clock (uart4_clk_enable) + 0x18 + 2 + read-write + + + CG13 + gpio1 clock (gpio1_clk_enable) + 0x1A + 2 + read-write + + + CG14 + csu clock (csu_clk_enable) + 0x1C + 2 + read-write + + + CG15 + gpio5 clock (gpio5_clk_enable) + 0x1E + 2 + read-write + + + + + CCGR2 + CCM Clock Gating Register 2 + 0x70 + 32 + read-write + 0xFC3FFFFF + 0xFFFFFFFF + + + CG0 + esai clock (esai_clk_enable) + 0 + 2 + read-write + + + CG1 + csi clock (csi_clk_enable) + 0x2 + 2 + read-write + + + CG2 + iomuxc_snvs clock (iomuxc_snvs_clk_enable) + 0x4 + 2 + read-write + + + CG3 + i2c1_serial clock (i2c1_serial_clk_enable) + 0x6 + 2 + read-write + + + CG4 + i2c2_serial clock (i2c2_serial_clk_enable) + 0x8 + 2 + read-write + + + CG5 + i2c3_serial clock (i2c3_serial_clk_enable) + 0xA + 2 + read-write + + + CG6 + OCOTP_CTRL clock (iim_clk_enable) + 0xC + 2 + read-write + + + CG7 + iomux_ipt_clk_io clock (iomux_ipt_clk_io_enable) + 0xE + 2 + read-write + + + CG8 + ipmux1 clock (ipmux1_clk_enable) + 0x10 + 2 + read-write + + + CG9 + ipmux2 clock (ipmux2_clk_enable) + 0x12 + 2 + read-write + + + CG10 + ipmux3 clock (ipmux3_clk_enable) + 0x14 + 2 + read-write + + + CG11 + ipsync_ip2apb_tzasc1_ipg clocks (ipsync_ip2apb_tzasc1_ipg_master_clk_enable) + 0x16 + 2 + read-write + + + CG12 + Reserved + 0x18 + 2 + read-write + + + CG13 + gpio3 clock (gpio3_clk_enable) + 0x1A + 2 + read-write + + + CG14 + lcd clocks (lcd_clk_enable) + 0x1C + 2 + read-write + + + CG15 + pxp clocks (pxp_clk_enable) + 0x1E + 2 + read-write + + + + + CCGR3 + CCM Clock Gating Register 3 + 0x74 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + Reserved + 0 + 2 + read-write + + + CG1 + uart5 clock (uart5_clk_enable) + 0x2 + 2 + read-write + + + CG2 + epdc clock (epdc_clk_enable) + 0x4 + 2 + read-write + + + CG3 + uart6 clock (uart6_clk_enable) + 0x6 + 2 + read-write + + + CG4 + CA7 CCM DAP clock (ccm_dap_clk_enable) + 0x8 + 2 + read-write + + + CG5 + lcdif1 pix clock (lcdif1_pix_clk_enable) + 0xA + 2 + read-write + + + CG6 + gpio4 clock (gpio4_clk_enable) + 0xC + 2 + read-write + + + CG7 + qspi1 clock (qspi1_clk_enable) + 0xE + 2 + read-write + + + CG8 + wdog1 clock (wdog1_clk_enable) + 0x10 + 2 + read-write + + + CG9 + a7 clkdiv patch clock (a7_clkdiv_patch_clk_enable) + 0x12 + 2 + read-write + + + CG10 + mmdc_core_aclk_fast_core_p0 clock (mmdc_core_aclk_fast_core_p0_enable) + 0x14 + 2 + read-write + + + CG11 + Reserved + 0x16 + 2 + read-write + + + CG12 + mmdc_core_ipg_clk_p0 clock (mmdc_core_ipg_clk_p0_enable) + 0x18 + 2 + read-write + + + CG13 + mmdc_core_ipg_clk_p1 clock (mmdc_core_ipg_clk_p1_enable) + 0x1A + 2 + read-write + + + CG14 + axi clock (axi_clk_enable) + 0x1C + 2 + read-write + + + CG15 + iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable) + 0x1E + 2 + read-write + + + + + CCGR4 + CCM Clock Gating Register 4 + 0x78 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + Reserved + 0 + 2 + read-write + + + CG1 + iomuxc clock (iomuxc_clk_enable) + 0x2 + 2 + read-write + + + CG2 + iomuxc gpr clock (iomuxc_gpr_clk_enable) + 0x4 + 2 + read-write + + + CG3 + sim_cpu clock (sim_cpu_clk_enable) + 0x6 + 2 + read-write + + + CG4 + cxapbsyncbridge slave clock (cxapbsyncbridge_slave_clk_enable) + 0x8 + 2 + read-write + + + CG5 + tsc_dig clock (tsc_clk_enable) + 0xA + 2 + read-write + + + CG6 + pl301_mx6qper1_bch clocks (pl301_mx6qper1_bchclk_enable) This gates bch_clk_root to sim_m fabric. + 0xC + 2 + read-write + + + CG7 + pl301_mx6qper2_mainclk_enable (pl301_mx6qper2_mainclk_enable) + 0xE + 2 + read-write + + + CG8 + pwm1 clocks (pwm1_clk_enable) + 0x10 + 2 + read-write + + + CG9 + pwm2 clocks (pwm2_clk_enable) + 0x12 + 2 + read-write + + + CG10 + pwm3 clocks (pwm3_clk_enable) + 0x14 + 2 + read-write + + + CG11 + pwm4 clocks (pwm4_clk_enable) + 0x16 + 2 + read-write + + + CG12 + rawnand_u_bch_input_apb clock (rawnand_u_bch_input_apb_clk_enable) + 0x18 + 2 + read-write + + + CG13 + rawnand_u_gpmi_bch_input_bch clock (rawnand_u_gpmi_bch_input_bch_clk_enable) + 0x1A + 2 + read-write + + + CG14 + rawnand_u_gpmi_bch_input_gpmi_io clock (rawnand_u_gpmi_bch_input_gpmi_io_clk_enable) + 0x1C + 2 + read-write + + + CG15 + rawnand_u_gpmi_input_apb clock (rawnand_u_gpmi_input_apb_clk_enable) + 0x1E + 2 + read-write + + + + + CCGR5 + CCM Clock Gating Register 5 + 0x7C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + rom clock (rom_clk_enable) + 0 + 2 + read-write + + + CG1 + stcr clock (stcr_clk_enable) + 0x2 + 2 + read-write + + + CG2 + snvs dryice clock (snvs_dryice_clk_enable) + 0x4 + 2 + read-write + + + CG3 + sdma clock (sdma_clk_enable) + 0x6 + 2 + read-write + + + CG4 + kpp clock (kpp_clk_enable) + 0x8 + 2 + read-write + + + CG5 + wdog2 clock (wdog2_clk_enable) + 0xA + 2 + read-write + + + CG6 + spba clock (spba_clk_enable) + 0xC + 2 + read-write + + + CG7 + spdif / audio clock (spdif_clk_enable, audio_clk_root) + 0xE + 2 + read-write + + + CG8 + sim_main clock (sim_main_clk_enable) + 0x10 + 2 + read-write + + + CG9 + snvs_hp clock (snvs_hp_clk_enable) + 0x12 + 2 + read-write + + + CG10 + snvs_lp clock (snvs_lp_clk_enable) + 0x14 + 2 + read-write + + + CG11 + sai3 clock (sai3_clk_enable) + 0x16 + 2 + read-write + + + CG12 + uart1 clock (uart1_clk_enable) + 0x18 + 2 + read-write + + + CG13 + uart7 clock (uart7_clk_enable) + 0x1A + 2 + read-write + + + CG14 + sai1 clock (sai1_clk_enable) + 0x1C + 2 + read-write + + + CG15 + sai2 clock (sai2_clk_enable) + 0x1E + 2 + read-write + + + + + CCGR6 + CCM Clock Gating Register 6 + 0x80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + usboh3 clock (usboh3_clk_enable) + 0 + 2 + read-write + + + CG1 + usdhc1 clocks (usdhc1_clk_enable) + 0x2 + 2 + read-write + + + CG2 + usdhc2 clocks (usdhc2_clk_enable) + 0x4 + 2 + read-write + + + CG3 + Reserved + 0x6 + 2 + read-write + + + CG4 + ipmux4 clock (ipmux4_clk_enable) + 0x8 + 2 + read-write + + + CG5 + eim_slow clocks (eim_slow_clk_enable) + 0xA + 2 + read-write + + + CG6 + Reserved + 0xC + 2 + read-write + + + CG7 + uart8 clocks (uart8_clk_enable) + 0xE + 2 + read-write + + + CG8 + pwm8 clocks (pwm8_clk_enable) + 0x10 + 2 + read-write + + + CG9 + aips_tz3 clock (aips_tz3_clk_enable) + 0x12 + 2 + read-write + + + CG10 + wdog3 clock (wdog3_clk_enable) + 0x14 + 2 + read-write + + + CG11 + anadig clocks (anadig_clk_enable) + 0x16 + 2 + read-write + + + CG12 + i2c4 serial clock (i2c4_serial_clk_enable) + 0x18 + 2 + read-write + + + CG13 + pwm5 clocks (pwm5_clk_enable) + 0x1A + 2 + read-write + + + CG14 + pwm6 clocks (pwm6_clk_enable) + 0x1C + 2 + read-write + + + CG15 + pwm7 clocks (pwm7_clk_enable) + 0x1E + 2 + read-write + + + + + CMEOR + CCM Module Enable Overide Register + 0x88 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MOD_EN_OV_GPT + Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk' + 0x5 + 1 + read-write + + + MOD_EN_OV_GPT_0 + don't override module enable signal + 0 + + + MOD_EN_OV_GPT_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_EPIT + Overide clock enable signal from EPIT - clock will not be gated based on EPIT's signal 'ipg_enable_clk' + 0x6 + 1 + read-write + + + MOD_EN_OV_EPIT_0 + don't override module enable signal + 0 + + + MOD_EN_OV_EPIT_1 + override module enable signal + 0x1 + + + + + MOD_EN_USDHC + overide clock enable signal from USDHC. + 0x7 + 1 + read-write + + + MOD_EN_USDHC_0 + don't override module enable signal + 0 + + + MOD_EN_USDHC_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_CAN2_CPI + Overide clock enable signal from CAN2 - clock will not be gated based on CAN's signal 'enable_clk_cpi' + 0x1C + 1 + read-write + + + MOD_EN_OV_CAN2_CPI_0 + don't override module enable signal + 0 + + + MOD_EN_OV_CAN2_CPI_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_CAN1_CPI + Overide clock enable signal from CAN1 - clock will not be gated based on CAN's signal 'enable_clk_cpi' + 0x1E + 1 + read-write + + + MOD_EN_OV_CAN1_CPI_0 + don't overide module enable signal + 0 + + + MOD_EN_OV_CAN1_CPI_1 + overide module enable signal + 0x1 + + + + + + + + + CCM_ANALOG + CCM_ANALOG + CCM_ANALOG + CCM_ANALOG_ + 0x20C8000 + + 0 + 0x180 + registers + + + + PLL_ARM + Analog ARM PLL control Register + 0 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable the clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PLL_SEL + Reserved + 0x13 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_ARM_SET + Analog ARM PLL control Register + 0x4 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable the clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PLL_SEL + Reserved + 0x13 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_ARM_CLR + Analog ARM PLL control Register + 0x8 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable the clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PLL_SEL + Reserved + 0x13 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_ARM_TOG + Analog ARM PLL control Register + 0xC + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable the clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PLL_SEL + Reserved + 0x13 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB1 + Analog USB1 480MHz PLL Control Register + 0x10 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 0x6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB1_SET + Analog USB1 480MHz PLL Control Register + 0x14 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 0x6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB1_CLR + Analog USB1 480MHz PLL Control Register + 0x18 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 0x6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB1_TOG + Analog USB1 480MHz PLL Control Register + 0x1C + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 0x6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB2 + Analog USB2 480MHz PLL Control Register + 0x20 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 0x6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB2_SET + Analog USB2 480MHz PLL Control Register + 0x24 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 0x6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB2_CLR + Analog USB2 480MHz PLL Control Register + 0x28 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 0x6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_USB2_TOG + Analog USB2 480MHz PLL Control Register + 0x2C + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 2 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 0x6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 0xC + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_SYS + Analog System PLL Control Register + 0x30 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_SYS_SET + Analog System PLL Control Register + 0x34 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_SYS_CLR + Analog System PLL Control Register + 0x38 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_SYS_TOG + Analog System PLL Control Register + 0x3C + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + GPANAIO + no description available + 0x2 + + + CHRG_DET_B + no description available + 0x3 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_SYS_SS + 528MHz System PLL Spread Spectrum Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP + Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz. + 0 + 15 + read-write + + + ENABLE + no description available + 0xF + 1 + read-write + + + ENABLE_0 + Spread spectrum modulation disabled + 0 + + + ENABLE_1 + Soread spectrum modulation enabled + 0x1 + + + + + STOP + Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz. + 0x10 + 16 + read-write + + + + + PLL_SYS_NUM + Numerator of 528MHz System PLL Fractional Loop Divider Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + A + 30 bit numerator (A) of fractional loop divider (signed integer). + 0 + 30 + read-write + + + + + PLL_SYS_DENOM + Denominator of 528MHz System PLL Fractional Loop Divider Register + 0x60 + 32 + read-write + 0x12 + 0xFFFFFFFF + + + B + 30 bit Denominator (B) of fractional loop divider (unsigned integer). + 0 + 30 + read-write + + + + + PLL_AUDIO + Analog Audio PLL control Register + 0x70 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_AUDIO_SET + Analog Audio PLL control Register + 0x74 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_AUDIO_CLR + Analog Audio PLL control Register + 0x78 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_AUDIO_TOG + Analog Audio PLL control Register + 0x7C + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enable PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_AUDIO_NUM + Numerator of Audio PLL Fractional Loop Divider Register + 0x80 + 32 + read-write + 0x5F5E100 + 0xFFFFFFFF + + + A + 30 bit numerator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_AUDIO_DENOM + Denominator of Audio PLL Fractional Loop Divider Register + 0x90 + 32 + read-write + 0x2964619C + 0xFFFFFFFF + + + B + 30 bit Denominator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_VIDEO + Analog Video PLL control Register + 0xA0 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enalbe PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_VIDEO_SET + Analog Video PLL control Register + 0xA4 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enalbe PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_VIDEO_CLR + Analog Video PLL control Register + 0xA8 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enalbe PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_VIDEO_TOG + Analog Video PLL control Register + 0xAC + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENABLE + Enalbe PLL output + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 0x13 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_VIDEO_NUM + Numerator of Video PLL Fractional Loop Divider Register + 0xB0 + 32 + read-write + 0x5F5E100 + 0xFFFFFFFF + + + A + 30 bit numerator of fractional loop divider(Signed number), absolute value should be less than denominator + 0 + 30 + read-write + + + + + PLL_VIDEO_DENOM + Denominator of Video PLL Fractional Loop Divider Register + 0xC0 + 32 + read-write + 0x10A24447 + 0xFFFFFFFF + + + B + 30 bit Denominator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_ENET + Analog ENET PLL Control Register + 0xE0 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + ENET0_DIV_SELECT + Controls the frequency of the ethernet0 reference clock. + 0 + 2 + read-write + + + ENET0_DIV_SELECT_0 + 25MHz + 0 + + + ENET0_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET0_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET0_DIV_SELECT_3 + 125MHz + 0x3 + + + + + ENET1_DIV_SELECT + Controls the frequency of the ethernet1 reference clock. + 0x2 + 2 + read-write + + + ENET1_DIV_SELECT_0 + 25MHz + 0 + + + ENET1_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET1_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET1_DIV_SELECT_3 + 125MHz + 0x3 + + + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENET1_125M_EN + Enable the PLL providing the ENET1 125 MHz reference clock. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + ENABLE_125M + Enables an offset in the phase frequency detector. + 0x13 + 1 + read-write + + + ENET2_125M_EN + Enable the PLL providing the ENET2 125 MHz reference clock + 0x14 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 0x15 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_ENET_SET + Analog ENET PLL Control Register + 0xE4 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + ENET0_DIV_SELECT + Controls the frequency of the ethernet0 reference clock. + 0 + 2 + read-write + + + ENET0_DIV_SELECT_0 + 25MHz + 0 + + + ENET0_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET0_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET0_DIV_SELECT_3 + 125MHz + 0x3 + + + + + ENET1_DIV_SELECT + Controls the frequency of the ethernet1 reference clock. + 0x2 + 2 + read-write + + + ENET1_DIV_SELECT_0 + 25MHz + 0 + + + ENET1_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET1_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET1_DIV_SELECT_3 + 125MHz + 0x3 + + + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENET1_125M_EN + Enable the PLL providing the ENET1 125 MHz reference clock. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + ENABLE_125M + Enables an offset in the phase frequency detector. + 0x13 + 1 + read-write + + + ENET2_125M_EN + Enable the PLL providing the ENET2 125 MHz reference clock + 0x14 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 0x15 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_ENET_CLR + Analog ENET PLL Control Register + 0xE8 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + ENET0_DIV_SELECT + Controls the frequency of the ethernet0 reference clock. + 0 + 2 + read-write + + + ENET0_DIV_SELECT_0 + 25MHz + 0 + + + ENET0_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET0_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET0_DIV_SELECT_3 + 125MHz + 0x3 + + + + + ENET1_DIV_SELECT + Controls the frequency of the ethernet1 reference clock. + 0x2 + 2 + read-write + + + ENET1_DIV_SELECT_0 + 25MHz + 0 + + + ENET1_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET1_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET1_DIV_SELECT_3 + 125MHz + 0x3 + + + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENET1_125M_EN + Enable the PLL providing the ENET1 125 MHz reference clock. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + ENABLE_125M + Enables an offset in the phase frequency detector. + 0x13 + 1 + read-write + + + ENET2_125M_EN + Enable the PLL providing the ENET2 125 MHz reference clock + 0x14 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 0x15 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PLL_ENET_TOG + Analog ENET PLL Control Register + 0xEC + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + ENET0_DIV_SELECT + Controls the frequency of the ethernet0 reference clock. + 0 + 2 + read-write + + + ENET0_DIV_SELECT_0 + 25MHz + 0 + + + ENET0_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET0_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET0_DIV_SELECT_3 + 125MHz + 0x3 + + + + + ENET1_DIV_SELECT + Controls the frequency of the ethernet1 reference clock. + 0x2 + 2 + read-write + + + ENET1_DIV_SELECT_0 + 25MHz + 0 + + + ENET1_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET1_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET1_DIV_SELECT_3 + 125MHz + 0x3 + + + + + POWERDOWN + Powers down the PLL. + 0xC + 1 + read-write + + + ENET1_125M_EN + Enable the PLL providing the ENET1 125 MHz reference clock. + 0xD + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 0xE + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 0x10 + 1 + read-write + + + PFD_OFFSET_EN + Enables an offset in the phase frequency detector. + 0x12 + 1 + read-write + + + ENABLE_125M + Enables an offset in the phase frequency detector. + 0x13 + 1 + read-write + + + ENET2_125M_EN + Enable the PLL providing the ENET2 125 MHz reference clock + 0x14 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 0x15 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 0x1F + 1 + read-only + + + + + PFD_480 + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF0 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + PFD_480_SET + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF4 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + PFD_480_CLR + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF8 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + PFD_480_TOG + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xFC + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + PFD_528 + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x100 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + PFD_528_SET + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x104 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + PFD_528_CLR + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x108 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + PFD_528_TOG + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x10C + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 0x7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 0x8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0xE + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 0xF + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 0x10 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x16 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 0x17 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 0x18 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 0x1E + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 0x1F + 1 + read-write + + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 0x3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 0x4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 0x7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 0xA + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 0xC + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 0xD + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 0xF + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 0x10 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 0x19 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 0x1A + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 0x1D + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 0x1E + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 0x1F + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_SET + Miscellaneous Register 0 + 0x154 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 0x3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 0x4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 0x7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 0xA + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 0xC + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 0xD + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 0xF + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 0x10 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 0x19 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 0x1A + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 0x1D + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 0x1E + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 0x1F + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_CLR + Miscellaneous Register 0 + 0x158 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 0x3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 0x4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 0x7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 0xA + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 0xC + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 0xD + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 0xF + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 0x10 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 0x19 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 0x1A + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 0x1D + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 0x1E + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 0x1F + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_TOG + Miscellaneous Register 0 + 0x15C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 0x3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 0x4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 0x7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 0xA + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 0xC + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 0xD + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 0xF + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 0x10 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 0x19 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 0x1A + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 0x1D + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 0x1E + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 0x1F + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC1 + Miscellaneous Register 1 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 0xA + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 0xC + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 0x10 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 0x11 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 0x1B + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 0x1C + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 0x1D + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 0x1E + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 0x1F + 1 + read-write + oneToClear + + + + + MISC1_SET + Miscellaneous Register 1 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 0xA + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 0xC + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 0x10 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 0x11 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 0x1B + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 0x1C + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 0x1D + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 0x1E + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 0x1F + 1 + read-write + oneToClear + + + + + MISC1_CLR + Miscellaneous Register 1 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 0xA + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 0xC + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 0x10 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 0x11 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 0x1B + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 0x1C + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 0x1D + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 0x1E + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 0x1F + 1 + read-write + oneToClear + + + + + MISC1_TOG + Miscellaneous Register 1 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 0xA + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 0xC + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 0x10 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 0x11 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 0x1B + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 0x1C + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 0x1D + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 0x1E + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 0x1F + 1 + read-write + oneToClear + + + + + MISC2 + Miscellaneous Register 2 + 0x170 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x5 + 1 + read-write + + + PLL3_disable + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 0x7 + 1 + read-write + + + PLL3_disable_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_disable_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 0xB + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0xD + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 0xF + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x10 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x13 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x15 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 0x16 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 0x17 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x18 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1A + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1C + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 0x1E + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_SET + Miscellaneous Register 2 + 0x174 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x5 + 1 + read-write + + + PLL3_disable + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 0x7 + 1 + read-write + + + PLL3_disable_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_disable_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 0xB + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0xD + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 0xF + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x10 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x13 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x15 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 0x16 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 0x17 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x18 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1A + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1C + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 0x1E + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_CLR + Miscellaneous Register 2 + 0x178 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x5 + 1 + read-write + + + PLL3_disable + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 0x7 + 1 + read-write + + + PLL3_disable_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_disable_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 0xB + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0xD + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 0xF + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x10 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x13 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x15 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 0x16 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 0x17 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x18 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1A + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1C + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 0x1E + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_TOG + Miscellaneous Register 2 + 0x17C + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x5 + 1 + read-write + + + PLL3_disable + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 0x7 + 1 + read-write + + + PLL3_disable_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_disable_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 0xB + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0xD + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 0xF + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 0x10 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 0x13 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 0x15 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 0x16 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 0x17 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x18 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1A + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 0x1C + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 0x1E + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + + + PMU + PMU + PMU + PMU_ + 0x20C8110 + + 0 + 0x170 + registers + + + PMU_IRQ1 + 86 + + + PMU_IRQ2 + 159 + + + + REG_1P1 + Regulator 1P1 Register + 0 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 0x1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 0x2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 0x3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 0x4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 0x8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 0x10 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 0x11 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 0x12 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 0x13 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_CAP voltage + 0x1 + + + + + + + REG_3P0 + Regulator 3P0 Register + 0x10 + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 0x1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 0x2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 0x4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 0x7 + 1 + read-write + + + USB_OTG1_VBUS + Utilize VBUS OTG1 for power + 0 + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 0x8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 0x10 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 0x11 + 1 + read-only + + + + + REG_2P5 + Regulator 2P5 Register + 0x20 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 0x1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 0x2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 0x3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 0x4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 0x8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 0x10 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 0x11 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 0x12 + 1 + read-write + + + + + REG_CORE + Digital Regulator Core Register + 0x30 + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the ARM core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 0x12 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + RAMP_RATE + Regulator voltage ramp rate. + 0x1B + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 0x1D + 1 + read-write + + + + + LOWPWR_CTRL + Low Power Control Register + 0x160 + 32 + read-write + 0x4009 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + RC_OSC_PROG + RC osc. tuning values. + 0x1 + 3 + read-write + + + OSC_SEL + Select the source for the 24MHz clock. + 0x4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 0x5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 0x6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 0x7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 0x8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 0x9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 0xA + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 0xB + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 0xD + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 0xE + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 0x10 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 0x11 + 1 + read-write + + + + + LOWPWR_CTRL_SET + Low Power Control Register + 0x164 + 32 + read-write + 0x4009 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. Not related to PMU. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + RC_OSC_PROG + RC osc. tuning values. Not related to PMU. + 0x1 + 3 + read-write + + + OSC_SEL + Select the source for the 24MHz clock. Not related to PMU. + 0x4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. + 0x5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. + 0x6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. + 0x7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. + 0x8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. + 0x9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override.Test purpose only + 0xA + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. + 0xB + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 0xD + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 0xE + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. Not related to PMU. + 0x10 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 0x11 + 1 + read-write + + + + + LOWPWR_CTRL_CLR + Low Power Control Register + 0x168 + 32 + read-write + 0x4009 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. Not related to PMU. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + RC_OSC_PROG + RC osc. tuning values. Not related to PMU. + 0x1 + 3 + read-write + + + OSC_SEL + Select the source for the 24MHz clock. Not related to PMU. + 0x4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. + 0x5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. + 0x6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. + 0x7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. + 0x8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. + 0x9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override.Test purpose only + 0xA + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. + 0xB + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 0xD + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 0xE + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. Not related to PMU. + 0x10 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 0x11 + 1 + read-write + + + + + LOWPWR_CTRL_TOG + Low Power Control Register + 0x16C + 32 + read-write + 0x4009 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. Not related to PMU. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + RC_OSC_PROG + RC osc. tuning values. Not related to PMU. + 0x1 + 3 + read-write + + + OSC_SEL + Select the source for the 24MHz clock. Not related to PMU. + 0x4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. + 0x5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. + 0x6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. + 0x7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. + 0x8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. + 0x9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override.Test purpose only + 0xA + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. + 0xB + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 0xD + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 0xE + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. Not related to PMU. + 0x10 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 0x11 + 1 + read-write + + + + + + + TEMPMON + Temperature Monitor + TEMPMON + TEMPMON_ + 0x20C8180 + + 0 + 0x120 + registers + + + TEMPMON + 81 + + + + TEMPSENSE0 + Tempsensor Control Register 0 + 0 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 0x1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 0x2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 0x8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate an alarm interrupt + 0x14 + 12 + read-write + + + + + TEMPSENSE0_SET + Tempsensor Control Register 0 + 0x4 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 0x1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 0x2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 0x8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate an alarm interrupt + 0x14 + 12 + read-write + + + + + TEMPSENSE0_CLR + Tempsensor Control Register 0 + 0x8 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 0x1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 0x2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 0x8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate an alarm interrupt + 0x14 + 12 + read-write + + + + + TEMPSENSE0_TOG + Tempsensor Control Register 0 + 0xC + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 0x1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 0x2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 0x8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate an alarm interrupt + 0x14 + 12 + read-write + + + + + TEMPSENSE1 + Tempsensor Control Register 1 + 0x10 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_SET + Tempsensor Control Register 1 + 0x14 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_CLR + Tempsensor Control Register 1 + 0x18 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_TOG + Tempsensor Control Register 1 + 0x1C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE2 + Tempsensor Control Register 2 + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature that will generate a panic interrupt when exceeded by the temperature measurement + 0x10 + 12 + read-write + + + + + TEMPSENSE2_SET + Tempsensor Control Register 2 + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature that will generate a panic interrupt when exceeded by the temperature measurement + 0x10 + 12 + read-write + + + + + TEMPSENSE2_CLR + Tempsensor Control Register 2 + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature that will generate a panic interrupt when exceeded by the temperature measurement + 0x10 + 12 + read-write + + + + + TEMPSENSE2_TOG + Tempsensor Control Register 2 + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature that will generate a low alarm interrupt when the field is greater than the temperature measurement + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature that will generate a panic interrupt when exceeded by the temperature measurement + 0x10 + 12 + read-write + + + + + + + USB_ANALOG + USB Analog + USB_ANALOG + USB_ANALOG_ + 0x20C81A0 + + 0 + 0xC4 + registers + + + + USB1_VBUS_DETECT + USB VBUS Detect Register + 0 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB1_VBUS_DETECT_SET + USB VBUS Detect Register + 0x4 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB1_VBUS_DETECT_CLR + USB VBUS Detect Register + 0x8 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB1_VBUS_DETECT_TOG + USB VBUS Detect Register + 0xC + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB1_CHRG_DETECT + USB Charger Detect Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_SET + USB Charger Detect Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_CLR + USB Charger Detect Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_TOG + USB Charger Detect Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_VBUS_DETECT_STAT + USB VBUS Detect Status Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + Session End for USB OTG + 0 + 1 + read-only + + + BVALID + Indicates VBus is valid for a B-peripheral + 0x1 + 1 + read-only + + + AVALID + Indicates VBus is valid for a A-peripheral + 0x2 + 1 + read-only + + + VBUS_VALID + VBus valid for USB OTG + 0x3 + 1 + read-only + + + + + USB1_CHRG_DETECT_STAT + USB Charger Detect Status Register + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + State of the USB plug contact detector. + 0 + 1 + read-only + + + NO_CONTACT + The USB plug has not made contact. + 0 + + + GOOD_CONTACT + The USB plug has made good contact. + 0x1 + + + + + CHRG_DETECTED + State of charger detection. This bit is a read only version of the state of the analog signal. + 0x1 + 1 + read-only + + + CHARGER_NOT_PRESENT + The USB port is not connected to a charger. + 0 + + + CHARGER_PRESENT + A charger (either a dedicated charger or a host charger) is connected to the USB port. + 0x1 + + + + + DM_STATE + DM line state output of the charger detector. + 0x2 + 1 + read-only + + + DP_STATE + DP line state output of the charger detector. + 0x3 + 1 + read-only + + + + + USB1_MISC + USB Misc Register + 0x50 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + USB1_MISC_SET + USB Misc Register + 0x54 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + USB1_MISC_CLR + USB Misc Register + 0x58 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + USB1_MISC_TOG + USB Misc Register + 0x5C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + USB2_VBUS_DETECT + USB VBUS Detect Register + 0x60 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB2_VBUS_DETECT_SET + USB VBUS Detect Register + 0x64 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB2_VBUS_DETECT_CLR + USB VBUS Detect Register + 0x68 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB2_VBUS_DETECT_TOG + USB VBUS Detect Register + 0x6C + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 0x14 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 0x1A + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 0x1B + 1 + read-write + + + + + USB2_CHRG_DETECT + USB Charger Detect Register + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_SET + USB Charger Detect Register + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_CLR + USB Charger Detect Register + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_TOG + USB Charger Detect Register + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + no description available + 0x12 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + no description available + 0x13 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 0x14 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_VBUS_DETECT_STAT + USB VBUS Detect Status Register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + Session End for USB OTG + 0 + 1 + read-only + + + BVALID + Indicates VBus is valid for a B-peripheral + 0x1 + 1 + read-only + + + AVALID + Indicates VBus is valid for a A-peripheral + 0x2 + 1 + read-only + + + VBUS_VALID + VBus valid for USB OTG + 0x3 + 1 + read-only + + + + + USB2_CHRG_DETECT_STAT + USB Charger Detect Status Register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + State of the USB plug contact detector. + 0 + 1 + read-only + + + NO_CONTACT + The USB plug has not made contact. + 0 + + + GOOD_CONTACT + The USB plug has made good contact. + 0x1 + + + + + CHRG_DETECTED + State of charger detection. This bit is a read only version of the state of the analog signal. + 0x1 + 1 + read-only + + + CHARGER_NOT_PRESENT + The USB port is not connected to a charger. + 0 + + + CHARGER_PRESENT + A charger (either a dedicated charger or a host charger) is connected to the USB port. + 0x1 + + + + + DM_STATE + DM line state output of the charger detector. + 0x2 + 1 + read-only + + + DP_STATE + DP line state output of the charger detector. + 0x3 + 1 + read-only + + + + + USB2_MISC + USB Misc Register + 0xB0 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + USB2_MISC_SET + USB Misc Register + 0xB4 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + USB2_MISC_CLR + USB Misc Register + 0xB8 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + USB2_MISC_TOG + USB Misc Register + 0xBC + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 0x1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 0x1E + 1 + read-write + + + + + DIGPROG + Chip Silicon Version + 0xC0 + 32 + read-only + 0x640000 + 0xFFFFFFFF + + + MINOR + MINOR lower byte - Read-only value representing a minor silicon revision. + 0 + 8 + read-only + + + MINOR_0 + silicon revision x.0 + 0 + + + MINOR_1 + silicon revision x.1 + 0x1 + + + MINOR_2 + silicon revision x.2 + 0x2 + + + MINOR_3 + silicon revision x.3 + 0x3 + + + + + MAJOR_LOWER + MAJOR lower byte - Read-only value representing a major silicon revision. + 0x8 + 8 + read-only + + + MAJOR_LOWER_0 + silicon revision 1.x + 0 + + + MAJOR_LOWER_1 + silicon revision 2.x + 0x1 + + + + + MAJOR_UPPER + MAJOR upper byte-Read-only value representing the chip type. + 0x10 + 8 + read-only + + + MAJOR_UPPER_101 + i.MX 6ULL + 0x65 + + + + + + + + + XTALOSC24M + XTALOSC24M + XTALOSC24M + XTALOSC24M_ + 0x20C82A0 + + 0 + 0x30 + registers + + + + OSC_CONFIG0 + XTAL OSC Configuration 0 Register + 0 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 0x1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 0x2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 0x3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 0x4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 0xC + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 0x10 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 0x18 + 8 + read-write + + + + + OSC_CONFIG0_SET + XTAL OSC Configuration 0 Register + 0x4 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 0x1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 0x2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 0x3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 0x4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 0xC + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 0x10 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 0x18 + 8 + read-write + + + + + OSC_CONFIG0_CLR + XTAL OSC Configuration 0 Register + 0x8 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 0x1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 0x2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 0x3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 0x4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 0xC + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 0x10 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 0x18 + 8 + read-write + + + + + OSC_CONFIG0_TOG + XTAL OSC Configuration 0 Register + 0xC + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 0x1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 0x2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 0x3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 0x4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 0xC + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 0x10 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 0x18 + 8 + read-write + + + + + OSC_CONFIG1 + XTAL OSC Configuration 1 Register + 0x10 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 0x14 + 12 + read-write + + + + + OSC_CONFIG1_SET + XTAL OSC Configuration 1 Register + 0x14 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 0x14 + 12 + read-write + + + + + OSC_CONFIG1_CLR + XTAL OSC Configuration 1 Register + 0x18 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 0x14 + 12 + read-write + + + + + OSC_CONFIG1_TOG + XTAL OSC Configuration 1 Register + 0x1C + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 0x14 + 12 + read-write + + + + + OSC_CONFIG2 + XTAL OSC Configuration 2 Register + 0x20 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 0x10 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output. + 0x11 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32KHz period + 0x1F + 1 + read-write + + + + + OSC_CONFIG2_SET + XTAL OSC Configuration 2 Register + 0x24 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 0x10 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output. + 0x11 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32KHz period + 0x1F + 1 + read-write + + + + + OSC_CONFIG2_CLR + XTAL OSC Configuration 2 Register + 0x28 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 0x10 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output. + 0x11 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32KHz period + 0x1F + 1 + read-write + + + + + OSC_CONFIG2_TOG + XTAL OSC Configuration 2 Register + 0x2C + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 0x10 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output. + 0x11 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32KHz period + 0x1F + 1 + read-write + + + + + + + USBPHY1 + USBPHY Register Reference Index + USBPHY + USBPHY1_ + 0x20C9000 + USBPHY + + 0 + 0x84 + registers + + + USB_PHY1 + 76 + + + + PWD + USB PHY Power-Down Register + 0 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 0xA + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 0xB + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 0x11 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 0x12 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 0x13 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 0x14 + 1 + read-write + + + RSVD2 + Reserved. + 0x15 + 11 + read-only + + + + + PWD_SET + USB PHY Power-Down Register + 0x4 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 0xA + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 0xB + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 0x11 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 0x12 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 0x13 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 0x14 + 1 + read-write + + + RSVD2 + Reserved. + 0x15 + 11 + read-only + + + + + PWD_CLR + USB PHY Power-Down Register + 0x8 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 0xA + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 0xB + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 0x11 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 0x12 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 0x13 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 0x14 + 1 + read-write + + + RSVD2 + Reserved. + 0x15 + 11 + read-only + + + + + PWD_TOG + USB PHY Power-Down Register + 0xC + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 0xA + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 0xB + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 0x11 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 0x12 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 0x13 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 0x14 + 1 + read-write + + + RSVD2 + Reserved. + 0x15 + 11 + read-only + + + + + TX + USB PHY Transmitter Control Register + 0x10 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0x4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 0x8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 0xC + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 0x10 + 4 + read-write + + + RSVD2 + Reserved. + 0x14 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 0x1A + 3 + read-write + + + RSVD5 + Reserved. + 0x1D + 3 + read-only + + + + + TX_SET + USB PHY Transmitter Control Register + 0x14 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0x4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 0x8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 0xC + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 0x10 + 4 + read-write + + + RSVD2 + Reserved. + 0x14 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 0x1A + 3 + read-write + + + RSVD5 + Reserved. + 0x1D + 3 + read-only + + + + + TX_CLR + USB PHY Transmitter Control Register + 0x18 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0x4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 0x8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 0xC + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 0x10 + 4 + read-write + + + RSVD2 + Reserved. + 0x14 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 0x1A + 3 + read-write + + + RSVD5 + Reserved. + 0x1D + 3 + read-only + + + + + TX_TOG + USB PHY Transmitter Control Register + 0x1C + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0x4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 0x8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 0xC + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 0x10 + 4 + read-write + + + RSVD2 + Reserved. + 0x14 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 0x1A + 3 + read-write + + + RSVD5 + Reserved. + 0x1D + 3 + read-only + + + + + RX + USB PHY Receiver Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 0x3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 0x4 + 3 + read-write + + + RSVD1 + Reserved. + 0x7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 0x16 + 1 + read-write + + + RSVD2 + Reserved. + 0x17 + 9 + read-only + + + + + RX_SET + USB PHY Receiver Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 0x3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 0x4 + 3 + read-write + + + RSVD1 + Reserved. + 0x7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 0x16 + 1 + read-write + + + RSVD2 + Reserved. + 0x17 + 9 + read-only + + + + + RX_CLR + USB PHY Receiver Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 0x3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 0x4 + 3 + read-write + + + RSVD1 + Reserved. + 0x7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 0x16 + 1 + read-write + + + RSVD2 + Reserved. + 0x17 + 9 + read-only + + + + + RX_TOG + USB PHY Receiver Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 0x3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 0x4 + 3 + read-write + + + RSVD1 + Reserved. + 0x7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 0x16 + 1 + read-write + + + RSVD2 + Reserved. + 0x17 + 9 + read-only + + + + + CTRL + USB PHY General Control Register + 0x30 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 0x1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 0x2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 0x3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 0x4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 0x5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 0x6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 0x7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 0x8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 0x9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 0xA + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 0xB + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 0xC + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 0xD + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 0xE + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 0xF + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 0x10 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 0x11 + 1 + read-write + + + RSVD0 + Reserved. + 0x12 + 1 + read-only + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 0x13 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 0x14 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 0x15 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 0x16 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 0x17 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 0x18 + 1 + read-write + + + RSVD1 + Reserved. + 0x19 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 0x1B + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 0x1C + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 0x1D + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 0x1E + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 0x1F + 1 + read-write + + + + + CTRL_SET + USB PHY General Control Register + 0x34 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 0x1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 0x2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 0x3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 0x4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 0x5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 0x6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 0x7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 0x8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 0x9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 0xA + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 0xB + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 0xC + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 0xD + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 0xE + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 0xF + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 0x10 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 0x11 + 1 + read-write + + + RSVD0 + Reserved. + 0x12 + 1 + read-only + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 0x13 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 0x14 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 0x15 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 0x16 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 0x17 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 0x18 + 1 + read-write + + + RSVD1 + Reserved. + 0x19 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 0x1B + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 0x1C + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 0x1D + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 0x1E + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 0x1F + 1 + read-write + + + + + CTRL_CLR + USB PHY General Control Register + 0x38 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 0x1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 0x2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 0x3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 0x4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 0x5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 0x6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 0x7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 0x8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 0x9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 0xA + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 0xB + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 0xC + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 0xD + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 0xE + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 0xF + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 0x10 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 0x11 + 1 + read-write + + + RSVD0 + Reserved. + 0x12 + 1 + read-only + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 0x13 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 0x14 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 0x15 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 0x16 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 0x17 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 0x18 + 1 + read-write + + + RSVD1 + Reserved. + 0x19 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 0x1B + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 0x1C + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 0x1D + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 0x1E + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 0x1F + 1 + read-write + + + + + CTRL_TOG + USB PHY General Control Register + 0x3C + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 0x1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 0x2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 0x3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 0x4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 0x5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 0x6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 0x7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 0x8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 0x9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 0xA + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 0xB + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 0xC + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 0xD + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 0xE + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 0xF + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 0x10 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 0x11 + 1 + read-write + + + RSVD0 + Reserved. + 0x12 + 1 + read-only + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 0x13 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 0x14 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 0x15 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 0x16 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 0x17 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 0x18 + 1 + read-write + + + RSVD1 + Reserved. + 0x19 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 0x1B + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 0x1C + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 0x1D + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 0x1E + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 0x1F + 1 + read-write + + + + + STATUS + USB PHY Status Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 3 + read-only + + + HOSTDISCONDETECT_STATUS + Indicates that the device has disconnected while in high-speed host mode. + 0x3 + 1 + read-only + + + RSVD1 + Reserved. + 0x4 + 2 + read-only + + + DEVPLUGIN_STATUS + Indicates that the device has been connected on the USB_DP and USB_DM lines. + 0x6 + 1 + read-only + + + RSVD2 + Reserved. + 0x7 + 1 + read-only + + + OTGID_STATUS + Indicates the results of ID pin on MiniAB plug + 0x8 + 1 + read-write + + + RSVD3 + Reserved. + 0x9 + 1 + read-only + + + RESUME_STATUS + Indicates that the host is sending a wake-up after suspend and has triggered an interrupt. + 0xA + 1 + read-only + + + RSVD4 + Reserved. + 0xB + 21 + read-only + + + + + DEBUG + USB PHY Debug Register + 0x50 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 0x1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 0x2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 0x4 + 2 + read-write + + + RSVD0 + Reserved. + 0x6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 0x8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 0x10 + 5 + read-write + + + RSVD2 + Reserved. + 0x15 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 0x18 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 0x19 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 0x1D + 1 + read-write + + + CLKGATE + Gate Test Clocks + 0x1E + 1 + read-write + + + RSVD3 + Reserved. + 0x1F + 1 + read-only + + + + + DEBUG_SET + USB PHY Debug Register + 0x54 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 0x1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 0x2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 0x4 + 2 + read-write + + + RSVD0 + Reserved. + 0x6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 0x8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 0x10 + 5 + read-write + + + RSVD2 + Reserved. + 0x15 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 0x18 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 0x19 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 0x1D + 1 + read-write + + + CLKGATE + Gate Test Clocks + 0x1E + 1 + read-write + + + RSVD3 + Reserved. + 0x1F + 1 + read-only + + + + + DEBUG_CLR + USB PHY Debug Register + 0x58 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 0x1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 0x2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 0x4 + 2 + read-write + + + RSVD0 + Reserved. + 0x6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 0x8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 0x10 + 5 + read-write + + + RSVD2 + Reserved. + 0x15 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 0x18 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 0x19 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 0x1D + 1 + read-write + + + CLKGATE + Gate Test Clocks + 0x1E + 1 + read-write + + + RSVD3 + Reserved. + 0x1F + 1 + read-only + + + + + DEBUG_TOG + USB PHY Debug Register + 0x5C + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 0x1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 0x2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 0x4 + 2 + read-write + + + RSVD0 + Reserved. + 0x6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 0x8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 0xC + 1 + read-write + + + RSVD1 + Reserved. + 0xD + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 0x10 + 5 + read-write + + + RSVD2 + Reserved. + 0x15 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 0x18 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 0x19 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 0x1D + 1 + read-write + + + CLKGATE + Gate Test Clocks + 0x1E + 1 + read-write + + + RSVD3 + Reserved. + 0x1F + 1 + read-only + + + + + DEBUG0_STATUS + UTMI Debug Status Register 0 + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + LOOP_BACK_FAIL_COUNT + Running count of the failed pseudo-random generator loopback + 0 + 16 + read-only + + + UTMI_RXERROR_FAIL_COUNT + Running count of the UTMI_RXERROR. + 0x10 + 10 + read-only + + + SQUELCH_COUNT + Running count of the squelch reset instead of normal end for HS RX. + 0x1A + 6 + read-only + + + + + DEBUG1 + UTMI Debug Status Register 1 + 0x70 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 0xD + 2 + read-write + + + RSVD1 + Reserved. + 0xF + 17 + read-only + + + + + DEBUG1_SET + UTMI Debug Status Register 1 + 0x74 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 0xD + 2 + read-write + + + RSVD1 + Reserved. + 0xF + 17 + read-only + + + + + DEBUG1_CLR + UTMI Debug Status Register 1 + 0x78 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 0xD + 2 + read-write + + + RSVD1 + Reserved. + 0xF + 17 + read-only + + + + + DEBUG1_TOG + UTMI Debug Status Register 1 + 0x7C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 0xD + 2 + read-write + + + RSVD1 + Reserved. + 0xF + 17 + read-only + + + + + VERSION + UTMI RTL Version + 0x80 + 32 + read-only + 0x4020000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + + + USBPHY2 + USBPHY Register Reference Index + USBPHY + USBPHY2_ + 0x20CA000 + + 0 + 0x84 + registers + + + USB_PHY2 + 77 + + + + EPIT1 + EPIT + EPIT + EPIT1_ + 0x20D0000 + EPIT + + 0 + 0x14 + registers + + + EPIT1 + 88 + + + + CR + Control register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + This bit enables the EPIT + 0 + 1 + read-write + + + EN_0 + EPIT is disabled + 0 + + + EN_1 + EPIT is enabled + 0x1 + + + + + ENMOD + EPIT enable mode + 0x1 + 1 + read-write + + + ENMOD_0 + Counter starts counting from the value it had when it was disabled. + 0 + + + ENMOD_1 + Counter starts count from load value (RLD=1) or 0xFFFF_FFFF (If RLD=0) + 0x1 + + + + + OCIEN + Output compare interrupt enable + 0x2 + 1 + read-write + + + OCIEN_0 + Compare interrupt disabled + 0 + + + OCIEN_1 + Compare interrupt enabled + 0x1 + + + + + RLD + Counter reload control + 0x3 + 1 + read-write + + + RLD_0 + When the counter reaches zero it rolls over to 0xFFFF_FFFF (free-running mode) + 0 + + + RLD_1 + When the counter reaches zero it reloads from the modulus register (set-and-forget mode) + 0x1 + + + + + PRESCALAR + Counter clock prescaler value + 0x4 + 12 + read-write + + + PRESCALAR_0 + Divide by 1 + 0 + + + PRESCALAR_1 + Divide by 2... + 0x1 + + + PRESCALAR_4095 + Divide by 4096 + 0xFFF + + + + + SWR + Software reset + 0x10 + 1 + read-write + + + SWR_0 + EPIT is out of reset + 0 + + + SWR_1 + EPIT is undergoing reset + 0x1 + + + + + IOVW + EPIT counter overwrite enable + 0x11 + 1 + read-write + + + IOVW_0 + Write to load register does not result in counter value being overwritten. + 0 + + + IOVW_1 + Write to load register results in immediate overwriting of counter value. + 0x1 + + + + + DBGEN + This bit is used to keep the EPIT functional in debug mode + 0x12 + 1 + read-write + + + DBGEN_0 + Inactive in debug mode + 0 + + + DBGEN_1 + Active in debug mode + 0x1 + + + + + WAITEN + This read/write control bit enables the operation of the EPIT during wait mode + 0x13 + 1 + read-write + + + WAITEN_0 + EPIT is disabled in wait mode + 0 + + + WAITEN_1 + EPIT is enabled in wait mode + 0x1 + + + + + STOPEN + EPIT stop mode enable + 0x15 + 1 + read-write + + + STOPEN_0 + EPIT is disabled in stop mode + 0 + + + STOPEN_1 + EPIT is enabled in stop mode + 0x1 + + + + + OM + EPIT output mode.This bit field determines the mode of EPIT output on the output pin. + 0x16 + 2 + read-write + + + OM_0 + EPIT output is disconnected from pad + 0 + + + OM_1 + Toggle output pin + 0x1 + + + OM_2 + Clear output pin + 0x2 + + + OM_3 + Set output pin + 0x3 + + + + + CLKSRC + Select clock source These bits determine which clock input is to be selected for running the counter + 0x18 + 2 + read-write + + + CLKSRC_0 + Clock is off + 0 + + + CLKSRC_1 + Peripheral clock + 0x1 + + + CLKSRC_2 + High-frequency reference clock + 0x2 + + + CLKSRC_3 + Low-frequency reference clock + 0x3 + + + + + + + SR + Status register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + OCIF + Output compare interrupt flag + 0 + 1 + read-write + oneToClear + + + OCIF_0 + Compare event has not occurred + 0 + + + OCIF_1 + Compare event occurred + 0x1 + + + + + + + LR + Load register + 0x8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + LOAD + Load value. Value that is loaded into the counter at the start of each count cycle. + 0 + 32 + read-write + + + + + CMPR + Compare register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + COMPARE + Compare Value. When the counter value equals this bit field value a compare event is generated. + 0 + 32 + read-write + + + + + CNR + Counter register + 0x10 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + COUNT + Counter value. This contains the current value of the counter. + 0 + 32 + read-only + + + + + + + EPIT2 + EPIT + EPIT + EPIT2_ + 0x20D4000 + + 0 + 0x14 + registers + + + EPIT2 + 89 + + + + SRC + SRC + SRC + SRC_ + 0x20D8000 + + 0 + 0x48 + registers + + + SRC + 123 + + + SRC_Combined + 128 + + + + SCR + SRC Control Register + 0 + 32 + read-write + 0x521 + 0xFFFFFFFF + + + warm_reset_enable + WARM reset enable bit + 0 + 1 + read-write + + + warm_reset_enable_0 + WARM reset disabled + 0 + + + warm_reset_enable_1 + WARM reset enabled + 0x1 + + + + + warm_rst_bypass_count + Defines the XTALI cycles to count before bypassing the MMDC acknowledge for WARM reset + 0x5 + 2 + read-write + + + warm_rst_bypass_count_0 + Counter not to be used - system will wait until MMDC acknowledge until it is asserted. + 0 + + + warm_rst_bypass_count_1 + Wait 16 XTALI cycles before changing WARM reset to a COLD reset. + 0x1 + + + warm_rst_bypass_count_2 + Wait 32 XTALI cycles before changing WARM reset to a COLD reset. + 0x2 + + + warm_rst_bypass_count_3 + Wait 64 XTALI cycles before changing WARM reset to a COLD reset + 0x3 + + + + + mask_wdog_rst + Mask wdog_rst_b source + 0x7 + 4 + read-write + + + mask_wdog_rst_5 + wdog_rst_b is masked + 0x5 + + + mask_wdog_rst_10 + wdog_rst_b is not masked (default) + 0xA + + + + + eim_rst + EIM reset is needed in order to reconfigure the eim chip select + 0xB + 1 + read-write + + + core0_rst + Software reset for core0 only + 0xD + 1 + read-write + + + core0_rst_0 + do not assert core0 reset + 0 + + + core0_rst_1 + assert core0 reset + 0x1 + + + + + core0_dbg_rst + Software reset for core0 debug only + 0x11 + 1 + read-write + + + core0_dbg_rst_0 + do not assert core0 debug reset + 0 + + + core0_dbg_rst_1 + assert core0 debug reset + 0x1 + + + + + cores_dbg_rst + Software reset for debug of arm platform only + 0x15 + 1 + read-write + + + cores_dbg_rst_0 + do not assert arm platform debug reset + 0 + + + cores_dbg_rst_1 + assert arm platform debug reset + 0x1 + + + + + wdog3_rst_optn + Wdog3_rst_b option + 0x18 + 1 + read-write + + + wdog3_rst_optn_0 + Wdog3_rst_b asserts M4 reset (default) + 0 + + + wdog3_rst_optn_1 + Wdog3_rst_b asserts global reset + 0x1 + + + + + dbg_rst_msk_pg + Do not assert debug resets after power gating event of core + 0x19 + 1 + read-write + + + dbg_rst_msk_pg_0 + do not mask core debug resets (debug resets will be asserted after power gating event) + 0 + + + dbg_rst_msk_pg_1 + mask core debug resets (debug resets won't be asserted after power gating event) + 0x1 + + + + + mix_rst_strch + SoC mix (Audio, ENET, uSDHC, EIM, QSPI, OCRAM, MMDC, etc) power up reset stretch mix reset width = (mix_rst_strtch +1)* 88 ipg_clk cycles + 0x1A + 2 + read-write + + + mix_rst_strch_0 + mix reset width is 88 ipg_cycle cycles + 0 + + + mix_rst_strch_1 + mix reset width is 2 * 88 ipg_cycle cycles + 0x1 + + + mix_rst_strch_2 + mix reset width is 3 * 88 ipg_cycle cycles + 0x2 + + + mix_rst_strch_3 + mix reset width is 4 * 88 ipg_cycle cycles + 0x3 + + + + + mask_wdog3_rst + Mask wdog3_rst_b source + 0x1C + 4 + read-write + + + mask_wdog3_rst_5 + wdog3_rst_b is masked + 0x5 + + + mask_wdog3_rst_10 + wdog3_rst_b is not masked + 0xA + + + + + + + SBMR1 + SRC Boot Mode Register 1 + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + BOOT_CFG1 + Refer to fusemap. + 0 + 8 + read-only + + + BOOT_CFG2 + Refer to fusemap. + 0x8 + 8 + read-only + + + BOOT_CFG3 + Refer to fusemap. + 0x10 + 8 + read-only + + + BOOT_CFG4 + Refer to fusemap. + 0x18 + 8 + read-only + + + + + SRSR + SRC Reset Status Register + 0x8 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ipp_reset_b + Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence) + 0 + 1 + read-write + oneToClear + + + ipp_reset_b_0 + Reset is not a result of ipp_reset_b pin. + 0 + + + ipp_reset_b_1 + Reset is a result of ipp_reset_b pin. + 0x1 + + + + + csu_reset_b + Indicates whether the reset was the result of the csu_reset_b input + 0x2 + 1 + read-write + oneToClear + + + csu_reset_b_0 + Reset is not a result of the csu_reset_b event. + 0 + + + csu_reset_b_1 + Reset is a result of the csu_reset_b event. + 0x1 + + + + + ipp_user_reset_b + Indicates whether the reset was the result of the ipp_user_reset_b qualified reset. + 0x3 + 1 + read-write + oneToClear + + + ipp_user_reset_b_0 + Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + 0 + + + ipp_user_reset_b_1 + Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + 0x1 + + + + + wdog_rst_b + IC Watchdog Time-out reset + 0x4 + 1 + read-write + oneToClear + + + wdog_rst_b_0 + Reset is not a result of the watchdog time-out event. + 0 + + + wdog_rst_b_1 + Reset is a result of the watchdog time-out event. + 0x1 + + + + + jtag_rst_b + HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG. + 0x5 + 1 + read-write + oneToClear + + + jtag_rst_b_0 + Reset is not a result of HIGH-Z reset from JTAG. + 0 + + + jtag_rst_b_1 + Reset is a result of HIGH-Z reset from JTAG. + 0x1 + + + + + jtag_sw_rst + JTAG software reset. Indicates whether the reset was the result of software reset from JTAG. + 0x6 + 1 + read-write + oneToClear + + + jtag_sw_rst_0 + Reset is not a result of software reset from JTAG. + 0 + + + jtag_sw_rst_1 + Reset is a result of software reset from JTAG. + 0x1 + + + + + wdog3_rst_b + IC Watchdog3 Time-out reset + 0x7 + 1 + read-write + oneToClear + + + wdog3_rst_b_0 + Reset is not a result of the watchdog3 time-out event. + 0 + + + wdog3_rst_b_1 + Reset is a result of the watchdog3 time-out event. + 0x1 + + + + + tempsense_rst_b + Temper Sensor software reset + 0x8 + 1 + read-write + + + tempsense_rst_b_0 + Reset is not a result of software reset from Temperature Sensor. + 0 + + + tempsense_rst_b_1 + Reset is a result of software reset from Temperature Sensor. + 0x1 + + + + + warm_boot + WARM boot indication shows that WARM boot was initiated by software + 0x10 + 1 + read-write + + + warm_boot_0 + WARM boot process not initiated by software. + 0 + + + warm_boot_1 + WARM boot initiated by software. + 0x1 + + + + + + + SISR + SRC Interrupt Status Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + core0_wdog_rst_req + WDOG reset request from core0. Read-only status bit. + 0x5 + 1 + read-only + + + + + SBMR2 + SRC Boot Mode Register 2 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + SEC_CONFIG + SECONFIG[1] shows the state of the SECONFIG[1] fuse + 0 + 2 + read-only + + + DIR_BT_DIS + DIR_BT_DIS shows the state of the DIR_BT_DIS fuse + 0x3 + 1 + read-only + + + BT_FUSE_SEL + BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse + 0x4 + 1 + read-only + + + BMOD + BMOD[1:0] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B + 0x18 + 2 + read-only + + + + + GPR1 + SRC General Purpose Register 1 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ENTRY0 + Holds entry function for core0 for waking-up from low power mode + 0 + 32 + read-write + + + + + GPR2 + SRC General Purpose Register 2 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ARG0 + Holds argument of entry function for core0 for waking-up from low power mode + 0 + 32 + read-write + + + + + GPR3 + SRC General Purpose Register 3 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR4 + SRC General Purpose Register 4 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR5 + SRC General Purpose Register 5 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR6 + SRC General Purpose Register 6 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR7 + SRC General Purpose Register 7 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR8 + SRC General Purpose Register 8 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR9 + SRC General Purpose Register 9 + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR10 + SRC General Purpose Register 10 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + + + GPC + GPC + GPC + GPC_ + 0x20DC000 + + 0 + 0x28 + registers + + + GPC + 121 + + + + CNTR + GPC Interface control register + 0 + 32 + read-write + 0x520000 + 0xFFFFFFFF + + + MEGA_PDN_REQ + MEGA domain power down request + 0x2 + 1 + read-write + + + MEGA_PDN_REQ_0 + No Request + 0 + + + MEGA_PDN_REQ_1 + Request power down sequence + 0x1 + + + + + MEGA_PUP_REQ + MEGA domain power up request + 0x3 + 1 + read-write + + + MEGA_PUP_REQ_0 + No Request + 0 + + + MEGA_PUP_REQ_1 + Request power up sequence + 0x1 + + + + + DISPLAY_PDN_REQ + Display Power Down request + 0x4 + 1 + read-write + + + DISPLAY_PDN_REQ_0 + no request + 0 + + + DISPLAY_PDN_REQ_1 + Request Power Down sequence to start for Display + 0x1 + + + + + DISPLAY_PUP_REQ + Display Power Up request + 0x5 + 1 + read-write + + + DISPLAY_PUP_REQ_0 + no request + 0 + + + DISPLAY_PUP_REQ_1 + Request Power Up sequence to start for Display + 0x1 + + + + + DVFS0CR + DVFS0 (ARM) Change request (bit is read-only) + 0x10 + 1 + read-only + + + DVFS0CR_0 + DVFS0 has no request + 0 + + + DVFS0CR_1 + DVFS0 is requesting for frequency/voltage update + 0x1 + + + + + VADC_ANALOG_OFF + Indication to VADC whether the analog power to VADC is available or not + 0x11 + 1 + read-write + + + VADC_ANALOG_OFF_0 + VADC analog power is on + 0 + + + VADC_ANALOG_OFF_1 + VADC analog power is off + 0x1 + + + + + VADC_EXT_PWD_N + VADC power down bit + 0x12 + 1 + read-write + + + VADC_EXT_PWD_N_0 + VADC power down + 0 + + + VADC_EXT_PWD_N_1 + VADC not power down + 0x1 + + + + + GPCIRQM + GPC interrupt/event masking + 0x15 + 1 + read-write + + + GPCIRQM_0 + not masked + 0 + + + GPCIRQM_1 + interrupt/event is masked + 0x1 + + + + + L2_PGE + L2 Cache Power Gate Enable + 0x16 + 1 + read-write + + + L2_PGE_0 + L2 cache will keep power on even if CPU core is power down and will not be hardware invalidated when CPU core is re-power up the reset value is 1'b1 + 0 + + + L2_PGE_1 + L2 cache power gate off request, L2 cache will be power down once when CPU core is power down and will be hardware invalidated automatically when CPU core is re-power up + 0x1 + + + + + + + PGR + GPC Power Gating Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DRCIC + Debug ref cir in mux control + 0x1D + 2 + read-write + + + DRCIC_0 + ccm_cosr_1_clk_in + 0 + + + DRCIC_1 + ccm_cosr_2_clk_in + 0x1 + + + DRCIC_2 + restricted + 0x2 + + + DRCIC_3 + restricted + 0x3 + + + + + + + IMR1 + IRQ masking register 1 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR1 + IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR2 + IRQ masking register 2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR2 + IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR3 + IRQ masking register 3 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR3 + IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR4 + IRQ masking register 4 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR4 + IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + ISR1 + IRQ status resister 1 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR1 + IRQ[63:32] status, read only + 0 + 32 + read-only + + + + + ISR2 + IRQ status resister 2 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR2 + IRQ[95:64] status, read only + 0 + 32 + read-only + + + + + ISR3 + IRQ status resister 3 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR3 + IRQ[127:96] status, read only + 0 + 32 + read-only + + + + + ISR4 + IRQ status resister 4 + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR4 + IRQ[159:128] status, read only + 0 + 32 + read-only + + + + + + + DVFSC + DVFSC + DVFSC + DVFSC_ + 0x20DC180 + + 0 + 0x44 + registers + + + + THRS + DVFS Thresholds + 0 + 32 + read-write + 0xFAF003E + 0xFFFFFFFF + + + PNCTHR + Panic threshold for load tracking + 0 + 6 + read-write + + + DWTHR + Down threshold for load tracking + 0x10 + 6 + read-write + + + UPTHR + Upper threshold for load tracking + 0x16 + 6 + read-write + + + + + COUN + DVFS Counters thresholds + 0x4 + 32 + read-write + 0x70020 + 0xFFFFFFFF + + + UPCNT + UP counter threshold value + 0 + 8 + read-write + + + DN_CNT + Down counter threshold value + 0x10 + 8 + read-write + + + + + SIG1 + DVFS general purpose bits weight + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + WSW6 + General purpose load tracking signal weight dvfs_w_sig[6] + 0x2 + 3 + read-write + + + WSW7 + General purpose load tracking signal weight dvfs_w_sig[7] + 0x5 + 3 + read-write + + + WSW8 + General purpose load tracking signal weight dvfs_w_sig[8] + 0x8 + 3 + read-write + + + WSW9 + General purpose load tracking signal weight dvfs_w_sig[9] + 0xB + 3 + read-write + + + WSW10 + General purpose load tracking signal weight dvfs_w_sig[10] + 0xE + 3 + read-write + + + WSW11 + General purpose load tracking signal weight dvfs_w_sig[11] + 0x11 + 3 + read-write + + + WSW12 + General purpose load tracking signal weight dvfs_w_sig[12] + 0x14 + 3 + read-write + + + WSW13 + General purpose load tracking signal weight dvfs_w_sig[13] + 0x17 + 3 + read-write + + + WSW14 + General purpose load tracking signal weight dvfs_w_sig[14] + 0x1A + 3 + read-write + + + WSW15 + General purpose load tracking signal weight dvfs_w_sig[15] + 0x1D + 3 + read-write + + + + + DVFSSIG0 + DVFS general purpose bits weight + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WSW0 + General purpose load tracking signal weight dvfs_w_sig[0] + 0 + 6 + read-write + + + WSW1 + General purpose load tracking signal weight dvfs_w_sig[1] + 0x6 + 6 + read-write + + + WSW2 + General purpose load tracking signal weight dvfs_w_sig[2] + 0x14 + 3 + read-write + + + WSW3 + General purpose load tracking signal weight dvfs_w_sig[3] + 0x17 + 3 + read-write + + + WSW4 + General purpose load tracking signal weight dvfs_w_sig[4] + 0x1A + 3 + read-write + + + WSW5 + General purpose load tracking signal weight dvfs_w_sig[5] + 0x1D + 3 + read-write + + + + + DVFSGPC0 + DVFS general purpose bit 0 weight counter + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPBC0 + GPBC0 - General Purpose bits Counter 0 During period of this counter the GeP bit 0 will be set and WSW0 will be added to the calculations + 0 + 17 + read-write + + + C0ACT + C0ACT - Counter 0 active indicator + 0x1E + 1 + read-only + + + C0ACT_0 + General Purpose bit0 counter reached value of "0" - the instead of WSW0, "0" (zero) is provided to DVFS calculation + 0 + + + C0ACT_1 + General Purpose bit0 counter didn't reach value of "0" - the WSW0 is provided to DVFS calculation + 0x1 + + + + + C0STRT + C0STRT - Counter 0 start Setting of this bit will initialize down counting of the GPC0 value + 0x1F + 1 + read-write + + + + + DVFSGPC1 + DVFS general purpose bit 1 weight counter + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPBC1 + GPBC1 - General Purpose bits Counter 1 During period of this counter the GeP bit 1 will be set and WSW1 will be added to the calculations + 0 + 17 + read-write + + + C1ACT + C1ACT - Counter 1 active indicator + 0x1E + 1 + read-only + + + C1ACT_0 + General Purpose bit1 counter reached value of "0" - the instead of WSW1, "0" (zero) is provided to DVFS calculation + 0 + + + C1ACT_1 + General Purpose bit1 counter didn't reach value of "0" - the WSW1 is provided to DVFS calculation + 0x1 + + + + + C1STRT + C1STRT - Counter 1start Setting of this bit will initialize down counting of the GPC1 value + 0x1F + 1 + read-write + + + + + DVFSGPBT + DVFS general purpose bits enables + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPB0 + General purpose bit 0 + 0 + 1 + read-write + + + GPB1 + General purpose bit 1 + 0x1 + 1 + read-write + + + GPB2 + General purpose bit 2. Its weight is set by WSW2 value. + 0x2 + 1 + read-write + + + GPB3 + General purpose bit 3. Its weight is set by WSW3 value. + 0x3 + 1 + read-write + + + GPB4 + General purpose bit 4. Its weight is set by WSW4 value. + 0x4 + 1 + read-write + + + GPB5 + General purpose bit 5. Its weight is set by WSW5 value. + 0x5 + 1 + read-write + + + GPB6 + General purpose bit 6. Its weight is set by WSW6 value. + 0x6 + 1 + read-write + + + GPB7 + General purpose bit 7. Its weight is set by WSW7 value. + 0x7 + 1 + read-write + + + GPB8 + General purpose bit 8. Its weight is set by WSW8 value. + 0x8 + 1 + read-write + + + GPB9 + General purpose bit 9. Its weight is set by WSW9 value. + 0x9 + 1 + read-write + + + GPB10 + General purpose bit 10. Its weight is set by WSW10 value. + 0xA + 1 + read-write + + + GPB11 + General purpose bit 11. Its weight is set by WSW11 value. + 0xB + 1 + read-write + + + GPB12 + General purpose bit 12. Its weight is set by WSW12 value. + 0xC + 1 + read-write + + + GPB13 + General purpose bit 13. Its weight is set by WSW13 value. + 0xD + 1 + read-write + + + GPB14 + General purpose bit 14. Its weight is set by WSW14 value. + 0xE + 1 + read-write + + + GPB15 + General purpose bit 15. Its weight is set by WSW15 value. + 0xF + 1 + read-write + + + + + DVFSEMAC + DVFS EMAC settings + 0x1C + 32 + read-write + 0x4 + 0xFFFFFFFF + + + EMAC + EMAC - EMA control value + 0 + 9 + read-write + + + DVFEN0 + DVFS tracking for core0 enable. + 0x9 + 1 + read-write + + + DVFEN0_0 + DVFS disabled. + 0 + + + DVFEN0_1 + DVFS enabled. + 0x1 + + + + + FSVAI0 + DVFS Frequency adjustment status of core 0 + 0x10 + 2 + read-only + + + FSVAI0_0 + no change + 0 + + + FSVAI0_1 + frequency should be increased. Low priority source for interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MAXF = 1 (highest frequency). + 0x1 + + + FSVAI0_2 + frequency should be decreased. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MINF= 1 (lowest frequency). + 0x2 + + + FSVAI0_3 + frequency should be increased immediately. High priority source of interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MAXF = 1 (highest frequency). + 0x3 + + + + + WFIM0 + DVFS Wait for Interrupt of core 0 mask bit + 0x18 + 1 + read-write + + + WFIM0_0 + Wait for interrupt of core 0 isn't masked + 0 + + + WFIM0_1 + Wait for interrupt of core 0 is masked. + 0x1 + + + + + + + CNTR + DVFS Control + 0x20 + 32 + read-write + 0x900000E + 0xFFFFFFFF + + + LTBRSR + LTBRSR - Load Tracking Buffer Register Source: + 0x3 + 2 + read-write + + + LTBRSR_0 + pre_ld_add + 0 + + + LTBRSR_1 + ld_add + 0x1 + + + LTBRSR_2 + ema_ld + 0x2 + + + + + LTBRSH + LTBRSH - Load Tracking Buffer Register Shift: + 0x5 + 1 + read-write + + + LTBRSH_0 + values of [5:2] of the selected input are saving in Load Tracking Buffer + 0 + + + LTBRSH_1 + values of [4:1] of the selected input are saving in Load Tracking Buffer + 0x1 + + + + + PFUS + PFUS - Periodic Frequency Update Status + 0x6 + 3 + read-only + + + PFUS_0 + no update + 0 + + + PFUS_4 + DVFSPT0 period, previous finished(can be performance level decrease) + 0x4 + + + PFUS_5 + DVFSPT1 period, previous finished(can be EMA-detected performance level) + 0x5 + + + PFUS_6 + DVFSPT2 period, previous finished(can be performance level increase) + 0x6 + + + PFUS_7 + DVFSPT3 period, previous finished (can be EMA-detected performance level) + 0x7 + + + + + PFUE + PFUE - Period Frequency Update Enable + 0x9 + 1 + read-write + + + PFUE_0 + disabled + 0 + + + PFUE_1 + enabled + 0x1 + + + + + DIV_RATIO + DIV_RATIO - Divider value. Divider divides the input ARM clock, following the table + 0xB + 6 + read-write + + + MINF + Minimum frequency reached + 0x11 + 1 + read-write + + + MINF_0 + min frequency not reached + 0 + + + MINF_1 + min frequency reached + 0x1 + + + + + MAXF + Maximum frequency reached + 0x12 + 1 + read-write + + + MAXF_0 + max frequency not reached + 0 + + + MAXF_1 + max frequency reached + 0x1 + + + + + FSVAI + FSVAI DVFS Frequency adjustment interrupt + 0x14 + 2 + read-only + + + FSVAI_0 + no interrupt + 0 + + + FSVAI_1 + frequency should be increased. Low priority interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MAXF = 1 (highest frequency). + 0x1 + + + FSVAI_2 + frequency should be decreased. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MINF= 1 (lowest frequency). + 0x2 + + + FSVAI_3 + frequency should be increased immediately. High priority interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MAXF = 1 (highest frequency). + 0x3 + + + + + FSVAIM + DVFS Frequency adjustment interrupt mask + 0x16 + 1 + read-write + + + FSVAIM_0 + interrupt is enabled. + 0 + + + FSVAIM_1 + interrupt is masked. + 0x1 + + + + + PIRQS + PIRQS - Pattern IRQ Source * write '1' to clear + 0x17 + 1 + read-write + + + PIRQS_0 + DVFS IRQ source was not from pattern + 0 + + + PIRQS_1 + DVFS IRQ source was from pattern + 0x1 + + + + + DVFIS + DVFS Interrupt select. These bits define destination of DVFS interrupts. + 0x18 + 1 + read-write + + + DVFIS_0 + SDMA interrupt will be generated for DVFS events. + 0 + + + DVFIS_1 + MCU interrupt will be generated for DVFS events. + 0x1 + + + + + LBFL0 + Load buffer 0 - full status bit + 0x19 + 1 + read-write + + + LBFL0_0 + Load buffer1 is not full. + 0 + + + LBFL0_1 + Load buffer1 is full. + 0x1 + + + + + LBFL1 + Load buffer 1 - full status bit + 0x1A + 1 + read-write + + + LBFL1_0 + Load buffer0 is not full. + 0 + + + LBFL1_1 + Load buffer0 is full. + 0x1 + + + + + LBMI + Load buffer full mask interrupt + 0x1B + 1 + read-write + + + DVFEV + Always give a DVFS event. + 0x1C + 1 + read-write + + + DVFEV_0 + Do not give an event always. + 0 + + + DVFEV_1 + Always give event. + 0x1 + + + + + DIV3CK + DIV3CK - div_3_clk division ratio inside the DVFS module. According to the + 0x1D + 3 + read-write + + + + + DVFSLTR0_0 + DVFS Load Tracking Register 0, portion 0 + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTS0_0 + core 0 Load Tracking Sample 0 + 0 + 4 + read-only + + + LTS0_1 + core 0 Load Tracking Sample 1 + 0x4 + 4 + read-only + + + LTS0_2 + core 0 Load Tracking Sample 2 + 0x8 + 4 + read-only + + + LTS0_3 + core 0 Load Tracking Sample 3 + 0xC + 4 + read-only + + + LTS0_4 + core 0 Load Tracking Sample 4 + 0x10 + 4 + read-only + + + LTS0_5 + core 0 Load Tracking Sample 5 + 0x14 + 4 + read-only + + + LTS0_6 + core 0 Load Tracking Sample 6 + 0x18 + 4 + read-only + + + LTS0_7 + core 0 Load Tracking Sample 7 + 0x1C + 4 + read-only + + + + + DVFSLTR0_1 + DVFS Load Tracking Register 0, portion 1 + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTS0_8 + core 0 Load Tracking Sample 8 + 0 + 4 + read-only + + + LTS0_9 + core 0 Load Tracking Sample 9 + 0x4 + 4 + read-only + + + LTS0_10 + core 0 Load Tracking Sample 10 + 0x8 + 4 + read-only + + + LTS0_11 + core 0 Load Tracking Sample 11 + 0xC + 4 + read-only + + + LTS0_12 + core 0 Load Tracking Sample 12 + 0x10 + 4 + read-only + + + LTS0_13 + core 0 Load Tracking Sample 13 + 0x14 + 4 + read-only + + + LTS0_14 + core 0 Load Tracking Sample 14 + 0x18 + 4 + read-only + + + LTS0_15 + core 0 Load Tracking Sample 15 + 0x1C + 4 + read-only + + + + + DVFSLTR1_0 + DVFS Load Tracking Register 1, portion 0 + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + LTS1_0 + core 0 Load Tracking Sample 0 + 0 + 4 + read-only + + + LTS1_1 + core 0 Load Tracking Sample 1 + 0x4 + 4 + read-only + + + LTS1_2 + core 0 Load Tracking Sample 2 + 0x8 + 4 + read-only + + + LTS1_3 + core 0 Load Tracking Sample 3 + 0xC + 4 + read-only + + + LTS1_4 + core 0 Load Tracking Sample 4 + 0x10 + 4 + read-only + + + LTS1_5 + core 0 Load Tracking Sample 5 + 0x14 + 4 + read-only + + + LTS1_6 + core 0 Load Tracking Sample 6 + 0x18 + 4 + read-only + + + LTS1_7 + core 0 Load Tracking Sample 7 + 0x1C + 4 + read-only + + + + + DVFSLTR1_1 + DVFS Load Tracking Register 3, portion 1 + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTS1_8 + core 0 Load Tracking Sample 8 + 0 + 4 + read-only + + + LTS1_9 + core 0 Load Tracking Sample 9 + 0x4 + 4 + read-only + + + LTS1_10 + core 0 Load Tracking Sample 10 + 0x8 + 4 + read-only + + + LTS1_11 + core 0 Load Tracking Sample 11 + 0xC + 4 + read-only + + + LTS1_12 + core 0 Load Tracking Sample 12 + 0x10 + 4 + read-only + + + LTS1_13 + core 0 Load Tracking Sample 13 + 0x14 + 4 + read-only + + + LTS1_14 + core 0 Load Tracking Sample 14 + 0x18 + 4 + read-only + + + LTS1_15 + core 0 Load Tracking Sample 15 + 0x1C + 4 + read-only + + + + + DVFSPT0 + DVFS pattern 0 length + 0x34 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + FPTN0 + FPTN0 - Frequency pattern 0 counter During period of this counter the frequency will be reduced from the EMA-detected level + 0 + 17 + read-write + + + PT0A + PT0A - Pattern 0 currently active (read-only) + 0x11 + 1 + read-only + + + PT0A_0 + non-active + 0 + + + PT0A_1 + active + 0x1 + + + + + + + DVFSPT1 + DVFS pattern 1 length + 0x38 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + FPTN1 + FPTN1 - Frequency pattern 1 counter During period of this counter the frequency will be set to the EMA-detected level + 0 + 17 + read-write + + + PT1A + PT1A - Pattern 1 currently active (read-only) + 0x11 + 1 + read-only + + + PT1A_0 + non-active + 0 + + + PT1A_1 + active + 0x1 + + + + + + + DVFSPT2 + DVFS pattern 2 length + 0x3C + 32 + read-write + 0x10 + 0xFFFFFFFF + + + FPTN2 + FPTN2 - Frequency pattern 2 counter During period of this counter the frequency will be increased to higher, than detected by the EMA-detected level + 0 + 17 + read-write + + + PT2A + PT2A - Pattern 2 currently active (read-only) + 0x11 + 1 + read-only + + + PT2A_0 + non-active + 0 + + + PT2A_1 + active + 0x1 + + + + + P2THR + P2THR - Pattern 2 Threshold Threshold of current DVFS load (after EMA), for generating interrupts with PFUS indicators 110, 111 + 0x1A + 6 + read-write + + + + + DVFSPT3 + DVFS pattern 3 length + 0x40 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + FPTN3 + FPTN3 - Frequency pattern 3 counter During period of this counter the frequency will be set to the EMA-detected level + 0 + 17 + read-write + + + PT3A + PT3A - Pattern 3 currently active (read-only) + 0x11 + 1 + read-only + + + PT3A_0 + non-active + 0 + + + PT3A_1 + active + 0x1 + + + + + + + + + PGC + PGC + PGC + PGC_ + 0x20DC220 + + 0 + 0x90 + registers + + + + MEGA_CTRL + PGC Mega Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCR + Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + + + MEGA_PUPSCR + PGC Mega Power Up Sequence Control Register + 0x4 + 32 + read-write + 0xF01 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b) + 0 + 6 + read-write + + + SW2ISO + After asserting power toggle on/off signal (switch_b), the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation + 0x8 + 6 + read-write + + + + + MEGA_PDNSCR + PGC Mega Pull Down Sequence Control Register + 0x8 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISO + After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation + 0 + 6 + read-write + + + ISO2SW + After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b) + 0x8 + 6 + read-write + + + + + MEGA_SR + PGC Mega Power Gating Controller Status Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-write + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + + + CPU_CTRL + PGC CPU Control Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCR + Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + + + CPU_PUPSCR + PGC CPU Power Up Sequence Control Register + 0x84 + 32 + read-write + 0xF01 + 0xFFFFFFFF + + + SW + There are two different silicon revisions: 1 + 0 + 6 + read-write + + + SW2ISO + There are two different silicon revisions: 1 + 0x8 + 6 + read-write + + + + + CPU_PDNSCR + PGC CPU Pull Down Sequence Control Register + 0x88 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISO + After a power-down request (pdn_req assertion), the PGC waits a number of 32k clocks equal to the value of ISO before asserting isolation + 0 + 6 + read-write + + + ISO2SW + After asserting isolation, the PGC waits a number of 32k clocks equal to the value of ISO2SW before negating + 0x8 + 6 + read-write + + + + + CPU_SR + PGC CPU Power Gating Controller Status Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-write + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + + + + + IOMUXC + IOMUXC + IOMUXC + IOMUXC_ + 0x20E0000 + + 0 + 0x6A0 + registers + + + + SW_MUX_CTL_PAD_JTAG_MOD + SW_MUX_CTL_PAD_JTAG_MOD SW MUX Control Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SJC_MOD of instance: sjc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CLK of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SPDIF_OUT of instance: spdif + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET1_REF_CLK_25M of instance: enet1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CCM_PMIC_RDY of instance: ccm + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO10 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SDMA_EXT_EVENT00 of instance: sdma + 0x6 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad JTAG_MOD + 0x1 + + + + + + + SW_MUX_CTL_PAD_JTAG_TMS + SW_MUX_CTL_PAD_JTAG_TMS SW MUX Control Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SJC_TMS of instance: sjc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CAPTURE1 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_MCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CCM_CLKO1 of instance: ccm + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CCM_WAIT of instance: ccm + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO11 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SDMA_EXT_EVENT01 of instance: sdma + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: EPIT1_OUT of instance: epit1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad JTAG_TMS + 0x1 + + + + + + + SW_MUX_CTL_PAD_JTAG_TDO + SW_MUX_CTL_PAD_JTAG_TDO SW MUX Control Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SJC_TDO of instance: sjc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CAPTURE2 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_SYNC of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CCM_CLKO2 of instance: ccm + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CCM_STOP of instance: ccm + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: MQS_RIGHT of instance: mqs + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: EPIT2_OUT of instance: epit2 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad JTAG_TDO + 0x1 + + + + + + + SW_MUX_CTL_PAD_JTAG_TDI + SW_MUX_CTL_PAD_JTAG_TDI SW MUX Control Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SJC_TDI of instance: sjc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE1 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_BCLK of instance: sai2 + 0x2 + + + ALT4 + Select mux mode: ALT4 mux port: PWM6_OUT of instance: pwm6 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO13 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: MQS_LEFT of instance: mqs + 0x6 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad JTAG_TDI + 0x1 + + + + + + + SW_MUX_CTL_PAD_JTAG_TCK + SW_MUX_CTL_PAD_JTAG_TCK SW MUX Control Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SJC_TCK of instance: sjc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE2 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_DATA of instance: sai2 + 0x2 + + + ALT4 + Select mux mode: ALT4 mux port: PWM7_OUT of instance: pwm7 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO14 of instance: gpio1 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad JTAG_TCK + 0x1 + + + + + + + SW_MUX_CTL_PAD_JTAG_TRST_B + SW_MUX_CTL_PAD_JTAG_TRST_B SW MUX Control Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SJC_TRSTB of instance: sjc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE3 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_DATA of instance: sai2 + 0x2 + + + ALT4 + Select mux mode: ALT4 mux port: PWM8_OUT of instance: pwm8 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO15 of instance: gpio1 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad JTAG_TRST_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO00 + SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register + 0x5C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: I2C2_SCL of instance: i2c2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT1_CAPTURE1 of instance: gpt1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ANATOP_OTG1_ID of instance: anatop + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET1_REF_CLK1 of instance: enet1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: MQS_RIGHT of instance: mqs + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO00 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET1_1588_EVENT0_IN of instance: enet1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: SRC_SYSTEM_RESET of instance: src + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: WDOG3_WDOG_B of instance: wdog3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO01 + SW_MUX_CTL_PAD_GPIO1_IO01 SW MUX Control Register + 0x60 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: I2C2_SDA of instance: i2c2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT1_COMPARE1 of instance: gpt1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USB_OTG1_OC of instance: usb + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET2_REF_CLK2 of instance: enet2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: MQS_LEFT of instance: mqs + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO01 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET1_1588_EVENT0_OUT of instance: enet1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: SRC_EARLY_RESET of instance: src + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: WDOG1_WDOG_B of instance: wdog1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO02 + SW_MUX_CTL_PAD_GPIO1_IO02 SW MUX Control Register + 0x64 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: I2C1_SCL of instance: i2c1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT1_COMPARE2 of instance: gpt1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USB_OTG2_PWR of instance: usb + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET1_REF_CLK_25M of instance: enet1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC1_WP of instance: usdhc1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO02 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SDMA_EXT_EVENT00 of instance: sdma + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: SRC_ANY_PU_RESET of instance: src + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: UART1_TX of instance: uart1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO03 + SW_MUX_CTL_PAD_GPIO1_IO03 SW MUX Control Register + 0x68 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: I2C1_SDA of instance: i2c1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT1_COMPARE3 of instance: gpt1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USB_OTG2_OC of instance: usb + 0x2 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC1_CD_B of instance: usdhc1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO03 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_DI0_EXT_CLK of instance: ccm + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: SRC_TESTER_ACK of instance: src ALT7 mode will be automatically active when system reset. The PAD setting will be 100 K pull down and input enable during reset period. Once system reset is completed, the state of GPIO1_IO03 will be output keeper and input enable. + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: UART1_RX of instance: uart1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO04 + SW_MUX_CTL_PAD_GPIO1_IO04 SW MUX Control Register + 0x6C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_REF_CLK1 of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM3_OUT of instance: pwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USB_OTG1_PWR of instance: usb + 0x2 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO04 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET2_1588_EVENT0_IN of instance: enet2 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_TX of instance: uart5 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO05 + SW_MUX_CTL_PAD_GPIO1_IO05 SW MUX Control Register + 0x70 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_REF_CLK2 of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM4_OUT of instance: pwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ANATOP_OTG2_ID of instance: anatop + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_FIELD of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO05 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET2_1588_EVENT0_OUT of instance: enet2 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_RX of instance: uart5 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO06 + SW_MUX_CTL_PAD_GPIO1_IO06 SW MUX Control Register + 0x74 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_MDIO of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_MDIO of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USB_OTG_PWR_WAKE of instance: usb + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_MCLK of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC2_WP of instance: usdhc2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO06 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_WAIT of instance: ccm + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: CCM_REF_EN_B of instance: ccm + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: UART1_CTS_B of instance: uart1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO07 + SW_MUX_CTL_PAD_GPIO1_IO07 SW MUX Control Register + 0x78 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_MDC of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_MDC of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USB_OTG_HOST_MODE of instance: usb + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_PIXCLK of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC2_CD_B of instance: usdhc2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO07 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_STOP of instance: ccm + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART1_RTS_B of instance: uart1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO08 + SW_MUX_CTL_PAD_GPIO1_IO08 SW MUX Control Register + 0x7C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: PWM1_OUT of instance: pwm1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: WDOG1_WDOG_B of instance: wdog1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SPDIF_OUT of instance: spdif + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_VSYNC of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC2_VSELECT of instance: usdhc2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO08 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_PMIC_RDY of instance: ccm + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_RTS_B of instance: uart5 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO1_IO09 + SW_MUX_CTL_PAD_GPIO1_IO09 SW MUX Control Register + 0x80 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: PWM2_OUT of instance: pwm2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: WDOG1_WDOG_ANY of instance: wdog1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SPDIF_IN of instance: spdif + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_HSYNC of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO09 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_CTS_B of instance: uart5 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO1_IO09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART1_TX_DATA + SW_MUX_CTL_PAD_UART1_TX_DATA SW MUX Control Register + 0x84 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART1_TX of instance: uart1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_RDATA02 of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C3_SCL of instance: i2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA02 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_COMPARE1 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO16 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: SPDIF_OUT of instance: spdif + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: UART5_TX of instance: uart5 + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART1_TX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART1_RX_DATA + SW_MUX_CTL_PAD_UART1_RX_DATA SW MUX Control Register + 0x88 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART1_RX of instance: uart1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_RDATA03 of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C3_SDA of instance: i2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA03 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_CLK of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO17 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: SPDIF_IN of instance: spdif + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: UART5_RX of instance: uart5 + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART1_RX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART1_CTS_B + SW_MUX_CTL_PAD_UART1_CTS_B SW MUX Control Register + 0x8C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART1_CTS_B of instance: uart1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_RX_CLK of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USDHC1_WP of instance: usdhc1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA04 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET2_1588_EVENT1_IN of instance: enet2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO18 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_WP of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: UART5_CTS_B of instance: uart5 + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART1_CTS_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART1_RTS_B + SW_MUX_CTL_PAD_UART1_RTS_B SW MUX Control Register + 0x90 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART1_RTS_B of instance: uart1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_TX_ER of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USDHC1_CD_B of instance: usdhc1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA05 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET2_1588_EVENT1_OUT of instance: enet2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO19 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_CD_B of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: UART5_RTS_B of instance: uart5 + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART1_RTS_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART2_TX_DATA + SW_MUX_CTL_PAD_UART2_TX_DATA SW MUX Control Register + 0x94 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART2_TX of instance: uart2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_TDATA02 of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C4_SCL of instance: i2c4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA06 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_CAPTURE1 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO20 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_SS0 of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART2_TX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART2_RX_DATA + SW_MUX_CTL_PAD_UART2_RX_DATA SW MUX Control Register + 0x98 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART2_RX of instance: uart2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_TDATA03 of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C4_SDA of instance: i2c4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA07 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_CAPTURE2 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO21 of instance: gpio1 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: SJC_DONE of instance: sjc + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_SCLK of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART2_RX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART2_CTS_B + SW_MUX_CTL_PAD_UART2_CTS_B SW MUX Control Register + 0x9C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART2_CTS_B of instance: uart2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_CRS of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA08 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_COMPARE2 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO22 of instance: gpio1 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: SJC_DE_B of instance: sjc + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_MOSI of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART2_CTS_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART2_RTS_B + SW_MUX_CTL_PAD_UART2_RTS_B SW MUX Control Register + 0xA0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART2_RTS_B of instance: uart2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET1_COL of instance: enet1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA09 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_COMPARE3 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO23 of instance: gpio1 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: SJC_FAIL of instance: sjc + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_MISO of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART2_RTS_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART3_TX_DATA + SW_MUX_CTL_PAD_UART3_TX_DATA SW MUX Control Register + 0xA4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART3_TX of instance: uart3 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_RDATA02 of instance: enet2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA01 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: UART2_CTS_B of instance: uart2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO24 of instance: gpio1 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: SJC_JTAG_ACT of instance: sjc ALT7 mode will be automatically active (output SJC.SJC_JTAG_ACT) when system reset. Once system reset is completed, the state of UART3_TX_DATA will be output keeper and input enenable. + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ANATOP_OTG1_ID of instance: anatop + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART3_TX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART3_RX_DATA + SW_MUX_CTL_PAD_UART3_RX_DATA SW MUX Control Register + 0xA8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART3_RX of instance: uart3 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_RDATA03 of instance: enet2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA00 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: UART2_RTS_B of instance: uart2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO25 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: EPIT1_OUT of instance: epit1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART3_RX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART3_CTS_B + SW_MUX_CTL_PAD_UART3_CTS_B SW MUX Control Register + 0xAC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART3_CTS_B of instance: uart3 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_RX_CLK of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA10 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET1_1588_EVENT1_IN of instance: enet1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO26 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: EPIT2_OUT of instance: epit2 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART3_CTS_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART3_RTS_B + SW_MUX_CTL_PAD_UART3_RTS_B SW MUX Control Register + 0xB0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART3_RTS_B of instance: uart3 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_TX_ER of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA11 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET1_1588_EVENT1_OUT of instance: enet1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO27 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: WDOG1_WDOG_B of instance: wdog1 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART3_RTS_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART4_TX_DATA + SW_MUX_CTL_PAD_UART4_TX_DATA SW MUX Control Register + 0xB4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART4_TX of instance: uart4 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_TDATA02 of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C1_SCL of instance: i2c1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA12 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSU_CSU_ALARM_AUT02 of instance: csu + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO28 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_SCLK of instance: ecspi2 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART4_TX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART4_RX_DATA + SW_MUX_CTL_PAD_UART4_RX_DATA SW MUX Control Register + 0xB8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART4_RX of instance: uart4 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_TDATA03 of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C1_SDA of instance: i2c1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA13 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSU_CSU_ALARM_AUT01 of instance: csu + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO29 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_SS0 of instance: ecspi2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRCTRL01 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART4_RX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART5_TX_DATA + SW_MUX_CTL_PAD_UART5_TX_DATA SW MUX Control Register + 0xBC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART5_TX of instance: uart5 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_CRS of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C2_SCL of instance: i2c2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA14 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSU_CSU_ALARM_AUT00 of instance: csu + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO30 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_MOSI of instance: ecspi2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRCTRL02 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART5_TX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_UART5_RX_DATA + SW_MUX_CTL_PAD_UART5_RX_DATA SW MUX Control Register + 0xC0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: UART5_RX of instance: uart5 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET2_COL of instance: enet2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: I2C2_SDA of instance: i2c2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA15 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSU_CSU_INT_DEB of instance: csu + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO31 of instance: gpio1 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_MISO of instance: ecspi2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRCTRL03 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad UART5_RX_DATA + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_RX_DATA0 + SW_MUX_CTL_PAD_ENET1_RX_DATA0 SW MUX Control Register + 0xC4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_RDATA00 of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART4_RTS_B of instance: uart4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: PWM1_OUT of instance: pwm1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA16 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO00 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW00 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC1_LCTL of instance: usdhc1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE04 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_RX_DATA0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_RX_DATA1 + SW_MUX_CTL_PAD_ENET1_RX_DATA1 SW MUX Control Register + 0xC8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_RDATA01 of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART4_CTS_B of instance: uart4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: PWM2_OUT of instance: pwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA17 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO01 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL00 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_LCTL of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE05 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_RX_DATA1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_RX_EN + SW_MUX_CTL_PAD_ENET1_RX_EN SW MUX Control Register + 0xCC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_RX_EN of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART5_RTS_B of instance: uart5 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA18 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO02 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW01 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE06 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_RX_EN + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_TX_DATA0 + SW_MUX_CTL_PAD_ENET1_TX_DATA0 SW MUX Control Register + 0xD0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_TDATA00 of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART5_CTS_B of instance: uart5 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA19 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO03 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL01 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_VSELECT of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE07 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_TX_DATA0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_TX_DATA1 + SW_MUX_CTL_PAD_ENET1_TX_DATA1 SW MUX Control Register + 0xD4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_TDATA01 of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART6_CTS_B of instance: uart6 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: PWM5_OUT of instance: pwm5 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA20 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET2_MDIO of instance: enet2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW02 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: WDOG1_WDOG_RST_B_DEB of instance: wdog1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE08 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_TX_DATA1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_TX_EN + SW_MUX_CTL_PAD_ENET1_TX_EN SW MUX Control Register + 0xD8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_TX_EN of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART6_RTS_B of instance: uart6 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: PWM6_OUT of instance: pwm6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA21 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET2_MDC of instance: enet2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL02 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: WDOG2_WDOG_RST_B_DEB of instance: wdog2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE09 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_TX_EN + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_TX_CLK + SW_MUX_CTL_PAD_ENET1_TX_CLK SW MUX Control Register + 0xDC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_TX_CLK of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_CTS_B of instance: uart7 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: PWM7_OUT of instance: pwm7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA22 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET1_REF_CLK1 of instance: enet1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO06 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW03 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: GPT1_CLK of instance: gpt1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDOED of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_TX_CLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET1_RX_ER + SW_MUX_CTL_PAD_ENET1_RX_ER SW MUX Control Register + 0xE0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET1_RX_ER of instance: enet1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_RTS_B of instance: uart7 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: PWM8_OUT of instance: pwm8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA23 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_CRE of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL03 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: GPT1_CAPTURE2 of instance: gpt1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDOEZ of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET1_RX_ER + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_RX_DATA0 + SW_MUX_CTL_PAD_ENET2_RX_DATA0 SW MUX Control Register + 0xE4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_RDATA00 of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART6_TX of instance: uart6 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: I2C3_SCL of instance: i2c3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET1_MDIO of instance: enet1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO08 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW04 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG1_PWR of instance: usb + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO08 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_RX_DATA0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_RX_DATA1 + SW_MUX_CTL_PAD_ENET2_RX_DATA1 SW MUX Control Register + 0xE8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_RDATA01 of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART6_RX of instance: uart6 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: I2C3_SDA of instance: i2c3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET1_MDC of instance: enet1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO09 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL04 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG1_OC of instance: usb + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO09 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_RX_DATA1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_RX_EN + SW_MUX_CTL_PAD_ENET2_RX_EN SW MUX Control Register + 0xEC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_RX_EN of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_TX of instance: uart7 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: I2C4_SCL of instance: i2c4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR26 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO10 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW05 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET1_REF_CLK_25M of instance: enet1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO10 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_RX_EN + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_TX_DATA0 + SW_MUX_CTL_PAD_ENET2_TX_DATA0 SW MUX Control Register + 0xF0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_TDATA00 of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_RX of instance: uart7 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: I2C4_SDA of instance: i2c4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_EB_B02 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO11 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL05 of instance: kpp + 0x6 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO11 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_TX_DATA0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_TX_DATA1 + SW_MUX_CTL_PAD_ENET2_TX_DATA1 SW MUX Control Register + 0xF4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_TDATA01 of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_TX of instance: uart8 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_SCLK of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_EB_B03 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO12 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW06 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG2_PWR of instance: usb + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO12 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_TX_DATA1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_TX_EN + SW_MUX_CTL_PAD_ENET2_TX_EN SW MUX Control Register + 0xF8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_TX_EN of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_RX of instance: uart8 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_MOSI of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ACLK_FREERUN of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO13 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL06 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG2_OC of instance: usb + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO13 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_TX_EN + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_TX_CLK + SW_MUX_CTL_PAD_ENET2_TX_CLK SW MUX Control Register + 0xFC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_TX_CLK of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_CTS_B of instance: uart8 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_MISO of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET2_REF_CLK2 of instance: enet2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO14 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_ROW07 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ANATOP_OTG2_ID of instance: anatop + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO14 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_TX_CLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_ENET2_RX_ER + SW_MUX_CTL_PAD_ENET2_RX_ER SW MUX Control Register + 0x100 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET2_RX_ER of instance: enet2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_RTS_B of instance: uart8 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_SS0 of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR25 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO15 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: KPP_COL07 of instance: kpp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: WDOG1_WDOG_ANY of instance: wdog1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO15 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad ENET2_RX_ER + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_CLK + SW_MUX_CTL_PAD_LCD_CLK SW MUX Control Register + 0x104 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_CLK of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LCDIF_WR_RWN of instance: lcdif + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: UART4_TX of instance: uart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_MCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_CS2_B of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO00 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: WDOG1_WDOG_RST_B_DEB of instance: wdog1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCLK of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_CLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_ENABLE + SW_MUX_CTL_PAD_LCD_ENABLE SW MUX Control Register + 0x108 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_ENABLE of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LCDIF_RD_E of instance: lcdif + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: UART4_RX of instance: uart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_SYNC of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_CS3_B of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO01 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_RDY of instance: ecspi2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDLE of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_ENABLE + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_HSYNC + SW_MUX_CTL_PAD_LCD_HSYNC SW MUX Control Register + 0x10C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_HSYNC of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LCDIF_RS of instance: lcdif + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: UART4_CTS_B of instance: uart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_BCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: WDOG3_WDOG_RST_B_DEB of instance: wdog3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO02 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_SS1 of instance: ecspi2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDOE of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_HSYNC + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_VSYNC + SW_MUX_CTL_PAD_LCD_VSYNC SW MUX Control Register + 0x110 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_VSYNC of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LCDIF_BUSY of instance: lcdif + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: UART4_RTS_B of instance: uart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_RX_DATA of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: WDOG2_WDOG_B of instance: wdog2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO03 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_SS2 of instance: ecspi2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE00 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_VSYNC + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_RESET + SW_MUX_CTL_PAD_LCD_RESET SW MUX Control Register + 0x114 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_RESET of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LCDIF_CS of instance: lcdif + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CA7_MX6ULL_EVENTI of instance: ca7_mx6ull + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_DATA of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: WDOG1_WDOG_ANY of instance: wdog1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO04 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI2_SS3 of instance: ecspi2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_GDOE of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_RESET + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA00 + SW_MUX_CTL_PAD_LCD_DATA00 SW MUX Control Register + 0x118 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA00 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM1_OUT of instance: pwm1 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET1_1588_EVENT2_IN of instance: enet1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: I2C3_SDA of instance: i2c3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO05 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG00 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SAI1_MCLK of instance: sai1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO00 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA01 + SW_MUX_CTL_PAD_LCD_DATA01 SW MUX Control Register + 0x11C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA01 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM2_OUT of instance: pwm2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET1_1588_EVENT2_OUT of instance: enet1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: I2C3_SCL of instance: i2c3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO06 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG01 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SAI1_TX_SYNC of instance: sai1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO01 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA02 + SW_MUX_CTL_PAD_LCD_DATA02 SW MUX Control Register + 0x120 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA02 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM3_OUT of instance: pwm3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET1_1588_EVENT3_IN of instance: enet1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: I2C4_SDA of instance: i2c4 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO07 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG02 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SAI1_TX_BCLK of instance: sai1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO02 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA03 + SW_MUX_CTL_PAD_LCD_DATA03 SW MUX Control Register + 0x124 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA03 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM4_OUT of instance: pwm4 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET1_1588_EVENT3_OUT of instance: enet1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: I2C4_SCL of instance: i2c4 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO08 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG03 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SAI1_RX_DATA of instance: sai1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO03 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA04 + SW_MUX_CTL_PAD_LCD_DATA04 SW MUX Control Register + 0x128 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA04 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_CTS_B of instance: uart8 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET2_1588_EVENT2_IN of instance: enet2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: SPDIF_SR_CLK of instance: spdif + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO09 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG04 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SAI1_TX_DATA of instance: sai1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO04 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA05 + SW_MUX_CTL_PAD_LCD_DATA05 SW MUX Control Register + 0x12C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA05 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_RTS_B of instance: uart8 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET2_1588_EVENT2_OUT of instance: enet2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: SPDIF_OUT of instance: spdif + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO10 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG05 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI1_SS1 of instance: ecspi1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO05 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA06 + SW_MUX_CTL_PAD_LCD_DATA06 SW MUX Control Register + 0x130 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA06 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_CTS_B of instance: uart7 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET2_1588_EVENT3_IN of instance: enet2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: SPDIF_LOCK of instance: spdif + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO11 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG06 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI1_SS2 of instance: ecspi1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO06 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA07 + SW_MUX_CTL_PAD_LCD_DATA07 SW MUX Control Register + 0x134 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA07 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_RTS_B of instance: uart7 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ENET2_1588_EVENT3_OUT of instance: enet2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: SPDIF_EXT_CLK of instance: spdif + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO12 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG07 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI1_SS3 of instance: ecspi1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDDO07 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA08 + SW_MUX_CTL_PAD_LCD_DATA08 SW MUX Control Register + 0x138 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA08 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SPDIF_IN of instance: spdif + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA16 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA00 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO13 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG08 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRIRQ of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA09 + SW_MUX_CTL_PAD_LCD_DATA09 SW MUX Control Register + 0x13C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA09 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SAI3_MCLK of instance: sai3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA17 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA01 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO14 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG09 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRWAKE of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA10 + SW_MUX_CTL_PAD_LCD_DATA10 SW MUX Control Register + 0x140 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA10 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SAI3_RX_SYNC of instance: sai3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA18 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA02 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO15 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG10 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRCOM of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA11 + SW_MUX_CTL_PAD_LCD_DATA11 SW MUX Control Register + 0x144 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA11 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SAI3_RX_BCLK of instance: sai3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA19 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA03 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO16 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG11 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRSTAT of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA12 + SW_MUX_CTL_PAD_LCD_DATA12 SW MUX Control Register + 0x148 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA12 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SAI3_TX_SYNC of instance: sai3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA20 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA04 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO17 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG12 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI1_RDY of instance: ecspi1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_PWRCTRL00 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA13 + SW_MUX_CTL_PAD_LCD_DATA13 SW MUX Control Register + 0x14C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA13 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SAI3_TX_BCLK of instance: sai3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA21 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA05 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO18 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG13 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_BDR00 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA14 + SW_MUX_CTL_PAD_LCD_DATA14 SW MUX Control Register + 0x150 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA14 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SAI3_RX_DATA of instance: sai3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA22 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA06 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO19 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG14 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA4 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDSHR of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA15 + SW_MUX_CTL_PAD_LCD_DATA15 SW MUX Control Register + 0x154 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA15 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: SAI3_TX_DATA of instance: sai3 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA23 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA07 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO20 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG15 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA5 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_GDRL of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA16 + SW_MUX_CTL_PAD_LCD_DATA16 SW MUX Control Register + 0x158 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA16 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_TX of instance: uart7 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA01 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA08 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO21 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG24 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA6 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_GDCLK of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA16 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA17 + SW_MUX_CTL_PAD_LCD_DATA17 SW MUX Control Register + 0x15C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA17 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART7_RX of instance: uart7 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA00 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA09 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO22 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG25 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA7 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_GDSP of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA17 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA18 + SW_MUX_CTL_PAD_LCD_DATA18 SW MUX Control Register + 0x160 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA18 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM5_OUT of instance: pwm5 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CA7_MX6ULL_EVENTO of instance: ca7_mx6ull + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA10 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA10 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO23 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG26 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_CMD of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_BDR01 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA18 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA19 + SW_MUX_CTL_PAD_LCD_DATA19 SW MUX Control Register + 0x164 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA19 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: PWM6_OUT of instance: pwm6 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: WDOG1_WDOG_ANY of instance: wdog1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA11 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA11 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO24 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG27 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_CLK of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_VCOM00 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA19 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA20 + SW_MUX_CTL_PAD_LCD_DATA20 SW MUX Control Register + 0x168 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA20 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_TX of instance: uart8 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ECSPI1_SCLK of instance: ecspi1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA12 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA12 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO25 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG28 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA0 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_VCOM01 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA20 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA21 + SW_MUX_CTL_PAD_LCD_DATA21 SW MUX Control Register + 0x16C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA21 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: UART8_RX of instance: uart8 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ECSPI1_SS0 of instance: ecspi1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA13 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA13 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO26 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG29 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA1 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE01 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA21 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA22 + SW_MUX_CTL_PAD_LCD_DATA22 SW MUX Control Register + 0x170 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA22 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: MQS_RIGHT of instance: mqs + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ECSPI1_MOSI of instance: ecspi1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA14 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA14 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO27 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG30 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA2 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE02 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA22 + 0x1 + + + + + + + SW_MUX_CTL_PAD_LCD_DATA23 + SW_MUX_CTL_PAD_LCD_DATA23 SW MUX Control Register + 0x174 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCDIF_DATA23 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: MQS_LEFT of instance: mqs + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ECSPI1_MISO of instance: ecspi1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CSI_DATA15 of instance: csi + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DATA15 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO28 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG31 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC2_DATA3 of instance: usdhc2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: EPDC_SDCE03 of instance: epdc + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad LCD_DATA23 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_RE_B + SW_MUX_CTL_PAD_NAND_RE_B SW MUX Control Register + 0x178 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_RE_B of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_CLK of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_SCLK of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_ROW00 of instance: kpp + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_EB_B00 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO00 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_SS2 of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_RE_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_WE_B + SW_MUX_CTL_PAD_NAND_WE_B SW MUX Control Register + 0x17C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_WE_B of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_CMD of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_SS0_B of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_COL00 of instance: kpp + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_EB_B01 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO01 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_SS3 of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_WE_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA00 + SW_MUX_CTL_PAD_NAND_DATA00 SW MUX Control Register + 0x180 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA00 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA0 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_SS1_B of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_ROW01 of instance: kpp + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD08 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO02 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI4_RDY of instance: ecspi4 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA01 + SW_MUX_CTL_PAD_NAND_DATA01 SW MUX Control Register + 0x184 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA01 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA1 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_DQS of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_COL01 of instance: kpp + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD09 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO03 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI4_SS1 of instance: ecspi4 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA02 + SW_MUX_CTL_PAD_NAND_DATA02 SW MUX Control Register + 0x188 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA02 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA2 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_DATA00 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_ROW02 of instance: kpp + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD10 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO04 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI4_SS2 of instance: ecspi4 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA03 + SW_MUX_CTL_PAD_NAND_DATA03 SW MUX Control Register + 0x18C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA03 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA3 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_DATA01 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_COL02 of instance: kpp + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD11 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO05 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI4_SS3 of instance: ecspi4 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA04 + SW_MUX_CTL_PAD_NAND_DATA04 SW MUX Control Register + 0x190 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA04 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA4 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_DATA02 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_SCLK of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD12 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO06 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART2_TX of instance: uart2 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA05 + SW_MUX_CTL_PAD_NAND_DATA05 SW MUX Control Register + 0x194 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA05 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA5 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_B_DATA03 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_MOSI of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD13 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO07 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART2_RX of instance: uart2 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA06 + SW_MUX_CTL_PAD_NAND_DATA06 SW MUX Control Register + 0x198 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA06 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA6 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_BCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_MISO of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD14 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO08 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART2_CTS_B of instance: uart2 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DATA07 + SW_MUX_CTL_PAD_NAND_DATA07 SW MUX Control Register + 0x19C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DATA07 of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA7 of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_SS1_B of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI4_SS0 of instance: ecspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD15 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO09 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART2_RTS_B of instance: uart2 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DATA07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_ALE + SW_MUX_CTL_PAD_NAND_ALE SW MUX Control Register + 0x1A0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_ALE of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_DQS of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: PWM3_OUT of instance: pwm3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR17 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO10 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_SS1 of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_ALE + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_WP_B + SW_MUX_CTL_PAD_NAND_WP_B SW MUX Control Register + 0x1A4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_WP_B of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_SCLK of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: PWM4_OUT of instance: pwm4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_BCLK of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO11 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ECSPI3_RDY of instance: ecspi3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_WP_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_READY_B + SW_MUX_CTL_PAD_NAND_READY_B SW MUX Control Register + 0x1A8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_READY_B of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC1_DATA4 of instance: usdhc1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_DATA00 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI3_SS0 of instance: ecspi3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_CS1_B of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO12 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART3_TX of instance: uart3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_READY_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_CE0_B + SW_MUX_CTL_PAD_NAND_CE0_B SW MUX Control Register + 0x1AC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_CE0_B of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC1_DATA5 of instance: usdhc1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_DATA01 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI3_SCLK of instance: ecspi3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_DTACK_B of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO13 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART3_RX of instance: uart3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_CE0_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_CE1_B + SW_MUX_CTL_PAD_NAND_CE1_B SW MUX Control Register + 0x1B0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_CE1_B of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC1_DATA6 of instance: usdhc1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_DATA02 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI3_MOSI of instance: ecspi3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR18 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO14 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART3_CTS_B of instance: uart3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_CE1_B + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_CLE + SW_MUX_CTL_PAD_NAND_CLE SW MUX Control Register + 0x1B4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_CLE of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC1_DATA7 of instance: usdhc1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_DATA03 of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI3_MISO of instance: ecspi3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR16 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO15 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: UART3_RTS_B of instance: uart3 + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_CLE + 0x1 + + + + + + + SW_MUX_CTL_PAD_NAND_DQS + SW_MUX_CTL_PAD_NAND_DQS SW MUX Control Register + 0x1B8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: RAWNAND_DQS of instance: rawnand + 0 + + + ALT1 + Select mux mode: ALT1 mux port: CSI_FIELD of instance: csi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: QSPI_A_SS0_B of instance: qspi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: PWM5_OUT of instance: pwm5 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_WAIT of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO16 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SDMA_EXT_EVENT01 of instance: sdma + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SPDIF_EXT_CLK of instance: spdif + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad NAND_DQS + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_CMD + SW_MUX_CTL_PAD_SD1_CMD SW MUX Control Register + 0x1BC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_CMD of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE1 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_SYNC of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR19 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO16 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SDMA_EXT_EVENT00 of instance: sdma + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG1_PWR of instance: usb + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SD1_CMD + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_CLK + SW_MUX_CTL_PAD_SD1_CLK SW MUX Control Register + 0x1C0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_CLK of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE2 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_MCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_IN of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR20 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO17 of instance: gpio2 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG1_OC of instance: usb + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SD1_CLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA0 + SW_MUX_CTL_PAD_SD1_DATA0 SW MUX Control Register + 0x1C4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA0 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE3 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_SYNC of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR21 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO18 of instance: gpio2 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ANATOP_OTG1_ID of instance: anatop + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SD1_DATA0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA1 + SW_MUX_CTL_PAD_SD1_DATA1 SW MUX Control Register + 0x1C8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA1 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CLK of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_BCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR22 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO19 of instance: gpio2 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG2_PWR of instance: usb + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SD1_DATA1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA2 + SW_MUX_CTL_PAD_SD1_DATA2 SW MUX Control Register + 0x1CC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA2 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CAPTURE1 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_DATA of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR23 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO20 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_CLKO1 of instance: ccm + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USB_OTG2_OC of instance: usb + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SD1_DATA2 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SD1_DATA3 + SW_MUX_CTL_PAD_SD1_DATA3 SW MUX Control Register + 0x1D0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA3 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CAPTURE2 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_DATA of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_ADDR24 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO21 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_CLKO2 of instance: ccm + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ANATOP_OTG2_ID of instance: anatop + 0x8 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SD1_DATA3 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_MCLK + SW_MUX_CTL_PAD_CSI_MCLK SW MUX Control Register + 0x1D4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_MCLK of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_CD_B of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: RAWNAND_CE2_B of instance: rawnand + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: I2C1_SDA of instance: i2c1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_CS0_B of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO17 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SNVS_HP_VIO_5_CTL of instance: snvs_hp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART6_TX of instance: uart6 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX3_RX2 of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_MCLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_PIXCLK + SW_MUX_CTL_PAD_CSI_PIXCLK SW MUX Control Register + 0x1D8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_PIXCLK of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_WP of instance: usdhc2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: RAWNAND_CE3_B of instance: rawnand + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: I2C1_SCL of instance: i2c1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_OE of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO18 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SNVS_HP_VIO_5 of instance: snvs_hp + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART6_RX of instance: uart6 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX2_RX3 of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_PIXCLK + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_VSYNC + SW_MUX_CTL_PAD_CSI_VSYNC SW MUX Control Register + 0x1DC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_VSYNC of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_CLK of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: I2C2_SDA of instance: i2c2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_RW of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO19 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: PWM7_OUT of instance: pwm7 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART6_RTS_B of instance: uart6 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX4_RX1 of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_VSYNC + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_HSYNC + SW_MUX_CTL_PAD_CSI_HSYNC SW MUX Control Register + 0x1E0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_HSYNC of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_CMD of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: I2C2_SCL of instance: i2c2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_LBA_B of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO20 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: PWM8_OUT of instance: pwm8 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART6_CTS_B of instance: uart6 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX1 of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_HSYNC + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA00 + SW_MUX_CTL_PAD_CSI_DATA00 SW MUX Control Register + 0x1E4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA02 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA0 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI2_SCLK of instance: ecspi2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD00 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO21 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_INT_BOOT of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_TX of instance: uart5 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX_HF_CLK of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA01 + SW_MUX_CTL_PAD_CSI_DATA01 SW MUX Control Register + 0x1E8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA03 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA1 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI2_SS0 of instance: ecspi2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD01 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO22 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SAI1_MCLK of instance: sai1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_RX of instance: uart5 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_RX_HF_CLK of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA02 + SW_MUX_CTL_PAD_CSI_DATA02 SW MUX Control Register + 0x1EC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA04 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA2 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI2_MOSI of instance: ecspi2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD02 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO23 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SAI1_RX_SYNC of instance: sai1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_RTS_B of instance: uart5 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_RX_FS of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA03 + SW_MUX_CTL_PAD_CSI_DATA03 SW MUX Control Register + 0x1F0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA05 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA3 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI2_MISO of instance: ecspi2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD03 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO24 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SAI1_RX_BCLK of instance: sai1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: UART5_CTS_B of instance: uart5 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_RX_CLK of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA04 + SW_MUX_CTL_PAD_CSI_DATA04 SW MUX Control Register + 0x1F4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA06 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA4 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI1_SCLK of instance: ecspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD04 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO25 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SAI1_TX_SYNC of instance: sai1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC1_WP of instance: usdhc1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX_FS of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA05 + SW_MUX_CTL_PAD_CSI_DATA05 SW MUX Control Register + 0x1F8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA07 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA5 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI1_SS0 of instance: ecspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD05 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO26 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SAI1_TX_BCLK of instance: sai1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC1_CD_B of instance: usdhc1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX_CLK of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA06 + SW_MUX_CTL_PAD_CSI_DATA06 SW MUX Control Register + 0x1FC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA08 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA6 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI1_MOSI of instance: ecspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD06 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO27 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SAI1_RX_DATA of instance: sai1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX5_RX0 of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_CSI_DATA07 + SW_MUX_CTL_PAD_CSI_DATA07 SW MUX Control Register + 0x200 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CSI_DATA09 of instance: csi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: USDHC2_DATA7 of instance: usdhc2 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: ECSPI1_MISO of instance: ecspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: EIM_AD07 of instance: eim + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO28 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SAI1_TX_DATA of instance: sai1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ESAI_TX0 of instance: esai + 0x9 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad CSI_DATA07 + 0x1 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR00 + SW_PAD_CTL_PAD_DRAM_ADDR00 SW PAD Control Register + 0x204 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR01 + SW_PAD_CTL_PAD_DRAM_ADDR01 SW PAD Control Register + 0x208 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR02 + SW_PAD_CTL_PAD_DRAM_ADDR02 SW PAD Control Register + 0x20C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR03 + SW_PAD_CTL_PAD_DRAM_ADDR03 SW PAD Control Register + 0x210 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR04 + SW_PAD_CTL_PAD_DRAM_ADDR04 SW PAD Control Register + 0x214 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR05 + SW_PAD_CTL_PAD_DRAM_ADDR05 SW PAD Control Register + 0x218 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR06 + SW_PAD_CTL_PAD_DRAM_ADDR06 SW PAD Control Register + 0x21C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR07 + SW_PAD_CTL_PAD_DRAM_ADDR07 SW PAD Control Register + 0x220 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR08 + SW_PAD_CTL_PAD_DRAM_ADDR08 SW PAD Control Register + 0x224 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR09 + SW_PAD_CTL_PAD_DRAM_ADDR09 SW PAD Control Register + 0x228 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR10 + SW_PAD_CTL_PAD_DRAM_ADDR10 SW PAD Control Register + 0x22C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR11 + SW_PAD_CTL_PAD_DRAM_ADDR11 SW PAD Control Register + 0x230 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR12 + SW_PAD_CTL_PAD_DRAM_ADDR12 SW PAD Control Register + 0x234 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR13 + SW_PAD_CTL_PAD_DRAM_ADDR13 SW PAD Control Register + 0x238 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR14 + SW_PAD_CTL_PAD_DRAM_ADDR14 SW PAD Control Register + 0x23C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_ADDR15 + SW_PAD_CTL_PAD_DRAM_ADDR15 SW PAD Control Register + 0x240 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_DQM0 + SW_PAD_CTL_PAD_DRAM_DQM0 SW PAD Control Register + 0x244 + 32 + read-write + 0x8030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_DQM1 + SW_PAD_CTL_PAD_DRAM_DQM1 SW PAD Control Register + 0x248 + 32 + read-write + 0x8030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-only + + + DO_TRIM + min delay + 0 + + + + + + + SW_PAD_CTL_PAD_DRAM_RAS_B + SW_PAD_CTL_PAD_DRAM_RAS_B SW PAD Control Register + 0x24C + 32 + read-write + 0x8030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_CAS_B + SW_PAD_CTL_PAD_DRAM_CAS_B SW PAD Control Register + 0x250 + 32 + read-write + 0x8030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_CS0_B + SW_PAD_CTL_PAD_DRAM_CS0_B SW PAD Control Register + 0x254 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_CS1_B + SW_PAD_CTL_PAD_DRAM_CS1_B SW PAD Control Register + 0x258 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDWE_B + SW_PAD_CTL_PAD_DRAM_SDWE_B SW PAD Control Register + 0x25C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_ODT0 + SW_PAD_CTL_PAD_DRAM_ODT0 SW PAD Control Register + 0x260 + 32 + read-write + 0x3030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_ODT1 + SW_PAD_CTL_PAD_DRAM_ODT1 SW PAD Control Register + 0x264 + 32 + read-write + 0x3030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDBA0 + SW_PAD_CTL_PAD_DRAM_SDBA0 SW PAD Control Register + 0x268 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDBA1 + SW_PAD_CTL_PAD_DRAM_SDBA1 SW PAD Control Register + 0x26C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDBA2 + SW_PAD_CTL_PAD_DRAM_SDBA2 SW PAD Control Register + 0x270 + 32 + read-write + 0xB000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDCKE0 + SW_PAD_CTL_PAD_DRAM_SDCKE0 SW PAD Control Register + 0x274 + 32 + read-write + 0x3000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDCKE1 + SW_PAD_CTL_PAD_DRAM_SDCKE1 SW PAD Control Register + 0x278 + 32 + read-write + 0x3000 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-only + + + DSE + output driver disabled; + 0 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDCLK0_P + SW_PAD_CTL_PAD_DRAM_SDCLK0_P SW PAD Control Register + 0x27C + 32 + read-write + 0x8030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-only + + + PKE + Pull/Keeper Disabled + 0 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-only + + + PUE + Keeper + 0 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-only + + + PUS + 100K Ohm Pull Up + 0x2 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + DO_TRIM_PADN + do_trim_padn Field + 0x18 + 2 + read-write + + + DO_TRIM_PADN_0_min_delay + min delay + 0 + + + DO_TRIM_PADN_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_PADN_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_PADN_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDQS0_P + SW_PAD_CTL_PAD_DRAM_SDQS0_P SW PAD Control Register + 0x280 + 32 + read-write + 0x2030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-only + + + ODT + off + 0 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-only + + + HYS + Hysteresis Disabled + 0 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-only + + + DDR_INPUT + CMOS input type + 0 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + DO_TRIM_PADN + do_trim_padn Field + 0x18 + 2 + read-write + + + DO_TRIM_PADN_0_min_delay + min delay + 0 + + + DO_TRIM_PADN_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_PADN_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_PADN_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_SDQS1_P + SW_PAD_CTL_PAD_DRAM_SDQS1_P SW PAD Control Register + 0x284 + 32 + read-write + 0x2030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-only + + + ODT + off + 0 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-only + + + HYS + Hysteresis Disabled + 0 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-only + + + DDR_INPUT + CMOS input type + 0 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-only + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + DO_TRIM_PADN + do_trim_padn Field + 0x18 + 2 + read-write + + + DO_TRIM_PADN_0_min_delay + min delay + 0 + + + DO_TRIM_PADN_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_PADN_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_PADN_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_DRAM_RESET + SW_PAD_CTL_PAD_DRAM_RESET SW PAD Control Register + 0x288 + 32 + read-write + 0x83030 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + ODT + On Die Termination Field + 0x8 + 3 + read-write + + + ODT_0_off + off + 0 + + + ODT_1_120_Ohm_ODT + 120 Ohm ODT + 0x1 + + + ODT_2_60_Ohm_ODT + 60 Ohm ODT + 0x2 + + + ODT_3_40_Ohm_ODT + 40 Ohm ODT + 0x3 + + + ODT_4_30_Ohm_ODT + 30 Ohm ODT + 0x4 + + + ODT_5_24_Ohm_ODT + 24 Ohm ODT + 0x5 + + + ODT_6_20_Ohm_ODT + 20 Ohm ODT + 0x6 + + + ODT_7_17_Ohm_ODT + 17 Ohm ODT + 0x7 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-write + + + DDR_SEL_2_LPDDR2_mode + LPDDR2 mode + 0x2 + + + DDR_SEL_3_DDR3_mode + DDR3 mode + 0x3 + + + + + DO_TRIM + do_trim Field + 0x14 + 2 + read-write + + + DO_TRIM_0_min_delay + min delay + 0 + + + DO_TRIM_1_____50ps__ipp_do____pad_delay + + ~50ps ipp_do -> pad delay + 0x1 + + + DO_TRIM_2_____100ps_ipp_do____pad_delay + + ~100ps ipp_do -> pad delay + 0x2 + + + DO_TRIM_3_____150ps_ipp_do____pad_delay + + ~150ps ipp_do -> pad delay + 0x3 + + + + + + + SW_PAD_CTL_PAD_JTAG_MOD + SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register + 0x2D0 + 32 + read-write + 0xB0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_TMS + SW_PAD_CTL_PAD_JTAG_TMS SW PAD Control Register + 0x2D4 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_TDO + SW_PAD_CTL_PAD_JTAG_TDO SW PAD Control Register + 0x2D8 + 32 + read-write + 0x90B1 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_TDI + SW_PAD_CTL_PAD_JTAG_TDI SW PAD Control Register + 0x2DC + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_TCK + SW_PAD_CTL_PAD_JTAG_TCK SW PAD Control Register + 0x2E0 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_JTAG_TRST_B + SW_PAD_CTL_PAD_JTAG_TRST_B SW PAD Control Register + 0x2E4 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO00 + SW_PAD_CTL_PAD_GPIO1_IO00 SW PAD Control Register + 0x2E8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO01 + SW_PAD_CTL_PAD_GPIO1_IO01 SW PAD Control Register + 0x2EC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO02 + SW_PAD_CTL_PAD_GPIO1_IO02 SW PAD Control Register + 0x2F0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO03 + SW_PAD_CTL_PAD_GPIO1_IO03 SW PAD Control Register + 0x2F4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO04 + SW_PAD_CTL_PAD_GPIO1_IO04 SW PAD Control Register + 0x2F8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO05 + SW_PAD_CTL_PAD_GPIO1_IO05 SW PAD Control Register + 0x2FC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO06 + SW_PAD_CTL_PAD_GPIO1_IO06 SW PAD Control Register + 0x300 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO07 + SW_PAD_CTL_PAD_GPIO1_IO07 SW PAD Control Register + 0x304 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO08 + SW_PAD_CTL_PAD_GPIO1_IO08 SW PAD Control Register + 0x308 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO1_IO09 + SW_PAD_CTL_PAD_GPIO1_IO09 SW PAD Control Register + 0x30C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART1_TX_DATA + SW_PAD_CTL_PAD_UART1_TX_DATA SW PAD Control Register + 0x310 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART1_RX_DATA + SW_PAD_CTL_PAD_UART1_RX_DATA SW PAD Control Register + 0x314 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART1_CTS_B + SW_PAD_CTL_PAD_UART1_CTS_B SW PAD Control Register + 0x318 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART1_RTS_B + SW_PAD_CTL_PAD_UART1_RTS_B SW PAD Control Register + 0x31C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART2_TX_DATA + SW_PAD_CTL_PAD_UART2_TX_DATA SW PAD Control Register + 0x320 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART2_RX_DATA + SW_PAD_CTL_PAD_UART2_RX_DATA SW PAD Control Register + 0x324 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART2_CTS_B + SW_PAD_CTL_PAD_UART2_CTS_B SW PAD Control Register + 0x328 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART2_RTS_B + SW_PAD_CTL_PAD_UART2_RTS_B SW PAD Control Register + 0x32C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART3_TX_DATA + SW_PAD_CTL_PAD_UART3_TX_DATA SW PAD Control Register + 0x330 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART3_RX_DATA + SW_PAD_CTL_PAD_UART3_RX_DATA SW PAD Control Register + 0x334 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART3_CTS_B + SW_PAD_CTL_PAD_UART3_CTS_B SW PAD Control Register + 0x338 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART3_RTS_B + SW_PAD_CTL_PAD_UART3_RTS_B SW PAD Control Register + 0x33C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART4_TX_DATA + SW_PAD_CTL_PAD_UART4_TX_DATA SW PAD Control Register + 0x340 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART4_RX_DATA + SW_PAD_CTL_PAD_UART4_RX_DATA SW PAD Control Register + 0x344 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART5_TX_DATA + SW_PAD_CTL_PAD_UART5_TX_DATA SW PAD Control Register + 0x348 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_UART5_RX_DATA + SW_PAD_CTL_PAD_UART5_RX_DATA SW PAD Control Register + 0x34C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_RX_DATA0 + SW_PAD_CTL_PAD_ENET1_RX_DATA0 SW PAD Control Register + 0x350 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_RX_DATA1 + SW_PAD_CTL_PAD_ENET1_RX_DATA1 SW PAD Control Register + 0x354 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_RX_EN + SW_PAD_CTL_PAD_ENET1_RX_EN SW PAD Control Register + 0x358 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_TX_DATA0 + SW_PAD_CTL_PAD_ENET1_TX_DATA0 SW PAD Control Register + 0x35C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_TX_DATA1 + SW_PAD_CTL_PAD_ENET1_TX_DATA1 SW PAD Control Register + 0x360 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_TX_EN + SW_PAD_CTL_PAD_ENET1_TX_EN SW PAD Control Register + 0x364 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_TX_CLK + SW_PAD_CTL_PAD_ENET1_TX_CLK SW PAD Control Register + 0x368 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET1_RX_ER + SW_PAD_CTL_PAD_ENET1_RX_ER SW PAD Control Register + 0x36C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_RX_DATA0 + SW_PAD_CTL_PAD_ENET2_RX_DATA0 SW PAD Control Register + 0x370 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_RX_DATA1 + SW_PAD_CTL_PAD_ENET2_RX_DATA1 SW PAD Control Register + 0x374 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_RX_EN + SW_PAD_CTL_PAD_ENET2_RX_EN SW PAD Control Register + 0x378 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_TX_DATA0 + SW_PAD_CTL_PAD_ENET2_TX_DATA0 SW PAD Control Register + 0x37C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_TX_DATA1 + SW_PAD_CTL_PAD_ENET2_TX_DATA1 SW PAD Control Register + 0x380 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_TX_EN + SW_PAD_CTL_PAD_ENET2_TX_EN SW PAD Control Register + 0x384 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_TX_CLK + SW_PAD_CTL_PAD_ENET2_TX_CLK SW PAD Control Register + 0x388 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ENET2_RX_ER + SW_PAD_CTL_PAD_ENET2_RX_ER SW PAD Control Register + 0x38C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_CLK + SW_PAD_CTL_PAD_LCD_CLK SW PAD Control Register + 0x390 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_ENABLE + SW_PAD_CTL_PAD_LCD_ENABLE SW PAD Control Register + 0x394 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_HSYNC + SW_PAD_CTL_PAD_LCD_HSYNC SW PAD Control Register + 0x398 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_VSYNC + SW_PAD_CTL_PAD_LCD_VSYNC SW PAD Control Register + 0x39C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_RESET + SW_PAD_CTL_PAD_LCD_RESET SW PAD Control Register + 0x3A0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA00 + SW_PAD_CTL_PAD_LCD_DATA00 SW PAD Control Register + 0x3A4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA01 + SW_PAD_CTL_PAD_LCD_DATA01 SW PAD Control Register + 0x3A8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA02 + SW_PAD_CTL_PAD_LCD_DATA02 SW PAD Control Register + 0x3AC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA03 + SW_PAD_CTL_PAD_LCD_DATA03 SW PAD Control Register + 0x3B0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA04 + SW_PAD_CTL_PAD_LCD_DATA04 SW PAD Control Register + 0x3B4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA05 + SW_PAD_CTL_PAD_LCD_DATA05 SW PAD Control Register + 0x3B8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA06 + SW_PAD_CTL_PAD_LCD_DATA06 SW PAD Control Register + 0x3BC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA07 + SW_PAD_CTL_PAD_LCD_DATA07 SW PAD Control Register + 0x3C0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA08 + SW_PAD_CTL_PAD_LCD_DATA08 SW PAD Control Register + 0x3C4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA09 + SW_PAD_CTL_PAD_LCD_DATA09 SW PAD Control Register + 0x3C8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA10 + SW_PAD_CTL_PAD_LCD_DATA10 SW PAD Control Register + 0x3CC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA11 + SW_PAD_CTL_PAD_LCD_DATA11 SW PAD Control Register + 0x3D0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA12 + SW_PAD_CTL_PAD_LCD_DATA12 SW PAD Control Register + 0x3D4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA13 + SW_PAD_CTL_PAD_LCD_DATA13 SW PAD Control Register + 0x3D8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA14 + SW_PAD_CTL_PAD_LCD_DATA14 SW PAD Control Register + 0x3DC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA15 + SW_PAD_CTL_PAD_LCD_DATA15 SW PAD Control Register + 0x3E0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA16 + SW_PAD_CTL_PAD_LCD_DATA16 SW PAD Control Register + 0x3E4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA17 + SW_PAD_CTL_PAD_LCD_DATA17 SW PAD Control Register + 0x3E8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA18 + SW_PAD_CTL_PAD_LCD_DATA18 SW PAD Control Register + 0x3EC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA19 + SW_PAD_CTL_PAD_LCD_DATA19 SW PAD Control Register + 0x3F0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA20 + SW_PAD_CTL_PAD_LCD_DATA20 SW PAD Control Register + 0x3F4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA21 + SW_PAD_CTL_PAD_LCD_DATA21 SW PAD Control Register + 0x3F8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA22 + SW_PAD_CTL_PAD_LCD_DATA22 SW PAD Control Register + 0x3FC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_LCD_DATA23 + SW_PAD_CTL_PAD_LCD_DATA23 SW PAD Control Register + 0x400 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_RE_B + SW_PAD_CTL_PAD_NAND_RE_B SW PAD Control Register + 0x404 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_WE_B + SW_PAD_CTL_PAD_NAND_WE_B SW PAD Control Register + 0x408 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA00 + SW_PAD_CTL_PAD_NAND_DATA00 SW PAD Control Register + 0x40C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA01 + SW_PAD_CTL_PAD_NAND_DATA01 SW PAD Control Register + 0x410 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA02 + SW_PAD_CTL_PAD_NAND_DATA02 SW PAD Control Register + 0x414 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA03 + SW_PAD_CTL_PAD_NAND_DATA03 SW PAD Control Register + 0x418 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA04 + SW_PAD_CTL_PAD_NAND_DATA04 SW PAD Control Register + 0x41C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA05 + SW_PAD_CTL_PAD_NAND_DATA05 SW PAD Control Register + 0x420 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA06 + SW_PAD_CTL_PAD_NAND_DATA06 SW PAD Control Register + 0x424 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DATA07 + SW_PAD_CTL_PAD_NAND_DATA07 SW PAD Control Register + 0x428 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_ALE + SW_PAD_CTL_PAD_NAND_ALE SW PAD Control Register + 0x42C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_WP_B + SW_PAD_CTL_PAD_NAND_WP_B SW PAD Control Register + 0x430 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_READY_B + SW_PAD_CTL_PAD_NAND_READY_B SW PAD Control Register + 0x434 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_CE0_B + SW_PAD_CTL_PAD_NAND_CE0_B SW PAD Control Register + 0x438 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_CE1_B + SW_PAD_CTL_PAD_NAND_CE1_B SW PAD Control Register + 0x43C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_CLE + SW_PAD_CTL_PAD_NAND_CLE SW PAD Control Register + 0x440 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_NAND_DQS + SW_PAD_CTL_PAD_NAND_DQS SW PAD Control Register + 0x444 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_CMD + SW_PAD_CTL_PAD_SD1_CMD SW PAD Control Register + 0x448 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_CLK + SW_PAD_CTL_PAD_SD1_CLK SW PAD Control Register + 0x44C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA0 + SW_PAD_CTL_PAD_SD1_DATA0 SW PAD Control Register + 0x450 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA1 + SW_PAD_CTL_PAD_SD1_DATA1 SW PAD Control Register + 0x454 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA2 + SW_PAD_CTL_PAD_SD1_DATA2 SW PAD Control Register + 0x458 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SD1_DATA3 + SW_PAD_CTL_PAD_SD1_DATA3 SW PAD Control Register + 0x45C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_MCLK + SW_PAD_CTL_PAD_CSI_MCLK SW PAD Control Register + 0x460 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_PIXCLK + SW_PAD_CTL_PAD_CSI_PIXCLK SW PAD Control Register + 0x464 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_VSYNC + SW_PAD_CTL_PAD_CSI_VSYNC SW PAD Control Register + 0x468 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_HSYNC + SW_PAD_CTL_PAD_CSI_HSYNC SW PAD Control Register + 0x46C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA00 + SW_PAD_CTL_PAD_CSI_DATA00 SW PAD Control Register + 0x470 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA01 + SW_PAD_CTL_PAD_CSI_DATA01 SW PAD Control Register + 0x474 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA02 + SW_PAD_CTL_PAD_CSI_DATA02 SW PAD Control Register + 0x478 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA03 + SW_PAD_CTL_PAD_CSI_DATA03 SW PAD Control Register + 0x47C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA04 + SW_PAD_CTL_PAD_CSI_DATA04 SW PAD Control Register + 0x480 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA05 + SW_PAD_CTL_PAD_CSI_DATA05 SW PAD Control Register + 0x484 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA06 + SW_PAD_CTL_PAD_CSI_DATA06 SW PAD Control Register + 0x488 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CSI_DATA07 + SW_PAD_CTL_PAD_CSI_DATA07 SW PAD Control Register + 0x48C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_GRP_ADDDS + SW_PAD_CTL_GRP_ADDDS SW GRP Register + 0x490 + 32 + read-write + 0x30 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + + + SW_PAD_CTL_GRP_DDRMODE_CTL + SW_PAD_CTL_GRP_DDRMODE_CTL SW GRP Register + 0x494 + 32 + read-write + 0 + 0xFFFFFFFF + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + + + SW_PAD_CTL_GRP_B0DS + SW_PAD_CTL_GRP_B0DS SW GRP Register + 0x498 + 32 + read-write + 0x30 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + + + SW_PAD_CTL_GRP_DDRPK + SW_PAD_CTL_GRP_DDRPK SW GRP Register + 0x49C + 32 + read-write + 0x2000 + 0xFFFFFFFF + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + + + SW_PAD_CTL_GRP_CTLDS + SW_PAD_CTL_GRP_CTLDS SW GRP Register + 0x4A0 + 32 + read-write + 0x30 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + + + SW_PAD_CTL_GRP_B1DS + SW_PAD_CTL_GRP_B1DS SW GRP Register + 0x4A4 + 32 + read-write + 0x30 + 0xFFFFFFFF + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + + + SW_PAD_CTL_GRP_DDRHYS + SW_PAD_CTL_GRP_DDRHYS SW GRP Register + 0x4A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_GRP_DDRPKE + SW_PAD_CTL_GRP_DDRPKE SW GRP Register + 0x4AC + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + + + SW_PAD_CTL_GRP_DDRMODE + SW_PAD_CTL_GRP_DDRMODE SW GRP Register + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DDR_INPUT + DDR / CMOS Input Mode Field + 0x11 + 1 + read-write + + + DDR_INPUT_0_CMOS_input_type + CMOS input type + 0 + + + DDR_INPUT_1_Differential_input_mode + Differential input mode + 0x1 + + + + + + + SW_PAD_CTL_GRP_DDR_TYPE + SW_PAD_CTL_GRP_DDR_TYPE SW GRP Register + 0x4B4 + 32 + read-write + 0x80000 + 0xFFFFFFFF + + + DDR_SEL + ddr_sel Field + 0x12 + 2 + read-write + + + DDR_SEL_2_LPDDR2_mode + LPDDR2 mode + 0x2 + + + DDR_SEL_3_DDR3_mode + DDR3 mode + 0x3 + + + + + + + ANATOP_USB_OTG_ID_SELECT_INPUT + USB_OTG1_ID_SELECT_INPUT DAISY Register + 0x4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO00_ALT2 + Selecting Pad: GPIO1_IO00 for Mode: ALT2 + 0 + + + UART3_TX_DATA_ALT8 + Selecting Pad: UART3_TX_DATA for Mode: ALT8 + 0x1 + + + SD1_DATA0_ALT8 + Selecting Pad: SD1_DATA0 for Mode: ALT8 + 0x2 + + + + + + + USB_OTG2_ID_SELECT_INPUT + USB_OTG2_ID_SELECT_INPUT DAISY Register + 0x4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO05_ALT2 + Selecting Pad: GPIO1_IO05 for Mode: ALT2 + 0 + + + ENET2_TX_CLK_ALT8 + Selecting Pad: ENET2_TX_CLK for Mode: ALT8 + 0x1 + + + SD1_DATA3_ALT8 + Selecting Pad: SD1_DATA3 for Mode: ALT8 + 0x2 + + + + + + + CCM_PMIC_READY_SELECT_INPUT + CCM_PMIC_READY_SELECT_INPUT DAISY Register + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_MOD_ALT4 + Selecting Pad: JTAG_MOD for Mode: ALT4 + 0 + + + GPIO1_IO08_ALT6 + Selecting Pad: GPIO1_IO08 for Mode: ALT6 + 0x1 + + + + + + + CSI_DATA02_SELECT_INPUT + CSI_DATA02_SELECT_INPUT DAISY Register + 0x4C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_DATA00_ALT0 + Selecting Pad: CSI_DATA00 for Mode: ALT0 + 0 + + + UART1_TX_DATA_ALT3 + Selecting Pad: UART1_TX_DATA for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA03_SELECT_INPUT + CSI_DATA03_SELECT_INPUT DAISY Register + 0x4C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_DATA01_ALT0 + Selecting Pad: CSI_DATA01 for Mode: ALT0 + 0 + + + UART1_RX_DATA_ALT3 + Selecting Pad: UART1_RX_DATA for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA05_SELECT_INPUT + CSI_DATA05_SELECT_INPUT DAISY Register + 0x4CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_DATA03_ALT0 + Selecting Pad: CSI_DATA03 for Mode: ALT0 + 0 + + + UART1_RTS_B_ALT3 + Selecting Pad: UART1_RTS_B for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA00_SELECT_INPUT + CSI_DATA00_SELECT_INPUT DAISY Register + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART3_RX_DATA_ALT3 + Selecting Pad: UART3_RX_DATA for Mode: ALT3 + 0 + + + LCD_DATA17_ALT3 + Selecting Pad: LCD_DATA17 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA01_SELECT_INPUT + CSI_DATA01_SELECT_INPUT DAISY Register + 0x4D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART3_TX_DATA_ALT3 + Selecting Pad: UART3_TX_DATA for Mode: ALT3 + 0 + + + LCD_DATA16_ALT3 + Selecting Pad: LCD_DATA16 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA04_SELECT_INPUT + CSI_DATA04_SELECT_INPUT DAISY Register + 0x4D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART1_CTS_B_ALT3 + Selecting Pad: UART1_CTS_B for Mode: ALT3 + 0 + + + CSI_DATA02_ALT0 + Selecting Pad: CSI_DATA02 for Mode: ALT0 + 0x1 + + + + + + + CSI_DATA06_SELECT_INPUT + CSI_DATA06_SELECT_INPUT DAISY Register + 0x4DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_TX_DATA_ALT3 + Selecting Pad: UART2_TX_DATA for Mode: ALT3 + 0 + + + CSI_DATA04_ALT0 + Selecting Pad: CSI_DATA04 for Mode: ALT0 + 0x1 + + + + + + + CSI_DATA07_SELECT_INPUT + CSI_DATA07_SELECT_INPUT DAISY Register + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_RX_DATA_ALT3 + Selecting Pad: UART2_RX_DATA for Mode: ALT3 + 0 + + + CSI_DATA05_ALT0 + Selecting Pad: CSI_DATA05 for Mode: ALT0 + 0x1 + + + + + + + CSI_DATA08_SELECT_INPUT + CSI_DATA08_SELECT_INPUT DAISY Register + 0x4E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_CTS_B_ALT3 + Selecting Pad: UART2_CTS_B for Mode: ALT3 + 0 + + + CSI_DATA06_ALT0 + Selecting Pad: CSI_DATA06 for Mode: ALT0 + 0x1 + + + + + + + CSI_DATA09_SELECT_INPUT + CSI_DATA09_SELECT_INPUT DAISY Register + 0x4E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_RTS_B_ALT3 + Selecting Pad: UART2_RTS_B for Mode: ALT3 + 0 + + + CSI_DATA07_ALT0 + Selecting Pad: CSI_DATA07 for Mode: ALT0 + 0x1 + + + + + + + CSI_DATA10_SELECT_INPUT + CSI_DATA10_SELECT_INPUT DAISY Register + 0x4EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART3_CTS_B_ALT3 + Selecting Pad: UART3_CTS_B for Mode: ALT3 + 0 + + + LCD_DATA18_ALT3 + Selecting Pad: LCD_DATA18 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA11_SELECT_INPUT + CSI_DATA11_SELECT_INPUT DAISY Register + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART3_RTS_B_ALT3 + Selecting Pad: UART3_RTS_B for Mode: ALT3 + 0 + + + LCD_DATA19_ALT3 + Selecting Pad: LCD_DATA19 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA12_SELECT_INPUT + CSI_DATA12_SELECT_INPUT DAISY Register + 0x4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART4_TX_DATA_ALT3 + Selecting Pad: UART4_TX_DATA for Mode: ALT3 + 0 + + + LCD_DATA20_ALT3 + Selecting Pad: LCD_DATA20 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA13_SELECT_INPUT + CSI_DATA13_SELECT_INPUT DAISY Register + 0x4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART4_RX_DATA_ALT3 + Selecting Pad: UART4_RX_DATA for Mode: ALT3 + 0 + + + LCD_DATA21_ALT3 + Selecting Pad: LCD_DATA21 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA14_SELECT_INPUT + CSI_DATA14_SELECT_INPUT DAISY Register + 0x4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART5_TX_DATA_ALT3 + Selecting Pad: UART5_TX_DATA for Mode: ALT3 + 0 + + + LCD_DATA22_ALT3 + Selecting Pad: LCD_DATA22 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA15_SELECT_INPUT + CSI_DATA15_SELECT_INPUT DAISY Register + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART5_RX_DATA_ALT3 + Selecting Pad: UART5_RX_DATA for Mode: ALT3 + 0 + + + LCD_DATA23_ALT3 + Selecting Pad: LCD_DATA23 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA16_SELECT_INPUT + CSI_DATA16_SELECT_INPUT DAISY Register + 0x504 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_RX_DATA0_ALT3 + Selecting Pad: ENET1_RX_DATA0 for Mode: ALT3 + 0 + + + LCD_DATA08_ALT3 + Selecting Pad: LCD_DATA08 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA17_SELECT_INPUT + CSI_DATA17_SELECT_INPUT DAISY Register + 0x508 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_RX_DATA1_ALT3 + Selecting Pad: ENET1_RX_DATA1 for Mode: ALT3 + 0 + + + LCD_DATA09_ALT3 + Selecting Pad: LCD_DATA09 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA18_SELECT_INPUT + CSI_DATA18_SELECT_INPUT DAISY Register + 0x50C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_RX_EN_ALT3 + Selecting Pad: ENET1_RX_EN for Mode: ALT3 + 0 + + + LCD_DATA10_ALT3 + Selecting Pad: LCD_DATA10 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA19_SELECT_INPUT + CSI_DATA19_SELECT_INPUT DAISY Register + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_TX_DATA0_ALT3 + Selecting Pad: ENET1_TX_DATA0 for Mode: ALT3 + 0 + + + LCD_DATA11_ALT3 + Selecting Pad: LCD_DATA11 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA20_SELECT_INPUT + CSI_DATA20_SELECT_INPUT DAISY Register + 0x514 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_TX_DATA1_ALT3 + Selecting Pad: ENET1_TX_DATA1 for Mode: ALT3 + 0 + + + LCD_DATA12_ALT3 + Selecting Pad: LCD_DATA12 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA21_SELECT_INPUT + CSI_DATA21_SELECT_INPUT DAISY Register + 0x518 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_TX_EN_ALT3 + Selecting Pad: ENET1_TX_EN for Mode: ALT3 + 0 + + + LCD_DATA13_ALT3 + Selecting Pad: LCD_DATA13 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA22_SELECT_INPUT + CSI_DATA22_SELECT_INPUT DAISY Register + 0x51C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_TX_CLK_ALT3 + Selecting Pad: ENET1_TX_CLK for Mode: ALT3 + 0 + + + LCD_DATA14_ALT3 + Selecting Pad: LCD_DATA14 for Mode: ALT3 + 0x1 + + + + + + + CSI_DATA23_SELECT_INPUT + CSI_DATA23_SELECT_INPUT DAISY Register + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_RX_ER_ALT3 + Selecting Pad: ENET1_RX_ER for Mode: ALT3 + 0 + + + LCD_DATA15_ALT3 + Selecting Pad: LCD_DATA15 for Mode: ALT3 + 0x1 + + + + + + + CSI_HSYNC_SELECT_INPUT + CSI_HSYNC_SELECT_INPUT DAISY Register + 0x524 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_HSYNC_ALT0 + Selecting Pad: CSI_HSYNC for Mode: ALT0 + 0 + + + GPIO1_IO09_ALT3 + Selecting Pad: GPIO1_IO09 for Mode: ALT3 + 0x1 + + + + + + + CSI_PIXCLK_SELECT_INPUT + CSI_PIXCLK_SELECT_INPUT DAISY Register + 0x528 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO1_IO07_ALT3 + Selecting Pad: GPIO1_IO07 for Mode: ALT3 + 0 + + + CSI_PIXCLK_ALT0 + Selecting Pad: CSI_PIXCLK for Mode: ALT0 + 0x1 + + + + + + + CSI_VSYNC_SELECT_INPUT + CSI_VSYNC_SELECT_INPUT DAISY Register + 0x52C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_VSYNC_ALT0 + Selecting Pad: CSI_VSYNC for Mode: ALT0 + 0 + + + GPIO1_IO08_ALT3 + Selecting Pad: GPIO1_IO08 for Mode: ALT3 + 0x1 + + + + + + + CSI_FIELD_SELECT_INPUT + CSI_FIELD_SELECT_INPUT DAISY Register + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO1_IO05_ALT3 + Selecting Pad: GPIO1_IO05 for Mode: ALT3 + 0 + + + NAND_DQS_ALT1 + Selecting Pad: NAND_DQS for Mode: ALT1 + 0x1 + + + + + + + ECSPI1_SCLK_SELECT_INPUT + ECSPI1_SCLK_SELECT_INPUT DAISY Register + 0x534 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA20_ALT2 + Selecting Pad: LCD_DATA20 for Mode: ALT2 + 0 + + + CSI_DATA04_ALT3 + Selecting Pad: CSI_DATA04 for Mode: ALT3 + 0x1 + + + + + + + ECSPI1_MISO_SELECT_INPUT + ECSPI1_MISO_SELECT_INPUT DAISY Register + 0x538 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA23_ALT2 + Selecting Pad: LCD_DATA23 for Mode: ALT2 + 0 + + + CSI_DATA07_ALT3 + Selecting Pad: CSI_DATA07 for Mode: ALT3 + 0x1 + + + + + + + ECSPI1_MOSI_SELECT_INPUT + ECSPI1_MOSI_SELECT_INPUT DAISY Register + 0x53C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA22_ALT2 + Selecting Pad: LCD_DATA22 for Mode: ALT2 + 0 + + + CSI_DATA06_ALT3 + Selecting Pad: CSI_DATA06 for Mode: ALT3 + 0x1 + + + + + + + ECSPI1_SS0_B_SELECT_INPUT + ECSPI1_SS0_B_SELECT_INPUT DAISY Register + 0x540 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA21_ALT2 + Selecting Pad: LCD_DATA21 for Mode: ALT2 + 0 + + + CSI_DATA05_ALT3 + Selecting Pad: CSI_DATA05 for Mode: ALT3 + 0x1 + + + + + + + ECSPI2_SCLK_SELECT_INPUT + ECSPI2_SCLK_SELECT_INPUT DAISY Register + 0x544 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_DATA00_ALT3 + Selecting Pad: CSI_DATA00 for Mode: ALT3 + 0 + + + UART4_TX_DATA_ALT8 + Selecting Pad: UART4_TX_DATA for Mode: ALT8 + 0x1 + + + + + + + ECSPI2_MISO_SELECT_INPUT + ECSPI2_MISO_SELECT_INPUT DAISY Register + 0x548 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_DATA03_ALT3 + Selecting Pad: CSI_DATA03 for Mode: ALT3 + 0 + + + UART5_RX_DATA_ALT8 + Selecting Pad: UART5_RX_DATA for Mode: ALT8 + 0x1 + + + + + + + ECSPI2_MOSI_SELECT_INPUT + ECSPI2_MOSI_SELECT_INPUT DAISY Register + 0x54C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART5_TX_DATA_ALT8 + Selecting Pad: UART5_TX_DATA for Mode: ALT8 + 0 + + + CSI_DATA02_ALT3 + Selecting Pad: CSI_DATA02 for Mode: ALT3 + 0x1 + + + + + + + ECSPI2_SS0_B_SELECT_INPUT + ECSPI2_SS0_B_SELECT_INPUT DAISY Register + 0x550 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_DATA01_ALT3 + Selecting Pad: CSI_DATA01 for Mode: ALT3 + 0 + + + UART4_RX_DATA_ALT8 + Selecting Pad: UART4_RX_DATA for Mode: ALT8 + 0x1 + + + + + + + ECSPI3_SCLK_SELECT_INPUT + ECSPI3_SCLK_SELECT_INPUT DAISY Register + 0x554 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_RX_DATA_ALT8 + Selecting Pad: UART2_RX_DATA for Mode: ALT8 + 0 + + + NAND_CE0_B_ALT3 + Selecting Pad: NAND_CE0_B for Mode: ALT3 + 0x1 + + + + + + + ECSPI3_MISO_SELECT_INPUT + ECSPI3_MISO_SELECT_INPUT DAISY Register + 0x558 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_RTS_B_ALT8 + Selecting Pad: UART2_RTS_B for Mode: ALT8 + 0 + + + NAND_CLE_ALT3 + Selecting Pad: NAND_CLE for Mode: ALT3 + 0x1 + + + + + + + ECSPI3_MOSI_SELECT_INPUT + ECSPI3_MOSI_SELECT_INPUT DAISY Register + 0x55C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_CTS_B_ALT8 + Selecting Pad: UART2_CTS_B for Mode: ALT8 + 0 + + + NAND_CE1_B_ALT3 + Selecting Pad: NAND_CE1_B for Mode: ALT3 + 0x1 + + + + + + + ECSPI3_SS0_B_SELECT_INPUT + ECSPI3_SS0_B_SELECT_INPUT DAISY Register + 0x560 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_TX_DATA_ALT8 + Selecting Pad: UART2_TX_DATA for Mode: ALT8 + 0 + + + NAND_READY_B_ALT3 + Selecting Pad: NAND_READY_B for Mode: ALT3 + 0x1 + + + + + + + ECSPI4_SCLK_SELECT_INPUT + ECSPI4_SCLK_SELECT_INPUT DAISY Register + 0x564 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET2_TX_DATA1_ALT3 + Selecting Pad: ENET2_TX_DATA1 for Mode: ALT3 + 0 + + + NAND_DATA04_ALT3 + Selecting Pad: NAND_DATA04 for Mode: ALT3 + 0x1 + + + + + + + ECSPI4_MISO_SELECT_INPUT + ECSPI4_MISO_SELECT_INPUT DAISY Register + 0x568 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET2_TX_CLK_ALT3 + Selecting Pad: ENET2_TX_CLK for Mode: ALT3 + 0 + + + NAND_DATA06_ALT3 + Selecting Pad: NAND_DATA06 for Mode: ALT3 + 0x1 + + + + + + + ECSPI4_MOSI_SELECT_INPUT + ECSPI4_MOSI_SELECT_INPUT DAISY Register + 0x56C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET2_TX_EN_ALT3 + Selecting Pad: ENET2_TX_EN for Mode: ALT3 + 0 + + + NAND_DATA05_ALT3 + Selecting Pad: NAND_DATA05 for Mode: ALT3 + 0x1 + + + + + + + ECSPI4_SS0_B_SELECT_INPUT + ECSPI4_SS0_B_SELECT_INPUT DAISY Register + 0x570 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET2_RX_ER_ALT3 + Selecting Pad: ENET2_RX_ER for Mode: ALT3 + 0 + + + NAND_DATA07_ALT3 + Selecting Pad: NAND_DATA07 for Mode: ALT3 + 0x1 + + + + + + + ENET1_REF_CLK1_SELECT_INPUT + ENET1_REF_CLK1_SELECT_INPUT DAISY Register + 0x574 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO00_ALT3 + Selecting Pad: GPIO1_IO00 for Mode: ALT3 + 0 + + + GPIO1_IO04_ALT0 + Selecting Pad: GPIO1_IO04 for Mode: ALT0 + 0x1 + + + ENET1_TX_CLK_ALT4 + Selecting Pad: ENET1_TX_CLK for Mode: ALT4 + 0x2 + + + + + + + ENET1_MAC0_MDIO_SELECT_INPUT + ENET1_MAC0_MDIO_SELECT_INPUT DAISY Register + 0x578 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO1_IO06_ALT0 + Selecting Pad: GPIO1_IO06 for Mode: ALT0 + 0 + + + ENET2_RX_DATA0_ALT4 + Selecting Pad: ENET2_RX_DATA0 for Mode: ALT4 + 0x1 + + + + + + + ENET2_REF_CLK2_SELECT_INPUT + ENET2_REF_CLK2_SELECT_INPUT DAISY Register + 0x57C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO01_ALT3 + Selecting Pad: GPIO1_IO01 for Mode: ALT3 + 0 + + + GPIO1_IO05_ALT0 + Selecting Pad: GPIO1_IO05 for Mode: ALT0 + 0x1 + + + ENET2_TX_CLK_ALT4 + Selecting Pad: ENET2_TX_CLK for Mode: ALT4 + 0x2 + + + + + + + ENET2_MAC0_MDIO_SELECT_INPUT + ENET2_MAC0_MDIO_SELECT_INPUT DAISY Register + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO1_IO06_ALT1 + Selecting Pad: GPIO1_IO06 for Mode: ALT1 + 0 + + + ENET1_TX_DATA1_ALT4 + Selecting Pad: ENET1_TX_DATA1 for Mode: ALT4 + 0x1 + + + + + + + FLEXCAN1_RX_SELECT_INPUT + FLEXCAN1_RX_SELECT_INPUT DAISY Register + 0x584 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART3_RTS_B_ALT2 + Selecting Pad: UART3_RTS_B for Mode: ALT2 + 0 + + + ENET1_RX_DATA1_ALT4 + Selecting Pad: ENET1_RX_DATA1 for Mode: ALT4 + 0x1 + + + LCD_DATA09_ALT8 + Selecting Pad: LCD_DATA09 for Mode: ALT8 + 0x2 + + + SD1_DATA1_ALT3 + Selecting Pad: SD1_DATA1 for Mode: ALT3 + 0x3 + + + + + + + FLEXCAN2_RX_SELECT_INPUT + FLEXCAN2_RX_SELECT_INPUT DAISY Register + 0x588 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART2_RTS_B_ALT2 + Selecting Pad: UART2_RTS_B for Mode: ALT2 + 0 + + + ENET1_TX_DATA0_ALT4 + Selecting Pad: ENET1_TX_DATA0 for Mode: ALT4 + 0x1 + + + LCD_DATA11_ALT8 + Selecting Pad: LCD_DATA11 for Mode: ALT8 + 0x2 + + + SD1_DATA3_ALT3 + Selecting Pad: SD1_DATA3 for Mode: ALT3 + 0x3 + + + + + + + GPT1_CAPTURE1_SELECT_INPUT + GPT1_CAPTURE1_SELECT_INPUT DAISY Register + 0x58C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO1_IO00_ALT1 + Selecting Pad: GPIO1_IO00 for Mode: ALT1 + 0 + + + UART2_TX_DATA_ALT4 + Selecting Pad: UART2_TX_DATA for Mode: ALT4 + 0x1 + + + + + + + GPT1_CAPTURE2_SELECT_INPUT + GPT1_CAPTURE2_SELECT_INPUT DAISY Register + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART2_RX_DATA_ALT4 + Selecting Pad: UART2_RX_DATA for Mode: ALT4 + 0 + + + ENET1_RX_ER_ALT8 + Selecting Pad: ENET1_RX_ER for Mode: ALT8 + 0x1 + + + + + + + GPT1_CLK_SELECT_INPUT + GPT1_CLK_SELECT_INPUT DAISY Register + 0x594 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + UART1_RX_DATA_ALT4 + Selecting Pad: UART1_RX_DATA for Mode: ALT4 + 0 + + + ENET1_TX_CLK_ALT8 + Selecting Pad: ENET1_TX_CLK for Mode: ALT8 + 0x1 + + + + + + + GPT2_CAPTURE1_SELECT_INPUT + GPT2_CAPTURE1_SELECT_INPUT DAISY Register + 0x598 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_TMS_ALT1 + Selecting Pad: JTAG_TMS for Mode: ALT1 + 0 + + + SD1_DATA2_ALT1 + Selecting Pad: SD1_DATA2 for Mode: ALT1 + 0x1 + + + + + + + GPT2_CAPTURE2_SELECT_INPUT + GPT2_CAPTURE2_SELECT_INPUT DAISY Register + 0x59C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_TDO_ALT1 + Selecting Pad: JTAG_TDO for Mode: ALT1 + 0 + + + SD1_DATA3_ALT1 + Selecting Pad: SD1_DATA3 for Mode: ALT1 + 0x1 + + + + + + + GPT2_CLK_SELECT_INPUT + GPT2_CLK_SELECT_INPUT DAISY Register + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_MOD_ALT1 + Selecting Pad: JTAG_MOD for Mode: ALT1 + 0 + + + SD1_DATA1_ALT1 + Selecting Pad: SD1_DATA1 for Mode: ALT1 + 0x1 + + + + + + + I2C1_SCL_SELECT_INPUT + I2C1_SCL_SELECT_INPUT DAISY Register + 0x5A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO02_ALT0 + Selecting Pad: GPIO1_IO02 for Mode: ALT0 + 0 + + + UART4_TX_DATA_ALT2 + Selecting Pad: UART4_TX_DATA for Mode: ALT2 + 0x1 + + + CSI_PIXCLK_ALT3 + Selecting Pad: CSI_PIXCLK for Mode: ALT3 + 0x2 + + + + + + + I2C1_SDA_SELECT_INPUT + I2C1_SDA_SELECT_INPUT DAISY Register + 0x5A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_MCLK_ALT3 + Selecting Pad: CSI_MCLK for Mode: ALT3 + 0 + + + GPIO1_IO03_ALT0 + Selecting Pad: GPIO1_IO03 for Mode: ALT0 + 0x1 + + + UART4_RX_DATA_ALT2 + Selecting Pad: UART4_RX_DATA for Mode: ALT2 + 0x2 + + + + + + + I2C2_SCL_SELECT_INPUT + I2C2_SCL_SELECT_INPUT DAISY Register + 0x5AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_HSYNC_ALT3 + Selecting Pad: CSI_HSYNC for Mode: ALT3 + 0 + + + GPIO1_IO00_ALT0 + Selecting Pad: GPIO1_IO00 for Mode: ALT0 + 0x1 + + + UART5_TX_DATA_ALT2 + Selecting Pad: UART5_TX_DATA for Mode: ALT2 + 0x2 + + + + + + + I2C2_SDA_SELECT_INPUT + I2C2_SDA_SELECT_INPUT DAISY Register + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_VSYNC_ALT3 + Selecting Pad: CSI_VSYNC for Mode: ALT3 + 0 + + + GPIO1_IO01_ALT0 + Selecting Pad: GPIO1_IO01 for Mode: ALT0 + 0x1 + + + UART5_RX_DATA_ALT2 + Selecting Pad: UART5_RX_DATA for Mode: ALT2 + 0x2 + + + + + + + I2C3_SCL_SELECT_INPUT + I2C3_SCL_SELECT_INPUT DAISY Register + 0x5B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART1_TX_DATA_ALT2 + Selecting Pad: UART1_TX_DATA for Mode: ALT2 + 0 + + + ENET2_RX_DATA0_ALT3 + Selecting Pad: ENET2_RX_DATA0 for Mode: ALT3 + 0x1 + + + LCD_DATA01_ALT4 + Selecting Pad: LCD_DATA01 for Mode: ALT4 + 0x2 + + + + + + + I2C3_SDA_SELECT_INPUT + I2C3_SDA_SELECT_INPUT DAISY Register + 0x5B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART1_RX_DATA_ALT2 + Selecting Pad: UART1_RX_DATA for Mode: ALT2 + 0 + + + ENET2_RX_DATA1_ALT3 + Selecting Pad: ENET2_RX_DATA1 for Mode: ALT3 + 0x1 + + + LCD_DATA00_ALT4 + Selecting Pad: LCD_DATA00 for Mode: ALT4 + 0x2 + + + + + + + I2C4_SCL_SELECT_INPUT + I2C4_SCL_SELECT_INPUT DAISY Register + 0x5BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART2_TX_DATA_ALT2 + Selecting Pad: UART2_TX_DATA for Mode: ALT2 + 0 + + + ENET2_RX_EN_ALT3 + Selecting Pad: ENET2_RX_EN for Mode: ALT3 + 0x1 + + + LCD_DATA03_ALT4 + Selecting Pad: LCD_DATA03 for Mode: ALT4 + 0x2 + + + + + + + I2C4_SDA_SELECT_INPUT + I2C4_SDA_SELECT_INPUT DAISY Register + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART2_RX_DATA_ALT2 + Selecting Pad: UART2_RX_DATA for Mode: ALT2 + 0 + + + ENET2_TX_DATA0_ALT3 + Selecting Pad: ENET2_TX_DATA0 for Mode: ALT3 + 0x1 + + + LCD_DATA02_ALT4 + Selecting Pad: LCD_DATA02 for Mode: ALT4 + 0x2 + + + + + + + KPP_COL0_SELECT_INPUT + KPP_COL0_SELECT_INPUT DAISY Register + 0x5C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_RX_DATA1_ALT6 + Selecting Pad: ENET1_RX_DATA1 for Mode: ALT6 + 0 + + + NAND_WE_B_ALT3 + Selecting Pad: NAND_WE_B for Mode: ALT3 + 0x1 + + + + + + + KPP_COL1_SELECT_INPUT + KPP_COL1_SELECT_INPUT DAISY Register + 0x5C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_TX_DATA0_ALT6 + Selecting Pad: ENET1_TX_DATA0 for Mode: ALT6 + 0 + + + NAND_DATA01_ALT3 + Selecting Pad: NAND_DATA01 for Mode: ALT3 + 0x1 + + + + + + + KPP_COL2_SELECT_INPUT + KPP_COL2_SELECT_INPUT DAISY Register + 0x5CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_TX_EN_ALT6 + Selecting Pad: ENET1_TX_EN for Mode: ALT6 + 0 + + + NAND_DATA03_ALT3 + Selecting Pad: NAND_DATA03 for Mode: ALT3 + 0x1 + + + + + + + KPP_ROW0_SELECT_INPUT + KPP_ROW0_SELECT_INPUT DAISY Register + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_RX_DATA0_ALT6 + Selecting Pad: ENET1_RX_DATA0 for Mode: ALT6 + 0 + + + NAND_RE_B_ALT3 + Selecting Pad: NAND_RE_B for Mode: ALT3 + 0x1 + + + + + + + KPP_ROW1_SELECT_INPUT + KPP_ROW1_SELECT_INPUT DAISY Register + 0x5D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_RX_EN_ALT6 + Selecting Pad: ENET1_RX_EN for Mode: ALT6 + 0 + + + NAND_DATA00_ALT3 + Selecting Pad: NAND_DATA00 for Mode: ALT3 + 0x1 + + + + + + + KPP_ROW2_SELECT_INPUT + KPP_ROW2_SELECT_INPUT DAISY Register + 0x5D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + ENET1_TX_DATA1_ALT6 + Selecting Pad: ENET1_TX_DATA1 for Mode: ALT6 + 0 + + + NAND_DATA02_ALT3 + Selecting Pad: NAND_DATA02 for Mode: ALT3 + 0x1 + + + + + + + LCD_BUSY_SELECT_INPUT + LCD_BUSY_SELECT_INPUT DAISY Register + 0x5DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_HSYNC_ALT0 + Selecting Pad: LCD_HSYNC for Mode: ALT0 + 0 + + + LCD_VSYNC_ALT1 + Selecting Pad: LCD_VSYNC for Mode: ALT1 + 0x1 + + + + + + + SAI1_MCLK_SELECT_INPUT + SAI1_MCLK_SELECT_INPUT DAISY Register + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + CSI_DATA01_ALT6 + Selecting Pad: CSI_DATA01 for Mode: ALT6 + 0 + + + LCD_DATA00_ALT8 + Selecting Pad: LCD_DATA00 for Mode: ALT8 + 0x1 + + + + + + + SAI1_RX_DATA_SELECT_INPUT + SAI1_RX_DATA_SELECT_INPUT DAISY Register + 0x5E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA03_ALT8 + Selecting Pad: LCD_DATA03 for Mode: ALT8 + 0 + + + CSI_DATA06_ALT6 + Selecting Pad: CSI_DATA06 for Mode: ALT6 + 0x1 + + + + + + + SAI1_TX_BCLK_SELECT_INPUT + SAI1_TX_BCLK_SELECT_INPUT DAISY Register + 0x5E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA02_ALT8 + Selecting Pad: LCD_DATA02 for Mode: ALT8 + 0 + + + CSI_DATA05_ALT6 + Selecting Pad: CSI_DATA05 for Mode: ALT6 + 0x1 + + + + + + + SAI1_TX_SYNC_SELECT_INPUT + SAI1_TX_SYNC_SELECT_INPUT DAISY Register + 0x5EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA01_ALT8 + Selecting Pad: LCD_DATA01 for Mode: ALT8 + 0 + + + CSI_DATA04_ALT6 + Selecting Pad: CSI_DATA04 for Mode: ALT6 + 0x1 + + + + + + + SAI2_MCLK_SELECT_INPUT + SAI2_MCLK_SELECT_INPUT DAISY Register + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_TMS_ALT2 + Selecting Pad: JTAG_TMS for Mode: ALT2 + 0 + + + SD1_CLK_ALT2 + Selecting Pad: SD1_CLK for Mode: ALT2 + 0x1 + + + + + + + SAI2_RX_DATA_SELECT_INPUT + SAI2_RX_DATA_SELECT_INPUT DAISY Register + 0x5F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_TCK_ALT2 + Selecting Pad: JTAG_TCK for Mode: ALT2 + 0 + + + SD1_DATA2_ALT2 + Selecting Pad: SD1_DATA2 for Mode: ALT2 + 0x1 + + + + + + + SAI2_TX_BCLK_SELECT_INPUT + SAI2_TX_BCLK_SELECT_INPUT DAISY Register + 0x5F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_TDI_ALT2 + Selecting Pad: JTAG_TDI for Mode: ALT2 + 0 + + + SD1_DATA1_ALT2 + Selecting Pad: SD1_DATA1 for Mode: ALT2 + 0x1 + + + + + + + SAI2_TX_SYNC_SELECT_INPUT + SAI2_TX_SYNC_SELECT_INPUT DAISY Register + 0x5FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_TDO_ALT2 + Selecting Pad: JTAG_TDO for Mode: ALT2 + 0 + + + SD1_DATA0_ALT2 + Selecting Pad: SD1_DATA0 for Mode: ALT2 + 0x1 + + + + + + + SAI3_MCLK_SELECT_INPUT + SAI3_MCLK_SELECT_INPUT DAISY Register + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_CLK_ALT3 + Selecting Pad: LCD_CLK for Mode: ALT3 + 0 + + + LCD_DATA09_ALT1 + Selecting Pad: LCD_DATA09 for Mode: ALT1 + 0x1 + + + + + + + SAI3_RX_DATA_SELECT_INPUT + SAI3_RX_DATA_SELECT_INPUT DAISY Register + 0x604 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_VSYNC_ALT3 + Selecting Pad: LCD_VSYNC for Mode: ALT3 + 0 + + + LCD_DATA14_ALT1 + Selecting Pad: LCD_DATA14 for Mode: ALT1 + 0x1 + + + + + + + SAI3_TX_BCLK_SELECT_INPUT + SAI3_TX_BCLK_SELECT_INPUT DAISY Register + 0x608 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_HSYNC_ALT3 + Selecting Pad: LCD_HSYNC for Mode: ALT3 + 0 + + + LCD_DATA13_ALT1 + Selecting Pad: LCD_DATA13 for Mode: ALT1 + 0x1 + + + + + + + SAI3_TX_SYNC_SELECT_INPUT + SAI3_TX_SYNC_SELECT_INPUT DAISY Register + 0x60C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_ENABLE_ALT3 + Selecting Pad: LCD_ENABLE for Mode: ALT3 + 0 + + + LCD_DATA12_ALT1 + Selecting Pad: LCD_DATA12 for Mode: ALT1 + 0x1 + + + + + + + SDMA_EVENTS0_SELECT_INPUT + SDMA_EVENTS0_SELECT_INPUT DAISY Register + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + JTAG_MOD_ALT6 + Selecting Pad: JTAG_MOD for Mode: ALT6 + 0 + + + GPIO1_IO02_ALT6 + Selecting Pad: GPIO1_IO02 for Mode: ALT6 + 0x1 + + + SD1_CMD_ALT6 + Selecting Pad: SD1_CMD for Mode: ALT6 + 0x2 + + + + + + + SDMA_EVENTS1_SELECT_INPUT + SDMA_EVENTS1_SELECT_INPUT DAISY Register + 0x614 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + JTAG_TMS_ALT6 + Selecting Pad: JTAG_TMS for Mode: ALT6 + 0 + + + NAND_DQS_ALT6 + Selecting Pad: NAND_DQS for Mode: ALT6 + 0x1 + + + + + + + SPDIF_IN_SELECT_INPUT + SPDIF_IN_SELECT_INPUT DAISY Register + 0x618 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO09_ALT2 + Selecting Pad: GPIO1_IO09 for Mode: ALT2 + 0 + + + UART1_RX_DATA_ALT8 + Selecting Pad: UART1_RX_DATA for Mode: ALT8 + 0x1 + + + LCD_DATA08_ALT1 + Selecting Pad: LCD_DATA08 for Mode: ALT1 + 0x2 + + + SD1_CLK_ALT3 + Selecting Pad: SD1_CLK for Mode: ALT3 + 0x3 + + + + + + + SPDIF_EXT_CLK_SELECT_INPUT + SPDIF_EXT_CLK_SELECT_INPUT DAISY Register + 0x61C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + LCD_DATA07_ALT4 + Selecting Pad: LCD_DATA07 for Mode: ALT4 + 0 + + + NAND_DQS_ALT8 + Selecting Pad: NAND_DQS for Mode: ALT8 + 0x1 + + + + + + + UART1_RTS_B_SELECT_INPUT + UART1_RTS_B_SELECT_INPUT DAISY Register + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO06_ALT8 + Selecting Pad: GPIO1_IO06 for Mode: ALT8 + 0 + + + GPIO1_IO07_ALT8 + Selecting Pad: GPIO1_IO07 for Mode: ALT8 + 0x1 + + + UART1_CTS_B_ALT0 + Selecting Pad: UART1_CTS_B for Mode: ALT0 + 0x2 + + + UART1_RTS_B_ALT0 + Selecting Pad: UART1_RTS_B for Mode: ALT0 + 0x3 + + + + + + + UART1_RX_DATA_SELECT_INPUT + UART1_RX_DATA_SELECT_INPUT DAISY Register + 0x624 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO02_ALT8 + Selecting Pad: GPIO1_IO02 for Mode: ALT8 + 0 + + + GPIO1_IO03_ALT8 + Selecting Pad: GPIO1_IO03 for Mode: ALT8 + 0x1 + + + UART1_TX_DATA_ALT0 + Selecting Pad: UART1_TX_DATA for Mode: ALT0 + 0x2 + + + UART1_RX_DATA_ALT0 + Selecting Pad: UART1_RX_DATA for Mode: ALT0 + 0x3 + + + + + + + UART2_RTS_B_SELECT_INPUT + UART2_RTS_B_SELECT_INPUT DAISY Register + 0x628 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + UART2_CTS_B_ALT0 + Selecting Pad: UART2_CTS_B for Mode: ALT0 + 0 + + + UART2_RTS_B_ALT0 + Selecting Pad: UART2_RTS_B for Mode: ALT0 + 0x1 + + + UART3_TX_DATA_ALT4 + Selecting Pad: UART3_TX_DATA for Mode: ALT4 + 0x2 + + + UART3_RX_DATA_ALT4 + Selecting Pad: UART3_RX_DATA for Mode: ALT4 + 0x3 + + + NAND_DATA06_ALT8 + Selecting Pad: NAND_DATA06 for Mode: ALT8 + 0x4 + + + NAND_DATA07_ALT8 + Selecting Pad: NAND_DATA07 for Mode: ALT8 + 0x5 + + + + + + + UART2_RX_DATA_SELECT_INPUT + UART2_RX_DATA_SELECT_INPUT DAISY Register + 0x62C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART2_TX_DATA_ALT0 + Selecting Pad: UART2_TX_DATA for Mode: ALT0 + 0 + + + UART2_RX_DATA_ALT0 + Selecting Pad: UART2_RX_DATA for Mode: ALT0 + 0x1 + + + NAND_DATA04_ALT8 + Selecting Pad: NAND_DATA04 for Mode: ALT8 + 0x2 + + + NAND_DATA05_ALT8 + Selecting Pad: NAND_DATA05 for Mode: ALT8 + 0x3 + + + + + + + UART3_RTS_B_SELECT_INPUT + UART3_RTS_B_SELECT_INPUT DAISY Register + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART3_CTS_B_ALT0 + Selecting Pad: UART3_CTS_B for Mode: ALT0 + 0 + + + UART3_RTS_B_ALT0 + Selecting Pad: UART3_RTS_B for Mode: ALT0 + 0x1 + + + NAND_CE1_B_ALT8 + Selecting Pad: NAND_CE1_B for Mode: ALT8 + 0x2 + + + NAND_CLE_ALT8 + Selecting Pad: NAND_CLE for Mode: ALT8 + 0x3 + + + + + + + UART3_RX_DATA_SELECT_INPUT + UART3_RX_DATA_SELECT_INPUT DAISY Register + 0x634 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART3_TX_DATA_ALT0 + Selecting Pad: UART3_TX_DATA for Mode: ALT0 + 0 + + + UART3_RX_DATA_ALT0 + Selecting Pad: UART3_RX_DATA for Mode: ALT0 + 0x1 + + + NAND_READY_B_ALT8 + Selecting Pad: NAND_READY_B for Mode: ALT8 + 0x2 + + + NAND_CE0_B_ALT8 + Selecting Pad: NAND_CE0_B for Mode: ALT8 + 0x3 + + + + + + + UART4_RTS_B_SELECT_INPUT + UART4_RTS_B_SELECT_INPUT DAISY Register + 0x638 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + ENET1_RX_DATA0_ALT1 + Selecting Pad: ENET1_RX_DATA0 for Mode: ALT1 + 0 + + + ENET1_RX_DATA1_ALT1 + Selecting Pad: ENET1_RX_DATA1 for Mode: ALT1 + 0x1 + + + LCD_HSYNC_ALT2 + Selecting Pad: LCD_HSYNC for Mode: ALT2 + 0x2 + + + LCD_VSYNC_ALT2 + Selecting Pad: LCD_VSYNC for Mode: ALT2 + 0x3 + + + + + + + UART4_RX_DATA_SELECT_INPUT + UART4_RX_DATA_SELECT_INPUT DAISY Register + 0x63C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + UART4_TX_DATA_ALT0 + Selecting Pad: UART4_TX_DATA for Mode: ALT0 + 0 + + + UART4_RX_DATA_ALT0 + Selecting Pad: UART4_RX_DATA for Mode: ALT0 + 0x1 + + + LCD_CLK_ALT2 + Selecting Pad: LCD_CLK for Mode: ALT2 + 0x2 + + + LCD_ENABLE_ALT2 + Selecting Pad: LCD_ENABLE for Mode: ALT2 + 0x3 + + + + + + + UART5_RTS_B_SELECT_INPUT + UART5_RTS_B_SELECT_INPUT DAISY Register + 0x640 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + CSI_DATA03_ALT8 + Selecting Pad: CSI_DATA03 for Mode: ALT8 + 0 + + + GPIO1_IO08_ALT8 + Selecting Pad: GPIO1_IO08 for Mode: ALT8 + 0x1 + + + GPIO1_IO09_ALT8 + Selecting Pad: GPIO1_IO09 for Mode: ALT8 + 0x2 + + + UART1_CTS_B_ALT9 + Selecting Pad: UART1_CTS_B for Mode: ALT9 + 0x3 + + + UART1_RTS_B_ALT9 + Selecting Pad: UART1_RTS_B for Mode: ALT9 + 0x4 + + + ENET1_RX_EN_ALT1 + Selecting Pad: ENET1_RX_EN for Mode: ALT1 + 0x5 + + + ENET1_TX_DATA0_ALT1 + Selecting Pad: ENET1_TX_DATA0 for Mode: ALT1 + 0x6 + + + CSI_DATA02_ALT8 + Selecting Pad: CSI_DATA02 for Mode: ALT8 + 0x7 + + + + + + + UART5_RX_DATA_SELECT_INPUT + UART5_RX_DATA_SELECT_INPUT DAISY Register + 0x644 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + CSI_DATA00_ALT8 + Selecting Pad: CSI_DATA00 for Mode: ALT8 + 0 + + + CSI_DATA01_ALT8 + Selecting Pad: CSI_DATA01 for Mode: ALT8 + 0x1 + + + GPIO1_IO04_ALT8 + Selecting Pad: GPIO1_IO04 for Mode: ALT8 + 0x2 + + + GPIO1_IO05_ALT8 + Selecting Pad: GPIO1_IO05 for Mode: ALT8 + 0x3 + + + UART1_TX_DATA_ALT9 + Selecting Pad: UART1_TX_DATA for Mode: ALT9 + 0x4 + + + UART1_RX_DATA_ALT9 + Selecting Pad: UART1_RX_DATA for Mode: ALT9 + 0x5 + + + UART5_TX_DATA_ALT0 + Selecting Pad: UART5_TX_DATA for Mode: ALT0 + 0x6 + + + UART5_RX_DATA_ALT0 + Selecting Pad: UART5_RX_DATA for Mode: ALT0 + 0x7 + + + + + + + UART6_RTS_B_SELECT_INPUT + UART6_RTS_B_SELECT_INPUT DAISY Register + 0x648 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_VSYNC_ALT8 + Selecting Pad: CSI_VSYNC for Mode: ALT8 + 0 + + + CSI_HSYNC_ALT8 + Selecting Pad: CSI_HSYNC for Mode: ALT8 + 0x1 + + + ENET1_TX_DATA1_ALT1 + Selecting Pad: ENET1_TX_DATA1 for Mode: ALT1 + 0x2 + + + ENET1_TX_EN_ALT1 + Selecting Pad: ENET1_TX_EN for Mode: ALT1 + 0x3 + + + + + + + UART6_RX_DATA_SELECT_INPUT + UART6_RX_DATA_SELECT_INPUT DAISY Register + 0x64C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_MCLK_ALT8 + Selecting Pad: CSI_MCLK for Mode: ALT8 + 0 + + + ENET2_RX_DATA0_ALT1 + Selecting Pad: ENET2_RX_DATA0 for Mode: ALT1 + 0x1 + + + ENET2_RX_DATA1_ALT1 + Selecting Pad: ENET2_RX_DATA1 for Mode: ALT1 + 0x2 + + + CSI_PIXCLK_ALT8 + Selecting Pad: CSI_PIXCLK for Mode: ALT8 + 0x3 + + + + + + + UART7_RTS_B_SELECT_INPUT + UART7_RTS_B_SELECT_INPUT DAISY Register + 0x650 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + ENET1_TX_CLK_ALT1 + Selecting Pad: ENET1_TX_CLK for Mode: ALT1 + 0 + + + ENET1_RX_ER_ALT1 + Selecting Pad: ENET1_RX_ER for Mode: ALT1 + 0x1 + + + LCD_DATA06_ALT1 + Selecting Pad: LCD_DATA06 for Mode: ALT1 + 0x2 + + + LCD_DATA07_ALT1 + Selecting Pad: LCD_DATA07 for Mode: ALT1 + 0x3 + + + + + + + UART7_RX_DATA_SELECT_INPUT + UART7_RX_DATA_SELECT_INPUT DAISY Register + 0x654 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + ENET2_RX_EN_ALT1 + Selecting Pad: ENET2_RX_EN for Mode: ALT1 + 0 + + + ENET2_TX_DATA0_ALT1 + Selecting Pad: ENET2_TX_DATA0 for Mode: ALT1 + 0x1 + + + LCD_DATA16_ALT1 + Selecting Pad: LCD_DATA16 for Mode: ALT1 + 0x2 + + + LCD_DATA17_ALT1 + Selecting Pad: LCD_DATA17 for Mode: ALT1 + 0x3 + + + + + + + UART8_RTS_B_SELECT_INPUT + UART8_RTS_B_SELECT_INPUT DAISY Register + 0x658 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + ENET2_TX_CLK_ALT1 + Selecting Pad: ENET2_TX_CLK for Mode: ALT1 + 0 + + + ENET2_RX_ER_ALT1 + Selecting Pad: ENET2_RX_ER for Mode: ALT1 + 0x1 + + + LCD_DATA04_ALT1 + Selecting Pad: LCD_DATA04 for Mode: ALT1 + 0x2 + + + LCD_DATA05_ALT1 + Selecting Pad: LCD_DATA05 for Mode: ALT1 + 0x3 + + + + + + + UART8_RX_DATA_SELECT_INPUT + UART8_RX_DATA_SELECT_INPUT DAISY Register + 0x65C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + ENET2_TX_DATA1_ALT1 + Selecting Pad: ENET2_TX_DATA1 for Mode: ALT1 + 0 + + + ENET2_TX_EN_ALT1 + Selecting Pad: ENET2_TX_EN for Mode: ALT1 + 0x1 + + + LCD_DATA20_ALT1 + Selecting Pad: LCD_DATA20 for Mode: ALT1 + 0x2 + + + LCD_DATA21_ALT1 + Selecting Pad: LCD_DATA21 for Mode: ALT1 + 0x3 + + + + + + + USB_OTG2_OC_SELECT_INPUT + USB_OTG2_OC_SELECT_INPUT DAISY Register + 0x660 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO03_ALT2 + Selecting Pad: GPIO1_IO03 for Mode: ALT2 + 0 + + + ENET2_TX_EN_ALT8 + Selecting Pad: ENET2_TX_EN for Mode: ALT8 + 0x1 + + + SD1_DATA2_ALT8 + Selecting Pad: SD1_DATA2 for Mode: ALT8 + 0x2 + + + + + + + USB_OTG_OC_SELECT_INPUT + USB_OTG_OC_SELECT_INPUT DAISY Register + 0x664 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO01_ALT2 + Selecting Pad: GPIO1_IO01 for Mode: ALT2 + 0 + + + ENET2_RX_DATA1_ALT8 + Selecting Pad: ENET2_RX_DATA1 for Mode: ALT8 + 0x1 + + + SD1_CLK_ALT8 + Selecting Pad: SD1_CLK for Mode: ALT8 + 0x2 + + + + + + + USDHC1_CD_B_SELECT_INPUT + USDHC1_CD_B_SELECT_INPUT DAISY Register + 0x668 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO03_ALT4 + Selecting Pad: GPIO1_IO03 for Mode: ALT4 + 0 + + + UART1_RTS_B_ALT2 + Selecting Pad: UART1_RTS_B for Mode: ALT2 + 0x1 + + + CSI_DATA05_ALT8 + Selecting Pad: CSI_DATA05 for Mode: ALT8 + 0x2 + + + + + + + USDHC1_WP_SELECT_INPUT + USDHC1_WP_SELECT_INPUT DAISY Register + 0x66C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO02_ALT4 + Selecting Pad: GPIO1_IO02 for Mode: ALT4 + 0 + + + UART1_CTS_B_ALT2 + Selecting Pad: UART1_CTS_B for Mode: ALT2 + 0x1 + + + CSI_DATA04_ALT8 + Selecting Pad: CSI_DATA04 for Mode: ALT8 + 0x2 + + + + + + + USDHC2_CLK_SELECT_INPUT + USDHC2_CLK_SELECT_INPUT DAISY Register + 0x670 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_VSYNC_ALT1 + Selecting Pad: CSI_VSYNC for Mode: ALT1 + 0 + + + LCD_DATA19_ALT8 + Selecting Pad: LCD_DATA19 for Mode: ALT8 + 0x1 + + + NAND_RE_B_ALT1 + Selecting Pad: NAND_RE_B for Mode: ALT1 + 0x2 + + + + + + + USDHC2_CD_B_SELECT_INPUT + USDHC2_CD_B_SELECT_INPUT DAISY Register + 0x674 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_MCLK_ALT1 + Selecting Pad: CSI_MCLK for Mode: ALT1 + 0 + + + GPIO1_IO07_ALT4 + Selecting Pad: GPIO1_IO07 for Mode: ALT4 + 0x1 + + + UART1_RTS_B_ALT8 + Selecting Pad: UART1_RTS_B for Mode: ALT8 + 0x2 + + + + + + + USDHC2_CMD_SELECT_INPUT + USDHC2_CMD_SELECT_INPUT DAISY Register + 0x678 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_HSYNC_ALT1 + Selecting Pad: CSI_HSYNC for Mode: ALT1 + 0 + + + LCD_DATA18_ALT8 + Selecting Pad: LCD_DATA18 for Mode: ALT8 + 0x1 + + + NAND_WE_B_ALT1 + Selecting Pad: NAND_WE_B for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA0_SELECT_INPUT + USDHC2_DATA0_SELECT_INPUT DAISY Register + 0x67C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_DATA00_ALT1 + Selecting Pad: CSI_DATA00 for Mode: ALT1 + 0 + + + LCD_DATA20_ALT8 + Selecting Pad: LCD_DATA20 for Mode: ALT8 + 0x1 + + + NAND_DATA00_ALT1 + Selecting Pad: NAND_DATA00 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA1_SELECT_INPUT + USDHC2_DATA1_SELECT_INPUT DAISY Register + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_DATA01_ALT1 + Selecting Pad: CSI_DATA01 for Mode: ALT1 + 0 + + + LCD_DATA21_ALT8 + Selecting Pad: LCD_DATA21 for Mode: ALT8 + 0x1 + + + NAND_DATA01_ALT1 + Selecting Pad: NAND_DATA01 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA2_SELECT_INPUT + USDHC2_DATA2_SELECT_INPUT DAISY Register + 0x684 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + LCD_DATA22_ALT8 + Selecting Pad: LCD_DATA22 for Mode: ALT8 + 0 + + + NAND_DATA02_ALT1 + Selecting Pad: NAND_DATA02 for Mode: ALT1 + 0x1 + + + CSI_DATA02_ALT1 + Selecting Pad: CSI_DATA02 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA3_SELECT_INPUT + USDHC2_DATA3_SELECT_INPUT DAISY Register + 0x688 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + CSI_DATA03_ALT1 + Selecting Pad: CSI_DATA03 for Mode: ALT1 + 0 + + + LCD_DATA23_ALT8 + Selecting Pad: LCD_DATA23 for Mode: ALT8 + 0x1 + + + NAND_DATA03_ALT1 + Selecting Pad: NAND_DATA03 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA4_SELECT_INPUT + USDHC2_DATA4_SELECT_INPUT DAISY Register + 0x68C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + LCD_DATA14_ALT8 + Selecting Pad: LCD_DATA14 for Mode: ALT8 + 0 + + + NAND_DATA04_ALT1 + Selecting Pad: NAND_DATA04 for Mode: ALT1 + 0x1 + + + CSI_DATA04_ALT1 + Selecting Pad: CSI_DATA04 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA5_SELECT_INPUT + USDHC2_DATA5_SELECT_INPUT DAISY Register + 0x690 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + LCD_DATA15_ALT8 + Selecting Pad: LCD_DATA15 for Mode: ALT8 + 0 + + + NAND_DATA05_ALT1 + Selecting Pad: NAND_DATA05 for Mode: ALT1 + 0x1 + + + CSI_DATA05_ALT1 + Selecting Pad: CSI_DATA05 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA6_SELECT_INPUT + USDHC2_DATA6_SELECT_INPUT DAISY Register + 0x694 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + LCD_DATA16_ALT8 + Selecting Pad: LCD_DATA16 for Mode: ALT8 + 0 + + + NAND_DATA06_ALT1 + Selecting Pad: NAND_DATA06 for Mode: ALT1 + 0x1 + + + CSI_DATA06_ALT1 + Selecting Pad: CSI_DATA06 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_DATA7_SELECT_INPUT + USDHC2_DATA7_SELECT_INPUT DAISY Register + 0x698 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + LCD_DATA17_ALT8 + Selecting Pad: LCD_DATA17 for Mode: ALT8 + 0 + + + NAND_DATA07_ALT1 + Selecting Pad: NAND_DATA07 for Mode: ALT1 + 0x1 + + + CSI_DATA07_ALT1 + Selecting Pad: CSI_DATA07 for Mode: ALT1 + 0x2 + + + + + + + USDHC2_WP_SELECT_INPUT + USDHC2_WP_SELECT_INPUT DAISY Register + 0x69C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO1_IO06_ALT4 + Selecting Pad: GPIO1_IO06 for Mode: ALT4 + 0 + + + UART1_CTS_B_ALT8 + Selecting Pad: UART1_CTS_B for Mode: ALT8 + 0x1 + + + CSI_PIXCLK_ALT1 + Selecting Pad: CSI_PIXCLK for Mode: ALT1 + 0x2 + + + + + + + + + IOMUXC_GPR + IOMUXC + IOMUXC_GPR + IOMUXC_GPR_ + 0x20E4000 + + 0 + 0x3C + registers + + + + GPR0 + GPR0 General Purpose Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMAREQ_MUX_SEL0 + Selects between two possible sources for SDMA_EVENT[2]: + 0 + 1 + read-write + + + DMAREQ_MUX_SEL0_0 + sim2.ipd_sim_tx_dmareq + 0 + + + DMAREQ_MUX_SEL0_1 + uart6.ipd_uart_tx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL1 + Selects between two possible sources for SDMA_EVENT[7]: + 0x1 + 1 + read-write + + + DMAREQ_MUX_SEL1_0 + sim2.ipd_sim_rx_dmareq + 0 + + + DMAREQ_MUX_SEL1_1 + uart6.ipd_uart_rx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL2 + Selects between two possible sources for SDMA_EVENT[8]: + 0x2 + 1 + read-write + + + DMAREQ_MUX_SEL2_0 + sim1.ipd_sim_tx_dmareq + 0 + + + DMAREQ_MUX_SEL2_1 + uart5.ipd_uart_tx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL3 + Selects between two possible sources for SDMA_EVENT[9]: + 0x3 + 1 + read-write + + + DMAREQ_MUX_SEL3_0 + sim1.ipd_sim_rx_dmareq + 0 + + + DMAREQ_MUX_SEL3_1 + uart5.ipd_uart_rx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL4 + Selects between two possible sources for SDMA_EVENT[10]: + 0x4 + 1 + read-write + + + DMAREQ_MUX_SEL4_0 + enet2.ipd_req_mac0_timer[1] + 0 + + + DMAREQ_MUX_SEL4_1 + uart8.ipd_uart_tx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL5 + Selects between two possible sources for SDMA_EVENT[16]: + 0x5 + 1 + read-write + + + DMAREQ_MUX_SEL5_0 + enet2.ipd_req_mac0_timer[0] + 0 + + + DMAREQ_MUX_SEL5_1 + uart8.ipd_uart_rx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL6 + Selects between two possible sources for SDMA_EVENT[24]: + 0x6 + 1 + read-write + + + DMAREQ_MUX_SEL6_0 + enet1.ipd_req_mac0_timer[1] + 0 + + + DMAREQ_MUX_SEL6_1 + uart7.ipd_uart_tx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL7 + Selects between two possible sources for SDMA_EVENT[13]: + 0x7 + 1 + read-write + + + DMAREQ_MUX_SEL7_0 + enet1.ipd_req_mac0_timer[0] + 0 + + + DMAREQ_MUX_SEL7_1 + uart7.ipd_uart_rx_dmareq + 0x1 + + + + + DMAREQ_MUX_SEL8 + Selects between two possible sources for SDMA_EVENT[43]: + 0x8 + 1 + read-write + + + DMAREQ_MUX_SEL8_0 + adc2.ipd_req + 0 + + + DMAREQ_MUX_SEL8_1 + tsc_dig.interrupt + 0x1 + + + + + DMAREQ_MUX_SEL9 + Selects between two possible sources for SDMA_EVENT[44]: + 0x9 + 1 + read-write + + + DMAREQ_MUX_SEL9_0 + gpt2.ipi_int_gpt + 0 + + + DMAREQ_MUX_SEL9_1 + lcdif.lcdif_irq + 0x1 + + + + + DMAREQ_MUX_SEL10 + Selects between two possible sources for SDMA_EVENT[45]: + 0xA + 1 + read-write + + + DMAREQ_MUX_SEL10_0 + epit1.ipi_int_epit_oc + 0 + + + DMAREQ_MUX_SEL10_1 + csi.ipi_csi_int + 0x1 + + + + + DMAREQ_MUX_SEL11 + Selects between two possible sources for SDMA_EVENT[46]: + 0xB + 1 + read-write + + + DMAREQ_MUX_SEL11_0 + ecspi4.ipd_req_cspi_tdma + 0 + + + DMAREQ_MUX_SEL11_1 + i2c4.ipi_int + 0x1 + + + + + DMAREQ_MUX_SEL12 + Selects between two possible sources for SDMA_EVENT[33]: + 0xC + 1 + read-write + + + DMAREQ_MUX_SEL12_0 + ecspi4.ipd_req_cspi_rdma + 0 + + + DMAREQ_MUX_SEL12_1 + i2c3.ipi_int + 0x1 + + + + + DMAREQ_MUX_SEL13 + Selects between two possible sources for SDMA_EVENT[34]: + 0xD + 1 + read-write + + + DMAREQ_MUX_SEL13_0 + ecspi3.ipd_req_cspi_tdma + 0 + + + DMAREQ_MUX_SEL13_1 + i2c2.ipi_int + 0x1 + + + + + DMAREQ_MUX_SEL14 + Selects between two possible sources for SDMA_EVENT[0]: + 0xE + 1 + read-write + + + DMAREQ_MUX_SEL14_0 + ecspi3.ipd_req_cspi_rdma + 0 + + + DMAREQ_MUX_SEL14_1 + i2c1.ipi_int + 0x1 + + + + + DMAREQ_MUX_SEL15 + Selects between two possible sources for SDMA_EVENT[47]: + 0xF + 1 + read-write + + + DMAREQ_MUX_SEL15_0 + epit2.ipi_int_epit_oc + 0 + + + DMAREQ_MUX_SEL15_1 + pxp.pxp_irq + 0x1 + + + + + DMAREQ_MUX_SEL16 + Selects between two possible sources for SDMA_EVENT[32]: + 0x10 + 1 + read-write + + + DMAREQ_MUX_SEL16_0 + uart4.ipd_uart_tx_dmareq_b (default) + 0 + + + DMAREQ_MUX_SEL16_1 + sai1.ipd_req_sai_tx + 0x1 + + + + + DMAREQ_MUX_SEL17 + Selects between two possible sources for SDMA_EVENT[33]: + 0x11 + 1 + read-write + + + DMAREQ_MUX_SEL17_0 + uart5.ipd_uart_rx_dmareq_b (default) + 0 + + + DMAREQ_MUX_SEL17_1 + sai2.ipd_req_sai_rx + 0x1 + + + + + DMAREQ_MUX_SEL18 + Selects between two possible sources for SDMA_EVENT[34]: + 0x12 + 1 + read-write + + + DMAREQ_MUX_SEL18_0 + uart5.ipd_uart_tx_dmareq_b (default) + 0 + + + DMAREQ_MUX_SEL18_1 + sai2.ipd_req_sai_tx + 0x1 + + + + + DMAREQ_MUX_SEL19 + Selects between two possible sources for SDMA_EVENT[47]: + 0x13 + 1 + read-write + + + DMAREQ_MUX_SEL19_0 + uart6.ipd_uart_tx_dmareq_b (default) + 0 + + + + + DMAREQ_MUX_SEL20 + Selects between two possible sources for SDMA_EVENT[2]: + 0x14 + 1 + read-write + + + DMAREQ_MUX_SEL20_0 + iomux_top.sdma_events[14] (default) + 0 + + + DMAREQ_MUX_SEL20_1 + csi2.ipi_csi_int_b + 0x1 + + + + + DMAREQ_MUX_SEL21 + Selects between two possible sources for SDMA_EVENT[29]: + 0x15 + 1 + read-write + + + DMAREQ_MUX_SEL21_0 + uart3.ipd_uart_rx_dmareq_b (default) + 0 + + + + + DMAREQ_MUX_SEL22 + Selects between two possible sources for SDMA_EVENT[30]: + 0x16 + 1 + read-write + + + DMAREQ_MUX_SEL22_0 + uart3.ipd_uart_tx_dmareq_b (default) + 0 + + + + + + + GPR1 + GPR1 General Purpose Register + 0x4 + 32 + read-write + 0xF400005 + 0xFFFFFFFF + + + ACT_CS0 + See description for ADDRS3[10] + 0 + 1 + read-write + + + ADDRS0 + See description for ADDRS3[10] + 0x1 + 2 + read-write + + + ACT_CS1 + See description for ADDRS3[10] + 0x3 + 1 + read-write + + + ADDRS1 + See description for ADDRS3[10] + 0x4 + 2 + read-write + + + ACT_CS2 + See description for ADDRS3[10] + 0x6 + 1 + read-write + + + ADDRS2 + See description for ADDRS3[10] + 0x7 + 2 + read-write + + + ACT_CS3 + See description for ADDRS3[10] + 0x9 + 1 + read-write + + + ADDRS3 + Active Chip Select and Address Space + 0xA + 2 + read-write + + + ADDRS3_0 + 32 MByte + 0 + + + ADDRS3_1 + 64 MByte + 0x1 + + + ADDRS3_2 + 128 MByte + 0x2 + + + + + GINT + Global interrupt "0" bit (connected to ARM A7 IRQ#0 and GPC) + 0xC + 1 + read-write + + + GINT_0 + Global interrupt request is not asserted + 0 + + + GINT_1 + Global interrupt request is asserted + 0x1 + + + + + ENET1_CLK_SEL + ENET1 reference clock mode select. + 0xD + 1 + read-write + + + ENET1_CLK_SEL_0 + ENET1 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. + 0 + + + ENET1_CLK_SEL_1 + Gets ENET1 TX reference clk from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller + 0x1 + + + + + ENET2_CLK_SEL + ENET2 reference clock mode select. + 0xE + 1 + read-write + + + ENET2_CLK_SEL_0 + ENET2 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET_REF_CLK2 function. + 0 + + + ENET2_CLK_SEL_1 + Gets ENET2 TX reference clk from the ENET2_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller + 0x1 + + + + + USB_EXP_MODE + USB Exposure mode + 0xF + 1 + read-write + + + USB_EXP_MODE_0 + Exposure mode is disabled. + 0 + + + USB_EXP_MODE_1 + Exposure mode is enabled. + 0x1 + + + + + ADD_DS + Setting ADD_DS to 0 will make the output driver of the SD3 pins ~10% stronger at highest drive strength (DSE=111). This is for use if the I/O buffer operation at WCS and 200 MHz is marginal. + 0x10 + 1 + read-write + + + ADD_DS_0 + output driver ~10% stronger + 0 + + + ADD_DS_1 + output driver is normal + 0x1 + + + + + ENET1_TX_CLK_DIR + ENET1_TX_CLK data direction control when anatop. ENET_REF_CLK1 is selected (ALT1) + 0x11 + 1 + read-write + + + ENET1_TX_CLK_DIR_0 + ENET1_TX_CLK output driver is disabled when configured for ALT1 + 0 + + + ENET1_TX_CLK_DIR_1 + ENET1_TX_CLK output driver is enabled when configured for ALT1 + 0x1 + + + + + ENET2_TX_CLK_DIR + ENET2_TX_CLK data direction control when anatop. ENET_REF_CLK2 is selected (ALT1) + 0x12 + 1 + read-write + + + ENET2_TX_CLK_DIR_0 + ENET2_TX_CLK output driver is disabled when configured for ALT1 + 0 + + + ENET2_TX_CLK_DIR_1 + ENET2_TX_CLK output driver is enabled when configured for ALT1 + 0x1 + + + + + SAI1_MCLK_DIR + LCD_DATA00 data direction control when sai1.MCLK is selected (ALT8) + 0x13 + 1 + read-write + + + SAI1_MCLK_DIR_0 + LCD_DATA00 output driver is disabled when configured for ALT8 + 0 + + + SAI1_MCLK_DIR_1 + LCD_DATA00 output driver is enabled when configured for ALT8 + 0x1 + + + + + SAI2_MCLK_DIR + SD1_CLK data direction control when sai2.MCLK is selected (ALT2) + 0x14 + 1 + read-write + + + SAI2_MCLK_DIR_0 + SD1_CLK output driver is disabled when configured for ALT2 + 0 + + + SAI2_MCLK_DIR_1 + SD1_CLK output driver is enabled when configured for ALT2 + 0x1 + + + + + SAI3_MCLK_DIR + LCD_CLK data direction control when sai3.MCLK is selected (ALT3) + 0x15 + 1 + read-write + + + SAI3_MCLK_DIR_0 + LCD_CLK output driver is disabled when configured for ALT3 + 0 + + + SAI3_MCLK_DIR_1 + LCD_CLK output driver is enabled when configured for ALT3 + 0x1 + + + + + EXC_MON + Exclusive monitor response select of illegal command + 0x16 + 1 + read-write + + + EXC_MON_0 + OKAY response + 0 + + + EXC_MON_1 + SLVError response (default) + 0x1 + + + + + TZASC1_BOOT_LOCK + TZASC-1 secure boot lock + 0x17 + 1 + read-write + + + TZASC1_BOOT_LOCK_0 + secure boot lock is disabled + 0 + + + TZASC1_BOOT_LOCK_1 + secure boot lock is enabled + 0x1 + + + + + ARMA7_CLK_APB_DBG_EN + ARM A7 platform APB clock enable + 0x18 + 1 + read-write + + + ARMA7_CLK_APB_DBG_EN_0 + APB clock is not running (gated) + 0 + + + ARMA7_CLK_APB_DBG_EN_1 + APB clock is running (enabled) + 0x1 + + + + + ARMA7_CLK_ATB_EN + ARM A7 platform ATB clock enable + 0x19 + 1 + read-write + + + ARMA7_CLK_ATB_EN_0 + ATB clock is not running (gated) + 0 + + + ARMA7_CLK_ATB_EN_1 + ATB clock is running (enabled) + 0x1 + + + + + ARMA7_CLK_AHB_EN + ARM A7 platform AHB clock enable + 0x1A + 1 + read-write + + + ARMA7_CLK_AHB_EN_0 + AHB clock is not running (gated) + 0 + + + ARMA7_CLK_AHB_EN_1 + AHB clock is running (enabled) + 0x1 + + + + + + + GPR2 + GPR2 General Purpose Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PXP_MEM_EN_POWERSAVING + enable power saving features on PXP memory + 0 + 1 + read-write + + + PXP_MEM_EN_POWERSAVING_0 + none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + 0 + + + PXP_MEM_EN_POWERSAVING_1 + memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels + 0x1 + + + + + PXP_MEM_SHUTDOWN + set to bring memory to shutdown state (most power saving state, Shut Down periphery and core, no memory retention) + 0x1 + 1 + read-write + + + PXP_MEM_DEEPSLEEP + control how memory enter Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low) + 0x2 + 1 + read-write + + + PXP_MEM_DEEPSLEEP_0 + no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + 0 + + + PXP_MEM_DEEPSLEEP_1 + force memory into deep sleep mode + 0x1 + + + + + PXP_MEM_LIGHTSLEEP + set to bring memory to light sleep state (Low leakage mode, maintain memory contents, no change to memory output) + 0x3 + 1 + read-write + + + LCDIF1_MEM_EN_POWERSAVING + enable power saving features on LCDIF memory + 0x4 + 1 + read-write + + + LCDIF1_MEM_EN_POWERSAVING_0 + none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + 0 + + + LCDIF1_MEM_EN_POWERSAVING_1 + memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels + 0x1 + + + + + LCDIF1_MEM_SHUTDOWN + set to bring memory to shutdown state (most power saving state, Shut Down periphery and core, no memory retention) + 0x5 + 1 + read-write + + + LCDIF1_MEM_DEEPSLEEP + control how memory enter Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low) + 0x6 + 1 + read-write + + + LCDIF1_MEM_DEEPSLEEP_0 + no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + 0 + + + LCDIF1_MEM_DEEPSLEEP_1 + force memory into deep sleep mode + 0x1 + + + + + LCDIF1_MEM_LIGHTSLEEP + set to bring memory to light sleep state (Low leakage mode, maintain memory contents, no change to memory output) + 0x7 + 1 + read-write + + + LCDIF2_MEM_EN_POWERSAVING + enable power saving features on LCDIF memory + 0x8 + 1 + read-write + + + LCDIF2_MEM_EN_POWERSAVING_0 + none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + 0 + + + LCDIF2_MEM_EN_POWERSAVING_1 + memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels + 0x1 + + + + + LCDIF2_MEM_SHUTDOWN + set to bring memory to shutdown state (most power saving state, Shut Down periphery and core, no memory retention) + 0x9 + 1 + read-write + + + LCDIF2_MEM_DEEPSLEEP + control how memory enter Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low) + 0xA + 1 + read-write + + + LCDIF2_MEM_DEEPSLEEP_0 + no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + 0 + + + LCDIF2_MEM_DEEPSLEEP_1 + force memory into deep sleep mode + 0x1 + + + + + LCDIF2_MEM_LIGHTSLEEP + set to bring memory to light sleep state (Low leakage mode, maintain memory contents, no change to memory output) + 0xB + 1 + read-write + + + L2_MEM_EN_POWERSAVING + enable power saving features on L2 memory + 0xC + 1 + read-write + + + L2_MEM_EN_POWERSAVING_0 + none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + 0 + + + L2_MEM_EN_POWERSAVING_1 + memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels + 0x1 + + + + + L2_MEM_SHUTDOWN + set to bring memory to shutdown state (most power saving state, Shut Down periphery and core, no memory retention) + 0xD + 1 + read-write + + + L2_MEM_DEEPSLEEP + control how memory enter Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low) + 0xE + 1 + read-write + + + L2_MEM_DEEPSLEEP_0 + no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + 0 + + + L2_MEM_DEEPSLEEP_1 + force memory into deep sleep mode + 0x1 + + + + + L2_MEM_LIGHTSLEEP + set to bring memory to light sleep state (Low leakage mode, maintain memory contents, no change to memory output) + 0xF + 1 + read-write + + + MQS_CLK_DIV + Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency. + 0x10 + 8 + read-write + + + MQS_CLK_DIV_0 + mclk frequency = hmclk frequency + 0 + + + MQS_CLK_DIV_1 + mclk frequency = 1/2 * hmclk frequency + 0x1 + + + MQS_CLK_DIV_2 + mclk frequency = 1/3 * hmclk frequency + 0x2 + + + MQS_CLK_DIV_255 + mclk frequency = 1/256 * hmclk frequency + 0xFF + + + + + MQS_SW_RST + MQS software reset. + 0x18 + 1 + read-write + + + MQS_SW_RST_0 + Exit software reset for MQS + 0 + + + MQS_SW_RST_1 + Enable software reset for MQS + 0x1 + + + + + MQS_EN + MQS enable. + 0x19 + 1 + read-write + + + MQS_EN_0 + Disable MQS + 0 + + + MQS_EN_1 + Enable MQS + 0x1 + + + + + MQS_OVERSAMPLE + Used to control the PWM oversampling rate compared with mclk. + 0x1A + 1 + read-write + + + MQS_OVERSAMPLE_0 + 32 + 0 + + + MQS_OVERSAMPLE_1 + 64 + 0x1 + + + + + DRAM_RESET_BYPASS + DRAM Reset Bypass Select + 0x1B + 1 + read-write + + + DRAM_RESET_BYPASS_0 + DRAM reset driven by MMDC PHY Controller + 0 + + + DRAM_RESET_BYPASS_1 + DRAM reset driven by GPR2 register bit [28] + 0x1 + + + + + DRAM_RESET + DRAM Reset Value + 0x1C + 1 + read-write + + + DRAM_RESET_0 + Drive DRAM reset with 0 + 0 + + + DRAM_RESET_1 + Drive DRAM reset with 1 + 0x1 + + + + + DRAM_CKE0 + CKE0 Bypass Value + 0x1D + 1 + read-write + + + DRAM_CKE0_0 + Drive CKE0 with 0 + 0 + + + DRAM_CKE0_1 + Drive CKE0 with 1 + 0x1 + + + + + DRAM_CKE1 + CKE1 Bypass Value + 0x1E + 1 + read-write + + + DRAM_CKE1_0 + Drive CKE1 with 0 + 0 + + + DRAM_CKE1_1 + Drive CKE1 with 1 + 0x1 + + + + + DRAM_CKE_BYPASS + DRAM CKE Bypass Select + 0x1F + 1 + read-write + + + DRAM_CKE_BYPASS_0 + DRAM CKE1, CKE0 driven by MMDC PHY Controller + 0 + + + DRAM_CKE_BYPASS_1 + DRAM CKE1, CKE0 driven by GPR2 register bits [30:29] + 0x1 + + + + + + + GPR3 + GPR3 General Purpose Register + 0xC + 32 + read-write + 0xFFF + 0xFFFFFFFF + + + OCRAM_CTL + OCRAM_CTL[3] write address pipeline control bit + 0 + 4 + read-write + + + OCRAM_CTL_0 + read data pipeline is disabled + 0 + + + OCRAM_CTL_1 + read data pipeline is enabled + 0x1 + + + + + CORE_DBG_ACK_EN + Mask control of Core debug acknowledge to global debug acknowledge + 0xD + 1 + read-write + + + CORE_DBG_ACK_EN_0 + Core debug acknowledge is part of global acknowledge. + 0 + + + CORE_DBG_ACK_EN_1 + Core debug acknowledge is masked by this bit, and it is not part of global acknowledge. + 0x1 + + + + + OCRAM_STATUS + This field shows the OCRAM pipeline settings status, controlled by OCRAM_CTL[24:21] bits respectively + 0x10 + 4 + read-only + + + OCRAM_STATUS_0 + read data pipeline configuration valid + 0 + + + OCRAM_STATUS_1 + read data pipeline control bit changed + 0x1 + + + + + + + GPR4 + GPR4 General Purpose Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDMA_STOP_REQ + SDMA stop request. + 0 + 1 + read-only + + + SDMA_STOP_REQ_0 + stop request off + 0 + + + SDMA_STOP_REQ_1 + stop request on + 0x1 + + + + + CAN1_STOP_REQ + CAN1 stop request. + 0x1 + 1 + read-only + + + CAN1_STOP_REQ_0 + stop request off + 0 + + + CAN1_STOP_REQ_1 + stop request on + 0x1 + + + + + CAN2_STOP_REQ + CAN2 stop request. + 0x2 + 1 + read-only + + + CAN2_STOP_REQ_0 + stop request off + 0 + + + CAN2_STOP_REQ_1 + stop request on + 0x1 + + + + + ENET1_STOP_REQ + ENET1 stop request. + 0x3 + 1 + read-only + + + ENET1_STOP_REQ_0 + stop request off + 0 + + + ENET1_STOP_REQ_1 + stop request on + 0x1 + + + + + ENET2_STOP_REQ + ENET2 stop request. + 0x4 + 1 + read-only + + + ENET2_STOP_REQ_0 + stop request off + 0 + + + ENET2_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI1_STOP_REQ + SAI1 stop request. + 0x5 + 1 + read-only + + + SAI1_STOP_REQ_0 + stop request off + 0 + + + SAI1_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI2_STOP_REQ + SAI2 stop request. + 0x6 + 1 + read-only + + + SAI2_STOP_REQ_0 + stop request off + 0 + + + SAI2_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI3_STOP_REQ + SAI3 stop request. + 0x7 + 1 + read-only + + + SAI3_STOP_REQ_0 + stop request off + 0 + + + SAI3_STOP_REQ_1 + stop request on + 0x1 + + + + + ENET_IPG_CLK_S_EN + ENET ipg_clk_s clock gating enable + 0x8 + 1 + read-write + + + ENET_IPG_CLK_S_EN_0 + ipg_clk_s is gated when there's no IPS access + 0 + + + ENET_IPG_CLK_S_EN_1 + ipg_clk_s is always on + 0x1 + + + + + SDMA_STOP_ACK + SDMA stop acknowledge. This is a status (read-only) bit + 0x10 + 1 + read-only + + + SDMA_STOP_ACK_0 + SDMA stop acknowledge is not asserted + 0 + + + SDMA_STOP_ACK_1 + SDMA stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + CAN1_STOP_ACK + CAN1 stop acknowledge. This is a status (read-only) bit + 0x11 + 1 + read-only + + + CAN1_STOP_ACK_0 + CAN1 stop acknowledge is not asserted + 0 + + + CAN1_STOP_ACK_1 + CAN1 stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + CAN2_STOP_ACK + CAN2 stop acknowledge. This is a status (read-only) bit + 0x12 + 1 + read-only + + + CAN2_STOP_ACK_0 + CAN2 stop acknowledge is not asserted + 0 + + + CAN2_STOP_ACK_1 + CAN2 stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + ENET1_STOP_ACK + ENET1 stop acknowledge. This is a status (read-only) bit + 0x13 + 1 + read-only + + + ENET1_STOP_ACK_0 + ENET1 stop acknowledge is not asserted + 0 + + + ENET1_STOP_ACK_1 + ENET1 stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + ENET2_STOP_ACK + ENET2 stop acknowledge. This is a status (read-only) bit + 0x14 + 1 + read-only + + + ENET2_STOP_ACK_0 + ENET2 stop acknowledge is not asserted + 0 + + + ENET2_STOP_ACK_1 + ENET2 stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + SAI1_STOP_ACK + SAI1 stop acknowledge. This is a status (read-only) bit + 0x15 + 1 + read-only + + + SAI1_STOP_ACK_0 + SAI1 stop acknowledge is not asserted + 0 + + + SAI1_STOP_ACK_1 + SAI1 stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + SAI2_STOP_ACK + SAI2 stop acknowledge. This is a status (read-only) bit + 0x16 + 1 + read-only + + + SAI2_STOP_ACK_0 + SAI2 stop acknowledge is not asserted + 0 + + + SAI2_STOP_ACK_1 + SAI2 stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + SAI3_STOP_ACK + SAI3 stop acknowledge. This is a status (read-only) bit + 0x17 + 1 + read-only + + + SAI3_STOP_ACK_0 + SAI3 stop acknowledge is not asserted + 0 + + + SAI3_STOP_ACK_1 + SAI3 stop acknowledge is asserted, SDMA is in STOP mode + 0x1 + + + + + ARM_WFI + ARM A7 WFI event out indicating on WFI state of the cores (these are status, read only bits) + 0x1E + 1 + read-only + + + ARM_WFI_0 + ARM Core[GPR5-index] is not in WFI mode + 0 + + + ARM_WFI_1 + ARM Core[GPR5-index] is in WFI mode + 0x1 + + + + + ARM_WFE + ARM A7 WFE event out indication on WFE state of the cores (these are status, read only bits) + 0x1F + 1 + read-only + + + ARM_WFE_0 + ARM Core[GPR5-index - 4] is not in WFE mode + 0 + + + ARM_WFE_1 + ARM Core[GPR5-index - 4] is in WFE mode + 0x1 + + + + + + + GPR5 + GPR5 General Purpose Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDOG1_MASK + WDOG1 Timeout Mask + 0x6 + 1 + read-write + + + WDOG1_MASK_0 + WDOG1 Timeout behaves normally + 0 + + + WDOG1_MASK_1 + WDOG1 Timeout is masked + 0x1 + + + + + WDOG2_MASK + WDOG2 Timeout Mask + 0x7 + 1 + read-write + + + WDOG2_MASK_0 + WDOG2 Timeout behaves normally + 0 + + + WDOG2_MASK_1 + WDOG2 Timeout is masked + 0x1 + + + + + WDOG3_MASK + WDOG3 Timeout Mask + 0x14 + 1 + read-write + + + WDOG3_MASK_0 + WDOG3 Timeout behaves normally + 0 + + + WDOG3_MASK_1 + WDOG3 Timeout is masked + 0x1 + + + + + GPT2_CAPIN1_SEL + GPT2 input capture channel 1 source select + 0x17 + 1 + read-write + + + GPT2_CAPIN1_SEL_0 + source from pad + 0 + + + GPT2_CAPIN1_SEL_1 + source from enet1.ipp_do_mac0_timer[3] + 0x1 + + + + + GPT2_CAPIN2_SEL + GPT2 input capture channel 2 source select + 0x18 + 1 + read-write + + + GPT2_CAPIN2_SEL_0 + source from pad + 0 + + + GPT2_CAPIN2_SEL_1 + source from enet2.ipp_do_mac0_timer[3] + 0x1 + + + + + ENET1_EVENT3IN_SEL + ENET1 input timer event3 source select + 0x19 + 1 + read-write + + + ENET1_EVENT3IN_SEL_0 + event3 source input from pad + 0 + + + ENET1_EVENT3IN_SEL_1 + event3 source input from gpt2.ipp_do_cmpout1 + 0x1 + + + + + ENET2_EVENT3IN_SEL + ENET2 input timer event3 source select + 0x1A + 1 + read-write + + + ENET2_EVENT3IN_SEL_0 + event3 source input from pad + 0 + + + ENET2_EVENT3IN_SEL_1 + event3 source input from gpt2.ipp_do_cmpout2 + 0x1 + + + + + VREF_1M_CLK_GPT1 + GPT1 1 MHz clock source select + 0x1C + 1 + read-write + + + VREF_1M_CLK_GPT1_0 + GPT1 ipg_clk_highfreq driven by IPG_PERCLK + 0 + + + VREF_1M_CLK_GPT1_1 + GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock + 0x1 + + + + + VREF_1M_CLK_GPT2 + GPT2 1 MHz clock source select + 0x1D + 1 + read-write + + + VREF_1M_CLK_GPT2_0 + GPT2 ipg_clk_highfreq driven by IPG_PERCLK + 0 + + + VREF_1M_CLK_GPT2_1 + GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock + 0x1 + + + + + REF_1M_CLK_EPIT1 + EPIT1 1 MHz clock source select + 0x1E + 1 + read-write + + + REF_1M_CLK_EPIT1_0 + EPIT1 ipg_clk_highfreq driven by IPG_PERCLK + 0 + + + REF_1M_CLK_EPIT1_1 + EPIT1 ipg_clk highfreq driven by anatop 1 MHz clock + 0x1 + + + + + REF_1M_CLK_EPIT2 + EPIT2 1 MHz clock source select + 0x1F + 1 + read-write + + + REF_1M_CLK_EPIT2_0 + EPIT2 ipg_clk_highfreq driven by IPG_PERCLK + 0 + + + REF_1M_CLK_EPIT2_1 + EPIT2 ipg_clk_highfreq driven by anatop 1 MHz clock + 0x1 + + + + + + + GPR9 + GPR9 General Purpose Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + TZASC1_BYP + TZASC-1 BYPASS MUX control + 0 + 1 + read-only + + + TZASC1_BYP_0 + The TZASC-1 is bypassed and the transactions to DDR are not being checked. + 0 + + + TZASC1_BYP_1 + The TZASC-1 is not bypassed and the transactions to DDR are being monitored / checked. + 0x1 + + + + + + + GPR10 + GPR10 General Purpose Register + 0x28 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + DBG_EN + ARM non secure (non-invasive) debug enable + 0 + 1 + read-write + + + DBG_EN_0 + Debug turned off. + 0 + + + DBG_EN_1 + Debug enabled (default). + 0x1 + + + + + DBG_CLK_EN + ARM Debug clock enable + 0x1 + 1 + read-write + + + DBG_CLK_EN_0 + Debug turned off. + 0 + + + DBG_CLK_EN_1 + Debug enabled (default). + 0x1 + + + + + SEC_ERR_RESP + Security error response enable for all security gaskets (on both AHB and AXI busses) + 0x2 + 1 + read-write + + + SEC_ERR_RESP_0 + OKEY response + 0 + + + SEC_ERR_RESP_1 + SLVError (default) + 0x1 + + + + + OCRAM_TZ_EN + OCRAM TrustZone (TZ) enable. + 0xA + 1 + read-write + + + OCRAM_TZ_EN_0 + The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). + 0 + + + OCRAM_TZ_EN_1 + The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. + 0x1 + + + + + OCRAM_TZ_ADDR + OCRAM TrustZone (TZ) start address + 0xB + 5 + read-write + + + + + GPR14 + GPR14 General Purpose Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General purpose bits + 0x2 + 30 + read-write + + + + + + + SDMAARM + SDMA + SDMAARM + SDMAARM_ + 0x20EC000 + + 0 + 0x2C0 + registers + + + SDMA + 34 + + + + MC0PTR + ARM platform Channel 0 Pointer + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MC0PTR + Channel 0 Pointer contains the 32-bit address, in ARM platform memory, of channel 0 control block (the boot channel) + 0 + 32 + read-write + + + + + INTR + Channel Interrupts + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + HI + The ARM platform Interrupts register contains the 32 HI[i] bits + 0 + 32 + read-write + oneToClear + + + + + STOP_STAT + Channel Stop/Channel Status + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HE + This 32-bit register gives access to the ARM platform Enable bits + 0 + 32 + read-write + oneToClear + + + + + HSTART + Channel Start + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + HSTART_HE + The HSTART_HE registers are 32 bits wide with one bit for every channel + 0 + 32 + read-write + oneToClear + + + + + EVTOVR + Channel Event Override + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + EO + The Channel Event Override register contains the 32 EO[i] bits + 0 + 32 + read-write + + + + + DSPOVR + Channel BP Override + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DO + This register is reserved + 0 + 32 + read-write + + + DO_0 + - Reserved + 0 + + + DO_1 + - Reset value. + 0x1 + + + + + + + HOSTOVR + Channel ARM platform Override + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + HO + The Channel ARM platform Override register contains the 32 HO[i] bits + 0 + 32 + read-write + + + + + EVTPEND + Channel Event Pending + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + EP + The Channel Event Pending register contains the 32 EP[i] bits + 0 + 32 + read-write + oneToClear + + + + + RESET + Reset Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESET + When set, this bit causes the SDMA to be held in a software reset + 0 + 1 + read-only + + + RESCHED + When set, this bit forces the SDMA to reschedule as if a script had executed a done instruction + 0x1 + 1 + read-only + + + + + EVTERR + DMA Request Error Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + CHNERR + This register is used by the SDMA to warn the ARM platform when an incoming DMA request was detected and it triggers a channel that is already pending or being serviced + 0 + 32 + read-only + + + + + INTRMASK + Channel ARM platform Interrupt Mask + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + HIMASK + The Interrupt Mask Register contains 32 interrupt generation mask bits + 0 + 32 + read-write + + + + + PSW + Schedule Status + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + CCR + The Current Channel Register indicates the number of the channel that is being executed by the SDMA + 0 + 4 + read-only + + + CCP + The Current Channel Priority indicates the priority of the current active channel + 0x4 + 4 + read-only + + + CCP_0 + No running channel + 0 + + + CCP_1 + Active channel priority + 0x1 + + + + + NCR + The Next Channel Register indicates the number of the next scheduled pending channel with the highest priority + 0x8 + 5 + read-only + + + NCP + The Next Channel Priority gives the next pending channel priority + 0xD + 3 + read-only + + + NCP_0 + No running channel + 0 + + + NCP_1 + Active channel priority + 0x1 + + + + + + + EVTERRDBG + DMA Request Error Register + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + CHNERR + This register is the same as EVTERR, except reading it does not clear its contents + 0 + 32 + read-only + + + + + CONFIG + Configuration Register + 0x38 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + CSM + Selects the Context Switch Mode + 0 + 2 + read-write + + + CSM_0 + static + 0 + + + CSM_1 + dynamic low power + 0x1 + + + CSM_2 + dynamic with no loop + 0x2 + + + CSM_3 + dynamic + 0x3 + + + + + ACR + ARM platform DMA / SDMA Core Clock Ratio + 0x4 + 1 + read-write + + + ACR_0 + ARM platform DMA interface frequency equals twice core frequency + 0 + + + ACR_1 + ARM platform DMA interface frequency equals core frequency + 0x1 + + + + + RTDOBS + Indicates if Real-Time Debug pins are used: They do not toggle by default in order to reduce power consumption + 0xB + 1 + read-write + + + RTDOBS_0 + RTD pins disabled + 0 + + + RTDOBS_1 + RTD pins enabled + 0x1 + + + + + DSPDMA + This bit's function is reserved and should be configured as zero. + 0xC + 1 + read-write + + + DSPDMA_0 + - Reset Value + 0 + + + DSPDMA_1 + - Reserved + 0x1 + + + + + + + SDMA_LOCK + SDMA LOCK + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK + The LOCK bit is used to restrict access to update SDMA script memory through ROM channel zero scripts and through the OnCE interface under ARM platform control + 0 + 1 + read-write + + + LOCK_0 + LOCK disengaged. + 0 + + + LOCK_1 + LOCK enabled. + 0x1 + + + + + SRESET_LOCK_CLR + The SRESET_LOCK_CLR bit determine if the LOCK bit is cleared on a software reset triggered by writing to the RESET register + 0x1 + 1 + read-write + + + SRESET_LOCK_CLR_0 + Software Reset does not clear the LOCK bit. + 0 + + + SRESET_LOCK_CLR_1 + Software Reset clears the LOCK bit. + 0x1 + + + + + + + ONCE_ENB + OnCE Enable + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENB + The OnCE Enable register selects the OnCE control source: When cleared (0), the OnCE registers are accessed through the JTAG interface; when set (1), the OnCE registers may be accessed by the ARM platform through the addresses described, as follows + 0 + 1 + read-write + + + + + ONCE_DATA + OnCE Data Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data register of the OnCE JTAG controller + 0 + 32 + read-write + + + + + ONCE_INSTR + OnCE Instruction Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + INSTR + Instruction register of the OnCE JTAG controller + 0 + 16 + read-write + + + + + ONCE_STAT + OnCE Status Register + 0x4C + 32 + read-only + 0xE000 + 0xFFFFFFFF + + + ECDR + Event Cell Debug Request + 0 + 3 + read-only + + + ECDR_0 + 1 matched addra_cond + 0 + + + ECDR_1 + 1 matched addrb_cond + 0x1 + + + ECDR_2 + 1 matched data_cond + 0x2 + + + + + MST + This flag is raised when the OnCE is controlled from the ARM platform peripheral interface. + 0x7 + 1 + read-only + + + MST_0 + The JTAG interface controls the OnCE. + 0 + + + MST_1 + The ARM platform peripheral interface controls the OnCE. + 0x1 + + + + + SWB + This flag is raised when the SDMA has entered debug mode after a software breakpoint. + 0x8 + 1 + read-only + + + ODR + This flag is raised when the SDMA has entered debug mode after a OnCE debug request. + 0x9 + 1 + read-only + + + EDR + This flag is raised when the SDMA has entered debug mode after an external debug request. + 0xA + 1 + read-only + + + RCV + After each write access to the real time buffer (RTB), the RCV bit is set + 0xB + 1 + read-only + + + PST + The Processor Status bits reflect the state of the SDMA RISC engine + 0xC + 4 + read-only + + + PST_0 + Program + 0 + + + PST_1 + Data + 0x1 + + + PST_2 + Change of Flow + 0x2 + + + PST_3 + Change of Flow in Loop + 0x3 + + + PST_4 + Debug + 0x4 + + + PST_5 + Functional Unit + 0x5 + + + PST_6 + Sleep + 0x6 + + + PST_7 + Save + 0x7 + + + PST_8 + Program in Sleep + 0x8 + + + PST_9 + Data in Sleep + 0x9 + + + PST_12 + Debug in Sleep + 0xC + + + PST_13 + Functional Unit in Sleep + 0xD + + + PST_14 + Sleep after Reset + 0xE + + + PST_15 + Restore + 0xF + + + + + + + ONCE_CMD + OnCE Command Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD + Writing to this register will cause the OnCE to execute the command that is written + 0 + 4 + read-write + + + CMD_0 + rstatus + 0 + + + CMD_1 + dmov + 0x1 + + + CMD_2 + exec_once + 0x2 + + + CMD_3 + run_core + 0x3 + + + CMD_4 + exec_core + 0x4 + + + CMD_5 + debug_rqst + 0x5 + + + CMD_6 + rbuffer + 0x6 + + + + + + + ILLINSTADDR + Illegal Instruction Trap Address + 0x58 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ILLINSTADDR + The Illegal Instruction Trap Address is the address where the SDMA jumps when an illegal instruction is executed + 0 + 14 + read-write + + + + + CHN0ADDR + Channel 0 Boot Address + 0x5C + 32 + read-write + 0x50 + 0xFFFFFFFF + + + CHN0ADDR + This 14-bit register is used by the boot code of the SDMA + 0 + 14 + read-write + + + SMSZ + The bit 14 (Scratch Memory Size) determines if scratch memory must be available after every channel context + 0xE + 1 + read-write + + + SMSZ_0 + 24 words per context + 0 + + + SMSZ_1 + 32 words per context + 0x1 + + + + + + + EVT_MIRROR + DMA Requests + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + EVENTS + This register reflects the DMA requests received by the SDMA for events 31-0 + 0 + 32 + read-only + + + EVENTS_0 + DMA request event not pending + 0 + + + EVENTS_1 + DMA request event pending + 0x1 + + + + + + + EVT_MIRROR2 + DMA Requests 2 + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + EVENTS + This register reflects the DMA requests received by the SDMA for events 47-32 + 0 + 16 + read-only + + + EVENTS_0 + - DMA request event not pending + 0 + + + + + + + XTRIG_CONF1 + Cross-Trigger Events Configuration Register 1 + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM0 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0 + 6 + read-write + + + CNF0 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0x6 + 1 + read-write + + + CNF0_0 + channel + 0 + + + CNF0_1 + DMA request + 0x1 + + + + + NUM1 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0x8 + 6 + read-write + + + CNF1 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0xE + 1 + read-write + + + CNF1_0 + channel + 0 + + + CNF1_1 + DMA request + 0x1 + + + + + NUM2 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0x10 + 6 + read-write + + + CNF2 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0x16 + 1 + read-write + + + CNF2_0 + channel + 0 + + + CNF2_1 + DMA request + 0x1 + + + + + NUM3 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0x18 + 6 + read-write + + + CNF3 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0x1E + 1 + read-write + + + CNF3_0 + channel + 0 + + + CNF3_1 + DMA request + 0x1 + + + + + + + XTRIG_CONF2 + Cross-Trigger Events Configuration Register 2 + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + NUM4 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0 + 6 + read-write + + + CNF4 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0x6 + 1 + read-write + + + CNF4_0 + channel + 0 + + + CNF4_1 + DMA request + 0x1 + + + + + NUM5 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0x8 + 6 + read-write + + + CNF5 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0xE + 1 + read-write + + + CNF5_0 + channel + 0 + + + CNF5_1 + DMA request + 0x1 + + + + + NUM6 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0x10 + 6 + read-write + + + CNF6 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0x16 + 1 + read-write + + + CNF6_0 + channel + 0 + + + CNF6_1 + DMA request + 0x1 + + + + + NUM7 + Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line number i + 0x18 + 6 + read-write + + + CNF7 + Configuration of the SDMA event line number i that is connected to the cross-trigger + 0x1E + 1 + read-write + + + CNF7_0 + channel + 0 + + + CNF7_1 + DMA request + 0x1 + + + + + + + 32 + 0x4 + SDMA_CHNPRI%s + Channel Priority Registers + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHNPRIn + This contains the priority of channel number n + 0 + 3 + read-write + + + + + 48 + 0x4 + CHNENBL%s + Channel Enable RAM + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENBLn + This 32-bit value selects the channels that are triggered by the DMA request number n + 0 + 32 + read-write + + + + + + + USB1 + USB + USB + USB1_ + 0x2184000 + USB + + 0 + 0x1E0 + registers + + + USB_OTG1 + 75 + + + + ID + Identification register + 0 + 32 + read-only + 0xE4A1FA05 + 0xFFFFFFFF + + + ID + Configuration number + 0 + 6 + read-only + + + NID + Complement version of ID + 0x8 + 6 + read-only + + + REVISION + Revision number of the controller core. + 0x10 + 8 + read-only + + + + + HWGENERAL + Hardware General + 0x4 + 32 + read-only + 0x35 + 0xFFFFFFFF + + + PHYW + Data width of the transciever connected to the controller core. PHYW bit reset value is + 0x4 + 2 + read-only + + + PHYW_0 + 8 bit wide data bus Software non-programmable + 0 + + + PHYW_1 + 16 bit wide data bus Software non-programmable + 0x1 + + + PHYW_2 + Reset to 8 bit wide data bus Software programmable + 0x2 + + + PHYW_3 + Reset to 16 bit wide data bus Software programmable + 0x3 + + + + + PHYM + Transciever type + 0x6 + 3 + read-only + + + PHYM_0 + UTMI/UMTI+ + 0 + + + PHYM_1 + ULPI DDR + 0x1 + + + PHYM_2 + ULPI + 0x2 + + + PHYM_3 + Serial Only + 0x3 + + + PHYM_4 + Software programmable - reset to UTMI/UTMI+ + 0x4 + + + PHYM_5 + Software programmable - reset to ULPI DDR + 0x5 + + + PHYM_6 + Software programmable - reset to ULPI + 0x6 + + + PHYM_7 + Software programmable - reset to Serial + 0x7 + + + + + SM + Serial interface mode capability + 0x9 + 2 + read-only + + + SM_0 + No Serial Engine, always use parallel signalling. + 0 + + + SM_1 + Serial Engine present, always use serial signalling for FS/LS. + 0x1 + + + SM_2 + Software programmable - Reset to use parallel signalling for FS/LS + 0x2 + + + SM_3 + Software programmable - Reset to use serial signalling for FS/LS + 0x3 + + + + + + + HWHOST + Host Hardware Parameters + 0x8 + 32 + read-only + 0x10020001 + 0xFFFFFFFF + + + HC + Host Capable. Indicating whether host operation mode is supported or not. + 0 + 1 + read-only + + + HC_0 + Not supported + 0 + + + HC_1 + Supported + 0x1 + + + + + NPORT + The Nmber of downstream ports supported by the host controller is (NPORT+1) + 0x1 + 3 + read-only + + + + + HWDEVICE + Device Hardware Parameters + 0xC + 32 + read-only + 0x11 + 0xFFFFFFFF + + + DC + Device Capable. Indicating whether device operation mode is supported or not. + 0 + 1 + read-only + + + DC_0 + Not supported + 0 + + + DC_1 + Supported + 0x1 + + + + + DEVEP + Device Endpoint Number + 0x1 + 5 + read-only + + + + + HWTXBUF + TX Buffer Hardware Parameters + 0x10 + 32 + read-only + 0x80080B08 + 0xFFFFFFFF + + + TXBURST + Default burst size for memory to TX buffer transfer + 0 + 8 + read-only + + + TXCHANADD + TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes + 0x10 + 8 + read-only + + + + + HWRXBUF + RX Buffer Hardware Parameters + 0x14 + 32 + read-only + 0x808 + 0xFFFFFFFF + + + RXBURST + Default burst size for memory to RX buffer transfer + 0 + 8 + read-only + + + RXADD + Buffer total size for all receive endpoints is (2^RXADD) + 0x8 + 8 + read-only + + + + + GPTIMER0LD + General Purpose Timer #0 Load + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTLD + General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b' + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTCNT + General Purpose Timer Counter. This field is the count value of the countdown timer. + 0 + 24 + read-write + + + GPTMODE + General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again + 0x18 + 1 + read-write + + + GPTMODE_0 + One Shot Mode + 0 + + + GPTMODE_1 + Repeat Mode + 0x1 + + + + + GPTRST + General Purpose Timer Reset + 0x1E + 1 + read-write + + + GPTRST_0 + No action + 0 + + + GPTRST_1 + Load counter value from GPTLD bits in n_GPTIMER0LD + 0x1 + + + + + GPTRUN + General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. + 0x1F + 1 + read-write + + + GPTRUN_0 + Stop counting + 0 + + + GPTRUN_1 + Run + 0x1 + + + + + + + GPTIMER1LD + General Purpose Timer #1 Load + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTLD + General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b' + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTCNT + General Purpose Timer Counter. This field is the count value of the countdown timer. + 0 + 24 + read-write + + + GPTMODE + General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software + 0x18 + 1 + read-write + + + GPTMODE_0 + One Shot Mode + 0 + + + GPTMODE_1 + Repeat Mode + 0x1 + + + + + GPTRST + General Purpose Timer Reset + 0x1E + 1 + read-write + + + GPTRST_0 + No action + 0 + + + GPTRST_1 + Load counter value from GPTLD bits in USB_n_GPTIMER0LD + 0x1 + + + + + GPTRUN + General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. + 0x1F + 1 + read-write + + + GPTRUN_0 + Stop counting + 0 + + + GPTRUN_1 + Run + 0x1 + + + + + + + SBUSCFG + System Bus Config + 0x90 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + AHBBRST + AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority) + 0 + 3 + read-write + + + AHBBRST_0 + Incremental burst of unspecified length only + 0 + + + AHBBRST_1 + INCR4 burst, then single transfer + 0x1 + + + AHBBRST_2 + INCR8 burst, INCR4 burst, then single transfer + 0x2 + + + AHBBRST_3 + INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + 0x3 + + + AHBBRST_5 + INCR4 burst, then incremental burst of unspecified length + 0x5 + + + AHBBRST_6 + INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0x6 + + + AHBBRST_7 + INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0x7 + + + + + + + CAPLENGTH + Capability Registers Length + 0x100 + 8 + read-only + 0x40 + 0xFF + + + CAPLENGTH + These bits are used as an offset to add to register base to find the beginning of the Operational Register + 0 + 8 + read-only + + + + + HCIVERSION + Host Controller Interface Version + 0x102 + 16 + read-only + 0x100 + 0xFFFF + + + HCIVERSION + Host Controller Interface Version Number Default value is '10h', which means EHCI rev1.0. + 0 + 16 + read-only + + + + + HCSPARAMS + Host Controller Structural Parameters + 0x104 + 32 + read-only + 0x10011 + 0xFFFFFFFF + + + N_PORTS + Number of downstream ports + 0 + 4 + read-only + + + PPC + Port Power Control This field indicates whether the host controller implementation includes port power control + 0x4 + 1 + read-only + + + N_PCC + Number of Ports per Companion Controller This field indicates the number of ports supported per internal Companion Controller + 0x8 + 4 + read-only + + + N_CC + Number of Companion Controller (N_CC) + 0xC + 4 + read-only + + + N_CC_0 + There is no internal Companion Controller and port-ownership hand-off is not supported. + 0 + + + N_CC_1 + There are internal companion controller(s) and port-ownership hand-offs is supported. + 0x1 + + + + + PI + Port Indicators (P INDICATOR) This bit indicates whether the ports support port indicator control + 0x10 + 1 + read-only + + + N_PTT + Number of Ports per Transaction Translator (N_PTT) + 0x14 + 4 + read-only + + + N_TT + Number of Transaction Translators (N_TT) + 0x18 + 4 + read-only + + + + + HCCPARAMS + Host Controller Capability Parameters + 0x108 + 32 + read-only + 0x6 + 0xFFFFFFFF + + + ADC + 64-bit Addressing Capability This bit is set '0b' in all controller core, no 64-bit addressing capability is supported + 0 + 1 + read-only + + + PFL + Programmable Frame List Flag If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller + 0x1 + 1 + read-only + + + ASP + Asynchronous Schedule Park Capability If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule + 0x2 + 1 + read-only + + + IST + Isochronous Scheduling Threshold + 0x4 + 4 + read-only + + + EECP + EHCI Extended Capabilities Pointer + 0x8 + 8 + read-only + + + + + DCIVERSION + Device Controller Interface Version + 0x120 + 16 + read-only + 0x1 + 0xFFFF + + + DCIVERSION + Device Controller Interface Version Number Default value is '01h', which means rev0.1. + 0 + 16 + read-only + + + + + DCCPARAMS + Device Controller Capability Parameters + 0x124 + 32 + read-only + 0x188 + 0xFFFFFFFF + + + DEN + Device Endpoint Number This field indicates the number of endpoints built into the device controller + 0 + 5 + read-only + + + DC + Device Capable When this bit is 1, this controller is capable of operating as a USB 2.0 device. + 0x7 + 1 + read-only + + + HC + Host Capable When this bit is 1, this controller is capable of operating as an EHCI compatible USB 2 + 0x8 + 1 + read-only + + + + + USBCMD + USB Command Register + 0x140 + 32 + read-write + 0x80000 + 0xFFFFFFFF + + + RS + Run/Stop (RS) - Read/Write + 0 + 1 + read-write + + + RST + Controller Reset (RESET) - Read/Write + 0x1 + 1 + read-write + + + FS_1 + See description at bit 15 + 0x2 + 2 + read-write + + + PSE + Periodic Schedule Enable- Read/Write + 0x4 + 1 + read-write + + + PSE_0 + Do not process the Periodic Schedule + 0 + + + PSE_1 + Use the PERIODICLISTBASE register to access the Periodic Schedule. + 0x1 + + + + + ASE + Asynchronous Schedule Enable - Read/Write + 0x5 + 1 + read-write + + + ASE_0 + Do not process the Asynchronous Schedule. + 0 + + + ASE_1 + Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 0x1 + + + + + IAA + Interrupt on Async Advance Doorbell - Read/Write + 0x6 + 1 + read-write + + + ASP + Asynchronous Schedule Park Mode Count - Read/Write + 0x8 + 2 + read-write + + + ASPE + Asynchronous Schedule Park Mode Enable - Read/Write + 0xB + 1 + read-write + + + ATDTW + Add dTD TripWire - Read/Write + 0xC + 1 + read-write + + + SUTW + Setup TripWire - Read/Write + 0xD + 1 + read-write + + + FS_2 + See also bits 3-2 Frame List Size - (Read/Write or Read Only) + 0xF + 1 + read-write + + + FS_2_0 + 1024 elements (4096 bytes) Default value + 0 + + + FS_2_1 + 512 elements (2048 bytes) + 0x1 + + + + + ITC + Interrupt Threshold Control -Read/Write + 0x10 + 8 + read-write + + + ITC_0 + Immediate (no threshold) + 0 + + + ITC_1 + 1 micro-frame + 0x1 + + + ITC_2 + 2 micro-frames + 0x2 + + + ITC_4 + 4 micro-frames + 0x4 + + + ITC_8 + 8 micro-frames + 0x8 + + + ITC_16 + 16 micro-frames + 0x10 + + + ITC_32 + 32 micro-frames + 0x20 + + + ITC_64 + 64 micro-frames + 0x40 + + + + + + + USBSTS + USB Status Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + UI + USB Interrupt (USBINT) - R/WC + 0 + 1 + read-write + + + UEI + USB Error Interrupt (USBERRINT) - R/WC + 0x1 + 1 + read-write + + + PCI + Port Change Detect - R/WC + 0x2 + 1 + read-write + + + FRI + Frame List Rollover - R/WC + 0x3 + 1 + read-write + + + SEI + System Error- R/WC + 0x4 + 1 + read-write + + + AAI + Interrupt on Async Advance - R/WC + 0x5 + 1 + read-write + + + URI + USB Reset Received - R/WC + 0x6 + 1 + read-write + + + SRI + SOF Received - R/WC + 0x7 + 1 + read-write + + + SLI + DCSuspend - R/WC + 0x8 + 1 + read-write + + + ULPII + ULPI Interrupt - R/WC + 0xA + 1 + read-write + + + HCH + HCHaIted - Read Only + 0xC + 1 + read-write + + + RCL + Reclamation - Read Only + 0xD + 1 + read-write + + + PS + Periodic Schedule Status - Read Only + 0xE + 1 + read-write + + + AS + Asynchronous Schedule Status - Read Only + 0xF + 1 + read-write + + + NAKI + NAK Interrupt Bit--RO + 0x10 + 1 + read-only + + + TI0 + General Purpose Timer Interrupt 0(GPTINT0)--R/WC + 0x18 + 1 + read-write + + + TI1 + General Purpose Timer Interrupt 1(GPTINT1)--R/WC + 0x19 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + UE + USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt + 0 + 1 + read-write + + + UEE + USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x1 + 1 + read-write + + + PCE + Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x2 + 1 + read-write + + + FRE + Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x3 + 1 + read-write + + + SEE + System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x4 + 1 + read-write + + + AAE + Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x5 + 1 + read-write + + + URE + USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x6 + 1 + read-write + + + SRE + SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x7 + 1 + read-write + + + SLE + Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt + 0x8 + 1 + read-write + + + ULPIE + ULPI Interrupt Enable When this bit is one and the UPLII bit in n_USBSTS register is a one the controller will issue an interrupt + 0xA + 1 + read-write + + + NAKE + NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt + 0x10 + 1 + read-write + + + UAIE + USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold + 0x12 + 1 + read-write + + + UPIE + USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold + 0x13 + 1 + read-write + + + TIE0 + General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt + 0x18 + 1 + read-write + + + TIE1 + General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt + 0x19 + 1 + read-write + + + + + FRINDEX + USB Frame Index + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + FRINDEX + Frame Index + 0 + 14 + read-write + + + FRINDEX_0 + (1024) 12 + 0 + + + FRINDEX_1 + (512) 11 + 0x1 + + + FRINDEX_2 + (256) 10 + 0x2 + + + FRINDEX_3 + (128) 9 + 0x3 + + + FRINDEX_4 + (64) 8 + 0x4 + + + FRINDEX_5 + (32) 7 + 0x5 + + + FRINDEX_6 + (16) 6 + 0x6 + + + FRINDEX_7 + (8) 5 + 0x7 + + + + + + + DEVICEADDR + Device Address + DEVICEADDR_PERIODICLISTBASE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + USBADRA + Device Address Advance + 0x18 + 1 + read-write + + + USBADR + Device Address. These bits correspond to the USB device address + 0x19 + 7 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address + DEVICEADDR_PERIODICLISTBASE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASEADR + Base Address (Low) + 0xC + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address + ASYNCLISTADDR_ENDPTLISTADDR + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + ASYBASE + Link Pointer Low (LPL) + 0x5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address + ASYNCLISTADDR_ENDPTLISTADDR + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPBASE + Endpoint List Pointer(Low) + 0xB + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size + 0x160 + 32 + read-write + 0x808 + 0xFFFFFFFF + + + RXPBURST + Programmable RX Burst Size + 0 + 8 + read-write + + + TXPBURST + Programmable TX Burst Size + 0x8 + 9 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning + 0x164 + 32 + read-write + 0xA0000 + 0xFFFFFFFF + + + TXSCHOH + Scheduler Overhead + 0 + 8 + read-write + + + TXSCHHEALTH + Scheduler Health Counter + 0x8 + 5 + read-write + + + TXFIFOTHRES + FIFO Burst Threshold + 0x10 + 6 + read-write + + + + + ENDPTNAK + Endpoint NAK + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPRN + RX Endpoint NAK - R/WC + 0 + 8 + read-write + + + EPTN + TX Endpoint NAK - R/WC + 0x10 + 8 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + EPRNE + RX Endpoint NAK Enable - R/W + 0 + 8 + read-write + + + EPTNE + TX Endpoint NAK Enable - R/W + 0x10 + 8 + read-write + + + + + CONFIGFLAG + Configure Flag Register + 0x180 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + CF + Configure Flag Host software sets this bit as the last action in its process of configuring the Host Controller + 0 + 1 + read-only + + + CF_0 + Port routing control logic default-routes each port to an implementation dependent classic host controller. + 0 + + + CF_1 + Port routing control logic default-routes all ports to this host controller. + 0x1 + + + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + CCS + Current Connect Status-Read Only + 0 + 1 + read-only + + + CSC + Connect Status Change-R/WC + 0x1 + 1 + read-write + + + PE + Port Enabled/Disabled-Read/Write + 0x2 + 1 + read-write + + + PEC + Port Enable/Disable Change-R/WC + 0x3 + 1 + read-write + + + OCA + Over-current Active-Read Only + 0x4 + 1 + read-only + + + OCA_0 + This port does not have an over-current condition. + 0 + + + OCA_1 + This port currently has an over-current condition + 0x1 + + + + + OCC + Over-current Change-R/WC + 0x5 + 1 + read-write + + + FPR + Force Port Resume -Read/Write + 0x6 + 1 + read-write + + + SUSP + Suspend - Read/Write or Read Only + 0x7 + 1 + read-write + + + PR + Port Reset - Read/Write or Read Only + 0x8 + 1 + read-write + + + HSP + High-Speed Port - Read Only + 0x9 + 1 + read-only + + + LS + Line Status-Read Only + 0xA + 2 + read-write + + + LS_0 + SE0 + 0 + + + LS_1 + K-state + 0x1 + + + LS_2 + J-state + 0x2 + + + LS_3 + Undefined + 0x3 + + + + + PP + Port Power (PP)-Read/Write or Read Only + 0xC + 1 + read-write + + + PO + Port Owner-Read/Write + 0xD + 1 + read-write + + + PIC + Port Indicator Control - Read/Write + 0xE + 2 + read-write + + + PIC_0 + Port indicators are off + 0 + + + PIC_1 + Amber + 0x1 + + + PIC_2 + Green + 0x2 + + + PIC_3 + Undefined + 0x3 + + + + + PTC + Port Test Control - Read/Write + 0x10 + 4 + read-write + + + PTC_0 + TEST_MODE_DISABLE + 0 + + + PTC_1 + J_STATE + 0x1 + + + PTC_2 + K_STATE + 0x2 + + + PTC_3 + SE0 (host) / NAK (device) + 0x3 + + + PTC_4 + Packet + 0x4 + + + PTC_5 + FORCE_ENABLE_HS + 0x5 + + + PTC_6 + FORCE_ENABLE_FS + 0x6 + + + PTC_7 + FORCE_ENABLE_LS + 0x7 + + + + + WKCN + Wake on Connect Enable (WKCNNT_E) - Read/Write + 0x14 + 1 + read-write + + + WKDC + Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write + 0x15 + 1 + read-write + + + WKOC + Wake on Over-current Enable (WKOC_E) - Read/Write + 0x16 + 1 + read-write + + + PHCD + PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write + 0x17 + 1 + read-write + + + PHCD_0 + Enable PHY clock + 0 + + + PHCD_1 + Disable PHY clock + 0x1 + + + + + PFSC + Port Force Full Speed Connect - Read/Write + 0x18 + 1 + read-write + + + PFSC_0 + Normal operation + 0 + + + PFSC_1 + Forced to full speed + 0x1 + + + + + PTS_2 + See description at bits 31-30 + 0x19 + 1 + read-write + + + PSPD + Port Speed - Read Only. This register field indicates the speed at which the port is operating. + 0x1A + 2 + read-write + + + PSPD_0 + Full Speed + 0 + + + PSPD_1 + Low Speed + 0x1 + + + PSPD_2 + High Speed + 0x2 + + + PSPD_3 + Undefined + 0x3 + + + + + PTW + Parallel Transceiver Width This bit has no effect if serial interface engine is used + 0x1C + 1 + read-write + + + PTW_0 + Select the 8-bit UTMI interface [60MHz] + 0 + + + PTW_1 + Select the 16-bit UTMI interface [30MHz] + 0x1 + + + + + STS + Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals + 0x1D + 1 + read-write + + + PTS_1 + All USB port interface modes are listed in this field description, but not all are supported + 0x1E + 2 + read-write + + + + + OTGSC + On-The-Go Status & control + 0x1A4 + 32 + read-write + 0x1120 + 0xFFFFFFFF + + + VD + VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + VC + VBUS Charge - Read/Write + 0x1 + 1 + read-write + + + OT + OTG Termination - Read/Write + 0x3 + 1 + read-write + + + DP + Data Pulsing - Read/Write + 0x4 + 1 + read-write + + + IDPU + ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default] + 0x5 + 1 + read-write + + + ID + USB ID - Read Only. 0 = A device, 1 = B device + 0x8 + 1 + read-only + + + AVV + A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold. + 0x9 + 1 + read-only + + + ASV + A Session Valid - Read Only. Indicates VBus is above the A session valid threshold. + 0xA + 1 + read-only + + + BSV + B Session Valid - Read Only. Indicates VBus is above the B session valid threshold. + 0xB + 1 + read-only + + + BSE + B Session End - Read Only. Indicates VBus is below the B session end threshold. + 0xC + 1 + read-only + + + TOG_1MS + 1 millisecond timer toggle - Read Only. This bit toggles once per millisecond. + 0xD + 1 + read-only + + + DPS + Data Bus Pulsing Status - Read Only + 0xE + 1 + read-only + + + IDIS + USB ID Interrupt Status - Read/Write + 0x10 + 1 + read-write + + + AVVIS + A VBus Valid Interrupt Status - Read/Write to Clear + 0x11 + 1 + read-write + + + ASVIS + A Session Valid Interrupt Status - Read/Write to Clear + 0x12 + 1 + read-write + + + BSVIS + B Session Valid Interrupt Status - Read/Write to Clear + 0x13 + 1 + read-write + + + BSEIS + B Session End Interrupt Status - Read/Write to Clear + 0x14 + 1 + read-write + + + STATUS_1MS + 1 millisecond timer Interrupt Status - Read/Write to Clear + 0x15 + 1 + read-write + + + DPIS + Data Pulse Interrupt Status - Read/Write to Clear + 0x16 + 1 + read-write + + + IDIE + USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt. + 0x18 + 1 + read-write + + + AVVIE + A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt. + 0x19 + 1 + read-write + + + ASVIE + A Session Valid Interrupt Enable - Read/Write + 0x1A + 1 + read-write + + + BSVIE + B Session Valid Interrupt Enable - Read/Write + 0x1B + 1 + read-write + + + BSEIE + B Session End Interrupt Enable - Read/Write. Setting this bit enables the B session end interrupt. + 0x1C + 1 + read-write + + + EN_1MS + 1 millisecond timer Interrupt Enable - Read/Write + 0x1D + 1 + read-write + + + DPIE + Data Pulse Interrupt Enable + 0x1E + 1 + read-write + + + + + USBMODE + USB Device Mode + 0x1A8 + 32 + read-write + 0x5000 + 0xFFFFFFFF + + + CM + Controller Mode - R/WO + 0 + 2 + read-write + + + CM_0 + Idle [Default for combination host/device] + 0 + + + CM_2 + Device Controller [Default for device only controller] + 0x2 + + + CM_3 + Host Controller [Default for host only controller] + 0x3 + + + + + ES + Endian Select - Read/Write + 0x2 + 1 + read-write + + + ES_0 + Little Endian [Default] + 0 + + + ES_1 + Big Endian + 0x1 + + + + + SLOM + Setup Lockout Mode + 0x3 + 1 + read-write + + + SLOM_0 + Setup Lockouts On (default); + 0 + + + SLOM_1 + Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . + 0x1 + + + + + SDIS + Stream Disable Mode + 0x4 + 1 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENDPTSETUPSTAT + Setup Endpoint Status + 0 + 16 + read-write + + + + + ENDPTPRIME + Endpoint Prime + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERB + Prime Endpoint Receive Buffer - R/WS + 0 + 8 + read-write + + + PETB + Prime Endpoint Transmit Buffer - R/WS + 0x10 + 8 + read-write + + + + + ENDPTFLUSH + Endpoint Flush + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FERB + Flush Endpoint Receive Buffer - R/WS + 0 + 8 + read-write + + + FETB + Flush Endpoint Transmit Buffer - R/WS + 0x10 + 8 + read-write + + + + + ENDPTSTAT + Endpoint Status + 0x1B8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ERBR + Endpoint Receive Buffer Ready -- Read Only + 0 + 8 + read-only + + + ETBR + Endpoint Transmit Buffer Ready -- Read Only + 0x10 + 8 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + ERCE + Endpoint Receive Complete Event - RW/C + 0 + 8 + read-write + + + ETCE + Endpoint Transmit Complete Event - R/WC + 0x10 + 8 + read-write + + + + + ENDPTCTRL0 + Endpoint Control0 + 0x1C0 + 32 + read-write + 0x800080 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control Endpoint0 is fixed as a Control End Point. + 0x2 + 2 + read-write + + + RXE + RX Endpoint Enable 1 Enabled Endpoint0 is always enabled. + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK [Default] 1 End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host + 0x10 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 - Control Endpoint0 is fixed as a Control End Point. + 0x12 + 2 + read-write + + + TXE + TX Endpoint Enable 1 Enabled Endpoint0 is always enabled. + 0x17 + 1 + read-write + + + + + ENDPTCTRL1 + Endpoint Control 1 + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 0x1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 0x5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 0x6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 0x10 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 0x11 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x12 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 0x15 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 0x16 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x17 + 1 + read-write + + + + + ENDPTCTRL2 + Endpoint Control 2 + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 0x1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 0x5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 0x6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 0x10 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 0x11 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x12 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 0x15 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 0x16 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x17 + 1 + read-write + + + + + ENDPTCTRL3 + Endpoint Control 3 + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 0x1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 0x5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 0x6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 0x10 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 0x11 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x12 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 0x15 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 0x16 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x17 + 1 + read-write + + + + + ENDPTCTRL4 + Endpoint Control 4 + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 0x1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 0x5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 0x6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 0x10 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 0x11 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x12 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 0x15 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 0x16 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x17 + 1 + read-write + + + + + ENDPTCTRL5 + Endpoint Control 5 + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 0x1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 0x5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 0x6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 0x10 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 0x11 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x12 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 0x15 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 0x16 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x17 + 1 + read-write + + + + + ENDPTCTRL6 + Endpoint Control 6 + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 0x1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 0x5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 0x6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 0x10 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 0x11 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x12 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 0x15 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 0x16 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x17 + 1 + read-write + + + + + ENDPTCTRL7 + Endpoint Control 7 + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 0x1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 0x5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 0x6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 0x10 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 0x11 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 0x12 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 0x15 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 0x16 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 0x17 + 1 + read-write + + + + + + + USB2 + USB + USB + USB2_ + 0x2184200 + + 0 + 0x1E0 + registers + + + USB_OTG2 + 74 + + + + USBNC1 + USB + USBNC + USBNC1_ + 0x2184800 + USBNC + + 0 + 0x1C + registers + + + + USB_OTGn_CTRL + USB OTGn Control Register + 0 + 32 + read-write + 0x30001000 + 0xFFFFFFFF + + + OVER_CUR_DIS + Disable OTGn Overcurrent Detection + 0x7 + 1 + read-write + + + OVER_CUR_DIS_0 + Enables overcurrent detection + 0 + + + OVER_CUR_DIS_1 + Disables overcurrent detection + 0x1 + + + + + OVER_CUR_POL + OTGn Polarity of Overcurrent The polarity of OTGn port overcurrent event + 0x8 + 1 + read-write + + + OVER_CUR_POL_0 + High active (high on this signal represents an overcurrent condition) + 0 + + + OVER_CUR_POL_1 + Low active (low on this signal represents an overcurrent condition) + 0x1 + + + + + PWR_POL + OTGn Power Polarity This bit should be set according to PMIC Power Pin polarity. + 0x9 + 1 + read-write + + + PWR_POL_0 + PMIC Power Pin is Low active. + 0 + + + PWR_POL_1 + PMIC Power Pin is High active. + 0x1 + + + + + WIE + OTGn Wake-up Interrupt Enable This bit enables or disables the OTGn wake-up interrupt + 0xA + 1 + read-write + + + WIE_0 + Interrupt Disabled + 0 + + + WIE_1 + Interrupt Enabled + 0x1 + + + + + WKUP_SW_EN + OTGn Software Wake-up Enable + 0xE + 1 + read-write + + + WKUP_SW_EN_0 + Disable + 0 + + + WKUP_SW_EN_1 + Enable + 0x1 + + + + + WKUP_SW + OTGn Software Wake-up + 0xF + 1 + read-write + + + WKUP_SW_0 + Inactive + 0 + + + WKUP_SW_1 + Force wake-up + 0x1 + + + + + WKUP_ID_EN + OTGn Wake-up on ID change enable + 0x10 + 1 + read-write + + + WKUP_ID_EN_0 + Disable + 0 + + + WKUP_ID_EN_1 + Enable + 0x1 + + + + + WKUP_VBUS_EN + OTGn wake-up on VBUS change enable + 0x11 + 1 + read-write + + + WKUP_VBUS_EN_0 + Disable + 0 + + + WKUP_VBUS_EN_1 + Enable + 0x1 + + + + + WIR + OTGn Wake-up Interrupt Request This bit indicates that a wake-up interrupt request is received on the OTGn port + 0x1F + 1 + read-only + + + WIR_0 + No wake-up interrupt request received + 0 + + + WIR_1 + Wake-up Interrupt Request received + 0x1 + + + + + + + USB_OTGn_PHY_CTRL_0 + OTGn UTMI PHY Control 0 Register + 0x18 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + UTMI_CLK_VLD + Indicating whether OTGn UTMI PHY clock is valid + 0x1F + 1 + read-write + + + UTMI_CLK_VLD_0 + Invalid + 0 + + + UTMI_CLK_VLD_1 + Valid + 0x1 + + + + + + + + + USBNC2 + USB + USBNC + USBNC2_ + 0x2184804 + + 0 + 0x1C + registers + + + + ENET1 + Ethernet MAC-NET Core + ENET + ENET1_ + 0x2188000 + ENET + + 0 + 0x628 + registers + + + ENET1 + 150 + + + + EIR + Interrupt Event Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TS_TIMER + Timestamp Timer + 0xF + 1 + read-write + oneToClear + + + TS_AVAIL + Transmit Timestamp Available + 0x10 + 1 + read-write + oneToClear + + + WAKEUP + Node Wakeup Request Indication + 0x11 + 1 + read-write + oneToClear + + + PLR + Payload Receive Error + 0x12 + 1 + read-write + oneToClear + + + UN + Transmit FIFO Underrun + 0x13 + 1 + read-write + oneToClear + + + RL + Collision Retry Limit + 0x14 + 1 + read-write + oneToClear + + + LC + Late Collision + 0x15 + 1 + read-write + oneToClear + + + EBERR + Ethernet Bus Error + 0x16 + 1 + read-write + oneToClear + + + MII + MII Interrupt. + 0x17 + 1 + read-write + oneToClear + + + RXB + Receive Buffer Interrupt + 0x18 + 1 + read-write + oneToClear + + + RXF + Receive Frame Interrupt + 0x19 + 1 + read-write + oneToClear + + + TXB + Transmit Buffer Interrupt + 0x1A + 1 + read-write + oneToClear + + + TXF + Transmit Frame Interrupt + 0x1B + 1 + read-write + oneToClear + + + GRA + Graceful Stop Complete + 0x1C + 1 + read-write + oneToClear + + + BABT + Babbling Transmit Error + 0x1D + 1 + read-write + oneToClear + + + BABR + Babbling Receive Error + 0x1E + 1 + read-write + oneToClear + + + + + EIMR + Interrupt Mask Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TS_TIMER + TS_TIMER Interrupt Mask + 0xF + 1 + read-write + + + TS_AVAIL + TS_AVAIL Interrupt Mask + 0x10 + 1 + read-write + + + WAKEUP + WAKEUP Interrupt Mask + 0x11 + 1 + read-write + + + PLR + PLR Interrupt Mask + 0x12 + 1 + read-write + + + UN + UN Interrupt Mask + 0x13 + 1 + read-write + + + RL + RL Interrupt Mask + 0x14 + 1 + read-write + + + LC + LC Interrupt Mask + 0x15 + 1 + read-write + + + EBERR + EBERR Interrupt Mask + 0x16 + 1 + read-write + + + MII + MII Interrupt Mask + 0x17 + 1 + read-write + + + RXB + RXB Interrupt Mask + 0x18 + 1 + read-write + + + RXF + RXF Interrupt Mask + 0x19 + 1 + read-write + + + TXB + TXB Interrupt Mask + 0x1A + 1 + read-write + + + TXB_0 + The corresponding interrupt source is masked. + 0 + + + TXB_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + TXF + TXF Interrupt Mask + 0x1B + 1 + read-write + + + TXF_0 + The corresponding interrupt source is masked. + 0 + + + TXF_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + GRA + GRA Interrupt Mask + 0x1C + 1 + read-write + + + GRA_0 + The corresponding interrupt source is masked. + 0 + + + GRA_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + BABT + BABT Interrupt Mask + 0x1D + 1 + read-write + + + BABT_0 + The corresponding interrupt source is masked. + 0 + + + BABT_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + BABR + BABR Interrupt Mask + 0x1E + 1 + read-write + + + BABR_0 + The corresponding interrupt source is masked. + 0 + + + BABR_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + + + RDAR + Receive Descriptor Active Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDAR + Receive Descriptor Active + 0x18 + 1 + read-write + + + + + TDAR + Transmit Descriptor Active Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDAR + Transmit Descriptor Active + 0x18 + 1 + read-write + + + + + ECR + Ethernet Control Register + 0x24 + 32 + read-write + 0x70000000 + 0xFFFFFFFF + + + RESET + Ethernet MAC Reset + 0 + 1 + read-write + + + ETHEREN + Ethernet Enable + 0x1 + 1 + read-write + + + ETHEREN_0 + Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + 0 + + + ETHEREN_1 + MAC is enabled, and reception and transmission are possible. + 0x1 + + + + + MAGICEN + Magic Packet Detection Enable + 0x2 + 1 + read-write + + + MAGICEN_0 + Magic detection logic disabled. + 0 + + + MAGICEN_1 + The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + 0x1 + + + + + SLEEP + Sleep Mode Enable + 0x3 + 1 + read-write + + + SLEEP_0 + Normal operating mode. + 0 + + + SLEEP_1 + Sleep mode. + 0x1 + + + + + EN1588 + EN1588 Enable + 0x4 + 1 + read-write + + + EN1588_0 + Legacy FEC buffer descriptors and functions enabled. + 0 + + + EN1588_1 + Enhanced frame time-stamping functions enabled. + 0x1 + + + + + DBGEN + Debug Enable + 0x6 + 1 + read-write + + + DBGEN_0 + MAC continues operation in debug mode. + 0 + + + DBGEN_1 + MAC enters hardware freeze mode when the processor is in debug mode. + 0x1 + + + + + DBSWP + Descriptor Byte Swapping Enable + 0x8 + 1 + read-write + + + DBSWP_0 + The buffer descriptor bytes are not swapped to support big-endian devices. + 0 + + + DBSWP_1 + The buffer descriptor bytes are swapped to support little-endian devices. + 0x1 + + + + + + + MMFR + MII Management Frame Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Management Frame Data + 0 + 16 + read-write + + + TA + Turn Around + 0x10 + 2 + read-write + + + RA + Register Address + 0x12 + 5 + read-write + + + PA + PHY Address + 0x17 + 5 + read-write + + + OP + Operation Code + 0x1C + 2 + read-write + + + ST + Start Of Frame Delimiter + 0x1E + 2 + read-write + + + + + MSCR + MII Speed Control Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + MII_SPEED + MII Speed + 0x1 + 6 + read-write + + + DIS_PRE + Disable Preamble + 0x7 + 1 + read-write + + + DIS_PRE_0 + Preamble enabled. + 0 + + + DIS_PRE_1 + Preamble (32 ones) is not prepended to the MII management frame. + 0x1 + + + + + HOLDTIME + Hold time On MDIO Output + 0x8 + 3 + read-write + + + HOLDTIME_0 + 1 internal module clock cycle + 0 + + + HOLDTIME_1 + 2 internal module clock cycles + 0x1 + + + HOLDTIME_2 + 3 internal module clock cycles + 0x2 + + + HOLDTIME_7 + 8 internal module clock cycles + 0x7 + + + + + + + MIBC + MIB Control Register + 0x64 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + MIB_CLEAR + MIB Clear + 0x1D + 1 + read-write + + + MIB_CLEAR_0 + See note above. + 0 + + + MIB_CLEAR_1 + All statistics counters are reset to 0. + 0x1 + + + + + MIB_IDLE + MIB Idle + 0x1E + 1 + read-only + + + MIB_IDLE_0 + The MIB block is updating MIB counters. + 0 + + + MIB_IDLE_1 + The MIB block is not currently updating any MIB counters. + 0x1 + + + + + MIB_DIS + Disable MIB Logic + 0x1F + 1 + read-write + + + MIB_DIS_0 + MIB logic is enabled. + 0 + + + MIB_DIS_1 + MIB logic is disabled. The MIB logic halts and does not update any MIB counters. + 0x1 + + + + + + + RCR + Receive Control Register + 0x84 + 32 + read-write + 0x5EE0001 + 0xFFFFFFFF + + + LOOP + Internal Loopback + 0 + 1 + read-write + + + LOOP_0 + Loopback disabled. + 0 + + + LOOP_1 + Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + 0x1 + + + + + DRT + Disable Receive On Transmit + 0x1 + 1 + read-write + + + DRT_0 + Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. + 0 + + + DRT_1 + Disable reception of frames while transmitting. (Normally used for half-duplex mode.) + 0x1 + + + + + MII_MODE + Media Independent Interface Mode + 0x2 + 1 + read-write + + + MII_MODE_1 + MII or RMII mode, as indicated by the RMII_MODE field. + 0x1 + + + + + PROM + Promiscuous Mode + 0x3 + 1 + read-write + + + PROM_0 + Disabled. + 0 + + + PROM_1 + Enabled. + 0x1 + + + + + BC_REJ + Broadcast Frame Reject + 0x4 + 1 + read-write + + + FCE + Flow Control Enable + 0x5 + 1 + read-write + + + RMII_MODE + RMII Mode Enable + 0x8 + 1 + read-write + + + RMII_MODE_0 + MAC configured for MII mode. + 0 + + + RMII_MODE_1 + MAC configured for RMII operation. + 0x1 + + + + + RMII_10T + Enables 10-Mbit/s mode of the RMII . + 0x9 + 1 + read-write + + + RMII_10T_0 + 100-Mbit/s operation. + 0 + + + RMII_10T_1 + 10-Mbit/s operation. + 0x1 + + + + + PADEN + Enable Frame Padding Remove On Receive + 0xC + 1 + read-write + + + PADEN_0 + No padding is removed on receive by the MAC. + 0 + + + PADEN_1 + Padding is removed from received frames. + 0x1 + + + + + PAUFWD + Terminate/Forward Pause Frames + 0xD + 1 + read-write + + + PAUFWD_0 + Pause frames are terminated and discarded in the MAC. + 0 + + + PAUFWD_1 + Pause frames are forwarded to the user application. + 0x1 + + + + + CRCFWD + Terminate/Forward Received CRC + 0xE + 1 + read-write + + + CRCFWD_0 + The CRC field of received frames is transmitted to the user application. + 0 + + + CRCFWD_1 + The CRC field is stripped from the frame. + 0x1 + + + + + CFEN + MAC Control Frame Enable + 0xF + 1 + read-write + + + CFEN_0 + MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + 0 + + + CFEN_1 + MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + 0x1 + + + + + MAX_FL + Maximum Frame Length + 0x10 + 14 + read-write + + + NLC + Payload Length Check Disable + 0x1E + 1 + read-write + + + NLC_0 + The payload length check is disabled. + 0 + + + NLC_1 + The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field. + 0x1 + + + + + GRS + Graceful Receive Stopped + 0x1F + 1 + read-only + + + + + TCR + Transmit Control Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GTS + Graceful Transmit Stop + 0 + 1 + read-write + + + FDEN + Full-Duplex Enable + 0x2 + 1 + read-write + + + TFC_PAUSE + Transmit Frame Control Pause + 0x3 + 1 + read-write + + + TFC_PAUSE_0 + No PAUSE frame transmitted. + 0 + + + TFC_PAUSE_1 + The MAC stops transmission of data frames after the current transmission is complete. + 0x1 + + + + + RFC_PAUSE + Receive Frame Control Pause + 0x4 + 1 + read-only + + + ADDSEL + Source MAC Address Select On Transmit + 0x5 + 3 + read-write + + + ADDSEL_0 + Node MAC address programmed on PADDR1/2 registers. + 0 + + + + + ADDINS + Set MAC Address On Transmit + 0x8 + 1 + read-write + + + ADDINS_0 + The source MAC address is not modified by the MAC. + 0 + + + ADDINS_1 + The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + 0x1 + + + + + CRCFWD + Forward Frame From Application With CRC + 0x9 + 1 + read-write + + + CRCFWD_0 + TxBD[TC] controls whether the frame has a CRC from the application. + 0 + + + CRCFWD_1 + The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + 0x1 + + + + + + + PALR + Physical Address Lower Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PADDR1 + Pause Address + 0 + 32 + read-write + + + + + PAUR + Physical Address Upper Register + 0xE8 + 32 + read-write + 0x8808 + 0xFFFFFFFF + + + TYPE + Type Field In PAUSE Frames + 0 + 16 + read-only + + + PADDR2 + Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames + 0x10 + 16 + read-write + + + + + OPD + Opcode/Pause Duration Register + 0xEC + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + PAUSE_DUR + Pause Duration + 0 + 16 + read-write + + + OPCODE + Opcode Field In PAUSE Frames + 0x10 + 16 + read-only + + + + + TXIC + Transmit Interrupt Coalescing Register + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICTT + Interrupt coalescing timer threshold + 0 + 16 + read-write + + + ICFT + Interrupt coalescing frame count threshold + 0x14 + 8 + read-write + + + ICCS + Interrupt Coalescing Timer Clock Source Select + 0x1E + 1 + read-write + + + ICCS_0 + Use MII/GMII TX clocks. + 0 + + + ICCS_1 + Use ENET system clock. + 0x1 + + + + + ICEN + Interrupt Coalescing Enable + 0x1F + 1 + read-write + + + ICEN_0 + Disable Interrupt coalescing. + 0 + + + ICEN_1 + Enable Interrupt coalescing. + 0x1 + + + + + + + RXIC + Receive Interrupt Coalescing Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICTT + Interrupt coalescing timer threshold + 0 + 16 + read-write + + + ICFT + Interrupt coalescing frame count threshold + 0x14 + 8 + read-write + + + ICCS + Interrupt Coalescing Timer Clock Source Select + 0x1E + 1 + read-write + + + ICCS_0 + Use MII/GMII TX clocks. + 0 + + + ICCS_1 + Use ENET system clock. + 0x1 + + + + + ICEN + Interrupt Coalescing Enable + 0x1F + 1 + read-write + + + ICEN_0 + Disable Interrupt coalescing. + 0 + + + ICEN_1 + Enable Interrupt coalescing. + 0x1 + + + + + + + IAUR + Descriptor Individual Upper Address Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + IADDR1 + Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address + 0 + 32 + read-write + + + + + IALR + Descriptor Individual Lower Address Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + IADDR2 + Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address + 0 + 32 + read-write + + + + + GAUR + Descriptor Group Upper Address Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + GADDR1 + Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address + 0 + 32 + read-write + + + + + GALR + Descriptor Group Lower Address Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + GADDR2 + Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address + 0 + 32 + read-write + + + + + TFWR + Transmit FIFO Watermark Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFWR + Transmit FIFO Write + 0 + 6 + read-write + + + TFWR_0 + 64 bytes written. + 0 + + + TFWR_1 + 64 bytes written. + 0x1 + + + TFWR_2 + 128 bytes written. + 0x2 + + + TFWR_3 + 192 bytes written. + 0x3 + + + TFWR_31 + 1984 bytes written. + 0x1F + + + + + STRFWD + Store And Forward Enable + 0x8 + 1 + read-write + + + STRFWD_0 + Reset. The transmission start threshold is programmed in TFWR[TFWR]. + 0 + + + STRFWD_1 + Enabled. + 0x1 + + + + + + + RDSR + Receive Descriptor Ring Start Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_DES_START + Pointer to the beginning of the receive buffer descriptor queue. + 0x3 + 29 + read-write + + + + + TDSR + Transmit Buffer Descriptor Ring Start Register + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + X_DES_START + Pointer to the beginning of the transmit buffer descriptor queue. + 0x3 + 29 + read-write + + + + + MRBR + Maximum Receive Buffer Size Register + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_BUF_SIZE + Receive buffer size in bytes + 0x4 + 10 + read-write + + + + + RSFL + Receive FIFO Section Full Threshold + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SECTION_FULL + Value Of Receive FIFO Section Full Threshold + 0 + 8 + read-write + + + + + RSEM + Receive FIFO Section Empty Threshold + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SECTION_EMPTY + Value Of The Receive FIFO Section Empty Threshold + 0 + 8 + read-write + + + STAT_SECTION_EMPTY + RX Status FIFO Section Empty Threshold + 0x10 + 5 + read-write + + + + + RAEM + Receive FIFO Almost Empty Threshold + 0x198 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + RX_ALMOST_EMPTY + Value Of The Receive FIFO Almost Empty Threshold + 0 + 8 + read-write + + + + + RAFL + Receive FIFO Almost Full Threshold + 0x19C + 32 + read-write + 0x4 + 0xFFFFFFFF + + + RX_ALMOST_FULL + Value Of The Receive FIFO Almost Full Threshold + 0 + 8 + read-write + + + + + TSEM + Transmit FIFO Section Empty Threshold + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_SECTION_EMPTY + Value Of The Transmit FIFO Section Empty Threshold + 0 + 8 + read-write + + + + + TAEM + Transmit FIFO Almost Empty Threshold + 0x1A4 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + TX_ALMOST_EMPTY + Value of Transmit FIFO Almost Empty Threshold + 0 + 8 + read-write + + + + + TAFL + Transmit FIFO Almost Full Threshold + 0x1A8 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + TX_ALMOST_FULL + Value Of The Transmit FIFO Almost Full Threshold + 0 + 8 + read-write + + + + + TIPG + Transmit Inter-Packet Gap + 0x1AC + 32 + read-write + 0xC + 0xFFFFFFFF + + + IPG + Transmit Inter-Packet Gap + 0 + 5 + read-write + + + + + FTRL + Frame Truncation Length + 0x1B0 + 32 + read-write + 0x7FF + 0xFFFFFFFF + + + TRUNC_FL + Frame Truncation Length + 0 + 14 + read-write + + + + + TACC + Transmit Accelerator Function Configuration + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFT16 + TX FIFO Shift-16 + 0 + 1 + read-write + + + SHIFT16_0 + Disabled. + 0 + + + SHIFT16_1 + Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. + 0x1 + + + + + IPCHK + Enables insertion of IP header checksum. + 0x3 + 1 + read-write + + + IPCHK_0 + Checksum is not inserted. + 0 + + + IPCHK_1 + If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. + 0x1 + + + + + PROCHK + Enables insertion of protocol checksum. + 0x4 + 1 + read-write + + + PROCHK_0 + Checksum not inserted. + 0 + + + PROCHK_1 + If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. + 0x1 + + + + + + + RACC + Receive Accelerator Function Configuration + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PADREM + Enable Padding Removal For Short IP Frames + 0 + 1 + read-write + + + PADREM_0 + Padding not removed. + 0 + + + PADREM_1 + Any bytes following the IP payload section of the frame are removed from the frame. + 0x1 + + + + + IPDIS + Enable Discard Of Frames With Wrong IPv4 Header Checksum + 0x1 + 1 + read-write + + + IPDIS_0 + Frames with wrong IPv4 header checksum are not discarded. + 0 + + + IPDIS_1 + If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + 0x1 + + + + + PRODIS + Enable Discard Of Frames With Wrong Protocol Checksum + 0x2 + 1 + read-write + + + PRODIS_0 + Frames with wrong checksum are not discarded. + 0 + + + PRODIS_1 + If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + 0x1 + + + + + LINEDIS + Enable Discard Of Frames With MAC Layer Errors + 0x6 + 1 + read-write + + + LINEDIS_0 + Frames with errors are not discarded. + 0 + + + LINEDIS_1 + Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + 0x1 + + + + + SHIFT16 + RX FIFO Shift-16 + 0x7 + 1 + read-write + + + SHIFT16_0 + Disabled. + 0 + + + SHIFT16_1 + Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + 0x1 + + + + + + + RMON_T_DROP + Reserved Statistic Register + 0x200 + 32 + read-only + 0 + 0xFFFFFFFF + + + RMON_T_PACKETS + Tx Packet Count Statistic Register + 0x204 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Packet count + 0 + 16 + read-only + + + + + RMON_T_BC_PKT + Tx Broadcast Packets Statistic Register + 0x208 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Broadcast packets + 0 + 16 + read-only + + + + + RMON_T_MC_PKT + Tx Multicast Packets Statistic Register + 0x20C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Multicast packets + 0 + 16 + read-only + + + + + RMON_T_CRC_ALIGN + Tx Packets with CRC/Align Error Statistic Register + 0x210 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Packets with CRC/align error + 0 + 16 + read-only + + + + + RMON_T_UNDERSIZE + Tx Packets Less Than Bytes and Good CRC Statistic Register + 0x214 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets less than 64 bytes with good CRC + 0 + 16 + read-only + + + + + RMON_T_OVERSIZE + Tx Packets GT MAX_FL bytes and Good CRC Statistic Register + 0x218 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than MAX_FL bytes with good CRC + 0 + 16 + read-only + + + + + RMON_T_FRAG + Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register + 0x21C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of packets less than 64 bytes with bad CRC + 0 + 16 + read-only + + + + + RMON_T_JAB + Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register + 0x220 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than MAX_FL bytes and bad CRC + 0 + 16 + read-only + + + + + RMON_T_COL + Tx Collision Count Statistic Register + 0x224 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit collisions + 0 + 16 + read-only + + + + + RMON_T_P64 + Tx 64-Byte Packets Statistic Register + 0x228 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 64-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P65TO127 + Tx 65- to 127-byte Packets Statistic Register + 0x22C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 65- to 127-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P128TO255 + Tx 128- to 255-byte Packets Statistic Register + 0x230 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 128- to 255-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P256TO511 + Tx 256- to 511-byte Packets Statistic Register + 0x234 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 256- to 511-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P512TO1023 + Tx 512- to 1023-byte Packets Statistic Register + 0x238 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 512- to 1023-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P1024TO2047 + Tx 1024- to 2047-byte Packets Statistic Register + 0x23C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 1024- to 2047-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P_GTE2048 + Tx Packets Greater Than 2048 Bytes Statistic Register + 0x240 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than 2048 bytes + 0 + 16 + read-only + + + + + RMON_T_OCTETS + Tx Octets Statistic Register + 0x244 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXOCTS + Number of transmit octets + 0 + 32 + read-only + + + + + IEEE_T_DROP + Reserved Statistic Register + 0x248 + 32 + read-only + 0 + 0xFFFFFFFF + + + IEEE_T_FRAME_OK + Frames Transmitted OK Statistic Register + 0x24C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted OK + 0 + 16 + read-only + + + + + IEEE_T_1COL + Frames Transmitted with Single Collision Statistic Register + 0x250 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with one collision + 0 + 16 + read-only + + + + + IEEE_T_MCOL + Frames Transmitted with Multiple Collisions Statistic Register + 0x254 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with multiple collisions + 0 + 16 + read-only + + + + + IEEE_T_DEF + Frames Transmitted after Deferral Delay Statistic Register + 0x258 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with deferral delay + 0 + 16 + read-only + + + + + IEEE_T_LCOL + Frames Transmitted with Late Collision Statistic Register + 0x25C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with late collision + 0 + 16 + read-only + + + + + IEEE_T_EXCOL + Frames Transmitted with Excessive Collisions Statistic Register + 0x260 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with excessive collisions + 0 + 16 + read-only + + + + + IEEE_T_MACERR + Frames Transmitted with Tx FIFO Underrun Statistic Register + 0x264 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with transmit FIFO underrun + 0 + 16 + read-only + + + + + IEEE_T_CSERR + Frames Transmitted with Carrier Sense Error Statistic Register + 0x268 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with carrier sense error + 0 + 16 + read-only + + + + + IEEE_T_SQE + Reserved Statistic Register + 0x26C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + This read-only field is reserved and always has the value 0 + 0 + 16 + read-only + + + + + IEEE_T_FDXFC + Flow Control Pause Frames Transmitted Statistic Register + 0x270 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of flow-control pause frames transmitted + 0 + 16 + read-only + + + + + IEEE_T_OCTETS_OK + Octet Count for Frames Transmitted w/o Error Statistic Register + 0x274 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). + 0 + 32 + read-only + + + + + RMON_R_PACKETS + Rx Packet Count Statistic Register + 0x284 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of packets received + 0 + 16 + read-only + + + + + RMON_R_BC_PKT + Rx Broadcast Packets Statistic Register + 0x288 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive broadcast packets + 0 + 16 + read-only + + + + + RMON_R_MC_PKT + Rx Multicast Packets Statistic Register + 0x28C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive multicast packets + 0 + 16 + read-only + + + + + RMON_R_CRC_ALIGN + Rx Packets with CRC/Align Error Statistic Register + 0x290 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with CRC or align error + 0 + 16 + read-only + + + + + RMON_R_UNDERSIZE + Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register + 0x294 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with less than 64 bytes and good CRC + 0 + 16 + read-only + + + + + RMON_R_OVERSIZE + Rx Packets Greater Than MAX_FL and Good CRC Statistic Register + 0x298 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets greater than MAX_FL and good CRC + 0 + 16 + read-only + + + + + RMON_R_FRAG + Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register + 0x29C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with less than 64 bytes and bad CRC + 0 + 16 + read-only + + + + + RMON_R_JAB + Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register + 0x2A0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets greater than MAX_FL and bad CRC + 0 + 16 + read-only + + + + + RMON_R_RESVD_0 + Reserved Statistic Register + 0x2A4 + 32 + read-only + 0 + 0xFFFFFFFF + + + RMON_R_P64 + Rx 64-Byte Packets Statistic Register + 0x2A8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 64-byte receive packets + 0 + 16 + read-only + + + + + RMON_R_P65TO127 + Rx 65- to 127-Byte Packets Statistic Register + 0x2AC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 65- to 127-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P128TO255 + Rx 128- to 255-Byte Packets Statistic Register + 0x2B0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 128- to 255-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P256TO511 + Rx 256- to 511-Byte Packets Statistic Register + 0x2B4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 256- to 511-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P512TO1023 + Rx 512- to 1023-Byte Packets Statistic Register + 0x2B8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 512- to 1023-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P1024TO2047 + Rx 1024- to 2047-Byte Packets Statistic Register + 0x2BC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 1024- to 2047-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P_GTE2048 + Rx Packets Greater than 2048 Bytes Statistic Register + 0x2C0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of greater-than-2048-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_OCTETS + Rx Octets Statistic Register + 0x2C4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive octets + 0 + 32 + read-only + + + + + IEEE_R_DROP + Frames not Counted Correctly Statistic Register + 0x2C8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Frame count + 0 + 16 + read-only + + + + + IEEE_R_FRAME_OK + Frames Received OK Statistic Register + 0x2CC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received OK + 0 + 16 + read-only + + + + + IEEE_R_CRC + Frames Received with CRC Error Statistic Register + 0x2D0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received with CRC error + 0 + 16 + read-only + + + + + IEEE_R_ALIGN + Frames Received with Alignment Error Statistic Register + 0x2D4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received with alignment error + 0 + 16 + read-only + + + + + IEEE_R_MACERR + Receive FIFO Overflow Count Statistic Register + 0x2D8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Receive FIFO overflow count + 0 + 16 + read-only + + + + + IEEE_R_FDXFC + Flow Control Pause Frames Received Statistic Register + 0x2DC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of flow-control pause frames received + 0 + 16 + read-only + + + + + IEEE_R_OCTETS_OK + Octet Count for Frames Received without Error Statistic Register + 0x2E0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of octets for frames received without error + 0 + 32 + read-only + + + + + ATCR + Adjustable Timer Control Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable Timer + 0 + 1 + read-write + + + EN_0 + The timer stops at the current value. + 0 + + + EN_1 + The timer starts incrementing. + 0x1 + + + + + OFFEN + Enable One-Shot Offset Event + 0x2 + 1 + read-write + + + OFFEN_0 + Disable. + 0 + + + OFFEN_1 + The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field. + 0x1 + + + + + OFFRST + Reset Timer On Offset Event + 0x3 + 1 + read-write + + + OFFRST_0 + The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + 0 + + + OFFRST_1 + If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + 0x1 + + + + + PEREN + Enable Periodical Event + 0x4 + 1 + read-write + + + PEREN_0 + Disable. + 0 + + + PEREN_1 + A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details. + 0x1 + + + + + PINPER + Enables event signal output assertion on period event + 0x7 + 1 + read-write + + + PINPER_0 + Disable. + 0 + + + PINPER_1 + Enable. + 0x1 + + + + + RESTART + Reset Timer + 0x9 + 1 + read-write + + + CAPTURE + Capture Timer Value + 0xB + 1 + read-write + + + CAPTURE_0 + No effect. + 0 + + + CAPTURE_1 + The current time is captured and can be read from the ATVR register. + 0x1 + + + + + SLAVE + Enable Timer Slave Mode + 0xD + 1 + read-write + + + SLAVE_0 + The timer is active and all configuration fields in this register are relevant. + 0 + + + SLAVE_1 + The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + 0x1 + + + + + + + ATVR + Timer Value Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATIME + A write sets the timer + 0 + 32 + read-write + + + + + ATOFF + Timer Offset Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET + Offset value for one-shot event generation + 0 + 32 + read-write + + + + + ATPER + Timer Period Register + 0x40C + 32 + read-write + 0x3B9ACA00 + 0xFFFFFFFF + + + PERIOD + Value for generating periodic events + 0 + 32 + read-write + + + + + ATCOR + Timer Correction Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + COR + Correction Counter Wrap-Around Value + 0 + 31 + read-write + + + + + ATINC + Time-Stamping Clock Period Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds + 0 + 7 + read-write + + + INC_CORR + Correction Increment Value + 0x8 + 7 + read-write + + + + + ATSTMP + Timestamp of Last Transmitted Frame + 0x418 + 32 + read-only + 0 + 0xFFFFFFFF + + + TIMESTAMP + Timestamp of the last frame transmitted by the core that had TxBD[TS] set + 0 + 32 + read-only + + + + + TGSR + Timer Global Status Register + 0x604 + 32 + read-write + 0 + 0xFFFFFFFF + + + TF0 + Copy Of Timer Flag For Channel 0 + 0 + 1 + read-write + oneToClear + + + TF0_0 + Timer Flag for Channel 0 is clear + 0 + + + TF0_1 + Timer Flag for Channel 0 is set + 0x1 + + + + + TF1 + Copy Of Timer Flag For Channel 1 + 0x1 + 1 + read-write + oneToClear + + + TF1_0 + Timer Flag for Channel 1 is clear + 0 + + + TF1_1 + Timer Flag for Channel 1 is set + 0x1 + + + + + TF2 + Copy Of Timer Flag For Channel 2 + 0x2 + 1 + read-write + oneToClear + + + TF2_0 + Timer Flag for Channel 2 is clear + 0 + + + TF2_1 + Timer Flag for Channel 2 is set + 0x1 + + + + + TF3 + Copy Of Timer Flag For Channel 3 + 0x3 + 1 + read-write + oneToClear + + + TF3_0 + Timer Flag for Channel 3 is clear + 0 + + + TF3_1 + Timer Flag for Channel 3 is set + 0x1 + + + + + + + 4 + 0x8 + TCSR%s + Timer Control Status Register + 0x608 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDRE + Timer DMA Request Enable + 0 + 1 + read-write + + + TDRE_0 + DMA request is disabled + 0 + + + TDRE_1 + DMA request is enabled + 0x1 + + + + + TMODE + Timer Mode + 0x2 + 4 + read-write + + + TMODE_0 + Timer Channel is disabled. + 0 + + + TMODE_1 + Timer Channel is configured for Input Capture on rising edge. + 0x1 + + + TMODE_2 + Timer Channel is configured for Input Capture on falling edge. + 0x2 + + + TMODE_3 + Timer Channel is configured for Input Capture on both edges. + 0x3 + + + TMODE_4 + Timer Channel is configured for Output Compare - software only. + 0x4 + + + TMODE_5 + Timer Channel is configured for Output Compare - toggle output on compare. + 0x5 + + + TMODE_6 + Timer Channel is configured for Output Compare - clear output on compare. + 0x6 + + + TMODE_7 + Timer Channel is configured for Output Compare - set output on compare. + 0x7 + + + TMODE_10 + Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + 0xA + + + TMODE_14 + Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xE + + + TMODE_15 + Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xF + + + + + TIE + Timer Interrupt Enable + 0x6 + 1 + read-write + + + TIE_0 + Interrupt is disabled + 0 + + + TIE_1 + Interrupt is enabled + 0x1 + + + + + TF + Timer Flag + 0x7 + 1 + read-write + oneToClear + + + TF_0 + Input Capture or Output Compare has not occurred. + 0 + + + TF_1 + Input Capture or Output Compare has occurred. + 0x1 + + + + + TPWC + Timer PulseWidth Control + 0xB + 5 + read-write + + + TPWC_0 + Pulse width is one 1588-clock cycle. + 0 + + + TPWC_1 + Pulse width is two 1588-clock cycles. + 0x1 + + + TPWC_2 + Pulse width is three 1588-clock cycles. + 0x2 + + + TPWC_3 + Pulse width is four 1588-clock cycles. + 0x3 + + + TPWC_31 + Pulse width is 32 1588-clock cycles. + 0x1F + + + + + + + 4 + 0x8 + TCCR%s + Timer Compare Capture Register + 0x60C + 32 + read-write + 0 + 0xFFFFFFFF + + + TCC + Timer Capture Compare + 0 + 32 + read-write + + + + + + + ENET2 + Ethernet MAC-NET Core + ENET + ENET2_ + 0x20B4000 + + 0 + 0x628 + registers + + + ENET2 + 152 + + + + USDHC1 + USDHC + USDHC + USDHC1_ + 0x2190000 + USDHC + + 0 + 0xD0 + registers + + + USDHC1 + 54 + + + + DS_ADDR + DMA System Address + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DS_ADDR + DMA System Address / Argument 2 When ACMD23_ARGU2_EN is set to 0, SDMA uses this register as system address and supports only 32-bit addressing mode + 0 + 32 + read-write + + + + + BLK_ATT + Block Attributes + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLKSIZE + Transfer Block Size: This register specifies the block size for block data transfers + 0 + 13 + read-write + + + BLKSIZE_0 + No data transfer + 0 + + + BLKSIZE_1 + 1 Byte + 0x1 + + + BLKSIZE_2 + 2 Bytes + 0x2 + + + BLKSIZE_3 + 3 Bytes + 0x3 + + + BLKSIZE_4 + 4 Bytes + 0x4 + + + BLKSIZE_8 + 4096 Bytes + 0x8 + + + BLKSIZE_200 + 512 Bytes + 0xC8 + + + BLKSIZE_800 + 2048 Bytes + 0x320 + + + + + BLKCNT + Blocks Count For Current Transfer: This register is enabled when the Block Count Enable bit in the Transfer Mode register is set to 1 and is valid only for multiple block transfers + 0x10 + 16 + read-write + + + BLKCNT_0 + Stop Count + 0 + + + BLKCNT_1 + 1 block + 0x1 + + + BLKCNT_2 + 2 blocks + 0x2 + + + + + + + CMD_ARG + Command Argument + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMDARG + Command Argument + 0 + 32 + read-write + + + + + CMD_XFR_TYP + Command Transfer Type + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RSPTYP + Response Type Select + 0x10 + 2 + read-write + + + RSPTYP_0 + No Response + 0 + + + RSPTYP_1 + Response Length 136 + 0x1 + + + RSPTYP_2 + Response Length 48 + 0x2 + + + RSPTYP_3 + Response Length 48, check Busy after response + 0x3 + + + + + CCCEN + Command CRC Check Enable + 0x13 + 1 + read-write + + + CCCEN_0 + Disable + 0 + + + CCCEN_1 + Enable + 0x1 + + + + + CICEN + Command Index Check Enable + 0x14 + 1 + read-write + + + CICEN_0 + Disable + 0 + + + CICEN_1 + Enable + 0x1 + + + + + DPSEL + Data Present Select + 0x15 + 1 + read-write + + + DPSEL_0 + No Data Present + 0 + + + DPSEL_1 + Data Present + 0x1 + + + + + CMDTYP + Command Type + 0x16 + 2 + read-write + + + CMDTYP_0 + Normal Other commands + 0 + + + CMDTYP_1 + Suspend CMD52 for writing Bus Suspend in CCCR + 0x1 + + + CMDTYP_2 + Resume CMD52 for writing Function Select in CCCR + 0x2 + + + CMDTYP_3 + Abort CMD12, CMD52 for writing I/O Abort in CCCR + 0x3 + + + + + CMDINX + Command Index + 0x18 + 6 + read-write + + + + + CMD_RSP0 + Command Response0 + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP0 + Command Response 0 + 0 + 32 + read-only + + + + + CMD_RSP1 + Command Response1 + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP1 + Command Response 1 + 0 + 32 + read-only + + + + + CMD_RSP2 + Command Response2 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP2 + Command Response 2 + 0 + 32 + read-only + + + + + CMD_RSP3 + Command Response3 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP3 + Command Response 3 + 0 + 32 + read-only + + + + + DATA_BUFF_ACC_PORT + Data Buffer Access Port + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATCONT + Data Content + 0 + 32 + read-write + + + + + PRES_STATE + Present State + 0x24 + 32 + read-only + 0x8080 + 0xFFFFFFFF + + + CIHB + Command Inhibit (CMD) + 0 + 1 + read-only + + + CIHB_0 + Can issue command using only CMD line + 0 + + + CIHB_1 + Cannot issue command + 0x1 + + + + + CDIHB + Command Inhibit (DATA) + 0x1 + 1 + read-only + + + CDIHB_0 + Can issue command which uses the DATA line + 0 + + + CDIHB_1 + Cannot issue command which uses the DATA line + 0x1 + + + + + DLA + Data Line Active + 0x2 + 1 + read-only + + + DLA_0 + DATA Line Inactive + 0 + + + DLA_1 + DATA Line Active + 0x1 + + + + + SDSTB + SD Clock Stable + 0x3 + 1 + read-only + + + SDSTB_0 + Clock is changing frequency and not stable. + 0 + + + SDSTB_1 + Clock is stable. + 0x1 + + + + + IPGOFF + IPG_CLK Gated Off Internally + 0x4 + 1 + read-only + + + IPGOFF_0 + IPG_CLK is active. + 0 + + + IPGOFF_1 + IPG_CLK is gated off. + 0x1 + + + + + HCKOFF + HCLK Gated Off Internally + 0x5 + 1 + read-only + + + HCKOFF_0 + HCLK is active. + 0 + + + HCKOFF_1 + HCLK is gated off. + 0x1 + + + + + PEROFF + IPG_PERCLK Gated Off Internally + 0x6 + 1 + read-only + + + PEROFF_0 + IPG_PERCLK is active. + 0 + + + PEROFF_1 + IPG_PERCLK is gated off. + 0x1 + + + + + SDOFF + SD Clock Gated Off Internally + 0x7 + 1 + read-only + + + SDOFF_0 + SD Clock is active. + 0 + + + SDOFF_1 + SD Clock is gated off. + 0x1 + + + + + WTA + Write Transfer Active + 0x8 + 1 + read-only + + + WTA_0 + No valid data + 0 + + + WTA_1 + Transferring data + 0x1 + + + + + RTA + Read Transfer Active + 0x9 + 1 + read-only + + + RTA_0 + No valid data + 0 + + + RTA_1 + Transferring data + 0x1 + + + + + BWEN + Buffer Write Enable + 0xA + 1 + read-only + + + BWEN_0 + Write disable + 0 + + + BWEN_1 + Write enable + 0x1 + + + + + BREN + Buffer Read Enable + 0xB + 1 + read-only + + + BREN_0 + Read disable + 0 + + + BREN_1 + Read enable + 0x1 + + + + + RTR + Re-Tuning Request (only for SD3.0 SDR104 mode) + 0xC + 1 + read-only + + + RTR_0 + Fixed or well tuned sampling clock + 0 + + + RTR_1 + Sampling clock needs re-tuning + 0x1 + + + + + TSCD + Tape Select Change Done + 0xF + 1 + read-only + + + TSCD_0 + Delay cell select change is not finished. + 0 + + + TSCD_1 + Delay cell select change is finished. + 0x1 + + + + + CINST + Card Inserted + 0x10 + 1 + read-only + + + CINST_0 + Power on Reset or No Card + 0 + + + CINST_1 + Card Inserted + 0x1 + + + + + CDPL + Card Detect Pin Level + 0x12 + 1 + read-only + + + CDPL_0 + No card present (CD_B = 1) + 0 + + + CDPL_1 + Card present (CD_B = 0) + 0x1 + + + + + WPSPL + Write Protect Switch Pin Level + 0x13 + 1 + read-only + + + WPSPL_0 + Write protected (WP = 1) + 0 + + + WPSPL_1 + Write enabled (WP = 0) + 0x1 + + + + + CLSL + CMD Line Signal Level + 0x17 + 1 + read-only + + + DLSL + DATA[7:0] Line Signal Level + 0x18 + 8 + read-only + + + + + PROT_CTRL + Protocol Control + 0x28 + 32 + read-write + 0x8800020 + 0xFFFFFFFF + + + LCTL + LED Control + 0 + 1 + read-write + + + LCTL_0 + LED off + 0 + + + LCTL_1 + LED on + 0x1 + + + + + DTW + Data Transfer Width + 0x1 + 2 + read-write + + + DTW_0 + 1-bit mode + 0 + + + DTW_1 + 4-bit mode + 0x1 + + + DTW_2 + 8-bit mode + 0x2 + + + + + D3CD + DATA3 as Card Detection Pin + 0x3 + 1 + read-write + + + D3CD_0 + DATA3 does not monitor Card Insertion + 0 + + + D3CD_1 + DATA3 as Card Detection Pin + 0x1 + + + + + EMODE + Endian Mode + 0x4 + 2 + read-write + + + EMODE_0 + Big Endian Mode + 0 + + + EMODE_1 + Half Word Big Endian Mode + 0x1 + + + EMODE_2 + Little Endian Mode + 0x2 + + + + + CDTL + Card Detect Test Level + 0x6 + 1 + read-write + + + CDTL_0 + Card Detect Test Level is 0, no card inserted + 0 + + + CDTL_1 + Card Detect Test Level is 1, card inserted + 0x1 + + + + + CDSS + Card Detect Signal Selection + 0x7 + 1 + read-write + + + CDSS_0 + Card Detection Level is selected (for normal purpose). + 0 + + + CDSS_1 + Card Detection Test Level is selected (for test purpose). + 0x1 + + + + + DMASEL + DMA Select + 0x8 + 2 + read-write + + + DMASEL_0 + No DMA or Simple DMA is selected + 0 + + + DMASEL_1 + ADMA1 is selected + 0x1 + + + DMASEL_2 + ADMA2 is selected + 0x2 + + + + + SABGREQ + Stop At Block Gap Request + 0x10 + 1 + read-write + + + SABGREQ_0 + Transfer + 0 + + + SABGREQ_1 + Stop + 0x1 + + + + + CREQ + Continue Request + 0x11 + 1 + read-write + + + CREQ_0 + No effect + 0 + + + CREQ_1 + Restart + 0x1 + + + + + RWCTL + Read Wait Control + 0x12 + 1 + read-write + + + RWCTL_0 + Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + 0 + + + RWCTL_1 + Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + 0x1 + + + + + IABG + Interrupt At Block Gap + 0x13 + 1 + read-write + + + IABG_0 + Disabled + 0 + + + IABG_1 + Enabled + 0x1 + + + + + RD_DONE_NO_8CLK + Read done no 8 clock: According to the SD/MMC spec, for read data transaction, 8 clocks are needed after the end bit of the last data block + 0x14 + 1 + read-write + + + WECINT + Wakeup Event Enable On Card Interrupt + 0x18 + 1 + read-write + + + WECINT_0 + Disable + 0 + + + WECINT_1 + Enable + 0x1 + + + + + WECINS + Wakeup Event Enable On SD Card Insertion + 0x19 + 1 + read-write + + + WECINS_0 + Disable + 0 + + + WECINS_1 + Enable + 0x1 + + + + + WECRM + Wakeup Event Enable On SD Card Removal + 0x1A + 1 + read-write + + + WECRM_0 + Disable + 0 + + + WECRM_1 + Enable + 0x1 + + + + + BURST_LEN_EN + BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + 0x1B + 3 + read-write + + + NON_EXACT_BLK_RD + Current block read is non-exact block read. It is only used for SDIO. + 0x1E + 1 + read-write + + + NON_EXACT_BLK_RD_0 + The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + 0 + + + NON_EXACT_BLK_RD_1 + The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + 0x1 + + + + + + + SYS_CTRL + System Control + 0x2C + 32 + read-write + 0x8080800F + 0xFFFFFFFF + + + DVS + Divisor + 0x4 + 4 + read-write + + + DVS_0 + Divide-by-1 + 0 + + + DVS_1 + Divide-by-2 + 0x1 + + + DVS_14 + Divide-by-15 + 0xE + + + DVS_15 + Divide-by-16 + 0xF + + + + + SDCLKFS + SDCLK Frequency Select + 0x8 + 8 + read-write + + + DTOCV + Data Timeout Counter Value + 0x10 + 4 + read-write + + + DTOCV_0 + SDCLK x 2 1 3 + 0 + + + DTOCV_1 + SDCLK x 2 14 + 0x1 + + + DTOCV_14 + SDCLK x 2 2 7 + 0xE + + + DTOCV_15 + SDCLK x 2 28 + 0xF + + + + + IPP_RST_N + This register's value will be output to CARD from pad directly for hardware reset of the card if the card supports this feature + 0x17 + 1 + read-write + + + RSTA + Software Reset For ALL + 0x18 + 1 + read-write + + + RSTA_0 + No Reset + 0 + + + RSTA_1 + Reset + 0x1 + + + + + RSTC + Software Reset For CMD Line + 0x19 + 1 + read-write + + + RSTC_0 + No Reset + 0 + + + RSTC_1 + Reset + 0x1 + + + + + RSTD + Software Reset For DATA Line + 0x1A + 1 + read-write + + + RSTD_0 + No Reset + 0 + + + RSTD_1 + Reset + 0x1 + + + + + INITA + Initialization Active + 0x1B + 1 + read-write + + + RSTT + Reset Tuning + 0x1C + 1 + read-write + + + + + INT_STATUS + Interrupt Status + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + CC + Command Complete + 0 + 1 + read-write + oneToClear + + + CC_0 + Command not complete + 0 + + + CC_1 + Command complete + 0x1 + + + + + TC + Transfer Complete + 0x1 + 1 + read-write + oneToClear + + + TC_0 + Transfer not complete + 0 + + + TC_1 + Transfer complete + 0x1 + + + + + BGE + Block Gap Event + 0x2 + 1 + read-write + oneToClear + + + BGE_0 + No block gap event + 0 + + + BGE_1 + Transaction stopped at block gap + 0x1 + + + + + DINT + DMA Interrupt + 0x3 + 1 + read-write + oneToClear + + + DINT_0 + No DMA Interrupt + 0 + + + DINT_1 + DMA Interrupt is generated + 0x1 + + + + + BWR + Buffer Write Ready + 0x4 + 1 + read-write + oneToClear + + + BWR_0 + Not ready to write buffer + 0 + + + BWR_1 + Ready to write buffer: + 0x1 + + + + + BRR + Buffer Read Ready + 0x5 + 1 + read-write + oneToClear + + + BRR_0 + Not ready to read buffer + 0 + + + BRR_1 + Ready to read buffer + 0x1 + + + + + CINS + Card Insertion + 0x6 + 1 + read-write + oneToClear + + + CINS_0 + Card state unstable or removed + 0 + + + CINS_1 + Card inserted + 0x1 + + + + + CRM + Card Removal + 0x7 + 1 + read-write + oneToClear + + + CRM_0 + Card state unstable or inserted + 0 + + + CRM_1 + Card removed + 0x1 + + + + + CINT + Card Interrupt + 0x8 + 1 + read-write + oneToClear + + + CINT_0 + No Card Interrupt + 0 + + + CINT_1 + Generate Card Interrupt + 0x1 + + + + + RTE + Re-Tuning Event: (only for SD3.0 SDR104 mode) + 0xC + 1 + read-write + oneToClear + + + RTE_0 + Re-Tuning is not required + 0 + + + RTE_1 + Re-Tuning should be performed + 0x1 + + + + + TP + Tuning Pass:(only for SD3.0 SDR104 mode) + 0xE + 1 + read-write + oneToClear + + + CTOE + Command Timeout Error + 0x10 + 1 + read-write + oneToClear + + + CTOE_0 + No Error + 0 + + + CTOE_1 + Time out + 0x1 + + + + + CCE + Command CRC Error + 0x11 + 1 + read-write + oneToClear + + + CCE_0 + No Error + 0 + + + CCE_1 + CRC Error Generated. + 0x1 + + + + + CEBE + Command End Bit Error + 0x12 + 1 + read-write + oneToClear + + + CEBE_0 + No Error + 0 + + + CEBE_1 + End Bit Error Generated + 0x1 + + + + + CIE + Command Index Error + 0x13 + 1 + read-write + oneToClear + + + CIE_0 + No Error + 0 + + + CIE_1 + Error + 0x1 + + + + + DTOE + Data Timeout Error + 0x14 + 1 + read-write + oneToClear + + + DTOE_0 + No Error + 0 + + + DTOE_1 + Time out + 0x1 + + + + + DCE + Data CRC Error + 0x15 + 1 + read-write + oneToClear + + + DCE_0 + No Error + 0 + + + DCE_1 + Error + 0x1 + + + + + DEBE + Data End Bit Error + 0x16 + 1 + read-write + oneToClear + + + DEBE_0 + No Error + 0 + + + DEBE_1 + Error + 0x1 + + + + + AC12E + Auto CMD12 Error + 0x18 + 1 + read-write + oneToClear + + + AC12E_0 + No Error + 0 + + + AC12E_1 + Error + 0x1 + + + + + TNE + Tuning Error: (only for SD3.0 SDR104 mode) + 0x1A + 1 + read-write + oneToClear + + + DMAE + DMA Error + 0x1C + 1 + read-write + oneToClear + + + DMAE_0 + No Error + 0 + + + DMAE_1 + Error + 0x1 + + + + + + + INT_STATUS_EN + Interrupt Status Enable + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCSEN + Command Complete Status Enable + 0 + 1 + read-write + + + CCSEN_0 + Masked + 0 + + + CCSEN_1 + Enabled + 0x1 + + + + + TCSEN + Transfer Complete Status Enable + 0x1 + 1 + read-write + + + TCSEN_0 + Masked + 0 + + + TCSEN_1 + Enabled + 0x1 + + + + + BGESEN + Block Gap Event Status Enable + 0x2 + 1 + read-write + + + BGESEN_0 + Masked + 0 + + + BGESEN_1 + Enabled + 0x1 + + + + + DINTSEN + DMA Interrupt Status Enable + 0x3 + 1 + read-write + + + DINTSEN_0 + Masked + 0 + + + DINTSEN_1 + Enabled + 0x1 + + + + + BWRSEN + Buffer Write Ready Status Enable + 0x4 + 1 + read-write + + + BWRSEN_0 + Masked + 0 + + + BWRSEN_1 + Enabled + 0x1 + + + + + BRRSEN + Buffer Read Ready Status Enable + 0x5 + 1 + read-write + + + BRRSEN_0 + Masked + 0 + + + BRRSEN_1 + Enabled + 0x1 + + + + + CINSSEN + Card Insertion Status Enable + 0x6 + 1 + read-write + + + CINSSEN_0 + Masked + 0 + + + CINSSEN_1 + Enabled + 0x1 + + + + + CRMSEN + Card Removal Status Enable + 0x7 + 1 + read-write + + + CRMSEN_0 + Masked + 0 + + + CRMSEN_1 + Enabled + 0x1 + + + + + CINTSEN + Card Interrupt Status Enable + 0x8 + 1 + read-write + + + CINTSEN_0 + Masked + 0 + + + CINTSEN_1 + Enabled + 0x1 + + + + + RTESEN + Re-Tuning Event Status Enable + 0xC + 1 + read-write + + + RTESEN_0 + Masked + 0 + + + RTESEN_1 + Enabled + 0x1 + + + + + TPSEN + Tuning Pass Status Enable + 0xE + 1 + read-write + + + TPSEN_0 + Masked + 0 + + + TPSEN_1 + Enabled + 0x1 + + + + + CTOESEN + Command Timeout Error Status Enable + 0x10 + 1 + read-write + + + CTOESEN_0 + Masked + 0 + + + CTOESEN_1 + Enabled + 0x1 + + + + + CCESEN + Command CRC Error Status Enable + 0x11 + 1 + read-write + + + CCESEN_0 + Masked + 0 + + + CCESEN_1 + Enabled + 0x1 + + + + + CEBESEN + Command End Bit Error Status Enable + 0x12 + 1 + read-write + + + CEBESEN_0 + Masked + 0 + + + CEBESEN_1 + Enabled + 0x1 + + + + + CIESEN + Command Index Error Status Enable + 0x13 + 1 + read-write + + + CIESEN_0 + Masked + 0 + + + CIESEN_1 + Enabled + 0x1 + + + + + DTOESEN + Data Timeout Error Status Enable + 0x14 + 1 + read-write + + + DTOESEN_0 + Masked + 0 + + + DTOESEN_1 + Enabled + 0x1 + + + + + DCESEN + Data CRC Error Status Enable + 0x15 + 1 + read-write + + + DCESEN_0 + Masked + 0 + + + DCESEN_1 + Enabled + 0x1 + + + + + DEBESEN + Data End Bit Error Status Enable + 0x16 + 1 + read-write + + + DEBESEN_0 + Masked + 0 + + + DEBESEN_1 + Enabled + 0x1 + + + + + AC12ESEN + Auto CMD12 Error Status Enable + 0x18 + 1 + read-write + + + AC12ESEN_0 + Masked + 0 + + + AC12ESEN_1 + Enabled + 0x1 + + + + + TNESEN + Tuning Error Status Enable + 0x1A + 1 + read-write + + + TNESEN_0 + Masked + 0 + + + TNESEN_1 + Enabled + 0x1 + + + + + DMAESEN + DMA Error Status Enable + 0x1C + 1 + read-write + + + DMAESEN_0 + Masked + 0 + + + DMAESEN_1 + Enabled + 0x1 + + + + + + + INT_SIGNAL_EN + Interrupt Signal Enable + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCIEN + Command Complete Interrupt Enable + 0 + 1 + read-write + + + CCIEN_0 + Masked + 0 + + + CCIEN_1 + Enabled + 0x1 + + + + + TCIEN + Transfer Complete Interrupt Enable + 0x1 + 1 + read-write + + + TCIEN_0 + Masked + 0 + + + TCIEN_1 + Enabled + 0x1 + + + + + BGEIEN + Block Gap Event Interrupt Enable + 0x2 + 1 + read-write + + + BGEIEN_0 + Masked + 0 + + + BGEIEN_1 + Enabled + 0x1 + + + + + DINTIEN + DMA Interrupt Enable + 0x3 + 1 + read-write + + + DINTIEN_0 + Masked + 0 + + + DINTIEN_1 + Enabled + 0x1 + + + + + BWRIEN + Buffer Write Ready Interrupt Enable + 0x4 + 1 + read-write + + + BWRIEN_0 + Masked + 0 + + + BWRIEN_1 + Enabled + 0x1 + + + + + BRRIEN + Buffer Read Ready Interrupt Enable + 0x5 + 1 + read-write + + + BRRIEN_0 + Masked + 0 + + + BRRIEN_1 + Enabled + 0x1 + + + + + CINSIEN + Card Insertion Interrupt Enable + 0x6 + 1 + read-write + + + CINSIEN_0 + Masked + 0 + + + CINSIEN_1 + Enabled + 0x1 + + + + + CRMIEN + Card Removal Interrupt Enable + 0x7 + 1 + read-write + + + CRMIEN_0 + Masked + 0 + + + CRMIEN_1 + Enabled + 0x1 + + + + + CINTIEN + Card Interrupt Interrupt Enable + 0x8 + 1 + read-write + + + CINTIEN_0 + Masked + 0 + + + CINTIEN_1 + Enabled + 0x1 + + + + + RTEIEN + Re-Tuning Event Interrupt Enable + 0xC + 1 + read-write + + + RTEIEN_0 + Masked + 0 + + + RTEIEN_1 + Enabled + 0x1 + + + + + TPIEN + Tuning Pass Interrupt Enable + 0xE + 1 + read-write + + + TPIEN_0 + Masked + 0 + + + TPIEN_1 + Enabled + 0x1 + + + + + CTOEIEN + Command Timeout Error Interrupt Enable + 0x10 + 1 + read-write + + + CTOEIEN_0 + Masked + 0 + + + CTOEIEN_1 + Enabled + 0x1 + + + + + CCEIEN + Command CRC Error Interrupt Enable + 0x11 + 1 + read-write + + + CCEIEN_0 + Masked + 0 + + + CCEIEN_1 + Enabled + 0x1 + + + + + CEBEIEN + Command End Bit Error Interrupt Enable + 0x12 + 1 + read-write + + + CEBEIEN_0 + Masked + 0 + + + CEBEIEN_1 + Enabled + 0x1 + + + + + CIEIEN + Command Index Error Interrupt Enable + 0x13 + 1 + read-write + + + CIEIEN_0 + Masked + 0 + + + CIEIEN_1 + Enabled + 0x1 + + + + + DTOEIEN + Data Timeout Error Interrupt Enable + 0x14 + 1 + read-write + + + DTOEIEN_0 + Masked + 0 + + + DTOEIEN_1 + Enabled + 0x1 + + + + + DCEIEN + Data CRC Error Interrupt Enable + 0x15 + 1 + read-write + + + DCEIEN_0 + Masked + 0 + + + DCEIEN_1 + Enabled + 0x1 + + + + + DEBEIEN + Data End Bit Error Interrupt Enable + 0x16 + 1 + read-write + + + DEBEIEN_0 + Masked + 0 + + + DEBEIEN_1 + Enabled + 0x1 + + + + + AC12EIEN + Auto CMD12 Error Interrupt Enable + 0x18 + 1 + read-write + + + AC12EIEN_0 + Masked + 0 + + + AC12EIEN_1 + Enabled + 0x1 + + + + + TNEIEN + Tuning Error Interrupt Enable + 0x1A + 1 + read-write + + + TNEIEN_0 + Masked + 0 + + + TNEIEN_1 + Enabled + 0x1 + + + + + DMAEIEN + DMA Error Interrupt Enable + 0x1C + 1 + read-write + + + DMAEIEN_0 + Masked + 0 + + + DMAEIEN_1 + Enable + 0x1 + + + + + + + AUTOCMD12_ERR_STATUS + Auto CMD12 Error Status + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + AC12NE + Auto CMD12 Not Executed + 0 + 1 + read-only + + + AC12NE_0 + Executed + 0 + + + AC12NE_1 + Not executed + 0x1 + + + + + AC12TOE + Auto CMD12 / 23 Timeout Error + 0x1 + 1 + read-only + + + AC12TOE_0 + No error + 0 + + + AC12TOE_1 + Time out + 0x1 + + + + + AC12EBE + Auto CMD12 / 23 End Bit Error + 0x2 + 1 + read-only + + + AC12EBE_0 + No error + 0 + + + AC12EBE_1 + End Bit Error Generated + 0x1 + + + + + AC12CE + Auto CMD12 / 23 CRC Error + 0x3 + 1 + read-only + + + AC12CE_0 + No CRC error + 0 + + + AC12CE_1 + CRC Error Met in Auto CMD12/23 Response + 0x1 + + + + + AC12IE + Auto CMD12 / 23 Index Error + 0x4 + 1 + read-only + + + AC12IE_0 + No error + 0 + + + AC12IE_1 + Error, the CMD index in response is not CMD12/23 + 0x1 + + + + + CNIBAC12E + Command Not Issued By Auto CMD12 Error + 0x7 + 1 + read-only + + + CNIBAC12E_0 + No error + 0 + + + CNIBAC12E_1 + Not Issued + 0x1 + + + + + EXECUTE_TUNING + Execute Tuning + 0x16 + 1 + read-write + + + SMP_CLK_SEL + Sample Clock Select + 0x17 + 1 + read-write + + + SMP_CLK_SEL_0 + Fixed clock is used to sample data + 0 + + + SMP_CLK_SEL_1 + Tuned clock is used to sample data + 0x1 + + + + + + + HOST_CTRL_CAP + Host Controller Capabilities + 0x40 + 32 + read-write + 0x7F3B407 + 0xFFFFFFFF + + + SDR50_SUPPORT + SDR50 support + 0 + 1 + read-only + + + SDR104_SUPPORT + SDR104 support + 0x1 + 1 + read-only + + + DDR50_SUPPORT + DDR50 support + 0x2 + 1 + read-only + + + TIME_COUNT_RETUNING + Time Counter for Retuning + 0x8 + 4 + read-write + + + USE_TUNING_SDR50 + Use Tuning for SDR50 + 0xD + 1 + read-write + + + USE_TUNING_SDR50_0 + SDR does not require tuning + 0 + + + USE_TUNING_SDR50_1 + SDR50 requires tuning + 0x1 + + + + + RETUNING_MODE + Retuning Mode + 0xE + 2 + read-only + + + RETUNING_MODE_0 + Mode 1 + 0 + + + RETUNING_MODE_1 + Mode 2 + 0x1 + + + RETUNING_MODE_2 + Mode 3 + 0x2 + + + + + MBL + Max Block Length + 0x10 + 3 + read-only + + + MBL_0 + 512 bytes + 0 + + + MBL_1 + 1024 bytes + 0x1 + + + MBL_2 + 2048 bytes + 0x2 + + + MBL_3 + 4096 bytes + 0x3 + + + + + ADMAS + ADMA Support + 0x14 + 1 + read-only + + + ADMAS_0 + Advanced DMA Not supported + 0 + + + ADMAS_1 + Advanced DMA Supported + 0x1 + + + + + HSS + High Speed Support + 0x15 + 1 + read-only + + + HSS_0 + High Speed Not Supported + 0 + + + HSS_1 + High Speed Supported + 0x1 + + + + + DMAS + DMA Support + 0x16 + 1 + read-only + + + DMAS_0 + DMA not supported + 0 + + + DMAS_1 + DMA Supported + 0x1 + + + + + SRS + Suspend / Resume Support + 0x17 + 1 + read-only + + + SRS_0 + Not supported + 0 + + + SRS_1 + Supported + 0x1 + + + + + VS33 + Voltage Support 3.3V + 0x18 + 1 + read-only + + + VS33_0 + 3.3V not supported + 0 + + + VS33_1 + 3.3V supported + 0x1 + + + + + VS30 + Voltage Support 3.0 V + 0x19 + 1 + read-only + + + VS30_0 + 3.0V not supported + 0 + + + VS30_1 + 3.0V supported + 0x1 + + + + + VS18 + Voltage Support 1.8 V + 0x1A + 1 + read-only + + + VS18_0 + 1.8V not supported + 0 + + + VS18_1 + 1.8V supported + 0x1 + + + + + + + WTMK_LVL + Watermark Level + 0x44 + 32 + read-write + 0x8100810 + 0xFFFFFFFF + + + RD_WML + Read Watermark Level + 0 + 8 + read-write + + + RD_BRST_LEN + Read Burst Length Due to system restriction, the actual burst length may not exceed 16. + 0x8 + 5 + read-write + + + WR_WML + Write Watermark Level + 0x10 + 8 + read-write + + + WR_BRST_LEN + Write Burst Length Due to system restriction, the actual burst length may not exceed 16. + 0x18 + 5 + read-write + + + + + MIX_CTRL + Mixer Control + 0x48 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + DMAEN + DMA Enable + 0 + 1 + read-write + + + DMAEN_0 + Disable + 0 + + + DMAEN_1 + Enable + 0x1 + + + + + BCEN + Block Count Enable + 0x1 + 1 + read-write + + + BCEN_0 + Disable + 0 + + + BCEN_1 + Enable + 0x1 + + + + + AC12EN + Auto CMD12 Enable + 0x2 + 1 + read-write + + + AC12EN_0 + Disable + 0 + + + AC12EN_1 + Enable + 0x1 + + + + + DDR_EN + Dual Data Rate mode selection + 0x3 + 1 + read-write + + + DTDSEL + Data Transfer Direction Select + 0x4 + 1 + read-write + + + DTDSEL_0 + Write (Host to Card) + 0 + + + DTDSEL_1 + Read (Card to Host) + 0x1 + + + + + MSBSEL + Multi / Single Block Select + 0x5 + 1 + read-write + + + MSBSEL_0 + Single Block + 0 + + + MSBSEL_1 + Multiple Blocks + 0x1 + + + + + NIBBLE_POS + In DDR 4-bit mode nibble position indictation + 0x6 + 1 + read-write + + + AC23EN + Auto CMD23 Enable + 0x7 + 1 + read-write + + + EXE_TUNE + Execute Tuning: (Only used for SD3.0, SDR104 mode) + 0x16 + 1 + read-write + + + EXE_TUNE_0 + Not Tuned or Tuning Completed + 0 + + + EXE_TUNE_1 + Execute Tuning + 0x1 + + + + + SMP_CLK_SEL + When STD_TUNING_EN is 0, this bit is used to select Tuned clock or Fixed clock to sample data / cmd (Only used for SD3 + 0x17 + 1 + read-write + + + SMP_CLK_SEL_0 + Fixed clock is used to sample data / cmd + 0 + + + SMP_CLK_SEL_1 + Tuned clock is used to sample data / cmd + 0x1 + + + + + AUTO_TUNE_EN + Auto Tuning Enable (Only used for SD3.0, SDR104 mode) + 0x18 + 1 + read-write + + + AUTO_TUNE_EN_0 + Disable auto tuning + 0 + + + AUTO_TUNE_EN_1 + Enable auto tuning + 0x1 + + + + + FBCLK_SEL + Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode) + 0x19 + 1 + read-write + + + FBCLK_SEL_0 + Feedback clock comes from the loopback CLK + 0 + + + FBCLK_SEL_1 + Feedback clock comes from the ipp_card_clk_out + 0x1 + + + + + + + FORCE_EVENT + Force Event + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FEVTAC12NE + Force Event Auto Command 12 Not Executed + 0 + 1 + write-only + + + FEVTAC12TOE + Force Event Auto Command 12 Time Out Error + 0x1 + 1 + write-only + + + FEVTAC12CE + Force Event Auto Command 12 CRC Error + 0x2 + 1 + write-only + + + FEVTAC12EBE + Force Event Auto Command 12 End Bit Error + 0x3 + 1 + write-only + + + FEVTAC12IE + Force Event Auto Command 12 Index Error + 0x4 + 1 + write-only + + + FEVTCNIBAC12E + Force Event Command Not Executed By Auto Command 12 Error + 0x7 + 1 + write-only + + + FEVTCTOE + Force Event Command Time Out Error + 0x10 + 1 + write-only + + + FEVTCCE + Force Event Command CRC Error + 0x11 + 1 + write-only + + + FEVTCEBE + Force Event Command End Bit Error + 0x12 + 1 + write-only + + + FEVTCIE + Force Event Command Index Error + 0x13 + 1 + write-only + + + FEVTDTOE + Force Event Data Time Out Error + 0x14 + 1 + write-only + + + FEVTDCE + Force Event Data CRC Error + 0x15 + 1 + write-only + + + FEVTDEBE + Force Event Data End Bit Error + 0x16 + 1 + write-only + + + FEVTAC12E + Force Event Auto Command 12 Error + 0x18 + 1 + write-only + + + FEVTTNE + Force Tuning Error + 0x1A + 1 + write-only + + + FEVTDMAE + Force Event DMA Error + 0x1C + 1 + write-only + + + FEVTCINT + Force Event Card Interrupt + 0x1F + 1 + write-only + + + + + ADMA_ERR_STATUS + ADMA Error Status Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADMAES + ADMA Error State (when ADMA Error is occurred) + 0 + 2 + read-only + + + ADMALME + ADMA Length Mismatch Error + 0x2 + 1 + read-only + + + ADMALME_0 + No Error + 0 + + + ADMALME_1 + Error + 0x1 + + + + + ADMADCE + ADMA Descritor Error + 0x3 + 1 + read-only + + + ADMADCE_0 + No Error + 0 + + + ADMADCE_1 + Error + 0x1 + + + + + + + ADMA_SYS_ADDR + ADMA System Address + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADS_ADDR + ADMA System Address + 0x2 + 30 + read-write + + + + + DLL_CTRL + DLL (Delay Line) Control + 0x60 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + DLL_CTRL_ENABLE + Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL + 0 + 1 + read-write + + + DLL_CTRL_RESET + Setting this bit to 1 force a reset on DLL + 0x1 + 1 + read-write + + + DLL_CTRL_SLV_FORCE_UPD + Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately + 0x2 + 1 + read-write + + + DLL_CTRL_SLV_DLY_TARGET0 + The delay target for the USDHC loopback read clock can be programmed in 1/16th increments of an ref_clock half-period + 0x3 + 4 + read-write + + + DLL_CTRL_GATE_UPDATE + Set this bit to 1 to prevent the DLL from updating (since when clock_in exists, glitches may appear during DLL updates) + 0x7 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE + Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to disable manual override + 0x8 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE_VAL + When SLV_OVERRIDE = 1 This field is used to select 1 of 128 physical taps manually + 0x9 + 7 + read-write + + + DLL_CTRL_SLV_DLY_TARGET1 + Refer to DLL_CTRL_SLV_DLY_TARGET0 below. + 0x10 + 3 + read-write + + + DLL_CTRL_SLV_UPDATE_INT + Slave delay line update interval + 0x14 + 8 + read-write + + + DLL_CTRL_REF_UPDATE_INT + DLL control loop update interval + 0x1C + 4 + read-write + + + + + DLL_STATUS + DLL Status + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + DLL_STS_SLV_LOCK + Slave delay-line lock status + 0 + 1 + read-only + + + DLL_STS_REF_LOCK + Reference DLL lock status + 0x1 + 1 + read-only + + + DLL_STS_SLV_SEL + Slave delay line select status + 0x2 + 7 + read-only + + + DLL_STS_REF_SEL + Reference delay line select taps. This is encoded by 7 bits for 127 taps. + 0x9 + 7 + read-only + + + + + CLK_TUNE_CTRL_STATUS + CLK Tuning Control and Status + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLY_CELL_SET_POST + Set the number of delay cells on the feedback clock between CLK_OUT and CLK_POST. + 0 + 4 + read-write + + + DLY_CELL_SET_OUT + Set the number of delay cells on the feedback clock between CLK_PRE and CLK_OUT. + 0x4 + 4 + read-write + + + DLY_CELL_SET_PRE + Set the number of delay cells on the feedback clock between the feedback clock and CLK_PRE. + 0x8 + 7 + read-write + + + NXT_ERR + NXT error which means the number of delay cells added on the feedback clock is too large + 0xF + 1 + read-only + + + TAP_SEL_POST + Reflect the number of delay cells added on the feedback clock between CLK_OUT and CLK_POST. + 0x10 + 4 + read-only + + + TAP_SEL_OUT + Reflect the number of delay cells added on the feedback clock between CLK_PRE and CLK_OUT. + 0x14 + 4 + read-only + + + TAP_SEL_PRE + Reflects the number of delay cells added on the feedback clock between the feedback clock and CLK_PRE + 0x18 + 7 + read-only + + + PRE_ERR + PRE error which means the number of delay cells added on the feedback clock is too small + 0x1F + 1 + read-only + + + + + VEND_SPEC + Vendor Specific Register + 0xC0 + 32 + read-write + 0x20007809 + 0xFFFFFFFF + + + EXT_DMA_EN + External DMA Request Enable + 0 + 1 + read-write + + + EXT_DMA_EN_0 + In any scenario, USDHC does not send out external DMA request. + 0 + + + EXT_DMA_EN_1 + When internal DMA is not active, the external DMA request will be sent out. + 0x1 + + + + + VSELECT + Voltage Selection + 0x1 + 1 + read-write + + + VSELECT_0 + Change the voltage to high voltage range, around 3.0 V + 0 + + + VSELECT_1 + Change the voltage to low voltage range, around 1.8 V + 0x1 + + + + + CONFLICT_CHK_EN + Conflict check enable. + 0x2 + 1 + read-write + + + CONFLICT_CHK_EN_0 + Conflict check disable + 0 + + + CONFLICT_CHK_EN_1 + Conflict check enable + 0x1 + + + + + AC12_WR_CHKBUSY_EN + Check busy enable after auto CMD12 for write data packet + 0x3 + 1 + read-write + + + AC12_WR_CHKBUSY_EN_0 + Do not check busy after auto CMD12 for write data packet + 0 + + + AC12_WR_CHKBUSY_EN_1 + Check busy after auto CMD12 for write data packet + 0x1 + + + + + DAT3_CD_POL + Only for debug. Polarity of DATA3 pin when it is used as card detection. + 0x4 + 1 + read-write + + + DAT3_CD_POL_0 + Card detected when DATA3 is high. + 0 + + + DAT3_CD_POL_1 + Card detected when DATA3 is low. + 0x1 + + + + + CD_POL + Only for debug. Polarity of the CD_B pin: + 0x5 + 1 + read-write + + + CD_POL_0 + CD_B pin is low active. + 0 + + + CD_POL_1 + CD_B pin is high active. + 0x1 + + + + + WP_POL + Only for debug. Polarity of the WP pin: + 0x6 + 1 + read-write + + + WP_POL_0 + WP pin is high active. + 0 + + + WP_POL_1 + WP pin is low active. + 0x1 + + + + + CLKONJ_IN_ABORT + Only for debug. Force CLK output active when sending Abort command: + 0x7 + 1 + read-write + + + CLKONJ_IN_ABORT_0 + The CLK output is active when sending abort command while data is transmitting even if the internal FIFO is full (for read) or empty (for write). + 0 + + + CLKONJ_IN_ABORT_1 + The CLK output is inactive when sending abort command while data is transmitting if the internal FIFO is full (for read) or empty (for write). + 0x1 + + + + + FRC_SDCLK_ON + Force CLK output active + 0x8 + 1 + read-write + + + FRC_SDCLK_ON_0 + CLK active or inactive is fully controlled by the hardware. + 0 + + + FRC_SDCLK_ON_1 + Force CLK active. + 0x1 + + + + + IPG_CLK_SOFT_EN + IPG_CLK Software Enable + 0xB + 1 + read-write + + + IPG_CLK_SOFT_EN_0 + Gate off the IPG_CLK + 0 + + + IPG_CLK_SOFT_EN_1 + Enable the IPG_CLK + 0x1 + + + + + HCLK_SOFT_EN + AHB Clock Software Enable + 0xC + 1 + read-write + + + HCLK_SOFT_EN_0 + Gate off the AHB clock. + 0 + + + HCLK_SOFT_EN_1 + Enable the AHB clock. + 0x1 + + + + + IPG_PERCLK_SOFT_EN + IPG_PERCLK Software Enable + 0xD + 1 + read-write + + + IPG_PERCLK_SOFT_EN_0 + Gate off the IPG_PERCLK + 0 + + + IPG_PERCLK_SOFT_EN_1 + Enable the IPG_PERCLK + 0x1 + + + + + CARD_CLK_SOFT_EN + Card Clock Software Enable + 0xE + 1 + read-write + + + CARD_CLK_SOFT_EN_0 + Gate off the sd_clk + 0 + + + CARD_CLK_SOFT_EN_1 + Enable the sd_clk + 0x1 + + + + + CRC_CHK_DIS + CRC Check Disable + 0xF + 1 + read-write + + + CRC_CHK_DIS_0 + Check CRC16 for every read data packet and check CRC bits for every write data packet + 0 + + + CRC_CHK_DIS_1 + Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + 0x1 + + + + + INT_ST_VAL + Internal State Value + 0x10 + 8 + read-only + + + CMD_BYTE_EN + Byte access + 0x1F + 1 + read-write + + + CMD_BYTE_EN_0 + Disable + 0 + + + CMD_BYTE_EN_1 + Enable + 0x1 + + + + + + + MMC_BOOT + MMC Boot Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DTOCV_ACK + Boot ACK time out counter value. + 0 + 4 + read-write + + + DTOCV_ACK_0 + SDCLK x 2^13 + 0 + + + DTOCV_ACK_1 + SDCLK x 2^14 + 0x1 + + + DTOCV_ACK_2 + SDCLK x 2^15 + 0x2 + + + DTOCV_ACK_3 + SDCLK x 2^16 + 0x3 + + + DTOCV_ACK_4 + SDCLK x 2^17 + 0x4 + + + DTOCV_ACK_5 + SDCLK x 2^18 + 0x5 + + + DTOCV_ACK_6 + SDCLK x 2^19 + 0x6 + + + DTOCV_ACK_7 + SDCLK x 2^20 + 0x7 + + + DTOCV_ACK_14 + SDCLK x 2^27 + 0xE + + + DTOCV_ACK_15 + SDCLK x 2^28 + 0xF + + + + + BOOT_ACK + Boot ACK mode select + 0x4 + 1 + read-write + + + BOOT_ACK_0 + No ack + 0 + + + BOOT_ACK_1 + Ack + 0x1 + + + + + BOOT_MODE + Boot mode select + 0x5 + 1 + read-write + + + BOOT_MODE_0 + Normal boot + 0 + + + BOOT_MODE_1 + Alternative boot + 0x1 + + + + + BOOT_EN + Boot mode enable + 0x6 + 1 + read-write + + + BOOT_EN_0 + Fast boot disable + 0 + + + BOOT_EN_1 + Fast boot enable + 0x1 + + + + + AUTO_SABG_EN + During boot, enable auto stop at block gap function + 0x7 + 1 + read-write + + + DISABLE_TIME_OUT + Disable Time Out + 0x8 + 1 + read-write + + + DISABLE_TIME_OUT_0 + Enable time out + 0 + + + DISABLE_TIME_OUT_1 + Disable time out + 0x1 + + + + + BOOT_BLK_CNT + The value defines the Stop At Block Gap value of automatic mode + 0x10 + 16 + read-write + + + + + VEND_SPEC2 + Vendor Specific 2 Register + 0xC8 + 32 + read-write + 0x6 + 0xFFFFFFFF + + + SDR104_TIMING_DIS + Timeout counter test. This bit only uses for debugging. + 0 + 1 + read-write + + + SDR104_TIMING_DIS_0 + The timeout counter for Ncr changes to 80, Ncrc changes to 21. + 0 + + + SDR104_TIMING_DIS_1 + The timeout counter for Ncr changes to 72, Ncrc changes to 15. + 0x1 + + + + + SDR104_OE_DIS + CMD_OE / DATA_OE logic generation test. This bit only uses for debugging. + 0x1 + 1 + read-write + + + SDR104_OE_DIS_0 + Drive the CMD_OE / DATA_OE for one more clock cycle after the end bit. + 0 + + + SDR104_OE_DIS_1 + Stop to drive the CMD_OE / DATA_OE at once after driving the end bit. + 0x1 + + + + + SDR104_NSD_DIS + Interrupt window after abort command is sent. This bit only uses for debugging. + 0x2 + 1 + read-write + + + SDR104_NSD_DIS_0 + Enable the interrupt window 9 cycles later after the end of the I/O abort command (or CMD12) is sent. + 0 + + + SDR104_NSD_DIS_1 + Enable the interrupt window 5 cycles later after the end of the I/O abort command (or CMD12) is sent. + 0x1 + + + + + CARD_INT_D3_TEST + Card Interrupt Detection Test + 0x3 + 1 + read-write + + + CARD_INT_D3_TEST_0 + Check the card interrupt only when DATA3 is high. + 0 + + + CARD_INT_D3_TEST_1 + Check the card interrupt by ignoring the status of DATA3. + 0x1 + + + + + TUNING_8bit_EN + Enable the auto tuning circuit to check the DATA[7:0] + 0x4 + 1 + read-write + + + TUNING_8bit_EN_0 + Tuning circuit only checks the DATA[3:0]. + 0 + + + TUNING_8bit_EN_1 + Tuning circuit only checks the DATA0. + 0x1 + + + + + TUNING_1bit_EN + Enable the auto tuning circuit to check the DATA0 only + 0x5 + 1 + read-write + + + TUNING_CMD_EN + Enable the auto tuning circuit to check the CMD line. + 0x6 + 1 + read-write + + + TUNING_CMD_EN_0 + Auto tuning circuit does not check the CMD line. + 0 + + + TUNING_CMD_EN_1 + Auto tuning circuit checks the CMD line. + 0x1 + + + + + CARD_INT_AUTO_CLR_DIS + Disable the feature to clear the Card interrupt status bit when Card Interrupt status enable bit is cleared + 0x7 + 1 + read-write + + + CARD_INT_AUTO_CLR_DIS_0 + Card interrupt status bit (CINT) can be cleared when Card Interrupt status enable bit is 0. + 0 + + + CARD_INT_AUTO_CLR_DIS_1 + Card interrupt status bit (CINT) can only be cleared by writting a 1 to CINT bit. + 0x1 + + + + + ACMD23_ARGU2_EN + Default1 + 0x17 + 1 + read-write + + + ACMD23_ARGU2_EN_0 + Disable + 0 + + + ACMD23_ARGU2_EN_1 + Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable. + 0x1 + + + + + + + TUNING_CTRL + Tuning Control Register + 0xCC + 32 + read-write + 0x212800 + 0xFFFFFFFF + + + TUNING_START_TAP + The start dealy cell point when send first CMD19 in tuning procedure. + 0 + 8 + read-write + + + TUNING_COUNTER + The MAX repeat CMD19 times in tuning procedure. + 0x8 + 8 + read-write + + + TUNING_STEP + The increasing delay cell steps in tuning procedure. + 0x10 + 3 + read-write + + + TUNING_WINDOW + Select data window value for auto tuning + 0x14 + 3 + read-write + + + STD_TUNING_EN + Standard tuning circuit and procedure enable: This bit is used to enable standard tuning circuit and procedure + 0x18 + 1 + read-write + + + + + + + USDHC2 + USDHC + USDHC + USDHC2_ + 0x2194000 + + 0 + 0xD0 + registers + + + USDHC2 + 55 + + + + ADC1 + Analog-to-Digital Converter + ADC + ADC1_ + 0x2198000 + + 0 + 0x2C + registers + + + ADC1 + 132 + + + + HC0 + Control register + 0 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + ADCH_25 + VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + 0x19 + + + ADCH_31 + Conversion Disabled. + 0x1F + + + + + AIEN + Conversion Complete Interrupt Enable/Disable Control + 0x7 + 1 + read-write + + + AIEN_0 + Conversion complete interrupt disabled + 0 + + + AIEN_1 + Conversion complete interrupt enabled + 0x1 + + + + + + + HS + Status register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COCO0 + Conversion Complete Flag + 0 + 1 + read-only + + + + + R0 + Data result register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + CDATA + Data (result of an ADC conversion) + 0 + 12 + read-only + + + + + CFG + Configuration register + 0x14 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + ADICLK + Input Clock Select + 0 + 2 + read-write + + + ADICLK_0 + IPG clock + 0 + + + ADICLK_1 + IPG clock divided by 2 + 0x1 + + + ADICLK_3 + Asynchronous clock (ADACK) + 0x3 + + + + + MODE + Conversion Mode Selection + 0x2 + 2 + read-write + + + MODE_0 + 8-bit conversion + 0 + + + MODE_1 + 10-bit conversion + 0x1 + + + MODE_2 + 12-bit conversion + 0x2 + + + + + ADLSMP + Long Sample Time Configuration + 0x4 + 1 + read-write + + + ADLSMP_0 + Short sample mode. + 0 + + + ADLSMP_1 + Long sample mode. + 0x1 + + + + + ADIV + Clock Divide Select + 0x5 + 2 + read-write + + + ADIV_0 + Input clock + 0 + + + ADIV_1 + Input clock / 2 + 0x1 + + + ADIV_2 + Input clock / 4 + 0x2 + + + ADIV_3 + Input clock / 8 + 0x3 + + + + + ADLPC + Low-Power Configuration + 0x7 + 1 + read-write + + + ADLPC_0 + ADC hard block not in low power mode. + 0 + + + ADLPC_1 + ADC hard block in low power mode. + 0x1 + + + + + ADSTS + Defines the sample time duration + 0x8 + 2 + read-write + + + ADSTS_0 + Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b + 0 + + + ADSTS_1 + Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b + 0x1 + + + ADSTS_2 + Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b + 0x2 + + + ADSTS_3 + Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b + 0x3 + + + + + ADHSC + High Speed Configuration + 0xA + 1 + read-write + + + ADHSC_0 + Normal conversion selected. + 0 + + + ADHSC_1 + High speed conversion selected. + 0x1 + + + + + REFSEL + Voltage Reference Selection + 0xB + 2 + read-write + + + REFSEL_0 + Selects VREFH/VREFL as reference voltage. + 0 + + + + + ADTRG + Conversion Trigger Select + 0xD + 1 + read-write + + + ADTRG_0 + Software trigger selected + 0 + + + + + AVGS + Hardware Average select + 0xE + 2 + read-write + + + AVGS_0 + 4 samples averaged + 0 + + + AVGS_1 + 8 samples averaged + 0x1 + + + AVGS_2 + 16 samples averaged + 0x2 + + + AVGS_3 + 32 samples averaged + 0x3 + + + + + OVWREN + Data Overwrite Enable + 0x10 + 1 + read-write + + + OVWREN_0 + Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. + 0 + + + OVWREN_1 + Enable the overwriting. + 0x1 + + + + + + + GC + General control register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACKEN + Asynchronous clock output enable + 0 + 1 + read-write + + + ADACKEN_0 + Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. + 0 + + + ADACKEN_1 + Asynchronous clock and clock output enabled regardless of the state of the ADC + 0x1 + + + + + DMAEN + DMA Enable + 0x1 + 1 + read-write + + + DMAEN_0 + DMA disabled (default) + 0 + + + DMAEN_1 + DMA enabled + 0x1 + + + + + ACREN + Compare Function Range Enable + 0x2 + 1 + read-write + + + ACREN_0 + Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. + 0 + + + ACREN_1 + Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. + 0x1 + + + + + ACFGT + Compare Function Greater Than Enable + 0x3 + 1 + read-write + + + ACFGT_0 + Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register. + 0 + + + ACFGT_1 + Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers. + 0x1 + + + + + ACFE + Compare Function Enable + 0x4 + 1 + read-write + + + ACFE_0 + Compare function disabled + 0 + + + ACFE_1 + Compare function enabled + 0x1 + + + + + AVGE + Hardware average enable + 0x5 + 1 + read-write + + + AVGE_0 + Hardware average function disabled + 0 + + + AVGE_1 + Hardware average function enabled + 0x1 + + + + + ADCO + Continuous Conversion Enable + 0x6 + 1 + read-write + + + ADCO_0 + One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0 + + + ADCO_1 + Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0x1 + + + + + CAL + Calibration + 0x7 + 1 + read-write + + + + + GS + General status register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACT + Conversion Active + 0 + 1 + read-only + + + ADACT_0 + Conversion not in progress. + 0 + + + ADACT_1 + Conversion in progress. + 0x1 + + + + + CALF + Calibration Failed Flag + 0x1 + 1 + read-write + oneToClear + + + CALF_0 + Calibration completed normally. + 0 + + + CALF_1 + Calibration failed. ADC accuracy specifications are not guaranteed. + 0x1 + + + + + AWKST + Asynchronous wakeup interrupt status + 0x2 + 1 + read-write + oneToClear + + + AWKST_0 + No asynchronous interrupt. + 0 + + + AWKST_1 + Asynnchronous wake up interrupt occured in stop mode. + 0x1 + + + + + + + CV + Compare value register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CV1 + Compare Value 1 + 0 + 12 + read-write + + + CV2 + Compare Value 2 + 0x10 + 12 + read-write + + + + + OFS + Offset correction value register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFS + Offset value + 0 + 12 + read-write + + + SIGN + Sign bit + 0xC + 1 + read-write + + + SIGN_0 + The offset value is added with the raw result + 0 + + + SIGN_1 + The offset value is subtracted from the raw converted value + 0x1 + + + + + + + CAL + Calibration value register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_CODE + Calibration Result Value + 0 + 4 + read-write + + + + + + + ADC_5HC + Analog-to-Digital Converter + ADC_5HC + ADC_5HC_ + 0x219C000 + + 0 + 0x44 + registers + + + ADC_5HC + 133 + + + + HC0 + Control register for hardware triggers + 0 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + ADCH_25 + VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + 0x19 + + + ADCH_31 + Conversion Disabled. Hardware Triggers will not initiate any conversion. + 0x1F + + + + + AIEN + Conversion Complete Interrupt Enable/Disable Control + 0x7 + 1 + read-write + + + AIEN_0 + Conversion complete interrupt disabled + 0 + + + AIEN_1 + Conversion complete interrupt enabled + 0x1 + + + + + + + 4 + 0x4 + 1,2,3,4 + HC%s + Control register for hardware triggers + 0x4 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + ADCH_25 + VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + 0x19 + + + ADCH_31 + Conversion Disabled. Hardware Triggers will not initiate any conversion. + 0x1F + + + + + AIEN + Conversion Complete Interrupt Enable/Disable Control + 0x7 + 1 + read-write + + + AIEN_0 + Conversion complete interrupt disabled + 0 + + + AIEN_1 + Conversion complete interrupt enabled + 0x1 + + + + + + + HS + Status register for HW triggers + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + COCO0 + Conversion Complete Flag + 0 + 1 + read-only + + + COCO1 + See description for COCO0. + 0x1 + 1 + read-only + + + COCO2 + See description for COCO0. + 0x2 + 1 + read-only + + + COCO3 + See description for COCO0. + 0x3 + 1 + read-only + + + COCO4 + See description for COCO0. + 0x4 + 1 + read-only + + + + + R0 + Data result register for HW triggers + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + CDATA + Data (result of an ADC conversion) + 0 + 12 + read-only + + + + + 4 + 0x4 + 1,2,3,4 + R%s + Data result register for HW triggers + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CDATA + Data (result of an ADC conversion) + 0 + 12 + read-only + + + + + CFG + Configuration register + 0x2C + 32 + read-write + 0x200 + 0xFFFFFFFF + + + ADICLK + Input Clock Select + 0 + 2 + read-write + + + ADICLK_0 + IPG clock + 0 + + + ADICLK_1 + IPG clock divided by 2 + 0x1 + + + ADICLK_3 + Asynchronous clock (ADACK) + 0x3 + + + + + MODE + Conversion Mode Selection + 0x2 + 2 + read-write + + + MODE_0 + 8-bit conversion + 0 + + + MODE_1 + 10-bit conversion + 0x1 + + + MODE_2 + 12-bit conversion + 0x2 + + + + + ADLSMP + Long Sample Time Configuration + 0x4 + 1 + read-write + + + ADLSMP_0 + Short sample mode. + 0 + + + ADLSMP_1 + Long sample mode. + 0x1 + + + + + ADIV + Clock Divide Select + 0x5 + 2 + read-write + + + ADIV_0 + Input clock + 0 + + + ADIV_1 + Input clock / 2 + 0x1 + + + ADIV_2 + Input clock / 4 + 0x2 + + + ADIV_3 + Input clock / 8 + 0x3 + + + + + ADLPC + Low-Power Configuration + 0x7 + 1 + read-write + + + ADLPC_0 + ADC hard block not in low power mode. + 0 + + + ADLPC_1 + ADC hard block in low power mode. + 0x1 + + + + + ADSTS + Defines the sample time duration + 0x8 + 2 + read-write + + + ADSTS_0 + Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b + 0 + + + ADSTS_1 + Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b + 0x1 + + + ADSTS_2 + Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b + 0x2 + + + ADSTS_3 + Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b + 0x3 + + + + + ADHSC + High Speed Configuration + 0xA + 1 + read-write + + + ADHSC_0 + Normal conversion selected. + 0 + + + ADHSC_1 + High speed conversion selected. + 0x1 + + + + + REFSEL + Voltage Reference Selection + 0xB + 2 + read-write + + + REFSEL_0 + Selects VREFH/VREFL as reference voltage. + 0 + + + + + ADTRG + Conversion Trigger Select + 0xD + 1 + read-write + + + ADTRG_0 + Software trigger selected + 0 + + + ADTRG_1 + Hardware trigger selected + 0x1 + + + + + AVGS + Hardware Average select + 0xE + 2 + read-write + + + AVGS_0 + 4 samples averaged + 0 + + + AVGS_1 + 8 samples averaged + 0x1 + + + AVGS_2 + 16 samples averaged + 0x2 + + + AVGS_3 + 32 samples averaged + 0x3 + + + + + OVWREN + Data Overwrite Enable + 0x10 + 1 + read-write + + + OVWREN_0 + Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. + 0 + + + OVWREN_1 + Enable the overwriting. + 0x1 + + + + + + + GC + General control register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACKEN + Asynchronous clock output enable + 0 + 1 + read-write + + + ADACKEN_0 + Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. + 0 + + + ADACKEN_1 + Asynchronous clock and clock output enabled regardless of the state of the ADC + 0x1 + + + + + DMAEN + DMA Enable + 0x1 + 1 + read-write + + + DMAEN_0 + DMA disabled (default) + 0 + + + DMAEN_1 + DMA enabled + 0x1 + + + + + ACREN + Compare Function Range Enable + 0x2 + 1 + read-write + + + ACREN_0 + Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. + 0 + + + ACREN_1 + Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. + 0x1 + + + + + ACFGT + Compare Function Greater Than Enable + 0x3 + 1 + read-write + + + ACFGT_0 + Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register. + 0 + + + ACFGT_1 + Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers. + 0x1 + + + + + ACFE + Compare Function Enable + 0x4 + 1 + read-write + + + ACFE_0 + Compare function disabled + 0 + + + ACFE_1 + Compare function enabled + 0x1 + + + + + AVGE + Hardware average enable + 0x5 + 1 + read-write + + + AVGE_0 + Hardware average function disabled + 0 + + + AVGE_1 + Hardware average function enabled + 0x1 + + + + + ADCO + Continuous Conversion Enable + 0x6 + 1 + read-write + + + ADCO_0 + One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0 + + + ADCO_1 + Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0x1 + + + + + CAL + Calibration + 0x7 + 1 + read-write + + + + + GS + General status register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACT + Conversion Active + 0 + 1 + read-only + + + ADACT_0 + Conversion not in progress. + 0 + + + ADACT_1 + Conversion in progress. + 0x1 + + + + + CALF + Calibration Failed Flag + 0x1 + 1 + read-write + oneToClear + + + CALF_0 + Calibration completed normally. + 0 + + + CALF_1 + Calibration failed. ADC accuracy specifications are not guaranteed. + 0x1 + + + + + AWKST + Asynchronous wakeup interrupt status + 0x2 + 1 + read-write + oneToClear + + + AWKST_0 + No asynchronous interrupt. + 0 + + + AWKST_1 + Asynnchronous wake up interrupt occured in stop mode. + 0x1 + + + + + + + CV + Compare value register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + CV1 + Compare Value 1 + 0 + 12 + read-write + + + CV2 + Compare Value 2 + 0x10 + 12 + read-write + + + + + OFS + Offset correction value register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + OFS + Offset value + 0 + 12 + read-write + + + SIGN + Sign bit + 0xC + 1 + read-write + + + SIGN_0 + The offset value is added with the raw result + 0 + + + SIGN_1 + The offset value is subtracted from the raw converted value + 0x1 + + + + + + + CAL + Calibration value register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_CODE + Calibration Result Value + 0 + 4 + read-write + + + + + + + I2C1 + I2C + I2C + I2C1_ + 0x21A0000 + I2C + + 0 + 0x12 + registers + + + I2C1 + 68 + + + + IADR + I2C Address Register + 0 + 16 + read-write + 0 + 0xFFFF + + + ADR + Slave address + 0x1 + 7 + read-write + + + + + IFDR + I2C Frequency Divider Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + IC + I2C clock rate + 0 + 6 + read-write + + + + + I2CR + I2C Control Register + 0x8 + 16 + read-write + 0 + 0xFFFF + + + RSTA + Repeat start + 0x2 + 1 + write-only + + + RSTA_0 + No repeat start + 0 + + + RSTA_1 + Generates a Repeated Start condition + 0x1 + + + + + TXAK + Transmit acknowledge enable + 0x3 + 1 + read-write + + + TXAK_0 + An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. + 0 + + + TXAK_1 + No acknowledge signal response is sent (that is, the acknowledge bit = 1). + 0x1 + + + + + MTX + Transmit/Receive mode select bit. Selects the direction of master and slave transfers. + 0x4 + 1 + read-write + + + MTX_0 + Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in the I2C status register (I2C_I2SR[SRW]). + 0 + + + MTX_1 + Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1. + 0x1 + + + + + MSTA + Master/Slave mode select bit + 0x5 + 1 + read-write + + + MSTA_0 + Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode. + 0 + + + MSTA_1 + Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode. + 0x1 + + + + + IIEN + I2C interrupt enable + 0x6 + 1 + read-write + + + IIEN_0 + I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition occurs. + 0 + + + IIEN_1 + I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set. + 0x1 + + + + + IEN + I2C enable + 0x7 + 1 + read-write + + + IEN_0 + The block is disabled, but registers can still be accessed. + 0 + + + IEN_1 + The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect. + 0x1 + + + + + + + I2SR + I2C Status Register + 0xC + 16 + read-write + 0x81 + 0xFFFF + + + RXAK + Received acknowledge + 0 + 1 + read-only + + + RXAK_0 + An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus. + 0 + + + RXAK_1 + A "No acknowledge" signal was detected at the ninth clock. + 0x1 + + + + + IIF + I2C interrupt + 0x1 + 1 + read-write + + + IIF_0 + No I2C interrupt pending. + 0 + + + IIF_1 + An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific address in Slave Receive mode. Arbitration is lost. + 0x1 + + + + + SRW + Slave read/write + 0x2 + 1 + read-only + + + SRW_0 + Slave receive, master writing to slave + 0 + + + SRW_1 + Slave transmit, master reading from slave + 0x1 + + + + + IAL + Arbitration lost + 0x4 + 1 + read-write + + + IAL_0 + No arbitration lost. + 0 + + + IAL_1 + Arbitration is lost. + 0x1 + + + + + IBB + I2C bus busy bit + 0x5 + 1 + read-only + + + IBB_0 + Bus is idle. If a Stop signal is detected, IBB is cleared. + 0 + + + IBB_1 + Bus is busy. When Start is detected, IBB is set. + 0x1 + + + + + IAAS + I2C addressed as a slave bit + 0x6 + 1 + read-only + + + IAAS_0 + Not addressed + 0 + + + IAAS_1 + Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address. + 0x1 + + + + + ICF + Data transferring bit. While one byte of data is transferred, ICF is cleared. + 0x7 + 1 + read-only + + + ICF_0 + Transfer is in progress. + 0 + + + ICF_1 + Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer. + 0x1 + + + + + + + I2DR + I2C Data I/O Register + 0x10 + 16 + read-write + 0 + 0xFFFF + + + DATA + Data Byte + 0 + 8 + read-write + + + + + + + I2C2 + I2C + I2C + I2C2_ + 0x21A4000 + + 0 + 0x12 + registers + + + I2C2 + 69 + + + + I2C3 + I2C + I2C + I2C3_ + 0x21A8000 + + 0 + 0x12 + registers + + + I2C3 + 70 + + + + I2C4 + I2C + I2C + I2C4_ + 0x21F8000 + + 0 + 0x12 + registers + + + I2C4 + 67 + + + + ROMC + ROMC + ROMC + ROMC_ + 0x21AC000 + + 0 + 0x20C + registers + + + + 8 + 0x4 + 7,6,5,4,3,2,1,0 + ROMPATCH%sD + ROMC Data Registers + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATAX + Data Fix Registers - Stores the data used for 1-word data fix operations + 0 + 32 + read-write + + + + + ROMPATCHCNTL + ROMC Control Register + 0xF4 + 32 + read-write + 0x8400000 + 0xFFFFFFFF + + + DATAFIX + Data Fix Enable - Controls the use of the first 8 address comparators for 1-word data fix or for code patch routine + 0 + 8 + read-write + + + DATAFIX_0 + Address comparator triggers a opcode patch + 0 + + + DATAFIX_1 + Address comparator triggers a data fix + 0x1 + + + + + DIS + ROMC Disable -- This bit, when set, disables all ROMC operations + 0x1D + 1 + read-write + + + DIS_0 + Does not affect any ROMC functions (default) + 0 + + + DIS_1 + Disable all ROMC functions: data fixing, and opcode patching + 0x1 + + + + + + + ROMPATCHENH + ROMC Enable Register High + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ROMPATCHENL + ROMC Enable Register Low + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable Address Comparator - This bit enables the corresponding address comparator to trigger an event + 0 + 16 + read-write + + + ENABLE_0 + Address comparator disabled + 0 + + + ENABLE_1 + Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + 0x1 + + + + + + + 16 + 0x4 + ROMPATCH%sA + ROMC Address Registers + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + THUMBX + THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an ARM opcode patch + 0 + 1 + read-write + + + THUMBX_0 + ARM patch + 0 + + + THUMBX_1 + THUMB patch (ignore if data fix) + 0x1 + + + + + ADDRX + Address Comparator Registers - Indicates the memory address to be watched + 0x1 + 22 + read-write + + + + + ROMPATCHSR + ROMC Status Register + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOURCE + ROMC Source Number - Binary encoding of the number of the address comparator which has an address match in the most recent patch event on ROMC AHB + 0 + 6 + read-only + + + SOURCE_0 + Address Comparator 0 matched + 0 + + + SOURCE_1 + Address Comparator 1 matched + 0x1 + + + SOURCE_15 + Address Comparator 15 matched + 0xF + + + + + SW + ROMC AHB Multiple Address Comparator matches Indicator - Indicates that multiple address comparator matches occurred + 0x11 + 1 + read-write + oneToClear + + + SW_0 + no event or comparator collisions + 0 + + + SW_1 + a collision has occurred + 0x1 + + + + + + + + + MMDC + MMDC + MMDC + MMDC_ + 0x21B0000 + + 0 + 0x8C4 + registers + + + + MDCTL + MMDC Core Control Register + 0 + 32 + read-write + 0x3110000 + 0xFFFFFFFF + + + DSIZ + DDR data bus size. This field determines the size of the data bus of the DDR memory + 0x10 + 2 + read-write + + + DSIZ_0 + 16-bit data bus + 0 + + + + + BL + Burst Length + 0x13 + 1 + read-write + + + BL_0 + Burst Length 4 is used + 0 + + + BL_1 + Burst Length 8 is used + 0x1 + + + + + COL + Column Address Width + 0x14 + 3 + read-write + + + COL_0 + 9 bits column + 0 + + + COL_1 + 10 bits column + 0x1 + + + COL_2 + 11 bits column + 0x2 + + + COL_3 + 8 bits column + 0x3 + + + COL_4 + 12 bits column + 0x4 + + + + + ROW + Row Address Width + 0x18 + 3 + read-write + + + ROW_0 + 11 bits Row + 0 + + + ROW_1 + 12 bits Row + 0x1 + + + ROW_2 + 13 bits Row + 0x2 + + + ROW_3 + 14 bits Row + 0x3 + + + ROW_4 + 15 bits Row + 0x4 + + + ROW_5 + 16 bits Row + 0x5 + + + + + SDE_1 + MMDC Enable CS1 + 0x1E + 1 + read-write + + + SDE_1_0 + Disabled + 0 + + + SDE_1_1 + Enabled + 0x1 + + + + + SDE_0 + MMDC Enable CS0 + 0x1F + 1 + read-write + + + SDE_0_0 + Disabled + 0 + + + SDE_0_1 + Enabled + 0x1 + + + + + + + MDPDC + MMDC Core Power Down Control Register + 0x4 + 32 + read-write + 0x30012 + 0xFFFFFFFF + + + tCKSRE + Valid clock cycles after self-refresh entry + 0 + 3 + read-write + + + tCKSRE_0 + 0 cycle + 0 + + + tCKSRE_1 + 1 cycles + 0x1 + + + tCKSRE_6 + 6 cycles + 0x6 + + + tCKSRE_7 + 7 cycles + 0x7 + + + + + tCKSRX + Valid clock cycles before self-refresh exit + 0x3 + 3 + read-write + + + tCKSRX_0 + 0 cycle + 0 + + + tCKSRX_1 + 1 cycles + 0x1 + + + tCKSRX_6 + 6 cycles + 0x6 + + + tCKSRX_7 + 7 cycles + 0x7 + + + + + BOTH_CS_PD + Parallel power down entry to both chip selects + 0x6 + 1 + read-write + + + BOTH_CS_PD_0 + Each chip select can enter power down independently according to its configuration. + 0 + + + BOTH_CS_PD_1 + Chip selects can enter power down only if the amount of idle cycles of both chip selects was obtained. + 0x1 + + + + + SLOW_PD + Slow/fast power down + 0x7 + 1 + read-write + + + SLOW_PD_0 + Fast mode. + 0 + + + SLOW_PD_1 + Slow mode. + 0x1 + + + + + PWDT_0 + Power Down Timer - Chip Select 0 + 0x8 + 4 + read-write + + + PWDT_1 + Power Down Timer - Chip Select 1 + 0xC + 4 + read-write + + + tCKE + CKE minimum pulse width. This field determines the minimum pulse width of CKE. + 0x10 + 3 + read-write + + + tCKE_0 + 1 cycle + 0 + + + tCKE_1 + 2 cycles + 0x1 + + + tCKE_6 + 7 cycles + 0x6 + + + tCKE_7 + 8 cycles + 0x7 + + + + + PRCT_0 + Precharge Timer - Chip Select 0 + 0x18 + 3 + read-write + + + PRCT_1 + Precharge Timer - Chip Select 1 + 0x1C + 3 + read-write + + + + + MDOTC + MMDC Core ODT Timing Control Register + 0x8 + 32 + read-write + 0x12272000 + 0xFFFFFFFF + + + tODT_idle_off + ODT turn off latency + 0x4 + 5 + read-write + + + tODT_idle_off_0 + 0 cycle (turned off at the earliest possible time) + 0 + + + tODT_idle_off_1 + 1 cycle + 0x1 + + + tODT_idle_off_2 + 2 cycles + 0x2 + + + tODT_idle_off_30 + 30 cycles + 0x1E + + + tODT_idle_off_31 + 31 cycles + 0x1F + + + + + tODTLon + ODT turn on latency + 0xC + 3 + read-write + + + tODTLon_0 + - 0x1 Reserved + 0 + + + tODTLon_2 + 2 cycles + 0x2 + + + tODTLon_3 + 3 cycles + 0x3 + + + tODTLon_4 + 4 cycles + 0x4 + + + tODTLon_5 + 5 cycles + 0x5 + + + tODTLon_6 + 6 cycles + 0x6 + + + + + tAXPD + Asynchronous ODT to power down exit delay + 0x10 + 4 + read-write + + + tAXPD_0 + 1 clock + 0 + + + tAXPD_1 + 2 clocks + 0x1 + + + tAXPD_2 + 3 clocks + 0x2 + + + tAXPD_14 + 15 clocks + 0xE + + + tAXPD_15 + 16 clocks + 0xF + + + + + tANPD + Asynchronous ODT to power down entry delay + 0x14 + 4 + read-write + + + tANPD_0 + 1 clock + 0 + + + tANPD_1 + 2 clocks + 0x1 + + + tANPD_2 + 3 clocks + 0x2 + + + tANPD_14 + 15 clocks + 0xE + + + tANPD_15 + 16 clocks + 0xF + + + + + tAONPD + Asynchronous RTT turn-on delay (power down with DLL frozen) + 0x18 + 3 + read-write + + + tAONPD_0 + 1 cycle + 0 + + + tAONPD_1 + 2 cycles + 0x1 + + + tAONPD_6 + 7 cycles + 0x6 + + + tAONPD_7 + 8 cycles + 0x7 + + + + + tAOFPD + Asynchronous RTT turn-off delay (power down with DLL frozen) + 0x1B + 3 + read-write + + + tAOFPD_0 + 1 cycle + 0 + + + tAOFPD_1 + 2 cycles + 0x1 + + + tAOFPD_6 + 7 cycles + 0x6 + + + tAOFPD_7 + 8 cycles + 0x7 + + + + + + + MDCFG0 + MMDC Core Timing Configuration Register 0 + 0xC + 32 + read-write + 0x323622D3 + 0xFFFFFFFF + + + tCL + CAS Read Latency + 0 + 4 + read-write + + + tCL_0 + 3 cycles + 0 + + + tCL_1 + 4 cycles + 0x1 + + + tCL_2 + 5 cycles + 0x2 + + + tCL_3 + 6 cycles + 0x3 + + + tCL_4 + 7 cycles + 0x4 + + + tCL_5 + 8 cycles + 0x5 + + + tCL_6 + 9 cycles + 0x6 + + + tCL_7 + 10 cycles + 0x7 + + + tCL_8 + 11 cycles + 0x8 + + + tCL_9 + - 0xF Reserved + 0x9 + + + + + tFAW + Four Active Window (all banks) + 0x4 + 5 + read-write + + + tFAW_0 + 1 clock + 0 + + + tFAW_1 + 2 clocks + 0x1 + + + tFAW_2 + 3 clocks + 0x2 + + + tFAW_30 + 31 clocks + 0x1E + + + tFAW_31 + 32 clocks + 0x1F + + + + + tXPDLL + Exit precharge power down with DLL frozen to commands requiring DLL + 0x9 + 4 + read-write + + + tXPDLL_0 + 1 clock + 0 + + + tXPDLL_1 + 2 clocks + 0x1 + + + tXPDLL_2 + 3 clocks + 0x2 + + + tXPDLL_14 + 15 clocks + 0xE + + + tXPDLL_15 + 16 clocks + 0xF + + + + + tXP + Exit power down with DLL-on to any valid command + 0xD + 3 + read-write + + + tXP_0 + 1 cycle + 0 + + + tXP_1 + 2 cycles + 0x1 + + + tXP_6 + 7 cycles + 0x6 + + + tXP_7 + 8 cycles + 0x7 + + + + + tXS + Exit self refresh to non READ command + 0x10 + 8 + read-write + + + tXS_0 + - 0x15 reserved + 0 + + + tXS_22 + 23 clocks + 0x16 + + + tXS_23 + 24 clocks + 0x17 + + + tXS_254 + 255 clocks + 0xFE + + + tXS_255 + 256 clocks + 0xFF + + + + + tRFC + Refresh command to Active or Refresh command time + 0x18 + 8 + read-write + + + tRFC_0 + 1 clock + 0 + + + tRFC_1 + 2 clocks + 0x1 + + + tRFC_2 + 3 clocks + 0x2 + + + tRFC_254 + 255 clocks + 0xFE + + + tRFC_255 + 256 clocks + 0xFF + + + + + + + MDCFG1 + MMDC Core Timing Configuration Register 1 + 0x10 + 32 + read-write + 0xB6B18A23 + 0xFFFFFFFF + + + tCWL + CAS Write Latency + 0 + 3 + read-write + + + tCWL_0 + 2 cycles (DDR2/DDR3) , 1 cycles (LPDDR2/LPDDR3) + 0 + + + tCWL_1 + 3 cycles (DDR2/DDR3) , 2 cycles (LPDDR2/LPDDR3) + 0x1 + + + tCWL_2 + 4 cycles (DDR2/DDR3) , 3 cycles (LPDDR2/LPDDR3) + 0x2 + + + tCWL_3 + 5 cycles (DDR2/DDR3) , 4 cycles (LPDDR2/LPDDR3) + 0x3 + + + tCWL_4 + 6 cycles (DDR2/DDR3) , 5 cycles (LPDDR2/LPDDR3) + 0x4 + + + tCWL_5 + 7 cycles (DDR2/DDR3) , 6 cycles (LPDDR2/LPDDR3) + 0x5 + + + tCWL_6 + 8 cycles (DDR2/DDR3) , 7 cycles (LPDDR2/LPDDR3) + 0x6 + + + + + tMRD + Mode Register Set command cycle (all banks) + 0x5 + 4 + read-write + + + tMRD_0 + 1 clock + 0 + + + tMRD_1 + 2 clocks + 0x1 + + + tMRD_2 + 3 clocks + 0x2 + + + tMRD_14 + 15 clocks + 0xE + + + tMRD_15 + 16 clocks + 0xF + + + + + tWR + WRITE recovery time (same bank) + 0x9 + 3 + read-write + + + tWR_0 + 1cycle + 0 + + + tWR_1 + 2cycles + 0x1 + + + tWR_2 + 3cycles + 0x2 + + + tWR_3 + 4cycles + 0x3 + + + tWR_4 + 5cycles + 0x4 + + + tWR_5 + 6cycles + 0x5 + + + tWR_6 + 7cycles + 0x6 + + + tWR_7 + 8 cycles + 0x7 + + + + + tRPA + Precharge-all command period + 0xF + 1 + read-write + + + tRPA_0 + Will be equal to: tRP. + 0 + + + tRPA_1 + Will be equal to: tRP+1. + 0x1 + + + + + tRAS + Active to Precharge command period (same bank) + 0x10 + 5 + read-write + + + tRAS_0 + 1 clock + 0 + + + tRAS_1 + 2 clocks + 0x1 + + + tRAS_2 + 3 clocks + 0x2 + + + tRAS_30 + 31 clocks + 0x1E + + + + + tRC + Active to Active or Refresh command period (same bank) + 0x15 + 5 + read-write + + + tRC_0 + 1 clock + 0 + + + tRC_1 + 2 clocks + 0x1 + + + tRC_2 + 3 clocks + 0x2 + + + tRC_30 + 31 clocks + 0x1E + + + tRC_31 + 32 clocks + 0x1F + + + + + tRP + Precharge command period (same bank) + 0x1A + 3 + read-write + + + tRP_0 + 1 clock + 0 + + + tRP_1 + 2 clocks + 0x1 + + + tRP_2 + 3 clocks + 0x2 + + + tRP_3 + 4 clocks + 0x3 + + + tRP_4 + 5 clocks + 0x4 + + + tRP_5 + 6 clocks + 0x5 + + + tRP_6 + 7 clocks + 0x6 + + + tRP_7 + 8 clocks + 0x7 + + + + + tRCD + Active command to internal read or write delay time (same bank) + 0x1D + 3 + read-write + + + tRCD_0 + 1 clock + 0 + + + tRCD_1 + 2 clocks + 0x1 + + + tRCD_2 + 3 clocks + 0x2 + + + tRCD_3 + 4 clocks + 0x3 + + + tRCD_4 + 5 clocks + 0x4 + + + tRCD_5 + 6 clocks + 0x5 + + + tRCD_6 + 7 clocks + 0x6 + + + tRCD_7 + 8 clocks + 0x7 + + + + + + + MDCFG2 + MMDC Core Timing Configuration Register 2 + 0x14 + 32 + read-write + 0xC70092 + 0xFFFFFFFF + + + tRRD + Active to Active command period (all banks) + 0 + 3 + read-write + + + tRRD_0 + 1cycle + 0 + + + tRRD_1 + 2cycles + 0x1 + + + tRRD_2 + 3cycles + 0x2 + + + tRRD_3 + 4cycles + 0x3 + + + tRRD_4 + 5cycles + 0x4 + + + tRRD_5 + 6cycles + 0x5 + + + tRRD_6 + 7cycles + 0x6 + + + + + tWTR + Internal WRITE to READ command delay (same bank) + 0x3 + 3 + read-write + + + tWTR_0 + 1cycle + 0 + + + tWTR_1 + 2cycles + 0x1 + + + tWTR_2 + 3cycles + 0x2 + + + tWTR_3 + 4cycles + 0x3 + + + tWTR_4 + 5cycles + 0x4 + + + tWTR_5 + 6cycles + 0x5 + + + tWTR_6 + 7cycles + 0x6 + + + tWTR_7 + 8 cycles + 0x7 + + + + + tRTP + Internal READ command to Precharge command delay (same bank) + 0x6 + 3 + read-write + + + tRTP_0 + 1cycle + 0 + + + tRTP_1 + 2cycles + 0x1 + + + tRTP_2 + 3cycles + 0x2 + + + tRTP_3 + 4cycles + 0x3 + + + tRTP_4 + 5cycles + 0x4 + + + tRTP_5 + 6cycles + 0x5 + + + tRTP_6 + 7cycles + 0x6 + + + tRTP_7 + 8 cycles + 0x7 + + + + + tDLLK + DLL locking time + 0x10 + 9 + read-write + + + tDLLK_0 + 1 cycle. + 0 + + + tDLLK_1 + 2 cycles. + 0x1 + + + tDLLK_2 + 3 cycles. + 0x2 + + + tDLLK_199 + 200 cycles + 0xC7 + + + tDLLK_510 + 511 cycles. + 0x1FE + + + tDLLK_511 + 512 cycles (JEDEC value for DDR3). + 0x1FF + + + + + + + MDMISC + MMDC Core Miscellaneous Register + 0x18 + 32 + read-write + 0x1600 + 0xFFFFFFFF + + + RST + Software Reset + 0x1 + 1 + read-write + + + RST_0 + Do nothing. + 0 + + + RST_1 + Assert reset to the MMDC. + 0x1 + + + + + DDR_TYPE + DDR TYPE. This field determines the type of the external DDR device. + 0x3 + 2 + read-write + + + DDR_TYPE_0 + DDR3 device is used. + 0 + + + DDR_TYPE_1 + LPDDR2 device is used. + 0x1 + + + + + DDR_4_BANK + Number of banks per DDR device + 0x5 + 1 + read-write + + + DDR_4_BANK_0 + 8 banks device is being used. (Default) + 0 + + + DDR_4_BANK_1 + 4 banks device is being used + 0x1 + + + + + RALAT + Read Additional Latency + 0x6 + 3 + read-write + + + RALAT_0 + no additional latency. + 0 + + + RALAT_1 + 1 cycle additional latency. + 0x1 + + + RALAT_2 + 2 cycles additional latency. + 0x2 + + + RALAT_3 + 3 cycles additional latency. + 0x3 + + + RALAT_4 + 4 cycles additional latency. + 0x4 + + + RALAT_5 + 5 cycles additional latency. + 0x5 + + + RALAT_6 + 6 cycles additional latency. + 0x6 + + + RALAT_7 + 7 cycles additional latency. + 0x7 + + + + + MIF3_MODE + Command prediction working mode + 0x9 + 2 + read-write + + + MIF3_MODE_0 + Disable prediction. + 0 + + + MIF3_MODE_1 + Enable prediction based on : Valid access on first pipe line stage. + 0x1 + + + MIF3_MODE_2 + Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus. + 0x2 + + + MIF3_MODE_3 + Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus, Next miss access from access queue. + 0x3 + + + + + LPDDR2_S2 + LPDDR2 S2 device type indication + 0xB + 1 + read-write + + + LPDDR2_S2_0 + LPDDR2-S4 device is used. + 0 + + + LPDDR2_S2_1 + LPDDR2-S2 device is used. + 0x1 + + + + + BI_ON + Bank Interleaving On + 0xC + 1 + read-write + + + BI_ON_0 + Banks are not interleaved, and address will be decoded as bank-row-column + 0 + + + BI_ON_1 + Banks are interleaved, and address will be decoded as row-bank-column + 0x1 + + + + + WALAT + Write Additional latency + 0x10 + 2 + read-write + + + WALAT_0 + No additional latency required. + 0 + + + WALAT_1 + 1 cycle additional delay + 0x1 + + + WALAT_2 + 2 cycles additional delay + 0x2 + + + WALAT_3 + 3 cycles additional delay + 0x3 + + + + + LHD + Latency hiding disable + 0x12 + 1 + read-write + + + LHD_0 + Latency hiding on. + 0 + + + LHD_1 + Latency hiding disable. + 0x1 + + + + + ADDR_MIRROR + Address mirroring + 0x13 + 1 + read-write + + + ADDR_MIRROR_0 + Address mirroring disabled. + 0 + + + ADDR_MIRROR_1 + Address mirroring enabled. + 0x1 + + + + + CALIB_PER_CS + Number of chip-select for calibration process + 0x14 + 1 + read-write + + + CALIB_PER_CS_0 + Calibration is targetted to CS0 + 0 + + + CALIB_PER_CS_1 + Calibration is targetted to CS1 + 0x1 + + + + + CK1_GATING + Gating the secondary DDR clock + 0x15 + 1 + read-write + + + CK1_GATING_0 + MMDC drives two clocks toward the DDR memory + 0 + + + CK1_GATING_1 + MMDC drives only one clock toward the DDR memory (CK0) + 0x1 + + + + + CS1_RDY + External status device on CS1 + 0x1E + 1 + read-only + + + CS1_RDY_0 + Device in wake-up period. + 0 + + + CS1_RDY_1 + Device is ready for initialization. + 0x1 + + + + + CS0_RDY + External status device on CS0 + 0x1F + 1 + read-only + + + CS0_RDY_0 + Device in wake-up period. + 0 + + + CS0_RDY_1 + Device is ready for initialization. + 0x1 + + + + + + + MDSCR + MMDC Core Special Command Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD_BA + Bank Address + 0 + 3 + read-write + + + CMD_BA_0 + bank address 0 + 0 + + + CMD_BA_1 + bank address 1 + 0x1 + + + CMD_BA_2 + bank address 2 + 0x2 + + + CMD_BA_7 + bank address 7 + 0x7 + + + + + CMD_CS + Chip Select. This field determines which chip select the command is targeted to + 0x3 + 1 + read-write + + + CMD_CS_0 + to Chip-select 0 + 0 + + + CMD_CS_1 + to Chip-select 1 + 0x1 + + + + + CMD + Command + 0x4 + 3 + read-write + + + CMD_0 + Normal operation + 0 + + + CMD_2 + Auto-Refresh Command (set correct CMD_CS). + 0x2 + + + CMD_3 + Load Mode Register Command DDR2/DDR3, set correct CMD_CS, CMD_BA, CMD_ADDR_LSB, CMD_ADDR_MSB), MRW Command (LPDDR2/LPDDR3, set correct CMD_CS, MR_OP, MR_ADDR) + 0x3 + + + CMD_4 + ZQ calibration (DDR2/DDR3, set correct CMD_CS, {CMD_ADDR_MSB,CMD_ADDR_LSB} = 0x400 or 0x0 ) + 0x4 + + + CMD_5 + Precharge all, only if banks open (set correct CMD_CS). + 0x5 + + + CMD_6 + MRR command (LPDDR2/LPDDR3, set correct CMD_CS, MR_ADDR) + 0x6 + + + + + WL_EN + DQS pads direction + 0x9 + 1 + read-write + + + WL_EN_0 + Exit write leveling mode or stay in normal mode. + 0 + + + WL_EN_1 + Write leveling entry command was sent. + 0x1 + + + + + MRR_READ_DATA_VALID + MRR read data valid + 0xA + 1 + read-only + + + MRR_READ_DATA_VALID_0 + Cleared upon the assertion of MRR command + 0 + + + MRR_READ_DATA_VALID_1 + Set after MRR data is valid and stored at MDMRR register. + 0x1 + + + + + CON_ACK + Configuration acknowledge + 0xE + 1 + read-only + + + CON_ACK_0 + Configuration of MMDC registers is forbidden. + 0 + + + CON_ACK_1 + Configuration of MMDC registers is permitted. + 0x1 + + + + + CON_REQ + Configuration request + 0xF + 1 + read-write + + + CON_REQ_0 + No request to configure MMDC. + 0 + + + CON_REQ_1 + A request to configure MMDC is valid + 0x1 + + + + + CMD_ADDR_LSB_MR_ADDR + Command/Address LSB + 0x10 + 8 + read-write + + + CMD_ADDR_MSB_MR_OP + Command/Address MSB + 0x18 + 8 + read-write + + + + + MDREF + MMDC Core Refresh Control Register + 0x20 + 32 + read-write + 0xC000 + 0xFFFFFFFF + + + START_REF + Manual start of refresh cycle + 0 + 1 + read-write + + + START_REF_0 + Do nothing. + 0 + + + START_REF_1 + Start a refresh cycle. + 0x1 + + + + + REFR + Refresh Rate + 0xB + 3 + read-write + + + REFR_0 + 1 refresh + 0 + + + REFR_1 + 2 refreshes + 0x1 + + + REFR_2 + 3 refreshes + 0x2 + + + REFR_3 + 4 refreshes + 0x3 + + + REFR_4 + 5 refreshes + 0x4 + + + REFR_5 + 6 refreshes + 0x5 + + + REFR_6 + 7 refreshes + 0x6 + + + REFR_7 + 8 refreshes + 0x7 + + + + + REF_SEL + Refresh Selector. This bit selects the source of the clock that will trigger each refresh cycle: + 0xE + 2 + read-write + + + REF_SEL_0 + Periodic refresh cycles will be triggered in frequency of 64KHz. + 0 + + + REF_SEL_1 + Periodic refresh cycles will be triggered in frequency of 32KHz. + 0x1 + + + REF_SEL_2 + Periodic refresh cycles will be triggered every amount of cycles that are configured in REF_CNT field. + 0x2 + + + REF_SEL_3 + No refresh cycles will be triggered. + 0x3 + + + + + REF_CNT + Refresh Counter at DDR clock period If REF_SEL equals '2' a refresh cycle will begin every amount of DDR cycles configured in this field + 0x10 + 16 + read-write + + + REF_CNT_1 + 1 cycle. + 0x1 + + + REF_CNT_65534 + 65534 cycles. + 0xFFFE + + + REF_CNT_65535 + 65535 cycles. + 0xFFFF + + + + + + + MDRWD + MMDC Core Read/Write Command Delay Register + 0x2C + 32 + read-write + 0xF9F26D2 + 0xFFFFFFFF + + + RTR_DIFF + Read to read delay for different chip-select + 0 + 3 + read-write + + + RTR_DIFF_0 + 0 cycle + 0 + + + RTR_DIFF_1 + 1 cycle + 0x1 + + + RTR_DIFF_2 + 2 cycles (Default) + 0x2 + + + RTR_DIFF_3 + 3 cycles + 0x3 + + + RTR_DIFF_4 + 4 cycles + 0x4 + + + RTR_DIFF_5 + 5 cycles + 0x5 + + + RTR_DIFF_6 + 6 cycles + 0x6 + + + RTR_DIFF_7 + 7 cycles + 0x7 + + + + + RTW_DIFF + Read to write delay for different chip-select + 0x3 + 3 + read-write + + + RTW_DIFF_0 + 0 cycle + 0 + + + RTW_DIFF_1 + 1 cycle + 0x1 + + + RTW_DIFF_2 + 2 cycles (Default) + 0x2 + + + RTW_DIFF_3 + 3 cycles + 0x3 + + + RTW_DIFF_4 + 4 cycles + 0x4 + + + RTW_DIFF_5 + 5 cycles + 0x5 + + + RTW_DIFF_6 + 6 cycles + 0x6 + + + RTW_DIFF_7 + 7 cycles + 0x7 + + + + + WTW_DIFF + Write to write delay for different chip-select + 0x6 + 3 + read-write + + + WTW_DIFF_0 + 0 cycle + 0 + + + WTW_DIFF_1 + 1 cycle + 0x1 + + + WTW_DIFF_2 + 2 cycles + 0x2 + + + WTW_DIFF_3 + 3 cycles (Default) + 0x3 + + + WTW_DIFF_4 + 4 cycles + 0x4 + + + WTW_DIFF_5 + 5 cycles + 0x5 + + + WTW_DIFF_6 + 6 cycles + 0x6 + + + WTW_DIFF_7 + 7 cycles + 0x7 + + + + + WTR_DIFF + Write to read delay for different chip-select + 0x9 + 3 + read-write + + + WTR_DIFF_0 + 0 cycle + 0 + + + WTR_DIFF_1 + 1 cycle + 0x1 + + + WTR_DIFF_2 + 2 cycles + 0x2 + + + WTR_DIFF_3 + 3 cycles (Default) + 0x3 + + + WTR_DIFF_4 + 4 cycles + 0x4 + + + WTR_DIFF_5 + 5 cycles + 0x5 + + + WTR_DIFF_6 + 6 cycles + 0x6 + + + WTR_DIFF_7 + 7 cycles + 0x7 + + + + + RTW_SAME + Read to write delay for the same chip-select + 0xC + 3 + read-write + + + RTW_SAME_0 + 0 cycle + 0 + + + RTW_SAME_1 + 1 cycle + 0x1 + + + RTW_SAME_2 + 2 cycles (Default) + 0x2 + + + RTW_SAME_3 + 3 cycles + 0x3 + + + RTW_SAME_4 + 4 cycles + 0x4 + + + RTW_SAME_5 + 5 cycles + 0x5 + + + RTW_SAME_6 + 6 cycles + 0x6 + + + RTW_SAME_7 + 7 cycles + 0x7 + + + + + tDAI + Device auto initialization period.(maximum) This field is relevant only to LPDDR2 mode + 0x10 + 13 + read-write + + + tDAI_0 + 1 cycle + 0 + + + tDAI_3999 + 4000 cycles (Default, JEDEC value for LPDDR2, gives 10us at 400MHz clock). + 0xF9F + + + tDAI_8191 + 8192 cycles + 0x1FFF + + + + + + + MDOR + MMDC Core Out of Reset Delays Register + 0x30 + 32 + read-write + 0x9F0E0E + 0xFFFFFFFF + + + RST_to_CKE + DDR3: Time from SDE enable to CKE rise + 0 + 6 + read-write + + + RST_to_CKE_3 + 1 cycles + 0x3 + + + RST_to_CKE_16 + 14 cycles (JEDEC value for LPDDR2) - total of 200 us + 0x10 + + + RST_to_CKE_35 + 33 cycles (JEDEC value for DDR3) - total of 500 us + 0x23 + + + RST_to_CKE_62 + 60 cycles + 0x3E + + + RST_to_CKE_63 + 61 cycles + 0x3F + + + + + SDE_to_RST + DDR3 mode: Time from SDE enable until DDR reset# is high + 0x8 + 6 + read-write + + + SDE_to_RST_3 + 1 cycles + 0x3 + + + SDE_to_RST_4 + 2 cycles + 0x4 + + + SDE_to_RST_16 + 14 cycles (JEDEC value for DDR3) - total of 200 us + 0x10 + + + SDE_to_RST_62 + 60 cycles + 0x3E + + + SDE_to_RST_63 + 61 cycles + 0x3F + + + + + tXPR + DDR2/DDR3: CKE HIGH to a valid command + 0x10 + 8 + read-write + + + tXPR_1 + 2 cycles + 0x1 + + + tXPR_2 + 3 cycles + 0x2 + + + tXPR_254 + 255 cycles + 0xFE + + + tXPR_255 + 256 cycles + 0xFF + + + + + + + MDMRR + MMDC Core MRR Data Register + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + MRR_READ_DATA0 + MRR DATA that arrived on DQ[7:0] + 0 + 8 + read-only + + + MRR_READ_DATA1 + MRR DATA that arrived on DQ[15:8] + 0x8 + 8 + read-only + + + + + MDCFG3LP + MMDC Core Timing Configuration Register 3 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + tRPab_LP + Precharge (all banks) command period. This field is valid only for LPDDR2 memories + 0 + 4 + read-write + + + tRPab_LP_0 + 1 clock + 0 + + + tRPab_LP_1 + 2 clocks + 0x1 + + + tRPab_LP_2 + 3 clocks + 0x2 + + + tRPab_LP_14 + 15 clocks + 0xE + + + + + tRPpb_LP + Precharge (per bank) command period (same bank). This field is valid only for LPDDR2 memories + 0x4 + 4 + read-write + + + tRPpb_LP_0 + 1 clock + 0 + + + tRPpb_LP_1 + 2 clocks + 0x1 + + + tRPpb_LP_2 + 3 clocks + 0x2 + + + tRPpb_LP_14 + 15 clocks + 0xE + + + + + tRCD_LP + Active command to internal read or write delay time (same bank) + 0x8 + 4 + read-write + + + tRCD_LP_0 + 1 clock + 0 + + + tRCD_LP_1 + 2 clocks + 0x1 + + + tRCD_LP_2 + 3 clocks + 0x2 + + + tRCD_LP_14 + 15 clocks + 0xE + + + + + RC_LP + Active to Active or Refresh command period (same bank) + 0x10 + 6 + read-write + + + RC_LP_0 + 1 clock + 0 + + + RC_LP_1 + 2 clocks + 0x1 + + + RC_LP_2 + 3 clocks + 0x2 + + + RC_LP_62 + 63 clocks + 0x3E + + + + + + + MDMR4 + MMDC Core MR4 Derating Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + UPDATE_DE_REQ + Update Derated Values Request + 0 + 1 + read-write + + + UPDATE_DE_REQ_0 + Do nothing. + 0 + + + UPDATE_DE_REQ_1 + Request to update the following values: tRRD, tRCD, tRP, tRC, tRAS and refresh related fields(MDREF register): REF_CNT, REF_SEL, REFR + 0x1 + + + + + UPDATE_DE_ACK + Update Derated Values Acknowledge + 0x1 + 1 + read-only + + + tRCD_DE + tRCD derating value. + 0x4 + 1 + read-write + + + tRCD_DE_0 + Original tRCD is used. + 0 + + + tRCD_DE_1 + tRCD is derated in 1 cycle. + 0x1 + + + + + tRC_DE + tRC derating value. + 0x5 + 1 + read-write + + + tRC_DE_0 + Original tRC is used. + 0 + + + tRC_DE_1 + tRC is derated in 1 cycle. + 0x1 + + + + + tRAS_DE + tRAS derating value. + 0x6 + 1 + read-write + + + tRAS_DE_0 + Original tRAS is used. + 0 + + + tRAS_DE_1 + tRAS is derated in 1 cycle. + 0x1 + + + + + tRP_DE + tRP derating value. + 0x7 + 1 + read-write + + + tRP_DE_0 + Original tRP is used. + 0 + + + tRP_DE_1 + tRP is derated in 1 cycle. + 0x1 + + + + + tRRD_DE + tRRD derating value. + 0x8 + 1 + read-write + + + tRRD_DE_0 + Original tRRD is used. + 0 + + + tRRD_DE_1 + tRRD is derated in 1 cycle. + 0x1 + + + + + + + MDASP + MMDC Core Address Space Partition Register + 0x40 + 32 + read-write + 0x3F + 0xFFFFFFFF + + + CS0_END + CS0_END + 0 + 7 + read-write + + + + + MAARCR + MMDC Core AXI Reordering Control Register + 0x400 + 32 + read-write + 0x514201F0 + 0xFFFFFFFF + + + ARCR_GUARD + ARCR Guard + 0 + 4 + read-write + + + ARCR_GUARD_0 + 15 (default) + 0 + + + ARCR_GUARD_1 + 16 + 0x1 + + + ARCR_GUARD_15 + 30 + 0xF + + + + + ARCR_DYN_MAX + ARCR Dynamic Maximum + 0x4 + 4 + read-write + + + ARCR_DYN_MAX_0 + 0 + 0 + + + ARCR_DYN_MAX_1 + 1 + 0x1 + + + ARCR_DYN_MAX_15 + 15 (default) + 0xF + + + + + ARCR_DYN_JMP + ARCR Dynamic Jump + 0x8 + 4 + read-write + + + ARCR_ACC_HIT + ARCR Access Hit Rate + 0x10 + 3 + read-write + + + ARCR_PAG_HIT + ARCR Page Hit Rate + 0x14 + 3 + read-write + + + ARCR_RCH_EN + This bit defines whether Real time channel is activated and bypassed all other pending accesses, So accesses with QoS=='F' will be granted the highest priority in the optimization/reordering mechanism Default value is 0x1 - encoding 1 (Enabled) + 0x18 + 1 + read-write + + + ARCR_RCH_EN_0 + normal prioritization, no bypassing + 0 + + + ARCR_RCH_EN_1 + accesses with QoS=='F' bypass the arbitration + 0x1 + + + + + ARCR_REO_DIS + no description available + 0x19 + 1 + read-write + + + ARCR_REO_DIS_0 + MMDC reordering controls only enabled + 0 + + + ARCR_REO_DIS_1 + MMDC reordering controls only disabled + 0x1 + + + + + ARCR_ARB_REO_DIS + no description available + 0x1A + 1 + read-write + + + ARCR_ARB_REO_DIS_0 + MMDC arbitration and reordering controls enabled + 0 + + + ARCR_ARB_REO_DIS_1 + MMDC arbitration and reordering controls disabled + 0x1 + + + + + ARCR_EXC_ERR_EN + This bit defines whether exclusive read/write access violation of AXI 6 + 0x1C + 1 + read-write + + + ARCR_EXC_ERR_EN_0 + violation of AXI exclusive rules (6.2.4) result in OKAY response (rresp/bresp=2'b00) + 0 + + + ARCR_EXC_ERR_EN_1 + violation of AXI exclusive rules (6.2.4) result in SLAVE Error response (rresp/bresp=2'b10) + 0x1 + + + + + ARCR_SEC_ERR_EN + This bit defines whether security read/write access violation result in SLV Error response or in OKAY response Default value is 0x1 - encoding 1(response is SLV Error, rresp/bresp=2'b10) + 0x1E + 1 + read-write + + + ARCR_SEC_ERR_EN_0 + security violation results in OKAY response (rresp/bresp=2'b00) + 0 + + + ARCR_SEC_ERR_EN_1 + security violation results in SLAVE Error response (rresp/bresp=2'b10) + 0x1 + + + + + ARCR_SEC_ERR_LOCK + Once set, this bit locks ARCR_SEC_ERR_EN and prevents from its updating + 0x1F + 1 + read-write + + + ARCR_SEC_ERR_LOCK_0 + ARCR_SEC_ERR_EN is unlocked, so can be updated any moment + 0 + + + ARCR_SEC_ERR_LOCK_1 + ARCR_SEC_ERR_EN is locked, so it can't be updated + 0x1 + + + + + + + MAPSR + MMDC Core Power Saving Control and Status Register + 0x404 + 32 + read-write + 0x1007 + 0xFFFFFFFF + + + PSD + Automatic Power Saving Disable + 0 + 1 + read-write + + + PSD_0 + power saving enabled + 0 + + + PSD_1 + power saving disabled (default) + 0x1 + + + + + PSS + Power Saving Status + 0x4 + 1 + read-only + + + PSS_0 + not in power saving + 0 + + + PSS_1 + power saving + 0x1 + + + + + RIS + Read Idle Status. This read only bit indicates whether read request buffer is idle (empty) or not. + 0x5 + 1 + read-only + + + RIS_0 + idle + 0 + + + RIS_1 + not idle + 0x1 + + + + + WIS + Write Idle Status + 0x6 + 1 + read-only + + + WIS_0 + idle + 0 + + + WIS_1 + not idle + 0x1 + + + + + PST + Automatic Power saving timer + 0x8 + 8 + read-write + + + PST_1 + timer is configured to 64 clock cycles. + 0x1 + + + PST_2 + timer is configured to 128 clock cycles. + 0x2 + + + PST_16 + (Default)- 1024 clock cycles. + 0x10 + + + PST_255 + timer clock is configured to 16320 clock cycles. + 0xFF + + + + + LPMD + General LPMD request + 0x14 + 1 + read-write + + + LPMD_0 + no lpmd request + 0 + + + LPMD_1 + lpmd request + 0x1 + + + + + DVFS + General DVFS request + 0x15 + 1 + read-write + + + DVFS_0 + no dvfs request + 0 + + + DVFS_1 + dvfs request + 0x1 + + + + + LPACK + General low-power acknowledge + 0x18 + 1 + read-only + + + DVACK + General DVFS acknowledge + 0x19 + 1 + read-only + + + + + MAEXIDR0 + MMDC Core Exclusive ID Monitor Register0 + 0x408 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + EXC_ID_MONITOR0 + This field defines ID for Exclusive monitor#0. Default value is 0x0000 + 0 + 16 + read-write + + + EXC_ID_MONITOR1 + This field defines ID for Exclusive monitor#1. Default value is 0x0020 + 0x10 + 16 + read-write + + + + + MAEXIDR1 + MMDC Core Exclusive ID Monitor Register1 + 0x40C + 32 + read-write + 0x600040 + 0xFFFFFFFF + + + EXC_ID_MONITOR2 + This field defines ID for Exclusive monitor#2. Default value is 0x0040 + 0 + 16 + read-write + + + EXC_ID_MONITOR3 + This field defines ID for Exclusive monitor#3. Default value is 0x0060 + 0x10 + 16 + read-write + + + + + MADPCR0 + MMDC Core Debug and Profiling Control Register 0 + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + DBG_EN + Debug and Profiling Enable + 0 + 1 + read-write + + + DBG_EN_0 + disable + 0 + + + DBG_EN_1 + enable + 0x1 + + + + + DBG_RST + Debug and Profiling Reset. Reset all debug and profiling counters and components. + 0x1 + 1 + read-write + + + DBG_RST_0 + no reset + 0 + + + DBG_RST_1 + reset + 0x1 + + + + + PRF_FRZ + Profiling freeze + 0x2 + 1 + read-write + + + PRF_FRZ_0 + profiling counters are not frozen + 0 + + + PRF_FRZ_1 + profiling counters are frozen + 0x1 + + + + + CYC_OVF + Total Profiling Cycles Count Overflow + 0x3 + 1 + read-write + oneToClear + + + CYC_OVF_0 + no overflow + 0 + + + CYC_OVF_1 + overflow + 0x1 + + + + + SBS_EN + Step By Step debug Enable + 0x8 + 1 + read-write + + + SBS_EN_0 + disable + 0 + + + SBS_EN_1 + enable + 0x1 + + + + + SBS + Step By Step trigger + 0x9 + 1 + read-write + + + SBS_0 + No access will be launched toward the DDR + 0 + + + SBS_1 + Launch AXI pending access toward the DDR + 0x1 + + + + + + + MADPCR1 + MMDC Core Debug and Profiling Control Register 1 + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRF_AXI_ID + Profiling AXI ID + 0 + 16 + read-write + + + PRF_AXI_IDMASK + Profiling AXI ID Mask. AXI ID bits which masked by this value are chosen for profiling. + 0x10 + 16 + read-write + + + PRF_AXI_IDMASK_0 + AXI ID specific bit is ignored (don't care) + 0 + + + PRF_AXI_IDMASK_1 + AXI ID specific bit is chosen for profiling + 0x1 + + + + + + + MADPSR0 + MMDC Core Debug and Profiling Status Register 0 + 0x418 + 32 + read-only + 0 + 0xFFFFFFFF + + + CYC_COUNT + Total Profiling cycle Count + 0 + 32 + read-only + + + + + MADPSR1 + MMDC Core Debug and Profiling Status Register 1 + 0x41C + 32 + read-only + 0 + 0xFFFFFFFF + + + BUSY_COUNT + Profiling Busy Cycles Count + 0 + 32 + read-only + + + + + MADPSR2 + MMDC Core Debug and Profiling Status Register 2 + 0x420 + 32 + read-only + 0 + 0xFFFFFFFF + + + RD_ACC_COUNT + Profiling Read Access Count + 0 + 32 + read-only + + + + + MADPSR3 + MMDC Core Debug and Profiling Status Register 3 + 0x424 + 32 + read-only + 0 + 0xFFFFFFFF + + + WR_ACC_COUNT + Profiling Write Access Count + 0 + 32 + read-only + + + + + MADPSR4 + MMDC Core Debug and Profiling Status Register 4 + 0x428 + 32 + read-only + 0 + 0xFFFFFFFF + + + RD_BYTES_COUNT + Profiling Read Bytes Count + 0 + 32 + read-only + + + + + MADPSR5 + MMDC Core Debug and Profiling Status Register 5 + 0x42C + 32 + read-only + 0 + 0xFFFFFFFF + + + WR_BYTES_COUNT + Profiling Write Bytes Count + 0 + 32 + read-only + + + + + MASBS0 + MMDC Core Step By Step Address Register + 0x430 + 32 + read-only + 0 + 0xFFFFFFFF + + + SBS_ADDR + Step By Step Address + 0 + 32 + read-only + + + + + MASBS1 + MMDC Core Step By Step Address Attributes Register + 0x434 + 32 + read-only + 0 + 0xFFFFFFFF + + + SBS_VLD + Step By Step Valid + 0 + 1 + read-only + + + SBS_VLD_0 + not valid + 0 + + + SBS_VLD_1 + valid + 0x1 + + + + + SBS_TYPE + Step By Step Request Type + 0x1 + 1 + read-only + + + SBS_TYPE_0 + write + 0 + + + SBS_TYPE_1 + read + 0x1 + + + + + SBS_LOCK + Step By Step Lock + 0x2 + 2 + read-only + + + SBS_PROT + Step By Step Protection + 0x4 + 3 + read-only + + + SBS_SIZE + Step By Step Size + 0x7 + 3 + read-only + + + SBS_SIZE_0 + 8 bits + 0 + + + SBS_SIZE_1 + 16 bits + 0x1 + + + SBS_SIZE_2 + 32 bits + 0x2 + + + SBS_SIZE_3 + 64 bits + 0x3 + + + SBS_SIZE_4 + 128bits + 0x4 + + + + + SBS_BURST + Step By Step Burst + 0xA + 2 + read-only + + + SBS_BURST_0 + FIXED + 0 + + + SBS_BURST_1 + INCR burst + 0x1 + + + SBS_BURST_2 + WRAP burst + 0x2 + + + + + SBS_BUFF + Step By Step Buffered + 0xC + 1 + read-only + + + SBS_LEN + Step By Step Length + 0xD + 3 + read-only + + + SBS_LEN_0 + burst of length 1 + 0 + + + SBS_LEN_1 + burst of length 2 + 0x1 + + + SBS_LEN_7 + burst of length 8 + 0x7 + + + + + SBS_AXI_ID + Step By Step AXI ID + 0x10 + 16 + read-only + + + + + MAGENP + MMDC Core General Purpose Register + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + GP31_GP0 + General purpose read/write bits. + 0 + 32 + read-write + + + + + MPZQHWCTRL + MMDC PHY ZQ HW control register + 0x800 + 32 + read-write + 0xA1380000 + 0xFFFFFFFF + + + ZQ_MODE + ZQ calibration mode: + 0 + 2 + read-write + + + ZQ_MODE_0 + No ZQ calibration is issued. (Default) + 0 + + + ZQ_MODE_1 + ZQ calibration is issued to i.MX ZQ calibration pad together with ZQ long command to the external DDR device only when exiting self refresh. + 0x1 + + + ZQ_MODE_2 + ZQ calibration command long/short is issued only to the external DDR device periodically and when exiting self refresh + 0x2 + + + ZQ_MODE_3 + ZQ calibration is issued to i.MX ZQ calibration pad together with ZQ calibration command long/short to the external DDR device periodically and when exiting self refresh + 0x3 + + + + + ZQ_HW_PER + ZQ periodic calibration time + 0x2 + 4 + read-write + + + ZQ_HW_PER_0 + ZQ calibration is performed every 1 ms. + 0 + + + ZQ_HW_PER_1 + ZQ calibration is performed every 2 ms. + 0x1 + + + ZQ_HW_PER_2 + ZQ calibration is performed every 4 ms. + 0x2 + + + ZQ_HW_PER_10 + ZQ calibration is performed every 1 sec. + 0xA + + + ZQ_HW_PER_14 + ZQ calibration is performed every 16 sec. + 0xE + + + ZQ_HW_PER_15 + ZQ calibration is performed every 32 sec. + 0xF + + + + + ZQ_HW_PU_RES + ZQ automatic calibration pull-up result + 0x6 + 5 + read-only + + + ZQ_HW_PU_RES_0 + Min. resistance. + 0 + + + ZQ_HW_PU_RES_31 + Max. resistance. + 0x1F + + + + + ZQ_HW_PD_RES + ZQ HW calibration pull-down result + 0xB + 5 + read-only + + + ZQ_HW_PD_RES_0 + Max. resistance. + 0 + + + ZQ_HW_PD_RES_31 + Min. resistance. + 0x1F + + + + + ZQ_HW_FOR + Force ZQ automatic calibration process with the i + 0x10 + 1 + read-write + + + TZQ_INIT + Device ZQ long/init time + 0x11 + 3 + read-write + + + TZQ_INIT_2 + 128 cycles + 0x2 + + + TZQ_INIT_3 + 256 cycles + 0x3 + + + TZQ_INIT_4 + 512 cycles - Default (JEDEC value for DDR3) + 0x4 + + + TZQ_INIT_5 + 1024 cycles + 0x5 + + + + + TZQ_OPER + Device ZQ long/oper time + 0x14 + 3 + read-write + + + TZQ_OPER_2 + 128 cycles + 0x2 + + + TZQ_OPER_3 + 256 cycles - Default (JEDEC value for DDR3) + 0x3 + + + TZQ_OPER_4 + 512 cycles + 0x4 + + + TZQ_OPER_5 + 1024 cycles + 0x5 + + + + + TZQ_CS + Device ZQ short time + 0x17 + 3 + read-write + + + TZQ_CS_2 + 128 cycles (Default) + 0x2 + + + TZQ_CS_3 + 256 cycles + 0x3 + + + TZQ_CS_4 + 512 cycles + 0x4 + + + TZQ_CS_5 + 1024 cycles + 0x5 + + + + + ZQ_EARLY_COMPARATOR_EN_TIMER + ZQ early comparator enable timer + 0x1B + 5 + read-write + + + ZQ_EARLY_COMPARATOR_EN_TIMER_0 + - 0x6 Reserved + 0 + + + ZQ_EARLY_COMPARATOR_EN_TIMER_7 + 8 cycles + 0x7 + + + ZQ_EARLY_COMPARATOR_EN_TIMER_20 + 21 cycles (Default) + 0x14 + + + ZQ_EARLY_COMPARATOR_EN_TIMER_30 + 31 cycles + 0x1E + + + ZQ_EARLY_COMPARATOR_EN_TIMER_31 + 32 cycles + 0x1F + + + + + + + MPZQSWCTRL + MMDC PHY ZQ SW control register + 0x804 + 32 + read-write + 0 + 0xFFFFFFFF + + + ZQ_SW_FOR + ZQ SW calibration enable + 0 + 1 + read-write + + + ZQ_SW_RES + ZQ software calibration result. This bit reflects the ZQ calibration voltage comparator value. + 0x1 + 1 + read-only + + + ZQ_SW_RES_0 + Current ZQ calibration voltage is less than VDD/2. + 0 + + + ZQ_SW_RES_1 + Current ZQ calibration voltage is more than VDD/2 + 0x1 + + + + + ZQ_SW_PU_VAL + ZQ software pull-up resistence + 0x2 + 5 + read-write + + + ZQ_SW_PU_VAL_0 + Min. resistance. + 0 + + + ZQ_SW_PU_VAL_31 + Max. resistance. + 0x1F + + + + + ZQ_SW_PD_VAL + ZQ software pull-down resistence + 0x7 + 5 + read-write + + + ZQ_SW_PD_VAL_0 + Max. resistance. + 0 + + + ZQ_SW_PD_VAL_31 + Min. resistance. + 0x1F + + + + + ZQ_SW_PD + ZQ software PU/PD calibration. This bit determines the calibration stage (PU or PD). + 0xC + 1 + read-write + + + ZQ_SW_PD_0 + PU resistor calibration + 0 + + + ZQ_SW_PD_1 + PD resistor calibration + 0x1 + + + + + USE_ZQ_SW_VAL + Use SW ZQ configured value for I/O pads resistor controls + 0xD + 1 + read-write + + + USE_ZQ_SW_VAL_0 + Fields ZQ_HW_PD_VAL & ZQ_HW_PU_VAL will be driven to I/O pads resistor controls. + 0 + + + USE_ZQ_SW_VAL_1 + Fields ZQ_SW_PD_VAL & ZQ_SW_PU_VAL will be driven to I/O pads resistor controls. + 0x1 + + + + + ZQ_CMP_OUT_SMP + Defines the amount of cycles between driving the ZQ signals to the ZQ pad and till sampling the comparator enable output while performing ZQ calibration process with the i + 0x10 + 2 + read-write + + + ZQ_CMP_OUT_SMP_0 + 7 cycles + 0 + + + ZQ_CMP_OUT_SMP_1 + 15 cycles + 0x1 + + + ZQ_CMP_OUT_SMP_2 + 23 cycles + 0x2 + + + ZQ_CMP_OUT_SMP_3 + 31 cycles + 0x3 + + + + + + + MPWLGCR + MMDC PHY Write Leveling Configuration and Error Status Register + 0x808 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_WL_EN + Write-Leveling HW (automatic) enable + 0 + 1 + read-write + + + SW_WL_EN + Write-Leveling SW enable + 0x1 + 1 + read-write + + + SW_WL_CNT_EN + SW write-leveling count down enable + 0x2 + 1 + read-write + + + SW_WL_CNT_EN_0 + MMDC doesn't count 25+15 cycles before issuing write-leveling DQS. + 0 + + + SW_WL_CNT_EN_1 + MMDC counts 25+15 cycles before issuing write-leveling DQS. + 0x1 + + + + + WL_SW_RES0 + Byte0 write-leveling software result + 0x4 + 1 + read-only + + + WL_SW_RES0_0 + DQS0 sampled low CK during SW write-leveling. + 0 + + + WL_SW_RES0_1 + DQS0 sampled high CK during SW write-leveling. + 0x1 + + + + + WL_SW_RES1 + Byte1 write-leveling software result + 0x5 + 1 + read-only + + + WL_SW_RES1_0 + DQS1 sampled low CK during SW write-leveling. + 0 + + + WL_SW_RES1_1 + DQS1 sampled high CK during SW write-leveling. + 0x1 + + + + + WL_HW_ERR0 + Byte0 write-leveling HW calibration error + 0x8 + 1 + read-only + + + WL_HW_ERR0_0 + No error was found on byte0 during write-leveling HW calibration. + 0 + + + WL_HW_ERR0_1 + An error was found on byte0 during write-leveling HW calibration. + 0x1 + + + + + WL_HW_ERR1 + Byte1 write-leveling HW calibration error + 0x9 + 1 + read-only + + + WL_HW_ERR1_0 + No error was found on byte1 during write-leveling HW calibration. + 0 + + + WL_HW_ERR1_1 + An error was found on byte1 during write-leveling HW calibration. + 0x1 + + + + + + + MPWLDECTRL0 + MMDC PHY Write Leveling Delay Control Register 0 + 0x80C + 32 + read-write + 0 + 0xFFFFFFFF + + + WL_DL_ABS_OFFSET0 + Absolute write-leveling delay offset for Byte 0 + 0 + 7 + read-write + + + WL_HC_DEL0 + Write leveling half cycle delay for Byte 0 + 0x8 + 1 + read-write + + + WL_HC_DEL0_0 + No delay is added. + 0 + + + WL_HC_DEL0_1 + Half cycle delay is added. + 0x1 + + + + + WL_CYC_DEL0 + Write leveling cycle delay for Byte 0 + 0x9 + 2 + read-write + + + WL_CYC_DEL0_0 + No delay is added. + 0 + + + WL_CYC_DEL0_1 + 1 cycle delay is added. + 0x1 + + + WL_CYC_DEL0_2 + 2 cycles delay is added. + 0x2 + + + + + WL_DL_ABS_OFFSET1 + Absolute write-leveling delay offset for Byte 1 + 0x10 + 7 + read-write + + + WL_HC_DEL1 + Write leveling half cycle delay for Byte 1 + 0x18 + 1 + read-write + + + WL_HC_DEL1_0 + No delay is added. + 0 + + + WL_HC_DEL1_1 + Half cycle delay is added. + 0x1 + + + + + WL_CYC_DEL1 + Write leveling cycle delay for Byte 1 + 0x19 + 2 + read-write + + + WL_CYC_DEL1_0 + No delay is added. + 0 + + + WL_CYC_DEL1_1 + 1 cycle delay is added. + 0x1 + + + WL_CYC_DEL1_2 + 2 cycles delay is added. + 0x2 + + + + + + + MPWLDLST + MMDC PHY Write Leveling delay-line Status Register + 0x814 + 32 + read-only + 0 + 0xFFFFFFFF + + + WL_DL_UNIT_NUM0 + This field reflects the number of delay units that are actually used by write leveling delay-line 0 + 0 + 7 + read-only + + + WL_DL_UNIT_NUM1 + This field reflects the number of delay units that are actually used by write leveling delay-line 1 + 0x8 + 7 + read-only + + + + + MPODTCTRL + MMDC PHY ODT control register + 0x818 + 32 + read-write + 0 + 0xFFFFFFFF + + + ODT_WR_PAS_EN + Inactive write CS ODT enable + 0 + 1 + read-write + + + ODT_WR_PAS_EN_0 + Inactive CS ODT pin is disabled during write accesses to other CS. + 0 + + + ODT_WR_PAS_EN_1 + Inactive CS ODT pin is enabled during write accesses to other CS. + 0x1 + + + + + ODT_WR_ACT_EN + Active write CS ODT enable + 0x1 + 1 + read-write + + + ODT_WR_ACT_EN_0 + Active CS ODT pin is disabled during write access. + 0 + + + ODT_WR_ACT_EN_1 + Active CS ODT pin is enabled during write access. + 0x1 + + + + + ODT_RD_PAS_EN + Inactive read CS ODT enable + 0x2 + 1 + read-write + + + ODT_RD_PAS_EN_0 + Inactive CS ODT pin is disabled during read accesses to other CS. + 0 + + + ODT_RD_PAS_EN_1 + Inactive CS ODT pin is enabled during read accesses to other CS. + 0x1 + + + + + ODT_RD_ACT_EN + Active read CS ODT enable + 0x3 + 1 + read-write + + + ODT_RD_ACT_EN_0 + Active CS ODT pin is disabled during read access. + 0 + + + ODT_RD_ACT_EN_1 + Active CS ODT pin is enabled during read access. + 0x1 + + + + + ODT0_INT_RES + On chip ODT byte0 resistor - This field determines the Rtt_Nom of the on chip ODT byte0 resistor during read accesses + 0x4 + 3 + read-write + + + ODT0_INT_RES_0 + Rtt_Nom Disabled. + 0 + + + ODT0_INT_RES_1 + Rtt_Nom 120 Ohm + 0x1 + + + ODT0_INT_RES_2 + Rtt_Nom 60 Ohm + 0x2 + + + ODT0_INT_RES_3 + Rtt_Nom 40 Ohm + 0x3 + + + ODT0_INT_RES_4 + Rtt_Nom 30 Ohm + 0x4 + + + ODT0_INT_RES_5 + Rtt_Nom 24 Ohm + 0x5 + + + ODT0_INT_RES_6 + Rtt_Nom 20 Ohm + 0x6 + + + ODT0_INT_RES_7 + Rtt_Nom 17 Ohm + 0x7 + + + + + ODT1_INT_RES + On chip ODT byte1 resistor - This field determines the Rtt_Nom of the on chip ODT byte1 resistor during read accesses + 0x8 + 3 + read-write + + + ODT1_INT_RES_0 + Rtt_Nom Disabled. + 0 + + + ODT1_INT_RES_1 + Rtt_Nom 120 Ohm + 0x1 + + + ODT1_INT_RES_2 + Rtt_Nom 60 Ohm + 0x2 + + + ODT1_INT_RES_3 + Rtt_Nom 40 Ohm + 0x3 + + + ODT1_INT_RES_4 + Rtt_Nom 30 Ohm + 0x4 + + + ODT1_INT_RES_5 + Rtt_Nom 24 Ohm + 0x5 + + + ODT1_INT_RES_6 + Rtt_Nom 20 Ohm + 0x6 + + + ODT1_INT_RES_7 + Rtt_Nom 17 Ohm + 0x7 + + + + + + + MPRDDQBY0DL + MMDC PHY Read DQ Byte0 Delay Register + 0x81C + 32 + read-write + 0 + 0xFFFFFFFF + + + rd_dq0_del + Read dqs0 to dq0 delay fine-tuning + 0 + 3 + read-write + + + rd_dq0_del_0 + No change in dq0 delay + 0 + + + rd_dq0_del_1 + Add dq0 delay of 1 delay unit + 0x1 + + + rd_dq0_del_2 + Add dq0 delay of 2 delay units. + 0x2 + + + rd_dq0_del_3 + Add dq0 delay of 3 delay units. + 0x3 + + + rd_dq0_del_4 + Add dq0 delay of 4 delay units. + 0x4 + + + rd_dq0_del_5 + Add dq0 delay of 5 delay units. + 0x5 + + + rd_dq0_del_6 + Add dq0 delay of 6 delay units. + 0x6 + + + rd_dq0_del_7 + Add dq0 delay of 7 delay units. + 0x7 + + + + + rd_dq1_del + Read dqs0 to dq1 delay fine-tuning + 0x4 + 3 + read-write + + + rd_dq1_del_0 + No change in dq1 delay + 0 + + + rd_dq1_del_1 + Add dq1 delay of 1 delay unit + 0x1 + + + rd_dq1_del_2 + Add dq1 delay of 2 delay units. + 0x2 + + + rd_dq1_del_3 + Add dq1 delay of 3 delay units. + 0x3 + + + rd_dq1_del_4 + Add dq1 delay of 4 delay units. + 0x4 + + + rd_dq1_del_5 + Add dq1 delay of 5 delay units. + 0x5 + + + rd_dq1_del_6 + Add dq1 delay of 6 delay units. + 0x6 + + + rd_dq1_del_7 + Add dq1 delay of 7 delay units. + 0x7 + + + + + rd_dq2_del + Read dqs0 to dq2 delay fine-tuning + 0x8 + 3 + read-write + + + rd_dq2_del_0 + No change in dq2 delay + 0 + + + rd_dq2_del_1 + Add dq2 delay of 1 delay unit + 0x1 + + + rd_dq2_del_2 + Add dq2 delay of 2 delay units. + 0x2 + + + rd_dq2_del_3 + Add dq2 delay of 3 delay units. + 0x3 + + + rd_dq2_del_4 + Add dq2 delay of 4 delay units. + 0x4 + + + rd_dq2_del_5 + Add dq2 delay of 5 delay units. + 0x5 + + + rd_dq2_del_6 + Add dq2 delay of 6 delay units. + 0x6 + + + rd_dq2_del_7 + Add dq2 delay of 7 delay units. + 0x7 + + + + + rd_dq3_del + Read dqs0 to dq3 delay fine-tuning + 0xC + 3 + read-write + + + rd_dq3_del_0 + No change in dq3 delay + 0 + + + rd_dq3_del_1 + Add dq3 delay of 1 delay unit + 0x1 + + + rd_dq3_del_2 + Add dq3 delay of 2 delay units. + 0x2 + + + rd_dq3_del_3 + Add dq3 delay of 3 delay units. + 0x3 + + + rd_dq3_del_4 + Add dq3 delay of 4 delay units. + 0x4 + + + rd_dq3_del_5 + Add dq3 delay of 5 delay units. + 0x5 + + + rd_dq3_del_6 + Add dq3 delay of 6 delay units. + 0x6 + + + rd_dq3_del_7 + Add dq3 delay of 7 delay units. + 0x7 + + + + + rd_dq4_del + Read dqs0 to dq4 delay fine-tuning + 0x10 + 3 + read-write + + + rd_dq4_del_0 + No change in dq4 delay + 0 + + + rd_dq4_del_1 + Add dq4 delay of 1 delay unit + 0x1 + + + rd_dq4_del_2 + Add dq4 delay of 2 delay units. + 0x2 + + + rd_dq4_del_3 + Add dq4 delay of 3 delay units. + 0x3 + + + rd_dq4_del_4 + Add dq4 delay of 4 delay units. + 0x4 + + + rd_dq4_del_5 + Add dq4 delay of 5 delay units. + 0x5 + + + rd_dq4_del_6 + Add dq4 delay of 6 delay units. + 0x6 + + + rd_dq4_del_7 + Add dq4 delay of 7 delay units. + 0x7 + + + + + rd_dq5_del + Read dqs0 to dq5 delay fine-tuning + 0x14 + 3 + read-write + + + rd_dq5_del_0 + No change in dq5 delay + 0 + + + rd_dq5_del_1 + Add dq5 delay of 1 delay unit + 0x1 + + + rd_dq5_del_2 + Add dq5 delay of 2 delay units. + 0x2 + + + rd_dq5_del_3 + Add dq5 delay of 3 delay units. + 0x3 + + + rd_dq5_del_4 + Add dq5 delay of 4 delay units. + 0x4 + + + rd_dq5_del_5 + Add dq5 delay of 5 delay units. + 0x5 + + + rd_dq5_del_6 + Add dq5 delay of 6 delay units. + 0x6 + + + rd_dq5_del_7 + Add dq5 delay of 7 delay units. + 0x7 + + + + + rd_dq6_del + Read dqs0 to dq6 delay fine-tuning + 0x18 + 3 + read-write + + + rd_dq6_del_0 + No change in dq6 delay + 0 + + + rd_dq6_del_1 + Add dq6 delay of 1 delay unit + 0x1 + + + rd_dq6_del_2 + Add dq6 delay of 2 delay units. + 0x2 + + + rd_dq6_del_3 + Add dq6 delay of 3 delay units. + 0x3 + + + rd_dq6_del_4 + Add dq6 delay of 4 delay units. + 0x4 + + + rd_dq6_del_5 + Add dq6 delay of 5 delay units. + 0x5 + + + rd_dq6_del_6 + Add dq6 delay of 6 delay units. + 0x6 + + + rd_dq6_del_7 + Add dq6 delay of 7 delay units. + 0x7 + + + + + rd_dq7_del + Read dqs0 to dq7 delay fine-tuning + 0x1C + 3 + read-write + + + rd_dq7_del_0 + No change in dq7 delay + 0 + + + rd_dq7_del_1 + Add dq7 delay of 1 delay unit + 0x1 + + + rd_dq7_del_2 + Add dq7 delay of 2 delay units. + 0x2 + + + rd_dq7_del_3 + Add dq7 delay of 3 delay units. + 0x3 + + + rd_dq7_del_4 + Add dq7 delay of 4 delay units. + 0x4 + + + rd_dq7_del_5 + Add dq7 delay of 5 delay units. + 0x5 + + + rd_dq7_del_6 + Add dq7 delay of 6 delay units. + 0x6 + + + rd_dq7_del_7 + Add dq7 delay of 7 delay units. + 0x7 + + + + + + + MPRDDQBY1DL + MMDC PHY Read DQ Byte1 Delay Register + 0x820 + 32 + read-write + 0 + 0xFFFFFFFF + + + rd_dq8_del + Read dqs1 to dq8 delay fine-tuning + 0 + 3 + read-write + + + rd_dq8_del_0 + No change in dq8 delay + 0 + + + rd_dq8_del_1 + Add dq8 delay of 1 delay unit + 0x1 + + + rd_dq8_del_2 + Add dq8 delay of 2 delay units. + 0x2 + + + rd_dq8_del_3 + Add dq8 delay of 3 delay units. + 0x3 + + + rd_dq8_del_4 + Add dq8 delay of 4 delay units. + 0x4 + + + rd_dq8_del_5 + Add dq8 delay of 5 delay units. + 0x5 + + + rd_dq8_del_6 + Add dq8 delay of 6 delay units. + 0x6 + + + rd_dq8_del_7 + Add dq8 delay of 7 delay units. + 0x7 + + + + + rd_dq9_del + Read dqs1 to dq9 delay fine-tuning + 0x4 + 3 + read-write + + + rd_dq9_del_0 + No change in dq9 delay + 0 + + + rd_dq9_del_1 + Add dq9 delay of 1 delay unit + 0x1 + + + rd_dq9_del_2 + Add dq9 delay of 2 delay units. + 0x2 + + + rd_dq9_del_3 + Add dq9 delay of 3 delay units. + 0x3 + + + rd_dq9_del_4 + Add dq9 delay of 4 delay units. + 0x4 + + + rd_dq9_del_5 + Add dq9 delay of 5 delay units. + 0x5 + + + rd_dq9_del_6 + Add dq9 delay of 6 delay units. + 0x6 + + + rd_dq9_del_7 + Add dq9 delay of 7 delay units. + 0x7 + + + + + rd_dq10_del + Read dqs1 to dq10 delay fine-tuning + 0x8 + 3 + read-write + + + rd_dq10_del_0 + No change in dq10 delay + 0 + + + rd_dq10_del_1 + Add dq10 delay of 1 delay unit + 0x1 + + + rd_dq10_del_2 + Add dq10 delay of 2 delay units. + 0x2 + + + rd_dq10_del_3 + Add dq10 delay of 3 delay units. + 0x3 + + + rd_dq10_del_4 + Add dq10 delay of 4 delay units. + 0x4 + + + rd_dq10_del_5 + Add dq10 delay of 5 delay unit + 0x5 + + + rd_dq10_del_6 + Add dq10 delay of 6 delay units. + 0x6 + + + rd_dq10_del_7 + Add dq10 delay of 7 delay units. + 0x7 + + + + + rd_dq11_del + Read dqs1 to dq11 delay fine-tuning + 0xC + 3 + read-write + + + rd_dq11_del_0 + No change in dq11 delay + 0 + + + rd_dq11_del_1 + Add dq11 delay of 1 delay unit + 0x1 + + + rd_dq11_del_2 + Add dq11 delay of 2 delay units. + 0x2 + + + rd_dq11_del_3 + Add dq11 delay of 3 delay units. + 0x3 + + + rd_dq11_del_4 + Add dq11 delay of 4 delay units. + 0x4 + + + rd_dq11_del_5 + Add dq11 delay of 5 delay units. + 0x5 + + + rd_dq11_del_6 + Add dq11 delay of 6 delay units. + 0x6 + + + rd_dq11_del_7 + Add dq11 delay of 7 delay units. + 0x7 + + + + + rd_dq12_del + Read dqs1 to dq12 delay fine-tuning + 0x10 + 3 + read-write + + + rd_dq12_del_0 + No change in dq12 delay + 0 + + + rd_dq12_del_1 + Add dq12 delay of 1 delay unit + 0x1 + + + rd_dq12_del_2 + Add dq12 delay of 2 delay units. + 0x2 + + + rd_dq12_del_3 + Add dq12 delay of 3 delay units. + 0x3 + + + rd_dq12_del_4 + Add dq12 delay of 4 delay units. + 0x4 + + + rd_dq12_del_5 + Add dq12 delay of 5 delay units. + 0x5 + + + rd_dq12_del_6 + Add dq12 delay of 6 delay units. + 0x6 + + + rd_dq12_del_7 + Add dq12 delay of 7 delay units. + 0x7 + + + + + rd_dq13_del + Read dqs1 to dq13 delay fine-tuning + 0x14 + 3 + read-write + + + rd_dq13_del_0 + No change in dq13 delay + 0 + + + rd_dq13_del_1 + Add dq13 delay of 1 delay unit + 0x1 + + + rd_dq13_del_2 + Add dq13 delay of 2 delay units. + 0x2 + + + rd_dq13_del_3 + Add dq13 delay of 3 delay units. + 0x3 + + + rd_dq13_del_4 + Add dq13 delay of 4 delay units. + 0x4 + + + rd_dq13_del_5 + Add dq13 delay of 5 delay units. + 0x5 + + + rd_dq13_del_6 + Add dq13 delay of 6 delay units. + 0x6 + + + rd_dq13_del_7 + Add dq13 delay of 7 delay units. + 0x7 + + + + + rd_dq14_del + Read dqs1 to dq14 delay fine-tuning + 0x18 + 3 + read-write + + + rd_dq14_del_0 + No change in dq14 delay + 0 + + + rd_dq14_del_1 + Add dq14 delay of 1 delay unit + 0x1 + + + rd_dq14_del_2 + Add dq14 delay of 2 delay units. + 0x2 + + + rd_dq14_del_3 + Add dq14 delay of 3 delay units. + 0x3 + + + rd_dq14_del_4 + Add dq14 delay of 4 delay units. + 0x4 + + + rd_dq14_del_5 + Add dq14 delay of 5 delay units. + 0x5 + + + rd_dq14_del_6 + Add dq14 delay of 6 delay units. + 0x6 + + + rd_dq14_del_7 + Add dq14 delay of 7 delay units. + 0x7 + + + + + rd_dq15_del + Read dqs1 to dq15 delay fine-tuning + 0x1C + 3 + read-write + + + rd_dq15_del_0 + No change in dq15 delay + 0 + + + rd_dq15_del_1 + Add dq15 delay of 1 delay unit + 0x1 + + + rd_dq15_del_2 + Add dq15 delay of 2 delay units. + 0x2 + + + rd_dq15_del_3 + Add dq15 delay of 3 delay units. + 0x3 + + + rd_dq15_del_4 + Add dq15 delay of 4 delay units. + 0x4 + + + rd_dq15_del_5 + Add dq15 delay of 5 delay units. + 0x5 + + + rd_dq15_del_6 + Add dq15 delay of 6 delay units. + 0x6 + + + rd_dq15_del_7 + Add dq15 delay of 7 delay units. + 0x7 + + + + + + + MPWRDQBY0DL + MMDC PHY Write DQ Byte0 Delay Register + 0x82C + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq0_del + Write dq0 delay fine-tuning + 0 + 2 + read-write + + + wr_dq0_del_0 + No change in dq0 delay + 0 + + + wr_dq0_del_1 + Add dq0 delay of 1 delay unit. + 0x1 + + + wr_dq0_del_2 + Add dq0 delay of 2 delay units. + 0x2 + + + wr_dq0_del_3 + Add dq0 delay of 3 delay units. + 0x3 + + + + + wr_dq1_del + Write dq1 delay fine-tuning + 0x4 + 2 + read-write + + + wr_dq1_del_0 + No change in dq1 delay + 0 + + + wr_dq1_del_1 + Add dq1 delay of 1 delay unit. + 0x1 + + + wr_dq1_del_2 + Add dq1 delay of 2 delay units. + 0x2 + + + wr_dq1_del_3 + Add dq1 delay of 3 delay units. + 0x3 + + + + + wr_dq2_del + Write dq2 delay fine-tuning + 0x8 + 2 + read-write + + + wr_dq2_del_0 + No change in dq2 delay + 0 + + + wr_dq2_del_1 + Add dq2 delay of 1 delay unit. + 0x1 + + + wr_dq2_del_2 + Add dq2 delay of 2 delay units. + 0x2 + + + wr_dq2_del_3 + Add dq2 delay of 3 delay units. + 0x3 + + + + + wr_dq3_del + Write dq3 delay fine-tuning + 0xC + 2 + read-write + + + wr_dq3_del_0 + No change in dq3 delay + 0 + + + wr_dq3_del_1 + Add dq3 delay of 1 delay unit. + 0x1 + + + wr_dq3_del_2 + Add dq3 delay of 2 delay units. + 0x2 + + + wr_dq3_del_3 + Add dq3 delay of 3 delay units. + 0x3 + + + + + wr_dq4_del + Write dq4 delay fine-tuning + 0x10 + 2 + read-write + + + wr_dq4_del_0 + No change in dq4 delay + 0 + + + wr_dq4_del_1 + Add dq4 delay of 1 delay unit.. + 0x1 + + + wr_dq4_del_2 + Add dq4 delay of 2 delay units. + 0x2 + + + wr_dq4_del_3 + Add dq4 delay of 3 delay units. + 0x3 + + + + + wr_dq5_del + Write dq5 delay fine-tuning + 0x14 + 2 + read-write + + + wr_dq5_del_0 + No change in dq5 delay + 0 + + + wr_dq5_del_1 + Add dq5 delay of 1 delay unit. + 0x1 + + + wr_dq5_del_2 + Add dq5 delay of 2 delay units. + 0x2 + + + wr_dq5_del_3 + Add dq5 delay of 3 delay units. + 0x3 + + + + + wr_dq6_del + Write dq6 delay fine-tuning + 0x18 + 2 + read-write + + + wr_dq6_del_0 + No change in dq6 delay + 0 + + + wr_dq6_del_1 + Add dq6 delay of 1 delay unit. + 0x1 + + + wr_dq6_del_2 + Add dq6 delay of 2 delay units. + 0x2 + + + wr_dq6_del_3 + Add dq6 delay of 3 delay units. + 0x3 + + + + + wr_dq7_del + Write dq7 delay fine-tuning + 0x1C + 2 + read-write + + + wr_dq7_del_0 + No change in dq7 delay + 0 + + + wr_dq7_del_1 + Add dq7 delay of 1 delay unit. + 0x1 + + + wr_dq7_del_2 + Add dq7 delay of 2 delay units. + 0x2 + + + wr_dq7_del_3 + Add dq7 delay of 3 delay units. + 0x3 + + + + + wr_dm0_del + Write dm0 delay fine-tuning + 0x1E + 2 + read-write + + + wr_dm0_del_0 + No change in dm0 delay + 0 + + + wr_dm0_del_1 + Add dm0 delay of 1 delay unit. + 0x1 + + + wr_dm0_del_2 + Add dm0 delay of 2 delay units. + 0x2 + + + wr_dm0_del_3 + Add dm0 delay of 3 delay units. + 0x3 + + + + + + + MPWRDQBY1DL + MMDC PHY Write DQ Byte1 Delay Register + 0x830 + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq8_del + Write dq8 delay fine-tuning + 0 + 2 + read-write + + + wr_dq8_del_0 + No change in dq8 delay + 0 + + + wr_dq8_del_1 + Add dq8 delay of 1 delay unit. + 0x1 + + + wr_dq8_del_2 + Add dq8 delay of 2 delay units. + 0x2 + + + wr_dq8_del_3 + Add dq8 delay of 3 delay units. + 0x3 + + + + + wr_dq9_del + Write dq9 delay fine-tuning + 0x4 + 2 + read-write + + + wr_dq9_del_0 + No change in dq9 delay + 0 + + + wr_dq9_del_1 + Add dq9 delay of 1 delay unit. + 0x1 + + + wr_dq9_del_2 + Add dq9 delay of 2 delay units. + 0x2 + + + wr_dq9_del_3 + Add dq9 delay of 3 delay units. + 0x3 + + + + + wr_dq10_del + Write dq10 delay fine-tuning + 0x8 + 2 + read-write + + + wr_dq10_del_0 + No change in dq10 delay + 0 + + + wr_dq10_del_1 + Add dq10 delay of 1 delay unit. + 0x1 + + + wr_dq10_del_2 + Add dq10 delay of 2 delay units. + 0x2 + + + wr_dq10_del_3 + Add dq10 delay of 3 delay units. + 0x3 + + + + + wr_dq11_del + Write dq11 delay fine-tuning + 0xC + 2 + read-write + + + wr_dq11_del_0 + No change in dq11 delay + 0 + + + wr_dq11_del_1 + Add dq11 delay of 1 delay unit. + 0x1 + + + wr_dq11_del_2 + Add dq11 delay of 2 delay units. + 0x2 + + + wr_dq11_del_3 + Add dq11 delay of 3 delay units. + 0x3 + + + + + wr_dq12_del + Write dq12 delay fine-tuning + 0x10 + 2 + read-write + + + wr_dq12_del_0 + No change in dq12 delay + 0 + + + wr_dq12_del_1 + Add dq12 delay of 1 delay unit. + 0x1 + + + wr_dq12_del_2 + Add dq12 delay of 2 delay units. + 0x2 + + + wr_dq12_del_3 + Add dq12 delay of 3 delay units. + 0x3 + + + + + wr_dq13_del + Write dq13 delay fine-tuning + 0x14 + 2 + read-write + + + wr_dq13_del_0 + No change in dq13 delay + 0 + + + wr_dq13_del_1 + Add dq13 delay of 1 delay unit. + 0x1 + + + wr_dq13_del_2 + Add dq13 delay of 2 delay units. + 0x2 + + + wr_dq13_del_3 + Add dq13 delay of 3 delay units. + 0x3 + + + + + wr_dq14_del + Write dq14 delay fine-tuning + 0x18 + 2 + read-write + + + wr_dq14_del_0 + No change in dq14 delay + 0 + + + wr_dq14_del_1 + Add dq14 delay of 1 delay unit. + 0x1 + + + wr_dq14_del_2 + Add dq14 delay of 2 delay units. + 0x2 + + + wr_dq14_del_3 + Add dq14 delay of 3 delay units. + 0x3 + + + + + wr_dq15_del + Write dq15 delay fine-tuning + 0x1C + 2 + read-write + + + wr_dq15_del_0 + No change in dq15 delay + 0 + + + wr_dq15_del_1 + Add dq15 delay of 1 delay unit. + 0x1 + + + wr_dq15_del_2 + Add dq15 delay of 2 delay units. + 0x2 + + + wr_dq15_del_3 + Add dq15 delay of 3 delay units. + 0x3 + + + + + wr_dm1_del + Write dm1 delay fine-tuning + 0x1E + 2 + read-write + + + wr_dm1_del_0 + No change in dm1 delay + 0 + + + wr_dm1_del_1 + Add dm1 delay of 1 delay unit. + 0x1 + + + wr_dm1_del_2 + Add dm1 delay of 2 delay units. + 0x2 + + + wr_dm1_del_3 + Add dm1 delay of 3 delay units. + 0x3 + + + + + + + MPWRDQBY2DL + MMDC PHY Write DQ Byte2 Delay Register + 0x834 + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq16_del + Write dq16 delay fine tuning + 0 + 2 + read-write + + + wr_dq16_del_0 + No change in dq16 delay + 0 + + + wr_dq16_del_1 + Add dq16 delay of 1 delay unit. + 0x1 + + + wr_dq16_del_2 + Add dq16 delay of 2 delay units. + 0x2 + + + wr_dq16_del_3 + Add dq16 delay of 3 delay units. + 0x3 + + + + + wr_dq17_del + Write dq17 delay fine tuning + 0x4 + 2 + read-write + + + wr_dq17_del_0 + No change in dq17 delay + 0 + + + wr_dq17_del_1 + Add dq17 delay of 1 delay unit. + 0x1 + + + wr_dq17_del_2 + Add dq17 delay of 2 delay units. + 0x2 + + + wr_dq17_del_3 + Add dq17 delay of 3 delay units. + 0x3 + + + + + wr_dq18_del + Write dq18 delay fine tuning + 0x8 + 2 + read-write + + + wr_dq18_del_0 + No change in dq18 delay + 0 + + + wr_dq18_del_1 + Add dq18 delay of 1 delay unit. + 0x1 + + + wr_dq18_del_2 + Add dq18 delay of 2 delay units. + 0x2 + + + wr_dq18_del_3 + Add dq18 delay of 3 delay units. + 0x3 + + + + + wr_dq19_del + Write dq19 delay fine tuning + 0xC + 2 + read-write + + + wr_dq19_del_0 + No change in dq19 delay + 0 + + + wr_dq19_del_1 + Add dq19 delay of 1 delay unit. + 0x1 + + + wr_dq19_del_2 + Add dq19 delay of 2 delay units. + 0x2 + + + wr_dq19_del_3 + Add dq19 delay of 3 delay units. + 0x3 + + + + + wr_dq20_del + Write dq20 delay fine tuning + 0x10 + 2 + read-write + + + wr_dq20_del_0 + No change in dq20 delay + 0 + + + wr_dq20_del_1 + Add dq20 delay of 1 delay unit. + 0x1 + + + wr_dq20_del_2 + Add dq20 delay of 2 delay units. + 0x2 + + + wr_dq20_del_3 + Add dq20 delay of 3 delay units. + 0x3 + + + + + wr_dq21_del + Write dq21 delay fine tuning + 0x14 + 2 + read-write + + + wr_dq21_del_0 + No change in dq21 delay + 0 + + + wr_dq21_del_1 + Add dq21 delay of 1 delay unit. + 0x1 + + + wr_dq21_del_2 + Add dq21 delay of 2 delay units. + 0x2 + + + wr_dq21_del_3 + Add dq21 delay of 3 delay units. + 0x3 + + + + + wr_dq22_del + Write dq22 delay fine tuning + 0x18 + 2 + read-write + + + wr_dq22_del_0 + No change in dq22 delay + 0 + + + wr_dq22_del_1 + Add dq22 delay of 1 delay unit. + 0x1 + + + wr_dq22_del_2 + Add dq22 delay of 2 delay units. + 0x2 + + + wr_dq22_del_3 + Add dq22 delay of 3 delay units. + 0x3 + + + + + wr_dq23_del + Write dq23 delay fine tuning + 0x1C + 2 + read-write + + + wr_dq23_del_0 + No change in dq23 delay + 0 + + + wr_dq23_del_1 + Add dq23 delay of 1 delay unit. + 0x1 + + + wr_dq23_del_2 + Add dq23 delay of 2 delay units. + 0x2 + + + wr_dq23_del_3 + Add dq23 delay of 3 delay units. + 0x3 + + + + + wr_dm2_del + Write dm2 delay fine-tuning + 0x1E + 2 + read-write + + + wr_dm2_del_0 + No change in dm2 delay + 0 + + + wr_dm2_del_1 + Add dm2 delay of 1 delay unit. + 0x1 + + + wr_dm2_del_2 + Add dm2 delay of 2 delay units. + 0x2 + + + wr_dm2_del_3 + Add dm2 delay of 3 delay units. + 0x3 + + + + + + + MPWRDQBY3DL + MMDC PHY Write DQ Byte3 Delay Register + 0x838 + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq24_del + Write dq24 delay fine tuning + 0 + 2 + read-write + + + wr_dq24_del_0 + No change in dq24 delay + 0 + + + wr_dq24_del_1 + Add dq24 delay of 1 delay unit. + 0x1 + + + wr_dq24_del_2 + Add dq24 delay of 2 delay units. + 0x2 + + + wr_dq24_del_3 + Add dq24 delay of 3 delay units. + 0x3 + + + + + wr_dq25_del + Write dq25 delay fine tuning + 0x4 + 2 + read-write + + + wr_dq25_del_0 + No change in dq25 delay + 0 + + + wr_dq25_del_1 + Add dq25 delay of 1 delay unit. + 0x1 + + + wr_dq25_del_2 + Add dq25 delay of 2 delay units. + 0x2 + + + wr_dq25_del_3 + Add dq25 delay of 3 delay units. + 0x3 + + + + + wr_dq26_del + Write dq26 delay fine tuning + 0x8 + 2 + read-write + + + wr_dq26_del_0 + No change in dq26 delay + 0 + + + wr_dq26_del_1 + Add dq26 delay of 1 delay unit. + 0x1 + + + wr_dq26_del_2 + Add dq26 delay of 2 delay units. + 0x2 + + + wr_dq26_del_3 + Add dq26 delay of 3 delay units. + 0x3 + + + + + wr_dq27_del + Write dq27 delay fine tuning + 0xC + 2 + read-write + + + wr_dq27_del_0 + No change in dq27 delay + 0 + + + wr_dq27_del_1 + Add dq27 delay of 1 delay unit. + 0x1 + + + wr_dq27_del_2 + Add dq27 delay of 2 delay units. + 0x2 + + + wr_dq27_del_3 + Add dq27 delay of 3 delay units. + 0x3 + + + + + wr_dq28_del + Write dq28 delay fine tuning + 0x10 + 2 + read-write + + + wr_dq28_del_0 + No change in dq28 delay + 0 + + + wr_dq28_del_1 + Add dq28 delay of 1 delay unit. + 0x1 + + + wr_dq28_del_2 + Add dq28 delay of 2 delay units. + 0x2 + + + wr_dq28_del_3 + Add dq28 delay of 3 delay units. + 0x3 + + + + + wr_dq29_del + Write dq29 delay fine tuning + 0x14 + 2 + read-write + + + wr_dq29_del_0 + No change in dq29 delay + 0 + + + wr_dq29_del_1 + Add dq29 delay of 1 delay unit. + 0x1 + + + wr_dq29_del_2 + Add dq29 delay of 2 delay units. + 0x2 + + + wr_dq29_del_3 + Add dq29 delay of 3 delay units. + 0x3 + + + + + wr_dq30_del + Write dq30 delay fine tuning + 0x18 + 2 + read-write + + + wr_dq30_del_0 + No change in dq30 delay + 0 + + + wr_dq30_del_1 + Add dq30 delay of 1 delay unit. + 0x1 + + + wr_dq30_del_2 + Add dq30 delay of 2 delay units. + 0x2 + + + wr_dq30_del_3 + Add dq30 delay of 3 delay units. + 0x3 + + + + + wr_dq31_del + Write dq31 delay fine tuning + 0x1C + 2 + read-write + + + wr_dq31_del_0 + No change in dq31 delay + 0 + + + wr_dq31_del_1 + Add dq31 delay of 1 delay unit. + 0x1 + + + wr_dq31_del_2 + Add dq31 delay of 2 delay units. + 0x2 + + + wr_dq31_del_3 + Add dq31 delay of 3 delay units. + 0x3 + + + + + wr_dm3_del + Write dm3 delay fine tuning + 0x1E + 2 + read-write + + + wr_dm3_del_0 + No change in dm3 delay + 0 + + + wr_dm3_del_1 + Add dm3 delay of 1 delay unit. + 0x1 + + + wr_dm3_del_2 + Add dm3 delay of 2 delay units. + 0x2 + + + wr_dm3_del_3 + Add dm3 delay of 3 delay units. + 0x3 + + + + + + + MPDGCTRL0 + MMDC PHY Read DQS Gating Control Register 0 + 0x83C + 32 + read-write + 0 + 0xFFFFFFFF + + + DG_DL_ABS_OFFSET0 + Absolute read DQS gating delay offset for Byte0 + 0 + 7 + read-write + + + DG_HC_DEL0 + Read DQS gating half cycles delay for Byte0 + 0x8 + 4 + read-write + + + DG_HC_DEL0_0 + 0 cycles delay. + 0 + + + DG_HC_DEL0_1 + Half cycle delay. + 0x1 + + + DG_HC_DEL0_2 + 1 cycle delay + 0x2 + + + DG_HC_DEL0_13 + 6.5 cycles delay + 0xD + + + + + HW_DG_ERR + HW DQS gating error + 0xC + 1 + read-only + + + HW_DG_ERR_0 + No error was found during the DQS gating HW calibration process. + 0 + + + HW_DG_ERR_1 + An error was found during the DQS gating HW calibration process. + 0x1 + + + + + DG_DL_ABS_OFFSET1 + Absolute read DQS gating delay offset for Byte1 + 0x10 + 7 + read-write + + + DG_EXT_UP + DG extend upper boundary + 0x17 + 1 + read-write + + + DG_HC_DEL1 + Read DQS gating half cycles delay for Byte1 + 0x18 + 4 + read-write + + + DG_HC_DEL1_0 + 0 cycles delay. + 0 + + + DG_HC_DEL1_1 + Half cycle delay. + 0x1 + + + DG_HC_DEL1_2 + 1 cycle delay + 0x2 + + + DG_HC_DEL1_13 + 6.5 cycles delay + 0xD + + + + + HW_DG_EN + Enable automatic read DQS gating calibration + 0x1C + 1 + read-write + + + HW_DG_EN_0 + Disable automatic read DQS gating calibration + 0 + + + HW_DG_EN_1 + Start automatic read DQS gating calibration + 0x1 + + + + + DG_DIS + Read DQS gating disable + 0x1D + 1 + read-write + + + DG_DIS_0 + Read DQS gating mechanism is enabled + 0 + + + DG_DIS_1 + Read DQS gating mechanism is disabled + 0x1 + + + + + DG_CMP_CYC + Read DQS gating sample cycle + 0x1E + 1 + read-write + + + DG_CMP_CYC_0 + MMDC waits 16 DDR cycles + 0 + + + DG_CMP_CYC_1 + MMDC waits 32 DDR cycles + 0x1 + + + + + RST_RD_FIFO + Reset Read Data FIFO and associated pointers + 0x1F + 1 + read-write + + + + + MPDGDLST0 + MMDC PHY Read DQS Gating delay-line Status Register + 0x844 + 32 + read-only + 0 + 0xFFFFFFFF + + + DG_DL_UNIT_NUM0 + This field reflects the number of delay units that are actually used by read DQS gating delay-line 0 + 0 + 7 + read-only + + + DG_DL_UNIT_NUM1 + This field reflects the number of delay units that are actually used by read DQS gating delay-line 1 + 0x8 + 7 + read-only + + + + + MPRDDLCTL + MMDC PHY Read delay-lines Configuration Register + 0x848 + 32 + read-write + 0x40404040 + 0xFFFFFFFF + + + RD_DL_ABS_OFFSET0 + Absolute read delay offset for Byte0 + 0 + 7 + read-write + + + RD_DL_ABS_OFFSET1 + Absolute read delay offset for Byte1 + 0x8 + 7 + read-write + + + + + MPRDDLST + MMDC PHY Read delay-lines Status Register + 0x84C + 32 + read-only + 0 + 0xFFFFFFFF + + + RD_DL_UNIT_NUM0 + This field reflects the number of delay units that are actually used by read delay-line 0. + 0 + 7 + read-only + + + RD_DL_UNIT_NUM1 + This field reflects the number of delay units that are actually used by read delay-line 1. + 0x8 + 7 + read-only + + + + + MPWRDLCTL + MMDC PHY Write delay-lines Configuration Register + 0x850 + 32 + read-write + 0x40404040 + 0xFFFFFFFF + + + WR_DL_ABS_OFFSET0 + Absolute write delay offset for Byte0 + 0 + 7 + read-write + + + WR_DL_ABS_OFFSET1 + Absolute write delay offset for Byte1 + 0x8 + 7 + read-write + + + + + MPWRDLST + MMDC PHY Write delay-lines Status Register + 0x854 + 32 + read-only + 0 + 0xFFFFFFFF + + + WR_DL_UNIT_NUM0 + This field reflects the number of delay units that are actually used by write delay-line 0. + 0 + 7 + read-only + + + WR_DL_UNIT_NUM1 + This field reflects the number of delay units that are actually used by write delay-line 1. + 0x8 + 7 + read-only + + + + + MPSDCTRL + MMDC PHY CK Control Register + 0x858 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDclk0_del + DDR clock0 delay fine tuning + 0x8 + 2 + read-write + + + SDclk0_del_0 + No change in DDR clock0 delay + 0 + + + SDclk0_del_1 + Add DDR clock0 delay of 1 delay unit. + 0x1 + + + SDclk0_del_2 + Add DDR clock0 delay of 2 delay units. + 0x2 + + + SDclk0_del_3 + Add DDR clock0 delay of 3 delay units. + 0x3 + + + + + SDCLK1_del + DDR clock1 delay fine tuning + 0xA + 2 + read-write + + + SDCLK1_del_0 + No change in DDR clock delay + 0 + + + SDCLK1_del_1 + Add DDR clock delay of 1 delay unit. + 0x1 + + + SDCLK1_del_2 + Add DDR clock delay of 2 delay units. + 0x2 + + + SDCLK1_del_3 + Add DDR clock delay of 3 delay units. + 0x3 + + + + + + + MPZQLP2CTL + MMDC ZQ LPDDR2 HW Control Register + 0x85C + 32 + read-write + 0x1B5F0109 + 0xFFFFFFFF + + + ZQ_LP2_HW_ZQINIT + This register defines the period in cycles that it takes the memory device to perform a Init ZQ calibration + 0 + 9 + read-write + + + ZQ_LP2_HW_ZQINIT_55 + 112 cycles + 0x37 + + + ZQ_LP2_HW_ZQINIT_56 + 114 cycles + 0x38 + + + ZQ_LP2_HW_ZQINIT_265 + 532 cycles (Default, JEDEC value, tZQINIT, for LPDDR2, 1us @ clock frequency 533MHz) + 0x109 + + + ZQ_LP2_HW_ZQINIT_510 + 1022 cycles + 0x1FE + + + ZQ_LP2_HW_ZQINIT_511 + 1024 cycles + 0x1FF + + + + + ZQ_LP2_HW_ZQCL + This register defines the period in cycles that it takes the memory device to perform a long ZQ calibration + 0x10 + 8 + read-write + + + ZQ_LP2_HW_ZQCL_55 + 112 cycles + 0x37 + + + ZQ_LP2_HW_ZQCL_56 + 114 cycles + 0x38 + + + ZQ_LP2_HW_ZQCL_95 + 192 cycles (Default, JEDEC value, tZQCL, for LPDDR2, 360ns @ clock frequency 533MHz) + 0x5F + + + ZQ_LP2_HW_ZQCL_254 + 510 cycles + 0xFE + + + ZQ_LP2_HW_ZQCL_255 + 512 cycles + 0xFF + + + + + ZQ_LP2_HW_ZQCS + This register defines the period in cycles that it takes the memory device to perform a short ZQ calibration + 0x18 + 7 + read-write + + + ZQ_LP2_HW_ZQCS_27 + 112 cycles (default) + 0x1B + + + ZQ_LP2_HW_ZQCS_28 + 116 cycles + 0x1C + + + ZQ_LP2_HW_ZQCS_126 + 508 cycles + 0x7E + + + ZQ_LP2_HW_ZQCS_127 + 512 cycles + 0x7F + + + + + + + MPRDDLHWCTL + MMDC PHY Read Delay HW Calibration Control Register + 0x860 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_RD_DL_ERR0 + Automatic (HW) read calibration error of Byte0 + 0 + 1 + read-only + + + HW_RD_DL_ERR0_0 + No error was found in read delay-line 0 during the automatic (HW) read calibration process of read delay-line 0. + 0 + + + HW_RD_DL_ERR0_1 + An error was found in read delay-line 0 during the automatic (HW) read calibration process of read delay-line 0. + 0x1 + + + + + HW_RD_DL_ERR1 + Automatic (HW) read calibration error of Byte1 + 0x1 + 1 + read-only + + + HW_RD_DL_ERR1_0 + No error was found in read delay-line 1 during the automatic (HW) read calibration process of read delay-line 1. + 0 + + + HW_RD_DL_ERR1_1 + An error was found in read delay-line 1 during the automatic (HW) read calibration process of read delay-line 1. + 0x1 + + + + + HW_RD_DL_EN + Enable automatic (HW) read calibration + 0x4 + 1 + read-write + + + HW_RD_DL_CMP_CYC + Automatic (HW) read sample cycle + 0x5 + 1 + read-write + + + + + MPWRDLHWCTL + MMDC PHY Write Delay HW Calibration Control Register + 0x864 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_WR_DL_ERR0 + Automatic (HW) write calibration error of Byte0 + 0 + 1 + read-only + + + HW_WR_DL_ERR0_0 + No error was found during the automatic (HW) write calibration process of write delay-line 0. + 0 + + + HW_WR_DL_ERR0_1 + An error was found during the automatic (HW) write calibration process of write delay-line 0. + 0x1 + + + + + HW_WR_DL_ERR1 + Automatic (HW) write calibration error of Byte1 + 0x1 + 1 + read-only + + + HW_WR_DL_ERR1_0 + No error was found during the automatic (HW) write calibration process of write delay-line 1. + 0 + + + HW_WR_DL_ERR1_1 + An error was found during the automatic (HW) write calibration process of write delay-line 1. + 0x1 + + + + + HW_WR_DL_EN + Enable automatic (HW) write calibration + 0x4 + 1 + read-write + + + HW_WR_DL_CMP_CYC + Write sample cycle + 0x5 + 1 + read-write + + + + + MPRDDLHWST0 + MMDC PHY Read Delay HW Calibration Status Register 0 + 0x868 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_RD_DL_LOW0 + Automatic (HW) read calibration result of the lower boundary of Byte0 + 0 + 7 + read-only + + + HW_RD_DL_UP0 + Automatic (HW) read calibration result of the upper boundary of Byte0 + 0x8 + 7 + read-only + + + HW_RD_DL_LOW1 + Automatic (HW) read calibration result of the lower boundary of Byte1 + 0x10 + 7 + read-only + + + HW_RD_DL_UP1 + Automatic (HW) read calibration result of the upper boundary of Byte1 + 0x18 + 7 + read-only + + + + + MPWRDLHWST0 + MMDC PHY Write Delay HW Calibration Status Register 0 + 0x870 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_WR_DL_LOW0 + Automatic (HW) write calibration result of the lower boundary of Byte0 + 0 + 7 + read-only + + + HW_WR_DL_UP0 + Automatic (HW) write calibration result of the upper boundary of Byte0 + 0x8 + 7 + read-only + + + HW_WR_DL_LOW1 + Automatic (HW) write calibration result of the lower boundary of Byte1 + 0x10 + 7 + read-only + + + HW_WR_DL_UP1 + Automatic (HW) write automatic (HW) write calibration result of the upper boundary of Byte1 + 0x18 + 7 + read-only + + + + + MPWLHWERR + MMDC PHY Write Leveling HW Error Register + 0x878 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_WL0_DQ + HW write-leveling calibration result of Byte0 + 0 + 8 + read-only + + + HW_WL1_DQ + HW write-leveling calibration result of Byte1 + 0x8 + 8 + read-only + + + + + MPDGHWST0 + MMDC PHY Read DQS Gating HW Status Register 0 + 0x87C + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_DG_LOW0 + HW DQS gating calibration result of the lower boundary of Byte0 + 0 + 11 + read-only + + + HW_DG_UP0 + HW DQS gating calibration result of the upper boundary of Byte0 + 0x10 + 11 + read-only + + + + + MPDGHWST1 + MMDC PHY Read DQS Gating HW Status Register 1 + 0x880 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_DG_LOW1 + HW DQS gating calibration result of the lower boundary of Byte1 + 0 + 11 + read-only + + + HW_DG_UP1 + HW DQS gating calibration result of the upper boundary of Byte1 + 0x10 + 11 + read-only + + + + + MPPDCMPR1 + MMDC PHY Pre-defined Compare Register 1 + 0x88C + 32 + read-write + 0 + 0xFFFFFFFF + + + PDV1 + MMDC Pre defined compare value2 + 0 + 16 + read-write + + + PDV2 + MMDC Pre defined compare value2 + 0x10 + 16 + read-write + + + + + MPPDCMPR2 + MMDC PHY Pre-defined Compare and CA delay-line Configuration Register + 0x890 + 32 + read-write + 0x400000 + 0xFFFFFFFF + + + MPR_CMP + MPR(DDR3)/ DQ calibration (LPDDR2/LPDDR3) compare enable + 0 + 1 + read-write + + + MPR_FULL_CMP + MPR(DDR3)/ DQ calibration (LPDDR2/LPDDR3) full compare enable + 0x1 + 1 + read-write + + + READ_LEVEL_PATTERN + MPR(DDR3)/ DQ calibration (LPDDR2/LPDDR3) read compare pattern + 0x2 + 1 + read-write + + + READ_LEVEL_PATTERN_0 + Compare with read pattern 1010 + 0 + + + READ_LEVEL_PATTERN_1 + Compare with read pattern 0011 (Used only in LPDDR2/LPDDR3 mode) + 0x1 + + + + + ZQ_OFFSET_EN + no description available + 0x3 + 1 + read-write + + + ZQ_OFFSET_EN_0 + Hardware ZQ offset disabled + 0 + + + ZQ_OFFSET_EN_1 + Hardware ZQ offset enabled + 0x1 + + + + + ZQ_PD_OFFSET + Programmable offset from -7 to 7 added to the MMDC_MPZQHWCTRL[ZQ_HW_PD_RES] field when ZQ_OFFSET_EN is enabled + 0x4 + 4 + read-write + + + ZQ_PD_OFFSET_0 + +0 + 0 + + + ZQ_PD_OFFSET_1 + +1 + 0x1 + + + ZQ_PD_OFFSET_2 + +2 + 0x2 + + + ZQ_PD_OFFSET_3 + +3 + 0x3 + + + ZQ_PD_OFFSET_4 + +4 + 0x4 + + + ZQ_PD_OFFSET_5 + +5 + 0x5 + + + ZQ_PD_OFFSET_6 + +6 + 0x6 + + + ZQ_PD_OFFSET_7 + +7 + 0x7 + + + ZQ_PD_OFFSET_8 + -0 + 0x8 + + + ZQ_PD_OFFSET_9 + -1 + 0x9 + + + ZQ_PD_OFFSET_10 + -2 + 0xA + + + ZQ_PD_OFFSET_11 + -3 + 0xB + + + ZQ_PD_OFFSET_12 + -4 + 0xC + + + ZQ_PD_OFFSET_13 + -5 + 0xD + + + ZQ_PD_OFFSET_14 + -6 + 0xE + + + ZQ_PD_OFFSET_15 + -7 + 0xF + + + + + ZQ_PU_OFFSET + Programmable offset from -7 to 7 added to the MMDC_MPZQHWCTRL[ZQ_HW_PU_RES] field when ZQ_OFFSET_EN is enabled + 0x8 + 4 + read-write + + + ZQ_PU_OFFSET_0 + +0 + 0 + + + ZQ_PU_OFFSET_1 + +1 + 0x1 + + + ZQ_PU_OFFSET_2 + +2 + 0x2 + + + ZQ_PU_OFFSET_3 + +3 + 0x3 + + + ZQ_PU_OFFSET_4 + +4 + 0x4 + + + ZQ_PU_OFFSET_5 + +5 + 0x5 + + + ZQ_PU_OFFSET_6 + +6 + 0x6 + + + ZQ_PU_OFFSET_7 + +7 + 0x7 + + + ZQ_PU_OFFSET_8 + -0 + 0x8 + + + ZQ_PU_OFFSET_9 + -1 + 0x9 + + + ZQ_PU_OFFSET_10 + -2 + 0xA + + + ZQ_PU_OFFSET_11 + -3 + 0xB + + + ZQ_PU_OFFSET_12 + -4 + 0xC + + + ZQ_PU_OFFSET_13 + -5 + 0xD + + + ZQ_PU_OFFSET_14 + -6 + 0xE + + + ZQ_PU_OFFSET_15 + -7 + 0xF + + + + + CA_DL_ABS_OFFSET + Absolute CA (Command/Address of LPDDRR2) offset + 0x10 + 7 + read-write + + + PHY_CA_DL_UNIT + This field reflects the number of delay units that are actually used by CA(Command/Address of LPDDR2) delay-line + 0x18 + 7 + read-only + + + + + MPSWDAR0 + MMDC PHY SW Dummy Access Register + 0x894 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_DUMMY_WR + SW dummy write + 0 + 1 + read-write + + + SW_DUMMY_RD + SW dummy read + 0x1 + 1 + read-write + + + SW_DUM_CMP0 + SW dummy read byte0 compare results + 0x2 + 1 + read-only + + + SW_DUM_CMP0_0 + Dummy read fail + 0 + + + SW_DUM_CMP0_1 + Dummy read pass + 0x1 + + + + + SW_DUM_CMP1 + SW dummy read byte1 compare results + 0x3 + 1 + read-only + + + SW_DUM_CMP1_0 + Dummy read fail + 0 + + + SW_DUM_CMP1_1 + Dummy read pass + 0x1 + + + + + + + MPSWDRDR0 + MMDC PHY SW Dummy Read Data Register 0 + 0x898 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD0 + Dummy read data0 + 0 + 32 + read-only + + + + + MPSWDRDR1 + MMDC PHY SW Dummy Read Data Register 1 + 0x89C + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD1 + Dummy read data1 + 0 + 32 + read-only + + + + + MPSWDRDR2 + MMDC PHY SW Dummy Read Data Register 2 + 0x8A0 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD2 + Dummy read data2 + 0 + 32 + read-only + + + + + MPSWDRDR3 + MMDC PHY SW Dummy Read Data Register 3 + 0x8A4 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD3 + Dummy read data3 + 0 + 32 + read-only + + + + + MPSWDRDR4 + MMDC PHY SW Dummy Read Data Register 4 + 0x8A8 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD4 + Dummy read data4 + 0 + 32 + read-only + + + + + MPSWDRDR5 + MMDC PHY SW Dummy Read Data Register 5 + 0x8AC + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD5 + Dummy read data5 + 0 + 32 + read-only + + + + + MPSWDRDR6 + MMDC PHY SW Dummy Read Data Register 6 + 0x8B0 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD6 + Dummy read data6 + 0 + 32 + read-only + + + + + MPSWDRDR7 + MMDC PHY SW Dummy Read Data Register 7 + 0x8B4 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD7 + Dummy read data7 + 0 + 32 + read-only + + + + + MPMUR0 + MMDC PHY Measure Unit Register + 0x8B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MU_BYP_VAL + Number of delay units for measurement bypass + 0 + 10 + read-write + + + MU_BYP_EN + Measure unit bypass enable + 0xA + 1 + read-write + + + MU_BYP_EN_0 + The delay-lines use delay units as indicated at MU_UNIT_DEL_NUM. + 0 + + + MU_BYP_EN_1 + The delay-lines use delay units as indicated at MU_BYPASS_VAL. + 0x1 + + + + + FRC_MSR + Force measurement on delay-lines + 0xB + 1 + read-write + + + FRC_MSR_0 + No measurement is performed + 0 + + + FRC_MSR_1 + Perform measurement process + 0x1 + + + + + MU_UNIT_DEL_NUM + Number of delay units measured per cycle + 0x10 + 10 + read-only + + + + + MPWRCADL + MMDC Write CA delay-line controller + 0x8BC + 32 + read-write + 0 + 0xFFFFFFFF + + + WR_CA0_DEL + CA(Command/Address LPDDR2 bus) bit 0 delay fine tuning + 0 + 2 + read-write + + + WR_CA0_DEL_0 + No change in CA0 delay + 0 + + + WR_CA0_DEL_1 + Add CA0 delay of 1 delay unit + 0x1 + + + WR_CA0_DEL_2 + Add CA0 delay of 2 delay units. + 0x2 + + + WR_CA0_DEL_3 + Add CA0 delay of 3 delay units. + 0x3 + + + + + WR_CA1_DEL + CA (Command/Address LPDDR2 bus) bit 1 delay fine tuning + 0x2 + 2 + read-write + + + WR_CA1_DEL_0 + No change in CA1 delay + 0 + + + WR_CA1_DEL_1 + Add CA1 delay of 1 delay unit + 0x1 + + + WR_CA1_DEL_2 + Add CA1 delay of 2 delay units. + 0x2 + + + WR_CA1_DEL_3 + Add CA1 delay of 3 delay units. + 0x3 + + + + + WR_CA2_DEL + CA (Command/Address LPDDR2 bus) bit 2 delay fine tuning + 0x4 + 2 + read-write + + + WR_CA2_DEL_0 + No change in CA2 delay + 0 + + + WR_CA2_DEL_1 + Add CA2 delay of 1 delay unit + 0x1 + + + WR_CA2_DEL_2 + Add CA2 delay of 2 delay units. + 0x2 + + + WR_CA2_DEL_3 + Add CA2 delay of 3 delay units. + 0x3 + + + + + WR_CA3_DEL + CA (Command/Address LPDDR2 bus) bit 3 delay fine tuning + 0x6 + 2 + read-write + + + WR_CA3_DEL_0 + No change in CA3 delay + 0 + + + WR_CA3_DEL_1 + Add CA3 delay of 1 delay unit + 0x1 + + + WR_CA3_DEL_2 + Add CA3 delay of 2 delay units. + 0x2 + + + WR_CA3_DEL_3 + Add CA3 delay of 3 delay units. + 0x3 + + + + + WR_CA4_DEL + CA (Command/Address LPDDR2 bus) bit 4 delay fine tuning + 0x8 + 2 + read-write + + + WR_CA4_DEL_0 + No change in CA4 delay + 0 + + + WR_CA4_DEL_1 + Add CA4 delay of 1 delay unit + 0x1 + + + WR_CA4_DEL_2 + Add CA4 delay of 2 delay units. + 0x2 + + + WR_CA4_DEL_3 + Add CA4 delay of 3 delay units. + 0x3 + + + + + WR_CA5_DEL + CA (Command/Address LPDDR2 bus) bit 5 delay fine tuning + 0xA + 2 + read-write + + + WR_CA5_DEL_0 + No change in CA5 delay + 0 + + + WR_CA5_DEL_1 + Add CA5 delay of 1 delay unit + 0x1 + + + WR_CA5_DEL_2 + Add CA5 delay of 2 delay units. + 0x2 + + + WR_CA5_DEL_3 + Add CA5 delay of 3 delay units. + 0x3 + + + + + WR_CA6_DEL + CA (Command/Address LPDDR2 bus) bit 6 delay fine tuning + 0xC + 2 + read-write + + + WR_CA6_DEL_0 + No change in CA6 delay + 0 + + + WR_CA6_DEL_1 + Add CA6 delay of 1 delay unit + 0x1 + + + WR_CA6_DEL_2 + Add CA6 delay of 2 delay units. + 0x2 + + + WR_CA6_DEL_3 + Add CA6 delay of 3 delay units. + 0x3 + + + + + WR_CA7_DEL + CA (Command/Address LPDDR2 bus) bit 7 delay fine tuning + 0xE + 2 + read-write + + + WR_CA7_DEL_0 + No change in CA7 delay + 0 + + + WR_CA7_DEL_1 + Add CA7 delay of 1 delay unit + 0x1 + + + WR_CA7_DEL_2 + Add CA7 delay of 2 delay units. + 0x2 + + + WR_CA7_DEL_3 + Add CA7 delay of 3 delay units. + 0x3 + + + + + WR_CA8_DEL + CA (Command/Address LPDDR2 bus) bit 8 delay fine tuning + 0x10 + 2 + read-write + + + WR_CA8_DEL_0 + No change in CA8 delay + 0 + + + WR_CA8_DEL_1 + Add CA8 delay of 1 delay unit + 0x1 + + + WR_CA8_DEL_2 + Add CA8 delay of 2 delay units. + 0x2 + + + WR_CA8_DEL_3 + Add CA8 delay of 3 delay units. + 0x3 + + + + + WR_CA9_DEL + CA (Command/Address LPDDR2 bus) bit 9 delay fine tuning + 0x12 + 2 + read-write + + + WR_CA9_DEL_0 + No change in CA9 delay + 0 + + + WR_CA9_DEL_1 + Add CA9 delay of 1 delay unit + 0x1 + + + WR_CA9_DEL_2 + Add CA9 delay of 2 delay units. + 0x2 + + + WR_CA9_DEL_3 + Add CA9 delay of 3 delay units. + 0x3 + + + + + + + MPDCCR + MMDC Duty Cycle Control Register + 0x8C0 + 32 + read-write + 0x24922492 + 0xFFFFFFFF + + + WR_DQS0_FT_DCC + Write DQS duty cycle fine tuning control of Byte0 + 0 + 3 + read-write + + + WR_DQS0_FT_DCC_1 + 51.5% low 48.5% high + 0x1 + + + WR_DQS0_FT_DCC_2 + 50% duty cycle (default) + 0x2 + + + WR_DQS0_FT_DCC_4 + 48.5% low 51.5% high + 0x4 + + + + + WR_DQS1_FT_DCC + Write DQS duty cycle fine tuning control of Byte1 + 0x3 + 3 + read-write + + + WR_DQS1_FT_DCC_1 + 51.5% low 48.5% high + 0x1 + + + WR_DQS1_FT_DCC_2 + 50% duty cycle (default) + 0x2 + + + WR_DQS1_FT_DCC_4 + 48.5% low 51.5% high + 0x4 + + + + + CK_FT0_DCC + Primary duty cycle fine tuning control of DDR clock + 0xC + 3 + read-write + + + CK_FT0_DCC_1 + 48.5% low 51.5% high + 0x1 + + + CK_FT0_DCC_2 + 50% duty cycle (default) + 0x2 + + + CK_FT0_DCC_4 + 51.5% low 48.5% high + 0x4 + + + + + CK_FT1_DCC + Secondary duty cycle fine tuning control of DDR clock + 0x10 + 3 + read-write + + + CK_FT1_DCC_1 + 48.5% low 51.5% high + 0x1 + + + CK_FT1_DCC_2 + 50% duty cycle (default) + 0x2 + + + CK_FT1_DCC_4 + 51.5% low 48.5% high + 0x4 + + + + + RD_DQS0_FT_DCC + Read DQS duty cycle fine tuning control of Byte0 + 0x13 + 3 + read-write + + + RD_DQS0_FT_DCC_1 + 51.5% low 48.5% high + 0x1 + + + RD_DQS0_FT_DCC_2 + 50% duty cycle (default) + 0x2 + + + RD_DQS0_FT_DCC_4 + 48.5% low 51.5% high + 0x4 + + + + + RD_DQS1_FT_DCC + Read DQS duty cycle fine tuning control of Byte1 + 0x16 + 3 + read-write + + + RD_DQS1_FT_DCC_1 + 51.5% low 48.5% high + 0x1 + + + RD_DQS1_FT_DCC_2 + 50% duty cycle (default) + 0x2 + + + RD_DQS1_FT_DCC_4 + 48.5% low 51.5% high + 0x4 + + + + + + + + + EIM + EIM + EIM + EIM_ + 0x21B8000 + + 0 + 0x94 + registers + + + WEIM + 46 + + + + 6 + 0x18 + CS%sGCR1 + Chip Select n General Configuration Register 1 + 0 + 32 + read-write + 0x10080 + 0xFFFFFFFF + + + CSEN + CS Enable + 0 + 1 + read-write + + + CSEN_0 + Chip select function is disabled; attempts to access an address mapped by this chip select results in an error respond and no assertion of the chip select output + 0 + + + CSEN_1 + Chip select is enabled, and is asserted when presented with a valid access. + 0x1 + + + + + SWR + Synchronous Write Data + 0x1 + 1 + read-write + + + SWR_0 + write accesses are in Asynchronous mode + 0 + + + SWR_1 + write accesses are in Synchronous mode + 0x1 + + + + + SRD + Synchronous Read Data + 0x2 + 1 + read-write + + + SRD_0 + read accesses are in Asynchronous mode + 0 + + + SRD_1 + read accesses are in Synchronous mode + 0x1 + + + + + MUM + Multiplexed Mode + 0x3 + 1 + read-write + + + MUM_0 + Multiplexed Mode disable + 0 + + + MUM_1 + Multiplexed Mode enable + 0x1 + + + + + WFL + Write Fix Latency + 0x4 + 1 + read-write + + + WFL_0 + the External device WAIT signal is being monitored, and it reflect the external data bus state + 0 + + + WFL_1 + the state of the External devices is determined internally (Fix latency mode only) + 0x1 + + + + + RFL + Read Fix Latency + 0x5 + 1 + read-write + + + RFL_0 + the External device WAIT signal is being monitored, and it reflect the external data bus state + 0 + + + RFL_1 + the state of the External devices is determined internally (Fix latency mode only) + 0x1 + + + + + CRE + Configuration Register Enable + 0x6 + 1 + read-write + + + CRE_0 + CRE signal use is disable + 0 + + + CRE_1 + CRE signal use is enable + 0x1 + + + + + CREP + Configuration Register Enable Polarity + 0x7 + 1 + read-write + + + CREP_0 + CRE signal is active low + 0 + + + CREP_1 + CRE signal is active high + 0x1 + + + + + BL + Burst Length + 0x8 + 3 + read-write + + + BL_0 + 4 words Memory wrap burst length (read page burst size when APR = 1) + 0 + + + BL_1 + 8 words Memory wrap burst length (read page burst size when APR = 1) + 0x1 + + + BL_2 + 16 words Memory wrap burst length (read page burst size when APR = 1) + 0x2 + + + BL_3 + 32 words Memory wrap burst length (read page burst size when APR = 1) + 0x3 + + + BL_4 + Continuous burst length (2 words read page burst size when APR = 1) + 0x4 + + + + + WC + Write Continuous + 0xB + 1 + read-write + + + WC_0 + Write access burst length occurs according to BL value. + 0 + + + WC_1 + Write access burst length is continuous. + 0x1 + + + + + BCD + Burst Clock Divisor + 0xC + 2 + read-write + + + BCD_0 + Divide EIM clock by 1 + 0 + + + BCD_1 + Divide EIM clock by 2 + 0x1 + + + BCD_2 + Divide EIM clock by 3 + 0x2 + + + BCD_3 + Divide EIM clock by 4 + 0x3 + + + + + BCS + Burst Clock Start + 0xE + 2 + read-write + + + BCS_0 + 0 EIM clock cycle additional delay + 0 + + + BCS_1 + 1 EIM clock cycle additional delay + 0x1 + + + BCS_2 + 2 EIM clock cycle additional delay + 0x2 + + + BCS_3 + 3 EIM clock cycle additional delay + 0x3 + + + + + DSZ + Data Port Size + 0x10 + 3 + read-write + + + DSZ_1 + 16 bit port resides on DATA[15:0] + 0x1 + + + DSZ_2 + 16 bit port resides on DATA[31:16] + 0x2 + + + DSZ_3 + 32 bit port resides on DATA[31:0] + 0x3 + + + DSZ_4 + 8 bit port resides on DATA[7:0] + 0x4 + + + DSZ_5 + 8 bit port resides on DATA[15:8] + 0x5 + + + DSZ_6 + 8 bit port resides on DATA[23:16] + 0x6 + + + DSZ_7 + 8 bit port resides on DATA[31:24] + 0x7 + + + + + SP + Supervisor Protect + 0x13 + 1 + read-write + + + SP_0 + User mode accesses are allowed in the memory range defined by chip select. + 0 + + + SP_1 + User mode accesses are prohibited. All attempts to access an address mapped by this chip select in User mode results in an error response and no assertion of the chip select output. + 0x1 + + + + + CSREC + CS Recovery + 0x14 + 3 + read-write + + + CSREC_0 + 0 EIM clock cycles minimum width of CS, OE and WE signals (read async. mode only) + 0 + + + CSREC_1 + 1 EIM clock cycles minimum width of CS, OE and WE signals + 0x1 + + + CSREC_2 + 2 EIM clock cycles minimum width of CS, OE and WE signals + 0x2 + + + CSREC_7 + 7 EIM clock cycles minimum width of CS, OE and WE signals + 0x7 + + + + + AUS + Address UnShifted + 0x17 + 1 + read-write + + + AUS_0 + Address shifted according to port size (DSZ config) (128 Mbyte maximum supported memory density). + 0 + + + AUS_1 + Address unshifted (32 Mbyte maximum supported memory density). + 0x1 + + + + + GBC + Gap Between Chip Selects + 0x18 + 3 + read-write + + + GBC_0 + minimum of 0 EIM clock cycles before next access from different chip select (async. mode only) + 0 + + + GBC_1 + minimum of 1 EIM clock cycles before next access from different chip select + 0x1 + + + GBC_2 + minimum of 2 EIM clock cycles before next access from different chip select + 0x2 + + + GBC_7 + minimum of 7 EIM clock cycles before next access from different chip select + 0x7 + + + + + WP + Write Protect + 0x1B + 1 + read-write + + + WP_0 + Writes are allowed in the memory range defined by chip. + 0 + + + WP_1 + Writes are prohibited. All attempts to write to an address mapped by this chip select result in a error response and no assertion of the chip select output. + 0x1 + + + + + PSZ + Page Size + 0x1C + 4 + read-write + + + PSZ_0 + 8 words page size + 0 + + + PSZ_1 + 16 words page size + 0x1 + + + PSZ_2 + 32 words page size + 0x2 + + + PSZ_3 + 64 words page size + 0x3 + + + PSZ_4 + 128 words page size + 0x4 + + + PSZ_5 + 256 words page size + 0x5 + + + PSZ_6 + 512 words page size + 0x6 + + + PSZ_7 + 1024 (1k) words page size + 0x7 + + + PSZ_8 + 2048 (2k) words page size + 0x8 + + + PSZ_9 + - 1111 Reserved + 0x9 + + + + + + + 6 + 0x18 + CS%sGCR2 + Chip Select n General Configuration Register 2 + 0x4 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + ADH + Address hold time - This bit field determine the address hold time after ADV negation when mum = 1 (muxed mode) + 0 + 2 + read-write + + + ADH_0 + 0 cycle after ADV negation + 0 + + + ADH_1 + 1 cycle after ADV negation + 0x1 + + + ADH_2 + 2 cycle after ADV negation + 0x2 + + + + + DAPS + Data Acknowledge Poling Start + 0x4 + 4 + read-write + + + DAPS_0 + 3 EIM clk cycle between start of access and first DTACK check + 0 + + + DAPS_1 + 4 EIM clk cycles between start of access and first DTACK check + 0x1 + + + DAPS_2 + 5 EIM clk cycles between start of access and first DTACK check + 0x2 + + + DAPS_7 + 10 EIM clk cycles between start of access and first DTACK check + 0x7 + + + DAPS_11 + 14 EIM clk cycles between start of access and first DTACK check + 0xB + + + DAPS_15 + 18 EIM clk cycles between start of access and first DTACK check + 0xF + + + + + DAE + Data Acknowledge Enable + 0x8 + 1 + read-write + + + DAE_0 + DTACK signal use is disable + 0 + + + DAE_1 + DTACK signal use is enable + 0x1 + + + + + DAP + Data Acknowledge Polarity + 0x9 + 1 + read-write + + + DAP_0 + DTACK signal is active high + 0 + + + DAP_1 + DTACK signal is active low + 0x1 + + + + + MUX16_BYP_GRANT + Muxed 16 bypass grant + 0xC + 1 + read-write + + + MUX16_BYP_GRANT_0 + EIM waits for grant before driving a 16 bit muxed mode access to the memory. + 0 + + + MUX16_BYP_GRANT_1 + EIM ignores the grant signal and immediately drives a 16 bit muxed mode access to the memory. + 0x1 + + + + + + + 6 + 0x18 + CS%sRCR1 + Chip Select n Read Configuration Register 1 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RCSN + Read CS Negation + 0 + 3 + read-write + + + RCSN_0 + 0 EIM clock cycles between end of read access and CS negation + 0 + + + RCSN_1 + 1 EIM clock cycles between end of read access and CS negation + 0x1 + + + RCSN_2 + 2 EIM clock cycles between end of read access and CS negation + 0x2 + + + RCSN_7 + 7 EIM clock cycles between end of read access and CS negation + 0x7 + + + + + RCSA + Read CS Assertion + 0x4 + 3 + read-write + + + RCSA_0 + 0 EIM clock cycles between beginning of read access and CS assertion + 0 + + + RCSA_1 + 1 EIM clock cycles between beginning of read access and CS assertion + 0x1 + + + RCSA_2 + 2 EIM clock cycles between beginning of read access and CS assertion + 0x2 + + + RCSA_7 + 7 EIM clock cycles between beginning of read access and CS assertion + 0x7 + + + + + OEN + OE Negation + 0x8 + 3 + read-write + + + OEN_0 + 0 EIM clock cycles between end of access and OE negation + 0 + + + OEN_1 + 1 EIM clock cycles between end of access and OE negation + 0x1 + + + OEN_2 + 2 EIM clock cycles between end of access and OE negation + 0x2 + + + OEN_7 + 7 EIM clock cycles between end of access and OE negation + 0x7 + + + + + OEA + OE Assertion + 0xC + 3 + read-write + + + OEA_0 + 0 EIM clock cycles between beginning of access and OE assertion + 0 + + + OEA_1 + 1 EIM clock cycles between beginning of access and OE assertion + 0x1 + + + OEA_2 + 2 EIM clock cycles between beginning of access and OE assertion + 0x2 + + + OEA_7 + 7 EIM clock cycles between beginning of access and OE assertion + 0x7 + + + + + RADVN + ADV Negation + 0x10 + 3 + read-write + + + RAL + Read ADV Low + 0x13 + 1 + read-write + + + RADVA + ADV Assertion + 0x14 + 3 + read-write + + + RADVA_0 + 0 EIM clock cycles between beginning of access and ADV assertion + 0 + + + RADVA_1 + 1 EIM clock cycles between beginning of access and ADV assertion + 0x1 + + + RADVA_2 + 2 EIM clock cycles between beginning of access and ADV assertion + 0x2 + + + RADVA_7 + 7 EIM clock cycles between beginning of access and ADV assertion + 0x7 + + + + + RWSC + Read Wait State Control + 0x18 + 6 + read-write + + + RWSC_1 + RWSC value is 1 + 0x1 + + + RWSC_2 + RWSC value is 2 + 0x2 + + + RWSC_61 + RWSC value is 61 + 0x3D + + + RWSC_62 + RWSC value is 62 + 0x3E + + + RWSC_63 + RWSC value is 63 + 0x3F + + + + + + + 6 + 0x18 + CS%sRCR2 + Chip Select n Read Configuration Register 2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RBEN + Read BE Negation + 0 + 3 + read-write + + + RBEN_0 + 0 EIM clock cycles between end of read access and BE negation + 0 + + + RBEN_1 + 1 EIM clock cycles between end of read access and BE negation + 0x1 + + + RBEN_2 + 2 EIM clock cycles between end of read access and BE negation + 0x2 + + + RBEN_7 + 7 EIM clock cycles between end of read access and BE negation + 0x7 + + + + + RBE + Read BE enable. This bit field determines if BE will be asserted during read access. + 0x3 + 1 + read-write + + + RBE_0 + - BE are disabled during read access. + 0 + + + + + RBEA + Read BE Assertion + 0x4 + 3 + read-write + + + RBEA_0 + 0 EIM clock cycles between beginning of read access and BE assertion + 0 + + + RBEA_1 + 1 EIM clock cycles between beginning of read access and BE assertion + 0x1 + + + RBEA_2 + 2 EIM clock cycles between beginning of read access and BE assertion + 0x2 + + + RBEA_7 + 7 EIM clock cycles between beginning of read access and BE assertion + 0x7 + + + + + RL + Read Latency + 0x8 + 2 + read-write + + + RL_0 + Feedback clock loop delay is up to 1 cycle for BCD = 0 or 1.5 cycles for BCD != 0 + 0 + + + RL_1 + Feedback clock loop delay is up to 2 cycles for BCD = 0 or 2.5 cycles for BCD != 0 + 0x1 + + + RL_2 + Feedback clock loop delay is up to 3 cycles for BCD = 0 or 3.5 cycles for BCD != 0 + 0x2 + + + RL_3 + Feedback clock loop delay is up to 4 cycles for BCD = 0 or 4.5 cycles for BCD != 0 + 0x3 + + + + + PAT + Page Access Time + 0xC + 3 + read-write + + + PAT_0 + Address width is 2 EIM clock cycles + 0 + + + PAT_1 + Address width is 3 EIM clock cycles + 0x1 + + + PAT_2 + Address width is 4 EIM clock cycles + 0x2 + + + PAT_3 + Address width is 5 EIM clock cycles + 0x3 + + + PAT_4 + Address width is 6 EIM clock cycles + 0x4 + + + PAT_5 + Address width is 7 EIM clock cycles + 0x5 + + + PAT_6 + Address width is 8 EIM clock cycles + 0x6 + + + PAT_7 + Address width is 9 EIM clock cycles + 0x7 + + + + + APR + Asynchronous Page Read + 0xF + 1 + read-write + + + + + 6 + 0x18 + CS%sWCR1 + Chip Select n Write Configuration Register 1 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + WCSN + Write CS Negation + 0 + 3 + read-write + + + WCSN_0 + 0 EIM clock cycles between end of read access and CS negation + 0 + + + WCSN_1 + 1 EIM clock cycles between end of read access and CS negation + 0x1 + + + WCSN_2 + 2 EIM clock cycles between end of read access and CS negation + 0x2 + + + WCSN_7 + 7 EIM clock cycles between end of read access and CS negation + 0x7 + + + + + WCSA + Write CS Assertion + 0x3 + 3 + read-write + + + WCSA_0 + 0 EIM clock cycles between beginning of write access and CS assertion + 0 + + + WCSA_1 + 1 EIM clock cycles between beginning of write access and CS assertion + 0x1 + + + WCSA_2 + 2 EIM clock cycles between beginning of write access and CS assertion + 0x2 + + + WCSA_7 + 7 EIMclock cycles between beginning of write access and CS assertion + 0x7 + + + + + WEN + WE Negation + 0x6 + 3 + read-write + + + WEN_0 + 0 EIM clock cycles between beginning of access and WE assertion + 0 + + + WEN_1 + 1 EIM clock cycles between beginning of access and WE assertion + 0x1 + + + WEN_2 + 2 EIM clock cycles between beginning of access and WE assertion + 0x2 + + + WEN_7 + 7 EIM clock cycles between beginning of access and WE assertion + 0x7 + + + + + WEA + WE Assertion + 0x9 + 3 + read-write + + + WEA_0 + 0 EIM clock cycles between beginning of access and WE assertion + 0 + + + WEA_1 + 1 EIM clock cycles between beginning of access and WE assertion + 0x1 + + + WEA_2 + 2 EIM clock cycles between beginning of access and WE assertion + 0x2 + + + WEA_7 + 7 EIMclock cycles between beginning of access and WE assertion + 0x7 + + + + + WBEN + BE[3:0] Negation + 0xC + 3 + read-write + + + WBEA + BE Assertion + 0xF + 3 + read-write + + + WBEA_0 + 0 EIM clock cycles between beginning of access and BE assertion + 0 + + + WBEA_1 + 1 EIM clock cycles between beginning of access and BE assertion + 0x1 + + + WBEA_2 + 2 EIM clock cycles between beginning of access and BE assertion + 0x2 + + + WBEA_7 + 7 EIM clock cycles between beginning of access and BE assertion + 0x7 + + + + + WADVN + ADV Negation + 0x12 + 3 + read-write + + + WADVA + ADV Assertion + 0x15 + 3 + read-write + + + WADVA_0 + 0 EIM clock cycles between beginning of access and ADV assertion + 0 + + + WADVA_1 + 1 EIM clock cycles between beginning of access and ADV assertion + 0x1 + + + WADVA_2 + 2 EIM clock cycles between beginning of access and ADV assertion + 0x2 + + + WADVA_7 + 7 EIM clock cycles between beginning of access and ADV assertion + 0x7 + + + + + WWSC + Write Wait State Control + 0x18 + 6 + read-write + + + WWSC_1 + WWSC value is 1 + 0x1 + + + WWSC_2 + WWSC value is 2 + 0x2 + + + WWSC_3 + WWSC value is 3 + 0x3 + + + WWSC_63 + WWSC value is 63 + 0x3F + + + + + WBED + Write Byte Enable Disable + 0x1E + 1 + read-write + + + WAL + Write ADV Low + 0x1F + 1 + read-write + + + + + 6 + 0x18 + CS%sWCR2 + Chip Select n Write Configuration Register 2 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WBCDD + Write Burst Clock Divisor Decrement + 0 + 1 + read-write + + + + + WCR + EIM Configuration Register + 0x90 + 32 + read-write + 0x20 + 0xFFFFFFFF + + + BCM + Burst Clock Mode + 0 + 1 + read-write + + + BCM_0 + The burst clock runs only when accessing a chip select range with the SWR/SRD bits set. When the burst clock is not running it remains in a logic 0 state. When the burst clock is running it is configured by the BCD and BCS bit fields in the chip select Configuration Register. + 0 + + + BCM_1 + The burst clock runs whenever ACLK is active (independent of chip select configuration) + 0x1 + + + + + GBCD + General Burst Clock Divisor + 0x1 + 2 + read-write + + + GBCD_0 + Divide EIM clock by 1 + 0 + + + GBCD_1 + Divide EIM clock by 2 + 0x1 + + + GBCD_2 + Divide EIM clock by 3 + 0x2 + + + GBCD_3 + Divide EIM clock by 4 + 0x3 + + + + + CONT_BCLK_SEL + Continuous BCLK select + 0x3 + 1 + read-write + + + CONT_BCLK_SEL_0 + BCLK When nesserary + 0 + + + CONT_BCLK_SEL_1 + BCLK Continuous + 0x1 + + + + + INTEN + Interrupt Enable + 0x4 + 1 + read-write + + + INTEN_0 + External interrupt Disable + 0 + + + INTEN_1 + External interrupt Enable + 0x1 + + + + + INTPOL + Interrupt Polarity. This bit field determines the polarity of the external device interrupt. + 0x5 + 1 + read-write + + + INTPOL_0 + External interrupt polarity is active low + 0 + + + INTPOL_1 + External interrupt polarity is active high + 0x1 + + + + + WDOG_EN + Memory WDOG enable + 0x8 + 1 + read-write + + + WDOG_EN_0 + Memory WDOG is Disabled + 0 + + + WDOG_EN_1 + Memory WDOG is Enabled + 0x1 + + + + + WDOG_LIMIT + Memory Watchdog (WDOG) cycle limit + 0x9 + 2 + read-write + + + WDOG_LIMIT_0 + 128 BCLK cycles + 0 + + + WDOG_LIMIT_1 + 256 BCLK cycles + 0x1 + + + WDOG_LIMIT_2 + 512 BCLK cycles + 0x2 + + + WDOG_LIMIT_3 + 1024 BCLK cycles + 0x3 + + + + + FRUN_ACLK_EN + Free run ACLK enable + 0xB + 1 + read-write + + + + + + + OCOTP + OCOTP Register Reference Index + OCOTP + OCOTP_ + 0x21BC000 + + 0 + 0x8F4 + registers + + + + CTRL + OTP Controller Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + + + RSVD0 + Reserved + 0x6 + 2 + read-only + + + BUSY + OTP controller status bit + 0x8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 0x9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 0xA + 1 + read-write + + + CRC_TEST + Set to calculate CRC according to start address and end address in CRC_ADDR register + 0xB + 1 + read-write + + + CRC_FAIL + Set by controller when calculated CRC value is not equal to appointed CRC fuse word + 0xC + 1 + read-write + + + RSVD1 + Reserved + 0xD + 3 + read-only + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 0x10 + 16 + read-write + + + KEY + Key needed to unlock HW_OCOTP_DATA register. + 0x3E77 + + + + + + + CTRL_SET + OTP Controller Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + + + RSVD0 + Reserved + 0x6 + 2 + read-only + + + BUSY + OTP controller status bit + 0x8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 0x9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 0xA + 1 + read-write + + + CRC_TEST + Set to calculate CRC according to start address and end address in CRC_ADDR register + 0xB + 1 + read-write + + + CRC_FAIL + Set by controller when calculated CRC value is not equal to appointed CRC fuse word + 0xC + 1 + read-write + + + RSVD1 + Reserved + 0xD + 3 + read-only + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 0x10 + 16 + read-write + + + KEY + Key needed to unlock HW_OCOTP_DATA register. + 0x3E77 + + + + + + + CTRL_CLR + OTP Controller Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + + + RSVD0 + Reserved + 0x6 + 2 + read-only + + + BUSY + OTP controller status bit + 0x8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 0x9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 0xA + 1 + read-write + + + CRC_TEST + Set to calculate CRC according to start address and end address in CRC_ADDR register + 0xB + 1 + read-write + + + CRC_FAIL + Set by controller when calculated CRC value is not equal to appointed CRC fuse word + 0xC + 1 + read-write + + + RSVD1 + Reserved + 0xD + 3 + read-only + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 0x10 + 16 + read-write + + + KEY + Key needed to unlock HW_OCOTP_DATA register. + 0x3E77 + + + + + + + CTRL_TOG + OTP Controller Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + + + RSVD0 + Reserved + 0x6 + 2 + read-only + + + BUSY + OTP controller status bit + 0x8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 0x9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 0xA + 1 + read-write + + + CRC_TEST + Set to calculate CRC according to start address and end address in CRC_ADDR register + 0xB + 1 + read-write + + + CRC_FAIL + Set by controller when calculated CRC value is not equal to appointed CRC fuse word + 0xC + 1 + read-write + + + RSVD1 + Reserved + 0xD + 3 + read-only + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 0x10 + 16 + read-write + + + KEY + Key needed to unlock HW_OCOTP_DATA register. + 0x3E77 + + + + + + + TIMING + OTP Controller Timing Register + 0x10 + 32 + read-write + 0x2C64116 + 0xFFFFFFFF + + + STROBE_PROG + This count value specifies the strobe period in one time write OTP + 0 + 12 + read-write + + + RELAX + This count value specifies the time to add to all default timing parameters other than the Tpgm and Trd + 0xC + 4 + read-write + + + STROBE_READ + This count value specifies the strobe period in one time read OTP + 0x10 + 6 + read-write + + + WAIT + This count value specifies time interval between auto read and write access in one time program + 0x16 + 6 + read-write + + + RSRVD0 + These bits always read back zero. + 0x1C + 4 + read-only + + + + + DATA + OTP Controller Write Data Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Used to initiate a write to OTP + 0 + 32 + read-write + + + + + READ_CTRL + OTP Controller Write Data Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + READ_FUSE + Used to initiate a read to OTP + 0 + 1 + read-write + + + RSVD0 + Reserved + 0x1 + 31 + read-only + + + + + READ_FUSE_DATA + OTP Controller Read Data Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + The data read from OTP + 0 + 32 + read-write + + + + + SW_STICKY + Sticky bit Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRK_REVOKE_LOCK + Shadow register write and OTP write lock for SRK_REVOKE region + 0x1 + 1 + read-write + + + FIELD_RETURN_LOCK + Shadow register write and OTP write lock for FIELD_RETURN region + 0x2 + 1 + read-write + + + RSVD0 + Reserved + 0x5 + 27 + read-only + + + + + SCS + Software Controllable Signals Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 0x1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 0x1F + 1 + read-write + + + + + SCS_SET + Software Controllable Signals Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 0x1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 0x1F + 1 + read-write + + + + + SCS_CLR + Software Controllable Signals Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 0x1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 0x1F + 1 + read-write + + + + + SCS_TOG + Software Controllable Signals Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 0x1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 0x1F + 1 + read-write + + + + + CRC_ADDR + OTP Controller CRC test address + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_START_ADDR + End address of fuse location for CRC calculation + 0 + 8 + read-write + + + DATA_END_ADDR + Start address of fuse location for CRC calculation + 0x8 + 8 + read-write + + + CRC_ADDR + Address of 32-bit CRC result for comparing + 0x10 + 3 + read-write + + + OTPMK_CRC + Enable bit for CRC32 calculation address When OTPMK_CRC_ADDR_OTPMK_CRC bit sets to 1, calculation address sets to OTPMK_CRC (recommend) + 0x13 + 1 + read-write + + + RSVD0 + Reserved + 0x14 + 12 + read-only + + + + + CRC_VALUE + OTP Controller CRC Value Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + The crc32 value based on CRC_ADDR + 0 + 32 + read-write + + + + + VERSION + OTP Controller Version Register + 0x90 + 32 + read-only + 0x3000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 0x18 + 8 + read-only + + + + + TIMING2 + OTP Controller Timing Register 2 + 0x100 + 32 + read-write + 0x1C10042 + 0xFFFFFFFF + + + RELAX_PROG + This count value specifies the time to add to write OTP for complement address enable time. + 0 + 12 + read-write + + + RELAX_READ + This count value specifies the time to add to read OTP for complement address enable cycle time. + 0x10 + 6 + read-write + + + RELAX1 + Not used, preserved + 0x16 + 7 + read-write + + + + + LOCK + Value of OTP Bank0 Word0 (Lock controls) + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TESTER + Status of shadow register and OTP write lock for tester region + 0 + 2 + read-only + + + BOOT_CFG + Status of shadow register and OTP write lock for boot_cfg region + 0x2 + 2 + read-only + + + MEM_TRIM + Status of shadow register and OTP write lock for mem_trim region + 0x4 + 2 + read-only + + + SJC_RESP + Status of shadow register read and write, OTP read and write lock for sjc_resp region + 0x6 + 1 + read-only + + + RSVD0 + Reserved + 0x7 + 1 + read-only + + + MAC_ADDR + Status of shadow register and OTP write lock for mac_addr region + 0x8 + 2 + read-only + + + GP1 + Status of shadow register and OTP write lock for gp2 region + 0xA + 2 + read-only + + + GP2 + Status of shadow register and OTP write lock for gp2 region + 0xC + 2 + read-only + + + SRK + Status of shadow register and OTP write lock for srk region + 0xE + 1 + read-only + + + GP3 + Status of shadow register and OTP write lock for GP3 region + 0xF + 1 + read-only + + + SW_GP + Status of shadow register and OTP write lock for SW_GP region + 0x10 + 1 + read-only + + + OTPMK + Status of shadow register and OTP write lock for OTPMK region + 0x11 + 1 + read-only + + + ANALOG + Status of shadow register and OTP write lock for analog region + 0x12 + 2 + read-only + + + OTPMK_CRC + Status of shadow register and OTP write lock for otpmk crc region + 0x14 + 1 + read-only + + + ROM_PATCH + Status of shadow register and OTP write lock for rom_patch region + 0x15 + 1 + read-only + + + MISC_CONF + Status of shadow register and OTP write lock for misc_conf region + 0x16 + 1 + read-only + + + GP4 + Status of shadow register and OTP write lock for GP4 region + 0x17 + 1 + read-only + + + PIN + Status of Pin access lock bit. When set, pin access is disabled. + 0x19 + 1 + read-only + + + GP4_RLOCK + Status of shadow register and OTP read lock for GP4 region + 0x1E + 1 + read-write + + + GP3_RLOCK + Status of shadow register and OTP read lock for GP3 region + 0x1F + 1 + read-only + + + + + CFG0 + Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + This register contains 32 bits of the Unique ID and SJC_CHALLENGE field + 0 + 32 + read-write + + + + + CFG1 + Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + This register contains 32 bits of the Unique ID and SJC_CHALLENGE field + 0 + 32 + read-write + + + + + CFG2 + Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 3 (ADDR = 0x03) + 0 + 32 + read-write + + + + + CFG3 + Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 4 (ADDR = 0x04) + 0 + 32 + read-write + + + + + CFG4 + Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 5 (ADDR = 0x05) + 0 + 32 + read-write + + + + + CFG5 + Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 6 (ADDR = 0x06) + 0 + 32 + read-write + + + + + CFG6 + Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 7 (ADDR = 0x07) + 0 + 32 + read-write + + + + + MEM0 + Value of OTP Bank1 Word0 (Memory Related Info.) + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 0 (ADDR = 0x08) + 0 + 32 + read-write + + + + + MEM1 + Value of OTP Bank1 Word1 (Memory Related Info.) + 0x490 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 1 (ADDR = 0x09) + 0 + 32 + read-write + + + + + MEM2 + Value of OTP Bank1 Word2 (Memory Related Info.) + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 2 (ADDR = 0x0A) + 0 + 32 + read-write + + + + + MEM3 + Value of OTP Bank1 Word3 (Memory Related Info.) + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 3 (ADDR = 0x0B) + 0 + 32 + read-write + + + + + MEM4 + Value of OTP Bank1 Word4 (Memory Related Info.) + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 4 (ADDR = 0x0C) + 0 + 32 + read-write + + + + + ANA0 + Value of OTP Bank1 Word5 (Memory Related Info.) + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 5 (ADDR = 0x0D) + 0 + 32 + read-write + + + + + ANA1 + Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 6 (ADDR = 0x0E) + 0 + 32 + read-write + + + + + ANA2 + Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 7 (ADDR = 0x0F) + 0 + 32 + read-write + + + + + OTPMK0 + Value of OTP Bank2 Word0 (OTPMK Key) + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 0 (ADDR = 0x10)) + 0 + 32 + read-write + + + + + OTPMK1 + Value of OTP Bank2 Word1 (OTPMK Key) + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 1 (ADDR = 0x11)) + 0 + 32 + read-write + + + + + OTPMK2 + Value of OTP Bank2 Word2 (OTPMK Key) + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 2 (ADDR = 0x12)) + 0 + 32 + read-write + + + + + OTPMK3 + Value of OTP Bank2 Word3 (OTPMK Key) + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 3 (ADDR = 0x13)) + 0 + 32 + read-write + + + + + OTPMK4 + Value of OTP Bank2 Word4 (OTPMK Key) + 0x540 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 4 (ADDR = 0x14)) + 0 + 32 + read-write + + + + + OTPMK5 + Value of OTP Bank2 Word5 (OTPMK Key) + 0x550 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 4 (ADDR = 0x14)) + 0 + 32 + read-write + + + + + OTPMK6 + Value of OTP Bank2 Word6 (OTPMK Key) + 0x560 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 6 (ADDR = 0x16)) + 0 + 32 + read-write + + + + + OTPMK7 + Value of OTP Bank2 Word7 (OTPMK Key) + 0x570 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the OTPMK Key word0 (Copy of OTP Bank 2, word 7 (ADDR = 0x17)) + 0 + 32 + read-write + + + + + SRK0 + Shadow Register for OTP Bank3 Word0 (SRK Hash) + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word0 (Copy of OTP Bank 3, word 0 (ADDR = 0x18)) + 0 + 32 + read-write + + + + + SRK1 + Shadow Register for OTP Bank3 Word1 (SRK Hash) + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word1 (Copy of OTP Bank 3, word 1 (ADDR = 0x19)) + 0 + 32 + read-write + + + + + SRK2 + Shadow Register for OTP Bank3 Word2 (SRK Hash) + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word2 (Copy of OTP Bank 3, word 2 (ADDR = 0x1A)) + 0 + 32 + read-write + + + + + SRK3 + Shadow Register for OTP Bank3 Word3 (SRK Hash) + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word3 (Copy of OTP Bank 3, word 3 (ADDR = 0x1B)) + 0 + 32 + read-write + + + + + SRK4 + Shadow Register for OTP Bank3 Word4 (SRK Hash) + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word4 (Copy of OTP Bank 3, word 4 (ADDR = 0x1C)) + 0 + 32 + read-write + + + + + SRK5 + Shadow Register for OTP Bank3 Word5 (SRK Hash) + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word5 (Copy of OTP Bank 3, word 5 (ADDR = 0x1D)) + 0 + 32 + read-write + + + + + SRK6 + Shadow Register for OTP Bank3 Word6 (SRK Hash) + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word6 (Copy of OTP Bank 3, word 6 (ADDR = 0x1E)) + 0 + 32 + read-write + + + + + SRK7 + Shadow Register for OTP Bank3 Word7 (SRK Hash) + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word7 (Copy of OTP Bank 3, word 7 (ADDR = 0x1F)) + 0 + 32 + read-write + + + + + SJC_RESP0 + Value of OTP Bank4 Word0 (Secure JTAG Response Field) + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 4, word 0 (ADDR = 0x20)) + 0 + 32 + read-write + + + + + SJC_RESP1 + Value of OTP Bank4 Word1 (Secure JTAG Response Field) + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 4, word 1 (ADDR = 0x21)) + 0 + 32 + read-write + + + + + MAC0 + Value of OTP Bank4 Word2 (MAC Address) + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 2 (ADDR = 0x22). + 0 + 32 + read-write + + + + + MAC1 + Value of OTP Bank4 Word3 (MAC Address) + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 3 (ADDR = 0x23). + 0 + 32 + read-write + + + + + MAC + Value of OTP Bank4 Word4 (MAC Address) (OCOTP_RESERVED) + 0x640 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 4 (ADDR = 0x24). + 0 + 32 + read-write + + + + + CRC + Value of OTP Bank4 Word5 (CRC Key) + 0x650 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 5 (ADDR = 0x25). + 0 + 32 + read-write + + + + + GP1 + Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) + 0x660 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 6 (ADDR = 0x26). + 0 + 32 + read-write + + + + + GP2 + Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) + 0x670 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 7 (ADDR = 0x27). + 0 + 32 + read-write + + + + + SW_GP0 + Value of OTP Bank5 Word0 (SW GP) + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 0 (ADDR = 0x28). + 0 + 32 + read-write + + + + + SW_GP1 + Value of OTP Bank5 Word1 (SW GP) + 0x690 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 1 (ADDR = 0x29). + 0 + 32 + read-write + + + + + SW_GP2 + Value of OTP Bank5 Word2 (SW GP) + 0x6A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 2 (ADDR = 0x2a). + 0 + 32 + read-write + + + + + SW_GP3 + Value of OTP Bank5 Word3 (SW GP) + 0x6B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 3 (ADDR = 0x2b). + 0 + 32 + read-write + + + + + SW_GP4 + Value of OTP Bank5 Word4 (SW GP) + 0x6C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 4 (ADDR = 0x2c). + 0 + 32 + read-write + + + + + MISC_CONF + Value of OTP Bank5 Word5 (Misc Conf) + 0x6D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 5 (ADDR = 0x2d). + 0 + 32 + read-write + + + + + FIELD_RETURN + Value of OTP Bank5 Word6 (Field Return) + 0x6E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 6 (ADDR = 0x2e). + 0 + 32 + read-write + + + + + SRK_REVOKE + Value of OTP Bank5 Word7 (SRK Revoke) + 0x6F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 7 (ADDR = 0x2f). + 0 + 32 + read-write + + + + + ROM_PATCH0 + Value of OTP Bank6 Word0 (ROM Patch) + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 0 (ADDR = 0x30). + 0 + 32 + read-write + + + + + ROM_PATCH1 + Value of OTP Bank6 Word1 (ROM Patch) + 0x810 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 1 (ADDR = 0x31). + 0 + 32 + read-write + + + + + ROM_PATCH2 + Value of OTP Bank6 Word2 (ROM Patch) + 0x820 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 2 (ADDR = 0x32). + 0 + 32 + read-write + + + + + ROM_PATCH3 + Value of OTP Bank6 Word3 (ROM Patch) + 0x830 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 3 (ADDR = 0x33). + 0 + 32 + read-write + + + + + ROM_PATCH4 + Value of OTP Bank6 Word4 (ROM Patch) + 0x840 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 4 (ADDR = 0x34). + 0 + 32 + read-write + + + + + ROM_PATCH5 + Value of OTP Bank6 Word5 (ROM Patch) + 0x850 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 5 (ADDR = 0x35). + 0 + 32 + read-write + + + + + ROM_PATCH6 + Value of OTP Bank6 Word6 (ROM Patch) + 0x860 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 6 (ADDR = 0x36). + 0 + 32 + read-write + + + + + ROM_PATCH7 + Value of OTP Bank6 Word7 (ROM Patch) + 0x870 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 6, word 7 (ADDR = 0x37). + 0 + 32 + read-write + + + + + GP3_0 + Value of OTP Bank7 Word0 (General Purpose Customer Defined Info) + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 0 (ADDR = 0x40). + 0 + 32 + read-write + + + + + GP3_1 + Value of OTP Bank7 Word1 (General Purpose Customer Defined Info) + 0x890 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 1 (ADDR = 0x41). + 0 + 32 + read-write + + + + + GP3_2 + Value of OTP Bank7 Word2 (General Purpose Customer Defined Info) + 0x8A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 2 (ADDR = 0x42). + 0 + 32 + read-write + + + + + GP3_3 + Value of OTP Bank7 Word3 (General Purpose Customer Defined Info) + 0x8B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 3 (ADDR = 0x43). + 0 + 32 + read-write + + + + + GP3_4 + Value of OTP Bank8 Word4 (General Purpose Customer Defined Info) + 0x8C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 4 (ADDR = 0x44). + 0 + 32 + read-write + + + + + GP4_0 + Value of OTP Bank7 Word5 (General Purpose Customer Defined Info) + 0x8D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 5 (ADDR = 0x45). + 0 + 32 + read-write + + + + + GP4_1 + Value of OTP Bank7 Word6 (General Purpose Customer Defined Info) + 0x8E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 6 (ADDR = 0x46). + 0 + 32 + read-write + + + + + GP4_2 + Value of OTP Bank7 Word7 (General Purpose Customer Defined Info) + 0x8F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 8, word 7 (ADDR = 0x47). + 0 + 32 + read-write + + + + + + + CSI + CSI + CSI + CSI_ + 0x21C4000 + + 0 + 0x50 + registers + + + CSI + 39 + + + + CSICR1 + CSI Control Register 1 + 0 + 32 + read-write + 0x40000800 + 0xFFFFFFFF + + + PIXEL_BIT + Pixel Bit + 0 + 1 + read-write + + + PIXEL_BIT_0 + 8-bit data for each pixel + 0 + + + PIXEL_BIT_1 + 10-bit data for each pixel + 0x1 + + + + + REDGE + Valid Pixel Clock Edge Select + 0x1 + 1 + read-write + + + REDGE_0 + Pixel data is latched at the falling edge of CSI_PIXCLK + 0 + + + REDGE_1 + Pixel data is latched at the rising edge of CSI_PIXCLK + 0x1 + + + + + INV_PCLK + Invert Pixel Clock Input + 0x2 + 1 + read-write + + + INV_PCLK_0 + CSI_PIXCLK is directly applied to internal circuitry + 0 + + + INV_PCLK_1 + CSI_PIXCLK is inverted before applied to internal circuitry + 0x1 + + + + + INV_DATA + Invert Data Input. This bit enables or disables internal inverters on the data lines. + 0x3 + 1 + read-write + + + INV_DATA_0 + CSI_D[7:0] data lines are directly applied to internal circuitry + 0 + + + INV_DATA_1 + CSI_D[7:0] data lines are inverted before applied to internal circuitry + 0x1 + + + + + GCLK_MODE + Gated Clock Mode Enable + 0x4 + 1 + read-write + + + GCLK_MODE_0 + Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. + 0 + + + GCLK_MODE_1 + Gated clock mode. Pixel clock signal is valid only when HSYNC is active. + 0x1 + + + + + CLR_RXFIFO + Asynchronous RXFIFO Clear + 0x5 + 1 + read-write + + + CLR_STATFIFO + Asynchronous STATFIFO Clear + 0x6 + 1 + read-write + + + PACK_DIR + Data Packing Direction + 0x7 + 1 + read-write + + + PACK_DIR_0 + Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. + 0 + + + PACK_DIR_1 + Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO. + 0x1 + + + + + FCC + FIFO Clear Control + 0x8 + 1 + read-write + + + FCC_0 + Asynchronous FIFO clear is selected. + 0 + + + FCC_1 + Synchronous FIFO clear is selected. + 0x1 + + + + + CCIR_EN + CCIR656 Interface Enable + 0xA + 1 + read-write + + + CCIR_EN_0 + Traditional interface is selected. Timing interface logic is used to latch data. + 0 + + + CCIR_EN_1 + CCIR656 interface is selected. + 0x1 + + + + + HSYNC_POL + HSYNC Polarity Select + 0xB + 1 + read-write + + + HSYNC_POL_0 + HSYNC is active low + 0 + + + HSYNC_POL_1 + HSYNC is active high + 0x1 + + + + + SOF_INTEN + Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. + 0x10 + 1 + read-write + + + SOF_INTEN_0 + SOF interrupt disable + 0 + + + SOF_INTEN_1 + SOF interrupt enable + 0x1 + + + + + SOF_POL + SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. + 0x11 + 1 + read-write + + + SOF_POL_0 + SOF interrupt is generated on SOF falling edge + 0 + + + SOF_POL_1 + SOF interrupt is generated on SOF rising edge + 0x1 + + + + + RXFF_INTEN + RxFIFO Full Interrupt Enable. This bit enables the RxFIFO full interrupt. + 0x12 + 1 + read-write + + + RXFF_INTEN_0 + RxFIFO full interrupt disable + 0 + + + RXFF_INTEN_1 + RxFIFO full interrupt enable + 0x1 + + + + + FB1_DMA_DONE_INTEN + Frame Buffer1 DMA Transfer Done Interrupt Enable + 0x13 + 1 + read-write + + + FB1_DMA_DONE_INTEN_0 + Frame Buffer1 DMA Transfer Done interrupt disable + 0 + + + FB1_DMA_DONE_INTEN_1 + Frame Buffer1 DMA Transfer Done interrupt enable + 0x1 + + + + + FB2_DMA_DONE_INTEN + Frame Buffer2 DMA Transfer Done Interrupt Enable + 0x14 + 1 + read-write + + + FB2_DMA_DONE_INTEN_0 + Frame Buffer2 DMA Transfer Done interrupt disable + 0 + + + FB2_DMA_DONE_INTEN_1 + Frame Buffer2 DMA Transfer Done interrupt enable + 0x1 + + + + + STATFF_INTEN + STATFIFO Full Interrupt Enable. This bit enables the STAT FIFO interrupt. + 0x15 + 1 + read-write + + + STATFF_INTEN_0 + STATFIFO full interrupt disable + 0 + + + STATFF_INTEN_1 + STATFIFO full interrupt enable + 0x1 + + + + + SFF_DMA_DONE_INTEN + STATFIFO DMA Transfer Done Interrupt Enable + 0x16 + 1 + read-write + + + SFF_DMA_DONE_INTEN_0 + STATFIFO DMA Transfer Done interrupt disable + 0 + + + SFF_DMA_DONE_INTEN_1 + STATFIFO DMA Transfer Done interrupt enable + 0x1 + + + + + RF_OR_INTEN + RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. + 0x18 + 1 + read-write + + + RF_OR_INTEN_0 + RxFIFO overrun interrupt is disabled + 0 + + + RF_OR_INTEN_1 + RxFIFO overrun interrupt is enabled + 0x1 + + + + + SF_OR_INTEN + STAT FIFO Overrun Interrupt Enable. This bit enables the STATFIFO overrun interrupt. + 0x19 + 1 + read-write + + + SF_OR_INTEN_0 + STATFIFO overrun interrupt is disabled + 0 + + + SF_OR_INTEN_1 + STATFIFO overrun interrupt is enabled + 0x1 + + + + + COF_INT_EN + Change Of Image Field (COF) Interrupt Enable + 0x1A + 1 + read-write + + + COF_INT_EN_0 + COF interrupt is disabled + 0 + + + COF_INT_EN_1 + COF interrupt is enabled + 0x1 + + + + + VIDEO_MODE + Video mode select. This bit controls the video mode in CCIR mode and TV decoder input. + 0x1B + 1 + read-write + + + VIDEO_MODE_0 + Progressive mode is selected + 0 + + + VIDEO_MODE_1 + Interlace mode is selected + 0x1 + + + + + PrP_IF_EN + CSI-PrP Interface Enable + 0x1C + 1 + read-write + + + PrP_IF_EN_0 + CSI to PrP bus is disabled + 0 + + + PrP_IF_EN_1 + CSI to PrP bus is enabled + 0x1 + + + + + EOF_INT_EN + End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. + 0x1D + 1 + read-write + + + EOF_INT_EN_0 + EOF interrupt is disabled. + 0 + + + EOF_INT_EN_1 + EOF interrupt is generated when RX count value is reached. + 0x1 + + + + + EXT_VSYNC + External VSYNC Enable + 0x1E + 1 + read-write + + + EXT_VSYNC_0 + Internal VSYNC mode + 0 + + + EXT_VSYNC_1 + External VSYNC mode + 0x1 + + + + + SWAP16_EN + SWAP 16-Bit Enable + 0x1F + 1 + read-write + + + SWAP16_EN_0 + Disable swapping + 0 + + + SWAP16_EN_1 + Enable swapping + 0x1 + + + + + + + CSICR2 + CSI Control Register 2 + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + HSC + Horizontal Skip Count + 0 + 8 + read-write + + + VSC + Vertical Skip Count. Contains the number of rows to skip. SCE must be 1, otherwise VSC is ignored. + 0x8 + 8 + read-write + + + LVRM + Live View Resolution Mode. Selects the grid size used for live view resolution. + 0x10 + 3 + read-write + + + LVRM_0 + 512 x 384 + 0 + + + LVRM_1 + 448 x 336 + 0x1 + + + LVRM_2 + 384 x 288 + 0x2 + + + LVRM_3 + 384 x 256 + 0x3 + + + LVRM_4 + 320 x 240 + 0x4 + + + LVRM_5 + 288 x 216 + 0x5 + + + LVRM_6 + 400 x 300 + 0x6 + + + + + BTS + Bayer Tile Start. Controls the Bayer pattern starting point. + 0x13 + 2 + read-write + + + BTS_0 + GR + 0 + + + BTS_1 + RG + 0x1 + + + BTS_2 + BG + 0x2 + + + BTS_3 + GB + 0x3 + + + + + SCE + Skip Count Enable. Enables or disables the skip count feature. + 0x17 + 1 + read-write + + + SCE_0 + Skip count disable + 0 + + + SCE_1 + Skip count enable + 0x1 + + + + + AFS + Auto Focus Spread. Selects which green pixels are used for auto-focus. + 0x18 + 2 + read-write + + + AFS_0 + Abs Diff on consecutive green pixels + 0 + + + AFS_1 + Abs Diff on every third green pixels + 0x1 + + + + + DRM + Double Resolution Mode. Controls size of statistics grid. + 0x1A + 1 + read-write + + + DRM_0 + Stats grid of 8 x 6 + 0 + + + DRM_1 + Stats grid of 8 x 12 + 0x1 + + + + + DMA_BURST_TYPE_SFF + Burst Type of DMA Transfer from STATFIFO. Selects the burst type of DMA transfer from STATFIFO. + 0x1C + 2 + read-write + + + DMA_BURST_TYPE_SFF_1 + INCR4 + 0x1 + + + DMA_BURST_TYPE_SFF_3 + INCR16 + 0x3 + + + + + DMA_BURST_TYPE_RFF + Burst Type of DMA Transfer from RxFIFO. Selects the burst type of DMA transfer from RxFIFO. + 0x1E + 2 + read-write + + + DMA_BURST_TYPE_RFF_1 + INCR4 + 0x1 + + + DMA_BURST_TYPE_RFF_3 + INCR16 + 0x3 + + + + + + + CSICR3 + CSI Control Register 3 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ECC_AUTO_EN + Automatic Error Correction Enable + 0 + 1 + read-write + + + ECC_AUTO_EN_0 + Auto Error correction is disabled. + 0 + + + ECC_AUTO_EN_1 + Auto Error correction is enabled. + 0x1 + + + + + ECC_INT_EN + Error Detection Interrupt Enable + 0x1 + 1 + read-write + + + ECC_INT_EN_0 + No interrupt is generated when error is detected. Only the status bit ECC_INT is set. + 0 + + + ECC_INT_EN_1 + Interrupt is generated when error is detected. + 0x1 + + + + + ZERO_PACK_EN + Dummy Zero Packing Enable + 0x2 + 1 + read-write + + + ZERO_PACK_EN_0 + Zero packing disabled + 0 + + + ZERO_PACK_EN_1 + Zero packing enabled + 0x1 + + + + + TWO_8BIT_SENSOR + Two 8-bit Sensor Mode + 0x3 + 1 + read-write + + + TWO_8BIT_SENSOR_0 + Only one sensor is connected. + 0 + + + TWO_8BIT_SENSOR_1 + Two 8-bit sensors are connected or one 16-bit sensor is connected. + 0x1 + + + + + RxFF_LEVEL + RxFIFO Full Level + 0x4 + 3 + read-write + + + RxFF_LEVEL_0 + 4 Words + 0 + + + RxFF_LEVEL_1 + 8 Words + 0x1 + + + RxFF_LEVEL_2 + 16 Words + 0x2 + + + RxFF_LEVEL_3 + 24 Words + 0x3 + + + RxFF_LEVEL_4 + 32 Words + 0x4 + + + RxFF_LEVEL_5 + 48 Words + 0x5 + + + RxFF_LEVEL_6 + 64 Words + 0x6 + + + RxFF_LEVEL_7 + 96 Words + 0x7 + + + + + HRESP_ERR_EN + Hresponse Error Enable. This bit enables the hresponse error interrupt. + 0x7 + 1 + read-write + + + HRESP_ERR_EN_0 + Disable hresponse error interrupt + 0 + + + HRESP_ERR_EN_1 + Enable hresponse error interrupt + 0x1 + + + + + STATFF_LEVEL + STATFIFO Full Level + 0x8 + 3 + read-write + + + STATFF_LEVEL_0 + 4 Words + 0 + + + STATFF_LEVEL_1 + 8 Words + 0x1 + + + STATFF_LEVEL_2 + 12 Words + 0x2 + + + STATFF_LEVEL_3 + 16 Words + 0x3 + + + STATFF_LEVEL_4 + 24 Words + 0x4 + + + STATFF_LEVEL_5 + 32 Words + 0x5 + + + STATFF_LEVEL_6 + 48 Words + 0x6 + + + STATFF_LEVEL_7 + 64 Words + 0x7 + + + + + DMA_REQ_EN_SFF + DMA Request Enable for STATFIFO + 0xB + 1 + read-write + + + DMA_REQ_EN_SFF_0 + Disable the dma request + 0 + + + DMA_REQ_EN_SFF_1 + Enable the dma request + 0x1 + + + + + DMA_REQ_EN_RFF + DMA Request Enable for RxFIFO + 0xC + 1 + read-write + + + DMA_REQ_EN_RFF_0 + Disable the dma request + 0 + + + DMA_REQ_EN_RFF_1 + Enable the dma request + 0x1 + + + + + DMA_REFLASH_SFF + Reflash DMA Controller for STATFIFO + 0xD + 1 + read-write + + + DMA_REFLASH_SFF_0 + No reflashing + 0 + + + DMA_REFLASH_SFF_1 + Reflash the embedded DMA controller + 0x1 + + + + + DMA_REFLASH_RFF + Reflash DMA Controller for RxFIFO + 0xE + 1 + read-write + + + DMA_REFLASH_RFF_0 + No reflashing + 0 + + + DMA_REFLASH_RFF_1 + Reflash the embedded DMA controller + 0x1 + + + + + FRMCNT_RST + Frame Count Reset. Resets the Frame Counter. (Cleared automatically after reset is done) + 0xF + 1 + read-write + + + FRMCNT_RST_0 + Do not reset + 0 + + + FRMCNT_RST_1 + Reset frame counter immediately + 0x1 + + + + + FRMCNT + Frame Counter + 0x10 + 16 + read-write + + + + + CSISTATFIFO + CSI Statistic FIFO Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + STAT + Static data from sensor + 0 + 32 + read-only + + + + + CSIRFIFO + CSI RX FIFO Register + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + IMAGE + Received image data + 0 + 32 + read-only + + + + + CSIRXCNT + CSI RX Count Register + 0x14 + 32 + read-write + 0x9600 + 0xFFFFFFFF + + + RXCNT + RxFIFO Count + 0 + 22 + read-write + + + + + CSISR + CSI Status Register + 0x18 + 32 + read-write + 0x4000 + 0xFFFFFFFF + + + DRDY + RXFIFO Data Ready + 0 + 1 + read-write + + + DRDY_0 + No data (word) is ready + 0 + + + DRDY_1 + At least 1 datum (word) is ready in RXFIFO. + 0x1 + + + + + ECC_INT + CCIR Error Interrupt + 0x1 + 1 + read-write + + + ECC_INT_0 + No error detected + 0 + + + ECC_INT_1 + Error is detected in CCIR coding + 0x1 + + + + + HRESP_ERR_INT + Hresponse Error Interrupt Status + 0x7 + 1 + read-write + + + HRESP_ERR_INT_0 + No hresponse error. + 0 + + + HRESP_ERR_INT_1 + Hresponse error is detected. + 0x1 + + + + + COF_INT + Change Of Field Interrupt Status + 0xD + 1 + read-write + + + COF_INT_0 + Video field has no change. + 0 + + + COF_INT_1 + Change of video field is detected. + 0x1 + + + + + F1_INT + CCIR Field 1 Interrupt Status + 0xE + 1 + read-write + + + F1_INT_0 + Field 1 of video is not detected. + 0 + + + F1_INT_1 + Field 1 of video is about to start. + 0x1 + + + + + F2_INT + CCIR Field 2 Interrupt Status + 0xF + 1 + read-write + + + F2_INT_0 + Field 2 of video is not detected + 0 + + + F2_INT_1 + Field 2 of video is about to start + 0x1 + + + + + SOF_INT + Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) + 0x10 + 1 + read-write + + + SOF_INT_0 + SOF is not detected. + 0 + + + SOF_INT_1 + SOF is detected. + 0x1 + + + + + EOF_INT + End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) + 0x11 + 1 + read-write + + + EOF_INT_0 + EOF is not detected. + 0 + + + EOF_INT_1 + EOF is detected. + 0x1 + + + + + RxFF_INT + RXFIFO Full Interrupt Status + 0x12 + 1 + read-write + + + RxFF_INT_0 + RxFIFO is not full. + 0 + + + RxFF_INT_1 + RxFIFO is full. + 0x1 + + + + + DMA_TSF_DONE_FB1 + DMA Transfer Done in Frame Buffer1 + 0x13 + 1 + read-write + + + DMA_TSF_DONE_FB1_0 + DMA transfer is not completed. + 0 + + + DMA_TSF_DONE_FB1_1 + DMA transfer is completed. + 0x1 + + + + + DMA_TSF_DONE_FB2 + DMA Transfer Done in Frame Buffer2 + 0x14 + 1 + read-write + + + DMA_TSF_DONE_FB2_0 + DMA transfer is not completed. + 0 + + + DMA_TSF_DONE_FB2_1 + DMA transfer is completed. + 0x1 + + + + + STATFF_INT + STATFIFO Full Interrupt Status + 0x15 + 1 + read-write + + + STATFF_INT_0 + STATFIFO is not full. + 0 + + + STATFF_INT_1 + STATFIFO is full. + 0x1 + + + + + DMA_TSF_DONE_SFF + DMA Transfer Done from StatFIFO + 0x16 + 1 + read-write + + + DMA_TSF_DONE_SFF_0 + DMA transfer is not completed. + 0 + + + DMA_TSF_DONE_SFF_1 + DMA transfer is completed. + 0x1 + + + + + RF_OR_INT + RxFIFO Overrun Interrupt Status + 0x18 + 1 + read-write + + + RF_OR_INT_0 + RXFIFO has not overflowed. + 0 + + + RF_OR_INT_1 + RXFIFO has overflowed. + 0x1 + + + + + SF_OR_INT + STATFIFO Overrun Interrupt Status + 0x19 + 1 + read-write + + + SF_OR_INT_0 + STATFIFO has not overflowed. + 0 + + + SF_OR_INT_1 + STATFIFO has overflowed. + 0x1 + + + + + DMA_FIELD1_DONE + When DMA field 0 is complete, this bit will be set to 1(clear by writing 1). + 0x1A + 1 + read-write + + + DMA_FIELD0_DONE + When DMA field 0 is complete, this bit will be set to 1(clear by writing 1). + 0x1B + 1 + read-write + + + BASEADDR_CHHANGE_ERROR + When using base address switching enable, this bit will be 1 when switching occur before DMA complete + 0x1C + 1 + read-write + + + + + CSIDMASA_STATFIFO + CSI DMA Start Address Register - for STATFIFO + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_START_ADDR_SFF + DMA Start Address for STATFIFO + 0x2 + 30 + read-write + + + + + CSIDMATS_STATFIFO + CSI DMA Transfer Size Register - for STATFIFO + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_TSF_SIZE_SFF + DMA Transfer Size for STATFIFO + 0 + 32 + read-write + + + + + CSIDMASA_FB1 + CSI DMA Start Address Register - for Frame Buffer1 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_START_ADDR_FB1 + DMA Start Address in Frame Buffer1 + 0x2 + 30 + read-write + + + + + CSIDMASA_FB2 + CSI DMA Transfer Size Register - for Frame Buffer2 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_START_ADDR_FB2 + DMA Start Address in Frame Buffer2 + 0x2 + 30 + read-write + + + + + CSIFBUF_PARA + CSI Frame Buffer Parameter Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FBUF_STRIDE + Frame Buffer Parameter + 0 + 16 + read-write + + + DEINTERLACE_STRIDE + DEINTERLACE_STRIDE is only used in the deinterlace mode + 0x10 + 16 + read-write + + + + + CSIIMAG_PARA + CSI Image Parameter Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMAGE_HEIGHT + Image Height. Indicates how many pixels in a column of the image from the sensor. + 0 + 16 + read-write + + + IMAGE_WIDTH + Image Width + 0x10 + 16 + read-write + + + + + CSICR18 + CSI Control Register 18 + 0x48 + 32 + read-write + 0x2D000 + 0xFFFFFFFF + + + DEINTERLACE_EN + This bit is used to select the output method When input is standard CCIR656 video. + 0x2 + 1 + read-write + + + DEINTERLACE_EN_0 + Deinterlace disabled + 0 + + + DEINTERLACE_EN_1 + Deinterlace enabled + 0x1 + + + + + PARALLEL24_EN + When input is parallel rgb888/yuv444 24bit, this bit can be enabled. + 0x3 + 1 + read-write + + + BASEADDR_SWITCH_EN + When this bit is enabled, CSI DMA will switch the base address according to BASEADDR_SWITCH_SEL rather than atomically by DMA completed + 0x4 + 1 + read-write + + + BASEADDR_SWITCH_SEL + CSI 2 base addresses switching method. When using this bit, BASEADDR_SWITCH_EN is 1. + 0x5 + 1 + read-write + + + BASEADDR_SWITCH_SEL_0 + Switching base address at the edge of the vsync + 0 + + + BASEADDR_SWITCH_SEL_1 + Switching base address at the edge of the first data of each frame + 0x1 + + + + + FIELD0_DONE_IE + In interlace mode, fileld 0 means interrupt enabled. + 0x6 + 1 + read-write + + + FIELD0_DONE_IE_0 + Interrupt disabled + 0 + + + FIELD0_DONE_IE_1 + Interrupt enabled + 0x1 + + + + + DMA_FIELD1_DONE_IE + When in interlace mode, field 1 done interrupt enable. + 0x7 + 1 + read-write + + + DMA_FIELD1_DONE_IE_0 + Interrupt disabled + 0 + + + DMA_FIELD1_DONE_IE_1 + Interrupt enabled + 0x1 + + + + + LAST_DMA_REQ_SEL + Choosing the last DMA request condition. + 0x8 + 1 + read-write + + + LAST_DMA_REQ_SEL_0 + fifo_full_level + 0 + + + LAST_DMA_REQ_SEL_1 + hburst_length + 0x1 + + + + + BASEADDR_CHANGE_ERROR_IE + Base address change error interrupt enable signal. + 0x9 + 1 + read-write + + + RGB888A_FORMAT_SEL + Output is 32-bit format. + 0xA + 1 + read-write + + + RGB888A_FORMAT_SEL_0 + {8'h0, data[23:0]} + 0 + + + RGB888A_FORMAT_SEL_1 + {data[23:0], 8'h0} + 0x1 + + + + + AHB_HPROT + Hprot value in AHB bus protocol. + 0xC + 4 + read-write + + + CSI_LCDIF_BUFFER_LINES + The number of lines are used in handshake mode with LCDIF. + 0x10 + 2 + read-write + + + CSI_LCDIF_BUFFER_LINES_0 + 4 lines + 0 + + + CSI_LCDIF_BUFFER_LINES_1 + 8 lines + 0x1 + + + CSI_LCDIF_BUFFER_LINES_2 + 16 lines + 0x2 + + + CSI_LCDIF_BUFFER_LINES_3 + 16 lines + 0x3 + + + + + MASK_OPTION + These bits used to choose the method to mask the CSI input. + 0x12 + 2 + read-write + + + MASK_OPTION_0 + Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1. + 0 + + + MASK_OPTION_1 + Writing to memory when CSI_ENABLE is 1. + 0x1 + + + MASK_OPTION_2 + Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. + 0x2 + + + MASK_OPTION_3 + Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0. + 0x3 + + + + + CSI_ENABLE + CSI global enable signal + 0x1F + 1 + read-write + + + + + CSICR19 + CSI Control Register 19 + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_RFIFO_HIGHEST_FIFO_LEVEL + This byte stores the highest FIFO level achieved by CSI FIFO timely and will be clear by writing 8'ff to it + 0 + 8 + read-write + + + + + + + LCDIF + eLCDIF Register Reference Index + LCDIF + LCDIF_ + 0x21C8000 + + 0 + 0x264 + registers + + + LCDIF + 37 + + + + CTRL + eLCDIF General Control Register + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the eLCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 0x1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 0x2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 0x3 + 1 + read-write + + + MASTER + Set this bit to make the eLCDIF act as a bus master. + 0x5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the eLCDIF will act as bus master and the handshake mechanism between eLCDIF and PXP will be turned on + 0x6 + 1 + read-write + + + RGB_TO_YCBCR422_CSC + Set this bit to 1 to enable conversion from RGB to YCbCr colorspace + 0x7 + 1 + read-write + + + WORD_LENGTH + Input data format. + 0x8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 0xA + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 0xC + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 0xE + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DATA_SELECT + Command Mode polarity bit. This bit should only be changed when RUN is 0. + 0x10 + 1 + read-write + + + CMD_MODE + Command Mode. LCD_RS signal is Low. + 0 + + + DATA_MODE + Data Mode. LCD_RS signal is High. + 0x1 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 0x11 + 1 + read-write + + + VSYNC_MODE + Setting this bit to 1 will make the eLCDIF hardware go into VSYNC mode + 0x12 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that eLCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 0x13 + 1 + read-write + + + DVI_MODE + Set this bit to 1 to get into the ITU-R BT + 0x14 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 0x15 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data + 0x1A + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + WAIT_FOR_VSYNC_EDGE + Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD + 0x1B + 1 + read-write + + + READ_WRITEB + By default, eLCDIF is in the write mode + 0x1C + 1 + read-write + + + YCBCR422_INPUT + Zero implies input data is in RGB color space + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the eLCDIF + 0x1F + 1 + read-write + + + + + CTRL_SET + eLCDIF General Control Register + 0x4 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the eLCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 0x1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 0x2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 0x3 + 1 + read-write + + + MASTER + Set this bit to make the eLCDIF act as a bus master. + 0x5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the eLCDIF will act as bus master and the handshake mechanism between eLCDIF and PXP will be turned on + 0x6 + 1 + read-write + + + RGB_TO_YCBCR422_CSC + Set this bit to 1 to enable conversion from RGB to YCbCr colorspace + 0x7 + 1 + read-write + + + WORD_LENGTH + Input data format. + 0x8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 0xA + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 0xC + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 0xE + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DATA_SELECT + Command Mode polarity bit. This bit should only be changed when RUN is 0. + 0x10 + 1 + read-write + + + CMD_MODE + Command Mode. LCD_RS signal is Low. + 0 + + + DATA_MODE + Data Mode. LCD_RS signal is High. + 0x1 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 0x11 + 1 + read-write + + + VSYNC_MODE + Setting this bit to 1 will make the eLCDIF hardware go into VSYNC mode + 0x12 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that eLCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 0x13 + 1 + read-write + + + DVI_MODE + Set this bit to 1 to get into the ITU-R BT + 0x14 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 0x15 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data + 0x1A + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + WAIT_FOR_VSYNC_EDGE + Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD + 0x1B + 1 + read-write + + + READ_WRITEB + By default, eLCDIF is in the write mode + 0x1C + 1 + read-write + + + YCBCR422_INPUT + Zero implies input data is in RGB color space + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the eLCDIF + 0x1F + 1 + read-write + + + + + CTRL_CLR + eLCDIF General Control Register + 0x8 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the eLCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 0x1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 0x2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 0x3 + 1 + read-write + + + MASTER + Set this bit to make the eLCDIF act as a bus master. + 0x5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the eLCDIF will act as bus master and the handshake mechanism between eLCDIF and PXP will be turned on + 0x6 + 1 + read-write + + + RGB_TO_YCBCR422_CSC + Set this bit to 1 to enable conversion from RGB to YCbCr colorspace + 0x7 + 1 + read-write + + + WORD_LENGTH + Input data format. + 0x8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 0xA + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 0xC + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 0xE + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DATA_SELECT + Command Mode polarity bit. This bit should only be changed when RUN is 0. + 0x10 + 1 + read-write + + + CMD_MODE + Command Mode. LCD_RS signal is Low. + 0 + + + DATA_MODE + Data Mode. LCD_RS signal is High. + 0x1 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 0x11 + 1 + read-write + + + VSYNC_MODE + Setting this bit to 1 will make the eLCDIF hardware go into VSYNC mode + 0x12 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that eLCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 0x13 + 1 + read-write + + + DVI_MODE + Set this bit to 1 to get into the ITU-R BT + 0x14 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 0x15 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data + 0x1A + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + WAIT_FOR_VSYNC_EDGE + Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD + 0x1B + 1 + read-write + + + READ_WRITEB + By default, eLCDIF is in the write mode + 0x1C + 1 + read-write + + + YCBCR422_INPUT + Zero implies input data is in RGB color space + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the eLCDIF + 0x1F + 1 + read-write + + + + + CTRL_TOG + eLCDIF General Control Register + 0xC + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RUN + When this bit is set by software, the eLCDIF will begin transferring data between the SoC and the display + 0 + 1 + read-write + + + DATA_FORMAT_24_BIT + Used only when WORD_LENGTH = 3, i + 0x1 + 1 + read-write + + + ALL_24_BITS_VALID + Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + 0 + + + DROP_UPPER_2_BITS_PER_BYTE + Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + 0x1 + + + + + DATA_FORMAT_18_BIT + Used only when WORD_LENGTH = 2, i.e. 18-bit. + 0x2 + 1 + read-write + + + LOWER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + 0 + + + UPPER_18_BITS_VALID + Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + 0x1 + + + + + DATA_FORMAT_16_BIT + When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format + 0x3 + 1 + read-write + + + MASTER + Set this bit to make the eLCDIF act as a bus master. + 0x5 + 1 + read-write + + + ENABLE_PXP_HANDSHAKE + If this bit is set and LCDIF_MASTER bit is set, the eLCDIF will act as bus master and the handshake mechanism between eLCDIF and PXP will be turned on + 0x6 + 1 + read-write + + + RGB_TO_YCBCR422_CSC + Set this bit to 1 to enable conversion from RGB to YCbCr colorspace + 0x7 + 1 + read-write + + + WORD_LENGTH + Input data format. + 0x8 + 2 + read-write + + + 16_BIT + Input data is 16 bits per pixel. + 0 + + + 8_BIT + Input data is 8 bits wide. + 0x1 + + + 18_BIT + Input data is 18 bits per pixel. + 0x2 + + + 24_BIT + Input data is 24 bits per pixel. + 0x3 + + + + + LCD_DATABUS_WIDTH + LCD Data bus transfer width. + 0xA + 2 + read-write + + + 16_BIT + 16-bit data bus mode. + 0 + + + 8_BIT + 8-bit data bus mode. + 0x1 + + + 18_BIT + 18-bit data bus mode. + 0x2 + + + 24_BIT + 24-bit data bus mode. + 0x3 + + + + + CSC_DATA_SWIZZLE + This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus + 0xC + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes fetched by the bus master interface + 0xE + 2 + read-write + + + NO_SWAP + No byte swapping.(Little endian) + 0 + + + BIG_ENDIAN_SWAP + Big Endian swap (swap bytes 0,3 and 1,2). + 0x1 + + + HWD_SWAP + Swap half-words. + 0x2 + + + HWD_BYTE_SWAP + Swap bytes within each half-word. + 0x3 + + + + + DATA_SELECT + Command Mode polarity bit. This bit should only be changed when RUN is 0. + 0x10 + 1 + read-write + + + CMD_MODE + Command Mode. LCD_RS signal is Low. + 0 + + + DATA_MODE + Data Mode. LCD_RS signal is High. + 0x1 + + + + + DOTCLK_MODE + Set this bit to 1 to make the hardware go into the DOTCLK mode, i + 0x11 + 1 + read-write + + + VSYNC_MODE + Setting this bit to 1 will make the eLCDIF hardware go into VSYNC mode + 0x12 + 1 + read-write + + + BYPASS_COUNT + When this bit is 0, it means that eLCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out + 0x13 + 1 + read-write + + + DVI_MODE + Set this bit to 1 to get into the ITU-R BT + 0x14 + 1 + read-write + + + SHIFT_NUM_BITS + The data to be transmitted is shifted left or right by this number of bits. + 0x15 + 5 + read-write + + + DATA_SHIFT_DIR + Use this bit to determine the direction of shift of transmit data + 0x1A + 1 + read-write + + + TXDATA_SHIFT_LEFT + Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + 0 + + + TXDATA_SHIFT_RIGHT + Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + 0x1 + + + + + WAIT_FOR_VSYNC_EDGE + Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD + 0x1B + 1 + read-write + + + READ_WRITEB + By default, eLCDIF is in the write mode + 0x1C + 1 + read-write + + + YCBCR422_INPUT + Zero implies input data is in RGB color space + 0x1D + 1 + read-write + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + This bit must be set to zero to enable normal operation of the eLCDIF + 0x1F + 1 + read-write + + + + + CTRL1 + eLCDIF General Control1 Register + 0x10 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + RESET + Reset bit for the external LCD controller + 0 + 1 + read-write + + + LCDRESET_LOW + LCD_RESET output signal is low. + 0 + + + LCDRESET_HIGH + LCD_RESET output signal is high. + 0x1 + + + + + MODE86 + This bit is used to select between the 8080 and 6800 series of microprocessor modes + 0x1 + 1 + read-write + + + 8080_MODE + Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + 0 + + + 6800_MODE + Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + 0x1 + + + + + BUSY_ENABLE + This bit enables the use of the interface's busy signal input + 0x2 + 1 + read-write + + + BUSY_DISABLED + The busy signal from the LCD controller will be ignored. + 0 + + + BUSY_ENABLED + Enable the use of the busy signal from the LCD controller. + 0x1 + + + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xA + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xB + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 0xC + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 0xD + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 0xE + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 0xF + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 0x10 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the eLCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 0x14 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 0x15 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 0x16 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the eLCDIF block fetches odd lines in one field and even lines in the other field + 0x17 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 0x18 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x19 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the eLCDIF master mode. + 0x1A + 1 + read-write + + + COMBINE_MPU_WR_STRB + If this bit is not set, the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode + 0x1B + 1 + read-write + + + + + CTRL1_SET + eLCDIF General Control1 Register + 0x14 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + RESET + Reset bit for the external LCD controller + 0 + 1 + read-write + + + LCDRESET_LOW + LCD_RESET output signal is low. + 0 + + + LCDRESET_HIGH + LCD_RESET output signal is high. + 0x1 + + + + + MODE86 + This bit is used to select between the 8080 and 6800 series of microprocessor modes + 0x1 + 1 + read-write + + + 8080_MODE + Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + 0 + + + 6800_MODE + Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + 0x1 + + + + + BUSY_ENABLE + This bit enables the use of the interface's busy signal input + 0x2 + 1 + read-write + + + BUSY_DISABLED + The busy signal from the LCD controller will be ignored. + 0 + + + BUSY_ENABLED + Enable the use of the busy signal from the LCD controller. + 0x1 + + + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xA + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xB + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 0xC + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 0xD + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 0xE + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 0xF + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 0x10 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the eLCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 0x14 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 0x15 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 0x16 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the eLCDIF block fetches odd lines in one field and even lines in the other field + 0x17 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 0x18 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x19 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the eLCDIF master mode. + 0x1A + 1 + read-write + + + COMBINE_MPU_WR_STRB + If this bit is not set, the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode + 0x1B + 1 + read-write + + + + + CTRL1_CLR + eLCDIF General Control1 Register + 0x18 + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + RESET + Reset bit for the external LCD controller + 0 + 1 + read-write + + + LCDRESET_LOW + LCD_RESET output signal is low. + 0 + + + LCDRESET_HIGH + LCD_RESET output signal is high. + 0x1 + + + + + MODE86 + This bit is used to select between the 8080 and 6800 series of microprocessor modes + 0x1 + 1 + read-write + + + 8080_MODE + Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + 0 + + + 6800_MODE + Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + 0x1 + + + + + BUSY_ENABLE + This bit enables the use of the interface's busy signal input + 0x2 + 1 + read-write + + + BUSY_DISABLED + The busy signal from the LCD controller will be ignored. + 0 + + + BUSY_ENABLED + Enable the use of the busy signal from the LCD controller. + 0x1 + + + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xA + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xB + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 0xC + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 0xD + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 0xE + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 0xF + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 0x10 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the eLCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 0x14 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 0x15 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 0x16 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the eLCDIF block fetches odd lines in one field and even lines in the other field + 0x17 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 0x18 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x19 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the eLCDIF master mode. + 0x1A + 1 + read-write + + + COMBINE_MPU_WR_STRB + If this bit is not set, the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode + 0x1B + 1 + read-write + + + + + CTRL1_TOG + eLCDIF General Control1 Register + 0x1C + 32 + read-write + 0xF0000 + 0xFFFFFFFF + + + RESET + Reset bit for the external LCD controller + 0 + 1 + read-write + + + LCDRESET_LOW + LCD_RESET output signal is low. + 0 + + + LCDRESET_HIGH + LCD_RESET output signal is high. + 0x1 + + + + + MODE86 + This bit is used to select between the 8080 and 6800 series of microprocessor modes + 0x1 + 1 + read-write + + + 8080_MODE + Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. + 0 + + + 6800_MODE + Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. + 0x1 + + + + + BUSY_ENABLE + This bit enables the use of the interface's busy signal input + 0x2 + 1 + read-write + + + BUSY_DISABLED + The busy signal from the LCD controller will be ignored. + 0 + + + BUSY_ENABLED + Enable the use of the busy signal from the LCD controller. + 0x1 + + + + + VSYNC_EDGE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x8 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + CUR_FRAME_DONE_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x9 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + UNDERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xA + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + OVERFLOW_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0xB + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + VSYNC_EDGE_IRQ_EN + This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode + 0xC + 1 + read-write + + + CUR_FRAME_DONE_IRQ_EN + This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state + 0xD + 1 + read-write + + + UNDERFLOW_IRQ_EN + This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. + 0xE + 1 + read-write + + + OVERFLOW_IRQ_EN + This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. + 0xF + 1 + read-write + + + BYTE_PACKING_FORMAT + This bitfield is used to show which data bytes in a 32-bit word are valid + 0x10 + 4 + read-write + + + IRQ_ON_ALTERNATE_FIELDS + If this bit is set, the eLCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field + 0x14 + 1 + read-write + + + FIFO_CLEAR + Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. + 0x15 + 1 + read-write + + + START_INTERLACE_FROM_SECOND_FIELD + The default is to grab the odd lines first and then the even lines + 0x16 + 1 + read-write + + + INTERLACE_FIELDS + Set this bit if it is required that the eLCDIF block fetches odd lines in one field and even lines in the other field + 0x17 + 1 + read-write + + + RECOVER_ON_UNDERFLOW + Set this bit to enable the eLCDIF block to recover in the next field/frame if there was an underflow in the current field/frame + 0x18 + 1 + read-write + + + BM_ERROR_IRQ + This bit is set to indicate that an interrupt is requested by the eLCDIF block + 0x19 + 1 + read-write + + + NO_REQUEST + No Interrupt Request Pending. + 0 + + + REQUEST + Interrupt Request Pending. + 0x1 + + + + + BM_ERROR_IRQ_EN + This bit is set to enable bus master error interrupt in the eLCDIF master mode. + 0x1A + 1 + read-write + + + COMBINE_MPU_WR_STRB + If this bit is not set, the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode + 0x1B + 1 + read-write + + + + + CTRL2 + eLCDIF General Control2 Register + 0x20 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + INITIAL_DUMMY_READ + The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller + 0x1 + 3 + read-write + + + READ_MODE_NUM_PACKED_SUBWORDS + Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode + 0x4 + 3 + read-write + + + READ_MODE_6_BIT_INPUT + Setting this bit to 1 indicates to eLCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits, the input data is actually only 6 bits wide and exists on D5-D0 + 0x8 + 1 + read-write + + + READ_MODE_OUTPUT_IN_RGB_FORMAT + Setting this bit will enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield + 0x9 + 1 + read-write + + + READ_PACK_DIR + The default value of 0 indicates data is stored in the little endian format + 0xA + 1 + read-write + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 0xC + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 0x10 + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + BURST_LEN_8 + By default, when the eLCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 0x14 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master + 0x15 + 3 + read-write + + + REQ_1 + no description available + 0 + + + REQ_2 + no description available + 0x1 + + + REQ_4 + no description available + 0x2 + + + REQ_8 + no description available + 0x3 + + + REQ_16 + no description available + 0x4 + + + + + + + CTRL2_SET + eLCDIF General Control2 Register + 0x24 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + INITIAL_DUMMY_READ + The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller + 0x1 + 3 + read-write + + + READ_MODE_NUM_PACKED_SUBWORDS + Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode + 0x4 + 3 + read-write + + + READ_MODE_6_BIT_INPUT + Setting this bit to 1 indicates to eLCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits, the input data is actually only 6 bits wide and exists on D5-D0 + 0x8 + 1 + read-write + + + READ_MODE_OUTPUT_IN_RGB_FORMAT + Setting this bit will enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield + 0x9 + 1 + read-write + + + READ_PACK_DIR + The default value of 0 indicates data is stored in the little endian format + 0xA + 1 + read-write + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 0xC + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 0x10 + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + BURST_LEN_8 + By default, when the eLCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 0x14 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master + 0x15 + 3 + read-write + + + REQ_1 + no description available + 0 + + + REQ_2 + no description available + 0x1 + + + REQ_4 + no description available + 0x2 + + + REQ_8 + no description available + 0x3 + + + REQ_16 + no description available + 0x4 + + + + + + + CTRL2_CLR + eLCDIF General Control2 Register + 0x28 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + INITIAL_DUMMY_READ + The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller + 0x1 + 3 + read-write + + + READ_MODE_NUM_PACKED_SUBWORDS + Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode + 0x4 + 3 + read-write + + + READ_MODE_6_BIT_INPUT + Setting this bit to 1 indicates to eLCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits, the input data is actually only 6 bits wide and exists on D5-D0 + 0x8 + 1 + read-write + + + READ_MODE_OUTPUT_IN_RGB_FORMAT + Setting this bit will enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield + 0x9 + 1 + read-write + + + READ_PACK_DIR + The default value of 0 indicates data is stored in the little endian format + 0xA + 1 + read-write + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 0xC + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 0x10 + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + BURST_LEN_8 + By default, when the eLCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 0x14 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master + 0x15 + 3 + read-write + + + REQ_1 + no description available + 0 + + + REQ_2 + no description available + 0x1 + + + REQ_4 + no description available + 0x2 + + + REQ_8 + no description available + 0x3 + + + REQ_16 + no description available + 0x4 + + + + + + + CTRL2_TOG + eLCDIF General Control2 Register + 0x2C + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + INITIAL_DUMMY_READ + The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller + 0x1 + 3 + read-write + + + READ_MODE_NUM_PACKED_SUBWORDS + Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode + 0x4 + 3 + read-write + + + READ_MODE_6_BIT_INPUT + Setting this bit to 1 indicates to eLCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits, the input data is actually only 6 bits wide and exists on D5-D0 + 0x8 + 1 + read-write + + + READ_MODE_OUTPUT_IN_RGB_FORMAT + Setting this bit will enable the eLCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield + 0x9 + 1 + read-write + + + READ_PACK_DIR + The default value of 0 indicates data is stored in the little endian format + 0xA + 1 + read-write + + + EVEN_LINE_PATTERN + This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6, + 0xC + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + ODD_LINE_PATTERN + This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5, + 0x10 + 3 + read-write + + + RGB + no description available + 0 + + + RBG + no description available + 0x1 + + + GBR + no description available + 0x2 + + + GRB + no description available + 0x3 + + + BRG + no description available + 0x4 + + + BGR + no description available + 0x5 + + + + + BURST_LEN_8 + By default, when the eLCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15) + 0x14 + 1 + read-write + + + OUTSTANDING_REQS + This bitfield indicates the maximum number of outstanding transactions that eLCDIF should request when it is acting as a bus master + 0x15 + 3 + read-write + + + REQ_1 + no description available + 0 + + + REQ_2 + no description available + 0x1 + + + REQ_4 + no description available + 0x2 + + + REQ_8 + no description available + 0x3 + + + REQ_16 + no description available + 0x4 + + + + + + + TRANSFER_COUNT + eLCDIF Horizontal and Vertical Valid Data Count Register + 0x30 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + H_COUNT + Total valid data (pixels) in each horizontal line + 0 + 16 + read-write + + + V_COUNT + Number of horizontal lines per frame which contain valid data + 0x10 + 16 + read-write + + + + + CUR_BUF + LCD Interface Current Buffer Address Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address of the current frame being transmitted by eLCDIF. + 0 + 32 + read-write + + + + + NEXT_BUF + LCD Interface Next Buffer Address Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address of the next frame that will be transmitted by eLCDIF. + 0 + 32 + read-write + + + + + TIMING + LCD Interface Timing Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_SETUP + Data bus setup time in DISPLAY CLOCK (pix_clk) cycles + 0 + 8 + read-write + + + DATA_HOLD + Data bus hold time in DISPLAY CLOCK (pix_clk) cycles + 0x8 + 8 + read-write + + + CMD_SETUP + Number of DISPLAY CLOCK (pix_clk) cycles that the LCD_RS signal is active before LCD_CS is asserted + 0x10 + 8 + read-write + + + CMD_HOLD + Number of DISPLAY CLOCK (pix_clk) cycles that the LCD_RS signal is active after LCD_CS is deasserted + 0x18 + 8 + read-write + + + + + VDCTRL0 + eLCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 0x12 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 0x13 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 0x14 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 0x15 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 0x18 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 0x19 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 0x1A + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 0x1B + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 0x1C + 1 + read-write + + + VSYNC_OEB + 0 means the VSYNC signal is an output, 1 means it is an input + 0x1D + 1 + read-write + + + VSYNC_OUTPUT + The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the eLCDIF block. + 0 + + + VSYNC_INPUT + The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + 0x1 + + + + + + + VDCTRL0_SET + eLCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 0x12 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 0x13 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 0x14 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 0x15 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 0x18 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 0x19 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 0x1A + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 0x1B + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 0x1C + 1 + read-write + + + VSYNC_OEB + 0 means the VSYNC signal is an output, 1 means it is an input + 0x1D + 1 + read-write + + + VSYNC_OUTPUT + The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the eLCDIF block. + 0 + + + VSYNC_INPUT + The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + 0x1 + + + + + + + VDCTRL0_CLR + eLCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 0x12 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 0x13 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 0x14 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 0x15 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 0x18 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 0x19 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 0x1A + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 0x1B + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 0x1C + 1 + read-write + + + VSYNC_OEB + 0 means the VSYNC signal is an output, 1 means it is an input + 0x1D + 1 + read-write + + + VSYNC_OUTPUT + The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the eLCDIF block. + 0 + + + VSYNC_INPUT + The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + 0x1 + + + + + + + VDCTRL0_TOG + eLCDIF VSYNC Mode and Dotclk Mode Control Register0 + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PULSE_WIDTH + Number of units for which VSYNC signal is active + 0 + 18 + read-write + + + HALF_LINE_MODE + When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line + 0x12 + 1 + read-write + + + HALF_LINE + Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i + 0x13 + 1 + read-write + + + VSYNC_PULSE_WIDTH_UNIT + Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles + 0x14 + 1 + read-write + + + VSYNC_PERIOD_UNIT + Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles + 0x15 + 1 + read-write + + + ENABLE_POL + Default 0 active low during valid data transfer on each horizontal line. + 0x18 + 1 + read-write + + + DOTCLK_POL + Default is data launched at negative edge of DOTCLK and captured at positive edge + 0x19 + 1 + read-write + + + HSYNC_POL + Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period + 0x1A + 1 + read-write + + + VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 0x1B + 1 + read-write + + + ENABLE_PRESENT + Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK + 0x1C + 1 + read-write + + + VSYNC_OEB + 0 means the VSYNC signal is an output, 1 means it is an input + 0x1D + 1 + read-write + + + VSYNC_OUTPUT + The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the eLCDIF block. + 0 + + + VSYNC_INPUT + The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. + 0x1 + + + + + + + VDCTRL1 + eLCDIF VSYNC Mode and Dotclk Mode Control Register1 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_PERIOD + Total number of units between two positive or two negative edges of the VSYNC signal + 0 + 32 + read-write + + + + + VDCTRL2 + LCDIF VSYNC Mode and Dotclk Mode Control Register2 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + HSYNC_PERIOD + Total number of DISPLAY CLOCK (pix_clk) cycles between two positive or two negative edges of the HSYNC signal + 0 + 18 + read-write + + + HSYNC_PULSE_WIDTH + Number of DISPLAY CLOCK (pix_clk) cycles for which HSYNC signal is active. + 0x12 + 14 + read-write + + + + + VDCTRL3 + eLCDIF VSYNC Mode and Dotclk Mode Control Register3 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + VERTICAL_WAIT_CNT + In the VSYNC interface mode, wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set + 0 + 16 + read-write + + + HORIZONTAL_WAIT_CNT + In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins + 0x10 + 12 + read-write + + + VSYNC_ONLY + This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation. + 0x1C + 1 + read-write + + + MUX_SYNC_SIGNALS + When this bit is set, the eLCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins + 0x1D + 1 + read-write + + + + + VDCTRL4 + eLCDIF VSYNC Mode and Dotclk Mode Control Register4 + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DOTCLK_H_VALID_DATA_CNT + Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode + 0 + 18 + read-write + + + SYNC_SIGNALS_ON + Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end + 0x12 + 1 + read-write + + + DOTCLK_DLY_SEL + This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin + 0x1D + 3 + read-write + + + + + DVICTRL0 + Digital Video Interface Control0 Register + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + H_BLANKING_CNT + Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval. + 0 + 12 + read-write + + + H_ACTIVE_CNT + Number of active video samples to be transmitted + 0x10 + 12 + read-write + + + + + DVICTRL1 + Digital Video Interface Control1 Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + F2_START_LINE + Vertical line number from which Field 2 begins. + 0 + 10 + read-write + + + F1_END_LINE + Vertical line number at which Field1 ends. + 0xA + 10 + read-write + + + F1_START_LINE + Vertical line number from which Field 1 begins. + 0x14 + 10 + read-write + + + + + DVICTRL2 + Digital Video Interface Control2 Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + V1_BLANK_END_LINE + Vertical line number in the beginning part of Field2 where first Vertical Blanking interval ends. + 0 + 10 + read-write + + + V1_BLANK_START_LINE + Vertical line number towards the end of Field1 where first Vertical Blanking interval starts. + 0xA + 10 + read-write + + + F2_END_LINE + Vertical line number at which Field 2 ends. + 0x14 + 10 + read-write + + + + + DVICTRL3 + Digital Video Interface Control3 Register + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + V_LINES_CNT + Total number of vertical lines per frame (generally 525 or 625) + 0 + 10 + read-write + + + V2_BLANK_END_LINE + Vertical line number in the beginning part of Field1 where second Vertical Blanking interval ends. + 0xA + 10 + read-write + + + V2_BLANK_START_LINE + Vertical line number towards the end of Field2 where second Vertical Blanking interval starts. + 0x14 + 10 + read-write + + + + + DVICTRL4 + Digital Video Interface Control4 Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + H_FILL_CNT + Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval + 0 + 8 + read-write + + + CR_FILL_VALUE + Value of CR component of filler data. + 0x8 + 8 + read-write + + + CB_FILL_VALUE + Value of CB component of filler data + 0x10 + 8 + read-write + + + Y_FILL_VALUE + Value of Y component of filler data + 0x18 + 8 + read-write + + + + + CSC_COEFF0 + RGB to YCbCr 4:2:2 CSC Coefficient0 Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSC_SUBSAMPLE_FILTER + This register describes the filtering and subsampling scheme to be performed on the chroma components in order to convert from YCbCr 4:4:4 to YCbCr 4:2:2 space + 0 + 2 + read-write + + + SAMPLE_AND_HOLD + No filtering, simply keep every chroma value for samples numbered 2n and discard chroma values associated with all samples numbered 2n+1. + 0 + + + INTERSTITIAL + Chroma samples numbered 2n and 2n+1 are averaged (weights 1/2, 1/2) and that chroma value replaces the two chroma values at 2n and 2n+1. This chroma now exists horizontally halfway between the two luma samples. + 0x2 + + + COSITED + Chroma samples numbered 2n-1, 2n, and 2n+1 are averaged (weights 1/4, 1/2, 1/4) and that chroma value exists at the same site as the luma sample numbered 2n and the chroma samples at 2n+1 are discarded. + 0x3 + + + + + C0 + Two's complement red multiplier coefficient for Y + 0x10 + 10 + read-write + + + + + CSC_COEFF1 + RGB to YCbCr 4:2:2 CSC Coefficient1 Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + C1 + Two's complement green multiplier coefficient for Y + 0 + 10 + read-write + + + C2 + Two's complement blue multiplier coefficient for Y + 0x10 + 10 + read-write + + + + + CSC_COEFF2 + RGB to YCbCr 4:2:2 CSC Coefficent2 Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + C3 + Two's complement red multiplier coefficient for Cb + 0 + 10 + read-write + + + C4 + Two's complement green multiplier coefficient for Cb + 0x10 + 10 + read-write + + + + + CSC_COEFF3 + RGB to YCbCr 4:2:2 CSC Coefficient3 Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + C5 + Two's complement blue multiplier coefficient for Cb + 0 + 10 + read-write + + + C6 + Two's complement red multiplier coefficient for Cr + 0x10 + 10 + read-write + + + + + CSC_COEFF4 + RGB to YCbCr 4:2:2 CSC Coefficient4 Register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + C7 + Two's complement green multiplier coefficient for Cr + 0 + 10 + read-write + + + C8 + Two's complement blue multiplier coefficient for Cr + 0x10 + 10 + read-write + + + + + CSC_OFFSET + RGB to YCbCr 4:2:2 CSC Offset Register + 0x160 + 32 + read-write + 0x800010 + 0xFFFFFFFF + + + Y_OFFSET + Two's complement offset for the Y component + 0 + 9 + read-write + + + CBCR_OFFSET + Two's complement offset for the Cb and Cr components + 0x10 + 9 + read-write + + + + + CSC_LIMIT + RGB to YCbCr 4:2:2 CSC Limit Register + 0x170 + 32 + read-write + 0xFF00FF + 0xFFFFFFFF + + + Y_MAX + Upper limit of Y after RGB to 4:2:2 YCbCr conversion + 0 + 8 + read-write + + + Y_MIN + Lower limit of Y after RGB to 4:2:2 YCbCr conversion + 0x8 + 8 + read-write + + + CBCR_MAX + Upper limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion + 0x10 + 8 + read-write + + + CBCR_MIN + Lower limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion + 0x18 + 8 + read-write + + + + + DATA + LCD Interface Data Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_ZERO + Byte 0 (least significant byte) of data written to eLCDIF. + 0 + 8 + read-write + + + DATA_ONE + Byte 1 of data written to eLCDIF. + 0x8 + 8 + read-write + + + DATA_TWO + Byte 2 of data written to eLCDIF. + 0x10 + 8 + read-write + + + DATA_THREE + Byte 3 (most significant byte) of data written to LCDIF. + 0x18 + 8 + read-write + + + + + BM_ERROR_STAT + Bus Master Error Status Register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Virtual address at which bus master error occurred. + 0 + 32 + read-write + + + + + CRC_STAT + CRC Status Register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CRC_VALUE + Calculated CRC value. + 0 + 32 + read-write + + + + + STAT + LCD Interface Status Register + 0x1B0 + 32 + read-only + 0x95000000 + 0xFFFFFFFF + + + LFIFO_COUNT + Read only view of the current count in Latency buffer (LFIFO). + 0 + 9 + read-only + + + DVI_CURRENT_FIELD + Read only view of the current field being transmitted + 0x18 + 1 + read-only + + + BUSY + Read only view of the input busy signal from the external LCD controller. + 0x19 + 1 + read-only + + + TXFIFO_EMPTY + Read only view of the signal that indicates that LCD write dapatath FIFO is empty, will be generally used in the read mode of the LCD interface + 0x1A + 1 + read-only + + + TXFIFO_FULL + Read only view of the signal that indicates that LCD write datapath FIFO is full, will be generally used in the write mode of the LCD interface + 0x1B + 1 + read-only + + + LFIFO_EMPTY + Read only view of the signal that indicates that LCD read dapatath FIFO is empty, will be generally used in the read mode of the LCD interface + 0x1C + 1 + read-only + + + LFIFO_FULL + Read only view of the signal that indicates that LCD read datapath FIFO is full, will be generally used in the write mode of the LCD interface + 0x1D + 1 + read-only + + + PRESENT + 0: eLCDIF not present on this product 1: eLCDIF is present. + 0x1F + 1 + read-only + + + + + THRES + eLCDIF Threshold Register + 0x200 + 32 + read-write + 0x100000F + 0xFFFFFFFF + + + PANIC + This value should be set to a value of pixels from 0 to 511 + 0 + 9 + read-write + + + FASTCLOCK + This value should be set to a value of pixels, from 0 to 511 + 0x10 + 9 + read-write + + + + + AS_CTRL + eLCDIF AS Buffer Control Register + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + AS_ENABLE + When this bit is set by software, the LCDIF will start fetching AS buffer data in bus master mode and combine it with another buffer + 0 + 1 + read-write + + + ALPHA_CTRL + Determines how the alpha value is constructed for this alpha surface + 0x1 + 2 + read-write + + + ENABLE_COLORKEY + Indicates that colorkey functionality is enabled for this alpha surface + 0x3 + 1 + read-write + + + FORMAT + Indicates the input buffer format for AS + 0x4 + 4 + read-write + + + ALPHA + Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in REG_AS_CTRL[ALPHA_CTRL] + 0x8 + 8 + read-write + + + ROP + Indicates a raster operation to perform when enabled + 0x10 + 4 + read-write + + + ALPHA_INVERT + Setting this bit to logic 0 will not alter the alpha value + 0x14 + 1 + read-write + + + INPUT_DATA_SWIZZLE + This field specifies how to swap the bytes either in the HW_LCDIF_DATA register or those fetched by the AXI master part of LCDIF + 0x15 + 2 + read-write + + + PS_DISABLE + When this bit is set by software, the LCDIF will disable PS buffer data. + 0x17 + 1 + read-write + + + RVDS1 + Reserved, always set to zero. + 0x18 + 3 + read-only + + + CSI_SYNC_ON_IRQ + this bit is set by software to decide which vsync generate mode + 0x1B + 1 + read-write + + + CSI_SYNC_ON_IRQ_EN + This bit is set to enable an interrupt when LCDIF lock with CSI vsync input. + 0x1C + 1 + read-write + + + CSI_VSYNC_MODE + this bit is set by software to decide which vsync generate mode + 0x1D + 1 + read-write + + + CSI_VSYNC_POL + Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period + 0x1E + 1 + read-write + + + CSI_VSYNC_ENABLE + When this bit is set by software, the LCDIF work as sync mode with CSI input. + 0x1F + 1 + read-write + + + + + AS_BUF + Alpha Surface Buffer Pointer + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the alpha surface 0 buffer. + 0 + 32 + read-write + + + + + AS_NEXT_BUF + no description available + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address of the next frame that will be transmitted by eLCDIF. + 0 + 32 + read-write + + + + + AS_CLRKEYLOW + eLCDIF Overlay Color Key Low + 0x240 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of RGB color key applied to AS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-write + + + + + AS_CLRKEYHIGH + eLCDIF Overlay Color Key High + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of RGB color key applied to AS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-write + + + + + SYNC_DELAY + LCD working insync mode with CSI for VSYNC delay + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + H_COUNT_DELAY + LCDIF VSYNC delayed counter for CSI_VSYNC. + 0 + 16 + read-write + + + V_COUNT_DELAY + LCDIF VSYNC delayed counter for CSI_VSYNC. + 0x10 + 16 + read-write + + + + + + + PXP + PXP v3.0 Register Reference Index + PXP + PXP_ + 0x21CC000 + + 0 + 0x2D44 + registers + + + PXP_IRQ0 + 40 + + + PXP_IRQ1 + 50 + + + + HW_CTRL + Control Register 0 + 0 + 32 + read-write + 0xC7008000 + 0xFFFFFFFF + + + ENABLE + Enables PXP operation with specified parameters + 0 + 1 + read-write + + + IRQ_ENABLE + Interrupt enable + 0x1 + 1 + read-write + + + NEXT_IRQ_ENABLE + Next command interrupt enable + 0x2 + 1 + read-write + + + LUT_DMA_IRQ_ENABLE + LUT DMA interrupt enable + 0x3 + 1 + read-write + + + ENABLE_LCD0_HANDSHAKE + Enable handshake with LCD0 controller + 0x4 + 1 + read-write + + + HANDSHAKE_ABORT_SKIP + When skip is enable, even the abort asserted, pxp will not assert the ready directly but wait for whole block line complete + 0x5 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + ROTATE0 + Indicates the clockwise rotation to be applied at the output buffer + 0x8 + 2 + read-write + + + ROT_0 + no description available + 0 + + + ROT_90 + no description available + 0x1 + + + ROT_180 + no description available + 0x2 + + + ROT_270 + no description available + 0x3 + + + + + HFLIP0 + Indicates that the output buffer should be flipped horizontally (effect applied before rotation). + 0xA + 1 + read-write + + + VFLIP0 + Indicates that the output buffer should be flipped vertically (effect applied before rotation). + 0xB + 1 + read-write + + + ROTATE1 + Indicates the clockwise rotation to be applied at the input buffer + 0xC + 2 + read-write + + + ROT_0 + no description available + 0 + + + ROT_90 + no description available + 0x1 + + + ROT_180 + no description available + 0x2 + + + ROT_270 + no description available + 0x3 + + + + + HFLIP1 + Indicates that the input should be flipped horizontally (effect applied before rotation). + 0xE + 1 + read-write + + + VFLIP1 + Indicates that the input should be flipped vertically (effect applied before rotation). + 0xF + 1 + read-write + + + ENABLE_PS_AS_OUT + Enable the PS engine, AS engine, OUTBUF in the PXP primary processing flow. + 0x10 + 1 + read-write + + + ENABLE_DITHER + Enable the Dithering engine in the PXP primary processing flow. + 0x11 + 1 + read-write + + + ENABLE_WFE_A + Enable the WFE-A engine in the PXP primary processing flow. + 0x12 + 1 + read-write + + + ENABLE_WFE_B + Enable the WFE-B engine in the PXP primary processing flow. + 0x13 + 1 + read-write + + + ENABLE_INPUT_FETCH_STORE + Enable the Input Fetch and Store engine in the PXP primary processing flow. + 0x14 + 1 + read-write + + + ENABLE_ALPHA_B + Enable the Alpha-B engine in the PXP primary processing flow. + 0x15 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x16 + 1 + read-only + + + BLOCK_SIZE + Select the block size to process through the Rotate block. + 0x17 + 1 + read-write + + + 8X8 + Process 8x8 pixel blocks. + 0 + + + 16X16 + Process 16x16 pixel blocks. + 0x1 + + + + + ENABLE_CSC2 + Enable the CSC2 engine in the PXP primary processing flow. + 0x18 + 1 + read-write + + + ENABLE_LUT + Enable the LUT engine in the PXP primary processing flow. + 0x19 + 1 + read-write + + + ENABLE_ROTATE0 + Enable the ROTATE0 engine in the PXP primary processing flow. + 0x1A + 1 + read-write + + + ENABLE_ROTATE1 + Enable the ROTATE1 engine in the PXP primary processing flow. + 0x1B + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x1C + 1 + read-only + + + RSVD4 + Reserved, always set to zero. + 0x1D + 1 + read-only + + + CLKGATE + This bit must be set to zero for normal operation + 0x1E + 1 + read-write + + + SFTRST + Set this bit to zero to enable normal PXP operation + 0x1F + 1 + read-write + + + + + HW_STAT + Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IRQ0 + Indicates current PXP interrupt status + 0 + 1 + read-write + + + AXI_WRITE_ERROR_0 + Indicates PXP encountered an AXI write error and processing has been terminated. + 0x1 + 1 + read-write + + + AXI_READ_ERROR_0 + Indicates PXP encountered an AXI read error and processing has been terminated. + 0x2 + 1 + read-write + + + NEXT_IRQ + Indicates that a command issued with the "Next Command" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register + 0x3 + 1 + read-write + + + AXI_ERROR_ID_0 + Indicates the AXI0 ID of the failing bus operation. + 0x4 + 4 + read-only + + + LUT_DMA_LOAD_DONE_IRQ + Indicates that the LUT DMA transfer has completed. + 0x8 + 1 + read-write + + + AXI_WRITE_ERROR_1 + Indicates PXP encountered an AXI write error and processing has been terminated. + 0x9 + 1 + read-write + + + AXI_READ_ERROR_1 + Indicates PXP encountered an AXI read error and processing has been terminated. + 0xA + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xB + 1 + read-only + + + AXI_ERROR_ID_1 + Indicates the AXI1 ID of the failing bus operation. + 0xC + 4 + read-only + + + BLOCKY + Indicates the X coordinate of the block currently being rendered. + 0x10 + 8 + read-only + + + BLOCKX + Indicates the X coordinate of the block currently being rendered. + 0x18 + 8 + read-only + + + + + HW_OUT_CTRL + Output Buffer Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + Output framebuffer format + 0 + 5 + read-write + + + ARGB8888 + 32-bit pixels + 0 + + + RGB888 + 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) + 0x4 + + + RGB888P + 24-bit pixels (packed 24-bit format) + 0x5 + + + ARGB1555 + 16-bit pixels + 0x8 + + + ARGB4444 + 16-bit pixels + 0x9 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + + + RSVD0 + Reserved, always set to zero. + 0x5 + 3 + read-only + + + INTERLACED_OUTPUT + Determines how the PXP writes it's output data + 0x8 + 2 + read-write + + + PROGRESSIVE + All data written in progressive format to the OUTBUF Pointer. + 0 + + + FIELD0 + Interlaced output: only data for field 0 is written to the OUTBUF Pointer. + 0x1 + + + FIELD1 + Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. + 0x2 + + + INTERLACED + Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0xA + 13 + read-only + + + ALPHA_OUTPUT + Indicates that alpha component in output buffer pixels should be overwritten by REG_OUT_CTRL[ALPHA] register + 0x17 + 1 + read-write + + + ALPHA + When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline + 0x18 + 8 + read-write + + + + + HW_OUT_BUF + Output Frame Buffer Pointer + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Current address pointer for the output frame buffer + 0 + 32 + read-write + + + + + HW_OUT_BUF2 + Output Frame Buffer Pointer #2 + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Current address pointer for the output frame buffer + 0 + 32 + read-write + + + + + HW_OUT_PITCH + Output Buffer Pitch + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + RSVD + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_OUT_LRC + Output Surface Lower Right Coordinate + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + Indicates the number of vertical PIXELS in the output surface (non-rotated) + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xE + 2 + read-only + + + X + Indicates number of horizontal PIXELS in the output surface (non-rotated) + 0x10 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_OUT_PS_ULC + Processed Surface Upper Left Coordinate + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output buffer + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xE + 2 + read-only + + + X + This field indicates the upper left X-coordinate (in pixels) of the processed surface (PS) in the output buffer + 0x10 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_OUT_PS_LRC + Processed Surface Lower Right Coordinate + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xE + 2 + read-only + + + X + This field indicates the lower right X-coordinate (in pixels) of the processed surface (PS) in the output frame buffer + 0x10 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_OUT_AS_ULC + Alpha Surface Upper Left Coordinate + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the upper left Y-coordinate (in pixels) of the alpha surface in the output frame buffer + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xE + 2 + read-only + + + X + This field indicates the upper left X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer + 0x10 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_OUT_AS_LRC + Alpha Surface Lower Right Coordinate + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the alpha surface in the output frame buffer + 0 + 14 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xE + 2 + read-only + + + X + This field indicates the lower right X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer + 0x10 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_PS_CTRL + Processed Surface (PS) Control Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register. + 0 + 6 + read-write + + + RGB888 + 32-bit pixels (unpacked 24-bit format) + 0x4 + + + RGB555 + 16-bit pixels + 0xC + + + RGB444 + 16-bit pixels + 0xD + + + RGB565 + 16-bit pixels + 0xE + + + YUV1P444 + 32-bit pixels (1-plane XYUV unpacked) + 0x10 + + + UYVY1P422 + 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) + 0x12 + + + VYUY1P422 + 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) + 0x13 + + + Y8 + 8-bit monochrome pixels (1-plane Y luma output) + 0x14 + + + Y4 + 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) + 0x15 + + + YUV2P422 + 16-bit pixels (2-plane UV interleaved bytes) + 0x18 + + + YUV2P420 + 16-bit pixels (2-plane UV) + 0x19 + + + YVU2P422 + 16-bit pixels (2-plane VU interleaved bytes) + 0x1A + + + YVU2P420 + 16-bit pixels (2-plane VU) + 0x1B + + + YUV422 + 16-bit pixels (3-plane format) + 0x1E + + + YUV420 + 16-bit pixels (3-plane format) + 0x1F + + + + + WB_SWAP + Swap bytes in words. For each 16 bit word, the two bytes will be swapped. + 0x6 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + DECY + Verticle pre decimation filter control. + 0x8 + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECY2 + Decimate PS by 2. + 0x1 + + + DECY4 + Decimate PS by 4. + 0x2 + + + DECY8 + Decimate PS by 8. + 0x3 + + + + + DECX + Horizontal pre decimation filter control. + 0xA + 2 + read-write + + + DISABLE + Disable pre-decimation filter. + 0 + + + DECX2 + Decimate PS by 2. + 0x1 + + + DECX4 + Decimate PS by 4. + 0x2 + + + DECX8 + Decimate PS by 8. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0xC + 20 + read-only + + + + + HW_PS_BUF + PS Input Buffer Address + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS RGB or Y (luma) input buffer. + 0 + 32 + read-write + + + + + HW_PS_UBUF + PS U/Cb or 2 Plane UV Input Buffer Address + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS U/Cb or 2 plane UV Chroma input buffer. + 0 + 32 + read-write + + + + + HW_PS_VBUF + PS V/Cr Input Buffer Address + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS V/Cr Chroma input buffer. + 0 + 32 + read-write + + + + + HW_PS_PITCH + Processed Surface Pitch + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + RSVD + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_PS_BACKGROUND_0 + PS Background Color + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + COLOR + Background color (in 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC + 0 + 24 + read-write + + + RSVD + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_PS_SCALE + PS Scale Factor Register + 0x110 + 32 + read-write + 0x10001000 + 0xFFFFFFFF + + + XSCALE + This is a two bit integer and 12 bit fractional representation (## + 0 + 15 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xF + 1 + read-only + + + YSCALE + This is a two bit integer and 12 bit fractional representation (## + 0x10 + 15 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x1F + 1 + read-only + + + + + HW_PS_OFFSET + PS Scale Offset Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + XOFFSET + This is a 12 bit fractional representation (0 + 0 + 12 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xC + 4 + read-only + + + YOFFSET + This is a 12 bit fractional representation (0 + 0x10 + 12 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x1C + 4 + read-only + + + + + HW_PS_CLRKEYLOW_0 + PS Color Key Low + 0x130 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of color key applied to PS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_PS_CLRKEYHIGH_0 + PS Color Key High + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of color key applied to PS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_AS_CTRL + Alpha Surface Control + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Reserved, always set to zero. + 0 + 1 + read-only + + + ALPHA_CTRL + Determines how the alpha value is constructed for this alpha surface + 0x1 + 2 + read-write + + + Embedded + Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored. + 0 + + + Override + Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. + 0x1 + + + Multiply + Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. + 0x2 + + + ROPs + Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels. + 0x3 + + + + + ENABLE_COLORKEY + Indicates that colorkey functionality is enabled for this alpha surface + 0x3 + 1 + read-write + + + FORMAT + Indicates the input buffer format for AS. + 0x4 + 4 + read-write + + + ARGB8888 + 32-bit pixels with alpha + 0 + + + RGBA8888 + 32-bit pixels with alpha + 0x1 + + + RGB888 + 32-bit pixels without alpha (unpacked 24-bit format) + 0x4 + + + ARGB1555 + 16-bit pixels with alpha + 0x8 + + + ARGB4444 + 16-bit pixels with alpha + 0x9 + + + RGB555 + 16-bit pixels without alpha + 0xC + + + RGB444 + 16-bit pixels without alpha + 0xD + + + RGB565 + 16-bit pixels without alpha + 0xE + + + + + ALPHA + Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in REG_AS_CTRL[ALPHA_CTRL] + 0x8 + 8 + read-write + + + ROP + Indicates a raster operation to perform when enabled + 0x10 + 4 + read-write + + + MASKAS + AS AND PS + 0 + + + MASKNOTAS + nAS AND PS + 0x1 + + + MASKASNOT + AS AND nPS + 0x2 + + + MERGEAS + AS OR PS + 0x3 + + + MERGENOTAS + nAS OR PS + 0x4 + + + MERGEASNOT + AS OR nPS + 0x5 + + + NOTCOPYAS + nAS + 0x6 + + + NOT + nPS + 0x7 + + + NOTMASKAS + AS NAND PS + 0x8 + + + NOTMERGEAS + AS NOR PS + 0x9 + + + XORAS + AS XOR PS + 0xA + + + NOTXORAS + AS XNOR PS + 0xB + + + + + ALPHA0_INVERT + Setting this bit to logic 0 will not alter the alpha0 value + 0x14 + 1 + read-write + + + ALPHA1_INVERT + Setting this bit to logic 0 will not alter the alpha1 value + 0x15 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x16 + 10 + read-only + + + + + HW_AS_BUF + Alpha Surface Buffer Pointer + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Address pointer for the alpha surface 0 buffer. + 0 + 32 + read-write + + + + + HW_AS_PITCH + Alpha Surface Pitch + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + RSVD + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_AS_CLRKEYLOW_0 + Overlay Color Key Low + 0x180 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable. + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_AS_CLRKEYHIGH_0 + Overlay Color Key High + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable. + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_CSC1_COEF0 + Color Space Conversion Coefficient Register 0 + 0x1A0 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data + 0 + 9 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data + 0x9 + 9 + read-write + + + C0 + Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 0x12 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1D + 1 + read-only + + + BYPASS + Bypass the CSC unit in the scaling engine + 0x1E + 1 + read-write + + + YCBCR_MODE + Set to 1 when performing YCbCr conversion to RGB + 0x1F + 1 + read-write + + + + + HW_CSC1_COEF1 + Color Space Conversion Coefficient Register 1 + 0x1B0 + 32 + read-write + 0x1230208 + 0xFFFFFFFF + + + C4 + Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017) + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xB + 5 + read-only + + + C1 + Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596) + 0x10 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_CSC1_COEF2 + Color Space Conversion Coefficient Register 2 + 0x1C0 + 32 + read-write + 0x79B076C + 0xFFFFFFFF + + + C3 + Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392) + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xB + 5 + read-only + + + C2 + Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813) + 0x10 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_CSC2_CTRL + Color Space Conversion Control Register. + 0x1D0 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + BYPASS + This bit controls whether the pixels entering the CSC2 unit get converted or not + 0 + 1 + read-write + + + CSC_MODE + This field controls how the CSC unit operates on pixels when the CSC is not bypassed. + 0x1 + 2 + read-write + + + YUV2RGB + Convert from YUV to RGB. + 0 + + + YCbCr2RGB + Convert from YCbCr to RGB. + 0x1 + + + RGB2YUV + Convert from RGB to YUV. + 0x2 + + + RGB2YCbCr + Convert from RGB to YCbCr. + 0x3 + + + + + RSVD + Reserved, always set to zero. + 0x3 + 29 + read-only + + + + + HW_CSC2_COEF0 + Color Space Conversion Coefficient Register 0 + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + A1 + Two's compliment coefficient offset + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xB + 5 + read-only + + + A2 + Two's compliment coefficient offset + 0x10 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_CSC2_COEF1 + Color Space Conversion Coefficient Register 1 + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + A3 + Two's compliment coefficient offset + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xB + 5 + read-only + + + B1 + Two's compliment coefficient offset + 0x10 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_CSC2_COEF2 + Color Space Conversion Coefficient Register 2 + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + B2 + Two's compliment coefficient offset + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xB + 5 + read-only + + + B3 + Two's compliment coefficient offset + 0x10 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_CSC2_COEF3 + Color Space Conversion Coefficient Register 3 + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + C1 + Two's compliment coefficient offset + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xB + 5 + read-only + + + C2 + Two's compliment coefficient offset + 0x10 + 11 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_CSC2_COEF4 + Color Space Conversion Coefficient Register 4 + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + C3 + Two's compliment coefficient offset + 0 + 11 + read-write + + + RSVD0 + Reserved, always set to zero. + 0xB + 5 + read-only + + + D1 + Two's compliment coefficient integer offset to be added. + 0x10 + 9 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x19 + 7 + read-only + + + + + HW_CSC2_COEF5 + Color Space Conversion Coefficient Register 5 + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + D2 + Two's compliment D1 coefficient integer offset to be added. + 0 + 9 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x9 + 7 + read-only + + + D3 + Two's compliment coefficient integer offset to be added. + 0x10 + 9 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x19 + 7 + read-only + + + + + HW_LUT_CTRL + Lookup Table Control Register. + 0x240 + 32 + read-write + 0x80010000 + 0xFFFFFFFF + + + DMA_START + Setting this bit will result in the DMA operation to load the PXP LUT memory based on REG_LUT_ADDR_NUM_BYTES, REG_LUT_ADDR_ADDR, and REG_LUT_MEM_ADDR + 0 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1 + 7 + read-only + + + INVALID + Invalidate the cache LRU and valid bits. This bit will automatically reset when set to a logic 1. + 0x8 + 1 + read-write + + + LRU_UPD + Least Recently Used Policy Update Control: 1=> block LRU update for hit after miss + 0x9 + 1 + read-write + + + SEL_8KB + Selects which 8KB bank of memory to use for direct 12bpp lookup modes + 0xA + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xB + 5 + read-only + + + OUT_MODE + Select the output mode of operation for the LUT resource + 0x10 + 2 + read-write + + + Y8 + R/Y byte lane 2 lookup, bytes 1,0 bypassed. + 0x1 + + + RGBW4444CFA + Byte lane 2 = CFA_Y8, byte lane 1,0 = RGBW4444. + 0x2 + + + RGB888 + RGB565->RGB888 conversion for Gamma correction. + 0x3 + + + + + RSVD2 + Reserved, always set to zero. + 0x12 + 6 + read-only + + + LOOKUP_MODE + Configure the input address for the 16KB LUT memory + 0x18 + 2 + read-write + + + CACHE_RGB565 + LUT ADDR = R[7:3],G[7:2],B[7:3]. Use all 16KB of LUT for indirect cached 128KB lookup. + 0 + + + DIRECT_Y8 + LUT ADDR = 16'b0,Y[7:0]. Use only the first 256 bytes of LUT. Only the Y, or third data path byte, is tranformed. + 0x1 + + + DIRECT_RGB444 + LUT ADDR = R[7:4],G[7:4],B[7:4]. Use one 8KB bank of LUT selected by SEL_8KB. + 0x2 + + + DIRECT_RGB454 + LUT ADDR = R[7:4],G[7:3],B[7:4]. Use all 16KB of LUT. + 0x3 + + + + + RSVD3 + Reserved, always set to zero. + 0x1A + 5 + read-only + + + BYPASS + Setting this bit will bypass the LUT memory resource completely + 0x1F + 1 + read-write + + + + + HW_LUT_ADDR + Lookup Table Control Register. + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + LUT indexed address pointer + 0 + 14 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xE + 2 + read-only + + + NUM_BYTES + Indicates the number of bytes to load via a DMA operation + 0x10 + 15 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x1F + 1 + read-only + + + + + HW_LUT_DATA + Lookup Table Data Register. + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register + 0 + 32 + read-write + + + + + HW_LUT_EXTMEM + Lookup Table External Memory Address Register. + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + This register contains the external memory address used for LUT memory operation. + 0 + 32 + read-write + + + + + HW_CFA + Color Filter Array Register. + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + This register contains the Color Filter Array pattern for decimation of RGBW4444 16 bit pixels to individual R, G, B, W values + 0 + 32 + read-write + + + + + HW_ALPHA_A_CTRL + PXP Alpha Engine A Control Register. + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + POTER_DUFF_ENABLE + poter_duff enable + 0 + 1 + read-write + + + 0 + porter duff disable. + 0 + + + 1 + porter duff enable. + 0x1 + + + + + S0_S1_FACTOR_MODE + s0 to s1 factor mode + 0x1 + 2 + read-write + + + 0 + using 1. + 0 + + + 1 + using 0. + 0x1 + + + 2 + using straight alpha. + 0x2 + + + 3 + using inverse alpha. + 0x3 + + + + + S0_GLOBAL_ALPHA_MODE + s0 global alpha mode + 0x3 + 2 + read-write + + + 0 + using global alpha. + 0 + + + 1 + using local alpha. + 0x1 + + + 2 + using scaled alpha. + 0x2 + + + 3 + using scaled alpha. + 0x3 + + + + + S0_ALPHA_MODE + s0 alpha mode + 0x5 + 1 + read-write + + + 0 + straight mode for s0 alpha + 0 + + + 1 + inversed mode for s0 alpha + 0x1 + + + + + S0_COLOR_MODE + s0 color mode + 0x6 + 1 + read-write + + + 0 + straight mode for s0 color + 0 + + + 1 + multiply mode for s0 color + 0x1 + + + + + RSVD1 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + S1_S0_FACTOR_MODE + s1 to s0 factor mode + 0x8 + 2 + read-write + + + 0 + using 1. + 0 + + + 1 + using 0. + 0x1 + + + 2 + using straight alpha. + 0x2 + + + 3 + using inverse alpha. + 0x3 + + + + + S1_GLOBAL_ALPHA_MODE + s1 global alpha mode + 0xA + 2 + read-write + + + 0 + using global alpha. + 0 + + + + + S1_ALPHA_MODE + s1 alpha mode + 0xC + 1 + read-write + + + 0 + straight mode for s1 alpha + 0 + + + 1 + inversed mode for s1 alpha + 0x1 + + + + + S1_COLOR_MODE + s1 color mode + 0xD + 1 + read-write + + + 0 + straight mode for s1 color + 0 + + + 1 + multiply mode for s1 color + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0xE + 2 + read-only + + + S0_GLOBAL_ALPHA + s0 global alpha + 0x10 + 8 + read-write + + + S1_GLOBAL_ALPHA + s1 global alpha + 0x18 + 8 + read-write + + + + + HW_ALPHA_B_CTRL + PXP Alpha Engine B Control Register. + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + POTER_DUFF_ENABLE + poter_duff enable + 0 + 1 + read-write + + + 0 + porter duff disable. + 0 + + + 1 + porter duff enable. + 0x1 + + + + + S0_S1_FACTOR_MODE + s0 to s1 factor mode + 0x1 + 2 + read-write + + + 0 + using 1. + 0 + + + 1 + using 0. + 0x1 + + + 2 + using straight alpha. + 0x2 + + + 3 + using inverse alpha. + 0x3 + + + + + S0_GLOBAL_ALPHA_MODE + s0 global alpha mode + 0x3 + 2 + read-write + + + 0 + using global alpha. + 0 + + + 1 + using local alpha. + 0x1 + + + 2 + using scaled alpha. + 0x2 + + + 3 + using scaled alpha. + 0x3 + + + + + S0_ALPHA_MODE + s0 alpha mode + 0x5 + 1 + read-write + + + 0 + straight mode for s0 alpha + 0 + + + 1 + inversed mode for s0 alpha + 0x1 + + + + + S0_COLOR_MODE + s0 color mode + 0x6 + 1 + read-write + + + 0 + straight mode for s0 color + 0 + + + 1 + multiply mode for s0 color + 0x1 + + + + + RSVD1 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + S1_S0_FACTOR_MODE + s1 to s0 factor mode + 0x8 + 2 + read-write + + + 0 + using 1. + 0 + + + 1 + using 0. + 0x1 + + + 2 + using straight alpha. + 0x2 + + + 3 + using inverse alpha. + 0x3 + + + + + S1_GLOBAL_ALPHA_MODE + s1 global alpha mode + 0xA + 2 + read-write + + + 0 + using global alpha. + 0 + + + 1 + using local alpha. + 0x1 + + + 2 + using scaled alpha. + 0x2 + + + 3 + using scaled alpha. + 0x3 + + + + + S1_ALPHA_MODE + s1 alpha mode + 0xC + 1 + read-write + + + 0 + straight mode for s1 alpha + 0 + + + 1 + inversed mode for s1 alpha + 0x1 + + + + + S1_COLOR_MODE + s1 color mode + 0xD + 1 + read-write + + + 0 + straight mode for s1 color + 0 + + + 1 + multiply mode for s1 color + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0xE + 2 + read-only + + + S0_GLOBAL_ALPHA + s0 global alpha + 0x10 + 8 + read-write + + + S1_GLOBAL_ALPHA + s1 global alpha + 0x18 + 8 + read-write + + + + + HW_ALPHA_B_CTRL_1 + no description available + 0x2B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ROP_ENABLE + ROP ENABLE + 0 + 1 + read-write + + + OL_CLRKEY_ENABLE + Indicates that colorkey functionality is enabled for this alpha surface + 0x1 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x2 + 2 + read-only + + + ROP + Indicates a raster operation to perform when enabled. + 0x4 + 4 + read-write + + + MASKAS + AS AND PS + 0 + + + MASKNOTAS + nAS AND PS + 0x1 + + + MASKASNOT + AS AND nPS + 0x2 + + + MERGEAS + AS OR PS + 0x3 + + + MERGENOTAS + nAS OR PS + 0x4 + + + MERGEASNOT + AS OR nPS + 0x5 + + + NOTCOPYAS + nAS + 0x6 + + + NOT + nPS + 0x7 + + + NOTMASKAS + AS NAND PS + 0x8 + + + NOTMERGEAS + AS NOR PS + 0x9 + + + XORAS + AS XOR PS + 0xA + + + NOTXORAS + AS XNOR PS + 0xB + + + + + RSVD0 + Reserved, always set to zero. + 0x8 + 24 + read-only + + + + + HW_PS_BACKGROUND_1 + PS Background Color 1 + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + COLOR + Background color (in 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC + 0 + 24 + read-write + + + RSVD + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_PS_CLRKEYLOW_1 + PS Color Key Low 1 + 0x2D0 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of color key applied to PS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_PS_CLRKEYHIGH_1 + PS Color Key High 1 + 0x2E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of color key applied to PS buffer + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_AS_CLRKEYLOW_1 + Overlay Color Key Low + 0x2F0 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + Low range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable. + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_AS_CLRKEYHIGH_1 + Overlay Color Key High + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + High range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable. + 0 + 24 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_CTRL2 + Control Register 2 + 0x310 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enables PXP secondary data processing flow with specified parameters + 0 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1 + 7 + read-only + + + ROTATE0 + Indicates the clockwise rotation to be applied at the output buffer + 0x8 + 2 + read-write + + + ROT_0 + no description available + 0 + + + ROT_90 + no description available + 0x1 + + + ROT_180 + no description available + 0x2 + + + ROT_270 + no description available + 0x3 + + + + + HFLIP0 + Indicates that the output buffer should be flipped horizontally (effect applied before rotation). + 0xA + 1 + read-write + + + VFLIP0 + Indicates that the output buffer should be flipped vertically (effect applied before rotation). + 0xB + 1 + read-write + + + ROTATE1 + Indicates the clockwise rotation to be applied at the input buffer + 0xC + 2 + read-write + + + ROT_0 + no description available + 0 + + + ROT_90 + no description available + 0x1 + + + ROT_180 + no description available + 0x2 + + + ROT_270 + no description available + 0x3 + + + + + HFLIP1 + Indicates that the input should be flipped horizontally (effect applied before rotation). + 0xE + 1 + read-write + + + VFLIP1 + Indicates that the input should be flipped vertically (effect applied before rotation). + 0xF + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x10 + 1 + read-only + + + ENABLE_DITHER + Enable the Dithering engine in the PXP secondary processing flow. + 0x11 + 1 + read-write + + + ENABLE_WFE_A + Enable the WFE-A engine in the PXP secondary processing flow. + 0x12 + 1 + read-write + + + ENABLE_WFE_B + Enable the WFE-B engine in the PXP secondary processing flow. + 0x13 + 1 + read-write + + + ENABLE_INPUT_FETCH_STORE + Enable the Input Fetch and Store engine in the PXP secondary processing flow. + 0x14 + 1 + read-write + + + ENABLE_ALPHA_B + Enable the Alpha-B engine in the PXP secondary processing flow. + 0x15 + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x16 + 1 + read-only + + + BLOCK_SIZE + Select the block size to process through the Rotate block. + 0x17 + 1 + read-write + + + 8X8 + Process 8x8 pixel blocks. + 0 + + + 16X16 + Process 16x16 pixel blocks. + 0x1 + + + + + ENABLE_CSC2 + Enable the CSC2 engine in the PXP secondary processing flow. + 0x18 + 1 + read-write + + + ENABLE_LUT + Enable the LUT engine in the PXP secondary processing flow. + 0x19 + 1 + read-write + + + ENABLE_ROTATE0 + Enable the ROTATE0 engine in the PXP secondary processing flow. + 0x1A + 1 + read-write + + + ENABLE_ROTATE1 + Enable the ROTATE1 engine in the PXP secondary processing flow. + 0x1B + 1 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x1C + 4 + read-only + + + + + HW_POWER_REG0 + PXP Power Control Register. + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUT_LP_STATE_WAY0_BANK0 + Select the low power state of the LUT's WAY0-BANK0 memory. + 0 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + LUT_LP_STATE_WAY0_BANKN + Select the low power state of the LUT's WAY0-BANK1,2,3 memory. + 0x3 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + LUT_LP_STATE_WAY1_BANKN + Select the low power state of the LUT's WAY0-BANK0,1,2,3 memory. + 0x6 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + ROT0_MEM_LP_STATE + Select the low power state of the ROT 0 memory. + 0x9 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + CTRL + This register contains power control for the PXP. + 0xC + 20 + read-write + + + + + HW_POWER_REG1 + PXP Power Control Register 1. + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + ROT1_MEM_LP_STATE + Select the low power state of the ROT 1 memory. + 0 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + DITH0_LUT_MEM_LP_STATE + Select the low power state of the dither0 LUT memory. + 0x3 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + DITH0_ERR0_MEM_LP_STATE + Select the low power state of the dither0 ERR0 memory. + 0x6 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + DITH0_ERR1_MEM_LP_STATE + Select the low power state of the dither0 ERR1 memory. + 0x9 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + DITH1_LUT_MEM_LP_STATE + Select the low power state of the dither1 LUT memory. + 0xC + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + DITH2_LUT_MEM_LP_STATE + Select the low power state of the dither2 LUT memory. + 0xF + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + ALU_A_MEM_LP_STATE + Select the low power state of the ALU A memory. + 0x12 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + ALU_B_MEM_LP_STATE + Select the low power state of the ALU B memory. + 0x15 + 3 + read-write + + + NONE + Memory is not in low power state. + 0 + + + LS + Light Sleep Mode. Low leakage mode, maintain memory contents. + 0x1 + + + DS + Deep Sleep Mode. Low leakage mode, maintain memory contents. + 0x2 + + + SD + Shut Down Mode. Shut Down periphery and core, no memory retention. + 0x4 + + + + + RSVD0 + This register contains power control for the PXP. + 0x18 + 8 + read-only + + + + + HW_DATA_PATH_CTRL1 + no description available + 0x350 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX16_SEL + This mux chooses the data path through MUX 16. + 0 + 2 + read-write + + + 0 + Output of ALU A Engine + 0 + + + 1 + histogram_pixel output from output + 0x1 + + + 2 + Output of ALU B Engine + 0x2 + + + 3 + No output + 0x3 + + + + + MUX17_SEL + This field chooses the data path through MUX 17. + 0x2 + 2 + read-write + + + 0 + Output of ALU A + 0 + + + 1 + Output of ALU B + 0x1 + + + 2 + No output + 0x2 + + + 3 + No Output + 0x3 + + + + + RSVD0 + Reserved. This field always reads 0. + 0x4 + 28 + read-only + + + + + HW_INIT_MEM_CTRL + Initialize memory buffer control Register + 0x360 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Base address to start writing + 0 + 16 + read-write + + + RSVD0 + Reserved. + 0x10 + 11 + read-only + + + SELECT + Select which memory to write. + 0x1B + 4 + read-write + + + DITHER0_LUT + Select the LUT memory for access + 0 + + + DITHER0_ERR0 + Select the ERR0 memory for access + 0x1 + + + DITHER0_ERR1 + Select the ERR1 memory for access + 0x2 + + + DITHER1_LUT + Select the LUT memory for access + 0x3 + + + DITHER2_LUT + Select the LUT memory for access + 0x4 + + + ALU_A + Select the ALU instr memory for access + 0x5 + + + ALU_B + Select the ALU instr memory for access + 0x6 + + + WFE_A_FETCH + Select the WFE-A fetch memory for access + 0x7 + + + WFE_B_FETCH + Select the WFE-B fetch memory for access + 0x8 + + + + + START + Enable writing to the memory. + 0x1F + 1 + read-write + + + + + HW_INIT_MEM_DATA + Write data Register + 0x370 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data value to be written to the memory + 0 + 32 + read-write + + + + + HW_INIT_MEM_DATA_HIGH + Write data Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Data value to be written to the most significant 32 bits of the fetch memories + 0 + 32 + read-write + + + + + HW_IRQ_MASK + PXP IRQ Mask Register + 0x390 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIRST_CH0_PREFETCH_IRQ_EN + Enable First ch0 prefetch engine interrupt detection + 0 + 1 + read-write + + + FIRST_CH1_PREFETCH_IRQ_EN + Enable First ch1 prefetch engine interrupt detection + 0x1 + 1 + read-write + + + FIRST_CH0_STORE_IRQ_EN + Enable First ch0 store engine interrupt detection + 0x2 + 1 + read-write + + + FIRST_CH1_STORE_IRQ_EN + Enable First ch1 store engine interrupt detection + 0x3 + 1 + read-write + + + DITHER_CH0_PREFETCH_IRQ_EN + Enable Dither ch0 prefetch engine interrupt detection + 0x4 + 1 + read-write + + + DITHER_CH1_PREFETCH_IRQ_EN + Enable Dither ch1 prefetch engine interrupt detection + 0x5 + 1 + read-write + + + DITHER_CH0_STORE_IRQ_EN + Enable dither ch0 store engine interrupt detection. + 0x6 + 1 + read-write + + + DITHER_CH1_STORE_IRQ_EN + Enable dither ch1 store engine interrupt detection. + 0x7 + 1 + read-write + + + WFE_A_CH0_STORE_IRQ_EN + Enable WFE A ch0 store engine interrupt detection. + 0x8 + 1 + read-write + + + WFE_A_CH1_STORE_IRQ_EN + Enable WFE A ch1 store engine interrupt detection. + 0x9 + 1 + read-write + + + WFE_B_CH0_STORE_IRQ_EN + Enable WFE B ch0 store engine interrupt detection. + 0xA + 1 + read-write + + + WFE_B_CH1_STORE_IRQ_EN + Enable WFE B ch1 store engine interrupt detection. + 0xB + 1 + read-write + + + FIRST_STORE_IRQ_EN + Enable First store engine interrupt detection + 0xC + 1 + read-write + + + DITHER_STORE_IRQ_EN + Enable dither store engine interrupt detection. + 0xD + 1 + read-write + + + WFE_A_STORE_IRQ_EN + Enable WFE A store engine interrupt detection. + 0xE + 1 + read-write + + + WFE_B_STORE_IRQ_EN + Enable WFE B store engine interrupt detection. + 0xF + 1 + read-write + + + RSVD1 + Reserved. + 0x10 + 15 + read-only + + + COMPRESS_DONE_IRQ_EN + Enable compression done interrupt detection. + 0x1F + 1 + read-write + + + + + HW_IRQ + PXP Interrupt Register + 0x3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIRST_CH0_PREFETCH_IRQ + Initial ch0 prefetch engine interrupt + 0 + 1 + read-write + + + FIRST_CH1_PREFETCH_IRQ + Initial ch1 prefetch engine interrupt + 0x1 + 1 + read-write + + + FIRST_CH0_STORE_IRQ + Initial ch0 store engine interrupt + 0x2 + 1 + read-write + + + FIRST_CH1_STORE_IRQ + Initial ch1 store engine interrupt + 0x3 + 1 + read-write + + + DITHER_CH0_PREFETCH_IRQ + Dither ch0 prefetch engine interrupt + 0x4 + 1 + read-write + + + DITHER_CH1_PREFETCH_IRQ + Dither ch1 prefetch engine interrupt + 0x5 + 1 + read-write + + + DITHER_CH0_STORE_IRQ + Dither ch0 store engine Interrupt + 0x6 + 1 + read-write + + + DITHER_CH1_STORE_IRQ + Dither ch1 store engine Interrupt + 0x7 + 1 + read-write + + + WFE_A_CH0_STORE_IRQ + WFE A ch0 store engine Interrupt. + 0x8 + 1 + read-write + + + WFE_A_CH1_STORE_IRQ + WFE A ch1 store engine Interrupt. + 0x9 + 1 + read-write + + + WFE_B_CH0_STORE_IRQ + WFE B ch0 store engine Interrupt + 0xA + 1 + read-write + + + WFE_B_CH1_STORE_IRQ + WFE B ch1 store engine Interrupt + 0xB + 1 + read-write + + + FIRST_STORE_IRQ + Initial store engine interrupt + 0xC + 1 + read-write + + + DITHER_STORE_IRQ + Dither store engine Interrupt + 0xD + 1 + read-write + + + WFE_A_STORE_IRQ + WFE A store engine Interrupt. + 0xE + 1 + read-write + + + WFE_B_STORE_IRQ + WFE B store engine Interrupt + 0xF + 1 + read-write + + + RSVD1 + Reserved. + 0x10 + 15 + read-only + + + COMPRESS_DONE_IRQ + compression done Interrupt + 0x1F + 1 + read-write + + + + + HW_NEXT + Next Frame Pointer + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLED + Indicates that the "next frame" functionality has been enabled + 0 + 1 + read-only + + + RSVD + Reserved, always set to zero. + 0x1 + 1 + read-only + + + POINTER + A pointer to a data structure containing register values to be used when processing the next frame + 0x2 + 30 + read-write + + + + + HW_INPUT_FETCH_CTRL_CH0 + Pre-fetch engine Control Channel 0 Register + 0x450 + 32 + read-write + 0x20000 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + Prefetch function is disable + 0 + + + 1 + Prefetch function is enable + 0x1 + + + + + BLOCK_EN + Choses the prefetch mode. + 0x1 + 1 + read-write + + + 0 + Prefetch in scan mode + 0 + + + 1 + Prefetch in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the store engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the store engine is disabled + 0 + + + 1 + Handshake with the store engine is enabled + 0x1 + + + + + BYPASS_PIXEL_EN + Selects Channel 0 pixel source + 0x4 + 1 + read-write + + + 0 + Channel 0 is from memory + 0 + + + 1 + Channel 0 is from previous process engine + 0x1 + + + + + HIGH_BYTE + channel 0 high byte selection + 0x5 + 1 + read-write + + + 0 + In 64 bit mode, the output high byte will use channel1. + 0 + + + 1 + In 64 bit mode, the output high byte will use channel0 + 0x1 + + + + + RSVD4 + Reserved, always set to zero. + 0x6 + 3 + read-only + + + HFLIP + Enables HFLIP. + 0x9 + 1 + read-write + + + 0 + HFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + VFLIP + Enables VFLIP + 0xA + 1 + read-write + + + 0 + VFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + RSVD3 + Reserved, always set to zero. + 0xB + 1 + read-only + + + ROTATION_ANGLE + no description available + 0xC + 2 + read-write + + + ROT_0 + Rotate image by 0 degrees. + 0 + + + ROT_90 + Rotate image by 90 degrees. + 0x1 + + + ROT_180 + Rotate image by 180 degrees. + 0x2 + + + ROT_270 + Rotate image by 270 degrees. + 0x3 + + + + + RSVD2 + Reserved, always set to zero. + 0xE + 2 + read-only + + + RD_NUM_BYTES + Bytes in a read burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes. + 0 + + + 16_bytes + 16 bytes. + 0x1 + + + 32_bytes + 32 bytes. + 0x2 + + + 64_bytes + 64 bytes. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x12 + 6 + read-only + + + HANDSHAKE_SCAN_LINE_NUM + scan handshake line number + 0x18 + 2 + read-write + + + 0 + 1 line. + 0 + + + 1 + 8 lines + 0x1 + + + 2 + 16 lines + 0x2 + + + 3 + 16 lines + 0x3 + + + + + RSVD0 + Reserved, always set to zero. + 0x1A + 5 + read-only + + + ARBIT_EN + Enables Arbitration + 0x1F + 1 + read-write + + + 0 + Arbitration disable. If using 2 channels, will output 2 axi bus sets. + 0 + + + 1 + Arbitration enable. If using 2 channel, will only output 1 axi bus sets + 0x1 + + + + + + + HW_INPUT_FETCH_CTRL_CH1 + Pre-fetch engine Control Channel 1 Register + 0x460 + 32 + read-write + 0x20000 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + prefetch function is disable + 0 + + + 1 + prefetch function is enable + 0x1 + + + + + BLOCK_EN + Choses the prefetch mode. + 0x1 + 1 + read-write + + + 0 + Prefetch in scan mode + 0 + + + 1 + Prefetch in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the store engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the store engine is disabled + 0 + + + 1 + Handshake with the store engine is enabled + 0x1 + + + + + BYPASS_PIXEL_EN + Selects Channel 1 pixel source + 0x4 + 1 + read-write + + + 0 + Channel 1 is from memory + 0 + + + 1 + Channel 1 is from previous process engine + 0x1 + + + + + RSVD4 + Reserved, always set to zero. + 0x5 + 4 + read-only + + + HFLIP + Enables HFLIP. + 0x9 + 1 + read-write + + + 0 + HFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + VFLIP + Enables VFLIP + 0xA + 1 + read-write + + + 0 + VFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + RSVD3 + Reserved, always set to zero. + 0xB + 1 + read-only + + + ROTATION_ANGLE + no description available + 0xC + 2 + read-write + + + ROT_0 + Rotate image by 0 degrees. + 0 + + + ROT_90 + Rotate image by 90 degrees. + 0x1 + + + ROT_180 + Rotate image by 180 degrees. + 0x2 + + + ROT_270 + Rotate image by 270 degrees. + 0x3 + + + + + RSVD2 + Reserved, always set to zero. + 0xE + 2 + read-only + + + RD_NUM_BYTES + Bytes in a read burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes. + 0 + + + 16_bytes + 16 bytes. + 0x1 + + + 32_bytes + 32 bytes. + 0x2 + + + 64_bytes + 64 bytes. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x12 + 6 + read-only + + + HANDSHAKE_SCAN_LINE_NUM + scan handshake line number + 0x18 + 2 + read-write + + + 0 + 1 line. + 0 + + + 1 + 8 lines + 0x1 + + + 2 + 16 lines + 0x2 + + + 3 + 16 lines + 0x3 + + + + + RSVD0 + Reserved, always set to zero. + 0x1A + 6 + read-only + + + + + HW_INPUT_FETCH_STATUS_CH0 + Pre-fetch engine status Channel 0 Register + 0x470 + 32 + read-only + 0 + 0xFFFFFFFF + + + PREFETCH_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + PREFETCH_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_INPUT_FETCH_STATUS_CH1 + Store engine status Channel 1 Register + 0x480 + 32 + read-only + 0 + 0xFFFFFFFF + + + PREFETCH_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + PREFETCH_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0 + no description available + 0x490 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_ULC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_ULC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0 + no description available + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_LRC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_LRC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1 + no description available + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_ULC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_ULC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1 + no description available + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_LRC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_LRC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_INPUT_FETCH_SIZE_CH0 + no description available + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_TOTAL_WIDTH + actual total width -1 + 0 + 16 + read-write + + + INPUT_TOTAL_HEIGHT + actual total height - 1 + 0x10 + 16 + read-write + + + + + HW_INPUT_FETCH_SIZE_CH1 + no description available + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_TOTAL_WIDTH + actual total width -1 + 0 + 16 + read-write + + + INPUT_TOTAL_HEIGHT + actual total height -1 + 0x10 + 16 + read-write + + + + + HW_INPUT_FETCH_BACKGROUND_COLOR_CH0 + no description available + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BACKGROUND_COLOR + background color(in 32bpp format) for any pixels not within the bufffer range specified by the ULC/LRC + 0 + 32 + read-write + + + + + HW_INPUT_FETCH_BACKGROUND_COLOR_CH1 + no description available + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + BACKGROUND_COLOR + background color(in 32bpp format) for any pixels not within the bufffer range specified by the ULC/LRC + 0 + 32 + read-write + + + + + HW_INPUT_FETCH_PITCH + no description available + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_INPUT_PITCH + This field indicates the channel 0 input pitch + 0 + 16 + read-write + + + CH1_INPUT_PITCH + This field indicates the channel 1 input pitch + 0x10 + 16 + read-write + + + + + HW_INPUT_FETCH_SHIFT_CTRL_CH0 + no description available + 0x520 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + INPUT_ACTIVE_BPP + no description available + 0 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x2 + 6 + read-only + + + EXPAND_FORMAT + Select Pixel format + 0x8 + 3 + read-write + + + 0 + RGB 565 + 0 + + + 1 + RGB 555 + 0x1 + + + 2 + ARGB 1555 + 0x2 + + + 3 + RGB 444 + 0x3 + + + 4 + ARGB 4444 + 0x4 + + + 5 + YUYV/YVYU + 0x5 + + + 6 + UYVY/VYUY + 0x6 + + + 7 + YUV422_2P + 0x7 + + + + + EXPAND_EN + no description available + 0xB + 1 + read-write + + + 0 + channel0 format expanding disable + 0 + + + 1 + channel0 format expanding enable + 0x1 + + + + + SHIFT_BYPASS + no description available + 0xC + 1 + read-write + + + 0 + channel0 data will do shift function + 0 + + + 1 + channel0 will bypass shift function + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0xD + 19 + read-only + + + + + HW_INPUT_FETCH_SHIFT_CTRL_CH1 + no description available + 0x530 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + INPUT_ACTIVE_BPP + no description available + 0 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x2 + 6 + read-only + + + EXPAND_FORMAT + Select Pixel format + 0x8 + 3 + read-write + + + 0 + RGB 565 + 0 + + + 1 + RGB 555 + 0x1 + + + 2 + ARGB 1555 + 0x2 + + + 3 + RGB 444 + 0x3 + + + 4 + ARGB 4444 + 0x4 + + + 5 + YUYV/YVYU + 0x5 + + + 6 + UYVY/VYUY + 0x6 + + + 7 + YUV422_2P + 0x7 + + + + + EXPAND_EN + no description available + 0xB + 1 + read-write + + + 0 + channel1 format expanding disable + 0 + + + 1 + channel1 format expanding enable + 0x1 + + + + + SHIFT_BYPASS + no description available + 0xC + 1 + read-write + + + 0 + channel1 data will do shift function + 0 + + + 1 + channel1 will bypass shift function + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0xD + 19 + read-only + + + + + HW_INPUT_FETCH_SHIFT_OFFSET_CH0 + no description available + 0x540 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET0 + Shift Offset for channel 0 componnent 0. + 0 + 5 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x5 + 3 + read-only + + + OFFSET1 + Shift Offset for channel 0 componnent 1. + 0x8 + 5 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xD + 3 + read-only + + + OFFSET2 + Shift Offset for channel 0 componnent 2. + 0x10 + 5 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x15 + 3 + read-only + + + OFFSET3 + Shift Offset for channel 0 componnent 3. + 0x18 + 5 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1D + 3 + read-only + + + + + HW_INPUT_FETCH_SHIFT_OFFSET_CH1 + no description available + 0x550 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET0 + Shift Offset for channel 1 componnent 0. + 0 + 5 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x5 + 3 + read-only + + + OFFSET1 + Shift Offset for channel 1 componnent 1. + 0x8 + 5 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xD + 3 + read-only + + + OFFSET2 + Shift Offset for channel 1 componnent 2. + 0x10 + 5 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x15 + 3 + read-only + + + OFFSET3 + Shift Offset for channel 1 componnent 3. + 0x18 + 5 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1D + 3 + read-only + + + + + HW_INPUT_FETCH_SHIFT_WIDTH_CH0 + no description available + 0x560 + 32 + read-write + 0x8888 + 0xFFFFFFFF + + + WIDTH0 + Shift Width for channel 0 componnent 0. + 0 + 4 + read-write + + + WIDTH1 + Shift Width for channel 0 componnent 1. + 0x4 + 4 + read-write + + + WIDTH2 + Shift Width for channel 0 componnent 2. + 0x8 + 4 + read-write + + + WIDTH3 + Shift Width for channel 0 componnent 3. + 0xC + 4 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_INPUT_FETCH_SHIFT_WIDTH_CH1 + no description available + 0x570 + 32 + read-write + 0x8888 + 0xFFFFFFFF + + + WIDTH0 + Shift Width for channel 1 componnent 0. + 0 + 4 + read-write + + + WIDTH1 + Shift Width for channel 1 componnent 1. + 0x4 + 4 + read-write + + + WIDTH2 + Shift Width for channel 1 componnent 2. + 0x8 + 4 + read-write + + + WIDTH3 + Shift Width for channel 1 componnent 3. + 0xC + 4 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_INPUT_FETCH_ADDR_0_CH0 + no description available + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_INPUT_FETCH_ADDR_1_CH0 + no description available + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_INPUT_FETCH_ADDR_0_CH1 + no description available + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_INPUT_FETCH_ADDR_1_CH1 + no description available + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_INPUT_STORE_CTRL_CH0 + Store engine Control Channel 0 Register + 0x5C0 + 32 + read-write + 0x20200 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + Store function is disable + 0 + + + 1 + Store function is enable + 0x1 + + + + + BLOCK_EN + Choses the store mode. + 0x1 + 1 + read-write + + + 0 + Store in scan mode + 0 + + + 1 + Store in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the store engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the prefetch engine is disabled + 0 + + + 1 + Handshake with the prefetch engine is enabled + 0x1 + + + + + ARRAY_EN + no description available + 0x4 + 1 + read-write + + + 0 + Array Handshake Disabled + 0 + + + 1 + Array Handshake Enabled + 0x1 + + + + + ARRAY_LINE_NUM + Selects Array Size + 0x5 + 2 + read-write + + + 0 + Using 1x1 Array + 0 + + + 1 + Using 3x3 Array + 0x1 + + + 2 + Using 5x5 Array + 0x2 + + + 3 + Using 5x5 Array + 0x3 + + + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + STORE_BYPASS_EN + store bypass enable + 0x8 + 1 + read-write + + + 0 + store bypass mode disable. + 0 + + + 1 + store bypass mode enable. Data will bypass to store output. + 0x1 + + + + + STORE_MEMORY_EN + store memory enable + 0x9 + 1 + read-write + + + 0 + store memory mode disable. + 0 + + + 1 + store memory mode enable. Data will store to memory + 0x1 + + + + + PACK_IN_SEL + pack_in_sel + 0xA + 1 + read-write + + + 0 + select 64 shift out data to pack + 0 + + + 1 + select low 32 bit shift out data to pack + 0x1 + + + + + FILL_DATA_EN + fill data enable + 0xB + 1 + read-write + + + 0 + Fill data mode disable. + 0 + + + 1 + Fill data mode enable. When using fill_data mode, store_engine will store fixed data defined in fill_data register + 0x1 + + + + + RSVD2 + Reserved, always set to zero. + 0xC + 4 + read-only + + + WR_NUM_BYTES + Bytes in a write burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes + 0 + + + 16_bytes + 16 bytes + 0x1 + + + 32_bytes + 32 bytes + 0x2 + + + 64_bytes + 64 bytes + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x12 + 6 + read-only + + + COMBINE_2CHANNEL + Combine 2 channel Enable + 0x18 + 1 + read-write + + + 0 + combine 2 channel disable + 0 + + + 1 + combine 2 channel enable + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0x19 + 6 + read-only + + + ARBIT_EN + Arbitration Enable + 0x1F + 1 + read-write + + + 0 + Arbitration disable. If using 2 channels, will output 2 axi bus sets + 0 + + + 1 + Arbitration enable. If using 2 channel, will only output 1 axi bus sets + 0x1 + + + + + + + HW_INPUT_STORE_CTRL_CH1 + Store engine Control Channel 1 Register + 0x5D0 + 32 + read-write + 0x20200 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + Store function is disable + 0 + + + 1 + Store function is enable + 0x1 + + + + + BLOCK_EN + Choses the store mode. + 0x1 + 1 + read-write + + + 0 + Store in scan mode + 0 + + + 1 + Store in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the fetch engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the fetch engine is disabled + 0 + + + 1 + Handshake with the fetch engine is enabled + 0x1 + + + + + ARRAY_EN + no description available + 0x4 + 1 + read-write + + + 0 + Array Handshake Disabled + 0 + + + 1 + Array Handshake Enabled + 0x1 + + + + + ARRAY_LINE_NUM + Selects Array Size + 0x5 + 2 + read-write + + + 0 + Using 1x1 Array + 0 + + + 1 + Using 3x3 Array + 0x1 + + + 2 + Using 5x5 Array + 0x2 + + + 3 + Using 5x5 Array + 0x3 + + + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + STORE_BYPASS_EN + enable bit for store bypass + 0x8 + 1 + read-write + + + 0 + store bypass mode disable. + 0 + + + 1 + store bypass mode enable. Data will bypass to store output. + 0x1 + + + + + STORE_MEMORY_EN + store memory enable + 0x9 + 1 + read-write + + + 0 + store memory mode disable. + 0 + + + 1 + store memory mode enable. Data will store to memory. + 0x1 + + + + + PACK_IN_SEL + pack_in_sel + 0xA + 1 + read-write + + + 0 + select 64 shift out data to pack + 0 + + + 1 + select channel 0 high 32 bit shift out data to pack + 0x1 + + + + + RSVD1 + Reserved, always set to zero. + 0xB + 5 + read-only + + + WR_NUM_BYTES + Bytes in a write burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes + 0 + + + 16_bytes + 16 bytes + 0x1 + + + 32_bytes + 32 bytes + 0x2 + + + 64_bytes + 64 bytes + 0x3 + + + + + RSVD0 + Reserved, always set to zero. + 0x12 + 14 + read-only + + + + + HW_INPUT_STORE_STATUS_CH0 + Store engine status Channel 0 Register + 0x5E0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STORE_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + STORE_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_INPUT_STORE_STATUS_CH1 + Store engine status Channel 1 Register + 0x5F0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STORE_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + STORE_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_INPUT_STORE_SIZE_CH0 + no description available + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_WIDTH + actual output width -1 + 0 + 16 + read-write + + + OUT_HEIGHT + actual output height -1 + 0x10 + 16 + read-write + + + + + HW_INPUT_STORE_SIZE_CH1 + no description available + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_WIDTH + actual output width -1 + 0 + 16 + read-write + + + OUT_HEIGHT + actual output height -1 + 0x10 + 16 + read-write + + + + + HW_INPUT_STORE_PITCH + no description available + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_OUT_PITCH + This field indicates the channel 0 input pitch + 0 + 16 + read-write + + + CH1_OUT_PITCH + This field indicates the channel 1 input pitch + 0x10 + 16 + read-write + + + + + HW_INPUT_STORE_SHIFT_CTRL_CH0 + no description available + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD2 + Reserved, always set to zero. + 0 + 2 + read-only + + + OUTPUT_ACTIVE_BPP + no description available + 0x2 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + OUT_YUV422_1P_EN + Enable for YUV422 1 plane + 0x4 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + OUT_YUV422_2P_EN + Enable for YUV422 2 plane + 0x5 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + RSVD1 + Reserved, always set to zero. + 0x6 + 1 + read-only + + + SHIFT_BYPASS + CH0 shift bypass + 0x7 + 1 + read-write + + + 0 + data will do shift processing. + 0 + + + 1 + data will bypass shift module. + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0x8 + 24 + read-only + + + + + HW_INPUT_STORE_SHIFT_CTRL_CH1 + no description available + 0x640 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD2 + Reserved, always set to zero. + 0 + 2 + read-only + + + OUTPUT_ACTIVE_BPP + no description available + 0x2 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + OUT_YUV422_1P_EN + Enable for YUV422 1 plane + 0x4 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + OUT_YUV422_2P_EN + Enable for YUV422 2 plane + 0x5 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0x6 + 26 + read-only + + + + + HW_INPUT_STORE_ADDR_0_CH0 + no description available + 0x690 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_INPUT_STORE_ADDR_1_CH0 + no description available + 0x6A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_INPUT_STORE_FILL_DATA_CH0 + no description available + 0x6B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FILL_DATA_CH0 + when using fill_data mode,store engine channel0 will store the fill_data value defined here. + 0 + 32 + read-write + + + + + HW_INPUT_STORE_ADDR_0_CH1 + no description available + 0x6C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_INPUT_STORE_ADDR_1_CH1 + no description available + 0x6D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK0_H_CH0 + no description available + 0x6E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK0_H_CH0 + data mask0 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK0_L_CH0 + no description available + 0x6F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK0_L_CH0 + data mask0 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK1_H_CH0 + no description available + 0x700 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK1_H_CH0 + data mask1 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK1_L_CH0 + no description available + 0x710 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK1_L_CH0 + data mask1 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK2_H_CH0 + no description available + 0x720 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK2_H_CH0 + data mask2 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK2_L_CH0 + no description available + 0x730 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK2_L_CH0 + data mask2 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK3_H_CH0 + no description available + 0x740 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK3_H_CH0 + data mask3 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK3_L_CH0 + no description available + 0x750 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK3_L_CH0 + data mask3 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK4_H_CH0 + no description available + 0x760 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK4_H_CH0 + data mask4 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK4_L_CH0 + no description available + 0x770 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK4_L_CH0 + data mask4 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK5_H_CH0 + no description available + 0x780 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK5_H_CH0 + data mask5 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK5_L_CH0 + no description available + 0x790 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK5_L_CH0 + data mask5 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK6_H_CH0 + no description available + 0x7A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK6_H_CH0 + data mask6 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK6_L_CH0 + no description available + 0x7B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK6_L_CH0 + data mask6 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK7_H_CH0 + no description available + 0x7C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK7_H_CH0 + data mask7 high byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_MASK7_L_CH0 + no description available + 0x7E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK7_L_CH0 + data mask7 low byte + 0 + 32 + read-write + + + + + HW_INPUT_STORE_D_SHIFT_L_CH0 + no description available + 0x7F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_SHIFT_WIDTH0 + data shift width 0 + 0 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x6 + 1 + read-only + + + D_SHIFT_FLAG0 + data shift flag 0 + 0x7 + 1 + read-write + + + D_SHIFT_WIDTH1 + data shift width 1 + 0x8 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xE + 1 + read-only + + + D_SHIFT_FLAG1 + data shift flag 1 + 0xF + 1 + read-write + + + D_SHIFT_WIDTH2 + data shift width 2 + 0x10 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x16 + 1 + read-only + + + D_SHIFT_FLAG2 + data shift flag 2 + 0x17 + 1 + read-write + + + D_SHIFT_WIDTH3 + data shift width 3 + 0x18 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1E + 1 + read-only + + + D_SHIFT_FLAG3 + data shift flag 3 + 0x1F + 1 + read-write + + + + + HW_INPUT_STORE_D_SHIFT_H_CH0 + no description available + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_SHIFT_WIDTH4 + data shift width 4 + 0 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x6 + 1 + read-only + + + D_SHIFT_FLAG4 + data shift flag 4 + 0x7 + 1 + read-write + + + D_SHIFT_WIDTH5 + data shift width 5 + 0x8 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xE + 1 + read-only + + + D_SHIFT_FLAG5 + data shift flag 5 + 0xF + 1 + read-write + + + D_SHIFT_WIDTH6 + data shift width 6 + 0x10 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x16 + 1 + read-only + + + D_SHIFT_FLAG6 + data shift flag 6 + 0x17 + 1 + read-write + + + D_SHIFT_WIDTH7 + data shift width 3 + 0x18 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1E + 1 + read-only + + + D_SHIFT_FLAG7 + data shift flag 7 + 0x1F + 1 + read-write + + + + + HW_INPUT_STORE_F_SHIFT_L_CH0 + no description available + 0x810 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_SHIFT_WIDTH0 + flag shift width 0 + 0 + 6 + read-write + + + F_SHIFT_FLAG0 + flag shift flag0 + 0x6 + 1 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + F_SHIFT_WIDTH1 + flag shift width 1 + 0x8 + 6 + read-write + + + F_SHIFT_FLAG1 + flag shift flag1 + 0xE + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xF + 1 + read-only + + + F_SHIFT_WIDTH2 + flag shift width 2 + 0x10 + 6 + read-write + + + F_SHIFT_FLAG2 + flag shift flag2 + 0x16 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x17 + 1 + read-only + + + F_SHIFT_WIDTH3 + flag shift width 3 + 0x18 + 6 + read-write + + + F_SHIFT_FLAG3 + flag shift flag3 + 0x1E + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1F + 1 + read-only + + + + + HW_INPUT_STORE_F_SHIFT_H_CH0 + no description available + 0x820 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_SHIFT_WIDTH4 + flag shift width 4 + 0 + 6 + read-write + + + F_SHIFT_FLAG4 + flag shift flag4 + 0x6 + 1 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + F_SHIFT_WIDTH5 + flag shift width 5 + 0x8 + 6 + read-write + + + F_SHIFT_FLAG5 + flag shift flag5 + 0xE + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xF + 1 + read-only + + + F_SHIFT_WIDTH6 + flag shift width 5 + 0x10 + 6 + read-write + + + F_SHIFT_FLAG6 + flag shift flag6 + 0x16 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x17 + 1 + read-only + + + F_SHIFT_WIDTH7 + flag shift width 7 + 0x18 + 6 + read-write + + + F_SHIFT_FLAG7 + flag shift flag7 + 0x1E + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1F + 1 + read-only + + + + + HW_INPUT_STORE_F_MASK_L_CH0 + no description available + 0x830 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_MASK0 + flag mask0 + 0 + 8 + read-write + + + F_MASK1 + flag mask1 + 0x8 + 8 + read-write + + + F_MASK2 + flag mask2 + 0x10 + 8 + read-write + + + F_MASK3 + flag mask3 + 0x18 + 8 + read-write + + + + + HW_INPUT_STORE_F_MASK_H_CH0 + no description available + 0x840 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_MASK4 + flag mask4 + 0 + 8 + read-write + + + F_MASK5 + flag mask5 + 0x8 + 8 + read-write + + + F_MASK6 + flag mask6 + 0x10 + 8 + read-write + + + F_MASK7 + flag mask7 + 0x18 + 8 + read-write + + + + + HW_DITHER_FETCH_CTRL_CH0 + Pre-fetch engine Control Channel 0 Register + 0x850 + 32 + read-write + 0x20000 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + Prefetch function is disable + 0 + + + 1 + Prefetch function is enable + 0x1 + + + + + BLOCK_EN + Choses the prefetch mode. + 0x1 + 1 + read-write + + + 0 + Prefetch in scan mode + 0 + + + 1 + Prefetch in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the store engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the store engine is disabled + 0 + + + 1 + Handshake with the store engine is enabled + 0x1 + + + + + BYPASS_PIXEL_EN + Selects Channel 0 pixel source + 0x4 + 1 + read-write + + + 0 + Channel 0 is from memory + 0 + + + 1 + Channel 0 is from previous process engine + 0x1 + + + + + HIGH_BYTE + channel 0 high byte selection + 0x5 + 1 + read-write + + + 0 + In 64 bit mode, the output high byte will use channel1. + 0 + + + 1 + In 64 bit mode, the output high byte will use channel0 + 0x1 + + + + + RSVD4 + Reserved, always set to zero. + 0x6 + 3 + read-only + + + HFLIP + Enables HFLIP. + 0x9 + 1 + read-write + + + 0 + HFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + VFLIP + Enables VFLIP + 0xA + 1 + read-write + + + 0 + VFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + RSVD3 + Reserved, always set to zero. + 0xB + 1 + read-only + + + ROTATION_ANGLE + no description available + 0xC + 2 + read-write + + + ROT_0 + Rotate image by 0 degrees. + 0 + + + ROT_90 + Rotate image by 90 degrees. + 0x1 + + + ROT_180 + Rotate image by 180 degrees. + 0x2 + + + ROT_270 + Rotate image by 270 degrees. + 0x3 + + + + + RSVD2 + Reserved, always set to zero. + 0xE + 2 + read-only + + + RD_NUM_BYTES + Bytes in a read burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes. + 0 + + + 16_bytes + 16 bytes. + 0x1 + + + 32_bytes + 32 bytes. + 0x2 + + + 64_bytes + 64 bytes. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x12 + 6 + read-only + + + HANDSHAKE_SCAN_LINE_NUM + scan handshake line number + 0x18 + 2 + read-write + + + 0 + 1 line. + 0 + + + 1 + 8 lines + 0x1 + + + 2 + 16 lines + 0x2 + + + 3 + 16 lines + 0x3 + + + + + RSVD0 + Reserved, always set to zero. + 0x1A + 5 + read-only + + + ARBIT_EN + Enables Arbitration + 0x1F + 1 + read-write + + + 0 + Arbitration disable. If using 2 channels, will output 2 axi bus sets. + 0 + + + 1 + Arbitration enable. If using 2 channel, will only output 1 axi bus sets + 0x1 + + + + + + + HW_DITHER_FETCH_CTRL_CH1 + Pre-fetch engine Control Channel 1 Register + 0x860 + 32 + read-write + 0x20000 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + Prefetch function is disable + 0 + + + 1 + Prefetch function is enable + 0x1 + + + + + BLOCK_EN + Choses the prefetch mode. + 0x1 + 1 + read-write + + + 0 + Prefetch in scan mode + 0 + + + 1 + Prefetch in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the store engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the store engine is disabled + 0 + + + 1 + Handshake with the store engine is enabled + 0x1 + + + + + BYPASS_PIXEL_EN + Selects Channel 1 pixel source + 0x4 + 1 + read-write + + + 0 + Channel 1 is from memory + 0 + + + 1 + Channel 1 is from previous process engine + 0x1 + + + + + RSVD4 + Reserved, always set to zero. + 0x5 + 4 + read-only + + + HFLIP + Enables HFLIP. + 0x9 + 1 + read-write + + + 0 + HFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + VFLIP + Enables VFLIP + 0xA + 1 + read-write + + + 0 + VFLIP disable + 0 + + + 1 + VFLIP enable + 0x1 + + + + + RSVD3 + Reserved, always set to zero. + 0xB + 1 + read-only + + + ROTATION_ANGLE + no description available + 0xC + 2 + read-write + + + ROT_0 + Rotate image by 0 degrees. + 0 + + + ROT_90 + Rotate image by 90 degrees. + 0x1 + + + ROT_180 + Rotate image by 180 degrees. + 0x2 + + + ROT_270 + Rotate image by 270 degrees. + 0x3 + + + + + RSVD2 + Reserved, always set to zero. + 0xE + 2 + read-only + + + RD_NUM_BYTES + Bytes in a read burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes. + 0 + + + 16_bytes + 16 bytes. + 0x1 + + + 32_bytes + 32 bytes. + 0x2 + + + 64_bytes + 64 bytes. + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x12 + 6 + read-only + + + HANDSHAKE_SCAN_LINE_NUM + scan handshake line number + 0x18 + 2 + read-write + + + 0 + 1 line. + 0 + + + 1 + 8 lines + 0x1 + + + 2 + 16 lines + 0x2 + + + 3 + 16 lines + 0x3 + + + + + RSVD0 + Reserved, always set to zero. + 0x1A + 6 + read-only + + + + + HW_DITHER_FETCH_STATUS_CH0 + Pre-fetch engine status Channel 0 Register + 0x870 + 32 + read-only + 0 + 0xFFFFFFFF + + + PREFETCH_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + PREFETCH_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_DITHER_FETCH_STATUS_CH1 + Store engine status Channel 1 Register + 0x880 + 32 + read-only + 0 + 0xFFFFFFFF + + + PREFETCH_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + PREFETCH_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0 + no description available + 0x890 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_ULC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_ULC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0 + no description available + 0x8A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_LRC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_LRC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1 + no description available + 0x8B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_ULC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_ULC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1 + no description available + 0x8C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE_SIZE_LRC_X + This field indicates the upper left X-coordinate(in pixels) of the active surface of the total input memory + 0 + 16 + read-write + + + ACTIVE_SIZE_LRC_Y + This field indicates the upper left Y-coordinate(in pixels) of the active surface of the total input memory + 0x10 + 16 + read-write + + + + + HW_DITHER_FETCH_SIZE_CH0 + no description available + 0x8D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_TOTAL_WIDTH + actual total widht -1 + 0 + 16 + read-write + + + INPUT_TOTAL_HEIGHT + actual total height -1 + 0x10 + 16 + read-write + + + + + HW_DITHER_FETCH_SIZE_CH1 + no description available + 0x8E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_TOTAL_WIDTH + actual_total_width -1 + 0 + 16 + read-write + + + INPUT_TOTAL_HEIGHT + acutal total height -1 + 0x10 + 16 + read-write + + + + + HW_DITHER_FETCH_BACKGROUND_COLOR_CH0 + no description available + 0x8F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BACKGROUND_COLOR + background color(in 32bpp format) for any pixels not within the bufffer range specified by the ULC/LRC + 0 + 32 + read-write + + + + + HW_DITHER_FETCH_BACKGROUND_COLOR_CH1 + no description available + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + BACKGROUND_COLOR + background color(in 32bpp format) for any pixels not within the bufffer range specified by the ULC/LRC + 0 + 32 + read-write + + + + + HW_DITHER_FETCH_PITCH + no description available + 0x910 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_INPUT_PITCH + This field indicates the channel 0 input pitch + 0 + 16 + read-write + + + CH1_INPUT_PITCH + This field indicates the channel 1 input pitch + 0x10 + 16 + read-write + + + + + HW_DITHER_FETCH_SHIFT_CTRL_CH0 + no description available + 0x920 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + INPUT_ACTIVE_BPP + no description available + 0 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x2 + 6 + read-only + + + EXPAND_FORMAT + Select Pixel format + 0x8 + 3 + read-write + + + 0 + RGB 565 + 0 + + + 1 + RGB 555 + 0x1 + + + 2 + ARGB 1555 + 0x2 + + + 3 + RGB 444 + 0x3 + + + 4 + ARGB 4444 + 0x4 + + + 5 + YUYV/YVYU + 0x5 + + + 6 + UYVY/VYUY + 0x6 + + + 7 + YUV422_2P + 0x7 + + + + + EXPAND_EN + no description available + 0xB + 1 + read-write + + + 0 + channel0 format expanding disable + 0 + + + 1 + channel0 format expanding enable + 0x1 + + + + + SHIFT_BYPASS + no description available + 0xC + 1 + read-write + + + 0 + channel0 data will do shift function + 0 + + + 1 + channel0 will bypass shift function + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0xD + 19 + read-only + + + + + HW_DITHER_FETCH_SHIFT_CTRL_CH1 + no description available + 0x930 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + INPUT_ACTIVE_BPP + no description available + 0 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x2 + 6 + read-only + + + EXPAND_FORMAT + Select Pixel format + 0x8 + 3 + read-write + + + 0 + RGB 565 + 0 + + + 1 + RGB 555 + 0x1 + + + 2 + ARGB 1555 + 0x2 + + + 3 + RGB 444 + 0x3 + + + 4 + ARGB 4444 + 0x4 + + + 5 + YUYV/YVYU + 0x5 + + + 6 + UYVY/VYUY + 0x6 + + + 7 + YUV422_2P + 0x7 + + + + + EXPAND_EN + no description available + 0xB + 1 + read-write + + + 0 + channel1 format expanding disable + 0 + + + 1 + channel1 format expanding enable + 0x1 + + + + + SHIFT_BYPASS + no description available + 0xC + 1 + read-write + + + 0 + channel1 data will do shift function + 0 + + + 1 + channel1 will bypass shift function + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0xD + 19 + read-only + + + + + HW_DITHER_FETCH_SHIFT_OFFSET_CH0 + no description available + 0x940 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET0 + Shift Offset for channel 0 componnent 0. + 0 + 5 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x5 + 3 + read-only + + + OFFSET1 + Shift Offset for channel 0 componnent 1. + 0x8 + 5 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xD + 3 + read-only + + + OFFSET2 + Shift Offset for channel 0 componnent 2. + 0x10 + 5 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x15 + 3 + read-only + + + OFFSET3 + Shift Offset for channel 0 componnent 3. + 0x18 + 5 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1D + 3 + read-only + + + + + HW_DITHER_FETCH_SHIFT_OFFSET_CH1 + no description available + 0x950 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET0 + Shift Offset for channel 1 componnent 0. + 0 + 5 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x5 + 3 + read-only + + + OFFSET1 + Shift Offset for channel 1 componnent 1. + 0x8 + 5 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xD + 3 + read-only + + + OFFSET2 + Shift Offset for channel 1 componnent 2. + 0x10 + 5 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x15 + 3 + read-only + + + OFFSET3 + Shift Offset for channel 1 componnent 3. + 0x18 + 5 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1D + 3 + read-only + + + + + HW_DITHER_FETCH_SHIFT_WIDTH_CH0 + no description available + 0x960 + 32 + read-write + 0x8888 + 0xFFFFFFFF + + + WIDTH0 + Shift Width for channel 0 componnent 0. + 0 + 4 + read-write + + + WIDTH1 + Shift Width for channel 0 componnent 1. + 0x4 + 4 + read-write + + + WIDTH2 + Shift Width for channel 0 componnent 2. + 0x8 + 4 + read-write + + + WIDTH3 + Shift Width for channel 0 componnent 3. + 0xC + 4 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_DITHER_FETCH_SHIFT_WIDTH_CH1 + no description available + 0x970 + 32 + read-write + 0x8888 + 0xFFFFFFFF + + + WIDTH0 + Shift Width for channel 1 componnent 0. + 0 + 4 + read-write + + + WIDTH1 + Shift Width for channel 1 componnent 1. + 0x4 + 4 + read-write + + + WIDTH2 + Shift Width for channel 1 componnent 2. + 0x8 + 4 + read-write + + + WIDTH3 + Shift Width for channel 1 componnent 3. + 0xC + 4 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_DITHER_FETCH_ADDR_0_CH0 + no description available + 0x980 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_DITHER_FETCH_ADDR_1_CH0 + no description available + 0x990 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_DITHER_FETCH_ADDR_0_CH1 + no description available + 0x9A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_DITHER_FETCH_ADDR_1_CH1 + no description available + 0x9B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INPUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_DITHER_STORE_CTRL_CH0 + Store engine Control Channel 0 Register + 0x9C0 + 32 + read-write + 0x20200 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + Store function is disable + 0 + + + 1 + Store function is enable + 0x1 + + + + + BLOCK_EN + Choses the store mode. + 0x1 + 1 + read-write + + + 0 + Store in scan mode + 0 + + + 1 + Store in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the store engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the prefetch engine is disabled + 0 + + + 1 + Handshake with the prefetch engine is enabled + 0x1 + + + + + ARRAY_EN + no description available + 0x4 + 1 + read-write + + + 0 + Array Handshake Disabled + 0 + + + 1 + Array Handshake Enabled + 0x1 + + + + + ARRAY_LINE_NUM + Selects Array Size + 0x5 + 2 + read-write + + + 0 + Using 1x1 Array + 0 + + + 1 + Using 3x3 Array + 0x1 + + + 2 + Using 5x5 Array + 0x2 + + + 3 + Using 5x5 Array + 0x3 + + + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + STORE_BYPASS_EN + enable bit for store bypass + 0x8 + 1 + read-write + + + 0 + store bypass mode disable. + 0 + + + 1 + store bypass mode enable. Data will bypass to store output. + 0x1 + + + + + STORE_MEMORY_EN + store memory enable + 0x9 + 1 + read-write + + + 0 + store memory mode disable. + 0 + + + 1 + store memory mode enable. Data will store to memory + 0x1 + + + + + PACK_IN_SEL + pack_in_sel + 0xA + 1 + read-write + + + 0 + select 64 shift out data to pack + 0 + + + 1 + select low 32 bit shift out data to pack + 0x1 + + + + + FILL_DATA_EN + enable bit for fill data + 0xB + 1 + read-write + + + 0 + Fill data mode disable. + 0 + + + 1 + Fill data mode enable. When using fill_data mode, store_engine will store fixed data defined in fill_data register + 0x1 + + + + + RSVD2 + Reserved, always set to zero. + 0xC + 4 + read-only + + + WR_NUM_BYTES + Bytes in a write burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes + 0 + + + 16_bytes + 16 bytes + 0x1 + + + 32_bytes + 32 bytes + 0x2 + + + 64_bytes + 64 bytes + 0x3 + + + + + RSVD1 + Reserved, always set to zero. + 0x12 + 6 + read-only + + + COMBINE_2CHANNEL + Combine 2 channel Enable + 0x18 + 1 + read-write + + + 0 + combine 2 channel disable + 0 + + + 1 + combine 2 channel enable + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0x19 + 6 + read-only + + + ARBIT_EN + Arbitration Enable + 0x1F + 1 + read-write + + + 0 + Arbitration disable. If using 2 channels, will output 2 axi bus sets + 0 + + + 1 + Arbitration enable. If using 2 channel, will only output 1 axi bus sets + 0x1 + + + + + + + HW_DITHER_STORE_CTRL_CH1 + Store engine Control Channel 1 Register + 0x9D0 + 32 + read-write + 0x20200 + 0xFFFFFFFF + + + CH_EN + Channel enable. + 0 + 1 + read-write + + + 0 + Store function is disable + 0 + + + 1 + Store function is enable + 0x1 + + + + + BLOCK_EN + Choses the store mode. + 0x1 + 1 + read-write + + + 0 + Store in scan mode + 0 + + + 1 + Store in block mode + 0x1 + + + + + BLOCK_16 + Determines the block sixe. + 0x2 + 1 + read-write + + + 8x8 + Block size is 8x8 + 0 + + + 16x16 + Block size is 16x16 + 0x1 + + + + + HANDSHAKE_EN + Enable bit for handshake with the fetch engine. + 0x3 + 1 + read-write + + + 0 + Handshake with the fetch engine is disabled + 0 + + + 1 + Handshake with the fetch engine is enabled + 0x1 + + + + + ARRAY_EN + no description available + 0x4 + 1 + read-write + + + 0 + Array Handshake Disabled + 0 + + + 1 + Array Handshake Enabled + 0x1 + + + + + ARRAY_LINE_NUM + Selects Array Size + 0x5 + 2 + read-write + + + 0 + Using 1x1 Array + 0 + + + 1 + Using 3x3 Array + 0x1 + + + 2 + Using 5x5 Array + 0x2 + + + 3 + Using 5x5 Array + 0x3 + + + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + STORE_BYPASS_EN + enable bit for store bypass + 0x8 + 1 + read-write + + + 0 + store bypass mode disable. + 0 + + + 1 + store bypass mode enable. Data will bypass to store output. + 0x1 + + + + + STORE_MEMORY_EN + store memory enable + 0x9 + 1 + read-write + + + 0 + store memory mode disable. + 0 + + + 1 + store memory mode enable. Data will store to memory + 0x1 + + + + + PACK_IN_SEL + pack_in_sel + 0xA + 1 + read-write + + + 0 + select 64 shift out data to pack + 0 + + + 1 + select channel 0 high 32 bit shift out data to pack + 0x1 + + + + + RSVD1 + Reserved, always set to zero. + 0xB + 5 + read-only + + + WR_NUM_BYTES + Bytes in a write burst + 0x10 + 2 + read-write + + + 8_bytes + 8 bytes + 0 + + + 16_bytes + 16 bytes + 0x1 + + + 32_bytes + 32 bytes + 0x2 + + + 64_bytes + 64 bytes + 0x3 + + + + + RSVD0 + Reserved, always set to zero. + 0x12 + 14 + read-only + + + + + HW_DITHER_STORE_STATUS_CH0 + Store engine status Channel 0 Register + 0x9E0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STORE_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + STORE_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_DITHER_STORE_STATUS_CH1 + Store engine status Channel 1 Register + 0x9F0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STORE_BLOCK_X + When in scan mode, this field is always 0 + 0 + 16 + read-only + + + STORE_BLOCK_Y + When in scan mode, this field indicates the current Y coordinate of the frame + 0x10 + 16 + read-only + + + + + HW_DITHER_STORE_SIZE_CH0 + no description available + 0xA00 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_WIDTH + actual output width -1 + 0 + 16 + read-write + + + OUT_HEIGHT + actual output height -1 + 0x10 + 16 + read-write + + + + + HW_DITHER_STORE_SIZE_CH1 + no description available + 0xA10 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_WIDTH + actual output width -1 + 0 + 16 + read-write + + + OUT_HEIGHT + actual output height -1 + 0x10 + 16 + read-write + + + + + HW_DITHER_STORE_PITCH + no description available + 0xA20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_OUT_PITCH + This field indicates the channel 0 input pitch + 0 + 16 + read-write + + + CH1_OUT_PITCH + This field indicates the channel 1 input pitch + 0x10 + 16 + read-write + + + + + HW_DITHER_STORE_SHIFT_CTRL_CH0 + no description available + 0xA30 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD2 + Reserved, always set to zero. + 0 + 2 + read-only + + + OUTPUT_ACTIVE_BPP + no description available + 0x2 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + OUT_YUV422_1P_EN + Enable for YUV422 1 plane + 0x4 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + OUT_YUV422_2P_EN + Enable for YUV422 2 plane + 0x5 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + RSVD1 + Reserved, always set to zero. + 0x6 + 1 + read-only + + + SHIFT_BYPASS + CH0 shift bypass + 0x7 + 1 + read-write + + + 0 + data will do shift processing. + 0 + + + 1 + data will bypass shift module. + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0x8 + 24 + read-only + + + + + HW_DITHER_STORE_SHIFT_CTRL_CH1 + no description available + 0xA40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD2 + Reserved, always set to zero. + 0 + 2 + read-only + + + OUTPUT_ACTIVE_BPP + no description available + 0x2 + 2 + read-write + + + 0 + 8 bits + 0 + + + 1 + 16 bits + 0x1 + + + 2 + 32 bits + 0x2 + + + 3 + 32 bits + 0x3 + + + + + OUT_YUV422_1P_EN + Enable for YUV422 1 plane + 0x4 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + OUT_YUV422_2P_EN + Enable for YUV422 2 plane + 0x5 + 1 + read-write + + + 0 + YUYV422 2 plane disabled. + 0 + + + 1 + YUYV422 2 plane enabled. + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0x6 + 26 + read-only + + + + + HW_DITHER_STORE_ADDR_0_CH0 + no description available + 0xA90 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_DITHER_STORE_ADDR_1_CH0 + no description available + 0xAA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_DITHER_STORE_FILL_DATA_CH0 + no description available + 0xAB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FILL_DATA_CH0 + when using fill_data mode,store engine channel0 will store the fill_data value defined here. + 0 + 32 + read-write + + + + + HW_DITHER_STORE_ADDR_0_CH1 + no description available + 0xAC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR0 + input base address0 + 0 + 32 + read-write + + + + + HW_DITHER_STORE_ADDR_1_CH1 + no description available + 0xAD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OUT_BASE_ADDR1 + input base address1 + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK0_H_CH0 + no description available + 0xAE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK0_H_CH0 + data mask0 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK0_L_CH0 + no description available + 0xAF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK0_L_CH0 + data mask0 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK1_H_CH0 + no description available + 0xB00 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK1_H_CH0 + data mask1 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK1_L_CH0 + no description available + 0xB10 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK1_L_CH0 + data mask1 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK2_H_CH0 + no description available + 0xB20 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK2_H_CH0 + data mask2 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK2_L_CH0 + no description available + 0xB30 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK2_L_CH0 + data mask2 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK3_H_CH0 + no description available + 0xB40 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK3_H_CH0 + data mask3 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK3_L_CH0 + no description available + 0xB50 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK3_L_CH0 + data mask3 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK4_H_CH0 + no description available + 0xB60 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK4_H_CH0 + data mask4 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK4_L_CH0 + no description available + 0xB70 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK4_L_CH0 + data mask4 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK5_H_CH0 + no description available + 0xB80 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK5_H_CH0 + data mask5 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK5_L_CH0 + no description available + 0xB90 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK5_L_CH0 + data mask5 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK6_H_CH0 + no description available + 0xBA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK6_H_CH0 + data mask6 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK6_L_CH0 + no description available + 0xBB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK6_L_CH0 + data mask6 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK7_H_CH0 + no description available + 0xBC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK7_H_CH0 + data mask7 high byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_MASK7_L_CH0 + no description available + 0xBD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_MASK7_L_CH0 + data mask7 low byte + 0 + 32 + read-write + + + + + HW_DITHER_STORE_D_SHIFT_L_CH0 + no description available + 0xBE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_SHIFT_WIDTH0 + data shift width 0 + 0 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x6 + 1 + read-only + + + D_SHIFT_FLAG0 + data shift flag 0 + 0x7 + 1 + read-write + + + D_SHIFT_WIDTH1 + data shift width 1 + 0x8 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xE + 1 + read-only + + + D_SHIFT_FLAG1 + data shift flag 1 + 0xF + 1 + read-write + + + D_SHIFT_WIDTH2 + data shift width 2 + 0x10 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x16 + 1 + read-only + + + D_SHIFT_FLAG2 + data shift flag 2 + 0x17 + 1 + read-write + + + D_SHIFT_WIDTH3 + data shift width 3 + 0x18 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1E + 1 + read-only + + + D_SHIFT_FLAG3 + data shift flag 3 + 0x1F + 1 + read-write + + + + + HW_DITHER_STORE_D_SHIFT_H_CH0 + no description available + 0xBF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_SHIFT_WIDTH4 + data shift width 4 + 0 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x6 + 1 + read-only + + + D_SHIFT_FLAG4 + data shift flag 4 + 0x7 + 1 + read-write + + + D_SHIFT_WIDTH5 + data shift width 5 + 0x8 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xE + 1 + read-only + + + D_SHIFT_FLAG5 + data shift flag 5 + 0xF + 1 + read-write + + + D_SHIFT_WIDTH6 + data shift width 6 + 0x10 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x16 + 1 + read-only + + + D_SHIFT_FLAG6 + data shift flag 6 + 0x17 + 1 + read-write + + + D_SHIFT_WIDTH7 + data shift width 3 + 0x18 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1E + 1 + read-only + + + D_SHIFT_FLAG7 + data shift flag 7 + 0x1F + 1 + read-write + + + + + HW_DITHER_STORE_F_SHIFT_L_CH0 + no description available + 0xC00 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_SHIFT_WIDTH0 + flag shift width 0 + 0 + 6 + read-write + + + F_SHIFT_FLAG0 + flag shift flag0 + 0x6 + 1 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + F_SHIFT_WIDTH1 + flag shift width 1 + 0x8 + 6 + read-write + + + F_SHIFT_FLAG1 + flag shift flag1 + 0xE + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xF + 1 + read-only + + + F_SHIFT_WIDTH2 + flag shift width 2 + 0x10 + 6 + read-write + + + F_SHIFT_FLAG2 + flag shift flag2 + 0x16 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x17 + 1 + read-only + + + F_SHIFT_WIDTH3 + flag shift width 3 + 0x18 + 6 + read-write + + + F_SHIFT_FLAG3 + flag shift flag3 + 0x1E + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1F + 1 + read-only + + + + + HW_DITHER_STORE_F_SHIFT_H_CH0 + no description available + 0xC10 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_SHIFT_WIDTH4 + flag shift width 4 + 0 + 6 + read-write + + + F_SHIFT_FLAG4 + flag shift flag4 + 0x6 + 1 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x7 + 1 + read-only + + + F_SHIFT_WIDTH5 + flag shift width 5 + 0x8 + 6 + read-write + + + F_SHIFT_FLAG5 + flag shift flag5 + 0xE + 1 + read-write + + + RSVD2 + Reserved, always set to zero. + 0xF + 1 + read-only + + + F_SHIFT_WIDTH6 + flag shift width 5 + 0x10 + 6 + read-write + + + F_SHIFT_FLAG6 + flag shift flag6 + 0x16 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x17 + 1 + read-only + + + F_SHIFT_WIDTH7 + flag shift width 7 + 0x18 + 6 + read-write + + + F_SHIFT_FLAG7 + flag shift flag7 + 0x1E + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1F + 1 + read-only + + + + + HW_DITHER_STORE_F_MASK_L_CH0 + no description available + 0xC20 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_MASK0 + flag mask0 + 0 + 8 + read-write + + + F_MASK1 + flag mask1 + 0x8 + 8 + read-write + + + F_MASK2 + flag mask2 + 0x10 + 8 + read-write + + + F_MASK3 + flag mask3 + 0x18 + 8 + read-write + + + + + HW_DITHER_STORE_F_MASK_H_CH0 + no description available + 0xC30 + 32 + read-write + 0 + 0xFFFFFFFF + + + F_MASK4 + flag mask4 + 0 + 8 + read-write + + + F_MASK5 + flag mask5 + 0x8 + 8 + read-write + + + F_MASK6 + flag mask6 + 0x10 + 8 + read-write + + + F_MASK7 + flag mask7 + 0x18 + 8 + read-write + + + + + HW_DITHER_CTRL + Dither Control Register 0 + 0x1670 + 32 + read-write + 0x544000 + 0xFFFFFFFF + + + ENABLE0 + Enables the dither engine 0 + 0 + 1 + read-write + + + Disabled + The dither engine 0 will not process any frames. + 0 + + + Enabled + The dither engine 0 is on and ready for processing + 0x1 + + + + + ENABLE1 + Enables the dither engine 1 + 0x1 + 1 + read-write + + + Disabled + The dither engine 1 will not process any frames. + 0 + + + Enabled + The dither engine 1 is on and ready for processing + 0x1 + + + + + ENABLE2 + Enables the dither engine 2 + 0x2 + 1 + read-write + + + Disabled + The dither engine 2 will not process any frames. + 0 + + + Enabled + The dither engine 2 is on and ready for processing + 0x1 + + + + + DITHER_MODE0 + Dither mode. + 0x3 + 3 + read-write + + + 0 + Pass through. + 0 + + + 1 + Floyd-Steinberg. + 0x1 + + + 2 + Atkinson. + 0x2 + + + 3 + Ordered. + 0x3 + + + 4 + No Dithering, quantization only. + 0x4 + + + + + DITHER_MODE1 + Dither mode. + 0x6 + 3 + read-write + + + 0 + Pass through. + 0 + + + 3 + Ordered. + 0x3 + + + 4 + No Dithering, quantization only. + 0x4 + + + + + DITHER_MODE2 + Dither mode. + 0x9 + 3 + read-write + + + 0 + Pass through. + 0 + + + 3 + Ordered. + 0x3 + + + 4 + No Dithering, quantization only. + 0x4 + + + + + NUM_QUANT_BIT + Number of bits to quantize down to. From 8 to (0-7). + 0xC + 3 + read-write + + + 1 + Quantize down to 1 bit. + 0x1 + + + 2 + Quantize down to 2 bits. + 0x2 + + + 3 + Quantize down to 3 bits. + 0x3 + + + 4 + Quantize down to 4 bits. + 0x4 + + + 5 + Quantize down to 5 bits. + 0x5 + + + 6 + Quantize down to 6 bits. + 0x6 + + + 7 + Quantize down to 7 bits. + 0x7 + + + + + LUT_MODE + Specify to use memory lut to transform pixel + 0xF + 2 + read-write + + + 0 + LUT mode off. + 0 + + + 1 + Use LUT at pre-diter stage. + 0x1 + + + 2 + Use LUT at post-dither stage. + 0x2 + + + + + IDX_MATRIX0_SIZE + For Dither Engine 0 + 0x11 + 2 + read-write + + + 0 + 4x4 + 0 + + + 1 + 8x8 + 0x1 + + + 2 + 16x16 + 0x2 + + + 3 + Input value of index + 0x3 + + + + + IDX_MATRIX1_SIZE + For Dither Engine 1 + 0x13 + 2 + read-write + + + 0 + 4x4 + 0 + + + 1 + 8x8 + 0x1 + + + 2 + 16x16 + 0x2 + + + 3 + Input value of index + 0x3 + + + + + IDX_MATRIX2_SIZE + For Dither Engine 2 + 0x15 + 2 + read-write + + + 0 + 4x4 + 0 + + + 1 + 8x8 + 0x1 + + + 2 + 16x16 + 0x2 + + + 3 + Input value of index + 0x3 + + + + + FINAL_LUT_ENABLE + Enables a final stage register based LUT at the last stage before output + 0x17 + 1 + read-write + + + Disabled + The dither engine 2 will not process any frames. + 0 + + + Enabled + The dither engine 2 is on and ready for processing + 0x1 + + + + + ORDERED_ROUND_MODE + For test purposes + 0x18 + 1 + read-write + + + 0 + Use truncation method. + 0 + + + 1 + Use rounding method. + 0x1 + + + + + RSVD0 + Reserved, always set to zero. + 0x19 + 4 + read-only + + + BUSY2 + When set indicates if the dither engine 2 is busy -- started but not finished processing all of the pixels in the current frame + 0x1D + 1 + read-only + + + BUSY1 + When set indicates if the dither engine 1 is busy -- started but not finished processing all of the pixels in the current frame + 0x1E + 1 + read-only + + + BUSY0 + When set indicates if the dither engine 0 is busy -- started but not finished processing all of the pixels in the current frame + 0x1F + 1 + read-only + + + + + HW_DITHER_FINAL_LUT_DATA0 + Final stage lookup value Register + 0x1680 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA0 + Final stage LUT data value. + 0 + 8 + read-write + + + DATA1 + Final stage LUT data value. + 0x8 + 8 + read-write + + + DATA2 + Final stage LUT data value. + 0x10 + 8 + read-write + + + DATA3 + Final stage LUT data value. + 0x18 + 8 + read-write + + + + + HW_DITHER_FINAL_LUT_DATA1 + Final stage lookup value Register + 0x1690 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA4 + Final stage LUT data value. + 0 + 8 + read-write + + + DATA5 + Final stage LUT data value. + 0x8 + 8 + read-write + + + DATA6 + Final stage LUT data value. + 0x10 + 8 + read-write + + + DATA7 + Final stage LUT data value. + 0x18 + 8 + read-write + + + + + HW_DITHER_FINAL_LUT_DATA2 + Final stage lookup value Register + 0x16A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA8 + Final stage LUT data value. + 0 + 8 + read-write + + + DATA9 + Final stage LUT data value. + 0x8 + 8 + read-write + + + DATA10 + Final stage LUT data value. + 0x10 + 8 + read-write + + + DATA11 + Final stage LUT data value. + 0x18 + 8 + read-write + + + + + HW_DITHER_FINAL_LUT_DATA3 + Final stage lookup value Register + 0x16B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA12 + Final stage LUT data value. + 0 + 8 + read-write + + + DATA13 + Final stage LUT data value. + 0x8 + 8 + read-write + + + DATA14 + Final stage LUT data value. + 0x10 + 8 + read-write + + + DATA15 + Final stage LUT data value. + 0x18 + 8 + read-write + + + + + HW_HIST_A_CTRL + Histogram Control Register. + 0x2A00 + 32 + read-write + 0x5001F00 + 0xFFFFFFFF + + + ENABLE + Enable the Histogram Engine + 0 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1 + 3 + read-only + + + CLEAR + Write 1 to clear the histogram result and will be self-clear after clear function finished + 0x4 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x5 + 3 + read-only + + + STATUS + Indicates which histogram matched the processed bitmap + 0x8 + 5 + read-only + + + RSVD2 + Reserved, always set to zero. + 0xD + 3 + read-only + + + PIXEL_OFFSET + The offset of the pixel to be used for histogram calculation + 0x10 + 7 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x17 + 1 + read-only + + + PIXEL_WIDTH + The width of the pixel to be used for histogram calculation + 0x18 + 3 + read-write + + + RSVD4 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_HIST_A_MASK + Histogram Pixel Mask Register. + 0x2A10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK_EN + Enable the Pixel Mask Function in Histogram + 0 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1 + 3 + read-only + + + MASK_MODE + Operation mode of pixel mask function + 0x4 + 2 + read-write + + + EQUAL + Run histogram for pixels equal to value0 + 0 + + + NOT_EQUAL + Run histogram for pixels not equal to value0 + 0x1 + + + INSIDE + Run histogram for pixels within the range of value0 to value1 + 0x2 + + + OUTSIDE + Run histogram for pixels outside of the rang of value0 to value1 + 0x3 + + + + + MASK_OFFSET + The offset of the field to be checked against mask condition + 0x6 + 7 + read-write + + + MASK_WIDTH + The width of the field to be checked against mask condition + 0xD + 3 + read-write + + + MASK_VALUE0 + The value0 for mask condition checking + 0x10 + 8 + read-write + + + MASK_VALUE1 + The value1 for mask condition checking + 0x18 + 8 + read-write + + + + + HW_HIST_A_BUF_SIZE + Histogram Pixel Buffer Size Register. + 0x2A20 + 32 + read-write + 0 + 0xFFFFFFFF + + + WIDTH + This indicate the buffer width in pixels + 0 + 12 + read-write + + + RSVD1 + Reserved. This field always reads 0. + 0xC + 4 + read-only + + + HEIGHT + This indicate the buffer height in pixels + 0x10 + 12 + read-write + + + RSVD0 + Reserved. This field always reads 0. + 0x1C + 4 + read-only + + + + + HW_HIST_A_TOTAL_PIXEL + Total Number of Pixels Used by Histogram Engine. + 0x2A30 + 32 + read-only + 0 + 0xFFFFFFFF + + + TOTAL_PIXEL + Total number of pixels used by histogram engine, the pixels got masked will be skipped + 0 + 24 + read-only + + + RSVD0 + Reserved. This field always reads 0. + 0x18 + 8 + read-only + + + + + HW_HIST_A_ACTIVE_AREA_X + The X Coordinate Offset for Active Area. + 0x2A40 + 32 + read-only + 0 + 0xFFFFFFFF + + + MIN_X_OFFSET + Minimul X coordinate offset for the active area in histogram processing + 0 + 12 + read-only + + + RSVD0 + Reserved. This field always reads 0. + 0xC + 4 + read-only + + + MAX_X_OFFSET + Maximum X coordinate offset for the active area in histogram processing + 0x10 + 12 + read-only + + + RSVD1 + Reserved. This field always reads 0. + 0x1C + 4 + read-only + + + + + HW_HIST_A_ACTIVE_AREA_Y + The Y Coordinate Offset for Active Area. + 0x2A50 + 32 + read-only + 0 + 0xFFFFFFFF + + + MIN_Y_OFFSET + Minimul Y coordinate offset for the active area in histogram processing + 0 + 12 + read-only + + + RSVD0 + Reserved. This field always reads 0. + 0xC + 4 + read-only + + + MAX_Y_OFFSET + Maximum Y coordinate offset for the active area in histogram processing + 0x10 + 12 + read-only + + + RSVD1 + Reserved. This field always reads 0. + 0x1C + 4 + read-only + + + + + HW_HIST_A_RAW_STAT0 + Histogram Result Based on RAW Pixel Value. + 0x2A60 + 32 + read-only + 0 + 0xFFFFFFFF + + + STAT0 + Lower 32-bit result fo the histogram calculation + 0 + 32 + read-only + + + + + HW_HIST_A_RAW_STAT1 + Histogram Result Based on RAW Pixel Value. + 0x2A70 + 32 + read-only + 0 + 0xFFFFFFFF + + + STAT1 + Higher 32-bit result fo the histogram calculation + 0 + 32 + read-only + + + + + HW_HIST_B_CTRL + Histogram Control Register. + 0x2A80 + 32 + read-write + 0x5001F00 + 0xFFFFFFFF + + + ENABLE + Enable the Histogram Engine + 0 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1 + 3 + read-only + + + CLEAR + Write 1 to clear the histogram result and will be self-clear after clear function finished + 0x4 + 1 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x5 + 3 + read-only + + + STATUS + Indicates which histogram matched the processed bitmap + 0x8 + 5 + read-only + + + RSVD2 + Reserved, always set to zero. + 0xD + 3 + read-only + + + PIXEL_OFFSET + The offset of the pixel to be used for histogram calculation + 0x10 + 7 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x17 + 1 + read-only + + + PIXEL_WIDTH + The width of the pixel to be used for histogram calculation + 0x18 + 3 + read-write + + + RSVD4 + Reserved, always set to zero. + 0x1B + 5 + read-only + + + + + HW_HIST_B_MASK + Histogram Pixel Mask Register. + 0x2A90 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK_EN + Enable the Pixel Mask Function in Histogram + 0 + 1 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x1 + 3 + read-only + + + MASK_MODE + Operation mode of pixel mask function + 0x4 + 2 + read-write + + + EQUAL + Run histogram for pixels equal to value0 + 0 + + + NOT_EQUAL + Run histogram for pixels not equal to value0 + 0x1 + + + INSIDE + Run histogram for pixels within the range of value0 to value1 + 0x2 + + + OUTSIDE + Run histogram for pixels outside of the rang of value0 to value1 + 0x3 + + + + + MASK_OFFSET + The offset of the field to be checked against mask condition + 0x6 + 7 + read-write + + + MASK_WIDTH + The width of the field to be checked against mask condition + 0xD + 3 + read-write + + + MASK_VALUE0 + The value0 for mask condition checking + 0x10 + 8 + read-write + + + MASK_VALUE1 + The value1 for mask condition checking + 0x18 + 8 + read-write + + + + + HW_HIST_B_BUF_SIZE + Histogram Pixel Buffer Size Register. + 0x2AA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + WIDTH + This indicate the buffer width in pixels + 0 + 12 + read-write + + + RSVD1 + Reserved. This field always reads 0. + 0xC + 4 + read-only + + + HEIGHT + This indicate the buffer height in pixels + 0x10 + 12 + read-write + + + RSVD0 + Reserved. This field always reads 0. + 0x1C + 4 + read-only + + + + + HW_HIST_B_TOTAL_PIXEL + Total Number of Pixels Used by Histogram Engine. + 0x2AB0 + 32 + read-only + 0 + 0xFFFFFFFF + + + TOTAL_PIXEL + Total number of pixels used by histogram engine, the pixels got masked will be skipped + 0 + 24 + read-only + + + RSVD0 + Reserved. This field always reads 0. + 0x18 + 8 + read-only + + + + + HW_HIST_B_ACTIVE_AREA_X + The X Coordinate Offset for Active Area. + 0x2AC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + MIN_X_OFFSET + Minimul X coordinate offset for the active area in histogram processing + 0 + 12 + read-only + + + RSVD0 + Reserved. This field always reads 0. + 0xC + 4 + read-only + + + MAX_X_OFFSET + Maximum X coordinate offset for the active area in histogram processing + 0x10 + 12 + read-only + + + RSVD1 + Reserved. This field always reads 0. + 0x1C + 4 + read-only + + + + + HW_HIST_B_ACTIVE_AREA_Y + The Y Coordinate Offset for Active Area. + 0x2AD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + MIN_Y_OFFSET + Minimul Y coordinate offset for the active area in histogram processing + 0 + 12 + read-only + + + RSVD0 + Reserved. This field always reads 0. + 0xC + 4 + read-only + + + MAX_Y_OFFSET + Maximum Y coordinate offset for the active area in histogram processing + 0x10 + 12 + read-only + + + RSVD1 + Reserved. This field always reads 0. + 0x1C + 4 + read-only + + + + + HW_HIST_B_RAW_STAT0 + Histogram Result Based on RAW Pixel Value. + 0x2AE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STAT0 + Lower 32-bit result fo the histogram calculation + 0 + 32 + read-only + + + + + HW_HIST_B_RAW_STAT1 + Histogram Result Based on RAW Pixel Value. + 0x2AF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STAT1 + Higher 32-bit result fo the histogram calculation + 0 + 32 + read-only + + + + + HW_HIST2_PARAM + 2-level Histogram Parameter Register. + 0x2B00 + 32 + read-write + 0xF00 + 0xFFFFFFFF + + + VALUE0 + Black value for 2-level histogram + 0 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE1 + White value for 2-level histogram + 0x8 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xE + 2 + read-only + + + RSVD + Reserved, always set to zero. + 0x10 + 16 + read-only + + + + + HW_HIST4_PARAM + 4-level Histogram Parameter Register. + 0x2B10 + 32 + read-write + 0xF0A0500 + 0xFFFFFFFF + + + VALUE0 + GRAY0 (Black) value for 4-level histogram + 0 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE1 + GRAY1 value for 4-level histogram + 0x8 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE2 + GRAY2 value for 4-level histogram + 0x10 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE3 + GRAY3 (White) value for 4-level histogram + 0x18 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST8_PARAM0 + 8-level Histogram Parameter 0 Register. + 0x2B20 + 32 + read-write + 0x6040200 + 0xFFFFFFFF + + + VALUE0 + GRAY0 (Black) value for 8-level histogram + 0 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE1 + GRAY1 value for 8-level histogram + 0x8 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE2 + GRAY2 value for 8-level histogram + 0x10 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE3 + GRAY3 value for 8-level histogram + 0x18 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST8_PARAM1 + 8-level Histogram Parameter 1 Register. + 0x2B30 + 32 + read-write + 0xF0D0B09 + 0xFFFFFFFF + + + VALUE4 + GRAY4 value for 8-level histogram + 0 + 6 + read-write + + + RSVD4 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE5 + GRAY5 value for 8-level histogram + 0x8 + 6 + read-write + + + RSVD5 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE6 + GRAY6 value for 8-level histogram + 0x10 + 6 + read-write + + + RSVD6 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE7 + GRAY7 (White) value for 8-level histogram + 0x18 + 6 + read-write + + + RSVD7 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST16_PARAM0 + 16-level Histogram Parameter 0 Register. + 0x2B40 + 32 + read-write + 0x3020100 + 0xFFFFFFFF + + + VALUE0 + GRAY0 (Black) value for 16-level histogram + 0 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE1 + GRAY1 value for 16-level histogram + 0x8 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE2 + GRAY2 value for 16-level histogram + 0x10 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE3 + GRAY3 value for 16-level histogram + 0x18 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST16_PARAM1 + 16-level Histogram Parameter 1 Register. + 0x2B50 + 32 + read-write + 0x7060504 + 0xFFFFFFFF + + + VALUE4 + GRAY4 value for 16-level histogram + 0 + 6 + read-write + + + RSVD4 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE5 + GRAY5 value for 16-level histogram + 0x8 + 6 + read-write + + + RSVD5 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE6 + GRAY6 value for 16-level histogram + 0x10 + 6 + read-write + + + RSVD6 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE7 + GRAY7 value for 16-level histogram + 0x18 + 6 + read-write + + + RSVD7 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST16_PARAM2 + 16-level Histogram Parameter 2 Register. + 0x2B60 + 32 + read-write + 0xB0A0908 + 0xFFFFFFFF + + + VALUE8 + GRAY8 value for 16-level histogram + 0 + 6 + read-write + + + RSVD8 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE9 + GRAY9 value for 16-level histogram + 0x8 + 6 + read-write + + + RSVD9 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE10 + GRAY10 value for 16-level histogram + 0x10 + 6 + read-write + + + RSVD10 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE11 + GRAY11 value for 16-level histogram + 0x18 + 6 + read-write + + + RSVD11 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST16_PARAM3 + 16-level Histogram Parameter 3 Register. + 0x2B70 + 32 + read-write + 0xF0E0D0C + 0xFFFFFFFF + + + VALUE12 + GRAY12 value for 16-level histogram + 0 + 6 + read-write + + + RSVD12 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE13 + GRAY13 value for 16-level histogram + 0x8 + 6 + read-write + + + RSVD13 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE14 + GRAY14 value for 16-level histogram + 0x10 + 6 + read-write + + + RSVD14 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE15 + GRAY15 (White) value for 16-level histogram + 0x18 + 6 + read-write + + + RSVD15 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM0 + 32-level Histogram Parameter 0 Register. + 0x2B80 + 32 + read-write + 0x3020100 + 0xFFFFFFFF + + + VALUE0 + GRAY0 (Black) value for 32-level histogram + 0 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE1 + GRAY1 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE2 + GRAY2 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE3 + GRAY3 value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM1 + 32-level Histogram Parameter 1 Register. + 0x2B90 + 32 + read-write + 0x7060504 + 0xFFFFFFFF + + + VALUE4 + GRAY4 value for 32-level histogram + 0 + 6 + read-write + + + RSVD4 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE5 + GRAY5 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD5 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE6 + GRAY6 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD6 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE7 + GRAY7 value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD7 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM2 + 32-level Histogram Parameter 2 Register. + 0x2BA0 + 32 + read-write + 0xB0A0908 + 0xFFFFFFFF + + + VALUE8 + GRAY8 value for 32-level histogram + 0 + 6 + read-write + + + RSVD8 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE9 + GRAY9 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD9 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE10 + GRAY10 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD10 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE11 + GRAY11 value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD11 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM3 + 32-level Histogram Parameter 3 Register. + 0x2BB0 + 32 + read-write + 0xF0E0D0C + 0xFFFFFFFF + + + VALUE12 + GRAY12 value for 32-level histogram + 0 + 6 + read-write + + + RSVD12 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE13 + GRAY13 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD13 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE14 + GRAY14 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD14 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE15 + GRAY15 (White) value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD15 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM4 + 32-level Histogram Parameter 0 Register. + 0x2BC0 + 32 + read-write + 0x3020100 + 0xFFFFFFFF + + + VALUE16 + GRAY16 (Black) value for 32-level histogram + 0 + 6 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE17 + GRAY17 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD1 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE18 + GRAY18 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE19 + GRAY19 value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD3 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM5 + 32-level Histogram Parameter 1 Register. + 0x2BD0 + 32 + read-write + 0x7060504 + 0xFFFFFFFF + + + VALUE20 + GRAY20 value for 32-level histogram + 0 + 6 + read-write + + + RSVD4 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE21 + GRAY21 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD5 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE22 + GRAY22 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD6 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE23 + GRAY23 value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD7 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM6 + 32-level Histogram Parameter 2 Register. + 0x2BE0 + 32 + read-write + 0xB0A0908 + 0xFFFFFFFF + + + VALUE24 + GRAY24 value for 32-level histogram + 0 + 6 + read-write + + + RSVD8 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE25 + GRAY25 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD9 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE26 + GRAY26 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD10 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE27 + GRAY27 value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD11 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_HIST32_PARAM7 + 32-level Histogram Parameter 3 Register. + 0x2BF0 + 32 + read-write + 0xF0E0D0C + 0xFFFFFFFF + + + VALUE28 + GRAY28 value for 32-level histogram + 0 + 6 + read-write + + + RSVD2 + Reserved, always set to zero. + 0x6 + 2 + read-only + + + VALUE29 + GRAY29 value for 32-level histogram + 0x8 + 6 + read-write + + + RSVD13 + Reserved, always set to zero. + 0xE + 2 + read-only + + + VALUE30 + GRAY30 value for 32-level histogram + 0x10 + 6 + read-write + + + RSVD14 + Reserved, always set to zero. + 0x16 + 2 + read-only + + + VALUE31 + GRAY31 (White) value for 32-level histogram + 0x18 + 6 + read-write + + + RSVD15 + Reserved, always set to zero. + 0x1E + 2 + read-only + + + + + HW_COMP_CTRL + no description available + 0x2C00 + 32 + read-write + 0 + 0xFFFFFFFF + + + START + Write to 1 to start operation, self-clear + 0 + 1 + read-write + + + RSVD1 + Reserved. This field always reads 0. + 0x1 + 7 + read-only + + + SW_RESET + Write to 1 to do a software reset to the engine, self-clear. + 0x8 + 1 + read-write + + + RSVD0 + Reserved. This field always reads 0. + 0x9 + 23 + read-only + + + + + HW_COMP_FORMAT0 + no description available + 0x2C10 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLAG_32B + 1 indicate 32-bit for one pixel, 0 for 16-bit + 0 + 1 + read-write + + + RSVD3 + Reserved. This field always reads 0. + 0x1 + 3 + read-only + + + FIELD_NUM + indicate how many fields in one pixel,0 for only A;3 for ABCD + 0x4 + 2 + read-write + + + RSVD2 + Reserved. This field always reads 0. + 0x6 + 2 + read-only + + + MASK_INDEX + which field is the mask,0 for A, 3 for D + 0x8 + 2 + read-write + + + RSVD1 + Reserved. This field always reads 0. + 0xA + 6 + read-only + + + PIXEL_PITCH_64B + extend each line to be 64-bit aligned + 0x10 + 10 + read-write + + + ERR_PRONE + step1 write fifo full. If detected, this bit is 1, there is data error in current frame. + 0x1A + 1 + read-only + + + FIFOFULL + step1 write fifo full + 0x1B + 1 + read-only + + + RSVD0 + Reserved. This field always reads 0. + 0x1C + 4 + read-only + + + + + HW_COMP_FORMAT1 + no description available + 0x2C20 + 32 + read-write + 0 + 0xFFFFFFFF + + + A_OFFSET + offset for field A, 0 means A start from bit0 + 0 + 5 + read-write + + + A_LEN + length of field A, 0 for 1 byte, 7 for 8 bytes, length of the field plus the length of RLE(*_runlen) should not more than 16-bit + 0x5 + 3 + read-write + + + B_OFFSET + offset for field B, 0 means B start from bit0 + 0x8 + 5 + read-write + + + B_LEN + length of field B, 0 for 1 byte, 7 for 8 bytes, length of the field plus the length of RLE(*_runlen) should not more than 16-bit + 0xD + 3 + read-write + + + C_OFFSET + offset for field C, 0 means C start from bit0 + 0x10 + 5 + read-write + + + C_LEN + length of field C, 0 for 1 byte, 7 for 8 bytes, length of the field plus the length of RLE(*_runlen) should not more than 16-bit + 0x15 + 3 + read-write + + + D_OFFSET + offset for field D, 0 means D start from bit0 + 0x18 + 5 + read-write + + + D_LEN + length of field D, 0 for 1 byte, 7 for 8 bytes, length of the field plus the length of RLE(*_runlen) should not more than 16-bit + 0x1D + 3 + read-write + + + + + HW_COMP_FORMAT2 + no description available + 0x2C30 + 32 + read-write + 0 + 0xFFFFFFFF + + + A_RUNLEN + length of the RLE for field A, 12-bit(4095) max + 0 + 4 + read-write + + + B_RUNLEN + length of the RLE for field B, 12-bit(4095) max + 0x4 + 4 + read-write + + + C_RUNLEN + length of the RLE for field C, 12-bit(4095) max + 0x8 + 4 + read-write + + + D_RUNLEN + length of the RLE for field D, 12-bit(4095) max + 0xC + 4 + read-write + + + RSVD + Reserved. This field always reads 0. + 0x10 + 16 + read-only + + + + + HW_COMP_MASK0 + no description available + 0x2C40 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD_MASK_LOW + low 32bit of the valid mask, one of ABCD will be vld_flag,1 left shifted by vld_flag anded with vld_mask will be used to check whether this pixel is valid + 0 + 32 + read-write + + + + + HW_COMP_MASK1 + no description available + 0x2C50 + 32 + read-write + 0 + 0xFFFFFFFF + + + VLD_MASK_HIGH + high 32bit of the valid mask + 0 + 32 + read-write + + + + + HW_COMP_BUFFER_SIZE + no description available + 0x2C60 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL_LENGTH + pixel length of the input frame, 4096 max + 0 + 13 + read-write + + + RSVD1 + Reserved. This field always reads 0. + 0xD + 3 + read-only + + + PIXEL_WIDTH + pixel width of the input frame, 4096 max + 0x10 + 13 + read-write + + + RSVD0 + Reserved. This field always reads 0. + 0x1D + 3 + read-only + + + + + HW_COMP_SOURCE + no description available + 0x2C70 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOURCE_ADDR + source address of the input frame that located in the memory, should be 32-byte aligned + 0 + 32 + read-write + + + + + HW_COMP_TARGET + no description available + 0x2C80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TARGET_ADDR + taget address of the output frmae that the pxp compress engine should write to the memory, should be 32-byte aligned + 0 + 32 + read-write + + + + + HW_COMP_BUFFER_A + no description available + 0x2C90 + 32 + read-write + 0 + 0xFFFFFFFF + + + A_SRAM_ADDR + sram address used for inter-data saving of A filed,should be 32-bit aligned, SW should make sure the SRAM addr for 4 field will not overlap + 0 + 32 + read-write + + + + + HW_COMP_BUFFER_B + no description available + 0x2CA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + B_SRAM_ADDR + sram address used for inter-data saving of B filed,should be 32-bit aligned, SW should make sure the SRAM addr for 4 field will not overlap + 0 + 32 + read-write + + + + + HW_COMP_BUFFER_C + no description available + 0x2CB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + C_SRAM_ADDR + sram address used for inter-data saving of C filed,should be 32-bit aligned, SW should make sure the SRAM addr for 4 field will not overlap + 0 + 32 + read-write + + + + + HW_COMP_BUFFER_D + no description available + 0x2CC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + D_SRAM_ADDR + sram address used for inter-data saving of D filed,should be 32-bit aligned, SW should make sure the SRAM addr for 4 field will not overlap + 0 + 32 + read-write + + + + + HW_COMP_DEBUG + no description available + 0x2CD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DEBUG_SEL + debug selection + 0 + 8 + read-write + + + DEBUG_VALUE + value of selected debug signal + 0x8 + 24 + read-only + + + + + HW_BUS_MUX + no description available + 0x2CE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RD_SEL + Subblock BUS to AXI MUX, setting 0 to axi0 and setting 1 to axi1 + 0 + 8 + read-write + + + RSVD0 + Reserved, always set to zero. + 0x8 + 8 + read-only + + + WR_SEL + Subblock BUS to AXI MUX, setting 0 to axi0 and setting 1 to axi1 + 0x10 + 8 + read-write + + + RSVD1 + Reserved, always set to zero. + 0x18 + 8 + read-only + + + + + HW_HANDSHAKE_READY_MUX0 + no description available + 0x2CF0 + 32 + read-write + 0x76543210 + 0xFFFFFFFF + + + HSK0 + Subblock double buffer handshake signals MUX 0: Ready signal source is from pxp_control; 1: Ready signal source is from pxp_store_wfe_B CH0; 2: Ready signal source is from pxp_store_wfe_B CH1; 3: Ready signal source is from pxp_store_pre_ditering CH0; 4: Ready signal source is from pxp_store_pre_ditering CH1; 5: Ready signal source is from pxp_store_dithering CH0; 6: Ready signal source is from pxp_store_dithering CH1; 7: Ready signal source is from pxp_store_wfe_a CH0; 8: Ready signal source is from pxp_store_wfe_a CH1; 9: Ready signal source is from cpu_fetch_sw0_ready; A: Ready signal source is from cpu_fetch_sw1_ready; B: Ready signal source is from cpu_store_sw0_ready; C: Ready signal source is from cpu_store_sw1_ready; + 0 + 4 + read-write + + + HSK1 + Subblock double buffer handshake signals MUX + 0x4 + 4 + read-write + + + HSK2 + Subblock double buffer handshake signals MUX + 0x8 + 4 + read-write + + + HSK3 + Subblock double buffer handshake signals MUX + 0xC + 4 + read-write + + + HSK4 + Subblock double buffer handshake signals MUX + 0x10 + 4 + read-write + + + HSK5 + Subblock double buffer handshake signals MUX + 0x14 + 4 + read-write + + + HSK6 + Subblock double buffer handshake signals MUX + 0x18 + 4 + read-write + + + HSK7 + Subblock double buffer handshake signals MUX + 0x1C + 4 + read-write + + + + + HW_HANDSHAKE_READY_MUX1 + no description available + 0x2D00 + 32 + read-write + 0xFEDCBA98 + 0xFFFFFFFF + + + HSK8 + Subblock double buffer handshake signals MUX + 0 + 4 + read-write + + + HSK9 + Subblock double buffer handshake signals MUX + 0x4 + 4 + read-write + + + HSK10 + Subblock double buffer handshake signals MUX + 0x8 + 4 + read-write + + + HSK11 + Subblock double buffer handshake signals MUX + 0xC + 4 + read-write + + + HSK12 + Subblock double buffer handshake signals MUX + 0x10 + 4 + read-write + + + HSK13 + Subblock double buffer handshake signals MUX + 0x14 + 4 + read-write + + + HSK14 + Subblock double buffer handshake signals MUX + 0x18 + 4 + read-write + + + HSK15 + Subblock double buffer handshake signals MUX + 0x1C + 4 + read-write + + + + + HW_HANDSHAKE_DONE_MUX0 + no description available + 0x2D10 + 32 + read-write + 0x76543210 + 0xFFFFFFFF + + + HSK0 + Subblock double buffer handshake signals MUX 0: Done signal source is from LCDIF; 1: Done signal source is from pxp_fetch_input CH0; 2: Done signal source is from pxp_fetch_input CH1; 3: Done signal source is from pxp_fetch_dithering CH0; 4: Done signal source is from pxp_fetch_dithering CH1; 5: Done signal source is from pxp_fetch_wfe_a CH0; 6: Done signal source is from pxp_fetch_wfe_a CH1; 7: Done signal source is from pxp_fetch_wfe_b CH0; 8: Done signal source is from pxp_fetch_wfe_b CH1; 9: Done signal source is from cpu_fetch_sw0_done; A: Done signal source is from cpu_fetch_sw1_done; B: Done signal source is from cpu_store_sw0_done; C: Done signal source is from cpu_store_sw1_done; + 0 + 4 + read-write + + + HSK1 + Subblock double buffer handshake signals MUX + 0x4 + 4 + read-write + + + HSK2 + Subblock double buffer handshake signals MUX + 0x8 + 4 + read-write + + + HSK3 + Subblock double buffer handshake signals MUX + 0xC + 4 + read-write + + + HSK4 + Subblock double buffer handshake signals MUX + 0x10 + 4 + read-write + + + HSK5 + Subblock double buffer handshake signals MUX + 0x14 + 4 + read-write + + + HSK6 + Subblock double buffer handshake signals MUX + 0x18 + 4 + read-write + + + HSK7 + Subblock double buffer handshake signals MUX + 0x1C + 4 + read-write + + + + + HW_HANDSHAKE_DONE_MUX1 + no description available + 0x2D20 + 32 + read-write + 0xFEDCBA98 + 0xFFFFFFFF + + + HSK8 + Subblock double buffer handshake signals MUX + 0 + 4 + read-write + + + HSK9 + Subblock double buffer handshake signals MUX + 0x4 + 4 + read-write + + + HSK10 + Subblock double buffer handshake signals MUX + 0x8 + 4 + read-write + + + HSK11 + Subblock double buffer handshake signals MUX + 0xC + 4 + read-write + + + HSK12 + Subblock double buffer handshake signals MUX + 0x10 + 4 + read-write + + + HSK13 + Subblock double buffer handshake signals MUX + 0x14 + 4 + read-write + + + HSK14 + Subblock double buffer handshake signals MUX + 0x18 + 4 + read-write + + + HSK15 + Subblock double buffer handshake signals MUX + 0x1C + 4 + read-write + + + + + HW_HANDSHAKE_CPU_FETCH + no description available + 0x2D30 + 32 + read-write + 0x100010 + 0xFFFFFFFF + + + SW0_B0_READY + PXP b0 buffer ready to CPU + 0 + 1 + read-only + + + SW0_B1_READY + PXP b1 buffer ready to CPU + 0x1 + 1 + read-only + + + SW0_B0_DONE + CPU b0 buffer done to PXP + 0x2 + 1 + read-write + + + SW0_B1_DONE + CPU b1 buffer done to PXP + 0x3 + 1 + read-write + + + SW0_BUF_LINES + Buffer lines for software handshake + 0x4 + 2 + read-only + + + LINE_4 + Buffer lines is 4 lines. + 0 + + + LINE_8 + Buffer lines is 8 lines. + 0x1 + + + LINE_16 + Buffer lines is 16 lines. + 0x2 + + + + + RSVD0 + Reserved, always set to zero. + 0x6 + 9 + read-only + + + SW0_HSK_EN + Enable software handshake 0 with CPU + 0xF + 1 + read-write + + + SW1_B0_READY + PXP b0 buffer ready to CPU + 0x10 + 1 + read-only + + + SW1_B1_READY + PXP b1 buffer ready to CPU + 0x11 + 1 + read-only + + + SW1_B0_DONE + CPU b0 buffer done to PXP + 0x12 + 1 + read-write + + + SW1_B1_DONE + CPU b1 buffer done to PXP + 0x13 + 1 + read-write + + + SW1_BUF_LINES + Buffer lines for software handshake + 0x14 + 2 + read-only + + + LINE_4 + Buffer lines is 4 lines. + 0 + + + LINE_8 + Buffer lines is 8 lines. + 0x1 + + + LINE_16 + Buffer lines is 16 lines. + 0x2 + + + + + RSVD1 + Reserved, always set to zero. + 0x16 + 9 + read-only + + + SW1_HSK_EN + Enable software handshake 1 with CPU + 0x1F + 1 + read-write + + + + + HW_HANDSHAKE_CPU_STORE + no description available + 0x2D40 + 32 + read-write + 0x100010 + 0xFFFFFFFF + + + SW0_B0_READY + PXP b0 buffer ready to CPU + 0 + 1 + read-write + + + SW0_B1_READY + PXP b1 buffer ready to CPU + 0x1 + 1 + read-write + + + SW0_B0_DONE + CPU b0 buffer done to PXP + 0x2 + 1 + read-only + + + SW0_B1_DONE + CPU b1 buffer done to PXP + 0x3 + 1 + read-only + + + SW0_BUF_LINES + Buffer lines for software handshake + 0x4 + 2 + read-only + + + LINE_4 + Buffer lines is 4 lines. + 0 + + + LINE_8 + Buffer lines is 8 lines. + 0x1 + + + LINE_16 + Buffer lines is 16 lines. + 0x2 + + + + + RSVD0 + Reserved, always set to zero. + 0x6 + 9 + read-only + + + SW0_HSK_EN + Enable software handshake 0 with CPU + 0xF + 1 + read-write + + + SW1_B0_READY + PXP b0 buffer ready to CPU + 0x10 + 1 + read-write + + + SW1_B1_READY + PXP b1 buffer ready to CPU + 0x11 + 1 + read-write + + + SW1_B0_DONE + CPU b0 buffer done to PXP + 0x12 + 1 + read-only + + + SW1_B1_DONE + CPU b1 buffer done to PXP + 0x13 + 1 + read-only + + + SW1_BUF_LINES + Buffer lines for software handshake + 0x14 + 2 + read-only + + + LINE_4 + Buffer lines is 4 lines. + 0 + + + LINE_8 + Buffer lines is 8 lines. + 0x1 + + + LINE_16 + Buffer lines is 16 lines. + 0x2 + + + + + RSVD1 + Reserved, always set to zero. + 0x16 + 9 + read-only + + + SW1_HSK_EN + Enable software handshake 1 with CPU + 0x1F + 1 + read-write + + + + + + + QuadSPI + QuadSPI + QUADSPI + QuadSPI_ + 0x21E0000 + + 0 + 0x410 + registers + + + QSPI + 139 + + + + MCR + Module Configuration Register + 0 + 32 + read-write + 0xF4000 + 0xFFFFFFFF + + + SWRSTSD + Software reset for Serial Flash domainPlease keep other fields value when write to SWRSTHD and SWRSTSD These software reset don't reset register setting but only reset internal flip-flops in quadspi controller To remove the reset, need to write 0 to SWRSTHD and SWRSTSD + 0 + 1 + read-write + + + SWRSTSD_0 + No action + 0 + + + SWRSTSD_1 + Serial Flash domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. + 0x1 + + + + + SWRSTHD + Software reset for AHB domainPlease keep other fields value when write to SWRSTHD and SWRSTSD These software reset don't reset register setting but only reset internal flip-flops in quadspi controller To remove the reset, need to write 0 to SWRSTHD and SWRSTSD + 0x1 + 1 + read-write + + + SWRSTHD_0 + No action + 0 + + + SWRSTHD_1 + AHB domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. + 0x1 + + + + + END_CFG + Defines the endianness of the QSPI module.For more details refer to Byte Ordering Endianess + 0x2 + 2 + read-write + + + DQS_EN + DQS enable: This field is valid for both SDR and DDR mode + 0x6 + 1 + read-write + + + DQS_EN_0 + DQS disabled. + 0 + + + DQS_EN_1 + DQS enabled- When enabled, the incoming data is sampled on both the edges of DQS input when QSPI_MCR[DDR_EN] is set, else, on only one edge when QSPI_MCR[DDR_EN] is 0. The QSPI_SMPR[DDR_SMP] values are ignored. + 0x1 + + + + + DDR_EN + DDR mode enable: + 0x7 + 1 + read-write + + + DDR_EN_0 + 2x and 4x clocks are disabled for SDR instructions only + 0 + + + DDR_EN_1 + 2x and 4x clocks are enabled supports both SDR and DDR instruction. + 0x1 + + + + + CLR_RXF + Clear RX FIFO. Invalidate the RX Buffer. + 0xA + 1 + read-write + + + CLR_RXF_0 + No action. + 0 + + + CLR_RXF_1 + Read and write pointers of the RX Buffer are reset to 0. QSPI_RBSR[RDBFL] is reset to 0. + 0x1 + + + + + CLR_TXF + Clear TX FIFO/Buffer. Invalidate the TX Buffer content. + 0xB + 1 + read-write + + + CLR_TXF_0 + No action. + 0 + + + CLR_TXF_1 + Read and write pointers of the TX Buffer are reset to 0. QSPI_TBSR[TRCTR] is reset to 0. + 0x1 + + + + + MDIS + Module Disable + 0xE + 1 + read-write + + + MDIS_0 + Enable QuadSPI clocks. + 0 + + + MDIS_1 + Allow external logic to disable QuadSPI clocks. + 0x1 + + + + + DQS_LOOPBACK_EN + Quadspi will output serial data strobe signal which will be loopback from pad to sample input flash serial data + 0x18 + 1 + read-write + + + DQS_PHASE_EN + This bit controls internal DQS output phase + 0x1E + 1 + read-write + + + + + IPCR + IP Configuration Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDATSZ + IP data transfer size: Defines the data transfer size in bytes of the IP command. + 0 + 16 + read-write + + + PAR_EN + When set, a transaction to two serial flash devices is triggered in parallel mode + 0x10 + 1 + read-write + + + SEQID + Points to a sequence in the Look-up-table + 0x18 + 4 + read-write + + + + + FLSHCR + Flash Configuration Register + 0xC + 32 + read-write + 0x303 + 0xFFFFFFFF + + + TCSS + Serial flash CS setup time in terms of serial flash clock cycles + 0 + 4 + read-write + + + TCSH + Serial flash CS hold time in terms of serial flash clock cycles + 0x8 + 4 + read-write + + + + + BUF0CR + Buffer0 Configuration Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSTRID + Master ID: The ID of the AHB master associated with BUFFER0 + 0 + 4 + read-write + + + ADATSZ + AHB data transfer size: Defines the data transfer size in 8 bytes of an AHB triggered access to serial flash + 0x8 + 8 + read-write + + + HP_EN + High Priority Enable: When set, the master associated with this buffer is assigned a priority higher than the rest of the masters + 0x1F + 1 + read-write + + + + + BUF1CR + Buffer1 Configuration Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSTRID + Master ID: The ID of the AHB master associated with BUFFER1 + 0 + 4 + read-write + + + ADATSZ + AHB data transfer size: Defines the data transfer size in 8 bytes of an AHB triggered access to serial flash + 0x8 + 8 + read-write + + + + + BUF2CR + Buffer2 Configuration Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSTRID + Master ID: The ID of the AHB master associated with BUFFER2 + 0 + 4 + read-write + + + ADATSZ + AHB data transfer size: Defines the data transfer size in 8 Bytes of an AHB triggered access to serial flash + 0x8 + 8 + read-write + + + + + BUF3CR + Buffer3 Configuration Register + 0x1C + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + MSTRID + Master ID: The ID of the AHB master associated with BUFFER3 + 0 + 4 + read-write + + + ADATSZ + AHB data transfer size: Defines the data transfer size in 8 Bytes of an AHB triggered access to serial flash + 0x8 + 8 + read-write + + + ALLMST + All master enable: When set, buffer3 acts as an all-master buffer + 0x1F + 1 + read-write + + + + + BFGENCR + Buffer Generic Configuration Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEQID + Points to a sequence in the Look-up-table + 0xC + 4 + read-write + + + PAR_EN + When set, a transaction to two serial flash devices is triggered in parallel mode + 0x10 + 1 + read-write + + + + + BUF0IND + Buffer0 Top Index Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPINDX0 + Top index of buffer 0. + 0x3 + 29 + read-write + + + + + BUF1IND + Buffer1 Top Index Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPINDX1 + Top index of buffer 1. + 0x3 + 29 + read-write + + + + + BUF2IND + Buffer2 Top Index Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPINDX2 + Top index of buffer 2. + 0x3 + 29 + read-write + + + + + SFAR + Serial Flash Address Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SFADR + Serial Flash Address. The register content is used as byte address for all following IP Commands. + 0 + 32 + read-write + + + + + SMPR + Sampling Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDRSMP + SDR sampling point. + 0x5 + 2 + read-write + + + DDRSMP + DDR Sampling point + 0x10 + 3 + read-write + + + + + RBSR + RX Buffer Status Register + 0x10C + 32 + read-only + 0 + 0xFFFFFFFF + + + RDBFL + RX Buffer Fill Level, indicates how many entries of 4 bytes are still available in the RX Buffer + 0x8 + 6 + read-only + + + RDCTR + Read Counter, indicates how many entries of 4 bytes have been removed from the RX Buffer + 0x10 + 16 + read-only + + + + + RBCT + RX Buffer Control Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + WMRK + RX Buffer Watermark: This field determines when the readout action of the RX Buffer is triggered + 0 + 5 + read-write + + + RXBRD + RX Buffer Readout: This bit specifies the access scheme for the RX Buffer readout. + 0x8 + 1 + read-write + + + RXBRD_0 + RX Buffer content is read using the AHB Bus registers QSPI_ARDB0 to QSPI_ARDB31. For details, refer to Exclusive Access to Serial Flash for AHB Commands. + 0 + + + RXBRD_1 + RX Buffer content is read using the IP Bus registers QSPI_RBDR0 to QSPI_RBDR31. + 0x1 + + + + + + + TBSR + TX Buffer Status Register + 0x150 + 32 + read-only + 0 + 0xFFFFFFFF + + + TRBFL + TX Buffer Fill Level + 0x8 + 5 + read-only + + + TRCTR + Transmit Counter + 0x10 + 16 + read-only + + + + + TBDR + TX Buffer Data Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXDATA + TX Data On write access the data is written into the next available entry of the TX Buffer and the QPSI_TBSR[TRBFL] field is updated accordingly + 0 + 32 + read-write + + + + + SR + Status Register + 0x15C + 32 + read-only + 0x3800 + 0xFFFFFFFF + + + BUSY + Module Busy: Asserted when module is currently busy handling a transaction to an external flash device + 0 + 1 + read-only + + + IP_ACC + IP Access: Asserted when transaction currently executed was initiated by IP bus. + 0x1 + 1 + read-only + + + AHB_ACC + AHB Access: Asserted when the transaction currently executed was initiated by AHB bus. + 0x2 + 1 + read-only + + + AHBGNT + AHB Command priority Granted: Asserted when another module has been granted priority of AHB Commands against IP Commands + 0x5 + 1 + read-only + + + AHBTRN + AHB Access Transaction pending: Asserted when there is a pending request on the AHB interface + 0x6 + 1 + read-only + + + AHB0NE + AHB 0 Buffer Not Empty: Asserted when AHB 0 buffer contains data. + 0x7 + 1 + read-only + + + AHB1NE + AHB 1 Buffer Not Empty: Asserted when AHB 1 buffer contains data. + 0x8 + 1 + read-only + + + AHB2NE + AHB 2 Buffer Not Empty: Asserted when AHB 2 buffer contains data. + 0x9 + 1 + read-only + + + AHB3NE + AHB 3 Buffer Not Empty: Asserted when AHB 3 buffer contains data. + 0xA + 1 + read-only + + + AHB0FUL + AHB 0 Buffer Full: Asserted when AHB 0 buffer is full. + 0xB + 1 + read-only + + + AHB1FUL + AHB 1 Buffer Full: Asserted when AHB 1 buffer is full. + 0xC + 1 + read-only + + + AHB2FUL + AHB 2 Buffer Full: Asserted when AHB 2 buffer is full. + 0xD + 1 + read-only + + + AHB3FUL + AHB 3 Buffer Full: Asserted when AHB 3 buffer is full. + 0xE + 1 + read-only + + + RXWE + RX Buffer Watermark Exceeded: Asserted when the number of valid entries in the RX Buffer exceeds the number given in the QSPI_RBCT[WMRK] field + 0x10 + 1 + read-only + + + RXFULL + RX Buffer Full: Asserted when the RX Buffer is full, i + 0x13 + 1 + read-only + + + RXDMA + RX Buffer DMA: Asserted when RX Buffer read out via DMA is active i.e DMA is requested or running. + 0x17 + 1 + read-only + + + TXEDA + Tx Buffer Enough Data Available + 0x18 + 1 + read-only + + + TXFULL + TX Buffer Full: Asserted when no more data can be stored. + 0x1B + 1 + read-only + + + DLPSMP + Data learning is not implemented on this chip + 0x1D + 3 + read-only + + + + + FR + Flag Register + 0x160 + 32 + read-write + 0x8000000 + 0xFFFFFFFF + + + TFF + IP Command Transaction Finished Flag: Set when the QuadSPI module has finished a running IP Command + 0 + 1 + read-write + oneToClear + + + IPGEF + IP Command Trigger during AHB Grant Error Flag: Set when the following condition occurs: A write access occurs to the QSPI_IPCR[SEQID] field and the QSPI_SR[AHBGNT] bit is set + 0x4 + 1 + read-write + oneToClear + + + IPIEF + IP Command Trigger could not be executed Error Flag + 0x6 + 1 + read-write + oneToClear + + + IPAEF + IP Command Trigger during AHB Access Error Flag + 0x7 + 1 + read-write + oneToClear + + + IUEF + IP Command Usage Error Flag: Set when in parallel flash mode the execution of an IP Command is started and the sequence pointed to by the sequence ID contains a WRITE or a WRITE_DDR command + 0xB + 1 + read-write + oneToClear + + + ABOF + AHB Buffer Overflow Flag: Set when the size of the AHB access exceeds the size of the AHB buffer + 0xC + 1 + read-write + oneToClear + + + ABSEF + AHB Sequence Error Flag: Set when the execution of an AHB Command is started with an WRITE or WRITE_DDR Command in the sequence pointed to by the QSPI_BUFxCR QSPI_BUFxCR implies anyone of QSPI_BUF0CR/QSPI_BUF1CR/QSPI_BUF2CR/QSPI_BUF3CR register Communication with the serial flash device is terminated before the execution of WRITE/WRITE_DDR command by the QuadSPI module + 0xF + 1 + read-write + oneToClear + + + RBDF + RX Buffer Drain Flag: Will be set if the QuadSPI_SR[RXWE] status bit is asserted + 0x10 + 1 + read-write + oneToClear + + + RBOF + RX Buffer Overflow Flag: Set when not all the data read from the serial flash device could be pushed into the RX Buffer + 0x11 + 1 + read-write + oneToClear + + + ILLINE + Illegal Instruction Error Flag: Set when an illegal instruction is encountered by the controller in any of the sequences + 0x17 + 1 + read-write + oneToClear + + + TBUF + TX Buffer Underrun Flag: Set when the module tried to pull data although TX Buffer was emptyor the buffer contains less than 128bits of data + 0x1A + 1 + read-write + oneToClear + + + TBFF + TX Buffer Fill Flag: Before writing to the TX buffer, this bit should be cleared + 0x1B + 1 + read-write + oneToClear + + + DLPFF + Data learning is not implemented on this chip + 0x1F + 1 + read-write + oneToClear + + + + + RSER + Interrupt and DMA Request Select and Enable Register + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFIE + Transaction Finished Interrupt Enable + 0 + 1 + read-write + + + TFIE_0 + No TFF interrupt will be generated + 0 + + + TFIE_1 + TFF interrupt will be generated + 0x1 + + + + + IPGEIE + IP Command Trigger during AHB Grant Error Interrupt Enable + 0x4 + 1 + read-write + + + IPGEIE_0 + No IPGEF interrupt will be generated + 0 + + + IPGEIE_1 + IPGEF interrupt will be generated + 0x1 + + + + + IPIEIE + IP Command Trigger during IP Access Error Interrupt Enable + 0x6 + 1 + read-write + + + IPIEIE_0 + No IPIEF interrupt will be generated + 0 + + + + + IPAEIE + IP Command Trigger during AHB Access Error Interrupt Enable + 0x7 + 1 + read-write + + + IPAEIE_0 + No IPAEF interrupt will be generated + 0 + + + IPAEIE_1 + IPAEF interrupt will be generated + 0x1 + + + + + IUEIE + IP Command Usage Error Interrupt Enable + 0xB + 1 + read-write + + + IUEIE_0 + No IUEF interrupt will be generated + 0 + + + IUEIE_1 + IUEF interrupt will be generated + 0x1 + + + + + ABOIE + AHB Buffer Overflow Interrupt Enable + 0xC + 1 + read-write + + + ABOIE_0 + No ABOF interrupt will be generated + 0 + + + ABOIE_1 + ABOF interrupt will be generated + 0x1 + + + + + ABSEIE + AHB Sequence Error Interrupt Enable: Triggered by ABSEF flags of QSPI_FR + 0xF + 1 + read-write + + + ABSEIE_0 + No ABSEF interrupt will be generated + 0 + + + ABSEIE_1 + ABSEF interrupt will be generated + 0x1 + + + + + RBDIE + RX Buffer Drain Interrupt Enable: Enables generation of IRQ requests for RX Buffer Drain + 0x10 + 1 + read-write + + + RBDIE_0 + No RBDF interrupt will be generated + 0 + + + RBDIE_1 + RBDF Interrupt will be generated + 0x1 + + + + + RBOIE + RX Buffer Overflow Interrupt Enable + 0x11 + 1 + read-write + + + RBOIE_0 + No RBOF interrupt will be generated + 0 + + + RBOIE_1 + RBOF interrupt will be generated + 0x1 + + + + + RBDDE + RX Buffer Drain DMA Enable: Enables generation of DMA requests for RX Buffer Drain + 0x15 + 1 + read-write + + + RBDDE_0 + No DMA request will be generated + 0 + + + RBDDE_1 + DMA request will be generated + 0x1 + + + + + ILLINIE + Illegal Instruction Error Interrupt Enable. Triggered by ILLINE flag in QSPI_FR + 0x17 + 1 + read-write + + + ILLINIE_0 + No ILLINE interrupt will be generated + 0 + + + ILLINIE_1 + ILLINE interrupt will be generated + 0x1 + + + + + TBUIE + TX Buffer Underrun Interrupt Enable + 0x1A + 1 + read-write + + + TBUIE_0 + No TBUF interrupt will be generated + 0 + + + TBUIE_1 + TBUF interrupt will be generated + 0x1 + + + + + TBFIE + TX Buffer Fill Interrupt Enable + 0x1B + 1 + read-write + + + TBFIE_0 + No TBFF interrupt will be generated + 0 + + + TBFIE_1 + TBFF interrupt will be generated + 0x1 + + + + + DLPFIE + Data learning is not implemented on this chip + 0x1F + 1 + read-write + + + DLPFIE_0 + No DLPFF interrupt will be generated + 0 + + + DLPFIE_1 + DLPFF interrupt will be generated + 0x1 + + + + + + + SPNDST + Sequence Suspend Status Register + 0x168 + 32 + read-only + 0 + 0xFFFFFFFF + + + SUSPND + When set, it signifies that a sequence is in suspended state + 0 + 1 + read-only + + + SPDBUF + Suspended Buffer: Provides the suspended buffer number. Valid only when SUSPND is set to 1'b1 + 0x6 + 2 + read-only + + + DATLFT + Data left: Provides information about the amount of data left to be read in the suspended sequence + 0x9 + 7 + read-only + + + + + SPTRCLR + Sequence Pointer Clear Register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + BFPTRC + Buffer Pointer Clear: 1: Clears the sequence pointer for AHB accesses as defined in QuadSPI_BFGENCR + 0 + 1 + read-write + + + IPPTRC + IP Pointer Clear: 1: Clears the sequence pointer for IP accesses as defined in QuadSPI_IPCR + 0x8 + 1 + read-write + + + + + SFA1AD + Serial Flash A1 Top Address + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPADA1 + Top address for Serial Flash A1. In effect, TPADxx is the first location of the next memory. + 0xA + 22 + read-write + + + + + SFA2AD + Serial Flash A2 Top Address + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPADA2 + Top address for Serial Flash A2. In effect, TPxxAD is the first location of the next memory. + 0xA + 22 + read-write + + + + + SFB1AD + Serial Flash B1Top Address + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPADB1 + Top address for Serial Flash B1.In effect, TPxxAD is the first location of the next memory. + 0xA + 22 + read-write + + + + + SFB2AD + Serial Flash B2Top Address + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + TPADB2 + Top address for Serial Flash B2. In effect, TPxxAD is the first location of the next memory. + 0xA + 22 + read-write + + + + + 32 + 0x4 + RBDR%s + RX Buffer Data Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXDATA + RX Data + 0 + 32 + read-write + + + + + LUTKEY + LUT Key Register + 0x300 + 32 + read-write + 0x5AF05AF0 + 0xFFFFFFFF + + + KEY + The key to lock or unlock the LUT. The KEY is 0x5AF05AF0. The read value is always 0x5AF05AF0 + 0 + 32 + read-write + + + + + LCKCR + LUT Lock Configuration Register + 0x304 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + LOCK + Locks the LUT when the following condition is met: This register is written just after the LUTKEYLUT Key Register The LUT key register was written with 0x5AF05AF0 key + 0 + 1 + read-write + + + UNLOCK + Unlocks the LUT when the following two conditions are met: 1 + 0x1 + 1 + read-write + + + + + LUT0 + Look-up Table register + 0x310 + 32 + read-write + 0x8180403 + 0xFFFFFFFF + + + OPRND0 + Operand for INSTR0. + 0 + 8 + read-write + + + PAD0 + Pad information for INSTR0. + 0x8 + 2 + read-write + + + PAD0_0 + 1 Pad + 0 + + + PAD0_1 + 2 Pads + 0x1 + + + PAD0_2 + 4 Pads + 0x2 + + + PAD0_3 + NA + 0x3 + + + + + INSTR0 + Instruction 0 + 0xA + 6 + read-write + + + OPRND1 + Operand for INSTR1. + 0x10 + 8 + read-write + + + PAD1 + Pad information for INSTR1. + 0x18 + 2 + read-write + + + PAD1_0 + 1 Pad + 0 + + + PAD1_1 + 2 Pads + 0x1 + + + PAD1_2 + 4 Pads + 0x2 + + + PAD1_3 + NA + 0x3 + + + + + INSTR1 + Instruction 1 + 0x1A + 6 + read-write + + + + + LUT1 + Look-up Table register + 0x314 + 32 + read-write + 0x24001C08 + 0xFFFFFFFF + + + OPRND0 + Operand for INSTR0. + 0 + 8 + read-write + + + PAD0 + Pad information for INSTR0. + 0x8 + 2 + read-write + + + PAD0_0 + 1 Pad + 0 + + + PAD0_1 + 2 Pads + 0x1 + + + PAD0_2 + 4 Pads + 0x2 + + + PAD0_3 + NA + 0x3 + + + + + INSTR0 + Instruction 0 + 0xA + 6 + read-write + + + OPRND1 + Operand for INSTR1. + 0x10 + 8 + read-write + + + PAD1 + Pad information for INSTR1. + 0x18 + 2 + read-write + + + PAD1_0 + 1 Pad + 0 + + + PAD1_1 + 2 Pads + 0x1 + + + PAD1_2 + 4 Pads + 0x2 + + + PAD1_3 + NA + 0x3 + + + + + INSTR1 + Instruction 1 + 0x1A + 6 + read-write + + + + + 62 + 0x4 + 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 + LUT%s + Look-up Table register + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + OPRND0 + Operand for INSTR0. + 0 + 8 + read-write + + + PAD0 + Pad information for INSTR0. + 0x8 + 2 + read-write + + + PAD0_0 + 1 Pad + 0 + + + PAD0_1 + 2 Pads + 0x1 + + + PAD0_2 + 4 Pads + 0x2 + + + PAD0_3 + NA + 0x3 + + + + + INSTR0 + Instruction 0 + 0xA + 6 + read-write + + + OPRND1 + Operand for INSTR1. + 0x10 + 8 + read-write + + + PAD1 + Pad information for INSTR1. + 0x18 + 2 + read-write + + + PAD1_0 + 1 Pad + 0 + + + PAD1_1 + 2 Pads + 0x1 + + + PAD1_2 + 4 Pads + 0x2 + + + PAD1_3 + NA + 0x3 + + + + + INSTR1 + Instruction 1 + 0x1A + 6 + read-write + + + + + + + DCP + DCP register reference index + DCP + DCP_ + 0x2280000 + + 0 + 0x434 + registers + + + DCP_IRQ + 78 + + + DCP_VMI_IRQ + 79 + + + DCP_SEC_IRQ + 80 + + + + CTRL + DCP control register 0 + 0 + 32 + read-write + 0xF0800000 + 0xFFFFFFFF + + + CHANNEL_INTERRUPT_ENABLE + Per-channel interrupt enable bit + 0 + 8 + read-write + + + CH0 + no description available + 0x1 + + + CH1 + no description available + 0x2 + + + CH2 + no description available + 0x4 + + + CH3 + no description available + 0x8 + + + + + ENABLE_CONTEXT_SWITCHING + Enable automatic context switching for the channels + 0x15 + 1 + read-write + + + ENABLE_CONTEXT_CACHING + The software must set this bit to enable the caching of contexts between the operations + 0x16 + 1 + read-write + + + GATHER_RESIDUAL_WRITES + The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations + 0x17 + 1 + read-write + + + PRESENT_SHA + Indicates whether the SHA1/SHA2 functions are present. + 0x1C + 1 + read-only + + + Absent + no description available + 0 + + + Present + no description available + 0x1 + + + + + PRESENT_CRYPTO + Indicates whether the crypto (cipher/hash) functions are present. + 0x1D + 1 + read-only + + + Absent + no description available + 0 + + + Present + no description available + 0x1 + + + + + CLKGATE + This bit must be set to zero for a normal operation + 0x1E + 1 + read-write + + + SFTRST + Set this bit to zero to enable a normal DCP operation + 0x1F + 1 + read-write + + + + + STAT + DCP status register + 0x10 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + IRQ + Indicates which channels have pending interrupt requests + 0 + 4 + read-write + + + READY_CHANNELS + Indicates which channels are ready to proceed with a transfer (the active channel is also included) + 0x10 + 8 + read-only + + + CH0 + no description available + 0x1 + + + CH1 + no description available + 0x2 + + + CH2 + no description available + 0x4 + + + CH3 + no description available + 0x8 + + + + + CUR_CHANNEL + Current (active) channel (encoded) + 0x18 + 4 + read-only + + + None + no description available + 0 + + + CH0 + no description available + 0x1 + + + CH1 + no description available + 0x2 + + + CH2 + no description available + 0x3 + + + CH3 + no description available + 0x4 + + + + + OTP_KEY_READY + When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. + 0x1C + 1 + read-only + + + + + CHANNELCTRL + DCP channel control register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE_CHANNEL + Setting a bit in this field enables the DMA channel associated with it + 0 + 8 + read-write + + + CH0 + no description available + 0x1 + + + CH1 + no description available + 0x2 + + + CH2 + no description available + 0x4 + + + CH3 + no description available + 0x8 + + + + + HIGH_PRIORITY_CHANNEL + Setting a bit in this field causes the corresponding channel to have high-priority arbitration + 0x8 + 8 + read-write + + + CH0 + no description available + 0x1 + + + CH1 + no description available + 0x2 + + + CH2 + no description available + 0x4 + + + CH3 + no description available + 0x8 + + + + + CH0_IRQ_MERGED + Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt + 0x10 + 1 + read-write + + + + + CAPABILITY0 + DCP capability 0 register + 0x30 + 32 + read-write + 0x404 + 0xFFFFFFFF + + + NUM_KEYS + Encoded value indicating the number of key-storage locations implemented in the design + 0 + 8 + read-only + + + NUM_CHANNELS + Encoded value indicating the number of channels implemented in the design + 0x8 + 4 + read-only + + + DISABLE_UNIQUE_KEY + Write to a 1 to disable the per-device unique key + 0x1D + 1 + read-write + + + DISABLE_DECRYPT + Write to 1 to disable the decryption + 0x1F + 1 + read-write + + + + + CAPABILITY1 + DCP capability 1 register + 0x40 + 32 + read-only + 0x70001 + 0xFFFFFFFF + + + CIPHER_ALGORITHMS + One-hot field indicating which cipher algorithms are available + 0 + 16 + read-only + + + AES128 + no description available + 0x1 + + + + + HASH_ALGORITHMS + One-hot field indicating which hashing features are implemented in the hardware + 0x10 + 16 + read-only + + + SHA1 + no description available + 0x1 + + + CRC32 + no description available + 0x2 + + + SHA256 + no description available + 0x4 + + + + + + + CONTEXT + DCP context buffer pointer + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Context pointer address + 0 + 32 + read-write + + + + + KEY + DCP key index + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + SUBWORD + Key subword pointer + 0 + 2 + read-write + + + INDEX + Key index pointer. The valid indices are 0-[number_keys]. + 0x4 + 2 + read-write + + + + + KEYDATA + DCP key data + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Word 0 data for the key. This is the least-significant word. + 0 + 32 + read-write + + + + + PACKET0 + DCP work packet 0 status register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Next pointer register + 0 + 32 + read-only + + + + + PACKET1 + DCP work packet 1 status register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + INTERRUPT + Reflects whether the channel must issue an interrupt upon the completion of the packet. + 0 + 1 + read-only + + + DECR_SEMAPHORE + Reflects whether the channel's semaphore must be decremented at the end of the current operation + 0x1 + 1 + read-only + + + CHAIN + Reflects whether the next command pointer register must be loaded into the channel's current descriptor pointer + 0x2 + 1 + read-only + + + CHAIN_CONTIGUOUS + Reflects whether the next packet's address is located following this packet's payload. + 0x3 + 1 + read-only + + + ENABLE_MEMCOPY + Reflects whether the selected hashing function should be enabled for this operation. + 0x4 + 1 + read-only + + + ENABLE_CIPHER + Reflects whether the selected cipher function must be enabled for this operation. + 0x5 + 1 + read-only + + + ENABLE_HASH + Reflects whether the selected hashing function must be enabled for this operation. + 0x6 + 1 + read-only + + + ENABLE_BLIT + Reflects whether the DCP must perform a blit operation + 0x7 + 1 + read-only + + + CIPHER_ENCRYPT + When the cipher block is enabled, this bit indicates whether the operation is encryption or decryption + 0x8 + 1 + read-only + + + DECRYPT + no description available + 0 + + + ENCRYPT + no description available + 0x1 + + + + + CIPHER_INIT + Reflects whether the cipher block must load the initialization vector from the payload for this operation + 0x9 + 1 + read-only + + + OTP_KEY + Reflects whether a hardware-based key must be used + 0xA + 1 + read-only + + + PAYLOAD_KEY + When set, it indicates the payload contains the key + 0xB + 1 + read-only + + + HASH_INIT + Reflects whether the current hashing block is the initial block in the hashing operation, so the hash registers must be initialized before the operation + 0xC + 1 + read-only + + + HASH_TERM + Reflects whether the current hashing block is the final block in the hashing operation, so the hash padding must be applied by the hardware + 0xD + 1 + read-only + + + CHECK_HASH + Reflects whether the calculated hash value must be compared to the hash provided in the payload. + 0xE + 1 + read-only + + + HASH_OUTPUT + When the hashing is enabled, this bit controls whether the input or output data is hashed. + 0xF + 1 + read-only + + + INPUT + no description available + 0 + + + OUTPUT + no description available + 0x1 + + + + + CONSTANT_FILL + When this bit is set (MEMCOPY and BLIT modes only), the DCP simply fills the destination buffer with the value found in the source address field + 0x10 + 1 + read-only + + + TEST_SEMA_IRQ + This bit is used to test the channel semaphore transition to 0. FOR TEST USE ONLY! + 0x11 + 1 + read-only + + + KEY_BYTESWAP + Reflects whether the DCP engine swaps the key bytes (big-endian key). + 0x12 + 1 + read-only + + + KEY_WORDSWAP + Reflects whether the DCP engine swaps the key words (big-endian key). + 0x13 + 1 + read-only + + + INPUT_BYTESWAP + Reflects whether the DCP engine byteswaps the input data (big-endian data). + 0x14 + 1 + read-only + + + INPUT_WORDSWAP + Reflects whether the DCP engine wordswaps the input data (big-endian data). + 0x15 + 1 + read-only + + + OUTPUT_BYTESWAP + Reflects whether the DCP engine byteswaps the output data (big-endian data). + 0x16 + 1 + read-only + + + OUTPUT_WORDSWAP + Reflects whether the DCP engine wordswaps the output data (big-endian data). + 0x17 + 1 + read-only + + + TAG + Packet Tag + 0x18 + 8 + read-only + + + + + PACKET2 + DCP work packet 2 status register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + CIPHER_SELECT + Cipher selection field + 0 + 4 + read-only + + + AES128 + no description available + 0 + + + + + CIPHER_MODE + Cipher mode selection field. Reflects the mode of operation for the cipher operations. + 0x4 + 4 + read-only + + + ECB + no description available + 0 + + + CBC + no description available + 0x1 + + + + + KEY_SELECT + Key selection field + 0x8 + 8 + read-only + + + KEY0 + no description available + 0 + + + KEY1 + no description available + 0x1 + + + KEY2 + no description available + 0x2 + + + KEY3 + no description available + 0x3 + + + UNIQUE_KEY + no description available + 0xFE + + + OTP_KEY + no description available + 0xFF + + + + + HASH_SELECT + Hash Selection Field + 0x10 + 4 + read-only + + + SHA1 + no description available + 0 + + + CRC32 + no description available + 0x1 + + + SHA256 + no description available + 0x2 + + + + + CIPHER_CFG + Cipher configuration bits. Optional configuration bits are required for the ciphers. + 0x18 + 8 + read-only + + + + + PACKET3 + DCP work packet 3 status register + 0xB0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Source buffer address pointer + 0 + 32 + read-only + + + + + PACKET4 + DCP work packet 4 status register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Destination buffer address pointer + 0 + 32 + read-only + + + + + PACKET5 + DCP work packet 5 status register + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Byte count register. This value is the working value and updates as the operation proceeds. + 0 + 32 + read-only + + + + + PACKET6 + DCP work packet 6 status register + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + This regiser reflects the payload pointer for the current control packet. + 0 + 32 + read-only + + + + + CH0CMDPTR + DCP channel 0 command pointer address register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 0. + 0 + 32 + read-write + + + + + CH0SEMA + DCP channel 0 semaphore register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 0x10 + 8 + read-only + + + + + CH0STAT + DCP channel 0 status register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit + 0x1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 0x2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload + 0x3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 0x4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 0x5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 0x6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions + 0x10 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error signalled because the next pointer is 0x00000000 + 0x1 + + + NO_CHAIN + Error signalled because the semaphore is non-zero and neither chain bit is set + 0x2 + + + CONTEXT_ERROR + Error signalled because an error is reported reading/writing the context buffer + 0x3 + + + PAYLOAD_ERROR + Error signalled because an error is reported reading/writing the payload + 0x4 + + + INVALID_MODE + Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure + 0x18 + 8 + read-only + + + + + CH0OPTS + DCP channel 0 options register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH1CMDPTR + DCP channel 1 command pointer address register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 1. + 0 + 32 + read-write + + + + + CH1SEMA + DCP channel 1 semaphore register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and the DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 0x10 + 8 + read-only + + + + + CH1STAT + DCP channel 1 status register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 0x1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 0x2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 0x3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 0x4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 0x5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 0x6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions. + 0x10 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported when reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported when reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 0x18 + 8 + read-only + + + + + CH1OPTS + DCP channel 1 options register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH2CMDPTR + DCP channel 2 command pointer address register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 2. + 0 + 32 + read-write + + + + + CH2SEMA + DCP channel 2 semaphore register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 0x10 + 8 + read-only + + + + + CH2STAT + DCP channel 2 status register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 0x1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 0x2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 0x3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 0x4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 0x5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 0x6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 0x10 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 0x18 + 8 + read-only + + + + + CH2OPTS + DCP channel 2 options register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH3CMDPTR + DCP channel 3 command pointer address register + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 3. + 0 + 32 + read-write + + + + + CH3SEMA + DCP channel 3 semaphore register + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 0x10 + 8 + read-only + + + + + CH3STAT + DCP channel 3 status register + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 0x1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 0x2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod + 0x3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 0x4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 0x5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 0x6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 0x10 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 0x18 + 8 + read-only + + + + + CH3OPTS + DCP channel 3 options register + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + DBGSELECT + DCP debug select register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + INDEX + Selects a value to read via the debug data register. + 0 + 8 + read-write + + + CONTROL + no description available + 0x1 + + + OTPKEY0 + no description available + 0x10 + + + OTPKEY1 + no description available + 0x11 + + + OTPKEY2 + no description available + 0x12 + + + OTPKEY3 + no description available + 0x13 + + + + + + + DBGDATA + DCP debug data register + 0x410 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Debug data + 0 + 32 + read-only + + + + + PAGETABLE + DCP page table register + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Page table enable control + 0 + 1 + read-write + + + FLUSH + Page table flush control. To flush the TLB, write this bit to 1 and then back to 0. + 0x1 + 1 + read-write + + + BASE + Page table base address + 0x2 + 30 + read-write + + + + + VERSION + DCP version register + 0x430 + 32 + read-only + 0x2010000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the version of the design implementation. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR version of the design implementation. + 0x10 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR version of the design implementation. + 0x18 + 8 + read-only + + + + + + + RNG + Random number generator + RNG + RNG_ + 0x2284000 + + 0 + 0x18 + registers + + + RNGB + 38 + + + + VER + RNGB version ID register + 0 + 32 + read-only + 0x10000280 + 0xFFFFFFFF + + + MINOR + Minor version number + 0 + 8 + read-only + + + MAJOR + Major version number + 0x8 + 8 + read-only + + + TYPE + Random number generator type + 0x1C + 4 + read-only + + + TYPE_0 + RNGA + 0 + + + TYPE_1 + RNGB (This is the type used in this module.) + 0x1 + + + TYPE_2 + RNGC + 0x2 + + + + + + + CMD + RNGB command register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ST + Self test + 0 + 1 + read-write + + + ST_0 + Not in the self-test mode + 0 + + + ST_1 + Self-test mode + 0x1 + + + + + GS + Generate the seed. + 0x1 + 1 + read-write + + + GS_0 + Not in the seed generation mode + 0 + + + GS_1 + Generate the seed mode. + 0x1 + + + + + CI + Clear the interrupt. + 0x4 + 1 + write-only + + + CI_0 + Do not clear the interrupt. + 0 + + + CI_1 + Clear the interrupt. + 0x1 + + + + + CE + Clear the error. + 0x5 + 1 + write-only + + + CE_0 + Do not clear the errors and the interrupt. + 0 + + + CE_1 + Clear the errors and the interrupt. + 0x1 + + + + + SR + Software reset + 0x6 + 1 + write-only + + + SR_0 + Do not perform a software reset. + 0 + + + SR_1 + Software reset + 0x1 + + + + + + + CR + RNGB control register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FUFMOD + FIFO underflow response mode + 0 + 2 + read-write + + + FUFMOD_0 + Return all zeros and set the RNG_ESR[FUFE]. + 0 + + + FUFMOD_1 + Return all zeros and set the RNG_ESR[FUFE]. + 0x1 + + + FUFMOD_2 + Generate the bus transfer error + 0x2 + + + FUFMOD_3 + Generate the interrupt and return all zeros (overrides the RNG_CR[MASKERR]). + 0x3 + + + + + AR + Auto-reseed + 0x4 + 1 + read-write + + + AR_0 + Do not enable the automatic reseeding. + 0 + + + AR_1 + Enable the automatic reseeding. + 0x1 + + + + + MASKDONE + Mask the interrupt done. + 0x5 + 1 + read-write + + + MASKDONE_0 + No mask is applied. + 0 + + + MASKDONE_1 + The mask is applied. + 0x1 + + + + + MASKERR + Mask the error interrupt. + 0x6 + 1 + read-write + + + MASKERR_0 + No mask is applied. + 0 + + + MASKERR_1 + The mask applied to the error interrupt + 0x1 + + + + + + + SR + RNGB status register + 0xC + 32 + read-only + 0x500D + 0xFFFFFFFF + + + BUSY + Busy. + 0x1 + 1 + read-only + + + BUSY_0 + Not busy + 0 + + + BUSY_1 + Busy + 0x1 + + + + + SLP + Sleep + 0x2 + 1 + read-only + + + SLP_0 + The RNGB is not in the sleep mode. + 0 + + + SLP_1 + The RNGB is in the sleep mode. + 0x1 + + + + + RS + Reseed needed + 0x3 + 1 + read-only + + + RS_0 + The RNGB does not need to be reseeded. + 0 + + + RS_1 + The RNGB needs to be reseeded. + 0x1 + + + + + STDN + Self test done + 0x4 + 1 + read-only + + + STDN_0 + Self test not completed + 0 + + + STDN_1 + Completed a self test since the last reset + 0x1 + + + + + SDN + Seed done + 0x5 + 1 + read-only + + + SDN_0 + The seed-generation process is not complete. + 0 + + + SDN_1 + Completed the seed generation since the last reset + 0x1 + + + + + NSDN + New seed done + 0x6 + 1 + read-only + + + FIFO_LVL + FIFO level + 0x8 + 4 + read-only + + + FIFO_SIZE + FIFO size + 0xC + 4 + read-only + + + ERR + Error + 0x10 + 1 + read-only + + + ERR_0 + No error + 0 + + + ERR_1 + Error detected + 0x1 + + + + + ST_PF + Self-test pass fail + 0x15 + 3 + read-only + + + ST_PF_0 + Pass + 0 + + + ST_PF_1 + Fail + 0x1 + + + + + STATPF + Statistics test pass failed. + 0x18 + 8 + read-only + + + STATPF_0 + Pass + 0 + + + STATPF_1 + Fail + 0x1 + + + + + + + ESR + RNGB error status register + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + LFE + Linear feedback shift register (LFSR) error + 0 + 1 + read-only + + + LFE_0 + The LFSRs are working properly. + 0 + + + LFE_1 + The LFSR failure occurred. + 0x1 + + + + + OSCE + Oscillator error + 0x1 + 1 + read-only + + + OSCE_0 + The RNG oscillator is working properly. + 0 + + + OSCE_1 + A problem with the RNG oscillator was detected. + 0x1 + + + + + STE + Self-test error + 0x2 + 1 + read-only + + + STE_0 + The RNGB did not fail the self test. + 0 + + + STE_1 + The RNGB failed the self test. + 0x1 + + + + + SATE + Statistical test error + 0x3 + 1 + read-only + + + SATE_0 + The RNGB did not fail the statistical tests. + 0 + + + SATE_1 + The RNGB failed the statistical tests during the initialization. + 0x1 + + + + + FUFE + FIFO underflow error + 0x4 + 1 + read-only + + + FUFE_0 + FIFO underflow did not occur. + 0 + + + FUFE_1 + FIFO underflow occurred. + 0x1 + + + + + + + OUT + RNGB Output FIFO + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + RANDOUT + Random output + 0 + 32 + read-only + + + + + + + IOMUXC_SNVS + IOMUXC_SNVS + IOMUXC_SNVS + IOMUXC_SNVS_ + 0x2290000 + + 0 + 0x74 + registers + + + + SW_MUX_CTL_PAD_BOOT_MODE0 + SW_MUX_CTL_PAD_BOOT_MODE0 SW MUX Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO10 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad BOOT_MODE0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_BOOT_MODE1 + SW_MUX_CTL_PAD_BOOT_MODE1 SW MUX Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO11 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad BOOT_MODE1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER0 + SW_MUX_CTL_PAD_SNVS_TAMPER0 SW MUX Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER0 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER1 + SW_MUX_CTL_PAD_SNVS_TAMPER1 SW MUX Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + ALT5 mode is only valid when TAMPER PIN is used as GPIO + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER1 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER2 + SW_MUX_CTL_PAD_SNVS_TAMPER2 SW MUX Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + ALT5 mode is only valid when TAMPER PIN is used as GPIO + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER2 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER3 + SW_MUX_CTL_PAD_SNVS_TAMPER3 SW MUX Control Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + Mux Mode Select Field + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO03 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER3 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER4 + SW_MUX_CTL_PAD_SNVS_TAMPER4 SW MUX Control Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + ALT5 mode is only valid when TAMPER PIN is used as GPIO + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO04 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER4 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER5 + SW_MUX_CTL_PAD_SNVS_TAMPER5 SW MUX Control Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO05 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER5 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER6 + SW_MUX_CTL_PAD_SNVS_TAMPER6 SW MUX Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + ALT5 mode is only valid when TAMPER PIN is used as GPIO + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO06 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER6 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER7 + SW_MUX_CTL_PAD_SNVS_TAMPER7 SW MUX Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + ALT5 mode is only valid when TAMPER PIN is used as GPIO + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO07 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER7 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER8 + SW_MUX_CTL_PAD_SNVS_TAMPER8 SW MUX Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + ALT5 mode is only valid when TAMPER PIN is used as GPIO + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO08 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER8 + 0x1 + + + + + + + SW_MUX_CTL_PAD_SNVS_TAMPER9 + SW_MUX_CTL_PAD_SNVS_TAMPER9 SW MUX Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + ALT5 mode is only valid when TAMPER PIN is used as GPIO + 0 + 4 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO09 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 0x4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad SNVS_TAMPER9 + 0x1 + + + + + + + SW_PAD_CTL_PAD_TEST_MODE + SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register + 0x30 + 32 + read-write + 0x30A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_POR_B + SW_PAD_CTL_PAD_POR_B SW PAD Control Register + 0x34 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ONOFF + SW_PAD_CTL_PAD_ONOFF SW PAD Control Register + 0x38 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_PMIC_ON_REQ + SW_PAD_CTL_PAD_SNVS_PMIC_ON_REQ SW PAD Control Register + 0x3C + 32 + read-write + 0xB8A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_CCM_PMIC_STBY_REQ + SW_PAD_CTL_PAD_CCM_PMIC_STBY_REQ SW PAD Control Register + 0x40 + 32 + read-write + 0x20A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_BOOT_MODE0 + SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control Register + 0x44 + 32 + read-write + 0x130A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_BOOT_MODE1 + SW_PAD_CTL_PAD_BOOT_MODE1 SW PAD Control Register + 0x48 + 32 + read-write + 0x130A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER0 + SW_PAD_CTL_PAD_SNVS_TAMPER0 SW PAD Control Register + 0x4C + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER1 + SW_PAD_CTL_PAD_SNVS_TAMPER1 SW PAD Control Register + 0x50 + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER2 + SW_PAD_CTL_PAD_SNVS_TAMPER2 SW PAD Control Register + 0x54 + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER3 + SW_PAD_CTL_PAD_SNVS_TAMPER3 SW PAD Control Register + 0x58 + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER4 + SW_PAD_CTL_PAD_SNVS_TAMPER4 SW PAD Control Register + 0x5C + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER5 + SW_PAD_CTL_PAD_SNVS_TAMPER5 SW PAD Control Register + 0x60 + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER6 + SW_PAD_CTL_PAD_SNVS_TAMPER6 SW PAD Control Register + 0x64 + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER7 + SW_PAD_CTL_PAD_SNVS_TAMPER7 SW PAD Control Register + 0x68 + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER8 + SW_PAD_CTL_PAD_SNVS_TAMPER8 SW PAD Control Register + 0x6C + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_SNVS_TAMPER9 + SW_PAD_CTL_PAD_SNVS_TAMPER9 SW PAD Control Register + 0x70 + 32 + read-write + 0x110A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 0x3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 0x6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 0xB + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 0xC + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 0xD + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 0xE + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 0x10 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2_features.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2_features.h new file mode 100644 index 0000000000..15180c2bdd --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/MCIMX6Y2_features.h @@ -0,0 +1,801 @@ +/* +** ################################################################### +** Version: rev. 3.0, 2017-02-28 +** Build: b170422 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-12-18) +** Initial version. +** - rev. 2.0 (2016-08-02) +** Rev.B Header GA +** - rev. 3.0 (2017-02-28) +** Rev.1 Header GA +** +** ################################################################### +*/ + +#ifndef _MCIMX6Y2_FEATURES_H_ +#define _MCIMX6Y2_FEATURES_H_ + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0) +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (0) +/* @brief ADC_5HC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_5HC_COUNT (1) +/* @brief AES availability on the SoC. */ +#define FSL_FEATURE_SOC_AES_COUNT (0) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0) +/* @brief AGC availability on the SoC. */ +#define FSL_FEATURE_SOC_AGC_COUNT (0) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0) +/* @brief AIPSTZ availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPSTZ_COUNT (3) +/* @brief ANATOP availability on the SoC. */ +#define FSL_FEATURE_SOC_ANATOP_COUNT (0) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0) +/* @brief APBH availability on the SoC. */ +#define FSL_FEATURE_SOC_APBH_COUNT (1) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0) +/* @brief ASRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASRC_COUNT (1) +/* @brief ASYNC_SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (0) +/* @brief ATX availability on the SoC. */ +#define FSL_FEATURE_SOC_ATX_COUNT (0) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0) +/* @brief BCH availability on the SoC. */ +#define FSL_FEATURE_SOC_BCH_COUNT (1) +/* @brief BLEDP availability on the SoC. */ +#define FSL_FEATURE_SOC_BLEDP_COUNT (0) +/* @brief BOD availability on the SoC. */ +#define FSL_FEATURE_SOC_BOD_COUNT (0) +/* @brief CAAM availability on the SoC. */ +#define FSL_FEATURE_SOC_CAAM_COUNT (0) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0) +/* @brief CALIB availability on the SoC. */ +#define FSL_FEATURE_SOC_CALIB_COUNT (0) +/* @brief CAN availability on the SoC. */ +#define FSL_FEATURE_SOC_CAN_COUNT (0) +/* @brief CAU availability on the SoC. */ +#define FSL_FEATURE_SOC_CAU_COUNT (0) +/* @brief CAU3 availability on the SoC. */ +#define FSL_FEATURE_SOC_CAU3_COUNT (0) +/* @brief CCM availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_COUNT (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief CHRG availability on the SoC. */ +#define FSL_FEATURE_SOC_CHRG_COUNT (0) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (0) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (0) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0) +/* @brief COP availability on the SoC. */ +#define FSL_FEATURE_SOC_COP_COUNT (0) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (0) +/* @brief CS availability on the SoC. */ +#define FSL_FEATURE_SOC_CS_COUNT (0) +/* @brief CSI availability on the SoC. */ +#define FSL_FEATURE_SOC_CSI_COUNT (1) +/* @brief CT32B availability on the SoC. */ +#define FSL_FEATURE_SOC_CT32B_COUNT (0) +/* @brief CTI availability on the SoC. */ +#define FSL_FEATURE_SOC_CTI_COUNT (0) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (0) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (0) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (0) +/* @brief DCP availability on the SoC. */ +#define FSL_FEATURE_SOC_DCP_COUNT (1) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (0) +/* @brief DDRC availability on the SoC. */ +#define FSL_FEATURE_SOC_DDRC_COUNT (0) +/* @brief DDRC_MP availability on the SoC. */ +#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0) +/* @brief DDR_PHY availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (0) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (0) +/* @brief DMIC availability on the SoC. */ +#define FSL_FEATURE_SOC_DMIC_COUNT (0) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (0) +/* @brief ECSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_ECSPI_COUNT (4) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (0) +/* @brief EEPROM availability on the SoC. */ +#define FSL_FEATURE_SOC_EEPROM_COUNT (0) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EMC availability on the SoC. */ +#define FSL_FEATURE_SOC_EMC_COUNT (0) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (2) +/* @brief EPDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EPDC_COUNT (0) +/* @brief EPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_EPIT_COUNT (2) +/* @brief ESAI availability on the SoC. */ +#define FSL_FEATURE_SOC_ESAI_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (0) +/* @brief FLASH availability on the SoC. */ +#define FSL_FEATURE_SOC_FLASH_COUNT (0) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (0) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) +/* @brief FLEXRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXRAM_COUNT (0) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (0) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (0) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0) +/* @brief FSP availability on the SoC. */ +#define FSL_FEATURE_SOC_FSP_COUNT (0) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (0) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (0) +/* @brief GPC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_COUNT (1) +/* @brief GPC_PGC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (0) +/* @brief GPMI availability on the SoC. */ +#define FSL_FEATURE_SOC_GPMI_COUNT (1) +/* @brief GPT availability on the SoC. */ +#define FSL_FEATURE_SOC_GPT_COUNT (2) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (0) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (3) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0) +/* @brief IEE availability on the SoC. */ +#define FSL_FEATURE_SOC_IEE_COUNT (0) +/* @brief IEER availability on the SoC. */ +#define FSL_FEATURE_SOC_IEER_COUNT (0) +/* @brief IGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_IGPIO_COUNT (5) +/* @brief II2C availability on the SoC. */ +#define FSL_FEATURE_SOC_II2C_COUNT (4) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (0) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (0) +/* @brief IOMUXC availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_COUNT (1) +/* @brief IOMUXC_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) +/* @brief IOMUXC_LPSR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0) +/* @brief IOMUXC_LPSR_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0) +/* @brief IOMUXC_SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1) +/* @brief IPWM availability on the SoC. */ +#define FSL_FEATURE_SOC_IPWM_COUNT (8) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0) +/* @brief IUART availability on the SoC. */ +#define FSL_FEATURE_SOC_IUART_COUNT (8) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0) +/* @brief KPP availability on the SoC. */ +#define FSL_FEATURE_SOC_KPP_COUNT (1) +/* @brief L2CACHEC availability on the SoC. */ +#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0) +/* @brief LCD availability on the SoC. */ +#define FSL_FEATURE_SOC_LCD_COUNT (0) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0) +/* @brief LCDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDIF_COUNT (1) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (0) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (0) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (0) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (0) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (0) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (0) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (0) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (0) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (0) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (0) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (0) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (0) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (0) +/* @brief MIPI_CSI2 availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0) +/* @brief MIPI_DSI availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0) +/* @brief MIPI_DSI_HOST availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0) +/* @brief MMDC availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDC_COUNT (1) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (0) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (0) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (0) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (0) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (0) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0) +/* @brief OCOTP availability on the SoC. */ +#define FSL_FEATURE_SOC_OCOTP_COUNT (1) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (0) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0) +/* @brief PCIE_PHY_CMN availability on the SoC. */ +#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0) +/* @brief PCIE_PHY_TRSV availability on the SoC. */ +#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (0) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (0) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (0) +/* @brief PMU availability on the SoC. */ +#define FSL_FEATURE_SOC_PMU_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (0) +/* @brief PROP availability on the SoC. */ +#define FSL_FEATURE_SOC_PROP_COUNT (0) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0) +/* @brief PXP availability on the SoC. */ +#define FSL_FEATURE_SOC_PXP_COUNT (1) +/* @brief QDEC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDEC_COUNT (0) +/* @brief QuadSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPI_COUNT (1) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (0) +/* @brief RDC availability on the SoC. */ +#define FSL_FEATURE_SOC_RDC_COUNT (0) +/* @brief RDC_SEMAPHORE availability on the SoC. */ +#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (0) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) +/* @brief RIT availability on the SoC. */ +#define FSL_FEATURE_SOC_RIT_COUNT (0) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (1) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (0) +/* @brief ROMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ROMC_COUNT (1) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (0) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (0) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (0) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0) +/* @brief SDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIF_COUNT (0) +/* @brief SDIO availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIO_COUNT (0) +/* @brief SDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMA_COUNT (1) +/* @brief SDMAARM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMAARM_COUNT (0) +/* @brief SDMABP availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMABP_COUNT (0) +/* @brief SDMACORE availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMACORE_COUNT (0) +/* @brief SDMCORE availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMCORE_COUNT (0) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0) +/* @brief SEMA4 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA4_COUNT (0) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0) +/* @brief SHA availability on the SoC. */ +#define FSL_FEATURE_SOC_SHA_COUNT (0) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (0) +/* @brief SIMDGO availability on the SoC. */ +#define FSL_FEATURE_SOC_SIMDGO_COUNT (0) +/* @brief SJC availability on the SoC. */ +#define FSL_FEATURE_SOC_SJC_COUNT (0) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0) +/* @brief SMARTCARD availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTCARD_COUNT (0) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (0) +/* @brief SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_SNVS_COUNT (1) +/* @brief SPBA availability on the SoC. */ +#define FSL_FEATURE_SOC_SPBA_COUNT (1) +/* @brief SPDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SPDIF_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (0) +/* @brief SPIFI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPIFI_COUNT (0) +/* @brief SPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SPM_COUNT (0) +/* @brief SRC availability on the SoC. */ +#define FSL_FEATURE_SOC_SRC_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (0) +/* @brief TEMPMON availability on the SoC. */ +#define FSL_FEATURE_SOC_TEMPMON_COUNT (1) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (0) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (0) +/* @brief TSC availability on the SoC. */ +#define FSL_FEATURE_SOC_TSC_COUNT (1) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (0) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (0) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (0) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (0) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (2) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0) +/* @brief USBFSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBFSH_COUNT (0) +/* @brief USBHSD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSD_COUNT (0) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) +/* @brief USBHSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSH_COUNT (0) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (2) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (2) +/* @brief USB_HSIC availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0) +/* @brief USB_OTG availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_OTG_COUNT (0) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (2) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (0) +/* @brief VIU availability on the SoC. */ +#define FSL_FEATURE_SOC_VIU_COUNT (0) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (0) +/* @brief VFIFO availability on the SoC. */ +#define FSL_FEATURE_SOC_VFIFO_COUNT (0) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (3) +/* @brief WKPU availability on the SoC. */ +#define FSL_FEATURE_SOC_WKPU_COUNT (0) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (0) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (0) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (0) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (0) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0) +/* @brief XTALOSC availability on the SoC. */ +#define FSL_FEATURE_SOC_XTALOSC_COUNT (0) +/* @brief XTALOSC24M availability on the SoC. */ +#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (0) + +/* ADC module features */ + +/* @brief Remove Hardware Trigger feature. */ +#define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (1) +/* @brief Remove ALT Clock selection feature. */ +#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1) + +/* CACHEC module features */ + +/* @brief L1 ICACHE line size in byte. */ +#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) +/* @brief L1 DCACHE line size in byte. */ +#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (64) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) +/* @brief Has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0) +/* @brief Has extra MB interrupt or common one. */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (0) + +/* ECSPI module features */ + +/* @brief ECSPI Tx FIFO Size. */ +#define FSL_FEATURE_ECSPI_TX_FIFO_SIZEn(x) (64) + +/* ENET module features */ + +/* @brief Support Interrupt Coalesce */ +#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1) +/* @brief Queue Size. */ +#define FSL_FEATURE_ENET_QUEUE (1) +/* @brief Has AVB Support. */ +#define FSL_FEATURE_ENET_HAS_AVB (0) +/* @brief Has Timer Pulse Width control. */ +#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1) +/* @brief Has Extend MDIO Support. */ +#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) +/* @brief Has Additional 1588 Timer Channel Interrupt. */ +#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (1) + +/* ESAI module features */ + +/* @brief ESAI FIFO Size. */ +#define FSL_FEATURE_ESAI_FIFO_SIZEn(x) (128) + +/* GPC module features */ + +/* @brief Has No DVFS0 Change Request. */ +#define FSL_FEATURE_GPC_HAS_NO_CNTR_DVFS0CR (1) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNT (32) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNT (1) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (0) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) + +/* MMDC module features */ + +/* @brief MMDC module has CLK32 clock source gate. */ +#define FSL_FEATURE_MMDC_HAS_CLK32_GATE (1) +/* @brief MMDC module has arbitration and reordering control. */ +#define FSL_FEATURE_MMDC_HAS_ARB_REO_CONTROL (0) + +/* PXP module features */ + +/* @brief PXP module has dither engine. */ +#define FSL_FEATURE_PXP_HAS_DITHER (1) +/* @brief PXP module supports repeat run */ +#define FSL_FEATURE_PXP_HAS_EN_REPEAT (0) + +/* QSPI module features */ + +/* @brief QSPI lookup table depth. */ +#define FSL_FEATURE_QSPI_LUT_DEPTH (64) +/* @brief QSPI Tx FIFO depth. */ +#define FSL_FEATURE_QSPI_TXFIFO_DEPTH (16) +/* @brief QSPI Rx FIFO depth. */ +#define FSL_FEATURE_QSPI_RXFIFO_DEPTH (16) +/* @brief QSPI AHB buffer count. */ +#define FSL_FEATURE_QSPI_AHB_BUFFER_COUNT (4) +/* @brief QSPI has command usage error flag. */ +#define FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR (1) +/* @brief QSPI support parallel mode. */ +#define FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE (1) +/* @brief QSPI support dual die. */ +#define FSL_FEATURE_QSPI_SUPPORT_DUAL_DIE (1) +/* @brief there is no SCLKCFG bit in MCR register. */ +#define FSL_FEATURE_QSPI_CLOCK_CONTROL_EXTERNAL (1) +/* @brief there is no AITEF bit in FR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_AITEF (1) +/* @brief there is no AIBSEF bit in FR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_AIBSEF (1) +/* @brief there is no TXDMA and TXWA bit in SR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_TXDMA (1) +/* @brief there is no SFACR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_SFACR (1) +/* @brief there is no TDH bit in FLSHCR register. */ +#define FSL_FEATURE_QSPI_HAS_NO_TDH (1) +/* @brief QSPI AMBA base address. */ +#define FSL_FEATURE_QSPI_AMBA_BASE (0x60000000U) +/* @brief QSPI AHB buffer ARDB base address. */ +#define FSL_FEATURE_QSPI_ARDB_BASE (0x0C000000U) + +/* SDMA module features */ + +/* @brief SDMA module channel number. */ +#define FSL_FEATURE_SDMA_MODULE_CHANNEL (32) +/* @brief SDMA module event number. */ +#define FSL_FEATURE_SDMA_EVENT_NUM (48) +/* @brief SDMA ROM memory to memory script start address. */ +#define FSL_FEATURE_SDMA_M2M_ADDR (642) +/* @brief SDMA ROM peripheral to memory script start address. */ +#define FSL_FEATURE_SDMA_P2M_ADDR (683) +/* @brief SDMA ROM memory to peripheral script start address. */ +#define FSL_FEATURE_SDMA_M2P_ADDR (747) +/* @brief SDMA ROM uart to memory script start address. */ +#define FSL_FEATURE_SDMA_UART2M_ADDR (817) +/* @brief SDMA ROM peripheral on SPBA to memory script start address. */ +#define FSL_FEATURE_SDMA_SHP2M_ADDR (891) +/* @brief SDMA ROM memory to peripheral on SPBA script start address. */ +#define FSL_FEATURE_SDMA_M2SHP_ADDR (960) +/* @brief SDMA ROM UART on SPBA to memory script start address. */ +#define FSL_FEATURE_SDMA_UARTSH2M_ADDR (1032) +/* @brief SDMA ROM SPDIF to memory script start address. */ +#define FSL_FEATURE_SDMA_SPDIF2M_ADDR (1100) +/* @brief SDMA ROM memory to SPDIF script start address. */ +#define FSL_FEATURE_SDMA_M2SPDIF_ADDR (1134) + +/* SNVS module features */ + +/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ +#define FSL_FEATURE_SNVS_HAS_SRTC (0) + +/* SPBA module features */ + +/* @brief SPBA module start address. */ +#define FSL_FEATURE_SPBA_START (0x02000000U) +/* @brief SPBA module end address. */ +#define FSL_FEATURE_SPBA_END (0x0203FFFFU) + +/* SRC module features */ + +/* @brief There is MASK_WDOG3_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1) +/* @brief There is MIX_RST_STRCH bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (1) +/* @brief There is DBG_RST_MSK_PG bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1) +/* @brief There is WDOG3_RST_OPTN bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (1) +/* @brief There is CORES_DBG_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (1) +/* @brief There is MTSR bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MTSR (0) +/* @brief There is CORE0_DBG_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1) +/* @brief There is CORE0_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1) +/* @brief There is SWRC bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_SWRC (0) +/* @brief There is EIM_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (1) +/* @brief There is LUEN bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_LUEN (0) +/* @brief There is SISR register. */ +#define FSL_FEATURE_SRC_HAS_SISR (1) +/* @brief There is RESET_OUT bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0) +/* @brief There is WDOG3_RST_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1) +/* @brief There is SW bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_SW (0) +/* @brief There is IPP_USER_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1) +/* @brief There is SNVS bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0) +/* @brief There is CSU_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1) +/* @brief There is LOCKUP bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (0) +/* @brief There is POR bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_POR (0) +/* @brief There is IPP_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1) + +/* IUART module features */ + +/* @brief UART Transmit/Receive FIFO Size */ +#define FSL_FEATURE_IUART_FIFO_SIZEn(x) (32) +/* @brief UART RX MUXed input selected option */ +#define FSL_FEATURE_IUART_RXDMUXSEL (1) + +/* USBHS module features */ + +/* @brief EHCI module instance count */ +#define FSL_FEATURE_USBHS_EHCI_COUNT (2) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USBHS_ENDPT_COUNT (8) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (1) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) + +#endif /* _MCIMX6Y2_FEATURES_H_ */ + diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/SConscript b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/SConscript new file mode 100644 index 0000000000..97865d743a --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/SConscript @@ -0,0 +1,13 @@ +from building import * + +cwd = GetCurrentDir() +src = ['system_MCIMX6Y2.c'] + Glob('drivers/*.c') +CPPDEFINES = ['CHIP_MX6UL', 'CPU_MCIMX6Y2DVM09'] +path = [cwd, cwd + '/drivers'] + +src += Glob('drivers/usdhc/*.c') +path.append(cwd + '/drivers/usdhc') + +group = DefineGroup('libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_cache.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_cache.c new file mode 100644 index 0000000000..8df9a16f9e --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_cache.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_InvalidateICacheByRange(address, size_byte); +} + +void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_InvalidateDCacheByRange(address, size_byte); +} + +void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_CleanDCacheByRange(address, size_byte); +} + +void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_CleanInvalidateDCacheByRange(address, size_byte); +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_cache.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_cache.h new file mode 100644 index 0000000000..7eedede9e3 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_cache.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_CACHE_H_ +#define _FSL_CACHE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cache + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief cache driver version 2.0.0. */ +#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Cache Control for Cortex-a L1 cache + *@{ + */ + +/*! + * @brief Enables L1 instruction cache. + * + */ +static inline void L1CACHE_EnableICache(void) +{ + L1C_EnableInstructionCache(); +} +/*! + * @brief Disables L1 instruction cache. + * + */ +static inline void L1CACHE_DisableICache(void) +{ + L1C_DisableInstructionCache(); +} +/*! + * @brief Invalidates L1 instruction cache all. + * + */ +static inline void L1CACHE_InvalidateICache(void) +{ + L1C_InvalidateInstructionCacheAll(); +} +/*! + * @brief Invalidates L1 instruction cache by range. + * + * @param startAddr The start startAddr of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start startAddr and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned due to the + * cache operation unit is one L1 I-cache line. The startAddr here will be forced + * to align to L1 I-cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_InvalidateICacheByRange(uint32_t startAddr, uint32_t size_byte) +{ + L1C_InvalidateInstructionCacheRange((void *)startAddr, size_byte); +} +/*! + * @brief Enables L1 data cache. + * + */ +static inline void L1CACHE_EnableDCache(void) +{ + L1C_EnableDataCache(); +} +/*! + * @brief Disables L1 data cache. + * + */ +static inline void L1CACHE_DisableDCache(void) +{ + L1C_DisableDataCache(); +} +/*! + * @brief Invalidates L1 data cache all. + * + */ +static inline void L1CACHE_InvalidateDCache(void) +{ + L1C_InvalidateDataCacheAll(); +} +/*! + * @brief Invalidates L1 data cache by range. + * + * @param startAddr The start startAddr of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start startAddr and size_byte should be 64-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned due to the + * cache operation unit is one L1 D-cache line. The startAddr here will be forced + * to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_InvalidateDCacheByRange(uint32_t startAddr, uint32_t size_byte) +{ + L1C_InvalidateDataCacheRange((void *)startAddr, size_byte); +} +/*! + * @brief Clean L1 data cache all. + * + */ +static inline void L1CACHE_CleanDCache(void) +{ + L1C_CleanDataCacheAll(); +} +/*! + * @brief Cleans L1 data cache by range. + * + * @param startAddr The start startAddr of the memory to be cleaned. + * @param size_byte The memory size. + * @note The start startAddr and size_byte should be 64-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned due to the + * cache operation unit is one L1 D-cache line. The startAddr here will be forced + * to align to L1 D-cache line size if startAddr is not aligned. For size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_CleanDCacheByRange(uint32_t startAddr, uint32_t size_byte) +{ + L1C_CleanDataCacheRange((void *)startAddr, size_byte); +} +/*! + * @brief Cleans and invalidates L1 data cache all. + * + */ +static inline void L1CACHE_CleanInvalidateDCache(void) +{ + L1C_CleanInvalidateDataCacheAll(); +} +/*! + * @brief Cleans and invalidates L1 data cache by range. + * + * @param startAddr The start startAddr of the memory to be clean and invalidated. + * @param size_byte The memory size. + * @note The start startAddr and size_byte should be 64-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned due to the + * cache operation unit is one L1 D-cache line. The startAddr here will be forced + * to align to L1 D-cache line size if startAddr is not aligned. For size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t startAddr, uint32_t size_byte) +{ + L1C_CleanInvalidateDataCacheRange((void *)startAddr, size_byte); +} +/*@}*/ + +/*! + * @name Unified Cache Control for all caches which is mainly used for + * SDK Driver easy use cache driver + *@{ + */ + +/*! + * @brief Invalidates instruction cache by range. + * + * Cortex-a L1 instruction cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Invalidates data cache by range. + * + * Cortex-a L1 data cache line length is 64-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to cache line size + * 64-byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans data cache by range. + * + * Cortex-a L1 data cache line length is 64-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned. + * @note Address and size should be aligned to cache line size + * 64-byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and Invalidates data cache by range. + * + * Cortex-a L1 data cache line length is 64-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned and invalidated. + * @note Address and size should be aligned to cache line size + * 64-byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); +/*@}*/ +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CACHE_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_clock.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_clock.c new file mode 100644 index 0000000000..347d92e105 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_clock.c @@ -0,0 +1,915 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* External XTAL (OSC) clock frequency. */ +uint32_t g_xtalFreq; +/* External RTC XTAL clock frequency. */ +uint32_t g_rtcXtalFreq; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t CLOCK_GetPeriphClkFreq(void) +{ + uint32_t freq; + + /* Periph_clk2_clk ---> Periph_clk */ + if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) + { + switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) + { + /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + + /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(1U): + freq = CLOCK_GetOscFreq(); + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): + default: + freq = 0U; + break; + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); + } + /* Pll2_main_clk ---> Periph_clk */ + else + { + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + { + /* PLL2 ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + /* PLL2 PFD2 ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + + /* PLL2 PFD0 ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + + /* PLL2 PFD2 divided(/2) ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): + freq = (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) >> 1U); + break; + + default: + freq = 0U; + break; + } + } + + return freq; +} + +void CLOCK_InitExternalClk(bool bypassXtalOsc) +{ + /* This device does not support bypass XTAL OSC. */ + assert(!bypassXtalOsc); + + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power up */ + while ((PMU->LOWPWR_CTRL & PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0) + { + } + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; /* detect freq */ + while ((CCM_ANALOG->MISC0 & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) == 0) + { + } + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; +} + +void CLOCK_DeinitExternalClk(void) +{ + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */ +} + +void CLOCK_SwitchOsc(clock_osc_t osc) +{ + if (osc == kCLOCK_RcOsc) + PMU->LOWPWR_CTRL_SET = PMU_LOWPWR_CTRL_OSC_SEL_MASK; + else + PMU->LOWPWR_CTRL_CLR = PMU_LOWPWR_CTRL_OSC_SEL_MASK; +} + +void CLOCK_InitRcOsc24M(void) +{ + PMU->LOWPWR_CTRL |= PMU_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +void CLOCK_DeinitRcOsc24M(void) +{ + PMU->LOWPWR_CTRL &= ~PMU_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +uint32_t CLOCK_GetFreq(clock_name_t name) +{ + uint32_t freq; + + switch (name) + { + case kCLOCK_CpuClk: + switch (CCM->CCSR & (CCM_CCSR_STEP_SEL_MASK | CCM_CCSR_SECONDARY_CLK_SEL_MASK | CCM_CCSR_PLL1_SW_CLK_SEL_MASK)) + { + /* ARM PLL ---> CPU Clock */ + case 0U: + freq = CLOCK_GetPllFreq(kCLOCK_PllArm); + break; + + /* Osc_clk (24M) ---> Step Clock ---> CPU Clock */ + case (CCM_CCSR_PLL1_SW_CLK_SEL_MASK): + freq = CLOCK_GetOscFreq(); + break; + + /* PLL2 PFD2 ---> Secondary_clk ---> Step Clock ---> CPU Clock */ + case (CCM_CCSR_PLL1_SW_CLK_SEL_MASK | CCM_CCSR_STEP_SEL_MASK): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + + /* PLL2 ---> Secondary_clk ---> Step Clock ---> CPU Clock */ + case (CCM_CCSR_STEP_SEL_MASK | CCM_CCSR_SECONDARY_CLK_SEL_MASK | CCM_CCSR_PLL1_SW_CLK_SEL_MASK): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + default: + freq = 0U; + break; + } + freq /= (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); + break; + + case kCLOCK_AxiClk: + /* AXI alternative clock ---> AXI Clock */ + if (CCM->CBCDR & CCM_CBCDR_AXI_SEL_MASK) + { + /* PLL3 PFD1 ---> AXI alternative clock ---> AXI Clock */ + if (CCM->CBCDR & CCM_CBCDR_AXI_ALT_SEL_MASK) + { + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + } + /* PLL2 PFD2 ---> AXI alternative clock ---> AXI Clock */ + else + { + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + } + } + /* Periph_clk ---> AXI Clock */ + else + { + freq = CLOCK_GetPeriphClkFreq(); + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_AXI_PODF_MASK) >> CCM_CBCDR_AXI_PODF_SHIFT) + 1U); + break; + + case kCLOCK_AhbClk: + /* Periph_clk ---> AHB Clock */ + freq = CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); + break; + + case kCLOCK_IpgClk: + /* Periph_clk ---> AHB Clock ---> IPG Clock */ + freq = CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); + freq /= (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U); + break; + + case kCLOCK_MmdcClk: + /* periph2_clk2 ---> MMDC Clock */ + if (CCM->CBCDR & CCM_CBCDR_PERIPH2_CLK_SEL_MASK) + { + /* OSC ---> periph2_clk2 ---> MMDC Clock */ + if (CCM->CBCMR & CCM_CBCMR_PERIPH2_CLK2_SEL_MASK) + { + freq = CLOCK_GetOscFreq(); + } + /* pll3_sw_clk ---> periph2_clk2 ---> MMDC Clock */ + else + { + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH2_CLK2_PODF_SHIFT) + 1U); + } + /* pll2_main_clk ---> MMDC Clock */ + else + { + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) + { + /* PLL2 ---> pll2_main_clk ---> MMDC Clock */ + case CCM_CBCMR_PRE_PERIPH2_CLK_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + /* PLL2 PFD2 ---> pll2_main_clk ---> MMDC Clock */ + case CCM_CBCMR_PRE_PERIPH2_CLK_SEL(1U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + + /* PLL2 PFD0 ---> pll2_main_clk ---> MMDC Clock */ + case CCM_CBCMR_PRE_PERIPH2_CLK_SEL(2U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + + /* PLL4 ---> pll2_main_clk ---> MMDC Clock */ + case CCM_CBCMR_PRE_PERIPH2_CLK_SEL(3U): + freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + break; + + default: + freq = 0U; + break; + } + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_FABRIC_MMDC_PODF_MASK) >> CCM_CBCDR_FABRIC_MMDC_PODF_SHIFT) + 1U); + break; + + case kCLOCK_OscClk: + freq = CLOCK_GetOscFreq(); + break; + case kCLOCK_RtcClk: + freq = CLOCK_GetRtcFreq(); + break; + case kCLOCK_ArmPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllArm); + break; + case kCLOCK_Usb1PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + case kCLOCK_Usb1PllPfd0Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_Usb1PllPfd1Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_Usb1PllPfd2Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_Usb1PllPfd3Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_Usb2PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb2); + break; + case kCLOCK_SysPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + case kCLOCK_SysPllPfd0Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_SysPllPfd1Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_SysPllPfd2Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_SysPllPfd3Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_EnetPll0Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet0); + break; + case kCLOCK_EnetPll1Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet1); + break; + case kCLOCK_EnetPll2Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet2); + break; + case kCLOCK_AudioPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + break; + case kCLOCK_VideoPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllVideo); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config) +{ + CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_ENABLE_MASK | + CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0) + { + } +} + +void CLOCK_DeinitArmPll(void) +{ + CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK; +} + +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config) +{ + CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_ENABLE_MASK | + CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0) + { + } +} + +void CLOCK_DeinitSysPll(void) +{ + CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK; +} + +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config) +{ + CCM_ANALOG->PLL_USB1 = CCM_ANALOG_PLL_USB1_ENABLE_MASK | + CCM_ANALOG_PLL_USB1_POWER_MASK | + CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | + CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0) + { + } +} + +void CLOCK_DeinitUsb1Pll(void) +{ + CCM_ANALOG->PLL_USB1 = 0U; +} + +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config) +{ + CCM_ANALOG->PLL_USB2 = CCM_ANALOG_PLL_USB2_ENABLE_MASK | + CCM_ANALOG_PLL_USB2_POWER_MASK | + CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK | + CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0) + { + } +} + +void CLOCK_DeinitUsb2Pll(void) +{ + CCM_ANALOG->PLL_USB2 = 0U; +} + +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) +{ + uint32_t pllAudio; + uint32_t misc2 = 0; + + CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator); + CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_AUDIO[POST_DIV_SELECT] | MISC2[AUDIO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllAudio = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 8: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 4: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 2: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + break; + + default: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) + | misc2; + + CCM_ANALOG->PLL_AUDIO = pllAudio; + + while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) + { + } +} + +void CLOCK_DeinitAudioPll(void) +{ + CCM_ANALOG->PLL_AUDIO = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; +} + +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) +{ + uint32_t pllVideo; + uint32_t misc2 = 0; + + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_VIDEO[POST_DIV_SELECT] | MISC2[VIDEO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllVideo = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 8: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 4: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 2: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + break; + + default: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK) | misc2; + + CCM_ANALOG->PLL_VIDEO = pllVideo; + + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } +} + +void CLOCK_DeinitVideoPll(void) +{ + CCM_ANALOG->PLL_VIDEO = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; +} + +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config) +{ + uint32_t enet_pll = CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(config->loopDivider1) | + CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(config->loopDivider0); + + if (config->enableClkOutput0) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK; + } + + if (config->enableClkOutput1) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK; + } + + if (config->enableClkOutput2) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + } + + CCM_ANALOG->PLL_ENET = enet_pll; + + /* Wait for stable */ + while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) + { + } +} + +void CLOCK_DeinitEnetPll(void) +{ + CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; +} + +uint32_t CLOCK_GetPllFreq(clock_pll_t pll) +{ + uint32_t freq; + uint32_t divSelect; + uint64_t freqTmp; + + const uint32_t enetRefClkFreq[] = { + 25000000U, /* 25M */ + 50000000U, /* 50M */ + 100000000U, /* 100M */ + 125000000U /* 125M */ + }; + + switch (pll) + { + case kCLOCK_PllArm: + freq = ((CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); + break; + + case kCLOCK_PllSys: + freq = CLOCK_GetOscFreq(); + + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + + if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) + { + freq *= 22U; + } + else + { + freq *= 20U; + } + + freq += (uint32_t)freqTmp; + break; + + case kCLOCK_PllUsb1: + freq = (CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + break; + + case kCLOCK_PllAudio: + freq = CLOCK_GetOscFreq(); + + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; + + freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); + + freq = freq * divSelect + (uint32_t)freqTmp; + + /* AUDIO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_AUDIO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[AUDO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + default: + break; + } + + switch (CCM_ANALOG->MISC2 & (CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)) + { + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 1U; + break; + + default: + break; + } + break; + + case kCLOCK_PllVideo: + freq = CLOCK_GetOscFreq(); + + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT; + + freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); + + freq = freq * divSelect + (uint32_t)freqTmp; + + /* VIDEO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_VIDEO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[VIDEO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + default: + break; + } + + switch (CCM_ANALOG->MISC2 & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) + { + case CCM_ANALOG_MISC2_VIDEO_DIV(3): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_VIDEO_DIV(1): + freq >>= 1U; + break; + + default: + break; + } + break; + + case kCLOCK_PllEnet0: + divSelect = (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK) + >> CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT; + freq = enetRefClkFreq[divSelect]; + break; + + case kCLOCK_PllEnet1: + divSelect = (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK) + >> CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT; + freq = enetRefClkFreq[divSelect]; + break; + + case kCLOCK_PllEnet2: + /* ref_enetpll2 if fixed at 25MHz. */ + freq = 25000000UL; + break; + + case kCLOCK_PllUsb2: + freq = (CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) ? 22U : 20U)); + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd528; + + pfd528 = CCM_ANALOG->PFD_528 & ~((CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) << (8 * pfdIndex)); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); +} + +void CLOCK_DeinitSysPfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_528 |= CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfd); +} + +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd480; + + pfd480 = CCM_ANALOG->PFD_480 & ~((CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) << (8 * pfdIndex)); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); +} + +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_480 |= CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfd); +} + +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK ; + USB1->USBCMD |= USBHS_USBCMD_RST_MASK; + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + + +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK ; + USB1->USBCMD |= USBHS_USBCMD_RST_MASK; + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + + +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); + USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY1->PWD = 0; + USBPHY1->CTRL |= + USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | + USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | + USBPHY_CTRL_ENUTMILEVEL3_MASK; + return true; +} +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + CLOCK_InitUsb2Pll(&g_ccmConfigUsbPll); + USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY2->PWD = 0; + USBPHY2->CTRL |= + USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | + USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | + USBPHY_CTRL_ENUTMILEVEL3_MASK; + + return true; +} +void CLOCK_DisableUsbhs0PhyPllClock(void) +{ + CLOCK_DeinitUsb1Pll(); + USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ + +} +void CLOCK_DisableUsbhs1PhyPllClock(void) +{ + CLOCK_DeinitUsb2Pll(); + USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_clock.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_clock.h new file mode 100644 index 0000000000..b2916922b6 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_clock.h @@ -0,0 +1,1177 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name ofcopyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_device_registers.h" +#include +#include +#include + +/*! + * @addtogroup clock + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define CCM_TUPLE(reg, shift, mask, busyShift) ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple) & 0xFFU)))) +#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) +#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) +#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU) + +#define CCM_NO_BUSY_WAIT (0x20U) + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.1.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + + +/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency. + * + * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtalFreq to set the value in to clock driver. For example, + * if XTAL is 24MHz, + * @code + * CLOCK_InitExternalClk(false); // Setup the 24M OSC/SYSOSC + * CLOCK_SetXtalFreq(240000000); // Set the XTAL value to clock driver. + * @endcode + */ +extern uint32_t g_xtalFreq; + +/*! @brief External RTC XTAL (32K OSC) clock frequency. + * + * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetRtcXtalFreq to set the value in to clock driver. + */ +extern uint32_t g_rtcXtalFreq; + +/* For compatible with other platforms */ +#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq +#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq + + /*! @brief Clock ip name array for ADC. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Adc1 \ + } + +/*! @brief Clock ip name array for ADC_5HC. */ +#define ADC_5HC_CLOCKS \ + { \ + kCLOCK_Adc_5hc \ + } + +/*! @brief Clock ip name array for ECSPI. */ +#define ECSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Ecspi1, kCLOCK_Ecspi2, \ + kCLOCK_Ecspi3, kCLOCK_Ecspi4 \ + } + +/*! @brief Clock ip name array for ENET. */ +#define ENET_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enet, kCLOCK_Enet \ + } + +/*! @brief Clock ip name array for EPIT. */ +#define EPIT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Epit1, kCLOCK_Epit2 \ + } + +/*! @brief Clock ip name array for ESAI. */ +#define ESAI_CLOCKS \ + { \ + kCLOCK_Esai \ + } + +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \ + } + +/*! @brief Serial Clock ip name array for FLEXCAN. */ +#define FLEXCAN_PERIPH_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \ + } + +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, \ + kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ + } + +/*! @brief Clock ip name array for GPT. */ +#define GPT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \ + } + +/*! @brief Serial Clock ip name array for GPT. */ +#define GPT_PERIPH_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1S, kCLOCK_Gpt2S \ + } + +/*! @brief Clock ip name array for I2C. */ +#define I2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_I2c1S, kCLOCK_I2c2S, \ + kCLOCK_I2c3S, kCLOCK_I2c4S \ + } + +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + kCLOCK_IpInvalid, \ + kCLOCK_Pwm1, kCLOCK_Pwm2, kCLOCK_Pwm3, kCLOCK_Pwm4, \ + kCLOCK_Pwm5, kCLOCK_Pwm6, kCLOCK_Pwm7, kCLOCK_Pwm8, \ + } + +/*! @brief Clock ip name array for QSPI. */ +#define QSPI_CLOCKS \ + { \ + kCLOCK_Qspi1 \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, \ + } + +/*! @brief Clock ip name array for SDMA. */ +#define SDMA_CLOCKS \ + { \ + kCLOCK_Sdma \ + } + +/*! @brief Clock ip name array for TSC. */ +#define TSC_CLOCKS \ + { \ + kCLOCK_Tsc \ + } + +/*! @brief Clock ip name array for UART. */ +#define UART_CLOCKS \ + { \ + kCLOCK_IpInvalid, \ + kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \ + kCLOCK_Uart5, kCLOCK_Uart6, kCLOCK_Uart7, kCLOCK_Uart8 \ + } + +/*! @brief Clock ip name array for USDHC. */ +#define USDHC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ + } + +/*! @brief Clock ip name array for WDOG. */ +#define WDOG_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3 \ + } + +/*! @brief eLCDIF apb_clk. */ +#define LCDIF_CLOCKS \ + { \ + kCLOCK_Lcd \ + } + +/*! @brief eLCDIF pix_clk. */ +#define LCDIF_PERIPH_CLOCKS \ + { \ + kCLOCK_Lcdif1 \ + } + +/*! @brief PXP clock. */ +#define PXP_CLOCKS \ + { \ + kCLOCK_Pxp \ + } + +/*! @brief Clock ip name array for SNVS HP. */ +#define SNVS_HP_CLOCKS \ + { \ + kCLOCK_SnvsHp \ + } + +/*! @brief Clock ip name array for SNVS LP. */ +#define SNVS_LP_CLOCKS \ + { \ + kCLOCK_SnvsLp \ + } + +/*! @brief CSI clock. */ +#define CSI_CLOCKS \ + { \ + kCLOCK_Csi \ + } + +/*! @brief CSI MCLK. */ +#define CSI_MCLK_CLOCKS \ + { \ + kCLOCK_CsiMclk \ + } + +/*! @brief MMDC IPG clock. */ +#define FSL_CLOCK_MMDC_IPG_GATE_COUNT 2U +#define MMDC_CLOCKS \ + { \ + {kCLOCK_MmdcIpgP0, kCLOCK_MmdcIpgP1} \ + } + +/*! @brief MMDC ACLK. */ +#define MMDC_ACLK_CLOCKS \ + { \ + kCLOCK_MmdcAClk \ + } + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CpuClk = 0x0U, /*!< CPU clock */ + kCLOCK_AxiClk = 0x1U, /*!< AXI clock */ + kCLOCK_AhbClk = 0x2U, /*!< AHB clock */ + kCLOCK_IpgClk = 0x3U, /*!< IPG clock */ + kCLOCK_MmdcClk = 0x4U, /*!< MMDC clock */ + + kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */ + kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */ + + kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */ + + kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */ + kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */ + kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */ + kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */ + kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */ + + kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */ + + kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */ + kCLOCK_SysPllPfd0Clk = 0xFU, /*!< SYSPLLPDF0CLK. */ + kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */ + kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */ + kCLOCK_SysPllPfd3Clk = 0x12U, /*!< SYSPLLPFD3CLK. */ + + kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */ + kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */ + kCLOCK_EnetPll2Clk = 0x15U, /*!< Enet PLLCLK ref_enetpll2. */ + + kCLOCK_AudioPllClk = 0x16U, /*!< Audio PLLCLK. */ + kCLOCK_VideoPllClk = 0x17U, /*!< Video PLLCLK. */ +} clock_name_t; + +#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */ +#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */ + +/*! @brief Clock name used to enable/disable gate */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = -1, + /* CCM CCGR0 */ + kCLOCK_AipsTz1 = (0U << 8) | 0x0U, /*!< CCGR0, CG0 */ + kCLOCK_AipsTz2 = (0U << 8) | 0x1U, /*!< CCGR0, CG1 */ + kCLOCK_Apbhdma = (0U << 8) | 0x2U, /*!< CCGR0, CG2 */ + kCLOCK_Asrc = (0U << 8) | 0x3U, /*!< CCGR0, CG3 */ + /*!< CCGR(0U << 8), CG4 reserved */ + kCLOCK_Dcp = (0U << 8) | 0x5U, /*!< CCGR0, CG5 */ + kCLOCK_Enet = (0U << 8) | 0x6U, /*!< CCGR0, CG6 */ + kCLOCK_Can1 = (0U << 8) | 0x7U, /*!< CCGR0, CG7 */ + kCLOCK_Can1S = (0U << 8) | 0x8U, /*!< CCGR0, CG8 , Serial Clock */ + kCLOCK_Can2 = (0U << 8) | 0x9U, /*!< CCGR0, CG9 */ + kCLOCK_Can2S = (0U << 8) | 0xAU, /*!< CCGR0, CG10, Serial Clock */ + kCLOCK_CpuDbg = (0U << 8) | 0xBU, /*!< CCGR0, CG11 */ + kCLOCK_Gpt2 = (0U << 8) | 0xCU, /*!< CCGR0, CG12 */ + kCLOCK_Gpt2S = (0U << 8) | 0xDU, /*!< CCGR0, CG13, Serial Clock */ + kCLOCK_Uart2 = (0U << 8) | 0xEU, /*!< CCGR0, CG14 */ + kCLOCK_Gpio2 = (0U << 8) | 0xFU, /*!< CCGR0, CG15 */ + + /*!< CCM CCGR1 */ + kCLOCK_Ecspi1 = (1U << 8) | 0x0U, /*!< CCGR1, CG0 */ + kCLOCK_Ecspi2 = (1U << 8) | 0x1U, /*!< CCGR1, CG1 */ + kCLOCK_Ecspi3 = (1U << 8) | 0x2U, /*!< CCGR1, CG2 */ + kCLOCK_Ecspi4 = (1U << 8) | 0x3U, /*!< CCGR1, CG3 */ + kCLOCK_Adc_5hc = (1U << 8) | 0x4U, /*!< CCGR1, CG4 */ + kCLOCK_Uart3 = (1U << 8) | 0x5U, /*!< CCGR1, CG5 */ + kCLOCK_Epit1 = (1U << 8) | 0x6U, /*!< CCGR1, CG6 */ + kCLOCK_Epit2 = (1U << 8) | 0x7U, /*!< CCGR1, CG7 */ + kCLOCK_Adc1 = (1U << 8) | 0x8U, /*!< CCGR1, CG8 */ + kCLOCK_SimS = (1U << 8) | 0x9U, /*!< CCGR1, CG9 */ + kCLOCK_Gpt1 = (1U << 8) | 0xAU, /*!< CCGR1, CG10 */ + kCLOCK_Gpt1S = (1U << 8) | 0xBU, /*!< CCGR1, CG11, Serial Clock */ + kCLOCK_Uart4 = (1U << 8) | 0xCU, /*!< CCGR1, CG12 */ + kCLOCK_Gpio1 = (1U << 8) | 0xDU, /*!< CCGR1, CG13 */ + kCLOCK_Csu = (1U << 8) | 0xEU, /*!< CCGR1, CG14 */ + kCLOCK_Gpio5 = (1U << 8) | 0xFU, /*!< CCGR1, CG15 */ + + /*!< CCM CCGR2 */ + kCLOCK_Esai = (2U << 8) | 0x0U, /*!< CCGR2, CG0 */ + kCLOCK_Csi = (2U << 8) | 0x1U, /*!< CCGR2, CG1 */ + kCLOCK_IomuxcSnvs = (2U << 8) | 0x2U, /*!< CCGR2, CG2 */ + kCLOCK_I2c1S = (2U << 8) | 0x3U, /*!< CCGR2, CG3, Serial Clock */ + kCLOCK_I2c2S = (2U << 8) | 0x4U, /*!< CCGR2, CG4, Serial Clock */ + kCLOCK_I2c3S = (2U << 8) | 0x5U, /*!< CCGR2, CG5, Serial Clock */ + kCLOCK_Ocotp = (2U << 8) | 0x6U, /*!< CCGR2, CG6 */ + kCLOCK_IomuxcIpt = (2U << 8) | 0x7U, /*!< CCGR2, CG7 */ + kCLOCK_Ipmux1 = (2U << 8) | 0x8U, /*!< CCGR2, CG8 */ + kCLOCK_Ipmux2 = (2U << 8) | 0x9U, /*!< CCGR2, CG9 */ + kCLOCK_Ipmux3 = (2U << 8) | 0xAU, /*!< CCGR2, CG10 */ + kCLOCK_Ipsync = (2U << 8) | 0xBU, /*!< CCGR2, CG11 */ + /*!< CCGR2, CG12 reserved */ + kCLOCK_Gpio3 = (2U << 8) | 0xDU, /*!< CCGR2, CG13 */ + kCLOCK_Lcd = (2U << 8) | 0xEU, /*!< CCGR2, CG14 */ + kCLOCK_Pxp = (2U << 8) | 0xFU, /*!< CCGR2, CG15 */ + + /*!< CCM CCGR3 */ + kCLOCK_CsiMclk = (3U << 8) | 0x0U, /*!< CCGR3, CG0 */ + kCLOCK_Uart5 = (3U << 8) | 0x1U, /*!< CCGR3, CG1 */ + kCLOCK_Epdc = (3U << 8) | 0x2U, /*!< CCGR3, CG2 */ + kCLOCK_Uart6 = (3U << 8) | 0x3U, /*!< CCGR3, CG3 */ + kCLOCK_Dap = (3U << 8) | 0x4U, /*!< CCGR3, CG4 */ + kCLOCK_Lcdif1 = (3U << 8) | 0x5U, /*!< CCGR3, CG5 */ + kCLOCK_Gpio4 = (3U << 8) | 0x6U, /*!< CCGR3, CG6 */ + kCLOCK_Qspi1 = (3U << 8) | 0x7U, /*!< CCGR3, CG7 */ + kCLOCK_Wdog1 = (3U << 8) | 0x8U, /*!< CCGR3, CG8 */ + kCLOCK_Patch = (3U << 8) | 0x9U, /*!< CCGR3, CG9 */ + kCLOCK_MmdcAClk = (3U << 8) | 0xAU, /*!< CCGR3, CG10 */ + /*!< CCGR3, CG11 reserved */ + kCLOCK_MmdcIpgP0 = (3U << 8) | 0xCU, /*!< CCGR3, CG12 */ + kCLOCK_MmdcIpgP1 = (3U << 8) | 0xDU, /*!< CCGR3, CG13 */ + kCLOCK_Axi = (3U << 8) | 0xEU, /*!< CCGR3, CG14 */ + kCLOCK_IomuxcSnvsGpr = (3U << 8) | 0xFU, /*!< CCGR3, CG15 */ + + /*!< CCM CCGR4 */ + /*!< CCGR4, CG0 reserved */ + kCLOCK_Iomuxc = (4U << 8) | 0x1U, /*!< CCGR4, CG1 */ + kCLOCK_IomuxcGpr = (4U << 8) | 0x2U, /*!< CCGR4, CG2 */ + kCLOCK_SimCpu = (4U << 8) | 0x3U, /*!< CCGR4, CG3 */ + kCLOCK_ApbSlave = (4U << 8) | 0x4U, /*!< CCGR4, CG4 */ + kCLOCK_Tsc = (4U << 8) | 0x5U, /*!< CCGR4, CG5 */ + kCLOCK_SimM = (4U << 8) | 0x6U, /*!< CCGR4, CG6 */ + kCLOCK_Axi2Apb = (4U << 8) | 0x7U, /*!< CCGR4, CG7 */ + kCLOCK_Pwm1 = (4U << 8) | 0x8U, /*!< CCGR4, CG8 */ + kCLOCK_Pwm2 = (4U << 8) | 0x9U, /*!< CCGR4, CG9 */ + kCLOCK_Pwm3 = (4U << 8) | 0xAU, /*!< CCGR4, CG10 */ + kCLOCK_Pwm4 = (4U << 8) | 0xBU, /*!< CCGR4, CG11 */ + kCLOCK_RawNandBchApb = (4U << 8) | 0xCU, /*!< CCGR4, CG12 */ + kCLOCK_RawNandBch = (4U << 8) | 0xDU, /*!< CCGR4, CG13 */ + kCLOCK_RawNandGpmi = (4U << 8) | 0xEU, /*!< CCGR4, CG14 */ + kCLOCK_RawNandGpmiApb = (4U << 8) | 0xFU, /*!< CCGR4, CG15 */ + + /*!< CCM CCGR5 */ + kCLOCK_Rom = (5U << 8) | 0x0U, /*!< CCGR5, CG0 */ + kCLOCK_Stcr = (5U << 8) | 0x1U, /*!< CCGR5, CG1 */ + kCLOCK_SnvsDryice = (5U << 8) | 0x2U, /*!< CCGR5, CG2 */ + kCLOCK_Sdma = (5U << 8) | 0x3U, /*!< CCGR5, CG3 */ + kCLOCK_Kpp = (5U << 8) | 0x4U, /*!< CCGR5, CG4 */ + kCLOCK_Wdog2 = (5U << 8) | 0x5U, /*!< CCGR5, CG5 */ + kCLOCK_Spba = (5U << 8) | 0x6U, /*!< CCGR5, CG6 */ + kCLOCK_Spdif = (5U << 8) | 0x7U, /*!< CCGR5, CG7 */ + kCLOCK_SimMain = (5U << 8) | 0x8U, /*!< CCGR5, CG8 */ + kCLOCK_SnvsHp = (5U << 8) | 0x9U, /*!< CCGR5, CG9 */ + kCLOCK_SnvsLp = (5U << 8) | 0xAU, /*!< CCGR5, CG10 */ + kCLOCK_Sai3 = (5U << 8) | 0xBU, /*!< CCGR5, CG11 */ + kCLOCK_Uart1 = (5U << 8) | 0xCU, /*!< CCGR5, CG12 */ + kCLOCK_Uart7 = (5U << 8) | 0xDU, /*!< CCGR5, CG13 */ + kCLOCK_Sai1 = (5U << 8) | 0xEU, /*!< CCGR5, CG14 */ + kCLOCK_Sai2 = (5U << 8) | 0xFU, /*!< CCGR5, CG15 */ + + /*!< CCM CCGR6 */ + kCLOCK_UsbOh3 = (6U << 8) | 0x0U, /*!< CCGR6, CG0 */ + kCLOCK_Usdhc1 = (6U << 8) | 0x1U, /*!< CCGR6, CG1 */ + kCLOCK_Usdhc2 = (6U << 8) | 0x2U, /*!< CCGR6, CG2 */ + /*!< CCGR6, CG3 reserved */ + kCLOCK_Ipmux4 = (6U << 8) | 0x4U, /*!< CCGR6, CG4 */ + kCLOCK_EimSlow = (6U << 8) | 0x5U, /*!< CCGR6, CG5 */ + /*!< CCGR6, CG6 reserved */ + kCLOCK_Uart8 = (6U << 8) | 0x7U, /*!< CCGR6, CG7 */ + kCLOCK_Pwm8 = (6U << 8) | 0x8U, /*!< CCGR6, CG8 */ + kCLOCK_AipsTz3 = (6U << 8) | 0x9U, /*!< CCGR6, CG9 */ + kCLOCK_Wdog3 = (6U << 8) | 0xAU, /*!< CCGR6, CG10 */ + kCLOCK_Anadig = (6U << 8) | 0xBU, /*!< CCGR6, CG11 */ + kCLOCK_I2c4S = (6U << 8) | 0xCU, /*!< CCGR6, CG12, Serial Clock */ + kCLOCK_Pwm5 = (6U << 8) | 0xDU, /*!< CCGR6, CG13 */ + kCLOCK_Pwm6 = (6U << 8) | 0xEU, /*!< CCGR6, CG14 */ + kCLOCK_Pwm7 = (6U << 8) | 0xFU, /*!< CCGR6, CG15 */ +} clock_ip_name_t; + +/*! @brief OSC 24M sorce select */ +typedef enum _clock_osc +{ + kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ + kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ +} clock_osc_t; + +/*! @brief Clock gate value */ +typedef enum _clock_gate_value +{ + kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */ + kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */ + kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */ +} clock_gate_value_t; + +/*! @brief System clock mode */ +typedef enum _clock_mode_t +{ + kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ + kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ + kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ +} clock_mode_t; + +/*! + * @brief MUX control names for clock mux setting. + * + * These constants define the mux control names for clock mux setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_mux +{ + kCLOCK_StepMux = CCM_TUPLE(CCSR, CCM_CCSR_STEP_SEL_SHIFT, CCM_CCSR_STEP_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< atep clock mux name */ + kCLOCK_SecMux = CCM_TUPLE(CCSR, CCM_CCSR_SECONDARY_CLK_SEL_SHIFT, CCM_CCSR_SECONDARY_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< secondary clock mux name */ + kCLOCK_Pll1SwMux = CCM_TUPLE(CCSR, CCM_CCSR_PLL1_SW_CLK_SEL_SHIFT, CCM_CCSR_PLL1_SW_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< pll1_sw_clk mux name */ + kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR, CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT, CCM_CCSR_PLL3_SW_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< Pll3_sw_clk mux name */ + + kCLOCK_Periph2Mux = CCM_TUPLE(CBCDR, CCM_CBCDR_PERIPH2_CLK_SEL_SHIFT, CCM_CBCDR_PERIPH2_CLK_SEL_MASK, CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT), /*!< periph2 mux name */ + kCLOCK_PeriphMux = CCM_TUPLE(CBCDR, CCM_CBCDR_PERIPH_CLK_SEL_SHIFT, CCM_CBCDR_PERIPH_CLK_SEL_MASK, CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */ + kCLOCK_AxiAltMux = CCM_TUPLE(CBCDR, CCM_CBCDR_AXI_ALT_SEL_SHIFT, CCM_CBCDR_AXI_ALT_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< axi alt mux name */ + kCLOCK_AxiMux = CCM_TUPLE(CBCDR, CCM_CBCDR_AXI_SEL_SHIFT, CCM_CBCDR_AXI_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< axi mux name */ + + kCLOCK_PrePeriph2Mux = CCM_TUPLE(CBCMR, CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT, CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< pre-periph2 mux name */ + kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR, CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT, CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */ + kCLOCK_Periph2Clk2Mux = CCM_TUPLE(CBCMR, CCM_CBCMR_PERIPH2_CLK2_SEL_SHIFT, CCM_CBCMR_PERIPH2_CLK2_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< periph2 clock2 mux name */ + kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR, CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT, CCM_CBCMR_PERIPH_CLK2_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ + + kCLOCK_EimSlowMux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT, CCM_CSCMR1_ACLK_EIM_SLOW_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< aclk eim slow mux name */ + kCLOCK_GpmiMux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_GPMI_CLK_SEL_SHIFT, CCM_CSCMR1_GPMI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< gpmi mux name */ + kCLOCK_BchMux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_BCH_CLK_SEL_SHIFT, CCM_CSCMR1_BCH_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< bch mux name */ + kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT, CCM_CSCMR1_USDHC2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */ + kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT, CCM_CSCMR1_USDHC1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */ + kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, CCM_CSCMR1_SAI3_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 mux name */ + kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, CCM_CSCMR1_SAI2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 mux name */ + kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, CCM_CSCMR1_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 mux name */ + kCLOCK_Qspi1Mux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_QSPI1_CLK_SEL_SHIFT, CCM_CSCMR1_QSPI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< qspi1 mux name */ + kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1, CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT, CCM_CSCMR1_PERCLK_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< perclk mux name */ + + kCLOCK_VidMux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_VID_CLK_SEL_SHIFT, CCM_CSCMR2_VID_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< vid mux name */ + kCLOCK_EsaiMux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_ESAI_CLK_SEL_SHIFT, CCM_CSCMR2_ESAI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< esai mux name */ + kCLOCK_CanMux = CCM_TUPLE(CSCMR2, CCM_CSCMR2_CAN_CLK_SEL_SHIFT, CCM_CSCMR2_CAN_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< can mux name */ + + kCLOCK_UartMux = CCM_TUPLE(CSCDR1, CCM_CSCDR1_UART_CLK_SEL_SHIFT, CCM_CSCDR1_UART_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< uart mux name */ + + kCLOCK_EnfcMux = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ENFC_CLK_SEL_SHIFT, CCM_CS2CDR_ENFC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< enfc mux name */ + kCLOCK_LdbDi0Mux = CCM_TUPLE(CS2CDR, CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT, CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< ldb di0 mux name */ + + kCLOCK_SpdifMux = CCM_TUPLE(CDCDR, CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, CCM_CDCDR_SPDIF0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< spdif mux name */ + + kCLOCK_EpdcPreMux = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_EPDC_PRE_CLK_SEL_SHIFT, CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< epdc pre mux name */ + kCLOCK_EpdcMux = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_EPDC_CLK_SEL_SHIFT, CCM_CHSCCDR_EPDC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< epdc mux name */ + + kCLOCK_EcspiMux = CCM_TUPLE(CSCDR2, CCM_CSCDR2_ECSPI_CLK_SEL_SHIFT, CCM_CSCDR2_ECSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< ecspi mux name */ + kCLOCK_Lcdif1PreMux = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_SHIFT, CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 pre mux name */ + kCLOCK_Lcdif1Mux = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LCDIF1_CLK_SEL_SHIFT, CCM_CSCDR2_LCDIF1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 mux name */ + + kCLOCK_CsiMux = CCM_TUPLE(CSCDR3, CCM_CSCDR3_CSI_CLK_SEL_SHIFT, CCM_CSCDR3_CSI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< csi mux name */ +} clock_mux_t; + +/*! + * @brief DIV control names for clock div setting. + * + * These constants define div control names for clock div setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_div +{ + kCLOCK_ArmDiv = CCM_TUPLE(CACRR, CCM_CACRR_ARM_PODF_SHIFT, CCM_CACRR_ARM_PODF_MASK, CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */ + + kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR, CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT, CCM_CBCDR_PERIPH_CLK2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */ + kCLOCK_Periph2Clk2Div = CCM_TUPLE(CBCDR, CCM_CBCDR_PERIPH2_CLK2_PODF_SHIFT, CCM_CBCDR_PERIPH2_CLK2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< periph2 clock2 div name */ + kCLOCK_AxiDiv = CCM_TUPLE(CBCDR, CCM_CBCDR_AXI_PODF_SHIFT, CCM_CBCDR_AXI_PODF_MASK, CCM_CDHIPR_AXI_PODF_BUSY_SHIFT), /*!< axi div name */ + kCLOCK_AhbDiv = CCM_TUPLE(CBCDR, CCM_CBCDR_AHB_PODF_SHIFT, CCM_CBCDR_AHB_PODF_MASK, CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */ + kCLOCK_IpgDiv = CCM_TUPLE(CBCDR, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */ + kCLOCK_FabricMmdcDiv = CCM_TUPLE(CBCDR, CCM_CBCDR_FABRIC_MMDC_PODF_SHIFT, CCM_CBCDR_FABRIC_MMDC_PODF_MASK, CCM_CDHIPR_MMDC_PODF_BUSY_SHIFT), /*!< mmdc/fabric div name */ + + kCLOCK_Lcdif1Div = CCM_TUPLE(CBCMR, CCM_CBCMR_LCDIF1_PODF_SHIFT, CCM_CBCMR_LCDIF1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 div name */ + + kCLOCK_Qspi1Div = CCM_TUPLE(CSCMR1, CCM_CSCMR1_QSPI1_PODF_SHIFT, CCM_CSCMR1_QSPI1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< qspi1 div name */ + kCLOCK_EimSlowDiv = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT, CCM_CSCMR1_ACLK_EIM_SLOW_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< eim slow div name */ + kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1, CCM_CSCMR1_PERCLK_PODF_SHIFT, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< perclk div name */ + + kCLOCK_VidDiv = CCM_TUPLE(CSCMR2, CCM_CSCMR2_VID_CLK_PODF_SHIFT, CCM_CSCMR2_VID_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< vid div name */ + kCLOCK_VidPreDiv = CCM_TUPLE(CSCMR2, CCM_CSCMR2_VID_CLK_PRE_PODF_SHIFT, CCM_CSCMR2_VID_CLK_PRE_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< vid pre div name */ + kCLOCK_LdbDi0Div = CCM_TUPLE(CSCMR2, CCM_CSCMR2_LDB_DI0_DIV_SHIFT, CCM_CSCMR2_LDB_DI0_DIV_MASK, CCM_NO_BUSY_WAIT), /*!< ldb di0 div name */ + kCLOCK_LdbDi1Div = CCM_TUPLE(CSCMR2, CCM_CSCMR2_LDB_DI1_DIV_SHIFT, CCM_CSCMR2_LDB_DI1_DIV_MASK, CCM_NO_BUSY_WAIT), /*!< ldb di1 div name */ + kCLOCK_CanDiv = CCM_TUPLE(CSCMR2, CCM_CSCMR2_CAN_CLK_PODF_SHIFT, CCM_CSCMR2_CAN_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< can div name */ + + kCLOCK_GpmiDiv = CCM_TUPLE(CSCDR1, CCM_CSCDR1_GPMI_PODF_SHIFT, CCM_CSCDR1_GPMI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< gpmi div name */ + kCLOCK_BchDiv = CCM_TUPLE(CSCDR1, CCM_CSCDR1_BCH_PODF_SHIFT, CCM_CSCDR1_BCH_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< bch div name */ + kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1, CCM_CSCDR1_USDHC2_PODF_SHIFT, CCM_CSCDR1_USDHC2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */ + kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */ + kCLOCK_UartDiv = CCM_TUPLE(CSCDR1, CCM_CSCDR1_UART_CLK_PODF_SHIFT, CCM_CSCDR1_UART_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< uart div name */ + + kCLOCK_EsaiPreDiv = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ESAI_CLK_PRED_SHIFT, CCM_CS1CDR_ESAI_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_EsaiDiv = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ESAI_CLK_PODF_SHIFT, CCM_CS1CDR_ESAI_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< esai div name */ + kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI3_CLK_PRED_SHIFT, CCM_CS1CDR_SAI3_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, CCM_CS1CDR_SAI3_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 div name */ + kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI1_CLK_PRED_SHIFT, CCM_CS1CDR_SAI1_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */ + kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR, CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, CCM_CS1CDR_SAI1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 div name */ + + kCLOCK_EnfcPreDiv = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ENFC_CLK_PRED_SHIFT, CCM_CS2CDR_ENFC_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< enfc pre div name */ + kCLOCK_EnfcDiv = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ENFC_CLK_PODF_SHIFT, CCM_CS2CDR_ENFC_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< enfc div name */ + kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR, CCM_CS2CDR_SAI2_CLK_PRED_SHIFT, CCM_CS2CDR_SAI2_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */ + kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR, CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, CCM_CS2CDR_SAI2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 div name */ + + kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR, CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT, CCM_CDCDR_SPDIF0_CLK_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< spdif pre div name */ + kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR, CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT, CCM_CDCDR_SPDIF0_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< spdif div name */ + + kCLOCK_EpdcDiv = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_EPDC_PODF_SHIFT, CCM_CHSCCDR_EPDC_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< epdc div name */ + + kCLOCK_EcspiDiv = CCM_TUPLE(CSCDR2, CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT, CCM_CSCDR2_ECSPI_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ecspi div name */ + kCLOCK_Lcdif1PreDiv = CCM_TUPLE(CSCDR2, CCM_CSCDR2_LCDIF1_PRED_SHIFT, CCM_CSCDR2_LCDIF1_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif1 pre div name */ + + kCLOCK_CsiDiv = CCM_TUPLE(CSCDR3, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */ +} clock_div_t; + +/*! @brief PLL configuration for ARM */ +typedef struct _clock_arm_pll_config +{ + uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */ +} clock_arm_pll_config_t; + +/*! @brief PLL configuration for USB */ +typedef struct _clock_usb_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ +} clock_usb_pll_config_t; + + +/*! @brief PLL configuration for System */ +typedef struct _clock_sys_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ +} clock_sys_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_audio_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ +} clock_audio_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_video_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ +} clock_video_pll_config_t; + +/*! @brief PLL configuration for ENET */ +typedef struct _clock_enet_pll_config +{ + bool enableClkOutput0; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ + bool enableClkOutput1; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ + bool enableClkOutput2; /*!< Power on and enable PLL clock output for ENET2 (ref_enetpll2). */ + uint8_t loopDivider0; /*!< Controls the frequency of the ENET0 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ + uint8_t loopDivider1; /*!< Controls the frequency of the ENET1 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ +} clock_enet_pll_config_t; + +/*! @brief PLL name */ +typedef enum _clock_pll +{ + kCLOCK_PllArm = 0U, /*!< PLL ARM */ + kCLOCK_PllSys = 1U, /*!< PLL SYS */ + kCLOCK_PllUsb1 = 2U, /*!< PLL USB1 */ + kCLOCK_PllAudio = 3U, /*!< PLL Audio */ + kCLOCK_PllVideo = 4U, /*!< PLL Video */ + kCLOCK_PllEnet0 = 5U, /*!< PLL Enet0 */ + kCLOCK_PllEnet1 = 6U, /*!< PLL Enet1 */ + kCLOCK_PllEnet2 = 7U, /*!< PLL Enet2 */ + kCLOCK_PllUsb2 = 8U, /*!< PLL USB2 */ +} clock_pll_t; + +/*! @brief PLL PFD name */ +typedef enum _clock_pfd +{ + kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ + kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ + kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ + kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ +} clock_pfd_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_Usb480M = 0, /*!< Use 480M. */ + kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not + care the clock source. */ +} clock_usb_src_t; + +/*! @brief Source of the USB HS PHY. */ +typedef enum _clock_usb_phy_src +{ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ +} clock_usb_phy_src_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set CCM MUX node to certain value. + * + * @param mux Which mux node to set, see \ref clock_mux_t. + * @param value Clock mux value to set, different mux has different value range. + */ +static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(mux); + CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Get CCM MUX value. + * + * @param mux Which mux node to get, see \ref clock_mux_t. + * @return Clock mux value. + */ +static inline uint32_t CLOCK_GetMux(clock_mux_t mux) +{ + return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux); +} + +/*! + * @brief Set CCM DIV node to certain value. + * + * @param divider Which div node to set, see \ref clock_div_t. + * @param value Clock div value to set, different divider has different value range. + */ +static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(divider); + CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Get CCM DIV node value. + * + * @param divider Which div node to get, see \ref clock_div_t. + */ +static inline uint32_t CLOCK_GetDiv(clock_div_t divider) +{ + uint32_t value; + + value = (CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider); + return value; +} + +/*! + * @brief Control the clock gate for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + * @param value Clock gate value to set, see \ref clock_gate_value_t. + */ +static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value) +{ + uint32_t index = ((uint32_t)name) >> 8; + uint32_t shift = (((uint32_t)name) & 0xF) << 1; + volatile uint32_t *reg; + + assert (index <= 6); + + reg = ((volatile uint32_t *)&CCM->CCGR0) + index; + *reg = ((*reg) & ~(3U << shift)) | (((uint32_t)value) << shift); +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded); +} + +/*! + * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal. + * + * @param mode Which mode to enter, see \ref clock_mode_t. + */ +static inline void CLOCK_SetMode(clock_mode_t mode) +{ + CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode); +} + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name); + +/*! + * @name OSC operations + * @{ + */ + +/*! + * @brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call @ref CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * @note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ +void CLOCK_InitExternalClk(bool bypassXtalOsc); + +/*! + * @brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call @ref CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ +void CLOCK_DeinitExternalClk(void); + +/*! + * @brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * @param osc OSC source to switch to. + */ +void CLOCK_SwitchOsc(clock_osc_t osc); + +/*! + * @brief Gets the OSC clock frequency. + * + * This function will return the external XTAL OSC frequency if it is selected as the source of OSC, + * otherwise internal 24MHz RC OSC frequency will be returned. + * + * @param osc OSC type to get frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetOscFreq(void) +{ + return (PMU->LOWPWR_CTRL & PMU_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq; +} + +/*! + * @brief Gets the RTC clock frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetRtcFreq(void) +{ + return 32768U; +} + +/*! + * @brief Set the XTAL (24M OSC) frequency based on board setting. + * + * @param freq The XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetXtalFreq(uint32_t freq) +{ + g_xtalFreq = freq; +} + +/*! + * @brief Set the RTC XTAL (32K OSC) frequency based on board setting. + * + * @param freq The RTC XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetRtcXtalFreq(uint32_t freq) +{ + g_rtcXtalFreq = freq; +} + + +/*! + * @brief Initialize the RC oscillator 24MHz clock. + */ +void CLOCK_InitRcOsc24M(void); + +/*! + * @brief Power down the RCOSC 24M clock. + */ +void CLOCK_DeinitRcOsc24M(void); +/* @} */ + +/*! + * @name PLL/PFD operations + * @{ + */ + +/*! + * @brief Initialize the ARM PLL. + * + * This function initialize the ARM PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config); + +/*! + * @brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void); + +/*! + * @brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config); + +/*! + * @brief De-initialize the System PLL. + */ +void CLOCK_DeinitSysPll(void); + +/*! + * @brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB1 PLL. + */ +void CLOCK_DeinitUsb1Pll(void); + +/*! + * @brief Initialize the USB2 PLL. + * + * This function initializes the USB2 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB2 PLL. + */ +void CLOCK_DeinitUsb2Pll(void); + +/*! + * @brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config); + +/*! + * @brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void); + +/*! + * @brief Initialize the video PLL. + * + * This function configures the Video PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config); + +/*! + * @brief De-initialize the Video PLL. + */ +void CLOCK_DeinitVideoPll(void); + +/*! + * @brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config); + +/*! + * @brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ +void CLOCK_DeinitEnetPll(void); + +/*! + * @brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * @param pll pll name to get frequency. + * @return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll); + +/*! + * @brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitSysPfd(clock_pfd_t pfd); + +/*! + * @brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd); + +/*! + * @brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd); + +/*! + * @brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd); + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); + + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void); + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); + + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_common.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_common.c new file mode 100644 index 0000000000..90862b0ef7 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_common.c @@ -0,0 +1,207 @@ +/* +* Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_common.h" +#include +#define PRINTF rt_kprintf + +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned adress to real address */ +} mem_align_cb_t; + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); + for (;;) + { + __BKPT(0); + } +} +#elif(defined(__GNUC__)) +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); + for (;;) + { + __BKPT(0); + } +} +#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */ +#endif /* NDEBUG */ + +#ifndef __GIC_PRIO_BITS +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + + return ret; +} +#endif + +#ifndef CPU_QN908X +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t index = 0; + uint32_t intNumber = (uint32_t)interrupt; + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1u << intNumber; + EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t index = 0; + uint32_t intNumber = (uint32_t)interrupt; + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + SYSCON->STARTERCLR[index] = 1u << intNumber; +} +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ +#else +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t index = 0; + uint32_t intNumber = (uint32_t)interrupt; + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + /* SYSCON->STARTERSET[index] = 1u << intNumber; */ + EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t index = 0; + uint32_t intNumber = (uint32_t)interrupt; + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + /* SYSCON->STARTERCLR[index] = 1u << intNumber; */ +} +#endif /*CPU_QN908X */ + +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); + void *p_align_addr, *p_addr = malloc(alignedsize); + + if (!p_addr) + { + return NULL; + } + + p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; + + return (void *)p_align_addr; +} + +void SDK_Free(void *ptr) +{ + mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + free((void *)((uint32_t)ptr - p_cb->offset)); +} + + diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_common.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_common.h new file mode 100644 index 0000000000..8245d7750e --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_common.h @@ -0,0 +1,487 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http://supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__CC_ARM) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) +#endif +#else +#error Toolchain not supported +#define SDK_ALIGN(var, alignbytes) var +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var +#endif +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var +#endif +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) +/* @} */ + +/*! Function to allocate/free L1 cache aligned memory using the malloc/free. */ +void *SDK_Malloc(size_t size, size_t alignbytes); + +void SDK_Free(void *ptr); + +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#endif +#elif(defined(__CC_ARM)) +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var +#endif +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes))) +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#endif +#else +#error Toolchain not supported. +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var +#endif +/* @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif + + /*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ + static inline status_t EnableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + extern void rt_hw_interrupt_umask(int vector); + rt_hw_interrupt_umask(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ + static inline status_t DisableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + extern void rt_hw_interrupt_mask(int vector); + rt_hw_interrupt_mask(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ + static inline uint32_t DisableGlobalIRQ(void) + { +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif + } + + /*! + * @brief Enaable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ + static inline void EnableGlobalIRQ(uint32_t primask) + { +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif + } + + /*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ + uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + /*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). + * + * @param interrupt The IRQ number. + */ + void EnableDeepSleepIRQ(IRQn_Type interrupt); + + /*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). + * + * @param interrupt The IRQ number. + */ + void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.c new file mode 100644 index 0000000000..d16a40a06c --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.c @@ -0,0 +1,778 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_ecspi.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ +/*! @brief ECSPI transfer state, which is used for ECSPI transactiaonl APIs' internal state. */ +enum _ecspi_transfer_states_t +{ + kECSPI_Idle = 0x0, /*!< ECSPI is idle state */ + kECSPI_Busy /*!< ECSPI is busy tranferring data. */ +}; + +/*! @brief Typedef for ecspi master interrupt handler. ecspi master and slave handle is the same. */ +typedef void (*ecspi_isr_t)(ECSPI_Type *base, ecspi_master_handle_t *ecspiHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance for ECSPI module. + * + * @param base ECSPI base address + */ +uint32_t ECSPI_GetInstance(ECSPI_Type *base); + +/*! + * @brief Sends a buffer of data bytes in non-blocking way. + * + * @param base ECSPI base pointer + * @param buffer The data bytes to send + * @param size The number of data bytes to send + */ +static void ECSPI_WriteNonBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Receive a buffer of data bytes in non-blocking way. + * + * @param base ECSPI base pointer + * @param buffer The data bytes to send + * @param size The number of data bytes to send + */ +static void ECSPI_ReadNonBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Send a piece of data for ECSPI. + * + * This function computes the number of data to be written into D register or Tx FIFO, + * and write the data into it. At the same time, this function updates the values in + * master handle structure. + * + * @param base ECSPI base pointer + * @param handle Pointer to ECSPI master handle structure. + */ +static void ECSPI_SendTransfer(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/*! + * @brief Receive a piece of data for ECSPI master. + * + * This function computes the number of data to receive from D register or Rx FIFO, + * and write the data to destination address. At the same time, this function updates + * the values in master handle structure. + * + * @param base ECSPI base pointer + * @param handle Pointer to ECSPI master handle structure. + */ +static void ECSPI_ReceiveTransfer(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/*! +* @brief Sets the ECSPI channel configuration structure to default values. +* +* This function is to get the channel configuration structure initialized for use in ECSPI_SetChannelConfig(). +* User may use the initialized structure unchanged in ECSPI_SetChannelConfig(), or modify +* some fields of the structure before calling ECSPI_SetChannelConfig(). +* +* @param config pointer to config structure +*/ +static void ECSPI_GetDefaultChannelConfig(ecspi_channel_config_t *config); + +/*! + * @brief Common IRQ handler for SPI. + * + * @param base SPI base pointer. + * @param instance SPI instance number. + */ +static void ECSPI_CommonIRQHandler(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Base pointer array */ +static ECSPI_Type *const s_ecspiBases[] = ECSPI_BASE_PTRS; +/*! @brief ECSPI internal handle pointer array */ +static ecspi_master_handle_t *s_ecspiHandle[ARRAY_SIZE(s_ecspiBases)]; +/*! @brief IRQ name array */ +static const IRQn_Type s_ecspiIRQ[] = ECSPI_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Clock array name */ +static const clock_ip_name_t s_ecspiClock[] = ECSPI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointer to master IRQ handler for each instance. */ +static ecspi_isr_t s_ecspiMasterIsr; +/*! @brief Pointer to slave IRQ handler for each instance. */ +static ecspi_isr_t s_ecspiSlaveIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t ECSPI_GetInstance(ECSPI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_ecspiBases); instance++) + { + if (s_ecspiBases[instance] == base) + { + break; + } + } + assert(instance <= ARRAY_SIZE(s_ecspiBases)); + return instance; +} + +static void ECSPI_WriteNonBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size) +{ + size_t i = 0U; + + for (i = 0U; i < size; i++) + { + if (buffer != NULL) + { + base->TXDATA = *buffer++; + } + else + { + ECSPI_WriteData(base, ECSPI_DUMMYDATA); + } + } +} + +static void ECSPI_ReadNonBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size) +{ + if (NULL != buffer) + { + while (size--) + { + *buffer++ = ECSPI_ReadData(base); + } + } + else + { + while (size--) + { + (void)ECSPI_ReadData(base); + } + } +} + +static void ECSPI_SendTransfer(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + assert(base); + assert(handle); + + uint32_t dataCounts = 0U; + /* Caculate the data size to send */ + dataCounts = (FSL_FEATURE_ECSPI_TX_FIFO_SIZEn(base) - ECSPI_GetTxFifoCount(base)) < (handle->txRemainingBytes) ? + (FSL_FEATURE_ECSPI_TX_FIFO_SIZEn(base) - ECSPI_GetTxFifoCount(base)) : + (handle->txRemainingBytes); + while (dataCounts--) + { + ECSPI_WriteNonBlocking(base, handle->txData, 1); + if (NULL != handle->txData) + { + handle->txData += 1U; + } + handle->txRemainingBytes -= 1U; + } +} + +static void ECSPI_ReceiveTransfer(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + assert(base); + + uint32_t dataCounts = 0U; + /* Caculate the data size need to receive */ + dataCounts = + (ECSPI_GetRxFifoCount(base) < handle->rxRemainingBytes) ? ECSPI_GetRxFifoCount(base) : handle->rxRemainingBytes; + + ECSPI_ReadNonBlocking(base, handle->rxData, dataCounts); + if (NULL != handle->rxData) + { + handle->rxData += dataCounts; + } + handle->rxRemainingBytes -= dataCounts; +} +static void ECSPI_GetDefaultChannelConfig(ecspi_channel_config_t *config) +{ + config->channelMode = kECSPI_Slave; /*!< ECSPI peripheral operates in slave mode.*/ + config->clockInactiveState = kECSPI_ClockInactiveStateLow; /*!< Clock line (SCLK) inactive state */ + config->dataLineInactiveState = kECSPI_DataLineInactiveStateLow; /*!< Data line (MOSI&MISO) inactive state */ + config->chipSlectActiveState = kECSPI_ChipSelectActiveStateLow; /*!< Chip select(SS) line active state */ + config->waveForm = kECSPI_WaveFormSingle; /*!< ECSPI SS wave form */ + config->polarity = kECSPI_PolarityActiveHigh; /*!< Clock polarity */ + config->phase = kECSPI_ClockPhaseFirstEdge; /*!< clock phase */ +} + +void ECSPI_MasterGetDefaultConfig(ecspi_master_config_t *config) +{ + config->channel = kECSPI_Channel0; + config->burstLength = 8; + config->samplePeriodClock = kECSPI_spiClock; + config->baudRate_Bps = 500000; + config->chipSelectDelay = 0; + config->samplePeriod = 0; + config->txFifoThreshold = 1; + config->rxFifoThreshold = 0; + /* Default configuration of channel */ + ECSPI_GetDefaultChannelConfig(&config->channelConfig); + /*!< ECSPI peripheral operates in slave mode.*/ + config->channelConfig.channelMode = kECSPI_Master; +} + +void ECSPI_MasterInit(ECSPI_Type *base, const ecspi_master_config_t *config, uint32_t srcClock_Hz) +{ + assert(config && srcClock_Hz); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Open clock gate for SPI and open interrupt */ + CLOCK_EnableClock(s_ecspiClock[ECSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* Reset control register to default value */ + ECSPI_SoftwareReset(base); + /* Config CONREG register */ + base->CONREG = ECSPI_CONREG_BURST_LENGTH(config->burstLength - 1) | ECSPI_CONREG_SMC(1) | ECSPI_CONREG_EN(1); + /* Config CONFIGREG register */ + ECSPI_SetChannelConfig(base, config->channel, &config->channelConfig); + /* Config DMAREG register */ + base->DMAREG |= + ECSPI_DMAREG_TX_THRESHOLD(config->txFifoThreshold) | ECSPI_DMAREG_RX_THRESHOLD(config->rxFifoThreshold); + /* Config PERIODREG register */ + base->PERIODREG |= ECSPI_PERIODREG_CSRC(config->samplePeriodClock) | + ECSPI_PERIODREG_SAMPLE_PERIOD(config->samplePeriod) | + ECSPI_PERIODREG_CSD_CTL(config->chipSelectDelay); + /* Set baud rate */ + ECSPI_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); +} + +void ECSPI_SlaveGetDefaultConfig(ecspi_slave_config_t *config) +{ + /* Default configuration of channel nember */ + config->channel = kECSPI_Channel0; + config->burstLength = 8; + config->txFifoThreshold = 1; + config->rxFifoThreshold = 0; + /* Set default channel configuration */ + ECSPI_GetDefaultChannelConfig(&config->channelConfig); + /* ECSPI peripheral operates in slave mode.*/ + config->channelConfig.channelMode = kECSPI_Slave; +} + +void ECSPI_SlaveInit(ECSPI_Type *base, const ecspi_slave_config_t *config) +{ + assert(base && config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Open clock gate for SPI and open interrupt */ + CLOCK_EnableClock(s_ecspiClock[ECSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset control register to default value */ + ECSPI_SoftwareReset(base); + /* Config CONREG register */ + base->CONREG = ECSPI_CONREG_BURST_LENGTH(config->burstLength - 1) | ECSPI_CONREG_EN(1); + /* Config DMAREG register */ + base->DMAREG |= + ECSPI_DMAREG_TX_THRESHOLD(config->txFifoThreshold) | ECSPI_DMAREG_RX_THRESHOLD(config->rxFifoThreshold); + /* Setup channel configuration */ + ECSPI_SetChannelConfig(base, config->channel, &config->channelConfig); +} + +void ECSPI_Deinit(ECSPI_Type *base) +{ + /* Disable ECSPI module before shutting down */ + base->CONREG &= ~ECSPI_CONREG_EN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the clock */ + CLOCK_DisableClock(s_ecspiClock[ECSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void ECSPI_SetBaudRate(ECSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + assert(base); + + uint8_t bestPreDividerValue = 0U, preDividerValue = 0U; + uint8_t bestPostDividerValue = 0U, postDividerValue = 0U; + uint32_t realBaudrate = 0U; + uint32_t diff = 0xFFFFFFFFU; + uint32_t min_diff = 0xFFFFFFFFU; + + for (preDividerValue = 0; (preDividerValue < 16) && diff; preDividerValue++) + { + for (postDividerValue = 0; (postDividerValue < 16) && diff; postDividerValue++) + { + realBaudrate = (srcClock_Hz / (preDividerValue + 1)) >> postDividerValue; + if (realBaudrate > baudRate_Bps) + { + diff = realBaudrate - baudRate_Bps; + if (diff < min_diff) + { + min_diff = diff; + bestPreDividerValue = preDividerValue; + bestPostDividerValue = postDividerValue; + } + } + else + { + diff = baudRate_Bps - realBaudrate; + if (diff < min_diff) + { + min_diff = diff; + bestPreDividerValue = preDividerValue; + bestPostDividerValue = postDividerValue; + } + } + } + } + + base->CONREG |= ECSPI_CONREG_PRE_DIVIDER(bestPreDividerValue) | ECSPI_CONREG_POST_DIVIDER(bestPostDividerValue); +} + +void ECSPI_SetChannelConfig(ECSPI_Type *base, ecspi_channel_source_t channel, const ecspi_channel_config_t *config) +{ + switch (channel) + { + case kECSPI_Channel0: + base->CONREG |= ECSPI_CONREG_CHANNEL_MODE(config->channelMode); + base->CONFIGREG |= + (ECSPI_CONFIGREG_SCLK_CTL(config->clockInactiveState) | + ECSPI_CONFIGREG_DATA_CTL(config->dataLineInactiveState) | + ECSPI_CONFIGREG_SS_POL(config->chipSlectActiveState) | ECSPI_CONFIGREG_SS_CTL(config->waveForm) | + ECSPI_CONFIGREG_SCLK_POL(config->polarity) | ECSPI_CONFIGREG_SCLK_PHA(config->phase)); + break; + + case kECSPI_Channel1: + base->CONREG |= ECSPI_CONREG_CHANNEL_MODE(config->channelMode) << 1; + base->CONFIGREG |= + ((ECSPI_CONFIGREG_SCLK_CTL(config->clockInactiveState) << 1) | + (ECSPI_CONFIGREG_DATA_CTL(config->dataLineInactiveState) << 1) | + (ECSPI_CONFIGREG_SS_POL(config->chipSlectActiveState) << 1) | + (ECSPI_CONFIGREG_SS_CTL(config->waveForm) << 1) | (ECSPI_CONFIGREG_SCLK_POL(config->polarity) << 1) | + (ECSPI_CONFIGREG_SCLK_PHA(config->phase) << 1)); + break; + + case kECSPI_Channel2: + base->CONREG |= ECSPI_CONREG_CHANNEL_MODE(config->channelMode) << 2; + base->CONFIGREG |= + ((ECSPI_CONFIGREG_SCLK_CTL(config->clockInactiveState) << 2) | + (ECSPI_CONFIGREG_DATA_CTL(config->dataLineInactiveState) << 2) | + (ECSPI_CONFIGREG_SS_POL(config->chipSlectActiveState) << 2) | + (ECSPI_CONFIGREG_SS_CTL(config->waveForm) << 2) | (ECSPI_CONFIGREG_SCLK_POL(config->polarity) << 2) | + (ECSPI_CONFIGREG_SCLK_PHA(config->phase) << 2)); + break; + + case kECSPI_Channel3: + base->CONREG |= ECSPI_CONREG_CHANNEL_MODE(config->channelMode) << 3; + base->CONFIGREG |= + ((ECSPI_CONFIGREG_SCLK_CTL(config->clockInactiveState) << 3) | + (ECSPI_CONFIGREG_DATA_CTL(config->dataLineInactiveState) << 3) | + (ECSPI_CONFIGREG_SS_POL(config->chipSlectActiveState) << 3) | + (ECSPI_CONFIGREG_SS_CTL(config->waveForm) << 3) | (ECSPI_CONFIGREG_SCLK_POL(config->polarity) << 3) | + (ECSPI_CONFIGREG_SCLK_PHA(config->phase) << 3)); + break; + + default: + break; + } +} + +void ECSPI_WriteBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size) +{ + size_t i = 0U; + + while (i < size) + { + /* Wait for TX fifo buffer empty */ + while (!(base->STATREG & ECSPI_STATREG_TE_MASK)) + { + } + /* Write data to tx register */ + if (NULL != buffer) + { + ECSPI_WriteData(base, *buffer++); + } + else + { + ECSPI_WriteData(base, ECSPI_DUMMYDATA); + } + i++; + } +} + +static status_t ECSPI_ReadBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size) +{ + assert(base); + + uint32_t state = 0U; + size_t i = 0U; + + while (i < size) + { + /* Wait for RX FIFO buffer ready */ + while (!(base->STATREG & ECSPI_STATREG_RR_MASK)) + { + /* Get status flags of ECSPI */ + state = ECSPI_GetStatusFlags(base); + /* If hardware overflow happen */ + if (ECSPI_STATREG_RO_MASK & state) + { + /* Clear overflow flag for next transfer */ + ECSPI_ClearStatusFlags(base, kECSPI_RxFifoOverFlowFlag); + return kStatus_ECSPI_HardwareOverFlow; + } + } + /* Read data from rx register */ + if (NULL != buffer) + { + *buffer++ = ECSPI_ReadData(base); + } + else + { + (void)ECSPI_ReadData(base); + } + i++; + } + return kStatus_Success; +} + +void ECSPI_MasterTransferCreateHandle(ECSPI_Type *base, + ecspi_master_handle_t *handle, + ecspi_master_callback_t callback, + void *userData) +{ + assert(base); + assert(handle); + + uint8_t instance = ECSPI_GetInstance(base); + + /* Initialize the handle */ + s_ecspiHandle[instance] = handle; + handle->callback = callback; + handle->userData = userData; + s_ecspiMasterIsr = ECSPI_MasterTransferHandleIRQ; + + /* Enable ECSPI NVIC */ + EnableIRQ(s_ecspiIRQ[instance]); +} + +status_t ECSPI_MasterTransferBlocking(ECSPI_Type *base, ecspi_transfer_t *xfer) +{ + assert(base && xfer); + + status_t state; + uint32_t burstLength = 0U; + uint32_t dataCounts = 0U; + /* Check if the argument is legal */ + if ((xfer->txData == NULL) && (xfer->rxData == NULL)) + { + return kStatus_InvalidArgument; + } + /* Select ECSPI channel to current channel + * Note: + * xfer.channel must be configured before transfer, because every channel has + * it's own configuration,if don't configure this parameter, transfer channel + * will use the default channel0. + */ + ECSPI_SetChannelSelect(base, xfer->channel); + /* Caculate the data size need to be send for one burst */ + burstLength = ((base->CONREG & ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT) + 1; + dataCounts = (burstLength % 32) ? (burstLength / 32 + 1) : (burstLength / 32); + + while (xfer->dataSize > 0) + { + /* ECSPI will transmit and receive at the same time, if txData is NULL, + * instance will transmit dummy data, the dummy data can be set by user. + * if rxData is NULL, data will be read from RX FIFO buffer, but the + * data will be ignored by driver. + * Note that, txData and rxData can not be both NULL. + */ + ECSPI_WriteBlocking(base, xfer->txData, dataCounts); + if (NULL != xfer->txData) + { + xfer->txData += dataCounts; + } + state = ECSPI_ReadBlocking(base, xfer->rxData, dataCounts); + if ((kStatus_Success == state) && (NULL != xfer->rxData)) + { + xfer->rxData += dataCounts; + } + if (kStatus_ECSPI_HardwareOverFlow == state) + { + return kStatus_ECSPI_HardwareOverFlow; + } + + xfer->dataSize -= dataCounts; + } + + return kStatus_Success; +} + +status_t ECSPI_MasterTransferNonBlocking(ECSPI_Type *base, ecspi_master_handle_t *handle, ecspi_transfer_t *xfer) +{ + assert(base && handle && xfer); + + /* Check if ECSPI is busy */ + if (handle->state == kECSPI_Busy) + { + return kStatus_ECSPI_Busy; + } + + /* Check if the input arguments valid */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* Set the handle information */ + handle->channel = xfer->channel; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + handle->transferSize = xfer->dataSize; + handle->txRemainingBytes = xfer->dataSize; + handle->rxRemainingBytes = xfer->dataSize; + + /* Set the ECSPI state to busy */ + handle->state = kECSPI_Busy; + + /* Select ECSPI channel to current channel + * Note: + * xfer.channel must be configured before transferfer, because every channel has + * it's own configuration, if don't configure this parameter, transfer channel + * will use the default channel0. + */ + ECSPI_SetChannelSelect(base, xfer->channel); + + /* First send data to Tx FIFO to start a ECSPI transfer */ + ECSPI_SendTransfer(base, handle); + + if (NULL != xfer->rxData) + { + /* Enable Rx data request interrupt and receive overflow interrupt, when data in RX FIFO buffer is greater + * than the RX_THRESHOLD, then a interrupt occurred. Only enable Rx interrupt, + * use rx interrupt to driver ECSPI transfer. + */ + ECSPI_EnableInterrupts(base, kECSPI_RxFifoReadyInterruptEnable | kECSPI_RxFifoOverFlowInterruptEnable); + } + else + { + /* Enable Tx data request interrupt, when data in TX FIFO buffer is greater + * than the TX_THRESHOLD, then a interrupt occurred. + */ + ECSPI_EnableInterrupts(base, kECSPI_TxFifoDataRequstInterruptEnable); + } + + return kStatus_Success; +} + +status_t ECSPI_MasterTransferGetCount(ECSPI_Type *base, ecspi_master_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kStatus_ECSPI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + /* Return remaing bytes in different cases */ + if (handle->rxData) + { + *count = handle->transferSize - handle->rxRemainingBytes; + } + else + { + *count = handle->transferSize - handle->txRemainingBytes; + } + } + + return status; +} + +void ECSPI_MasterTransferAbort(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + assert(handle); + + /* Stop interrupts */ + if (NULL != handle->rxData) + { + ECSPI_DisableInterrupts(base, kECSPI_RxFifoReadyInterruptEnable | kECSPI_RxFifoOverFlowInterruptEnable); + } + else + { + ECSPI_DisableInterrupts(base, kECSPI_TxFifoDataRequstInterruptEnable); + } + /* Transfer finished, set the state to Done*/ + handle->state = kECSPI_Idle; + + /* Clear the internal state */ + handle->rxRemainingBytes = 0; + handle->txRemainingBytes = 0; +} + +void ECSPI_MasterTransferHandleIRQ(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + assert(handle); + + /* If hardware overflow happens */ + if (base->STATREG & ECSPI_STATREG_RO_MASK) + { + /* Clear overflow flag for next transfer */ + ECSPI_ClearStatusFlags(base, kECSPI_RxFifoOverFlowFlag); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_ECSPI_HardwareOverFlow, handle->userData); + } + } + /* If need to receive data, do a receive */ + if (handle->rxRemainingBytes) + { + ECSPI_ReceiveTransfer(base, handle); + } + + /* We always need to send a data to make the ECSPI run */ + if (handle->txRemainingBytes) + { + ECSPI_SendTransfer(base, handle); + } + + /* All the transfer finished */ + if ((handle->txRemainingBytes == 0) && (handle->rxRemainingBytes == 0)) + { + /* Complete the transfer */ + ECSPI_MasterTransferAbort(base, handle); + + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_Success, handle->userData); + } + } +} + +void ECSPI_SlaveTransferCreateHandle(ECSPI_Type *base, + ecspi_slave_handle_t *handle, + ecspi_slave_callback_t callback, + void *userData) +{ + assert(handle); + + /* Slave create handle share same logic with master create handle, the only difference + is the Isr pointer. */ + ECSPI_MasterTransferCreateHandle(base, handle, callback, userData); + s_ecspiSlaveIsr = ECSPI_SlaveTransferHandleIRQ; +} + +void ECSPI_SlaveTransferHandleIRQ(ECSPI_Type *base, ecspi_slave_handle_t *handle) +{ + assert(handle); + /* If hardware overflow happens */ + if (base->STATREG & ECSPI_STATREG_RO_MASK) + { + /* Clear overflow flag for next transfer */ + ECSPI_ClearStatusFlags(base, kECSPI_RxFifoOverFlowFlag); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_ECSPI_HardwareOverFlow, handle->userData); + } + } + /* If needs to receive data, do a receive */ + if (handle->rxRemainingBytes) + { + ECSPI_ReceiveTransfer(base, handle); + } + + /* We always need to send a data to make the ECSPI run */ + if (handle->txRemainingBytes) + { + ECSPI_SendTransfer(base, handle); + } + + /* All the transfer finished */ + if ((handle->txRemainingBytes == 0) && (handle->rxRemainingBytes == 0)) + { + /* Complete the transfer */ + ECSPI_SlaveTransferAbort(base, handle); + + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_Success, handle->userData); + } + } +} + +static void ECSPI_CommonIRQHandler(ECSPI_Type *base, ecspi_master_handle_t *handle) +{ + if (ECSPI_IsMaster(base, handle->channel)) + { + s_ecspiMasterIsr(base, handle); + } + else + { + s_ecspiSlaveIsr(base, handle); + } +} + +#if defined(ECSPI1) +void ECSPI1_DriverIRQHandler(void) +{ + assert(s_ecspiHandle[1]); + ECSPI_CommonIRQHandler(ECSPI1, s_ecspiHandle[1]); +} +#endif /* ECSPI1 */ + +#if defined(ECSPI2) +void ECSPI2_DriverIRQHandler(void) +{ + assert(s_ecspiHandle[2]); + ECSPI_CommonIRQHandler(ECSPI2, s_ecspiHandle[2]); +} +#endif /* ECSPI2 */ + +#if defined(ECSPI3) +void ECSPI3_DriverIRQHandler(void) +{ + assert(s_ecspiHandle[3]); + ECSPI_CommonIRQHandler(ECSPI3, s_ecspiHandle[3]); +} +#endif /* ECSPI3 */ + +#if defined(ECSPI4) +void ECSPI4_DriverIRQHandler(void) +{ + assert(s_ecspiHandle[4]); + ECSPI_CommonIRQHandler(ECSPI4, s_ecspiHandle[4]); +} +#endif /* ECSPI4 */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.h new file mode 100644 index 0000000000..b5885572da --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_ecspi.h @@ -0,0 +1,749 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_ECSPI_H_ +#define _FSL_ECSPI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ecspi_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief ECSPI driver version 2.0.0. */ +#define FSL_ECSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#ifndef ECSPI_DUMMYDATA +/*! @brief ECSPI dummy transfer data, the data is sent while txBuff is NULL. */ +#define ECSPI_DUMMYDATA (0xFFFFFFFFU) +#endif + +/*! @brief Return status for the ECSPI driver. */ +enum _ecspi_status +{ + kStatus_ECSPI_Busy = MAKE_STATUS(kStatusGroup_ECSPI, 0), /*!< ECSPI bus is busy */ + kStatus_ECSPI_Idle = MAKE_STATUS(kStatusGroup_ECSPI, 1), /*!< ECSPI is idle */ + kStatus_ECSPI_Error = MAKE_STATUS(kStatusGroup_ECSPI, 2), /*!< ECSPI error */ + kStatus_ECSPI_HardwareOverFlow = MAKE_STATUS(kStatusGroup_ECSPI, 3), /*!< ECSPI hardware overflow */ +}; + +/*! @brief ECSPI clock polarity configuration. */ +typedef enum _ecspi_clock_polarity +{ + kECSPI_PolarityActiveHigh = 0x0U, /*!< Active-high ECSPI polarity high (idles low). */ + kECSPI_PolarityActiveLow, /*!< Active-low ECSPI polarity low (idles high). */ +} ecspi_clock_polarity_t; + +/*! @brief ECSPI clock phase configuration. */ +typedef enum _ecspi_clock_phase +{ + kECSPI_ClockPhaseFirstEdge = + 0x0U, /*!< First edge on SPSCK occurs at the middle of the first cycle of a data transfer. */ + kECSPI_ClockPhaseSecondEdge, /*!< First edge on SPSCK occurs at the start of the first cycle of a data transfer. */ +} ecspi_clock_phase_t; + +/*! @brief ECSPI interrupt sources. */ +enum _ecspi_interrupt_enable +{ + kECSPI_TxfifoEmptyInterruptEnable = ECSPI_INTREG_TEEN_MASK, /*!< Transmit FIFO buffer empty interrupt */ + kECSPI_TxFifoDataRequstInterruptEnable = ECSPI_INTREG_TDREN_MASK, /*!< Transmit FIFO data requst interrupt */ + kECSPI_TxFifoFullInterruptEnable = ECSPI_INTREG_TFEN_MASK, /*!< Transmit FIFO full interrupt */ + kECSPI_RxFifoReadyInterruptEnable = ECSPI_INTREG_RREN_MASK, /*!< Receiver FIFO ready interrupt */ + kECSPI_RxFifoDataRequstInterruptEnable = ECSPI_INTREG_RDREN_MASK, /*!< Receiver FIFO data requst interrupt */ + kECSPI_RxFifoFullInterruptEnable = ECSPI_INTREG_RFEN_MASK, /*!< Receiver FIFO full interrupt */ + kECSPI_RxFifoOverFlowInterruptEnable = ECSPI_INTREG_ROEN_MASK, /*!< Receiver FIFO buffer overflow interrupt */ + kECSPI_TransferCompleteInterruptEnable = ECSPI_INTREG_TCEN_MASK, /*!< Transfer complete interrupt */ + kECSPI_AllInterruptEnable = (ECSPI_INTREG_TEEN_MASK | ECSPI_INTREG_TDREN_MASK | ECSPI_INTREG_TFEN_MASK | + ECSPI_INTREG_RREN_MASK | ECSPI_INTREG_RDREN_MASK | ECSPI_INTREG_RFEN_MASK | + ECSPI_INTREG_ROEN_MASK | ECSPI_INTREG_TCEN_MASK), /*!< All interrupt */ +}; + +/*! @brief ECSPI status flags. */ +enum _ecspi_flags +{ + kECSPI_TxfifoEmptyFlag = ECSPI_STATREG_TE_MASK, /*!< Transmit FIFO buffer empty flag */ + kECSPI_TxFifoDataRequstFlag = ECSPI_STATREG_TDR_MASK, /*!< Transmit FIFO data requst flag */ + kECSPI_TxFifoFullFlag = ECSPI_STATREG_TF_MASK, /*!< Transmit FIFO full flag */ + kECSPI_RxFifoReadyFlag = ECSPI_STATREG_RR_MASK, /*!< Receiver FIFO ready flag */ + kECSPI_RxFifoDataRequstFlag = ECSPI_STATREG_RDR_MASK, /*!< Receiver FIFO data requst flag */ + kECSPI_RxFifoFullFlag = ECSPI_STATREG_RF_MASK, /*!< Receiver FIFO full flag */ + kECSPI_RxFifoOverFlowFlag = ECSPI_STATREG_RO_MASK, /*!< Receiver FIFO buffer overflow flag */ + kECSPI_TransferCompleteFlag = ECSPI_STATREG_TC_MASK, /*!< Transfer complete flag */ +}; +/*! @brief ECSPI DMA enable.*/ +enum _ecspi_dma_enable_t +{ + kECSPI_TxDmaEnable = ECSPI_DMAREG_TEDEN_MASK, /*!< Tx DMA request source */ + kECSPI_RxDmaEnable = ECSPI_DMAREG_RXDEN_MASK, /*!< Rx DMA request source */ + kECSPI_DmaAllEnable = (ECSPI_DMAREG_TEDEN_MASK | ECSPI_DMAREG_RXDEN_MASK) /*!< All DMA request source*/ +}; + +/*! @brief ECSPI SPI_RDY signal configuration. */ +typedef enum _ecspi_data_ready +{ + kECSPI_DataReadyIgnore = 0x0U, /*!< SPI_RDY signal is ignored */ + kECSPI_DataReadyFallingEdge, /*!< SPI_RDY signal will be triggerd by the falling edge */ + kECSPI_DataReadyLowLevel, /*!< SPI_RDY signal will be triggerd by a low level */ +} ecspi_Data_ready_t; + +/*! @brief ECSPI channel select source. */ +typedef enum _ecspi_channel_source +{ + kECSPI_Channel0 = 0x0U, /*!< Channel 0 is selectd */ + kECSPI_Channel1, /*!< Channel 1 is selectd */ + kECSPI_Channel2, /*!< Channel 2 is selectd */ + kECSPI_Channel3, /*!< Channel 3 is selectd */ +} ecspi_channel_source_t; + +/*! @brief ECSPI master or slave mode configuration. */ +typedef enum _ecspi_master_slave_mode +{ + kECSPI_Slave = 0U, /*!< ECSPI peripheral operates in slave mode.*/ + kECSPI_Master, /*!< ECSPI peripheral operates in master mode.*/ +} ecspi_master_slave_mode_t; + +/*! @brief ECSPI data line inactive state configuration. */ +typedef enum _ecspi_data_line_inactive_state_t +{ + kECSPI_DataLineInactiveStateHigh = 0x0U, /*!< The data line inactive state stays high. */ + kECSPI_DataLineInactiveStateLow, /*!< The data line inactive state stays low. */ +} ecspi_data_line_inactive_state_t; + +/*! @brief ECSPI clock inactive state configuration. */ +typedef enum _ecspi_clock_inactive_state_t +{ + kECSPI_ClockInactiveStateLow = 0x0U, /*!< The SCLK inactive state stays low. */ + kECSPI_ClockInactiveStateHigh, /*!< The SCLK inactive state stays high. */ +} ecspi_clock_inactive_state_t; + +/*! @brief ECSPI active state configuration.*/ +typedef enum _ecspi_chip_select_active_state_t +{ + kECSPI_ChipSelectActiveStateLow = 0x0U, /*!< The SS signal line active stays low. */ + kECSPI_ChipSelectActiveStateHigh, /*!< The SS signal line active stays high. */ +} ecspi_chip_select_active_state_t; + +/*! @brief ECSPI wave form configuration.*/ +typedef enum _ecspi_wave_form_t +{ + kECSPI_WaveFormSingle = 0x0U, /*!< The wave form for signal burst */ + kECSPI_WaveFormMultiple, /*!< The wave form for multiple burst */ +} ecspi_wave_form_t; + +/*! @brief ECSPI sample period clock configuration.*/ +typedef enum _ecspi_sample_period_clock_source +{ + kECSPI_spiClock = 0x0U, /*!< The sample period clock source is SCLK. */ + kECSPI_lowFreqClock, /*!< The sample seriod clock source is low_frequency reference clock(32.768 kHz). */ +} ecspi_sample_period_clock_source_t; + +/*! @brief ECSPI user channel configure structure.*/ +typedef struct _ecspi_channel_config +{ + ecspi_master_slave_mode_t channelMode; /*!< Channel mode */ + ecspi_clock_inactive_state_t clockInactiveState; /*!< Clock line (SCLK) inactive state */ + ecspi_data_line_inactive_state_t dataLineInactiveState; /*!< Data line (MOSI&MISO) inactive state */ + ecspi_chip_select_active_state_t chipSlectActiveState; /*!< Chip select(SS) line active state */ + ecspi_wave_form_t waveForm; /*!< Wave form */ + ecspi_clock_polarity_t polarity; /*!< Clock polarity */ + ecspi_clock_phase_t phase; /*!< Clock phase */ +} ecspi_channel_config_t; + +/*! @brief ECSPI master configure structure.*/ +typedef struct _ecspi_master_config +{ + ecspi_channel_source_t channel; /*!< Channel number */ + ecspi_channel_config_t channelConfig; /*!< Channel configuration */ + ecspi_sample_period_clock_source_t samplePeriodClock; /*!< Sample period clock source */ + + uint8_t burstLength; /*!< Burst length */ + uint8_t chipSelectDelay; /*!< SS delay time */ + uint16_t samplePeriod; /*!< Sample period */ + uint8_t txFifoThreshold; /*!< TX Threshold */ + uint8_t rxFifoThreshold; /*!< RX Threshold */ + uint32_t baudRate_Bps; /*!< ECSPI baud rate for master mode */ +} ecspi_master_config_t; + +/*! @brief ECSPI slave configure structure.*/ +typedef struct _ecspi_slave_config +{ + ecspi_channel_source_t channel; /*Channel number */ + uint8_t burstLength; /*!< Burst length */ + uint8_t txFifoThreshold; /*!< TX Threshold */ + uint8_t rxFifoThreshold; /*!< RX Threshold */ + ecspi_channel_config_t channelConfig; /*!< Channel configuration */ +} ecspi_slave_config_t; + +/*! @brief ECSPI transfer structure */ +typedef struct _ecspi_transfer +{ + uint32_t *txData; /*!< Send buffer */ + uint32_t *rxData; /*!< Receive buffer */ + size_t dataSize; /*!< Transfer bytes */ + ecspi_channel_source_t channel; /*!< ECSPI channel select */ +} ecspi_transfer_t; + +typedef struct _ecspi_master_handle ecspi_master_handle_t; +/*! @brief Slave handle is the same with master handle */ +typedef ecspi_master_handle_t ecspi_slave_handle_t; + +/*! @brief ECSPI master callback for finished transmit */ +typedef void (*ecspi_master_callback_t)(ECSPI_Type *base, + ecspi_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief ECSPI slave callback for finished transmit */ +typedef void (*ecspi_slave_callback_t)(ECSPI_Type *base, ecspi_slave_handle_t *handle, status_t status, void *userData); + +/*! @brief ECSPI master handle structure */ +struct _ecspi_master_handle +{ + ecspi_channel_source_t channel; /*!< Channel number */ + uint32_t *volatile txData; /*!< Transfer buffer */ + uint32_t *volatile rxData; /*!< Receive buffer */ + volatile size_t txRemainingBytes; /*!< Send data remaining in bytes */ + volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes */ + volatile uint32_t state; /*!< ECSPI internal state */ + size_t transferSize; /*!< Bytes to be transferred */ + ecspi_master_callback_t callback; /*!< ECSPI callback */ + void *userData; /*!< Callback parameter */ +}; + +#if defined(__cplusplus) +extern "C" { +#endif +/******************************************************************************* + * APIs + ******************************************************************************/ +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Sets the ECSPI configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in ECSPI_MasterInit(). + * User may use the initialized structure unchanged in ECSPI_MasterInit, or modify + * some fields of the structure before calling ECSPI_MasterInit. After calling this API, + * the master is ready to transfer. + * Example: + @code + ecspi_master_config_t config; + ECSPI_MasterGetDefaultConfig(&config); + @endcode + * + * @param config pointer to config structure + */ +void ECSPI_MasterGetDefaultConfig(ecspi_master_config_t *config); + +/*! + * @brief Initializes the ECSPI with configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by ECSPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + @code + ecspi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + ECSPI_MasterInit(ECSPI0, &config); + @endcode + * + * @param base ECSPI base pointer + * @param config pointer to master configuration structure + * @param srcClock_Hz Source clock frequency. + */ +void ECSPI_MasterInit(ECSPI_Type *base, const ecspi_master_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Sets the ECSPI configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in ECSPI_SlaveInit(). + * User may use the initialized structure unchanged in ECSPI_SlaveInit(), or modify + * some fields of the structure before calling ECSPI_SlaveInit(). After calling this API, + * the master is ready to transfer. + * Example: + @code + ecspi_Slaveconfig_t config; + ECSPI_SlaveGetDefaultConfig(&config); + @endcode + * + * @param config pointer to config structure + */ +void ECSPI_SlaveGetDefaultConfig(ecspi_slave_config_t *config); + +/*! + * @brief Initializes the ECSPI with configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by ECSPI_SlaveGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + @code + ecspi_Salveconfig_t config = { + .baudRate_Bps = 400000, + ... + }; + ECSPI_SlaveInit(ECSPI1, &config); + @endcode + * + * @param base ECSPI base pointer + * @param config pointer to master configuration structure + */ +void ECSPI_SlaveInit(ECSPI_Type *base, const ecspi_slave_config_t *config); + +/*! + * @brief De-initializes the ECSPI. + * + * Calling this API resets the ECSPI module, gates the ECSPI clock. + * The ECSPI module can't work unless calling the ECSPI_MasterInit/ECSPI_SlaveInit to initialize module. + * + * @param base ECSPI base pointer + */ +void ECSPI_Deinit(ECSPI_Type *base); + +/*! + * @brief Enables or disables the ECSPI. + * + * @param base ECSPI base pointer + * @param enable pass true to enable module, false to disable module + */ +static inline void ECSPI_Enable(ECSPI_Type *base, bool enable) +{ + if (enable) + { + base->CONREG |= ECSPI_CONREG_EN_MASK; + } + else + { + base->CONREG &= ~ECSPI_CONREG_EN_MASK; + } +} +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the status flag. + * + * @param base ECSPI base pointer + * @return ECSPI Status, use status flag to AND #_ecspi_flags could get the related status. + */ +static inline uint32_t ECSPI_GetStatusFlags(ECSPI_Type *base) +{ + return (base->STATREG); +} + +/*! + * @brief Clear the status flag. + * + * @param base ECSPI base pointer + * @param mask ECSPI Status, use status flag to AND #_ecspi_flags could get the related status. + */ +static inline void ECSPI_ClearStatusFlags(ECSPI_Type *base, uint32_t mask) +{ + base->STATREG |= mask; +} +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt for the ECSPI. + * + * @param base ECSPI base pointer + * @param mask ECSPI interrupt source. The parameter can be any combination of the following values: + * @arg kECSPI_TxfifoEmptyInterruptEnable + * @arg kECSPI_TxFifoDataRequstInterruptEnable + * @arg kECSPI_TxFifoFullInterruptEnable + * @arg kECSPI_RxFifoReadyInterruptEnable + * @arg kECSPI_RxFifoDataRequstInterruptEnable + * @arg kECSPI_RxFifoFullInterruptEnable + * @arg kECSPI_RxFifoOverFlowInterruptEnable + * @arg kECSPI_TransferCompleteInterruptEnable + * @arg kECSPI_AllInterruptEnable + */ +static inline void ECSPI_EnableInterrupts(ECSPI_Type *base, uint32_t mask) +{ + base->INTREG |= mask; +} + +/*! + * @brief Disables the interrupt for the ECSPI. + * + * @param base ECSPI base pointer + * @param mask ECSPI interrupt source. The parameter can be any combination of the following values: + * @arg kECSPI_TxfifoEmptyInterruptEnable + * @arg kECSPI_TxFifoDataRequstInterruptEnable + * @arg kECSPI_TxFifoFullInterruptEnable + * @arg kECSPI_RxFifoReadyInterruptEnable + * @arg kECSPI_RxFifoDataRequstInterruptEnable + * @arg kECSPI_RxFifoFullInterruptEnable + * @arg kECSPI_RxFifoOverFlowInterruptEnable + * @arg kECSPI_TransferCompleteInterruptEnable + * @arg kECSPI_AllInterruptEnable + */ +static inline void ECSPI_DisableInterrupts(ECSPI_Type *base, uint32_t mask) +{ + base->INTREG &= ~(mask); +} +/*! @} */ + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Software reset. + * + * @param base ECSPI base pointer + */ +static inline void ECSPI_SoftwareReset(ECSPI_Type *base) +{ + /* Disables the block and resets the internal logic with the exception of the ECSPI control register */ + base->CONREG &= ~ECSPI_CONREG_EN_MASK; + /* Software reset can not reset the control register, so clear the control register manually */ + base->CONREG = 0x0U; +} +/*! @} */ + +/*! + * @name Channel mode check + * @{ + */ + +/*! + * @brief Mode check + * + * @param base ECSPI base pointer + * @param channel ECSPI channel source + * @return mode of channel + */ +static inline bool ECSPI_IsMaster(ECSPI_Type *base, ecspi_channel_source_t channel) +{ + return (bool)(((base->CONREG & ECSPI_CONREG_CHANNEL_MODE_MASK) >> (ECSPI_CONREG_CHANNEL_MODE_SHIFT + channel)) & + 0x1U); +} +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the DMA source for ECSPI. + * + * @param base ECSPI base pointer + * @param source ECSPI DMA source. + * @param enable True means enable DMA, false means disable DMA + */ +static inline void ECSPI_EnableDMA(ECSPI_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->DMAREG |= mask; + } + else + { + base->DMAREG &= ~mask; + } +} +/*! @} */ + +/*! + * @name FIFO Operation + * @{ + */ + +/*! + * @brief Get the Tx FIFO data count. + * + * @param base ECSPI base pointer. + * @return the number of words in Tx FIFO buffer. + */ +static inline uint8_t ECSPI_GetTxFifoCount(ECSPI_Type *base) +{ + return (uint8_t)((base->TESTREG & ECSPI_TESTREG_TXCNT_MASK) >> ECSPI_TESTREG_TXCNT_SHIFT); +} + +/*! + * @brief Get the Rx FIFO data count. + * + * @param base ECSPI base pointer. + * @return the number of words in Rx FIFO buffer. + */ +static inline uint8_t ECSPI_GetRxFifoCount(ECSPI_Type *base) +{ + return (uint8_t)((base->TESTREG & ECSPI_TESTREG_RXCNT_MASK) >> ECSPI_TESTREG_RXCNT_SHIFT); +} +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Set channel select for transfer. + * + * @param base ECSPI base pointer + * @param channel Channel source. + */ +static inline void ECSPI_SetChannelSelect(ECSPI_Type *base, ecspi_channel_source_t channel) +{ + /* Clear Channel select bits in CONREG register */ + uint32_t temp = base->CONREG & (~(ECSPI_CONREG_CHANNEL_SELECT_MASK)); + /* Set channel select bits */ + base->CONREG = (temp | ECSPI_CONREG_CHANNEL_SELECT(channel)); +} +/*! + * @brief Set channel select configuration for transfer. + * + * The purpose of this API is to set the channel will be use to transfer. + * User may use this API after instance has been initialized or before transfer start. + * The configuration structure #_ecspi_channel_config_ can be filled by user from scratch. + * After calling this API, user can select this channel as transfer channel. + * + * @param base ECSPI base pointer + * @param channel Channel source. + * @param config Configuration struct of channel + */ +void ECSPI_SetChannelConfig(ECSPI_Type *base, ecspi_channel_source_t channel, const ecspi_channel_config_t *config); + +/*! + * @brief Sets the baud rate for ECSPI transfer. This is only used in master. + * + * @param base ECSPI base pointer + * @param baudRate_Bps baud rate needed in Hz. + * @param srcClock_Hz ECSPI source clock frequency in Hz. + */ +void ECSPI_SetBaudRate(ECSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends a buffer of data bytes using a blocking method. + * + * @note This function blocks via polling until all bytes have been sent. + * + * @param base ECSPI base pointer + * @param buffer The data bytes to send + * @param size The number of data bytes to send + */ +void ECSPI_WriteBlocking(ECSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Writes a data into the ECSPI data register. + * + * @param base ECSPI base pointer + * @param data Data needs to be write. + */ +static inline void ECSPI_WriteData(ECSPI_Type *base, uint32_t data) +{ + base->TXDATA = data; +} + +/*! + * @brief Gets a data from the ECSPI data register. + * + * @param base ECSPI base pointer + * @return Data in the register. + */ +static inline uint32_t ECSPI_ReadData(ECSPI_Type *base) +{ + return (uint32_t)(base->RXDATA); +} +/*! @} */ + +/*! + * @name Transactional + * @{ + */ +/*! + * @brief Initializes the ECSPI master handle. + * + * This function initializes the ECSPI master handle which can be used for other ECSPI master transactional APIs. + * Usually, + * for a specified ECSPI instance, call this API once to get the initialized handle. + * + * @param base ECSPI peripheral base address. + * @param handle ECSPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void ECSPI_MasterTransferCreateHandle(ECSPI_Type *base, + ecspi_master_handle_t *handle, + ecspi_master_callback_t callback, + void *userData); + +/*! + * @brief Transfers a block of data using a polling method. + * + * @param base SPI base pointer + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + */ +status_t ECSPI_MasterTransferBlocking(ECSPI_Type *base, ecspi_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking ECSPI interrupt transfer. + * + * @note The API immediately returns after transfer initialization is finished. + * @note If ECSPI transfer data frame size is 16 bits, the transfer size cannot be an odd number. + * + * @param base ECSPI peripheral base address. + * @param handle pointer to ecspi_master_handle_t structure which stores the transfer state + * @param xfer pointer to ecspi_transfer_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_ECSPI_Busy ECSPI is not idle, is running another transfer. + */ +status_t ECSPI_MasterTransferNonBlocking(ECSPI_Type *base, ecspi_master_handle_t *handle, ecspi_transfer_t *xfer); + +/*! + * @brief Gets the bytes of the ECSPI interrupt transferred. + * + * @param base ECSPI peripheral base address. + * @param handle Pointer to ECSPI transfer handle, this should be a static variable. + * @param count Transferred bytes of ECSPI master. + * @retval kStatus_ECSPI_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t ECSPI_MasterTransferGetCount(ECSPI_Type *base, ecspi_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an ECSPI transfer using interrupt. + * + * @param base ECSPI peripheral base address. + * @param handle Pointer to ECSPI transfer handle, this should be a static variable. + */ +void ECSPI_MasterTransferAbort(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/*! + * @brief Interrupts the handler for the ECSPI. + * + * @param base ECSPI peripheral base address. + * @param handle pointer to ecspi_master_handle_t structure which stores the transfer state. + */ +void ECSPI_MasterTransferHandleIRQ(ECSPI_Type *base, ecspi_master_handle_t *handle); + +/*! + * @brief Initializes the ECSPI slave handle. + * + * This function initializes the ECSPI slave handle which can be used for other ECSPI slave transactional APIs. Usually, + * for a specified ECSPI instance, call this API once to get the initialized handle. + * + * @param base ECSPI peripheral base address. + * @param handle ECSPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void ECSPI_SlaveTransferCreateHandle(ECSPI_Type *base, + ecspi_slave_handle_t *handle, + ecspi_slave_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking ECSPI slave interrupt transfer. + * + * @note The API returns immediately after the transfer initialization is finished. + * + * @param base ECSPI peripheral base address. + * @param handle pointer to ecspi_master_handle_t structure which stores the transfer state + * @param xfer pointer to ecspi_transfer_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_ECSPI_Busy ECSPI is not idle, is running another transfer. + */ +static inline status_t ECSPI_SlaveTransferNonBlocking(ECSPI_Type *base, + ecspi_slave_handle_t *handle, + ecspi_transfer_t *xfer) +{ + return ECSPI_MasterTransferNonBlocking(base, handle, xfer); +} + +/*! + * @brief Gets the bytes of the ECSPI interrupt transferred. + * + * @param base ECSPI peripheral base address. + * @param handle Pointer to ECSPI transfer handle, this should be a static variable. + * @param count Transferred bytes of ECSPI slave. + * @retval kStatus_ECSPI_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +static inline status_t ECSPI_SlaveTransferGetCount(ECSPI_Type *base, ecspi_slave_handle_t *handle, size_t *count) +{ + return ECSPI_MasterTransferGetCount(base, handle, count); +} + +/*! + * @brief Aborts an ECSPI slave transfer using interrupt. + * + * @param base ECSPI peripheral base address. + * @param handle Pointer to ECSPI transfer handle, this should be a static variable. + */ +static inline void ECSPI_SlaveTransferAbort(ECSPI_Type *base, ecspi_slave_handle_t *handle) +{ + ECSPI_MasterTransferAbort(base, handle); +} + +/*! + * @brief Interrupts a handler for the ECSPI slave. + * + * @param base ECSPI peripheral base address. + * @param handle pointer to ecspi_slave_handle_t structure which stores the transfer state + */ +void ECSPI_SlaveTransferHandleIRQ(ECSPI_Type *base, ecspi_slave_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_ECSPI_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.c new file mode 100644 index 0000000000..f0a6f0aaa8 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.c @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2017, NXP Semiconductors, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_elcdif.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for ELCDIF module. + * + * @param base ELCDIF peripheral base address + */ +static uint32_t ELCDIF_GetInstance(LCDIF_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to ELCDIF bases for each instance. */ +static LCDIF_Type *const s_elcdifBases[] = LCDIF_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to eLCDIF apb_clk for each instance. */ +static const clock_ip_name_t s_elcdifApbClocks[] = LCDIF_CLOCKS; +#if defined(LCDIF_PERIPH_CLOCKS) +/*! @brief Pointers to eLCDIF pix_clk for each instance. */ +static const clock_ip_name_t s_elcdifPixClocks[] = LCDIF_PERIPH_CLOCKS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief The control register value to select different pixel format. */ +elcdif_pixel_format_reg_t s_pixelFormatReg[] = { + /* kELCDIF_PixelFormatRAW8 */ + {/* Register CTRL. */ + LCDIF_CTRL_WORD_LENGTH(1U), + /* Register CTRL1. */ + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)}, + /* kELCDIF_PixelFormatRGB565 */ + {/* Register CTRL. */ + LCDIF_CTRL_WORD_LENGTH(0U) | LCDIF_CTRL_DATA_FORMAT_16_BIT(1U), + /* Register CTRL1. */ + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0FU)}, + /* kELCDIF_PixelFormatRGB666 */ + {/* Register CTRL. */ + LCDIF_CTRL_WORD_LENGTH(3U) | LCDIF_CTRL_DATA_FORMAT_24_BIT(1U), + /* Register CTRL1. */ + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)}, + /* kELCDIF_PixelFormatRGB888 */ + {/* Register CTRL. 24-bit. */ + LCDIF_CTRL_WORD_LENGTH(3U), + /* Register CTRL1. */ + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)}, +}; + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t ELCDIF_GetInstance(LCDIF_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_elcdifBases); instance++) + { + if (s_elcdifBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_elcdifBases)); + + return instance; +} + +void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config) +{ + assert(config); + assert(config->pixelFormat < ARRAY_SIZE(s_pixelFormatReg)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = ELCDIF_GetInstance(base); + /* Enable the clock. */ + CLOCK_EnableClock(s_elcdifApbClocks[instance]); +#if defined(LCDIF_PERIPH_CLOCKS) + CLOCK_EnableClock(s_elcdifPixClocks[instance]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset. */ + ELCDIF_Reset(base); + + base->CTRL = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl | (uint32_t)(config->dataBus) | + LCDIF_CTRL_DOTCLK_MODE_MASK | /* RGB mode. */ + LCDIF_CTRL_BYPASS_COUNT_MASK | /* Keep RUN bit set. */ + LCDIF_CTRL_MASTER_MASK; + + base->CTRL1 = s_pixelFormatReg[(uint32_t)config->pixelFormat].regCtrl1; + + base->TRANSFER_COUNT = ((uint32_t)config->panelHeight << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT) | + ((uint32_t)config->panelWidth << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT); + + base->VDCTRL0 = LCDIF_VDCTRL0_ENABLE_PRESENT_MASK | /* Data enable signal. */ + LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK | /* VSYNC period in the unit of display clock. */ + LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK | /* VSYNC pulse width in the unit of display clock. */ + (uint32_t)config->polarityFlags | (uint32_t)config->vsw; + + base->VDCTRL1 = config->vsw + config->panelHeight + config->vfp + config->vbp; + base->VDCTRL2 = ((uint32_t)config->hsw << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT) | + ((uint32_t)(config->hfp + config->hbp + config->panelWidth + config->hsw)) + << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT; + + base->VDCTRL3 = (((uint32_t)config->hbp + config->hsw) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT) | + (((uint32_t)config->vbp + config->vsw) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT); + + base->VDCTRL4 = LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK | + ((uint32_t)config->panelWidth << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT); + + base->CUR_BUF = config->bufferAddr; + base->NEXT_BUF = config->bufferAddr; +} + +void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config) +{ + assert(config); + + config->panelWidth = 480U; + config->panelHeight = 272U; + config->hsw = 41; + config->hfp = 4; + config->hbp = 8; + config->vsw = 10; + config->vfp = 4; + config->vbp = 2; + config->polarityFlags = kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveLow | + kELCDIF_DriveDataOnFallingClkEdge; + config->bufferAddr = 0U; + config->pixelFormat = kELCDIF_PixelFormatRGB888; + config->dataBus = kELCDIF_DataBus24Bit; +} + +void ELCDIF_Deinit(LCDIF_Type *base) +{ + ELCDIF_Reset(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = ELCDIF_GetInstance(base); +/* Disable the clock. */ +#if defined(LCDIF_PERIPH_CLOCKS) + CLOCK_DisableClock(s_elcdifPixClocks[instance]); +#endif + CLOCK_DisableClock(s_elcdifApbClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void ELCDIF_RgbModeStop(LCDIF_Type *base) +{ + base->CTRL_CLR = LCDIF_CTRL_DOTCLK_MODE_MASK; + + /* Wait for data transfer finished. */ + while (base->CTRL & LCDIF_CTRL_DOTCLK_MODE_MASK) + { + } +} + +void ELCDIF_Reset(LCDIF_Type *base) +{ + volatile uint32_t i = 0x100; + + /* Disable the clock gate. */ + base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK; + /* Confirm the clock gate is disabled. */ + while (base->CTRL & LCDIF_CTRL_CLKGATE_MASK) + { + } + + /* Reset the block. */ + base->CTRL_SET = LCDIF_CTRL_SFTRST_MASK; + /* Confirm the reset bit is set. */ + while (!(base->CTRL & LCDIF_CTRL_SFTRST_MASK)) + { + } + + /* Delay for the reset. */ + while (i--) + { + } + + /* Bring the module out of reset. */ + base->CTRL_CLR = LCDIF_CTRL_SFTRST_MASK; + /* Disable the clock gate. */ + base->CTRL_CLR = LCDIF_CTRL_CLKGATE_MASK; +} + +void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config) +{ + assert(config); + + base->AS_CTRL = (base->AS_CTRL & ~LCDIF_AS_CTRL_FORMAT_MASK) | LCDIF_AS_CTRL_FORMAT(config->pixelFormat); + base->AS_BUF = config->bufferAddr; + base->AS_NEXT_BUF = config->bufferAddr; +} + +void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config) +{ + assert(config); + uint32_t reg; + + reg = base->AS_CTRL; + reg &= ~(LCDIF_AS_CTRL_ALPHA_INVERT_MASK | LCDIF_AS_CTRL_ROP_MASK | LCDIF_AS_CTRL_ALPHA_MASK | + LCDIF_AS_CTRL_ALPHA_CTRL_MASK); + reg |= (LCDIF_AS_CTRL_ROP(config->ropMode) | LCDIF_AS_CTRL_ALPHA(config->alpha) | + LCDIF_AS_CTRL_ALPHA_CTRL(config->alphaMode)); + + if (config->invertAlpha) + { + reg |= LCDIF_AS_CTRL_ALPHA_INVERT_MASK; + } + + base->AS_CTRL = reg; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.h new file mode 100644 index 0000000000..84d6b2aa9c --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_elcdif.h @@ -0,0 +1,659 @@ +/* + * Copyright (c) 2017, NXP Semiconductors, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_ELCDIF_H_ +#define _FSL_ELCDIF_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup elcdif + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief eLCDIF driver version */ +#define FSL_ELCDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/* All IRQ flags in CTRL1 register. */ +#define ELCDIF_CTRL1_IRQ_MASK \ + (LCDIF_CTRL1_BM_ERROR_IRQ_MASK | LCDIF_CTRL1_OVERFLOW_IRQ_MASK | LCDIF_CTRL1_UNDERFLOW_IRQ_MASK | \ + LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK | LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) + +/* All IRQ enable control bits in CTRL1 register. */ +#define ELCDIF_CTRL1_IRQ_EN_MASK \ + (LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK | LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK | LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK | \ + LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK | LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) + +/* All IRQ flags in AS_CTRL register. */ +#define ELCDIF_AS_CTRL_IRQ_MASK (LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) + +/* All IRQ enable control bits in AS_CTRL register. */ +#define ELCDIF_AS_CTRL_IRQ_EN_MASK (LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) + +#if ((ELCDIF_CTRL1_IRQ_MASK & ELCDIF_AS_CTRL_IRQ_MASK) || (ELCDIF_AS_CTRL_IRQ_MASK & ELCDIF_AS_CTRL_IRQ_EN_MASK)) +#error Interrupt bits overlap, need to update the interrupt functions. +#endif + +/*! + * @brief eLCDIF signal polarity flags + */ +enum _elcdif_polarity_flags +{ + kELCDIF_VsyncActiveLow = 0U, /*!< VSYNC active low. */ + kELCDIF_VsyncActiveHigh = LCDIF_VDCTRL0_VSYNC_POL_MASK, /*!< VSYNC active high. */ + kELCDIF_HsyncActiveLow = 0U, /*!< HSYNC active low. */ + kELCDIF_HsyncActiveHigh = LCDIF_VDCTRL0_HSYNC_POL_MASK, /*!< HSYNC active high. */ + kELCDIF_DataEnableActiveLow = 0U, /*!< Data enable line active low. */ + kELCDIF_DataEnableActiveHigh = LCDIF_VDCTRL0_ENABLE_POL_MASK, /*!< Data enable line active high. */ + kELCDIF_DriveDataOnFallingClkEdge = 0U, /*!< Drive data on falling clock edge, capture data + on rising clock edge. */ + kELCDIF_DriveDataOnRisingClkEdge = LCDIF_VDCTRL0_DOTCLK_POL_MASK, /*!< Drive data on falling + clock edge, capture data + on rising clock edge. */ +}; + +/*! + * @brief The eLCDIF interrupts to enable. + */ +enum _elcdif_interrupt_enable +{ + kELCDIF_BusMasterErrorInterruptEnable = LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK, /*!< Bus master error interrupt. */ + kELCDIF_TxFifoOverflowInterruptEnable = LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK, /*!< TXFIFO overflow interrupt. */ + kELCDIF_TxFifoUnderflowInterruptEnable = LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK, /*!< TXFIFO underflow interrupt. */ + kELCDIF_CurFrameDoneInterruptEnable = + LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK, /*!< Interrupt when hardware enters vertical blanking state. */ + kELCDIF_VsyncEdgeInterruptEnable = + LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK, /*!< Interrupt when hardware encounters VSYNC edge. */ + kELCDIF_SciSyncOnInterruptEnable = + LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK, /*!< Interrupt when eLCDIF lock with CSI input. */ +}; + +/*! + * @brief The eLCDIF interrupt status flags. + */ +enum _elcdif_interrupt_flags +{ + kELCDIF_BusMasterError = LCDIF_CTRL1_BM_ERROR_IRQ_MASK, /*!< Bus master error interrupt. */ + kELCDIF_TxFifoOverflow = LCDIF_CTRL1_OVERFLOW_IRQ_MASK, /*!< TXFIFO overflow interrupt. */ + kELCDIF_TxFifoUnderflow = LCDIF_CTRL1_UNDERFLOW_IRQ_MASK, /*!< TXFIFO underflow interrupt. */ + kELCDIF_CurFrameDone = + LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK, /*!< Interrupt when hardware enters vertical blanking state. */ + kELCDIF_VsyncEdge = LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK, /*!< Interrupt when hardware encounters VSYNC edge. */ + kELCDIF_SciSyncOn = LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK, /*!< Interrupt when eLCDIF lock with CSI input. */ +}; + +/*! + * @brief eLCDIF status flags + */ +enum _elcdif_status_flags +{ + kELCDIF_LFifoFull = LCDIF_STAT_LFIFO_FULL_MASK, /*!< LFIFO full. */ + kELCDIF_LFifoEmpty = LCDIF_STAT_LFIFO_EMPTY_MASK, /*!< LFIFO empty. */ + kELCDIF_TxFifoFull = LCDIF_STAT_TXFIFO_FULL_MASK, /*!< TXFIFO full. */ + kELCDIF_TxFifoEmpty = LCDIF_STAT_TXFIFO_EMPTY_MASK, /*!< TXFIFO empty. */ + kELCDIF_LcdControllerBusy = LCDIF_STAT_BUSY_MASK, /*!< The external LCD controller busy signal. */ + kELCDIF_CurDviField2 = LCDIF_STAT_DVI_CURRENT_FIELD_MASK, /*!< Current DVI filed, if set, then current filed is 2, + otherwise current filed is 1. */ +}; + +/*! + * @brief The pixel format. + * + * This enumerator should be defined together with the array s_pixelFormatReg. + * To support new pixel format, enhance this enumerator and s_pixelFormatReg. + */ +typedef enum _elcdif_pixel_format +{ + kELCDIF_PixelFormatRAW8 = 0, /*!< RAW 8 bit, four data use 32 bits. */ + kELCDIF_PixelFormatRGB565 = 1, /*!< RGB565, two pixel use 32 bits. */ + kELCDIF_PixelFormatRGB666 = 2, /*!< RGB666 unpacked, one pixel uses 32 bits, high byte unused, + upper 2 bits of other bytes unused. */ + kELCDIF_PixelFormatRGB888 = 3, /*!< RGB888 unpacked, one pixel uses 32 bits, high byte unused. */ +} elcdif_pixel_format_t; + +/*! @brief The LCD data bus type. */ +typedef enum _elcdif_lcd_data_bus +{ + kELCDIF_DataBus8Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(1), /*!< 8-bit data bus. */ + kELCDIF_DataBus16Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(0), /*!< 16-bit data bus, support RGB565. */ + kELCDIF_DataBus18Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(2), /*!< 18-bit data bus, support RGB666. */ + kELCDIF_DataBus24Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(3), /*!< 24-bit data bus, support RGB888. */ +} elcdif_lcd_data_bus_t; + +/*! + * @brief The register value when using different pixel format. + * + * These register bits control the pixel format: + * - CTRL[DATA_FORMAT_24_BIT] + * - CTRL[DATA_FORMAT_18_BIT] + * - CTRL[DATA_FORMAT_16_BIT] + * - CTRL[WORD_LENGTH] + * - CTRL1[BYTE_PACKING_FORMAT] + */ +typedef struct _elcdif_pixel_format_reg +{ + uint32_t regCtrl; /*!< Value of register CTRL. */ + uint32_t regCtrl1; /*!< Value of register CTRL1. */ +} elcdif_pixel_format_reg_t; + +/*! + * @brief eLCDIF configure structure for RGB mode (DOTCLK mode). + */ +typedef struct _elcdif_rgb_mode_config +{ + uint16_t panelWidth; /*!< Display panel width, pixels per line. */ + uint16_t panelHeight; /*!< Display panel height, how many lines per panel. */ + uint8_t hsw; /*!< HSYNC pulse width. */ + uint8_t hfp; /*!< Horizontal front porch. */ + uint8_t hbp; /*!< Horizontal back porch. */ + uint8_t vsw; /*!< VSYNC pulse width. */ + uint8_t vfp; /*!< Vrtical front porch. */ + uint8_t vbp; /*!< Vertical back porch. */ + uint32_t polarityFlags; /*!< OR'ed value of @ref _elcdif_polarity_flags, used to contol the signal polarity. */ + uint32_t bufferAddr; /*!< Frame buffer address. */ + elcdif_pixel_format_t pixelFormat; /*!< Pixel format. */ + elcdif_lcd_data_bus_t dataBus; /*!< LCD data bus. */ +} elcdif_rgb_mode_config_t; + +/*! + * @brief eLCDIF alpha surface pixel format. + */ +typedef enum _elcdif_as_pixel_format +{ + kELCDIF_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */ + kELCDIF_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */ + kELCDIF_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */ + kELCDIF_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */ + kELCDIF_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */ + kELCDIF_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */ + kELCDIF_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */ +} elcdif_as_pixel_format_t; + +/*! + * @brief eLCDIF alpha surface buffer configuration. + */ +typedef struct _elcdif_as_buffer_config +{ + uint32_t bufferAddr; /*!< Buffer address. */ + elcdif_as_pixel_format_t pixelFormat; /*!< Pixel format. */ +} elcdif_as_buffer_config_t; + +/*! + * @brief eLCDIF alpha mode during blending. + */ +typedef enum _elcdif_alpha_mode +{ + kELCDIF_AlphaEmbedded, /*!< The alpha surface pixel alpha value will be used for blend. */ + kELCDIF_AlphaOverride, /*!< The user defined alpha value will be used for blend directly. */ + kELCDIF_AlphaMultiply, /*!< The alpha surface pixel alpha value scaled the user defined + alpha value will be used for blend, for example, pixel alpha set + set to 200, user defined alpha set to 100, then the reault alpha + is 200 * 100 / 255. */ + kELCDIF_AlphaRop /*!< Raster operation. */ +} elcdif_alpha_mode_t; + +/*! + * @brief eLCDIF ROP mode during blending. + * + * Explanation: + * - AS: Alpha surface + * - PS: Process surface + * - nAS: Alpha surface NOT value + * - nPS: Process surface NOT value + */ +typedef enum _elcdif_rop_mode +{ + kELCDIF_RopMaskAs = 0x0, /*!< AS AND PS. */ + kELCDIF_RopMaskNotAs = 0x1, /*!< nAS AND PS. */ + kELCDIF_RopMaskAsNot = 0x2, /*!< AS AND nPS. */ + kELCDIF_RopMergeAs = 0x3, /*!< AS OR PS. */ + kELCDIF_RopMergeNotAs = 0x4, /*!< nAS OR PS. */ + kELCDIF_RopMergeAsNot = 0x5, /*!< AS OR nPS. */ + kELCDIF_RopNotCopyAs = 0x6, /*!< nAS. */ + kELCDIF_RopNot = 0x7, /*!< nPS. */ + kELCDIF_RopNotMaskAs = 0x8, /*!< AS NAND PS. */ + kELCDIF_RopNotMergeAs = 0x9, /*!< AS NOR PS. */ + kELCDIF_RopXorAs = 0xA, /*!< AS XOR PS. */ + kELCDIF_RopNotXorAs = 0xB /*!< AS XNOR PS. */ +} elcdif_rop_mode_t; + +/*! + * @brief eLCDIF alpha surface blending configuration. + */ +typedef struct _elcdif_as_blend_config +{ + uint8_t alpha; /*!< User defined alpha value, only used when @ref alphaMode is @ref kELCDIF_AlphaOverride or @ref + kELCDIF_AlphaRop. */ + bool invertAlpha; /*!< Set true to invert the alpha. */ + elcdif_alpha_mode_t alphaMode; /*!< Alpha mode. */ + elcdif_rop_mode_t ropMode; /*!< ROP mode, only valid when @ref alphaMode is @ref kELCDIF_AlphaRop. */ +} elcdif_as_blend_config_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name eLCDIF initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode). + * + * This function ungates the eLCDIF clock and configures the eLCDIF peripheral according + * to the configuration structure. + * + * @param base eLCDIF peripheral base address. + * @param config Pointer to the configuration structure. + */ +void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config); + +/*! + * @brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * @code + config->panelWidth = 480U; + config->panelHeight = 272U; + config->hsw = 41; + config->hfp = 4; + config->hbp = 8; + config->vsw = 10; + config->vfp = 4; + config->vbp = 2; + config->polarityFlags = kELCDIF_VsyncActiveLow | + kELCDIF_HsyncActiveLow | + kELCDIF_DataEnableActiveLow | + kELCDIF_DriveDataOnFallingClkEdge; + config->bufferAddr = 0U; + config->pixelFormat = kELCDIF_PixelFormatRGB888; + config->dataBus = kELCDIF_DataBus24Bit; + @code + * + * @param config Pointer to the eLCDIF configuration structure. + */ +void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config); + +/*! + * @brief Deinitializes the eLCDIF peripheral. + * + * @param base eLCDIF peripheral base address. + */ +void ELCDIF_Deinit(LCDIF_Type *base); + +/* @} */ + +/*! + * @name Module operation + * @{ + */ + +/*! + * @brief Start to display in RGB (DOTCLK) mode. + * + * @param base eLCDIF peripheral base address. + */ +static inline void ELCDIF_RgbModeStart(LCDIF_Type *base) +{ + base->CTRL_SET = LCDIF_CTRL_RUN_MASK | LCDIF_CTRL_DOTCLK_MODE_MASK; +} + +/*! + * @brief Stop display in RGB (DOTCLK) mode and wait until finished. + * + * @param base eLCDIF peripheral base address. + */ +void ELCDIF_RgbModeStop(LCDIF_Type *base); + +/*! + * @brief Set the next frame buffer address to display. + * + * @param base eLCDIF peripheral base address. + * @param bufferAddr The frame buffer address to set. + */ +static inline void ELCDIF_SetNextBufferAddr(LCDIF_Type *base, uint32_t bufferAddr) +{ + base->NEXT_BUF = bufferAddr; +} + +/*! + * @brief Reset the eLCDIF peripheral. + * + * @param base eLCDIF peripheral base address. + */ +void ELCDIF_Reset(LCDIF_Type *base); + +/*! + * @brief Pull up or down the reset pin for the externel LCD controller. + * + * @param base eLCDIF peripheral base address. + * @param pullUp True to pull up reset pin, false to pull down. + */ +static inline void ELCDIF_PullUpResetPin(LCDIF_Type *base, bool pullUp) +{ + if (pullUp) + { + base->CTRL1_SET = LCDIF_CTRL1_RESET_MASK; + } + else + { + base->CTRL1_CLR = LCDIF_CTRL1_RESET_MASK; + } +} + +/*! + * @brief Enable or disable the hand shake with PXP. + * + * @param base eLCDIF peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void ELCDIF_EnablePxpHandShake(LCDIF_Type *base, bool enable) +{ + if (enable) + { + base->CTRL_SET = LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK; + } + else + { + base->CTRL_CLR = LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get the CRC value of the frame sent out. + * + * When a frame is sent complete (the interrupt @ref kELCDIF_CurFrameDone assert), this function + * can be used to get the CRC value of the frame sent. + * + * @param base eLCDIF peripheral base address. + * @return The CRC value. + * + * @note The CRC value is dependent on the LCD_DATABUS_WIDTH. + */ +static inline uint32_t ELCDIF_GetCrcValue(LCDIF_Type *base) +{ + return base->CRC_STAT; +} + +/*! + * @brief Get the bus master error virtual address. + * + * When bus master error occurs (the interrupt kELCDIF_BusMasterError assert), this function + * can get the virtual address at which the AXI master received an error + * response from the slave. + * + * @param base eLCDIF peripheral base address. + * @return The error virtual address. + */ +static inline uint32_t ELCDIF_GetBusMasterErrorAddr(LCDIF_Type *base) +{ + return base->BM_ERROR_STAT; +} + +/*! + * @brief Get the eLCDIF status. + * + * The status flags are returned as a mask value, application could check the + * corresponding bit. Example: + * + * @code + uint32_t statusFlags; + statusFlags = ELCDIF_GetStatus(LCDIF); + + // If LFIFO is full. + if (kELCDIF_LFifoFull & statusFlags) + { + // ...; + } + // If TXFIFO is empty. + if (kELCDIF_TxFifoEmpty & statusFlags) + { + // ...; + } + @endcode + * + * @param base eLCDIF peripheral base address. + * @return The mask value of status flags, it is OR'ed value of @ref _elcdif_status_flags. + */ +static inline uint32_t ELCDIF_GetStatus(LCDIF_Type *base) +{ + return base->STAT & (LCDIF_STAT_LFIFO_FULL_MASK | LCDIF_STAT_LFIFO_EMPTY_MASK | LCDIF_STAT_TXFIFO_FULL_MASK | + LCDIF_STAT_TXFIFO_EMPTY_MASK | LCDIF_STAT_BUSY_MASK | LCDIF_STAT_DVI_CURRENT_FIELD_MASK); +} + +/*! + * @brief Get current count in Latency buffer (LFIFO). + * + * @param base eLCDIF peripheral base address. + * @return The LFIFO current count + */ +static inline uint32_t ELCDIF_GetLFifoCount(LCDIF_Type *base) +{ + return (base->STAT & LCDIF_STAT_LFIFO_COUNT_MASK) >> LCDIF_STAT_LFIFO_COUNT_SHIFT; +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables eLCDIF interrupt requests. + * + * @param base eLCDIF peripheral base address. + * @param mask interrupt source, OR'ed value of _elcdif_interrupt_enable. + */ +static inline void ELCDIF_EnableInterrupts(LCDIF_Type *base, uint32_t mask) +{ + base->CTRL1_SET = (mask & ELCDIF_CTRL1_IRQ_EN_MASK); + base->AS_CTRL |= (mask & ELCDIF_AS_CTRL_IRQ_EN_MASK); +} + +/*! + * @brief Disables eLCDIF interrupt requests. + * + * @param base eLCDIF peripheral base address. + * @param mask interrupt source, OR'ed value of _elcdif_interrupt_enable. + */ +static inline void ELCDIF_DisableInterrupts(LCDIF_Type *base, uint32_t mask) +{ + base->CTRL1_CLR = (mask & ELCDIF_CTRL1_IRQ_EN_MASK); + base->AS_CTRL &= ~(mask & ELCDIF_AS_CTRL_IRQ_EN_MASK); +} + +/*! + * @brief Get eLCDIF interrupt peding status. + * + * @param base eLCDIF peripheral base address. + * @return Interrupt pending status, OR'ed value of _elcdif_interrupt_flags. + */ +static inline uint32_t ELCDIF_GetInterruptStatus(LCDIF_Type *base) +{ + uint32_t flags; + + flags = (base->CTRL1 & ELCDIF_CTRL1_IRQ_MASK); + flags |= (base->AS_CTRL & ELCDIF_AS_CTRL_IRQ_MASK); + + return flags; +} + +/*! + * @brief Clear eLCDIF interrupt peding status. + * + * @param base eLCDIF peripheral base address. + * @param mask of the flags to clear, OR'ed value of _elcdif_interrupt_flags. + */ +static inline void ELCDIF_ClearInterruptStatus(LCDIF_Type *base, uint32_t mask) +{ + base->CTRL1_CLR = (mask & ELCDIF_CTRL1_IRQ_MASK); + base->AS_CTRL &= ~(mask & ELCDIF_AS_CTRL_IRQ_MASK); +} + +/* @} */ + +/*! + * @name Alpha surface + * @{ + */ + +/*! + * @brief Set the configuration for alpha surface buffer. + * + * @param base eLCDIF peripheral base address. + * @param config Pointer to the configuration structure. + */ +void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config); + +/*! + * @brief Set the alpha surface blending configuration. + * + * @param base eLCDIF peripheral base address. + * @param config Pointer to the configuration structure. + */ +void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config); + +/*! + * @brief Set the next alpha surface buffer address. + * + * @param base eLCDIF peripheral base address. + * @param bufferAddr Alpha surface buffer address. + */ +static inline void ELCDIF_SetNextAlphaSurfaceBufferAddr(LCDIF_Type *base, uint32_t bufferAddr) +{ + base->AS_NEXT_BUF = bufferAddr; +} + +/*! + * @brief Set the overlay color key. + * + * If a pixel in the current overlay image with a color that falls in the range + * from the @p colorKeyLow to @p colorKeyHigh range, it will use the process surface + * pixel value for that location. + * + * @param base eLCDIF peripheral base address. + * @param colorKeyLow Color key low range. + * @param colorKeyHigh Color key high range. + * + * @note Colorkey operations are higher priority than alpha or ROP operations + */ +static inline void ELCDIF_SetOverlayColorKey(LCDIF_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh) +{ + base->AS_CLRKEYLOW = colorKeyLow; + base->AS_CLRKEYHIGH = colorKeyHigh; +} + +/*! + * @brief Enable or disable the color key. + * + * @param base eLCDIF peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void ELCDIF_EnableOverlayColorKey(LCDIF_Type *base, bool enable) +{ + if (enable) + { + base->AS_CTRL |= LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK; + } + else + { + base->AS_CTRL &= ~LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK; + } +} + +/*! + * @brief Enable or disable the alpha surface. + * + * @param base eLCDIF peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void ELCDIF_EnableAlphaSurface(LCDIF_Type *base, bool enable) +{ + if (enable) + { + base->AS_CTRL |= LCDIF_AS_CTRL_AS_ENABLE_MASK; + } + else + { + base->AS_CTRL &= ~LCDIF_AS_CTRL_AS_ENABLE_MASK; + } +} + +/*! + * @brief Enable or disable the process surface. + * + * Process surface is the normal frame buffer. The process surface content + * is controlled by @ref ELCDIF_SetNextBufferAddr. + * + * @param base eLCDIF peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void ELCDIF_EnableProcessSurface(LCDIF_Type *base, bool enable) +{ + if (enable) + { + base->AS_CTRL &= ~LCDIF_AS_CTRL_PS_DISABLE_MASK; + } + else + { + base->AS_CTRL |= LCDIF_AS_CTRL_PS_DISABLE_MASK; + } +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*_FSL_ELCDIF_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_enet.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_enet.c new file mode 100644 index 0000000000..9a1f10494b --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_enet.c @@ -0,0 +1,1243 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-06-16 songchao support emac driver + */ + +#include +#include "fsl_enet.h" +#include "fsl_iomuxc.h" +#include "ioremap.h" +#define DBG_TAG "drv.enet" +#define DBG_LVL DBG_LOG +#include + +#define ETH_ENABLE (1U) +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief IPv4 PTP message IP version offset. */ +#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU +/*! @brief IPv4 PTP message UDP protocol offset. */ +#define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U +/*! @brief IPv4 PTP message UDP port offset. */ +#define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U +/*! @brief IPv4 PTP message UDP message type offset. */ +#define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU +/*! @brief IPv4 PTP message UDP version offset. */ +#define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU +/*! @brief IPv4 PTP message UDP clock id offset. */ +#define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU +/*! @brief IPv4 PTP message UDP sequence id offset. */ +#define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U +/*! @brief IPv4 PTP message UDP control offset. */ +#define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU +/*! @brief IPv6 PTP message UDP protocol offset. */ +#define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U +/*! @brief IPv6 PTP message UDP port offset. */ +#define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U +/*! @brief IPv6 PTP message UDP message type offset. */ +#define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU +/*! @brief IPv6 PTP message UDP version offset. */ +#define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU +/*! @brief IPv6 PTP message UDP clock id offset. */ +#define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U +/*! @brief IPv6 PTP message UDP sequence id offset. */ +#define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU +/*! @brief IPv6 PTP message UDP control offset. */ +#define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU +/*! @brief PTPv2 message Ethernet packet type offset. */ +#define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU +/*! @brief PTPv2 message Ethernet message type offset. */ +#define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU +/*! @brief PTPv2 message Ethernet version type offset. */ +#define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU +/*! @brief PTPv2 message Ethernet clock id offset. */ +#define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22 +/*! @brief PTPv2 message Ethernet sequence id offset. */ +#define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c +/*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */ +#define ENET_ETHERNETL2 0x88F7U +/*! @brief Packet type IPv4. */ +#define ENET_IPV4 0x0800U +/*! @brief Packet type IPv6. */ +#define ENET_IPV6 0x86ddU +/*! @brief Packet type VLAN. */ +#define ENET_8021QVLAN 0x8100U +/*! @brief UDP protocol type. */ +#define ENET_UDPVERSION 0x0011U +/*! @brief Packet IP version IPv4. */ +#define ENET_IPV4VERSION 0x0004U +/*! @brief Packet IP version IPv6. */ +#define ENET_IPV6VERSION 0x0006U +/*! @brief Ethernet mac address length. */ +#define ENET_FRAME_MACLEN 6U +/*! @brief Ethernet VLAN header length. */ +#define ENET_FRAME_VLAN_TAGLEN 4U +/*! @brief MDC frequency. */ +#define ENET_MDC_FREQUENCY 2500000U +/*! @brief NanoSecond in one second. */ +#define ENET_NANOSECOND_ONE_SECOND 1000000000U +/*! @brief Define a common clock cycle delays used for time stamp capture. */ +#define ENET_1588TIME_DELAY_COUNT 10U +/*! @brief Defines the macro for converting constants from host byte order to network byte order. */ +#define ENET_HTONS(n) __REV16(n) +#define ENET_HTONL(n) __REV(n) +#define ENET_NTOHS(n) __REV16(n) +#define ENET_NTOHL(n) __REV(n) + +/* Typedef for interrupt handler. */ +typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle); +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +uint32_t ENET_GetInstance(ENET_Type *base); + +/*! + * @brief Set ENET MAC controller with the configuration. + * + * @param base ENET peripheral base address. + * @param config ENET Mac configuration. + * @param bufferConfig ENET buffer configuration. + * @param macAddr ENET six-byte mac address. + * @param srcClock_Hz ENET module clock source, normally it's system clock. + */ +static void ENET_SetMacController(ENET_Type *base, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz); +/*! + * @brief Set ENET handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param config ENET configuration stucture pointer. + * @param bufferConfig ENET buffer configuration. + */ +static void ENET_SetHandler(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig); +/*! + * @brief Set ENET MAC transmit buffer descriptors. + * + * @param txBdStartAlign The aligned start address of ENET transmit buffer descriptors. + * is recommended to evenly divisible by 16. + * @param txBuffStartAlign The aligned start address of ENET transmit buffers, must be evenly divisible by 16. + * @param txBuffSizeAlign The aligned ENET transmit buffer size, must be evenly divisible by 16. + * @param txBdNumber The number of ENET transmit buffers. + */ +static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartAlign, + uint8_t *txBuffStartAlign, + uint32_t txBuffSizeAlign, + uint32_t txBdNumber); + +/*! + * @brief Set ENET MAC receive buffer descriptors. + * + * @param rxBdStartAlign The aligned start address of ENET receive buffer descriptors. + * is recommended to evenly divisible by 16. + * @param rxBuffStartAlign The aligned start address of ENET receive buffers, must be evenly divisible by 16. + * @param rxBuffSizeAlign The aligned ENET receive buffer size, must be evenly divisible by 16. + * @param rxBdNumber The number of ENET receive buffers. + * @param enableInterrupt Enable/disables to generate the receive byte and frame interrupt. + * It's used for ENET_ENHANCEDBUFFERDESCRIPTOR_MODE enabled case. + */ +static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartAlign, + uint8_t *rxBuffStartAlign, + uint32_t rxBuffSizeAlign, + uint32_t rxBdNumber, + bool enableInterrupt); + +/*! + * @brief Updates the ENET read buffer descriptors. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + */ +static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle); + +void rt_hw_cpu_dcache_clean(void *addr, int size); +void rt_hw_cpu_dcache_invalidate(void *addr, int size); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to enet handles for each instance. */ +static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_ENET_COUNT] = {NULL,NULL}; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to enet clocks for each instance. */ +const clock_ip_name_t s_enetClock[] = ENET_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to enet transmit IRQ number for each instance. */ +static const IRQn_Type s_enetTxIrqId[] = ENET_Transmit_IRQS; +/*! @brief Pointers to enet receive IRQ number for each instance. */ +static const IRQn_Type s_enetRxIrqId[] = ENET_Receive_IRQS; + +/*! @brief Pointers to enet error IRQ number for each instance. */ +static const IRQn_Type s_enetErrIrqId[] = ENET_Error_IRQS; + +/*! @brief Pointers to enet bases for each instance. */ +static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS; + +/* ENET ISR for transactional APIs. */ +static enet_isr_t s_enetTxIsr = NULL; +static enet_isr_t s_enetRxIsr = NULL; +static enet_isr_t s_enetErrIsr = NULL; +static enet_isr_t s_enetTsIsr = NULL; + +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t ENET_GetInstance(ENET_Type *base) +{ + uint32_t instance; + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_enetBases); instance++) + { + if (s_enetBases[instance] == base) + { + break; + } + } + RT_ASSERT(instance < ARRAY_SIZE(s_enetBases)); + + return instance; +} + +void ENET_GetDefaultConfig(enet_config_t *config) +{ + /* Checks input parameter. */ + RT_ASSERT(config); + + /* Initializes the MAC configure structure to zero. */ + memset(config, 0, sizeof(enet_config_t)); + + /* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */ + config->miiMode = kENET_RmiiMode; + config->miiSpeed = kENET_MiiSpeed100M; + config->miiDuplex = kENET_MiiFullDuplex; + + /* Sets the maximum receive frame length. */ + config->rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; +} + +void ENET_Init(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz) +{ + /* Checks input parameters. */ + RT_ASSERT(handle); + RT_ASSERT(config); + RT_ASSERT(bufferConfig); + RT_ASSERT(bufferConfig->rxBdStartAddrAlign); + RT_ASSERT(bufferConfig->txBdStartAddrAlign); + RT_ASSERT(bufferConfig->rxBufferAlign); + RT_ASSERT(bufferConfig->txBufferAlign); + RT_ASSERT(macAddr); + RT_ASSERT(bufferConfig->rxBuffSizeAlign >= ENET_RX_MIN_BUFFERSIZE); + /* Make sure the buffers should be have the capability of process at least one maximum frame. */ + if (config->macSpecialConfig & kENET_ControlVLANTagEnable) + { + RT_ASSERT(bufferConfig->txBuffSizeAlign * bufferConfig->txBdNumber > (ENET_FRAME_MAX_FRAMELEN + ENET_FRAME_VLAN_TAGLEN)); + } + else + { + RT_ASSERT(bufferConfig->txBuffSizeAlign * bufferConfig->txBdNumber > ENET_FRAME_MAX_FRAMELEN); + RT_ASSERT(bufferConfig->rxBuffSizeAlign * bufferConfig->rxBdNumber > config->rxMaxFrameLen); + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate ENET clock. */ + uint32_t instance = ENET_GetInstance(IMX6UL_ENET); + CLOCK_EnableClock(s_enetClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* Reset ENET module. */ + ENET_Reset(base); + /* Initializes the ENET transmit buffer descriptors. */ + ENET_SetTxBufferDescriptors(bufferConfig->txBdStartAddrAlign, bufferConfig->txPhyBufferAlign, + bufferConfig->txBuffSizeAlign, bufferConfig->txBdNumber); + /* Initializes the ENET receive buffer descriptors. */ + + + ENET_SetRxBufferDescriptors(bufferConfig->rxBdStartAddrAlign, bufferConfig->rxPhyBufferAlign, + bufferConfig->rxBuffSizeAlign, bufferConfig->rxBdNumber, + !!(config->interrupt & (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt))); + /* Initializes the ENET MAC controller. */ + ENET_SetMacController(base, config, bufferConfig, macAddr, srcClock_Hz); + /* Set all buffers or data in handler for data transmit/receive process. */ + ENET_SetHandler(base, handle, config, bufferConfig); +} + +void ENET_Deinit(ENET_Type *base) +{ + /* Disable interrupt. */ + base->EIMR = 0; + + /* Disable ENET. */ + base->ECR &= ~ENET_ECR_ETHEREN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disables the clock source. */ + CLOCK_DisableClock(s_enetClock[ENET_GetInstance(IMX6UL_ENET)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData) +{ + RT_ASSERT(handle); + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; +} + +static void ENET_SetHandler(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig) +{ + uint32_t instance = ENET_GetInstance(IMX6UL_ENET); + memset(handle, 0, sizeof(enet_handle_t)); + handle->rxBdBase = bufferConfig->rxBdStartAddrAlign; + handle->rxBdCurrent = bufferConfig->rxBdStartAddrAlign; + handle->txBdBase = bufferConfig->txBdStartAddrAlign; + handle->txBdCurrent = bufferConfig->txBdStartAddrAlign; + handle->rxBuffSizeAlign = bufferConfig->rxBuffSizeAlign; + handle->txBuffSizeAlign = bufferConfig->txBuffSizeAlign; + + /* Save the handle pointer in the global variables. */ + s_ENETHandle[instance] = handle; + + /* Set the IRQ handler when the interrupt is enabled. */ + if (config->interrupt & ENET_TX_INTERRUPT) + { + s_enetTxIsr = ENET_TransmitIRQHandler; + EnableIRQ(s_enetTxIrqId[instance]); + } + if (config->interrupt & ENET_RX_INTERRUPT) + { + s_enetRxIsr = ENET_ReceiveIRQHandler; + EnableIRQ(s_enetRxIrqId[instance]); + } + if (config->interrupt & ENET_ERR_INTERRUPT) + { + s_enetErrIsr = ENET_ErrorIRQHandler; + EnableIRQ(s_enetErrIrqId[instance]); + } +} + +static void ENET_SetMacController(ENET_Type *base, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz) +{ + uint32_t rcr = 0; + uint32_t tcr = 0; + uint32_t ecr = 0; + uint32_t macSpecialConfig = config->macSpecialConfig; + uint32_t maxFrameLen = config->rxMaxFrameLen; + + /* Maximum frame length check. */ + if ((macSpecialConfig & kENET_ControlVLANTagEnable) && (maxFrameLen <= ENET_FRAME_MAX_FRAMELEN)) + { + maxFrameLen = (ENET_FRAME_MAX_FRAMELEN + ENET_FRAME_VLAN_TAGLEN); + } + + /* Configures MAC receive controller with user configure structure. */ + rcr = ENET_RCR_NLC(!!(macSpecialConfig & kENET_ControlRxPayloadCheckEnable)) | + ENET_RCR_CFEN(!!(macSpecialConfig & kENET_ControlFlowControlEnable)) | + ENET_RCR_FCE(!!(macSpecialConfig & kENET_ControlFlowControlEnable)) | + ENET_RCR_PADEN(!!(macSpecialConfig & kENET_ControlRxPadRemoveEnable)) | + ENET_RCR_BC_REJ(!!(macSpecialConfig & kENET_ControlRxBroadCastRejectEnable)) | + ENET_RCR_PROM(!!(macSpecialConfig & kENET_ControlPromiscuousEnable)) | ENET_RCR_MII_MODE(1) | + ENET_RCR_RMII_MODE(config->miiMode) | ENET_RCR_RMII_10T(!config->miiSpeed) | + ENET_RCR_MAX_FL(maxFrameLen) | ENET_RCR_CRCFWD(1); + /* Receive setting for half duplex. */ + if (config->miiDuplex == kENET_MiiHalfDuplex) + { + rcr |= ENET_RCR_DRT_MASK; + } + /* Sets internal loop only for MII mode. */ + if ((config->macSpecialConfig & kENET_ControlMIILoopEnable) && (config->miiMode == kENET_MiiMode)) + { + rcr |= ENET_RCR_LOOP_MASK; + rcr &= ~ENET_RCR_DRT_MASK; + } + base->RCR = rcr; + + /* Configures MAC transmit controller: duplex mode, mac address insertion. */ + tcr = base->TCR & ~(ENET_TCR_FDEN_MASK | ENET_TCR_ADDINS_MASK); + tcr |= ENET_TCR_FDEN(config->miiDuplex) | ENET_TCR_ADDINS(!!(macSpecialConfig & kENET_ControlMacAddrInsert)); + base->TCR = tcr; + + /* Configures receive and transmit accelerator. */ + base->TACC = config->txAccelerConfig; + base->RACC = config->rxAccelerConfig; + + /* Sets the pause duration and FIFO threshold for the flow control enabled case. */ + if (macSpecialConfig & kENET_ControlFlowControlEnable) + { + uint32_t reemReg; + base->OPD = config->pauseDuration; + reemReg = ENET_RSEM_RX_SECTION_EMPTY(config->rxFifoEmptyThreshold); +#if defined (FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD + reemReg |= ENET_RSEM_STAT_SECTION_EMPTY(config->rxFifoStatEmptyThreshold); +#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ + base->RSEM = reemReg; + } + + /* FIFO threshold setting for store and forward enable/disable case. */ + if (macSpecialConfig & kENET_ControlStoreAndFwdDisable) + { + /* Transmit fifo watermark settings. */ + base->TFWR = config->txFifoWatermark & ENET_TFWR_TFWR_MASK; + /* Receive fifo full threshold settings. */ + base->RSFL = config->rxFifoFullThreshold & ENET_RSFL_RX_SECTION_FULL_MASK; + } + else + { + /* Transmit fifo watermark settings. */ + base->TFWR = ENET_TFWR_STRFWD_MASK; + base->RSFL = 0; + } + + /* Enable store and forward when accelerator is enabled */ + if (config->txAccelerConfig & (kENET_TxAccelIpCheckEnabled | kENET_TxAccelProtoCheckEnabled)) + { + base->TFWR = ENET_TFWR_STRFWD_MASK; + } + if (config->rxAccelerConfig & (kENET_RxAccelIpCheckEnabled | kENET_RxAccelProtoCheckEnabled)) + { + base->RSFL = 0; + } + + /* Initializes transmit buffer descriptor rings start address, two start address should be aligned. */ + base->TDSR = (uint32_t)bufferConfig->txPhyBdStartAddrAlign; + base->RDSR = (uint32_t)bufferConfig->rxPhyBdStartAddrAlign; + + /* Initializes the maximum buffer size, the buffer size should be aligned. */ + + base->MRBR = ENET_MRBR_R_BUF_SIZE(bufferConfig->rxBuffSizeAlign); + + /* Configures the Mac address. */ + ENET_SetMacAddr(base, macAddr); + + /* Initialize the SMI if uninitialized. */ + if (!ENET_GetSMI(base)) + { + ENET_SetSMI(base, srcClock_Hz, !!(config->macSpecialConfig & kENET_ControlSMIPreambleDisable)); + } + +/* Enables Ethernet interrupt and NVIC. */ +#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE + if (config->intCoalesceCfg) + { + uint32_t intMask = (ENET_EIMR_TXB_MASK | ENET_EIMR_RXB_MASK); + + /* Clear all buffer interrupts. */ + base->EIMR &= ~intMask; + + /* Set the interrupt coalescence. */ + base->TXIC = ENET_TXIC_ICFT(config->intCoalesceCfg->txCoalesceFrameCount[0]) | + config->intCoalesceCfg->txCoalesceTimeCount[0] | ENET_TXIC_ICCS_MASK | ENET_TXIC_ICEN_MASK; + base->RXIC = ENET_RXIC_ICFT(config->intCoalesceCfg->rxCoalesceFrameCount[0]) | + config->intCoalesceCfg->rxCoalesceTimeCount[0] | ENET_RXIC_ICCS_MASK | ENET_RXIC_ICEN_MASK; + } +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ + ENET_EnableInterrupts(base, config->interrupt); + + /* ENET control register setting. */ + ecr = base->ECR; + + /* Enables Ethernet module after all configuration except the buffer descriptor active. */ + ecr |= ENET_ECR_ETHEREN_MASK | ENET_ECR_DBSWP_MASK; + base->ECR = ecr; +} + +static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartAlign, + uint8_t *txBuffStartAlign, + uint32_t txBuffSizeAlign, + uint32_t txBdNumber) +{ + RT_ASSERT(txBdStartAlign); + RT_ASSERT(txBuffStartAlign); + uint32_t count; + volatile enet_tx_bd_struct_t *curBuffDescrip = txBdStartAlign; + for (count = 0; count < txBdNumber; count++) + { + + /* Set data buffer address. */ + curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffStartAlign[count * txBuffSizeAlign]); + /* Initializes data length. */ + curBuffDescrip->length = 0; + /* Sets the crc. */ + curBuffDescrip->control = (ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK); + /* Sets the last buffer descriptor with the wrap flag. */ + if (count == txBdNumber - 1) + { + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_WRAP_MASK; + } + + /* Add cache clean operation. */ + rt_hw_cpu_dcache_clean((void *)curBuffDescrip, sizeof(enet_tx_bd_struct_t)); + /* Increase the index. */ + curBuffDescrip++; + } +} + +static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartAlign, + uint8_t *rxBuffStartAlign, + uint32_t rxBuffSizeAlign, + uint32_t rxBdNumber, + bool enableInterrupt) +{ + RT_ASSERT(rxBdStartAlign); + RT_ASSERT(rxBuffStartAlign); + + volatile enet_rx_bd_struct_t *curBuffDescrip = rxBdStartAlign; + uint32_t count = 0; + + /* Initializes receive buffer descriptors. */ + for (count = 0; count < rxBdNumber; count++) + { + /* Set data buffer and the length. */ + curBuffDescrip->buffer = (uint8_t *)((void *)&rxBuffStartAlign[count * rxBuffSizeAlign]); + curBuffDescrip->length = 0; + /* Initializes the buffer descriptors with empty bit. */ + curBuffDescrip->control = ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + /* Sets the last buffer descriptor with the wrap flag. */ + if (count == rxBdNumber - 1) + { + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; + } + /* Add cache clean operation. */ + rt_hw_cpu_dcache_clean((void *)curBuffDescrip, sizeof(enet_rx_bd_struct_t)); + /* Increase the index. */ + curBuffDescrip++; + } +} + +void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex) +{ + uint32_t rcr = base->RCR; + uint32_t tcr = base->TCR; + /* Sets speed mode. */ + if (kENET_MiiSpeed10M == speed) + { + rcr |= ENET_RCR_RMII_10T_MASK; + } + else + { + rcr &= ~ENET_RCR_RMII_10T_MASK; + } + /* Set duplex mode. */ + if (duplex == kENET_MiiHalfDuplex) + { + rcr |= ENET_RCR_DRT_MASK; + tcr &= ~ENET_TCR_FDEN_MASK; + } + else + { + rcr &= ~ENET_RCR_DRT_MASK; + tcr |= ENET_TCR_FDEN_MASK; + } + + base->RCR = rcr; + base->TCR = tcr; +} + +void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr) +{ + uint32_t address; + + /* Set physical address lower register. */ + address = (uint32_t)(((uint32_t)macAddr[0] << 24U) | ((uint32_t)macAddr[1] << 16U) | ((uint32_t)macAddr[2] << 8U) | + (uint32_t)macAddr[3]); + base->PALR = address; + /* Set physical address high register. */ + address = (uint32_t)(((uint32_t)macAddr[4] << 8U) | ((uint32_t)macAddr[5])); + base->PAUR = address << ENET_PAUR_PADDR2_SHIFT; +} + +void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr) +{ + RT_ASSERT(macAddr); + + uint32_t address; + + /* Get from physical address lower register. */ + address = base->PALR; + macAddr[0] = 0xFFU & (address >> 24U); + macAddr[1] = 0xFFU & (address >> 16U); + macAddr[2] = 0xFFU & (address >> 8U); + macAddr[3] = 0xFFU & address; + + /* Get from physical address high register. */ + address = (base->PAUR & ENET_PAUR_PADDR2_MASK) >> ENET_PAUR_PADDR2_SHIFT; + macAddr[4] = 0xFFU & (address >> 8U); + macAddr[5] = 0xFFU & address; +} + +void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled) +{ + RT_ASSERT(srcClock_Hz); + + uint32_t clkCycle = 0; + uint32_t speed = 0; + uint32_t mscr = 0; + + /* Calculate the MII speed which controls the frequency of the MDC. */ + speed = srcClock_Hz / (2 * ENET_MDC_FREQUENCY); + /* Calculate the hold time on the MDIO output. */ + clkCycle = (10 + ENET_NANOSECOND_ONE_SECOND / srcClock_Hz - 1) / (ENET_NANOSECOND_ONE_SECOND / srcClock_Hz) - 1; + /* Build the configuration for MDC/MDIO control. */ + mscr = ENET_MSCR_MII_SPEED(speed) | ENET_MSCR_DIS_PRE(isPreambleDisabled) | ENET_MSCR_HOLDTIME(clkCycle); + base->MSCR = mscr; +} + +void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data) +{ + uint32_t mmfr = 0; + + /* Build MII write command. */ + mmfr = ENET_MMFR_ST(1) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg) | ENET_MMFR_TA(2) | + (data & 0xFFFF); + base->MMFR = mmfr; +} + +void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation) +{ + uint32_t mmfr = 0; + + /* Build MII read command. */ + mmfr = ENET_MMFR_ST(1) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg) | ENET_MMFR_TA(2); + base->MMFR = mmfr; +} + +#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) +{ + uint32_t mmfr = 0; + + /* Parse the address from the input register. */ + uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU; + uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU); + + /* Address write firstly. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); + base->MMFR = mmfr; + + /* Build MII write command. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiWriteFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(data); + base->MMFR = mmfr; +} + +void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg) +{ + uint32_t mmfr = 0; + + /* Parse the address from the input register. */ + uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU; + uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU); + + /* Address write firstly. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); + base->MMFR = mmfr; + + /* Build MII read command. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiReadFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2); + base->MMFR = mmfr; +} +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) +{ + RT_ASSERT(handle); + RT_ASSERT(handle->rxBdCurrent); + RT_ASSERT(eErrorStatic); + + uint16_t control = 0; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent; + + do + { + /* Add the cache invalidate maintain. */ + rt_hw_cpu_dcache_invalidate((void *)curBuffDescrip, sizeof(enet_rx_bd_struct_t)); + + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + control = curBuffDescrip->control; + if (control & ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK) + { + /* The receive truncate error. */ + eErrorStatic->statsRxTruncateErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK) + { + /* The receive over run error. */ + eErrorStatic->statsRxOverRunErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK) + { + /* The receive length violation error. */ + eErrorStatic->statsRxLenGreaterErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK) + { + /* The receive alignment error. */ + eErrorStatic->statsRxAlignErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_CRC_MASK) + { + /* The receive CRC error. */ + eErrorStatic->statsRxFcsErr++; + } + break; + } + + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase; + } + else + { + curBuffDescrip++; + } + + } while (curBuffDescrip != handle->rxBdCurrent); +} + +status_t ENET_ReadFrame(ENET_Type *base,enet_handle_t *handle,const enet_config_t *config,uint8_t *data,uint16_t *length) +{ + RT_ASSERT(handle); + RT_ASSERT(handle->rxBdCurrent); + RT_ASSERT(length); + + /* Reset the length to zero. */ + *length = 0; + + uint16_t validLastMask = ENET_BUFFDESCRIPTOR_RX_LAST_MASK | ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent; + + rt_hw_cpu_dcache_invalidate((void *)physical_to_virtual(curBuffDescrip->buffer), handle->rxBuffSizeAlign); + + /* Check the current buffer descriptor's empty flag. if empty means there is no frame received. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK) + { + return kStatus_ENET_RxFrameEmpty; + } + else + { + if ((curBuffDescrip->control & validLastMask) == ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + if(curBuffDescrip->length <= config->rxMaxFrameLen) + { + *length = curBuffDescrip->length; + + memcpy(data, physical_to_virtual(curBuffDescrip->buffer),curBuffDescrip->length); + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle); + return kStatus_Success; + } + else + { + LOG_E("frame error0 curBuffDescrip->control 0x%04x length %d\n",curBuffDescrip->control,curBuffDescrip->length); + *length = curBuffDescrip->length; + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle); + return kStatus_ENET_RxFrameError; + } + } + else + { + LOG_E("frame error1 curBuffDescrip->control 0x%04x length %d\n",curBuffDescrip->control,curBuffDescrip->length); + *length = curBuffDescrip->length; + ENET_UpdateReadBuffers(base, handle); + return kStatus_ENET_RxFrameError; + } + } + /* The frame is on processing - set to empty status to make application to receive it next time. */ + return kStatus_ENET_RxFrameEmpty; +} + +static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle) +{ + RT_ASSERT(handle); + + /* Clears status. */ + handle->rxBdCurrent->control &= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; + /* Sets the receive buffer descriptor with the empty flag. */ + handle->rxBdCurrent->control |= ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + /* Increase current buffer descriptor to the next one. */ + if (handle->rxBdCurrent->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + handle->rxBdCurrent = handle->rxBdBase; + } + else + { + handle->rxBdCurrent++; + } + /* Actives the receive buffer descriptor. */ + base->RDAR = ENET_RDAR_RDAR_MASK; +} + +status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint16_t length,uint32_t last_flag) +{ + RT_ASSERT(handle); + RT_ASSERT(handle->txBdCurrent); + RT_ASSERT(data); + RT_ASSERT(length <= ENET_FRAME_MAX_FRAMELEN); + + volatile enet_tx_bd_struct_t *curBuffDescrip = handle->txBdCurrent; + /* Check if the transmit buffer is ready. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + /* One transmit buffer is enough for one frame. */ + if (handle->txBuffSizeAlign >= length) + { + /* Copy data to the buffer for uDMA transfer. */ + memcpy(physical_to_virtual(curBuffDescrip->buffer), data, length); + /* Set data length. */ + curBuffDescrip->length = length; + if(last_flag) + { + curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); + } + else + { + curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; + } + + rt_hw_cpu_dcache_clean((void *)physical_to_virtual(curBuffDescrip->buffer),length); + /* Active the transmit buffer descriptor. */ + + base->TDAR = ENET_TDAR_TDAR_MASK; + /* Increase the buffer descriptor address. */ + while((base->TDAR != 0)) + { + } + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent = handle->txBdBase; + } + else + { + handle->txBdCurrent++; + } + return kStatus_Success; + } + else + { + return kStatus_ENET_RxFrameError; + } +} + +void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address) +{ + RT_ASSERT(address); + + uint32_t crc = 0xFFFFFFFFU; + uint32_t count1 = 0; + uint32_t count2 = 0; + + /* Calculates the CRC-32 polynomial on the multicast group address. */ + for (count1 = 0; count1 < ENET_FRAME_MACLEN; count1++) + { + uint8_t c = address[count1]; + for (count2 = 0; count2 < 0x08U; count2++) + { + if ((c ^ crc) & 1U) + { + crc >>= 1U; + c >>= 1U; + crc ^= 0xEDB88320U; + } + else + { + crc >>= 1U; + c >>= 1U; + } + } + } + + /* Enable a multicast group address. */ + if (!((crc >> 0x1FU) & 1U)) + { + base->GALR |= 1U << ((crc >> 0x1AU) & 0x1FU); + } + else + { + base->GAUR |= 1U << ((crc >> 0x1AU) & 0x1FU); + } +} + +void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address) +{ + RT_ASSERT(address); + + uint32_t crc = 0xFFFFFFFFU; + uint32_t count1 = 0; + uint32_t count2 = 0; + + /* Calculates the CRC-32 polynomial on the multicast group address. */ + for (count1 = 0; count1 < ENET_FRAME_MACLEN; count1++) + { + uint8_t c = address[count1]; + for (count2 = 0; count2 < 0x08U; count2++) + { + if ((c ^ crc) & 1U) + { + crc >>= 1U; + c >>= 1U; + crc ^= 0xEDB88320U; + } + else + { + crc >>= 1U; + c >>= 1U; + } + } + } + + /* Set the hash table. */ + if (!((crc >> 0x1FU) & 1U)) + { + base->GALR &= ~(1U << ((crc >> 0x1AU) & 0x1FU)); + } + else + { + base->GAUR &= ~(1U << ((crc >> 0x1AU) & 0x1FU)); + } +} +void tx_enet_callback(); +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + RT_ASSERT(handle); + /* Check if the transmit interrupt happen. */ + if((kENET_TxBufferInterrupt | kENET_TxFrameInterrupt) & base->EIR) + { + /* Clear the transmit interrupt event. */ + base->EIR = kENET_TxFrameInterrupt | kENET_TxBufferInterrupt; + } + tx_enet_callback(); +} +void rx_enet_callback(); +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + RT_ASSERT(handle); + + /* Check if the receive interrupt happen. */ + if((kENET_RxBufferInterrupt | kENET_RxFrameInterrupt) & base->EIR) + { + /* Clear the transmit interrupt event. */ + base->EIR = kENET_RxFrameInterrupt | kENET_RxBufferInterrupt; + rx_enet_callback(); + } +} +void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + RT_ASSERT(handle); + + uint32_t errMask = kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_PayloadRxInterrupt | + kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt; + /* Check if the error interrupt happen. */ + if (kENET_WakeupInterrupt & base->EIR) + { + /* Clear the wakeup interrupt. */ + base->EIR = kENET_WakeupInterrupt; + /* wake up and enter the normal mode. */ + ENET_EnableSleepMode(base, false); + /* Callback function. */ + if (handle->callback) + { + handle->callback(base, handle, kENET_WakeUpEvent, handle->userData); + } + } + else + { + /* Clear the error interrupt event status. */ + errMask &= base->EIR; + base->EIR = errMask; + /* Callback function. */ + if (handle->callback) + { + handle->callback(base, handle, kENET_ErrEvent, handle->userData); + } + } +} + +void ENET_CommonFrame0IRQHandler(ENET_Type *base) +{ + uint32_t event = base->EIR; + uint32_t instance = ENET_GetInstance(IMX6UL_ENET); + + if(base->EIMR & ENET_TX_INTERRUPT) + { + if (event & ENET_TX_INTERRUPT) + { + if(s_enetTxIsr) + { + s_enetTxIsr(base, s_ENETHandle[instance]); + } + } + } + if (base->EIMR & ENET_RX_INTERRUPT) + { + if (event & ENET_RX_INTERRUPT) + { + if(s_enetRxIsr) + { + s_enetRxIsr(base, s_ENETHandle[instance]); + } + } + } + if(base->EIMR & ENET_TS_INTERRUPT) + { + if (event & ENET_TS_INTERRUPT) + { + if(s_enetTsIsr) + { + s_enetTsIsr(base, s_ENETHandle[instance]); + } + } + } + if(base->EIMR & ENET_ERR_INTERRUPT) + { + if (event & ENET_ERR_INTERRUPT) + { + if(s_enetErrIsr) + { + s_enetErrIsr(base, s_ENETHandle[instance]); + } + } + } + +} +void ENET_DriverIRQHandler(int irq, void *base) +{ + ENET_CommonFrame0IRQHandler((ENET_Type *)base); +} + +static inline void RT_IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + void *muxRegisterVir = (void *)rt_ioremap((void *)muxRegister,0x1000); + *((volatile uint32_t *)muxRegisterVir) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + void *inputRegisterVir = (void *)rt_ioremap((void *)inputRegister,0x1000); + *((volatile uint32_t *)inputRegisterVir) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } + +} + +static inline void RT_IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + void *configRegisterVir = (void *)rt_ioremap((void *)configRegister,0x1000); + *((volatile uint32_t *)configRegisterVir) = configValue; + } + +} + +void ENET_InitPins(void) +{ + rt_uint32_t reg_value; + #ifdef BSP_USING_IMX6ULL_ART_PI + RT_IOMUXC_SetPinMux(IOMUXC_SNVS_SNVS_TAMPER9_GPIO5_IO09, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_SNVS_SNVS_TAMPER9_GPIO5_IO09, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET1_RX_DATA0_ENET1_RDATA00, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET1_RX_DATA0_ENET1_RDATA00, 0xB0E9); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET1_RX_DATA1_ENET1_RDATA01, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET1_RX_DATA1_ENET1_RDATA01, 0xB0E9); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET1_RX_EN_ENET1_RX_EN, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET1_RX_EN_ENET1_RX_EN, 0xB0E9); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET1_RX_ER_ENET1_RX_ER, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET1_RX_ER_ENET1_RX_ER, 0xB0E9); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET1_TX_CLK_ENET1_REF_CLK1, 1U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET1_TX_CLK_ENET1_REF_CLK1, 0x0031); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET1_TX_DATA0_ENET1_TDATA00, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET1_TX_DATA0_ENET1_TDATA00, 0xB0E9); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET1_TX_DATA1_ENET1_TDATA01, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET1_TX_DATA1_ENET1_TDATA01, 0xB0E9); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET1_TX_EN_ENET1_TX_EN, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET1_TX_EN_ENET1_TX_EN, 0xB0E9); + + RT_IOMUXC_SetPinMux(IOMUXC_GPIO1_IO06_ENET1_MDIO, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO06_ENET1_MDIO, 0xB829); + + RT_IOMUXC_SetPinMux(IOMUXC_GPIO1_IO07_ENET1_MDC, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO07_ENET1_MDC, 0xB0E9); + + IOMUXC_GPR_Type *GPR1 = (IOMUXC_GPR_Type *)rt_ioremap((void *)IOMUXC_GPR,0x1000); + reg_value = GPR1->GPR1; + reg_value &= ~(IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK + | IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK); + reg_value |= IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(1); + reg_value |= IOMUXC_GPR_GPR1_ENET1_CLK_SEL(0); + GPR1->GPR1 = reg_value; + #endif + + #ifdef BSP_USING_IMX6ULL_POR + RT_IOMUXC_SetPinMux(IOMUXC_SNVS_SNVS_TAMPER6_GPIO5_IO06, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_SNVS_SNVS_TAMPER6_GPIO5_IO06, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET2_RX_DATA0_ENET2_RDATA00, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET2_RX_DATA0_ENET2_RDATA00, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(5U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(3U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(2U)); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET2_RX_DATA1_ENET2_RDATA01, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET2_RX_DATA1_ENET2_RDATA01, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(5U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(3U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(2U)); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET2_RX_EN_ENET2_RX_EN, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET2_RX_EN_ENET2_RX_EN, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(5U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(3U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(2U)); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET2_RX_ER_ENET2_RX_ER, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET2_RX_ER_ENET2_RX_ER, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(5U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(3U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(2U)); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET2_TX_CLK_ENET2_REF_CLK2, 1U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET2_TX_CLK_ENET2_REF_CLK2, + IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(3U)); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET2_TX_DATA0_ENET2_TDATA00, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET2_TX_DATA0_ENET2_TDATA00, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(5U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(3U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(2U)); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET2_TX_DATA1_ENET2_TDATA01, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET2_TX_DATA1_ENET2_TDATA01, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(5U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(3U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(2U)); + + RT_IOMUXC_SetPinMux(IOMUXC_ENET2_TX_EN_ENET2_TX_EN, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_ENET2_TX_EN_ENET2_TX_EN, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(5U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(3U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(2U)); + + RT_IOMUXC_SetPinMux(IOMUXC_GPIO1_IO04_ENET2_1588_EVENT0_IN, 0U); + + RT_IOMUXC_SetPinMux(IOMUXC_GPIO1_IO05_ENET2_1588_EVENT0_OUT, 0U); + + RT_IOMUXC_SetPinMux(IOMUXC_GPIO1_IO06_ENET2_MDIO, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO06_ENET2_MDIO, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(5U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(2U)); + + RT_IOMUXC_SetPinMux(IOMUXC_GPIO1_IO07_ENET2_MDC, 0U); + RT_IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO07_ENET2_MDC, + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_DSE(5U) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(3U) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(2U)); + IOMUXC_GPR_Type *GPR1 = (IOMUXC_GPR_Type *)rt_ioremap((void *)IOMUXC_GPR,0x1000); + reg_value = GPR1->GPR1; + reg_value &= ~(IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK + | IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK); + reg_value |= IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR(1); + reg_value |= IOMUXC_GPR_GPR1_ENET2_CLK_SEL(0); + GPR1->GPR1 = reg_value; + #endif + +} + + diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_enet.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_enet.h new file mode 100644 index 0000000000..95740c85e8 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_enet.h @@ -0,0 +1,1355 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_ENET_H_ +#define _FSL_ENET_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup enet + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BSP_USING_IMX6ULL_ART_PI + +#define ENET_PHY2 0x01U +#define ENET_PHY1 0x0U + +#ifdef BSP_USING_IMX6ULL_ART_PI +#define ENET_PHY ENET_PHY1 +#define IMX6UL_ENET ENET1 +#define IMX_INT_ENET IMX_INT_ENET1 +#define ENET_NAME "e1" +#define ENET_IRQ_NAME "emac1_intr" + +#endif + +#ifdef BSP_USING_IMX6ULL_POR +#define ENET_PHY ENET_PHY2 +#define IMX6UL_ENET ENET2 +#define IMX_INT_ENET IMX_INT_ENET2 +#define ENET_NAME "e2" +#define ENET_IRQ_NAME "emac2_intr" +#endif + +#define DETECT_DELAY_ONE_SECOND 1000 +#define ENET_RXBD_NUM (128) +#define ENET_TXBD_NUM (128) + +#define ENET_RXBUFF_ALIGN_SIZE (1536) +#define ENET_TXBUFF_ALIGN_SIZE (1536) + +#define ENET_RXBUFF_TOTAL_SIZE (ENET_RXBD_NUM*ENET_RXBUFF_ALIGN_SIZE) +#define ENET_TXBUFF_TOTAL_SIZE (ENET_TXBD_NUM*ENET_TXBUFF_ALIGN_SIZE) + +#define ENET_RX_MAX_BUFFER_SIZE (65536U) +#define SYS_PAGE_SIZE (4096U) + +#define TX_BUFFER_INDEX_NUM (6) +#define RX_BUFFER_INDEX_NUM (6) + +#define TX_BD_INDEX_NUM (0) +#define RX_BD_INDEX_NUM (0) + +#define SYS_CLOCK_HZ (66000000) + +#define virtual_to_physical(v) ((void *)((size_t)v + PV_OFFSET)) +#define physical_to_virtual(p) ((void *)((size_t)p - PV_OFFSET)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines the driver version. */ +#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */ +/*@}*/ + +/*! @name Control and status region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK 0x8000U /*!< Empty bit mask. */ +#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK 0x4000U /*!< Software owner one mask. */ +#define ENET_BUFFDESCRIPTOR_RX_WRAP_MASK 0x2000U /*!< Next buffer descriptor is the start address. */ +#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask 0x1000U /*!< Software owner two mask. */ +#define ENET_BUFFDESCRIPTOR_RX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MISS_MASK 0x0100U /*!< Received because of the promiscuous mode. */ +#define ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK 0x0080U /*!< Broadcast packet mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK 0x0040U /*!< Multicast packet mask. */ +#define ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK 0x0020U /*!< Length violation mask. */ +#define ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK 0x0010U /*!< Non-octet aligned frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_CRC_MASK 0x0004U /*!< CRC error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK 0x0002U /*!< FIFO overrun mask. */ +#define ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK 0x0001U /*!< Frame is truncated mask. */ +/*@}*/ + +/*! @name Control and status bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_READY_MASK 0x8000U /*!< Ready bit mask. */ +#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK 0x4000U /*!< Software owner one mask. */ +#define ENET_BUFFDESCRIPTOR_TX_WRAP_MASK 0x2000U /*!< Wrap buffer descriptor mask. */ +#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK 0x1000U /*!< Software owner two mask. */ +#define ENET_BUFFDESCRIPTOR_TX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK 0x0400U /*!< Transmit CRC mask. */ +/*@}*/ + +/* Extended control regions for enhanced buffer descriptors. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @name First extended control region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_IPV4_MASK 0x0001U /*!< Ipv4 frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_IPV6_MASK 0x0002U /*!< Ipv6 frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_VLAN_MASK 0x0004U /*!< VLAN frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_PROTOCOLCHECKSUM_MASK 0x0010U /*!< Protocol checksum error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_IPHEADCHECKSUM_MASK 0x0020U /*!< IP header checksum error mask. */ +/*@}*/ + +/*! @name Second extended control region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK 0x0080U /*!< BD interrupt mask. */ +#define ENET_BUFFDESCRIPTOR_RX_UNICAST_MASK 0x0100U /*!< Unicast frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK 0x0200U /*!< BD collision mask. */ +#define ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK 0x0400U /*!< PHY error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MACERR_MASK 0x8000U /*!< Mac error mask. */ +/*@}*/ + +/*! @name First extended control region bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_ERR_MASK 0x8000U /*!< Transmit error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK 0x2000U /*!< Underflow error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK 0x1000U /*!< Excess collision error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_FRAMEERR_MASK 0x0800U /*!< Frame error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK 0x0400U /*!< Late collision error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK 0x0200U /*!< Overflow error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMPERR_MASK 0x0100U /*!< Timestamp error mask. */ +/*@}*/ + +/*! @name Second extended control region bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK 0x4000U /*!< Interrupt mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK 0x2000U /*!< Timestamp flag mask. */ +/*@}*/ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! @brief Defines the receive error status flag mask. */ +#define ENET_BUFFDESCRIPTOR_RX_ERR_MASK \ + (ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK | \ + ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK | ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK | ENET_BUFFDESCRIPTOR_RX_CRC_MASK) +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +#define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \ + (ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) +#endif +#define ENET_TX_INTERRUPT (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt) +#define ENET_RX_INTERRUPT (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt) +#define ENET_TS_INTERRUPT (kENET_TsTimerInterrupt | kENET_TsAvailInterrupt) +#define ENET_ERR_INTERRUPT (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | \ + kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt) + + +/*! @name Defines the maximum Ethernet frame size. */ +/*@{*/ +#define ENET_FRAME_MAX_FRAMELEN 1518U /*!< Default maximum Ethernet frame size. */ +/*@}*/ + +#define ENET_FIFO_MIN_RX_FULL 5U /*!< ENET minimum receive FIFO full. */ +#define ENET_RX_MIN_BUFFERSIZE 256U /*!< ENET minimum buffer size. */ + +/*! @brief Defines the PHY address scope for the ENET. */ +#define ENET_PHY_MAXADDRESS (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT) + +/*! @brief Defines the status return codes for transaction. */ +enum _enet_status +{ + kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 0U), /*!< A frame received but data error happen. */ + kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 1U), /*!< Failed to receive a frame. */ + kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 2U), /*!< No frame arrive. */ + kStatus_ENET_TxFrameBusy = + MAKE_STATUS(kStatusGroup_ENET, 3U), /*!< Transmit buffer descriptors are under process. */ + kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 4U) /*!< Transmit frame fail. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + , + kStatus_ENET_PtpTsRingFull = MAKE_STATUS(kStatusGroup_ENET, 5U), /*!< Timestamp ring full. */ + kStatus_ENET_PtpTsRingEmpty = MAKE_STATUS(kStatusGroup_ENET, 6U) /*!< Timestamp ring empty. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +}; + +/*! @brief Defines the RMII or MII mode for data interface between the MAC and the PHY. */ +typedef enum _enet_mii_mode +{ + kENET_MiiMode = 0U, /*!< MII mode for data interface. */ + kENET_RmiiMode /*!< RMII mode for data interface. */ +} enet_mii_mode_t; + +/*! @brief Defines the 10 Mbps or 100 Mbps speed for the MII data interface. */ +typedef enum _enet_mii_speed +{ + kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */ + kENET_MiiSpeed100M /*!< Speed 100 Mbps. */ +} enet_mii_speed_t; + +/*! @brief Defines the half or full duplex for the MII data interface. */ +typedef enum _enet_mii_duplex +{ + kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */ + kENET_MiiFullDuplex /*!< Full duplex mode. */ +} enet_mii_duplex_t; + +/*! @brief Defines the write operation for the MII management frame. */ +typedef enum _enet_mii_write +{ + kENET_MiiWriteNoCompliant = 0U, /*!< Write frame operation, but not MII-compliant. */ + kENET_MiiWriteValidFrame /*!< Write frame operation for a valid MII management frame. */ +} enet_mii_write_t; + +/*! @brief Defines the read operation for the MII management frame. */ +typedef enum _enet_mii_read +{ + kENET_MiiReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame. */ + kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */ +} enet_mii_read_t; + +#if defined (FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +/*! @brief Define the MII opcode for extended MDIO_CLAUSES_45 Frame. */ +typedef enum _enet_mii_extend_opcode { + kENET_MiiAddrWrite_C45 = 0U, /*!< Address Write operation. */ + kENET_MiiWriteFrame_C45 = 1U, /*!< Write frame operation for a valid MII management frame. */ + kENET_MiiReadFrame_C45 = 3U /*!< Read frame operation for a valid MII management frame. */ +} enet_mii_extend_opcode; +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +/*! @brief Defines a special configuration for ENET MAC controller. + * + * These control flags are provided for special user requirements. + * Normally, these control flags are unused for ENET initialization. + * For special requirements, set the flags to + * macSpecialConfig in the enet_config_t. + * The kENET_ControlStoreAndFwdDisable is used to disable the FIFO store + * and forward. FIFO store and forward means that the FIFO read/send is started + * when a complete frame is stored in TX/RX FIFO. If this flag is set, + * configure rxFifoFullThreshold and txFifoWatermark + * in the enet_config_t. + */ +typedef enum _enet_special_control_flag +{ + kENET_ControlFlowControlEnable = 0x0001U, /*!< Enable ENET flow control: pause frame. */ + kENET_ControlRxPayloadCheckEnable = 0x0002U, /*!< Enable ENET receive payload length check. */ + kENET_ControlRxPadRemoveEnable = 0x0004U, /*!< Padding is removed from received frames. */ + kENET_ControlRxBroadCastRejectEnable = 0x0008U, /*!< Enable broadcast frame reject. */ + kENET_ControlMacAddrInsert = 0x0010U, /*!< Enable MAC address insert. */ + kENET_ControlStoreAndFwdDisable = 0x0020U, /*!< Enable FIFO store and forward. */ + kENET_ControlSMIPreambleDisable = 0x0040U, /*!< Enable SMI preamble. */ + kENET_ControlPromiscuousEnable = 0x0080U, /*!< Enable promiscuous mode. */ + kENET_ControlMIILoopEnable = 0x0100U, /*!< Enable ENET MII loop back. */ + kENET_ControlVLANTagEnable = 0x0200U /*!< Enable VLAN tag frame. */ +} enet_special_control_flag_t; + +/*! @brief List of interrupts supported by the peripheral. This + * enumeration uses one-bot encoding to allow a logical OR of multiple + * members. Members usually map to interrupt enable bits in one or more + * peripheral registers. + */ +typedef enum _enet_interrupt_enable +{ + kENET_BabrInterrupt = ENET_EIR_BABR_MASK, /*!< Babbling receive error interrupt source */ + kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */ + kENET_GraceStopInterrupt = ENET_EIR_GRA_MASK, /*!< Graceful stop complete interrupt source */ + kENET_TxFrameInterrupt = ENET_EIR_TXF_MASK, /*!< TX FRAME interrupt source */ + kENET_TxBufferInterrupt = ENET_EIR_TXB_MASK, /*!< TX BUFFER interrupt source */ + kENET_RxFrameInterrupt = ENET_EIR_RXF_MASK, /*!< RX FRAME interrupt source */ + kENET_RxBufferInterrupt = ENET_EIR_RXB_MASK, /*!< RX BUFFER interrupt source */ + kENET_MiiInterrupt = ENET_EIR_MII_MASK, /*!< MII interrupt source */ + kENET_EBusERInterrupt = ENET_EIR_EBERR_MASK, /*!< Ethernet bus error interrupt source */ + kENET_LateCollisionInterrupt = ENET_EIR_LC_MASK, /*!< Late collision interrupt source */ + kENET_RetryLimitInterrupt = ENET_EIR_RL_MASK, /*!< Collision Retry Limit interrupt source */ + kENET_UnderrunInterrupt = ENET_EIR_UN_MASK, /*!< Transmit FIFO underrun interrupt source */ + kENET_PayloadRxInterrupt = ENET_EIR_PLR_MASK, /*!< Payload Receive interrupt source */ + kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK, /*!< WAKEUP interrupt source */ + kENET_TsAvailInterrupt = ENET_EIR_TS_AVAIL_MASK, /*!< TS AVAIL interrupt source for PTP */ + kENET_TsTimerInterrupt = ENET_EIR_TS_TIMER_MASK /*!< TS WRAP interrupt source for PTP */ +} enet_interrupt_enable_t; + +/*! @brief Defines the common interrupt event for callback use. */ +typedef enum _enet_event +{ + kENET_RxEvent, /*!< Receive event. */ + kENET_TxEvent, /*!< Transmit event. */ + kENET_ErrEvent, /*!< Error event: BABR/BABT/EBERR/LC/RL/UN/PLR . */ + kENET_WakeUpEvent, /*!< Wake up from sleep mode event. */ + kENET_TimeStampEvent, /*!< Time stamp event. */ + kENET_TimeStampAvailEvent /*!< Time stamp available event.*/ +} enet_event_t; + +/*! @brief Defines the transmit accelerator configuration. */ +typedef enum _enet_tx_accelerator +{ + kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK, /*!< Transmit FIFO shift-16. */ + kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK, /*!< Insert IP header checksum. */ + kENET_TxAccelProtoCheckEnabled = ENET_TACC_PROCHK_MASK /*!< Insert protocol checksum. */ +} enet_tx_accelerator_t; + +/*! @brief Defines the receive accelerator configuration. */ +typedef enum _enet_rx_accelerator +{ + kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK, /*!< Padding removal for short IP frames. */ + kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK, /*!< Discard with wrong IP header checksum. */ + kENET_RxAccelProtoCheckEnabled = ENET_RACC_PRODIS_MASK, /*!< Discard with wrong protocol checksum. */ + kENET_RxAccelMacCheckEnabled = ENET_RACC_LINEDIS_MASK, /*!< Discard with Mac layer errors. */ + kENET_RxAccelisShift16Enabled = ENET_RACC_SHIFT16_MASK /*!< Receive FIFO shift-16. */ +} enet_rx_accelerator_t; + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Defines the ENET PTP message related constant. */ +typedef enum _enet_ptp_event_type +{ + kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */ + kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */ + kENET_PtpEventPort = 319U, /*!< PTP event port number. */ + kENET_PtpGnrlPort = 320U /*!< PTP general port number. */ +} enet_ptp_event_type_t; + +/*! @brief Defines the IEEE 1588 PTP timer channel numbers. */ +typedef enum _enet_ptp_timer_channel +{ + kENET_PtpTimerChannel1 = 0U, /*!< IEEE 1588 PTP timer Channel 1. */ + kENET_PtpTimerChannel2, /*!< IEEE 1588 PTP timer Channel 2. */ + kENET_PtpTimerChannel3, /*!< IEEE 1588 PTP timer Channel 3. */ + kENET_PtpTimerChannel4 /*!< IEEE 1588 PTP timer Channel 4. */ +} enet_ptp_timer_channel_t; + +/*! @brief Defines the capture or compare mode for IEEE 1588 PTP timer channels. */ +typedef enum _enet_ptp_timer_channel_mode +{ + kENET_PtpChannelDisable = 0U, /*!< Disable timer channel. */ + kENET_PtpChannelRisingCapture = 1U, /*!< Input capture on rising edge. */ + kENET_PtpChannelFallingCapture = 2U, /*!< Input capture on falling edge. */ + kENET_PtpChannelBothCapture = 3U, /*!< Input capture on both edges. */ + kENET_PtpChannelSoftCompare = 4U, /*!< Output compare software only. */ + kENET_PtpChannelToggleCompare = 5U, /*!< Toggle output on compare. */ + kENET_PtpChannelClearCompare = 6U, /*!< Clear output on compare. */ + kENET_PtpChannelSetCompare = 7U, /*!< Set output on compare. */ + kENET_PtpChannelClearCompareSetOverflow = 10U, /*!< Clear output on compare, set output on overflow. */ + kENET_PtpChannelSetCompareClearOverflow = 11U, /*!< Set output on compare, clear output on overflow. */ + kENET_PtpChannelPulseLowonCompare = 14U, /*!< Pulse output low on compare for one IEEE 1588 clock cycle. */ + kENET_PtpChannelPulseHighonCompare = 15U /*!< Pulse output high on compare for one IEEE 1588 clock cycle. */ +} enet_ptp_timer_channel_mode_t; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! @brief Defines the receive buffer descriptor structure for the little endian system.*/ +typedef struct _enet_rx_bd_struct +{ + uint16_t length; /*!< Buffer descriptor data length. */ + uint16_t control; /*!< Buffer descriptor control and status. */ + uint8_t *buffer; /*!< Data buffer pointer. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ + uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ + uint16_t payloadCheckSum; /*!< Internal payload checksum. */ + uint8_t headerLength; /*!< Header length. */ + uint8_t protocolTyte; /*!< Protocol type. */ + uint16_t reserved0; + uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ + uint32_t timestamp; /*!< Timestamp. */ + uint16_t reserved1; + uint16_t reserved2; + uint16_t reserved3; + uint16_t reserved4; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_rx_bd_struct_t; + +/*! @brief Defines the enhanced transmit buffer descriptor structure for the little endian system. */ +typedef struct _enet_tx_bd_struct +{ + uint16_t length; /*!< Buffer descriptor data length. */ + uint16_t control; /*!< Buffer descriptor control and status. */ + uint8_t *buffer; /*!< Data buffer pointer. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ + uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ + uint16_t reserved0; + uint16_t reserved1; + uint16_t reserved2; + uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ + uint32_t timestamp; /*!< Timestamp. */ + uint16_t reserved3; + uint16_t reserved4; + uint16_t reserved5; + uint16_t reserved6; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_tx_bd_struct_t; + +/*! @brief Defines the ENET data error statistic structure. */ +typedef struct _enet_data_error_stats +{ + uint32_t statsRxLenGreaterErr; /*!< Receive length greater than RCR[MAX_FL]. */ + uint32_t statsRxAlignErr; /*!< Receive non-octet alignment/ */ + uint32_t statsRxFcsErr; /*!< Receive CRC error. */ + uint32_t statsRxOverRunErr; /*!< Receive over run. */ + uint32_t statsRxTruncateErr; /*!< Receive truncate. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint32_t statsRxProtocolChecksumErr; /*!< Receive protocol checksum error. */ + uint32_t statsRxIpHeadChecksumErr; /*!< Receive IP header checksum error. */ + uint32_t statsRxMacErr; /*!< Receive Mac error. */ + uint32_t statsRxPhyErr; /*!< Receive PHY error. */ + uint32_t statsRxCollisionErr; /*!< Receive collision. */ + uint32_t statsTxErr; /*!< The error happen when transmit the frame. */ + uint32_t statsTxFrameErr; /*!< The transmit frame is error. */ + uint32_t statsTxOverFlowErr; /*!< Transmit overflow. */ + uint32_t statsTxLateCollisionErr; /*!< Transmit late collision. */ + uint32_t statsTxExcessCollisionErr; /*!< Transmit excess collision.*/ + uint32_t statsTxUnderFlowErr; /*!< Transmit under flow error. */ + uint32_t statsTxTsErr; /*!< Transmit time stamp error. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_data_error_stats_t; + +/*! @brief Defines the receive buffer descriptor configuration structure. + * + * Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements. + * 1. The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT. + * when the data buffers are in cacheable region when cache is enabled, all those size should be + * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. + * 2. The aligned transmit and receive buffer descriptor start address must be at + * least 64 bit aligned. However, it's recommended to be evenly divisible by ENET_BUFF_ALIGNMENT. + * buffer descriptors should be put in non-cacheable region when cache is enabled. + * 3. The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT. + * Receive buffers should be continuous with the total size equal to "rxBdNumber * rxBuffSizeAlign". + * Transmit buffers should be continuous with the total size equal to "txBdNumber * txBuffSizeAlign". + * when the data buffers are in cacheable region when cache is enabled, all those size should be + * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. + */ +typedef struct _enet_buffer_config +{ + uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */ + uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */ + uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ + uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */ + volatile enet_rx_bd_struct_t *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address. */ + volatile enet_tx_bd_struct_t *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address. */ + uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */ + uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */ + void *rxPhyBdStartAddrAlign; /*!< Aligned receive buffer descriptor physical start address. */ + void *txPhyBdStartAddrAlign; /*!< Aligned transmit buffer descriptor physical start address. */ + uint8_t *rxPhyBufferAlign; /*!< Receive data buffer physical start address. */ + uint8_t *txPhyBufferAlign; /*!< Transmit data buffer physical start address. */ + uint32_t rxBufferTotalSize; /*!< Receive data buffer max size. */ + uint32_t txBufferTotalSize; /*!< Transmit data buffer max size. */ +} enet_buffer_config_t; + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Defines the ENET PTP time stamp structure. */ +typedef struct _enet_ptp_time +{ + uint64_t second; /*!< Second. */ + uint32_t nanosecond; /*!< Nanosecond. */ +} enet_ptp_time_t; + +/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/ +typedef struct _enet_ptp_time_data +{ + uint8_t version; /*!< PTP version. */ + uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */ + uint16_t sequenceId; /*!< PTP sequence ID. */ + uint8_t messageType; /*!< PTP message type. */ + enet_ptp_time_t timeStamp; /*!< PTP timestamp. */ +} enet_ptp_time_data_t; + +/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/ +typedef struct _enet_ptp_time_data_ring +{ + uint32_t front; /*!< The first index of the ring. */ + uint32_t end; /*!< The end index of the ring. */ + uint32_t size; /*!< The size of the ring. */ + enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */ +} enet_ptp_time_data_ring_t; + +/*! @brief Defines the ENET PTP configuration structure. */ +typedef struct _enet_ptp_config +{ + uint8_t ptpTsRxBuffNum; /*!< Receive 1588 timestamp buffer number*/ + uint8_t ptpTsTxBuffNum; /*!< Transmit 1588 timestamp buffer number*/ + enet_ptp_time_data_t *rxPtpTsData; /*!< The start address of 1588 receive timestamp buffers */ + enet_ptp_time_data_t *txPtpTsData; /*!< The start address of 1588 transmit timestamp buffers */ + enet_ptp_timer_channel_t channel; /*!< Used for ERRATA_2579: the PTP 1588 timer channel for time interrupt. */ + uint32_t ptp1588ClockSrc_Hz; /*!< The clock source of the PTP 1588 timer. */ +} enet_ptp_config_t; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +#if defined (FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE +/*! @brief Defines the interrupt coalescing configure structure. */ +typedef struct _enet_intcoalesce_config +{ + uint8_t txCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing frame count threshold. */ + uint16_t txCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing timer count threshold. */ + uint8_t rxCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing frame count threshold. */ + uint16_t rxCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing timer count threshold. */ +} enet_intcoalesce_config_t; +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ + +/*! @brief Defines the basic configuration structure for the ENET device. + * + * Note: + * 1. macSpecialConfig is used for a special control configuration, a logical OR of + * "enet_special_control_flag_t". For a special configuration for MAC, + * set this parameter to 0. + * 2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes. + * 0/1 - 64 bytes written to TX FIFO before transmission of a frame begins. + * 2 - 128 bytes written to TX FIFO .... + * 3 - 192 bytes written to TX FIFO .... + * The maximum of txWatermark is 0x2F - 4032 bytes written to TX FIFO. + * txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1 + * or for larger bus access latency 3 or larger due to contention for the system bus. + * 3. rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX. + * It is in 64-bit words. The minimum is ENET_FIFO_MIN_RX_FULL and the maximum is 0xFF. + * If the end of the frame is stored in FIFO and the frame size if smaller than the + * txWatermark, the frame is still transmitted. The rule is the + * same for rxFifoFullThreshold in the receive direction. + * 4. When "kENET_ControlFlowControlEnable" is set in the macSpecialConfig, ensure + * that the pauseDuration, rxFifoEmptyThreshold, and rxFifoStatEmptyThreshold + * are set for flow control enabled case. + * 5. When "kENET_ControlStoreAndFwdDisabled" is set in the macSpecialConfig, ensure + * that the rxFifoFullThreshold and txFifoWatermark are set for store and forward disable. + * 6. The rxAccelerConfig and txAccelerConfig default setting with 0 - accelerator + * are disabled. The "enet_tx_accelerator_t" and "enet_rx_accelerator_t" are + * recommended to be used to enable the transmit and receive accelerator. + * After the accelerators are enabled, the store and forward feature should be enabled. + * As a result, kENET_ControlStoreAndFwdDisabled should not be set. + */ +typedef struct _enet_config +{ + uint32_t macSpecialConfig; /*!< Mac special configuration. A logical OR of "enet_special_control_flag_t". */ + uint32_t interrupt; /*!< Mac interrupt source. A logical OR of "enet_interrupt_enable_t". */ + uint16_t rxMaxFrameLen; /*!< Receive maximum frame length. */ + enet_mii_mode_t miiMode; /*!< MII mode. */ + enet_mii_speed_t miiSpeed; /*!< MII Speed. */ + enet_mii_duplex_t miiDuplex; /*!< MII duplex. */ + uint8_t rxAccelerConfig; /*!< Receive accelerator, A logical OR of "enet_rx_accelerator_t". */ + uint8_t txAccelerConfig; /*!< Transmit accelerator, A logical OR of "enet_rx_accelerator_t". */ + uint16_t pauseDuration; /*!< For flow control enabled case: Pause duration. */ + uint8_t rxFifoEmptyThreshold; /*!< For flow control enabled case: when RX FIFO level reaches this value, + it makes MAC generate XOFF pause frame. */ +#if defined (FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD + uint8_t rxFifoStatEmptyThreshold; /*!< For flow control enabled case: number of frames in the receive FIFO, + independent of size, that can be accept. If the limit is reached, reception + continues and a pause frame is triggered. */ +#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ + uint8_t rxFifoFullThreshold; /*!< For store and forward disable case, the data required in RX FIFO to notify + the MAC receive ready status. */ + uint8_t txFifoWatermark; /*!< For store and forward disable case, the data required in TX FIFO + before a frame transmit start. */ +#if defined (FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE + enet_intcoalesce_config_t *intCoalesceCfg; /* If the interrupt coalsecence is not required in the ring n(0,1,2), please set + to NULL. */ +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ +} enet_config_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _enet_handle enet_handle_t; + +/*! @brief ENET callback function. */ +typedef void (*enet_callback_t)(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData); + +/*! @brief Defines the ENET handler structure. */ +struct _enet_handle +{ + volatile enet_rx_bd_struct_t *rxBdBase; /*!< Receive buffer descriptor base address pointer. */ + volatile enet_rx_bd_struct_t *rxBdCurrent; /*!< The current available receive buffer descriptor pointer. */ + volatile enet_tx_bd_struct_t *txBdBase; /*!< Transmit buffer descriptor base address pointer. */ + volatile enet_tx_bd_struct_t *txBdCurrent; /*!< The current available transmit buffer descriptor pointer. */ + uint32_t rxBuffSizeAlign; /*!< Receive buffer size alignment. */ + uint32_t txBuffSizeAlign; /*!< Transmit buffer size alignment. */ + enet_callback_t callback; /*!< Callback function. */ + void *userData; /*!< Callback function parameter.*/ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + volatile enet_tx_bd_struct_t *txBdDirtyStatic; /*!< The dirty transmit buffer descriptor for error static update. */ + volatile enet_tx_bd_struct_t *txBdDirtyTime; /*!< The dirty transmit buffer descriptor for time stamp update. */ + uint64_t msTimerSecond; /*!< The second for Master PTP timer .*/ + enet_ptp_time_data_ring_t rxPtpTsDataRing; /*!< Receive PTP 1588 time stamp data ring buffer. */ + enet_ptp_time_data_ring_t txPtpTsDataRing; /*!< Transmit PTP 1588 time stamp data ring buffer. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and de-initialization + * @{ + */ + +/*! + * @brief Gets the ENET default configuration structure. + * + * The purpose of this API is to get the default ENET MAC controller + * configuration structure for ENET_Init(). Users may use the initialized + * structure unchanged in ENET_Init() or modify fields of the + * structure before calling ENET_Init(). + * This is an example. + @code + enet_config_t config; + ENET_GetDefaultConfig(&config); + @endcode + * @param config The ENET mac controller configuration structure pointer. + */ +void ENET_GetDefaultConfig(enet_config_t *config); + +/*! + * @brief Initializes the ENET module. + * + * This function ungates the module clock and initializes it with the ENET configuration. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param config ENET Mac configuration structure pointer. + * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig + * can be used directly. It is also possible to verify the Mac configuration using other methods. + * @param bufferConfig ENET buffer configuration structure pointer. + * The buffer configuration should be prepared for ENET Initialization. + * @param macAddr ENET mac address of the Ethernet device. This Mac address should be + * provided. + * @param srcClock_Hz The internal module clock source for MII clock. + * + * @note ENET has two buffer descriptors legacy buffer descriptors and + * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To + * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor + * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() + * to configure the 1588 feature and related buffers after calling ENET_Init(). + */ +void ENET_Init(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz); +/*! + * @brief Deinitializes the ENET module. + + * This function gates the module clock, clears ENET interrupts, and disables the ENET module. + * + * @param base ENET peripheral base address. + */ +void ENET_Deinit(ENET_Type *base); + +/*! + * @brief Resets the ENET module. + * + * This function restores the ENET module to the reset state. + * Note that this function sets all registers to the + * reset state. As a result, the ENET module can't work after calling this function. + * + * @param base ENET peripheral base address. + */ +static inline void ENET_Reset(ENET_Type *base) +{ + base->ECR |= ENET_ECR_RESET_MASK; +} + +/* @} */ + +/*! + * @name MII interface operation + * @{ + */ + +/*! + * @brief Sets the ENET MII speed and duplex. + * + * @param base ENET peripheral base address. + * @param speed The speed of the RMII mode. + * @param duplex The duplex of the RMII mode. + */ +void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex); + +/*! + * @brief Sets the ENET SMI (serial management interface) - MII management interface. + * + * @param base ENET peripheral base address. + * @param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution. + * @param isPreambleDisabled The preamble disable flag. + * - true Enables the preamble. + * - false Disables the preamble. + */ +void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled); + +/*! + * @brief Gets the ENET SMI- MII management interface configuration. + * + * This API is used to get the SMI configuration to check whether the MII management + * interface has been set. + * + * @param base ENET peripheral base address. + * @return The SMI setup status true or false. + */ +static inline bool ENET_GetSMI(ENET_Type *base) +{ + return (0 != (base->MSCR & 0x7E)); +} + +/*! + * @brief Reads data from the PHY register through an SMI interface. + * + * @param base ENET peripheral base address. + * @return The data read from PHY + */ +static inline uint32_t ENET_ReadSMIData(ENET_Type *base) +{ + return (uint32_t)((base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT); +} + +/*! + * @brief Starts an SMI (Serial Management Interface) read command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param operation The read operation. + */ +void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation); + +/*! + * @brief Starts an SMI write command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param operation The write operation. + * @param data The data written to PHY. + */ +void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data); + +#if defined (FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +/*! + * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI read command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + */ +void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg); + +/*! + * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI write command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + * @param data The data written to PHY. + */ +void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +/* @} */ + +/*! + * @name MAC Address Filter + * @{ + */ + +/*! + * @brief Sets the ENET module Mac address. + * + * @param base ENET peripheral base address. + * @param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr); + +/*! + * @brief Gets the ENET module Mac address. + * + * @param base ENET peripheral base address. + * @param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr); + +/*! + * @brief Adds the ENET device to a multicast group. + * + * @param base ENET peripheral base address. + * @param address The six-byte multicast group address which is provided by application. + */ +void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address); + +/*! + * @brief Moves the ENET device from a multicast group. + * + * @param base ENET peripheral base address. + * @param address The six-byte multicast group address which is provided by application. + */ +void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address); + +/* @} */ + +/*! + * @name Other basic operations + * @{ + */ + +/*! + * @brief Activates ENET read or receive. + * + * @param base ENET peripheral base address. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * ENET_Ptp1588Configure(). This should be called when the ENET receive required. + */ +static inline void ENET_ActiveRead(ENET_Type *base) +{ + base->RDAR = ENET_RDAR_RDAR_MASK; +} + +/*! + * @brief Enables/disables the MAC to enter sleep mode. + * This function is used to set the MAC enter sleep mode. + * When entering sleep mode, the magic frame wakeup interrupt should be enabled + * to wake up MAC from the sleep mode and reset it to normal mode. + * + * @param base ENET peripheral base address. + * @param enable True enable sleep mode, false disable sleep mode. + */ +static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable) +{ + if (enable) + { + /* When this field is set, MAC enters sleep mode. */ + base->ECR |= ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK; + } + else + { /* MAC exits sleep mode. */ + base->ECR &= ~(ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK); + } +} + +/*! + * @brief Gets ENET transmit and receive accelerator functions from the MAC controller. + * + * @param base ENET peripheral base address. + * @param txAccelOption The transmit accelerator option. The "enet_tx_accelerator_t" is + * recommended as the mask to get the exact the accelerator option. + * @param rxAccelOption The receive accelerator option. The "enet_rx_accelerator_t" is + * recommended as the mask to get the exact the accelerator option. + */ +static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption) +{ + assert(txAccelOption); + assert(txAccelOption); + + *txAccelOption = base->TACC; + *rxAccelOption = base->RACC; +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the ENET interrupt. + * + * This function enables the ENET interrupt according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. + * For example, to enable the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_EnableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupts to enable. This is a logical OR of the + * enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask) +{ + base->EIMR |= mask; +} + +/*! + * @brief Disables the ENET interrupt. + * + * This function disables the ENET interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. + * For example, to disable the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_DisableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupts to disable. This is a logical OR of the + * enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask) +{ + base->EIMR &= ~mask; +} + +/*! + * @brief Gets the ENET interrupt status flag. + * + * @param base ENET peripheral base address. + * @return The event status of the interrupt source. This is the logical OR of members + * of the enumeration :: enet_interrupt_enable_t. + */ +static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base) +{ + return base->EIR; +} + +/*! + * @brief Clears the ENET interrupt events status flag. + * + * This function clears enabled ENET interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See the @ref enet_interrupt_enable_t. + * For example, to clear the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_ClearInterruptStatus(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupt source to be cleared. + * This is the logical OR of members of the enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask) +{ + base->EIR = mask; +} + +/* @} */ + +/*! + * @name Transactional operation + * @{ + */ + +/*! + * @brief Sets the callback function. + * This API is provided for the application callback required case when ENET + * interrupt is enabled. This API should be called after calling ENET_Init. + * + * @param handle ENET handler pointer. Should be provided by application. + * @param callback The ENET callback function. + * @param userData The callback function parameter. + */ +void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData); + +/*! + * @brief Gets the ENET the error statistics of a received frame. + * + * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). + * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. + * This is an example. + * @code + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (status == kStatus_ENET_RxFrameError) + * { + * // Get the error information of the received frame. + * ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic); + * // update the receive buffer. + * ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0); + * } + * @endcode + * @param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + */ +void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @brief Gets the ENET transmit frame statistics after the data send. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API. It is recommended to call this function on + * transmit interrupt handler. After calling the ENET_SendFrame, the + * transmit interrupt notifies the transmit completion. + * + * @param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + * @return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +/*! +* @brief Gets the size of the read frame. +* This function gets a received frame size from the ENET buffer descriptors. +* @note The FCS of the frame is automatically removed by Mac and the size is the length without the FCS. +* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the +* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". +* +* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. +* @param length The length of the valid frame received. +* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. +* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data +* and NULL length to update the receive buffers. +* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame +* should be called with the right data buffer and the captured data length input. +*/ +status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length); + +/*! + * @brief Reads a frame from the ENET device. + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. + * This is an example. + * @code + * uint32_t length; + * enet_handle_t g_handle; + * //Get the received frame size firstly. + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (length != 0) + * { + * //Allocate memory here with the size of "length" + * uint8_t *data = memory allocate interface; + * if (!data) + * { + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * //Add the console warning log. + * } + * else + * { + * status = ENET_ReadFrame(ENET, &g_handle, data, length); + * //Call stack input API to deliver the data to stack + * } + * } + * else if (status == kStatus_ENET_RxFrameError) + * { + * //Update the received buffer when a error frame is received. + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * } + * @endcode + * @param base ENET peripheral base address. + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to store the frame which memory size should be at least "length". + * @param length The size of the data buffer which is still the length of the received frame. + * @return The execute status, successful or failure. + */ +status_t ENET_ReadFrame(ENET_Type *base,enet_handle_t *handle,const enet_config_t *config, uint8_t *data,uint16_t *length); + +/*! + * @brief Transmits an ENET frame. + * @note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to be send. + * @param length The length of the data to be send. + * @retval kStatus_Success Send frame succeed. + * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ +status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint16_t length,uint32_t last_flag); + +/*! + * @brief The transmit IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief The receive IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief The error IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief the common IRQ handler for the tx/rx/error etc irq handler. + * + * This is used for the combined tx/rx/error interrupt for single ring (ring 0). + * + * @param base ENET peripheral base address. + */ +void ENET_CommonFrame0IRQHandler(ENET_Type *base); +/* @} */ + +/*! + * @brief the common IRQ handler for the tx/rx/error etc irq handler. + * + * This is used for the combined tx/rx/error interrupt for single ring (ring 0). + * @param irq gic interrupt number. + * @param base ENET peripheral base address. + */ +void ENET_DriverIRQHandler(int irq, void *base); + +/*! + * config pin for enet function + */ +void ENET_InitPins(void); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @name ENET PTP 1588 function operation + * @{ + */ + +/*! + * @brief Configures the ENET PTP IEEE 1588 feature with the basic configuration. + * The function sets the clock for PTP 1588 timer and enables + * time stamp interrupts and transmit interrupts for PTP 1588 features. + * This API should be called when the 1588 feature is enabled + * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined. + * ENET_Init should be called before calling this API. + * + * @note The PTP 1588 time-stamp second increase though time-stamp interrupt handler + * and the transmit time-stamp store is done through transmit interrupt handler. + * As a result, the TS interrupt and TX interrupt are enabled when you call this API. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param ptpConfig The ENET PTP1588 configuration. + */ +void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig); + +/*! + * @brief Starts the ENET PTP 1588 Timer. + * This function is used to initialize the PTP timer. After the PTP starts, + * the PTP timer starts running. + * + * @param base ENET peripheral base address. + * @param ptpClkSrc The clock source of the PTP timer. + */ +void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc); + +/*! + * @brief Stops the ENET PTP 1588 Timer. + * This function is used to stops the ENET PTP timer. + * + * @param base ENET peripheral base address. + */ +static inline void ENET_Ptp1588StopTimer(ENET_Type *base) +{ + /* Disable PTP timer and reset the timer. */ + base->ATCR &= ~ENET_ATCR_EN_MASK; + base->ATCR |= ENET_ATCR_RESTART_MASK; +} + +/*! + * @brief Adjusts the ENET PTP 1588 timer. + * + * @param base ENET peripheral base address. + * @param corrIncrease The correction increment value. This value is added every time the correction + * timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer, + * a value greater than the 1/ptpClkSrc speeds up the timer. + * @param corrPeriod The PTP timer correction counter wrap-around value. This defines after how + * many timer clock the correction counter should be reset and trigger a correction + * increment on the timer. A value of 0 disables the correction counter and no correction occurs. + */ +void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod); + +/*! + * @brief Sets the ENET PTP 1588 timer channel mode. + * + * @param base ENET peripheral base address. + * @param channel The ENET PTP timer channel number. + * @param mode The PTP timer channel mode, see "enet_ptp_timer_channel_mode_t". + * @param intEnable Enables or disables the interrupt. + */ +static inline void ENET_Ptp1588SetChannelMode(ENET_Type *base, + enet_ptp_timer_channel_t channel, + enet_ptp_timer_channel_mode_t mode, + bool intEnable) +{ + uint32_t tcrReg = 0; + + tcrReg = ENET_TCSR_TMODE(mode) | ENET_TCSR_TIE(intEnable); + /* Disable channel mode first. */ + base->CHANNEL[channel].TCSR = 0; + base->CHANNEL[channel].TCSR = tcrReg; +} + +#if defined(FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL) && FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL +/*! + * @brief Sets ENET PTP 1588 timer channel mode pulse width. + * + * For the input "mode" in ENET_Ptp1588SetChannelMode, the kENET_PtpChannelPulseLowonCompare + * kENET_PtpChannelPulseHighonCompare only support the pulse width for one 1588 clock. + * this function is extended for control the pulse width from 1 to 32 1588 clock cycles. + * so call this function if you need to set the timer channel mode for + * kENET_PtpChannelPulseLowonCompare or kENET_PtpChannelPulseHighonCompare + * with pulse width more than one 1588 clock, + * + * @param base ENET peripheral base address. + * @param channel The ENET PTP timer channel number. + * @param isOutputLow True --- timer channel is configured for output compare + * pulse output low. + * false --- timer channel is configured for output compare + * pulse output high. + * @param pulseWidth The pulse width control value, range from 0 ~ 31. + * 0 --- pulse width is one 1588 clock cycle. + * 31 --- pulse width is thirty two 1588 clock cycles. + * @param intEnable Enables or disables the interrupt. + */ +static inline void ENET_Ptp1588SetChannelOutputPulseWidth(ENET_Type *base, + enet_ptp_timer_channel_t channel, + bool isOutputLow, + uint8_t pulseWidth, + bool intEnable) +{ + uint32_t tcrReg; + + tcrReg = ENET_TCSR_TIE(intEnable) | ENET_TCSR_TPWC(pulseWidth); + + if (isOutputLow) + { + tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseLowonCompare); + } + else + { + tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseHighonCompare); + } + + /* Disable channel mode first. */ + base->CHANNEL[channel].TCSR = 0; + base->CHANNEL[channel].TCSR = tcrReg; +} +#endif /* FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL */ + +/*! + * @brief Sets the ENET PTP 1588 timer channel comparison value. + * + * @param base ENET peripheral base address. + * @param channel The PTP timer channel, see "enet_ptp_timer_channel_t". + * @param cmpValue The compare value for the compare setting. + */ +static inline void ENET_Ptp1588SetChannelCmpValue(ENET_Type *base, enet_ptp_timer_channel_t channel, uint32_t cmpValue) +{ + base->CHANNEL[channel].TCCR = cmpValue; +} + +/*! + * @brief Gets the ENET PTP 1588 timer channel status. + * + * @param base ENET peripheral base address. + * @param channel The IEEE 1588 timer channel number. + * @return True or false, Compare or capture operation status + */ +static inline bool ENET_Ptp1588GetChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) +{ + return (0 != (base->CHANNEL[channel].TCSR & ENET_TCSR_TF_MASK)); +} + +/*! + * @brief Clears the ENET PTP 1588 timer channel status. + * + * @param base ENET peripheral base address. + * @param channel The IEEE 1588 timer channel number. + */ +static inline void ENET_Ptp1588ClearChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) +{ + base->CHANNEL[channel].TCSR |= ENET_TCSR_TF_MASK; + base->TGSR = (1U << channel); +} + +/*! + * @brief Gets the current ENET time from the PTP 1588 timer. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * @param ptpTime The PTP timer structure. + */ +void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); + +/*! + * @brief Sets the ENET PTP 1588 timer to the assigned time. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * @param ptpTime The timer to be set to the PTP timer. + */ +void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); + +/*! + * @brief The IEEE 1588 PTP time stamp interrupt handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + */ +void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief Gets the time stamp of the received frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * @param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * @retval kStatus_Success Get 1588 timestamp success. + * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); + +/*! + * @brief Gets the time stamp of the transmit frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * @param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * @retval kStatus_Success Get 1588 timestamp success. + * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_ENET_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_epit.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_epit.c new file mode 100644 index 0000000000..2213758248 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_epit.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_epit.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base EPIT peripheral base address + * + * @return The EPIT instance + */ +static uint32_t EPIT_GetInstance(EPIT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to EPIT bases for each instance. */ +static EPIT_Type *const s_epitBases[] = EPIT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to EPIT clocks for each instance. */ +static const clock_ip_name_t s_epitClocks[] = EPIT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t EPIT_GetInstance(EPIT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_epitBases); instance++) + { + if (s_epitBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_epitBases)); + + return instance; +} + +void EPIT_Init(EPIT_Type *base, const epit_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the EPIT clock*/ + CLOCK_EnableClock(s_epitClocks[EPIT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->CR = 0U; + + EPIT_SoftwareReset(base); + + base->CR = + (config->enableRunInStop ? EPIT_CR_STOPEN_MASK : 0U) | (config->enableRunInWait ? EPIT_CR_WAITEN_MASK : 0U) | + (config->enableRunInDbg ? EPIT_CR_DBGEN_MASK : 0U) | (config->enableCounterOverwrite ? EPIT_CR_IOVW_MASK : 0U) | + (config->enableFreeRun ? 0U : EPIT_CR_RLD_MASK) | (config->enableResetMode ? EPIT_CR_ENMOD_MASK : 0U); + + EPIT_SetClockSource(base, config->clockSource); + EPIT_SetClockDivider(base, config->divider); +} + +void EPIT_Deinit(EPIT_Type *base) +{ + /* Disable EPIT timers */ + base->CR = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the EPIT clock*/ + CLOCK_DisableClock(s_epitClocks[EPIT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void EPIT_GetDefaultConfig(epit_config_t *config) +{ + assert(config); + + config->clockSource = kEPIT_ClockSource_Periph; + config->divider = 1U; + config->enableRunInStop = true; + config->enableRunInWait = true; + config->enableRunInDbg = false; + config->enableCounterOverwrite = false; + config->enableFreeRun = false; + config->enableResetMode = true; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_epit.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_epit.h new file mode 100644 index 0000000000..14dd31240b --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_epit.h @@ -0,0 +1,397 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_EPIT_H_ +#define _FSL_EPIT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup epit + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_EPIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ + /*@}*/ + +/*! + * @brief List of clock sources + * @note Actual number of clock sources is SoC dependent + */ +typedef enum _epit_clock_source +{ + kEPIT_ClockSource_Off = 0U, /*!< EPIT Clock Source Off.*/ + kEPIT_ClockSource_Periph = 1U, /*!< EPIT Clock Source from Peripheral Clock.*/ + kEPIT_ClockSource_HighFreq = 2U, /*!< EPIT Clock Source from High Frequency Reference Clock.*/ + kEPIT_ClockSource_LowFreq = 3U, /*!< EPIT Clock Source from Low Frequency Reference Clock.*/ +} epit_clock_source_t; + +/*! + * @brief List of output compare operation mode + */ +typedef enum _epit_output_operation_mode +{ + kEPIT_OutputOperation_Disconnected = 0U, /*!< EPIT Output Operation: Disconnected from pad.*/ + kEPIT_OutputOperation_Toggle = 1U, /*!< EPIT Output Operation: Toggle output pin.*/ + kEPIT_OutputOperation_Clear = 2U, /*!< EPIT Output Operation: Clear output pin.*/ + kEPIT_OutputOperation_Set = 3U, /*!< EPIT Output Operation: Set putput pin.*/ +} epit_output_operation_mode_t; + +/*! @brief List of EPIT interrupts */ +typedef enum _epit_interrupt_enable +{ + kEPIT_OutputCompareInterruptEnable = EPIT_CR_OCIEN_MASK, /*!< Output Compare interrupt enable*/ +} epit_interrupt_enable_t; + +/*! @brief List of EPIT status flags */ +typedef enum _epit_status_flags +{ + kEPIT_OutputCompareFlag = EPIT_SR_OCIF_MASK, /*!< Output Compare flag */ +} epit_status_flags_t; + +/*! @brief Structure to configure the running mode. */ +typedef struct _epit_config +{ + epit_clock_source_t clockSource; /*!< clock source for EPIT module. */ + uint32_t divider; /*!< clock divider (prescaler+1) from clock source to counter. */ + bool enableRunInStop; /*!< EPIT enabled in stop mode. */ + bool enableRunInWait; /*!< EPIT enabled in wait mode. */ + bool enableRunInDbg; /*!< EPIT enabled in debug mode. */ + bool enableCounterOverwrite; /*!< set timer period results in counter value being overwritten. */ + bool enableFreeRun; /*!< true: free-running mode, counter will be reset to 0xFFFFFFFF when timer expires; + false: set-and-forget mode, counter will be reloaded from set timer periods. */ + bool enableResetMode; /*!< true: counter is reset to timer periods in set-and-forget mode or 0xFFFFFFFF in + free-running mode when enabled; + false: counter restores the value that it was disabled when enabled. */ +} epit_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Software reset of EPIT module. + * + * @param base EPIT peripheral base address. + */ +static inline void EPIT_SoftwareReset(EPIT_Type *base) +{ + base->CR |= EPIT_CR_SWR_MASK; + /* Wait reset finished. */ + while ((base->CR & EPIT_CR_SWR_MASK) == EPIT_CR_SWR_MASK) + { + } +} + +/* @} */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the EPIT clock and configures the peripheral for a basic operation. + * + * This function issues a software reset to reset all the registers to their reset values, + * except for the EN, ENMOD, STOPEN, WAITEN and DBGEN bits in Control register. + * + * @note This API should be called at the beginning of the application using the EPIT driver. + * + * @param base EPIT peripheral base address. + * @param config Pointer to the user configuration structure. + */ +void EPIT_Init(EPIT_Type *base, const epit_config_t *config); + +/*! + * @brief Disables the module and gates the EPIT clock. + * + * @param base EPIT peripheral base address. + */ +void EPIT_Deinit(EPIT_Type *base); + +/*! + * @brief Fills in the EPIT configuration structure with default settings. + * + * The default values are: + * @code + * config->clockSource = kEPIT_ClockSource_Periph; + * config->divider = 1U; + * config->enableRunInStop = true; + * config->enableRunInWait = true; + * config->enableRunInDbg = false; + * config->enableCounterOverwrite = false; + * config->enableFreeRun = false; + * config->enableResetMode = true; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void EPIT_GetDefaultConfig(epit_config_t *config); + +/*! @}*/ + +/*! + * @name Clock source and frequency control + * @{ + */ + +/*! + * @brief Set clock source of EPIT. + * + * @param base EPIT peripheral base address. + * @param source clock source to switch to. + */ +static inline void EPIT_SetClockSource(EPIT_Type *base, epit_clock_source_t source) +{ + base->CR = (base->CR & ~EPIT_CR_CLKSRC_MASK) | EPIT_CR_CLKSRC(source); +} + +/*! + * @brief Set clock divider inside EPIT module. + * + * @param base EPIT peripheral base address. + * @param divider Clock divider in EPIT module (1-4096, divider = prescaler + 1). + */ +static inline void EPIT_SetClockDivider(EPIT_Type *base, uint32_t divider) +{ + assert((divider > 0) && (divider <= (EPIT_CR_PRESCALAR_MASK >> EPIT_CR_PRESCALAR_SHIFT) + 1)); + base->CR = (base->CR & ~EPIT_CR_PRESCALAR_MASK) | EPIT_CR_PRESCALAR(divider - 1); +} + +/*! + * @brief Get clock divider inside EPIT module. + * + * @param base EPIT base pointer. + * @return clock divider in EPIT module (1-4096). + */ +static inline uint32_t EPIT_GetClockDivider(EPIT_Type *base) +{ + return ((base->CR & EPIT_CR_PRESCALAR_MASK) >> EPIT_CR_PRESCALAR_SHIFT) + 1; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Start EPIT timer. + * + * @param base EPIT peripheral base address. + */ +static inline void EPIT_StartTimer(EPIT_Type *base) +{ + base->CR |= EPIT_CR_EN_MASK; +} + +/*! + * @brief Stop EPIT timer. + * + * @param base EPIT peripheral base address. + */ +static inline void EPIT_StopTimer(EPIT_Type *base) +{ + base->CR &= ~EPIT_CR_EN_MASK; +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers begin counting down from the value set by this function until it reaches 0, at which point + * it generates an interrupt and loads this register value again. + * When enableCounterOverwrite is false, writing a new value to this register does not restart the timer, + * and the value is loaded after the timer expires. When enableCounterOverwrite is true, the counter + * will be set immediately and starting counting down from that value. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks. + * + * @param base EPIT peripheral base address. + * @param ticks Timer period in units of ticks. + */ +static inline void EPIT_SetTimerPeriod(EPIT_Type *base, uint32_t ticks) +{ + base->LR = ticks; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to microseconds or milliseconds. + * + * @param base EPIT peripheral base address. + * + * @return Current timer counting value in ticks. + */ +static inline uint32_t EPIT_GetCurrentTimerCount(EPIT_Type *base) +{ + return base->CNR; +} + +/*@}*/ + +/*! + * @name Output Signal Control + * @{ + */ + +/*! + * @brief Set EPIT output compare operation mode. + * + * @param base EPIT peripheral base address. + * @param mode EPIT output compare operation mode. + */ +static inline void EPIT_SetOutputOperationMode(EPIT_Type *base, epit_output_operation_mode_t mode) +{ + base->CR = (base->CR & ~EPIT_CR_OM_MASK) | EPIT_CR_OM(mode); +} + +/*! + * @brief Set EPIT output compare value. + * + * @param base EPIT peripheral base address. + * @param value EPIT output compare value. + */ +static inline void EPIT_SetOutputCompareValue(EPIT_Type *base, uint32_t value) +{ + base->CMPR = value; +} + +/*@}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected EPIT interrupts. + * + * @param base EPIT peripheral base address. + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::epit_interrupt_enable_t + */ +static inline void EPIT_EnableInterrupts(EPIT_Type *base, uint32_t mask) +{ + base->CR |= mask; +} + +/*! + * @brief Disables the selected EPIT interrupts. + * + * @param base EPIT peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::epit_interrupt_enable_t + */ +static inline void EPIT_DisableInterrupts(EPIT_Type *base, uint32_t mask) +{ + base->CR &= ~mask; +} + +/*! + * @brief Gets the enabled EPIT interrupts. + * + * @param base EPIT peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::epit_interrupt_enable_t + */ +static inline uint32_t EPIT_GetEnabledInterrupts(EPIT_Type *base) +{ + return (base->CR & EPIT_CR_OCIEN_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the EPIT status flags. + * + * @param base EPIT peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::epit_status_flags_t + */ +static inline uint32_t EPIT_GetStatusFlags(EPIT_Type *base) +{ + return (base->SR & EPIT_SR_OCIF_MASK); +} + +/*! + * @brief Clears the EPIT status flags. + * + * @param base EPIT peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::epit_status_flags_t + */ +static inline void EPIT_ClearStatusFlags(EPIT_Type *base, uint32_t mask) +{ + base->SR = mask; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /*_FSL_EPIT_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_gpio.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_gpio.c new file mode 100644 index 0000000000..be1665ffdd --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_gpio.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_gpio.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of GPIO peripheral base address. */ +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of GPIO clock name. */ +static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* +* Prototypes +******************************************************************************/ + +/*! +* @brief Gets the GPIO instance according to the GPIO base +* +* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) +* @retval GPIO instance +*/ +static uint32_t GPIO_GetInstance(GPIO_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t GPIO_GetInstance(GPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++) + { + if (s_gpioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gpioBases)); + + return instance; +} + +void GPIO_PinInit(GPIO_Type* base, uint32_t pin, const gpio_pin_config_t* Config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable GPIO clock. */ + CLOCK_EnableClock(s_gpioClock[GPIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Register reset to default value */ + base->IMR &= ~(1U << pin); + + /* Configure GPIO pin direction */ + if (Config->direction == kGPIO_DigitalInput) + { + base->GDIR &= ~(1U << pin); + } + else + { + GPIO_WritePinOutput(base, pin, Config->outputLogic); + base->GDIR |= (1U << pin); + } + + /* Configure GPIO pin interrupt mode */ + GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode); +} + +void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, uint8_t output) +{ + assert(pin < 32); + if (output == 0U) + { + base->DR &= ~(1U << pin); /* Set pin output to low level.*/ + } + else + { + base->DR |= (1U << pin); /* Set pin output to high level.*/ + } +} + +void GPIO_SetPinInterruptConfig(GPIO_Type* base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) +{ + volatile uint32_t *icr; + uint32_t icrShift; + + icrShift = pin; + + /* Register reset to default value */ + base->EDGE_SEL &= ~(1U << pin); + + if(pin < 16) + { + icr = &(base->ICR1); + } + else + { + icr = &(base->ICR2); + icrShift -= 16; + } + switch(pinInterruptMode) + { + case(kGPIO_IntLowLevel): + *icr &= ~(3U << (2 * icrShift)); + break; + case(kGPIO_IntHighLevel): + *icr = (*icr & (~(3U << (2 * icrShift)))) | (1U << (2 * icrShift)); + break; + case(kGPIO_IntRisingEdge): + *icr = (*icr & (~(3U << (2 * icrShift)))) | (2U << (2 * icrShift)); + break; + case(kGPIO_IntFallingEdge): + *icr |= (3U << (2 * icrShift)); + break; + case(kGPIO_IntRisingOrFallingEdge): + base->EDGE_SEL |= (1U << pin); + break; + default: + break; + } +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_gpio.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_gpio.h new file mode 100644 index 0000000000..53d6ba5737 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_gpio.h @@ -0,0 +1,243 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_GPIO_H_ +#define _FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPIO driver version 2.0.0. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief GPIO direction definition. */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/ +} gpio_pin_direction_t; + +/*! @brief GPIO interrupt mode definition. */ +typedef enum _gpio_interrupt_mode +{ + kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/ + kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/ + kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/ + kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/ + kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/ + kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/ +} gpio_interrupt_mode_t; + +/*! @brief GPIO Init structure definition. */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ + gpio_interrupt_mode_t interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ +} gpio_pin_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name GPIO Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initializes the GPIO peripheral according to the specified + * parameters in the initConfig. + * + * @param base GPIO base pointer. + * @param pin Specifies the pin number + * @param initConfig pointer to a @ref gpio_pin_config_t structure that + * contains the configuration information. + */ +void GPIO_PinInit(GPIO_Type* base, uint32_t pin, const gpio_pin_config_t* Config); +/*@}*/ + +/*! + * @name GPIO Reads and Write Functions + * @{ + */ + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param output GPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. */ +void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, uint8_t output); + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_SetPinsOutput(GPIO_Type* base, uint32_t mask) +{ + base->DR |= mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type* base, uint32_t mask) +{ + base->DR &= ~mask; +} + +/*! + * @brief Reads the current input value of the GPIO port. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO port input value. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type* base, uint32_t pin) +{ + assert(pin < 32); + + return (((base->DR) >> pin) & 0x1U); +} +/*@}*/ + +/*! + * @name GPIO Reads Pad Status Functions + * @{ + */ + + /*! + * @brief Reads the current GPIO pin pad status. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO pin pad status value. + */ +static inline uint8_t GPIO_ReadPadStatus(GPIO_Type* base, uint32_t pin) +{ + assert(pin < 32); + + return (uint8_t)(((base->PSR) >> pin) & 0x1U); +} +/*@}*/ + +/*! + * @name Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Sets the current pin interrupt mode. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param pininterruptMode pointer to a @ref gpio_interrupt_mode_t structure + * that contains the interrupt mode information. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type* base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode); + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_EnableInterrupts(GPIO_Type* base, uint32_t mask) +{ + base->IMR |= mask; +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_DisableInterrupts(GPIO_Type* base, uint32_t mask) +{ + base->IMR &= ~mask; +} + +/*! + * @brief Reads individual pin interrupt status. + * + * @param base GPIO base pointer. + * @retval current pin interrupt status flag. + */ +static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type* base) +{ + return base->ISR; +} + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type* base, uint32_t mask) +{ + base->ISR = mask; +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_GPIO_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_i2c.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_i2c.c new file mode 100644 index 0000000000..460212425d --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_i2c.c @@ -0,0 +1,1376 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_i2c.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief i2c transfer state. */ +enum _i2c_transfer_states +{ + kIdleState = 0x0U, /*!< I2C bus idle. */ + kCheckAddressState = 0x1U, /*!< 7-bit address check state. */ + kSendCommandState = 0x2U, /*!< Send command byte phase. */ + kSendDataState = 0x3U, /*!< Send data transfer phase. */ + kReceiveDataBeginState = 0x4U, /*!< Receive data transfer phase begin. */ + kReceiveDataState = 0x5U, /*!< Receive data transfer phase. */ +}; + +/*! @brief Common sets of flags used by the driver. */ +enum _i2c_flag_constants +{ + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag, + kIrqFlags = kI2C_GlobalInterruptEnable, +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for I2C module. + * + * @param base I2C peripheral base address. + */ +uint32_t I2C_GetInstance(I2C_Type *base); + +/*! + * @brief Set up master transfer, send slave address and decide the initial + * transfer state. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + */ +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Check and clear status operation. + * + * @param base I2C peripheral base address. + * @param status current i2c hardware status. + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + */ +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status); + +/*! + * @brief Master run transfer state machine to perform a byte of transfer. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + * @param isDone input param to get whether the thing is done, true is done + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); + +/*! + * @brief I2C common interrupt handler. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + */ +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief SCL clock divider used to calculate baudrate. */ +static const uint16_t s_i2cDividerTable[] = { + 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, 160, 192, 240, + 288, 320, 384, 480, 576, 640, 768, 960, 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840, + 22, 24, 26, 28, 32, 36, 40, 44, 48, 56, 64, 72, 80, 96, 112, 128, + 160, 192, 224, 256, 320, 384, 448, 512, 640, 768, 896, 1024, 1280, 1536, 1792, 2048}; + +/*! @brief Pointers to i2c bases for each instance. */ +static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS; + +/*! @brief Pointers to i2c IRQ number for each instance. */ +static const IRQn_Type s_i2cIrqs[] = I2C_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to i2c clocks for each instance. */ +static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to i2c handles for each instance. */ +static void *s_i2cHandle[ARRAY_SIZE(s_i2cBases)] = {NULL}; + +/*! @brief Pointer to master IRQ handler for each instance. */ +static i2c_isr_t s_i2cMasterIsr; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static i2c_isr_t s_i2cSlaveIsr; + +/******************************************************************************* + * Codes + ******************************************************************************/ + +uint32_t I2C_GetInstance(I2C_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_i2cBases); instance++) + { + if (s_i2cBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_i2cBases)); + + return instance; +} + +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result = kStatus_Success; + i2c_direction_t direction = xfer->direction; + + /* Initialize the handle transfer information. */ + handle->transfer = *xfer; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Initial transfer state. */ + if (handle->transfer.subaddressSize > 0) + { + if (xfer->direction == kI2C_Read) + { + direction = kI2C_Write; + } + } + + handle->state = kCheckAddressState; + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* If repeated start is requested, send repeated start. */ + if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); + } + + return result; +} + +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check arbitration lost. */ + if (status & kI2C_ArbitrationLostFlag) + { + /* Clear arbitration lost flag. */ + base->I2SR &= (uint8_t)(~kI2C_ArbitrationLostFlag); + + /* Reset I2C controller*/ + base->I2CR &= ~I2C_I2CR_IEN_MASK; + base->I2CR |= I2C_I2CR_IEN_MASK; + + result = kStatus_I2C_ArbitrationLost; + } + /* Check NAK */ + else if (status & kI2C_ReceiveNakFlag) + { + result = kStatus_I2C_Nak; + } + else + { + } + + return result; +} + +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = base->I2SR; + *isDone = false; + volatile uint8_t dummy = 0; + bool ignoreNak = ((handle->state == kSendDataState) && (handle->transfer.dataSize == 0U)) || + ((handle->state == kReceiveDataState) && (handle->transfer.dataSize == 1U)); + + /* Add this to avoid build warning. */ + dummy++; + + /* Check & clear error flags. */ + result = I2C_CheckAndClearError(base, statusFlags); + + /* Ignore Nak when it's appeared for last byte. */ + if ((result == kStatus_I2C_Nak) && ignoreNak) + { + result = kStatus_Success; + } + + /* Handle Check address state to check the slave address is Acked in slave + probe application. */ + if (handle->state == kCheckAddressState) + { + if (statusFlags & kI2C_ReceiveNakFlag) + { + result = kStatus_I2C_Addr_Nak; + } + else + { + if (handle->transfer.subaddressSize > 0) + { + handle->state = kSendCommandState; + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = kSendDataState; + } + else + { + /* Next state, receive data begin. */ + handle->state = kReceiveDataBeginState; + } + } + } + } + + if (result) + { + return result; + } + + /* Run state machine. */ + switch (handle->state) + { + /* Send I2C command. */ + case kSendCommandState: + if (handle->transfer.subaddressSize) + { + handle->transfer.subaddressSize--; + base->I2DR = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)); + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = kSendDataState; + + /* Send first byte of data. */ + if (handle->transfer.dataSize > 0) + { + base->I2DR = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + } + else + { + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); + + /* Next state, receive data begin. */ + handle->state = kReceiveDataBeginState; + } + } + break; + + /* Send I2C data. */ + case kSendDataState: + /* Send one byte of data. */ + if (handle->transfer.dataSize > 0) + { + base->I2DR = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + *isDone = true; + } + break; + + /* Start I2C data receive. */ + case kReceiveDataBeginState: + base->I2CR &= ~(I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + base->I2CR |= I2C_I2CR_TXAK_MASK; + } + + /* Read dummy to release the bus. */ + dummy = base->I2DR; + + /* Next state, receive data. */ + handle->state = kReceiveDataState; + break; + + /* Receive I2C data. */ + case kReceiveDataState: + /* Receive one byte of data. */ + if (handle->transfer.dataSize--) + { + if (handle->transfer.dataSize == 0) + { + *isDone = true; + + /* Send stop if kI2C_TransferNoStop is not asserted. */ + if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + result = I2C_MasterStop(base); + } + else + { + base->I2CR |= I2C_I2CR_MTX_MASK; + } + } + + /* Send NAK at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + base->I2CR |= I2C_I2CR_TXAK_MASK; + } + + /* Read the data byte into the transfer buffer. */ + *handle->transfer.data = base->I2DR; + handle->transfer.data++; + } + break; + + default: + break; + } + + return result; +} + +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle) +{ + /* Check if master interrupt. */ + if ((base->I2SR & kI2C_ArbitrationLostFlag) || (base->I2CR & I2C_I2CR_MSTA_MASK)) + { + s_i2cMasterIsr(base, handle); + } + else + { + s_i2cSlaveIsr(base, handle); + } + __DSB(); +} + +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(masterConfig && srcClock_Hz); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable I2C clock. */ + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable I2C prior to configuring it. */ + base->I2CR &= ~(I2C_I2CR_IEN_MASK); + + /* Clear all flags. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Configure baud rate. */ + I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); + + /* Enable the I2C peripheral based on the configuration. */ + base->I2CR = I2C_I2CR_IEN(masterConfig->enableMaster); +} + +void I2C_MasterDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) +{ + assert(masterConfig); + + /* Default baud rate at 100kbps. */ + masterConfig->baudRate_Bps = 100000U; + + /* Enable the I2C peripheral. */ + masterConfig->enableMaster = true; +} + +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask) +{ + if (mask & kI2C_GlobalInterruptEnable) + { + base->I2CR |= I2C_I2CR_IIEN_MASK; + } +} + +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask) +{ + if (mask & kI2C_GlobalInterruptEnable) + { + base->I2CR &= ~I2C_I2CR_IIEN_MASK; + } +} + +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t computedRate; + uint32_t absError; + uint32_t bestError = UINT32_MAX; + uint32_t bestIcr = 0u; + uint8_t i; + + /* Scan table to find best match. */ + for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(s_i2cDividerTable[0]); ++i) + { + computedRate = srcClock_Hz / s_i2cDividerTable[i]; + absError = baudRate_Bps > computedRate ? (baudRate_Bps - computedRate) : (computedRate - baudRate_Bps); + + if (absError < bestError) + { + bestIcr = i; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0) + { + break; + } + } + } + + /* Set frequency register based on best settings. */ + base->IFDR = I2C_IFDR_IC(bestIcr); +} + +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + + /* Return an error if the bus is already in use. */ + if (statusFlags & kI2C_BusBusyFlag) + { + result = kStatus_I2C_Busy; + } + else + { + /* Send the START signal. */ + base->I2CR |= I2C_I2CR_MSTA_MASK | I2C_I2CR_MTX_MASK; + + base->I2DR = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + + /* Return an error if the bus is already in use, but not by us. */ + if ((statusFlags & kI2C_BusBusyFlag) && ((base->I2CR & I2C_I2CR_MSTA_MASK) == 0)) + { + result = kStatus_I2C_Busy; + } + else + { + /* We are already in a transfer, so send a repeated start. */ + base->I2CR |= I2C_I2CR_RSTA_MASK | I2C_I2CR_MTX_MASK; + + base->I2DR = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +status_t I2C_MasterStop(I2C_Type *base) +{ + status_t result = kStatus_Success; + uint16_t timeout = UINT16_MAX; + + /* Issue the STOP command on the bus. */ + base->I2CR &= ~(I2C_I2CR_MSTA_MASK | I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + + /* Wait until data transfer complete. */ + while ((base->I2SR & kI2C_BusBusyFlag) && (--timeout)) + { + } + + if (timeout == 0) + { + result = kStatus_I2C_Timeout; + } + + return result; +} + +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags) +{ + status_t result = kStatus_Success; + uint8_t statusFlags = 0; + + /* Wait until the data register is ready for transmit. */ + while (!(base->I2SR & kI2C_TransferCompleteFlag)) + { + } + + /* Clear the IICIF flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to transmit data. */ + base->I2CR |= I2C_I2CR_MTX_MASK; + + while (txSize--) + { + /* Send a byte of data. */ + base->I2DR = *txBuff++; + + /* Wait until data transfer complete. */ + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + + statusFlags = base->I2SR; + + /* Clear the IICIF flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Check if arbitration lost or no acknowledgement (NAK), return failure status. */ + if (statusFlags & kI2C_ArbitrationLostFlag) + { + base->I2SR = kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + + if ((statusFlags & kI2C_ReceiveNakFlag) && txSize) + { + base->I2SR = kI2C_ReceiveNakFlag; + result = kStatus_I2C_Nak; + } + + if (result != kStatus_Success) + { + /* Breaking out of the send loop. */ + break; + } + } + + if (((result == kStatus_Success) && (!(flags & kI2C_TransferNoStopFlag))) || (result == kStatus_I2C_Nak)) + { + /* Clear the IICIF flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Send stop. */ + result = I2C_MasterStop(base); + } + + return result; +} + +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags) +{ + status_t result = kStatus_Success; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Wait until the data register is ready for transmit. */ + while (!(base->I2SR & kI2C_TransferCompleteFlag)) + { + } + + /* Clear the IICIF flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to receive data. */ + base->I2CR &= ~(I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + + /* If rxSize equals 1, configure to send NAK. */ + if (rxSize == 1) + { + /* Issue NACK on read. */ + base->I2CR |= I2C_I2CR_TXAK_MASK; + } + + /* Do dummy read. */ + dummy = base->I2DR; + + while ((rxSize--)) + { + /* Wait until data transfer complete. */ + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + + /* Clear the IICIF flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Single byte use case. */ + if (rxSize == 0) + { + if (!(flags & kI2C_TransferNoStopFlag)) + { + /* Issue STOP command before reading last byte. */ + result = I2C_MasterStop(base); + } + else + { + /* Change direction to Tx to avoid extra clocks. */ + base->I2CR |= I2C_I2CR_MTX_MASK; + } + } + + if (rxSize == 1) + { + /* Issue NACK on read. */ + base->I2CR |= I2C_I2CR_TXAK_MASK; + } + + /* Read from the data register. */ + *rxBuff++ = base->I2DR; + } + + return result; +} + +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) +{ + assert(xfer); + + i2c_direction_t direction = xfer->direction; + status_t result = kStatus_Success; + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Wait until ready to complete. */ + while (!(base->I2SR & kI2C_TransferCompleteFlag)) + { + } + + /* Change to send write address when it's a read operation with command. */ + if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) + { + direction = kI2C_Write; + } + + /* If repeated start is requested, send repeated start. */ + if (xfer->flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, xfer->slaveAddress, direction); + } + + /* Return if error. */ + if (result) + { + return result; + } + + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->I2SR); + + /* Return if error. */ + if (result) + { + if (result == kStatus_I2C_Nak) + { + result = kStatus_I2C_Addr_Nak; + + I2C_MasterStop(base); + } + + return result; + } + + /* Send subaddress. */ + if (xfer->subaddressSize) + { + do + { + /* Clear interrupt pending flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + xfer->subaddressSize--; + base->I2DR = ((xfer->subaddress) >> (8 * xfer->subaddressSize)); + + /* Wait until data transfer complete. */ + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->I2SR); + + if (result) + { + if (result == kStatus_I2C_Nak) + { + I2C_MasterStop(base); + } + + return result; + } + + } while ((xfer->subaddressSize > 0) && (result == kStatus_Success)); + + if (xfer->direction == kI2C_Read) + { + /* Clear pending flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read); + + /* Return if error. */ + if (result) + { + return result; + } + + /* Wait until data transfer complete. */ + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->I2SR); + + if (result) + { + if (result == kStatus_I2C_Nak) + { + result = kStatus_I2C_Addr_Nak; + + I2C_MasterStop(base); + } + + return result; + } + } + } + + /* Transmit data. */ + if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) + { + /* Send Data. */ + result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + + /* Receive Data. */ + if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) + { + result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + + return result; +} + +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save master interrupt handler. */ + s_i2cMasterIsr = I2C_MasterTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + EnableIRQ(s_i2cIrqs[instance]); +} + +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + status_t result = kStatus_Success; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->state != kIdleState) + { + result = kStatus_I2C_Busy; + } + else + { + /* Start up the master transfer state machine. */ + result = I2C_InitTransferStateMachine(base, handle, xfer); + + if (result == kStatus_Success) + { + /* Enable the I2C interrupts. */ + I2C_EnableInterrupts(base, kI2C_GlobalInterruptEnable); + } + } + + return result; +} + +void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +{ + assert(handle); + + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); + + /* Reset the state to idle. */ + handle->state = kIdleState; + + /* Send STOP signal. */ + if (handle->transfer.direction == kI2C_Read) + { + base->I2CR |= I2C_I2CR_TXAK_MASK; + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + base->I2CR &= ~(I2C_I2CR_MSTA_MASK | I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + dummy = base->I2DR; + } + else + { + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + base->I2CR &= ~(I2C_I2CR_MSTA_MASK | I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + } +} + +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->transferSize - handle->transfer.dataSize; + + return kStatus_Success; +} + +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(i2cHandle); + + i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle; + status_t result = kStatus_Success; + bool isDone; + + /* Clear the interrupt flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Check transfer complete flag. */ + result = I2C_MasterTransferRunStateMachine(base, handle, &isDone); + + if (isDone || result) + { + /* Send stop command if transfer done or received Nak. */ + if ((!(handle->transfer.flags & kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak) || + (result == kStatus_I2C_Addr_Nak)) + { + /* Ensure stop command is a need. */ + if ((base->I2CR & I2C_I2CR_MSTA_MASK)) + { + if (I2C_MasterStop(base) != kStatus_Success) + { + result = kStatus_I2C_Timeout; + } + } + } + + /* Restore handle to idle state. */ + handle->state = kIdleState; + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); + + /* Call the callback function after the function has completed. */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable I2C clock. */ + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->IADR = ((uint32_t)(slaveConfig->slaveAddress)) << 1U; + base->I2CR = I2C_I2CR_IEN(slaveConfig->enableSlave); +} + +void I2C_SlaveDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + /* Enable the I2C peripheral. */ + slaveConfig->enableSlave = true; +} + +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + status_t result = kStatus_Success; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Wait for address match flag. */ + while (!(base->I2SR & kI2C_AddressMatchFlag)) + { + } + + /* Read dummy to release bus. */ + dummy = base->I2DR; + + result = I2C_MasterWriteBlocking(base, txBuff, txSize, kI2C_TransferDefaultFlag); + + /* Switch to receive mode. */ + base->I2CR &= ~(I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + + /* Read dummy to release bus. */ + dummy = base->I2DR; + + return result; +} + +void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Wait for address match and int pending flag. */ + while (!(base->I2SR & kI2C_AddressMatchFlag)) + { + } + + /* Read dummy to release bus. */ + dummy = base->I2DR; + + /* Clear the IICIF flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to receive data. */ + base->I2CR &= ~(I2C_I2CR_MTX_MASK); + + while (rxSize--) + { + /* Wait until data transfer complete. */ + while (!(base->I2SR & kI2C_IntPendingFlag)) + { + } + /* Clear the IICIF flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Read from the data register. */ + *rxBuff++ = base->I2DR; + } +} + +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save slave interrupt handler. */ + s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + EnableIRQ(s_i2cIrqs[instance]); +} + +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) +{ + assert(handle); + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->state != kIdleState) + { + return kStatus_I2C_Busy; + } + else + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, kIrqFlags); + + /* Clear transfer in handle. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Record that we're busy. */ + handle->state = kCheckAddressState; + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent; + + /* Clear all flags. */ + I2C_SlaveClearStatusFlags(base, kClearFlags); + + /* Enable I2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I2C_EnableInterrupts(base, kIrqFlags); + } + + return kStatus_Success; +} + +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) +{ + assert(handle); + + if (handle->state != kIdleState) + { + /* Disable interrupts. */ + I2C_DisableInterrupts(base, kIrqFlags); + + /* Reset transfer info. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Reset the state to idle. */ + handle->state = kIdleState; + } +} + +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transfer.transferredCount; + + return kStatus_Success; +} + +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(i2cHandle); + + uint16_t status; + bool doTransmit = false; + i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle; + i2c_slave_transfer_t *xfer; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + status = I2C_SlaveGetStatusFlags(base); + xfer = &(handle->transfer); + + /* Clear the interrupt flag. */ + base->I2SR &= (uint8_t)~kI2C_IntPendingFlag; + + /* Check NAK */ + if (status & kI2C_ReceiveNakFlag) + { + /* Set receive mode. */ + base->I2CR &= ~(I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + + /* Read dummy. */ + dummy = base->I2DR; + + if (handle->transfer.dataSize != 0) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_I2C_Nak; + handle->state = kIdleState; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + else + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->state = kIdleState; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + } + /* Check address match. */ + else if (status & kI2C_AddressMatchFlag) + { + xfer->event = kI2C_SlaveAddressMatchEvent; + + /* Slave transmit, master reading from slave. */ + if (status & kI2C_TransferDirectionFlag) + { + handle->state = kSendDataState; + /* Change direction to send data. */ + base->I2CR |= I2C_I2CR_MTX_MASK; + + doTransmit = true; + } + else + { + handle->state = kReceiveDataState; + /* Slave receive, master writing to slave. */ + base->I2CR &= ~(I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + + /* Read dummy to release the bus. */ + dummy = base->I2DR; + } + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + /* Check transfer complete flag. */ + else if (status & kI2C_TransferCompleteFlag) + { + /* Slave transmit, master reading from slave. */ + if (handle->state == kSendDataState) + { + doTransmit = true; + } + else + { + /* If we're out of data, invoke callback to get more. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kI2C_SlaveReceiveEvent; + + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + /* Slave receive, master writing to slave. */ + uint8_t data = base->I2DR; + + if (handle->transfer.dataSize) + { + /* Receive data. */ + *handle->transfer.data++ = data; + handle->transfer.dataSize--; + xfer->transferredCount++; + + if (!handle->transfer.dataSize) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->state = kIdleState; + + /* Proceed receive complete event. */ + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + } + } + } + else + { + /* Read dummy to release bus. */ + dummy = base->I2DR; + } + + /* Send data if there is the need. */ + if (doTransmit) + { + /* If we're out of data, invoke callback to get more. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kI2C_SlaveTransmitEvent; + + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + if (handle->transfer.dataSize) + { + /* Send data. */ + base->I2DR = *handle->transfer.data++; + handle->transfer.dataSize--; + xfer->transferredCount++; + } + else + { + /* Switch to receive mode. */ + base->I2CR &= ~(I2C_I2CR_MTX_MASK | I2C_I2CR_TXAK_MASK); + + /* Read dummy to release bus. */ + dummy = base->I2DR; + + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->state = kIdleState; + + /* Proceed txdone event. */ + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + } +} + +#if defined(I2C1) +void I2C1_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]); +} +#endif + +#if defined(I2C2) +void I2C2_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]); +} +#endif + +#if defined(I2C3) +void I2C3_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]); +} +#endif + +#if defined(I2C4) +void I2C4_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C4, s_i2cHandle[4]); +} +#endif diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_i2c.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_i2c.h new file mode 100644 index 0000000000..9656b65eae --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_i2c.h @@ -0,0 +1,671 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_I2C_H_ +#define _FSL_I2C_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C driver version 2.0.0. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief I2C status return codes. */ +enum _i2c_status +{ + kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_I2C, 0), /*!< I2C is busy with current transfer. */ + kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1), /*!< Bus is Idle. */ + kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2), /*!< NAK received during transfer. */ + kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */ + kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Wait event timeout. */ + kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_I2C, 5), /*!< NAK received during the address probe. */ +}; + +/*! + * @brief I2C peripheral flags + * + * The following status register flags can be cleared: + * - #kI2C_ArbitrationLostFlag + * - #kI2C_IntPendingFlag + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + * + */ +enum _i2c_flags +{ + kI2C_ReceiveNakFlag = I2C_I2SR_RXAK_MASK, /*!< I2C receive NAK flag. */ + kI2C_IntPendingFlag = I2C_I2SR_IIF_MASK, /*!< I2C interrupt pending flag. */ + kI2C_TransferDirectionFlag = I2C_I2SR_SRW_MASK, /*!< I2C transfer direction flag. */ + kI2C_ArbitrationLostFlag = I2C_I2SR_IAL_MASK, /*!< I2C arbitration lost flag. */ + kI2C_BusBusyFlag = I2C_I2SR_IBB_MASK, /*!< I2C bus busy flag. */ + kI2C_AddressMatchFlag = I2C_I2SR_IAAS_MASK, /*!< I2C address match flag. */ + kI2C_TransferCompleteFlag = I2C_I2SR_ICF_MASK, + /*!< I2C transfer complete flag. */ +}; + +/*! @brief I2C feature interrupt source. */ +enum _i2c_interrupt_enable +{ + kI2C_GlobalInterruptEnable = I2C_I2CR_IIEN_MASK, /*!< I2C global interrupt. */ +}; + +/*! @brief The direction of master and slave transfers. */ +typedef enum _i2c_direction +{ + kI2C_Write = 0x0U, /*!< Master transmits to the slave. */ + kI2C_Read = 0x1U, /*!< Master receives from the slave. */ +} i2c_direction_t; + +/*! @brief I2C transfer control flag. */ +enum _i2c_master_transfer_flags +{ + kI2C_TransferDefaultFlag = 0x0U, /*!< A transfer starts with a start signal, stops with a stop signal. */ + kI2C_TransferNoStartFlag = 0x1U, /*!< A transfer starts without a start signal. */ + kI2C_TransferRepeatedStartFlag = 0x2U, /*!< A transfer starts with a repeated start signal. */ + kI2C_TransferNoStopFlag = 0x4U, /*!< A transfer ends without a stop signal. */ +}; + +/*! @brief I2C master user configuration. */ +typedef struct _i2c_master_config +{ + bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */ + uint32_t baudRate_Bps; /*!< Baud rate configuration of I2C peripheral. */ +} i2c_master_config_t; + +/*! @brief I2C master handle typedef. */ +typedef struct _i2c_master_handle i2c_master_handle_t; + +/*! @brief I2C master transfer callback typedef. */ +typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, + i2c_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief I2C master transfer structure. */ +typedef struct _i2c_master_transfer +{ + uint32_t flags; /*!< A transfer flag which controls the transfer. */ + uint8_t slaveAddress; /*!< 7-bit slave address. */ + i2c_direction_t direction; /*!< A transfer direction, read or write. */ + uint32_t subaddress; /*!< A sub address. Transferred MSB first. */ + uint8_t subaddressSize; /*!< A size of the command buffer. */ + uint8_t *volatile data; /*!< A transfer buffer. */ + volatile size_t dataSize; /*!< A transfer size. */ +} i2c_master_transfer_t; + +/*! @brief I2C master handle structure. */ +struct _i2c_master_handle +{ + i2c_master_transfer_t transfer; /*!< I2C master transfer copy. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< A transfer state maintained during transfer. */ + i2c_master_transfer_callback_t completionCallback; /*!< A callback function called when the transfer is finished. */ + void *userData; /*!< A callback parameter passed to the callback function. */ +}; + +/*! + * @brief Set of events sent to the callback for nonblocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to I2C_SlaveTransferNonBlocking() to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _i2c_slave_transfer_event +{ + kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kI2C_SlaveTransmitEvent = 0x02U, /*!< A callback is requested to provide data to transmit + (slave-transmitter role). */ + kI2C_SlaveReceiveEvent = 0x04U, /*!< A callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kI2C_SlaveTransmitAckEvent = 0x08U, /*!< A callback needs to either transmit an ACK or NACK. */ + kI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */ + /*! A bit mask of all available events. */ + kI2C_SlaveAllEvents = + kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | kI2C_SlaveCompletionEvent, +} i2c_slave_transfer_event_t; + +/*! @brief I2C slave handle typedef. */ +typedef struct _i2c_slave_handle i2c_slave_handle_t; + +/*! @brief I2C slave user configuration. */ +typedef struct _i2c_slave_config +{ + bool enableSlave; /*!< Enables the I2C peripheral at initialization time. */ + uint16_t slaveAddress; /*!< A slave address configuration. */ +} i2c_slave_config_t; + +/*! @brief I2C slave transfer structure. */ +typedef struct _i2c_slave_transfer +{ + i2c_slave_transfer_event_t event; /*!< A reason that the callback is invoked. */ + uint8_t *volatile data; /*!< A transfer buffer. */ + volatile size_t dataSize; /*!< A transfer size. */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< A number of bytes actually transferred since the start or since the last repeated + start. */ +} i2c_slave_transfer_t; + +/*! @brief I2C slave transfer callback typedef. */ +typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData); + +/*! @brief I2C slave handle structure. */ +struct _i2c_slave_handle +{ + volatile uint8_t state; /*!< A transfer state maintained during transfer. */ + i2c_slave_transfer_t transfer; /*!< I2C slave transfer copy. */ + uint32_t eventMask; /*!< A mask of enabled events. */ + i2c_slave_transfer_callback_t callback; /*!< A callback function called at the transfer event. */ + void *userData; /*!< A callback parameter passed to the callback. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and configure the I2C with master configuration. + * + * @note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can be custom filled + * or it can be set with default values by using the I2C_MasterGetDefaultConfig(). + * After calling this API, the master is ready to transfer. + * This is an example. + * @code + * i2c_master_config_t config = { + * .enableMaster = true, + * .baudRate_Bps = 100000 + * }; + * I2C_MasterInit(I2C0, &config, 12000000U); + * @endcode + * + * @param base I2C base pointer + * @param masterConfig A pointer to the master configuration structure + * @param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock. + * The I2C master module can't work unless the I2C_MasterInit is called. + * @param base I2C base pointer + */ +void I2C_MasterDeinit(I2C_Type *base); + +/*! + * @brief Sets the I2C master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterInit(). + * Use the initialized structure unchanged in the I2C_MasterInit() or modify + * the structure before calling the I2C_MasterInit(). + * This is an example. + * @code + * i2c_master_config_t config; + * I2C_MasterGetDefaultConfig(&config); + * @endcode + * @param masterConfig A pointer to the master configuration structure. +*/ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and initialize the I2C with the slave configuration. + * + * @note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can partly be set + * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user. + * This is an example. + * @code + * i2c_slave_config_t config = { + * .enableSlave = true, + * .slaveAddress = 0x1DU, + * }; + * I2C_SlaveInit(I2C0, &config); + * @endcode + * + * @param base I2C base pointer + * @param slaveConfig A pointer to the slave configuration structure + * @param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig); + +/*! + * @brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock. + * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock. + * @param base I2C base pointer + */ +void I2C_SlaveDeinit(I2C_Type *base); + +/*! + * @brief Sets the I2C slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveInit(). + * Modify fields of the structure before calling the I2C_SlaveInit(). + * This is an example. + * @code + * i2c_slave_config_t config; + * I2C_SlaveGetDefaultConfig(&config); + * @endcode + * @param slaveConfig A pointer to the slave configuration structure. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); + +/*! + * @brief Enables or disabless the I2C peripheral operation. + * + * @param base I2C base pointer + * @param enable Pass true to enable and false to disable the module. + */ +static inline void I2C_Enable(I2C_Type *base, bool enable) +{ + if (enable) + { + base->I2CR |= I2C_I2CR_IEN_MASK; + } + else + { + base->I2CR &= ~I2C_I2CR_IEN_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags to get the related status. + */ +static inline uint32_t I2C_MasterGetStatusFlags(I2C_Type *base) +{ + return base->I2SR; +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag. + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter can be any combination of the following values: + * @arg kI2C_ArbitrationLostFlag + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + base->I2SR = (uint8_t)statusMask; +} + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags to get the related status. + */ +static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base) +{ + return I2C_MasterGetStatusFlags(base); +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter can be any combination of the following values: + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + I2C_MasterClearStatusFlags(base, statusMask); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask); + +/*! + * @brief Disables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask); + +/* @} */ +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the I2C master transfer baud rate. + * + * @param base I2C base pointer + * @param baudRate_Bps the baud rate value in bps + * @param srcClock_Hz Source clock + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * @retval kStatus_Success Successfully send the stop signal. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base); + +/*! + * @brief Sends a REPEATED START on the I2C bus. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Performs a polling send transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag +* to issue a stop and kI2C_TransferNoStop to not send a stop. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags); + +/*! + * @brief Performs a polling receive transaction on the I2C bus. + * + * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte. + * Without stopping the bus prior for the final read, the bus issues another read, resulting + * in garbage data being read into the data register. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag +* to issue a stop and kI2C_TransferNoStop to not send a stop. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags); + +/*! + * @brief Performs a polling send transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transaction on the I2C bus. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + */ +void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * @param base I2C peripheral base address. + * @param xfer Pointer to the transfer structure. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * @note Calling the API returns immediately after transfer initiates. The user needs + * to call I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer + * is finished. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + */ +void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_master_handle_t structure. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Aborts the slave transfer. + * + * @note This API can be called at any time to stop slave for handling the bus events. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Slave interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ + +#endif /* _FSL_I2C_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_iomuxc.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_iomuxc.h new file mode 100644 index 0000000000..8f314567f7 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_iomuxc.h @@ -0,0 +1,1151 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.0. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @name Pin function ID */ +/*@{*/ +/*! @brief The pin function ID is a tuple of */ +#define IOMUXC_SNVS_BOOT_MODE0_GPIO5_IO10 0x02290000U, 0x5U, 0x00000000U, 0x0U, 0x02290044U +#define IOMUXC_SNVS_BOOT_MODE1_GPIO5_IO11 0x02290004U, 0x5U, 0x00000000U, 0x0U, 0x02290048U +#define IOMUXC_SNVS_SNVS_TAMPER0_GPIO5_IO00 0x02290008U, 0x5U, 0x00000000U, 0x0U, 0x0229004CU +#define IOMUXC_SNVS_SNVS_TAMPER1_GPIO5_IO01 0x0229000CU, 0x5U, 0x00000000U, 0x0U, 0x02290050U +#define IOMUXC_SNVS_SNVS_TAMPER2_GPIO5_IO02 0x02290010U, 0x5U, 0x00000000U, 0x0U, 0x02290054U +#define IOMUXC_SNVS_SNVS_TAMPER3_GPIO5_IO03 0x02290014U, 0x5U, 0x00000000U, 0x0U, 0x02290058U +#define IOMUXC_SNVS_SNVS_TAMPER4_GPIO5_IO04 0x02290018U, 0x5U, 0x00000000U, 0x0U, 0x0229005CU +#define IOMUXC_SNVS_SNVS_TAMPER5_GPIO5_IO05 0x0229001CU, 0x5U, 0x00000000U, 0x0U, 0x02290060U +#define IOMUXC_SNVS_SNVS_TAMPER6_GPIO5_IO06 0x02290020U, 0x5U, 0x00000000U, 0x0U, 0x02290064U +#define IOMUXC_SNVS_SNVS_TAMPER7_GPIO5_IO07 0x02290024U, 0x5U, 0x00000000U, 0x0U, 0x02290068U +#define IOMUXC_SNVS_SNVS_TAMPER8_GPIO5_IO08 0x02290028U, 0x5U, 0x00000000U, 0x0U, 0x0229006CU +#define IOMUXC_SNVS_SNVS_TAMPER9_GPIO5_IO09 0x0229002CU, 0x5U, 0x00000000U, 0x0U, 0x02290070U +#define IOMUXC_SNVS_TEST_MODE 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x02290030U +#define IOMUXC_SNVS_POR_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x02290034U +#define IOMUXC_SNVS_ONOFF 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x02290038U +#define IOMUXC_SNVS_SNVS_PMIC_ON_REQ 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x0229003CU +#define IOMUXC_SNVS_CCM_PMIC_STBY_REQ 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x02290040U +#define IOMUXC_JTAG_MOD_SJC_MOD 0x020E0044U, 0x0U, 0x00000000U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_GPT2_CLK 0x020E0044U, 0x1U, 0x020E05A0U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_SPDIF_OUT 0x020E0044U, 0x2U, 0x00000000U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_ENET1_REF_CLK_25M 0x020E0044U, 0x3U, 0x00000000U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_CCM_PMIC_RDY 0x020E0044U, 0x4U, 0x020E04C0U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_GPIO1_IO10 0x020E0044U, 0x5U, 0x00000000U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_SDMA_EXT_EVENT00 0x020E0044U, 0x6U, 0x020E0610U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_TMS_SJC_TMS 0x020E0048U, 0x0U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_GPT2_CAPTURE1 0x020E0048U, 0x1U, 0x020E0598U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_SAI2_MCLK 0x020E0048U, 0x2U, 0x020E05F0U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_CCM_CLKO1 0x020E0048U, 0x3U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_CCM_WAIT 0x020E0048U, 0x4U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_GPIO1_IO11 0x020E0048U, 0x5U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_SDMA_EXT_EVENT01 0x020E0048U, 0x6U, 0x020E0614U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_EPIT1_OUT 0x020E0048U, 0x8U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TDO_SJC_TDO 0x020E004CU, 0x0U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_GPT2_CAPTURE2 0x020E004CU, 0x1U, 0x020E059CU, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_SAI2_TX_SYNC 0x020E004CU, 0x2U, 0x020E05FCU, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_CCM_CLKO2 0x020E004CU, 0x3U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_CCM_STOP 0x020E004CU, 0x4U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_GPIO1_IO12 0x020E004CU, 0x5U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_MQS_RIGHT 0x020E004CU, 0x6U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_EPIT2_OUT 0x020E004CU, 0x8U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDI_SJC_TDI 0x020E0050U, 0x0U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_GPT2_COMPARE1 0x020E0050U, 0x1U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_SAI2_TX_BCLK 0x020E0050U, 0x2U, 0x020E05F8U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_PWM6_OUT 0x020E0050U, 0x4U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_GPIO1_IO13 0x020E0050U, 0x5U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_MQS_LEFT 0x020E0050U, 0x6U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TCK_SJC_TCK 0x020E0054U, 0x0U, 0x00000000U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TCK_GPT2_COMPARE2 0x020E0054U, 0x1U, 0x00000000U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TCK_SAI2_RX_DATA 0x020E0054U, 0x2U, 0x020E05F4U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TCK_PWM7_OUT 0x020E0054U, 0x4U, 0x00000000U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TCK_GPIO1_IO14 0x020E0054U, 0x5U, 0x00000000U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TRST_B_SJC_TRSTB 0x020E0058U, 0x0U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_JTAG_TRST_B_GPT2_COMPARE3 0x020E0058U, 0x1U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_JTAG_TRST_B_SAI2_TX_DATA 0x020E0058U, 0x2U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_JTAG_TRST_B_PWM8_OUT 0x020E0058U, 0x4U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_JTAG_TRST_B_GPIO1_IO15 0x020E0058U, 0x5U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_GPIO1_IO00_I2C2_SCL 0x020E005CU, 0x0U, 0x020E05ACU, 0x1U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_GPT1_CAPTURE1 0x020E005CU, 0x1U, 0x020E058CU, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_ANATOP_OTG1_ID 0x020E005CU, 0x2U, 0x020E04B8U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_ENET1_REF_CLK1 0x020E005CU, 0x3U, 0x020E0574U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_MQS_RIGHT 0x020E005CU, 0x4U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x020E005CU, 0x5U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_ENET1_1588_EVENT0_IN 0x020E005CU, 0x6U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_SRC_SYSTEM_RESET 0x020E005CU, 0x7U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_WDOG3_WDOG_B 0x020E005CU, 0x8U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO01_I2C2_SDA 0x020E0060U, 0x0U, 0x020E05B0U, 0x1U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_GPT1_COMPARE1 0x020E0060U, 0x1U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_USB_OTG1_OC 0x020E0060U, 0x2U, 0x020E0664U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_ENET2_REF_CLK2 0x020E0060U, 0x3U, 0x020E057CU, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_MQS_LEFT 0x020E0060U, 0x4U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x020E0060U, 0x5U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_ENET1_1588_EVENT0_OUT 0x020E0060U, 0x6U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_SRC_EARLY_RESET 0x020E0060U, 0x7U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_WDOG1_WDOG_B 0x020E0060U, 0x8U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO02_I2C1_SCL 0x020E0064U, 0x0U, 0x020E05A4U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_GPT1_COMPARE2 0x020E0064U, 0x1U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_USB_OTG2_PWR 0x020E0064U, 0x2U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_ENET1_REF_CLK_25M 0x020E0064U, 0x3U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_USDHC1_WP 0x020E0064U, 0x4U, 0x020E066CU, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x020E0064U, 0x5U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_SDMA_EXT_EVENT00 0x020E0064U, 0x6U, 0x020E0610U, 0x1U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_SRC_ANY_PU_RESET 0x020E0064U, 0x7U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_UART1_TX 0x020E0064U, 0x8U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_UART1_RX 0x020E0064U, 0x8U, 0x020E0624U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO03_I2C1_SDA 0x020E0068U, 0x0U, 0x020E05A8U, 0x1U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_GPT1_COMPARE3 0x020E0068U, 0x1U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_USB_OTG2_OC 0x020E0068U, 0x2U, 0x020E0660U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_USDHC1_CD_B 0x020E0068U, 0x4U, 0x020E0668U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x020E0068U, 0x5U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_CCM_DI0_EXT_CLK 0x020E0068U, 0x6U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_SRC_TESTER_ACK 0x020E0068U, 0x7U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_UART1_RX 0x020E0068U, 0x8U, 0x020E0624U, 0x1U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_UART1_TX 0x020E0068U, 0x8U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO04_ENET1_REF_CLK1 0x020E006CU, 0x0U, 0x020E0574U, 0x1U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_PWM3_OUT 0x020E006CU, 0x1U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_USB_OTG1_PWR 0x020E006CU, 0x2U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_USDHC1_RESET_B 0x020E006CU, 0x4U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x020E006CU, 0x5U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_ENET2_1588_EVENT0_IN 0x020E006CU, 0x6U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_UART5_TX 0x020E006CU, 0x8U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_UART5_RX 0x020E006CU, 0x8U, 0x020E0644U, 0x2U, 0x020E02F8U +#define IOMUXC_GPIO1_IO05_ENET2_REF_CLK2 0x020E0070U, 0x0U, 0x020E057CU, 0x1U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_PWM4_OUT 0x020E0070U, 0x1U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_ANATOP_OTG2_ID 0x020E0070U, 0x2U, 0x020E04BCU, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_CSI_FIELD 0x020E0070U, 0x3U, 0x020E0530U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_USDHC1_VSELECT 0x020E0070U, 0x4U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x020E0070U, 0x5U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_ENET2_1588_EVENT0_OUT 0x020E0070U, 0x6U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_UART5_RX 0x020E0070U, 0x8U, 0x020E0644U, 0x3U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_UART5_TX 0x020E0070U, 0x8U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO06_ENET1_MDIO 0x020E0074U, 0x0U, 0x020E0578U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_ENET2_MDIO 0x020E0074U, 0x1U, 0x020E0580U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_USB_OTG_PWR_WAKE 0x020E0074U, 0x2U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_CSI_MCLK 0x020E0074U, 0x3U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_USDHC2_WP 0x020E0074U, 0x4U, 0x020E069CU, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x020E0074U, 0x5U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_CCM_WAIT 0x020E0074U, 0x6U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_CCM_REF_EN_B 0x020E0074U, 0x7U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_UART1_CTS_B 0x020E0074U, 0x8U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_UART1_RTS_B 0x020E0074U, 0x8U, 0x020E0620U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO07_ENET1_MDC 0x020E0078U, 0x0U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_ENET2_MDC 0x020E0078U, 0x1U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_USB_OTG_HOST_MODE 0x020E0078U, 0x2U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_CSI_PIXCLK 0x020E0078U, 0x3U, 0x020E0528U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_USDHC2_CD_B 0x020E0078U, 0x4U, 0x020E0674U, 0x1U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x020E0078U, 0x5U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_CCM_STOP 0x020E0078U, 0x6U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_UART1_RTS_B 0x020E0078U, 0x8U, 0x020E0620U, 0x1U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_UART1_CTS_B 0x020E0078U, 0x8U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO08_PWM1_OUT 0x020E007CU, 0x0U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_WDOG1_WDOG_B 0x020E007CU, 0x1U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_SPDIF_OUT 0x020E007CU, 0x2U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_CSI_VSYNC 0x020E007CU, 0x3U, 0x020E052CU, 0x1U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_USDHC2_VSELECT 0x020E007CU, 0x4U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x020E007CU, 0x5U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_CCM_PMIC_RDY 0x020E007CU, 0x6U, 0x020E04C0U, 0x1U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_UART5_RTS_B 0x020E007CU, 0x8U, 0x020E0640U, 0x1U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_UART5_CTS_B 0x020E007CU, 0x8U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO09_PWM2_OUT 0x020E0080U, 0x0U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_WDOG1_WDOG_ANY 0x020E0080U, 0x1U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_SPDIF_IN 0x020E0080U, 0x2U, 0x020E0618U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_CSI_HSYNC 0x020E0080U, 0x3U, 0x020E0524U, 0x1U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_USDHC2_RESET_B 0x020E0080U, 0x4U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x020E0080U, 0x5U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_USDHC1_RESET_B 0x020E0080U, 0x6U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_UART5_CTS_B 0x020E0080U, 0x8U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_UART5_RTS_B 0x020E0080U, 0x8U, 0x020E0640U, 0x2U, 0x020E030CU +#define IOMUXC_UART1_TX_DATA_UART1_TX 0x020E0084U, 0x0U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_UART1_RX 0x020E0084U, 0x0U, 0x020E0624U, 0x2U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_ENET1_RDATA02 0x020E0084U, 0x1U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_I2C3_SCL 0x020E0084U, 0x2U, 0x020E05B4U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_CSI_DATA02 0x020E0084U, 0x3U, 0x020E04C4U, 0x1U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_GPT1_COMPARE1 0x020E0084U, 0x4U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_GPIO1_IO16 0x020E0084U, 0x5U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_SPDIF_OUT 0x020E0084U, 0x8U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_UART5_TX 0x020E0084U, 0x9U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_UART5_RX 0x020E0084U, 0x9U, 0x020E0644U, 0x4U, 0x020E0310U +#define IOMUXC_UART1_RX_DATA_UART1_RX 0x020E0088U, 0x0U, 0x020E0624U, 0x3U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_UART1_TX 0x020E0088U, 0x0U, 0x00000000U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_ENET1_RDATA03 0x020E0088U, 0x1U, 0x00000000U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_I2C3_SDA 0x020E0088U, 0x2U, 0x020E05B8U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_CSI_DATA03 0x020E0088U, 0x3U, 0x020E04C8U, 0x1U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_GPT1_CLK 0x020E0088U, 0x4U, 0x020E0594U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_GPIO1_IO17 0x020E0088U, 0x5U, 0x00000000U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_SPDIF_IN 0x020E0088U, 0x8U, 0x020E0618U, 0x1U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_UART5_RX 0x020E0088U, 0x9U, 0x020E0644U, 0x5U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_UART5_TX 0x020E0088U, 0x9U, 0x00000000U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_CTS_B_UART1_CTS_B 0x020E008CU, 0x0U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_UART1_RTS_B 0x020E008CU, 0x0U, 0x020E0620U, 0x2U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_ENET1_RX_CLK 0x020E008CU, 0x1U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_USDHC1_WP 0x020E008CU, 0x2U, 0x020E066CU, 0x1U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_CSI_DATA04 0x020E008CU, 0x3U, 0x020E04D8U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_ENET2_1588_EVENT1_IN 0x020E008CU, 0x4U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_GPIO1_IO18 0x020E008CU, 0x5U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_USDHC2_WP 0x020E008CU, 0x8U, 0x020E069CU, 0x1U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_UART5_CTS_B 0x020E008CU, 0x9U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_UART5_RTS_B 0x020E008CU, 0x9U, 0x020E0640U, 0x3U, 0x020E0318U +#define IOMUXC_UART1_RTS_B_UART1_RTS_B 0x020E0090U, 0x0U, 0x020E0620U, 0x3U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_UART1_CTS_B 0x020E0090U, 0x0U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_ENET1_TX_ER 0x020E0090U, 0x1U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_USDHC1_CD_B 0x020E0090U, 0x2U, 0x020E0668U, 0x1U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_CSI_DATA05 0x020E0090U, 0x3U, 0x020E04CCU, 0x1U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_ENET2_1588_EVENT1_OUT 0x020E0090U, 0x4U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_GPIO1_IO19 0x020E0090U, 0x5U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_USDHC2_CD_B 0x020E0090U, 0x8U, 0x020E0674U, 0x2U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_UART5_RTS_B 0x020E0090U, 0x9U, 0x020E0640U, 0x4U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_UART5_CTS_B 0x020E0090U, 0x9U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART2_TX_DATA_UART2_TX 0x020E0094U, 0x0U, 0x00000000U, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_UART2_RX 0x020E0094U, 0x0U, 0x020E062CU, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_ENET1_TDATA02 0x020E0094U, 0x1U, 0x00000000U, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_I2C4_SCL 0x020E0094U, 0x2U, 0x020E05BCU, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_CSI_DATA06 0x020E0094U, 0x3U, 0x020E04DCU, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_GPT1_CAPTURE1 0x020E0094U, 0x4U, 0x020E058CU, 0x1U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_GPIO1_IO20 0x020E0094U, 0x5U, 0x00000000U, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_ECSPI3_SS0 0x020E0094U, 0x8U, 0x020E0560U, 0x0U, 0x020E0320U +#define IOMUXC_UART2_RX_DATA_UART2_RX 0x020E0098U, 0x0U, 0x020E062CU, 0x1U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_UART2_TX 0x020E0098U, 0x0U, 0x00000000U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_ENET1_TDATA03 0x020E0098U, 0x1U, 0x00000000U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_I2C4_SDA 0x020E0098U, 0x2U, 0x020E05C0U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_CSI_DATA07 0x020E0098U, 0x3U, 0x020E04E0U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_GPT1_CAPTURE2 0x020E0098U, 0x4U, 0x020E0590U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_GPIO1_IO21 0x020E0098U, 0x5U, 0x00000000U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_SJC_DONE 0x020E0098U, 0x7U, 0x00000000U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_ECSPI3_SCLK 0x020E0098U, 0x8U, 0x020E0554U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_CTS_B_UART2_CTS_B 0x020E009CU, 0x0U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_UART2_RTS_B 0x020E009CU, 0x0U, 0x020E0628U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_ENET1_CRS 0x020E009CU, 0x1U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_FLEXCAN2_TX 0x020E009CU, 0x2U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_CSI_DATA08 0x020E009CU, 0x3U, 0x020E04E4U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_GPT1_COMPARE2 0x020E009CU, 0x4U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_GPIO1_IO22 0x020E009CU, 0x5U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_SJC_DE_B 0x020E009CU, 0x7U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_ECSPI3_MOSI 0x020E009CU, 0x8U, 0x020E055CU, 0x0U, 0x020E0328U +#define IOMUXC_UART2_RTS_B_UART2_RTS_B 0x020E00A0U, 0x0U, 0x020E0628U, 0x1U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_UART2_CTS_B 0x020E00A0U, 0x0U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_ENET1_COL 0x020E00A0U, 0x1U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_FLEXCAN2_RX 0x020E00A0U, 0x2U, 0x020E0588U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_CSI_DATA09 0x020E00A0U, 0x3U, 0x020E04E8U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_GPT1_COMPARE3 0x020E00A0U, 0x4U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_GPIO1_IO23 0x020E00A0U, 0x5U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_SJC_FAIL 0x020E00A0U, 0x7U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_ECSPI3_MISO 0x020E00A0U, 0x8U, 0x020E0558U, 0x0U, 0x020E032CU +#define IOMUXC_UART3_TX_DATA_UART3_TX 0x020E00A4U, 0x0U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_UART3_RX 0x020E00A4U, 0x0U, 0x020E0634U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_ENET2_RDATA02 0x020E00A4U, 0x1U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_CSI_DATA01 0x020E00A4U, 0x3U, 0x020E04D4U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_UART2_CTS_B 0x020E00A4U, 0x4U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_UART2_RTS_B 0x020E00A4U, 0x4U, 0x020E0628U, 0x2U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_GPIO1_IO24 0x020E00A4U, 0x5U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_SJC_JTAG_ACT 0x020E00A4U, 0x7U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_ANATOP_OTG1_ID 0x020E00A4U, 0x8U, 0x020E04B8U, 0x1U, 0x020E0330U +#define IOMUXC_UART3_RX_DATA_UART3_RX 0x020E00A8U, 0x0U, 0x020E0634U, 0x1U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_UART3_TX 0x020E00A8U, 0x0U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_ENET2_RDATA03 0x020E00A8U, 0x1U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_CSI_DATA00 0x020E00A8U, 0x3U, 0x020E04D0U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_UART2_RTS_B 0x020E00A8U, 0x4U, 0x020E0628U, 0x3U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_UART2_CTS_B 0x020E00A8U, 0x4U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_GPIO1_IO25 0x020E00A8U, 0x5U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_EPIT1_OUT 0x020E00A8U, 0x8U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_CTS_B_UART3_CTS_B 0x020E00ACU, 0x0U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_UART3_RTS_B 0x020E00ACU, 0x0U, 0x020E0630U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_ENET2_RX_CLK 0x020E00ACU, 0x1U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_FLEXCAN1_TX 0x020E00ACU, 0x2U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_CSI_DATA10 0x020E00ACU, 0x3U, 0x020E04ECU, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_ENET1_1588_EVENT1_IN 0x020E00ACU, 0x4U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_GPIO1_IO26 0x020E00ACU, 0x5U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_EPIT2_OUT 0x020E00ACU, 0x8U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_RTS_B_UART3_RTS_B 0x020E00B0U, 0x0U, 0x020E0630U, 0x1U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_UART3_CTS_B 0x020E00B0U, 0x0U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_ENET2_TX_ER 0x020E00B0U, 0x1U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_FLEXCAN1_RX 0x020E00B0U, 0x2U, 0x020E0584U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_CSI_DATA11 0x020E00B0U, 0x3U, 0x020E04F0U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_ENET1_1588_EVENT1_OUT 0x020E00B0U, 0x4U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_GPIO1_IO27 0x020E00B0U, 0x5U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_WDOG1_WDOG_B 0x020E00B0U, 0x8U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART4_TX_DATA_UART4_TX 0x020E00B4U, 0x0U, 0x00000000U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_UART4_RX 0x020E00B4U, 0x0U, 0x020E063CU, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_ENET2_TDATA02 0x020E00B4U, 0x1U, 0x00000000U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_I2C1_SCL 0x020E00B4U, 0x2U, 0x020E05A4U, 0x1U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_CSI_DATA12 0x020E00B4U, 0x3U, 0x020E04F4U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_CSU_CSU_ALARM_AUT02 0x020E00B4U, 0x4U, 0x00000000U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_GPIO1_IO28 0x020E00B4U, 0x5U, 0x00000000U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_ECSPI2_SCLK 0x020E00B4U, 0x8U, 0x020E0544U, 0x1U, 0x020E0340U +#define IOMUXC_UART4_RX_DATA_UART4_RX 0x020E00B8U, 0x0U, 0x020E063CU, 0x1U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_UART4_TX 0x020E00B8U, 0x0U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_ENET2_TDATA03 0x020E00B8U, 0x1U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_I2C1_SDA 0x020E00B8U, 0x2U, 0x020E05A8U, 0x2U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_CSI_DATA13 0x020E00B8U, 0x3U, 0x020E04F8U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_CSU_CSU_ALARM_AUT01 0x020E00B8U, 0x4U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_GPIO1_IO29 0x020E00B8U, 0x5U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_ECSPI2_SS0 0x020E00B8U, 0x8U, 0x020E0550U, 0x1U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_EPDC_PWRCTRL01 0x020E00B8U, 0x9U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART5_TX_DATA_GPIO1_IO30 0x020E00BCU, 0x5U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_ECSPI2_MOSI 0x020E00BCU, 0x8U, 0x020E054CU, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_EPDC_PWRCTRL02 0x020E00BCU, 0x9U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_UART5_TX 0x020E00BCU, 0x0U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_UART5_RX 0x020E00BCU, 0x0U, 0x020E0644U, 0x6U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_ENET2_CRS 0x020E00BCU, 0x1U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_I2C2_SCL 0x020E00BCU, 0x2U, 0x020E05ACU, 0x2U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_CSI_DATA14 0x020E00BCU, 0x3U, 0x020E04FCU, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_CSU_CSU_ALARM_AUT00 0x020E00BCU, 0x4U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_RX_DATA_UART5_RX 0x020E00C0U, 0x0U, 0x020E0644U, 0x7U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_UART5_TX 0x020E00C0U, 0x0U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_ENET2_COL 0x020E00C0U, 0x1U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_I2C2_SDA 0x020E00C0U, 0x2U, 0x020E05B0U, 0x2U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_CSI_DATA15 0x020E00C0U, 0x3U, 0x020E0500U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_CSU_CSU_INT_DEB 0x020E00C0U, 0x4U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_GPIO1_IO31 0x020E00C0U, 0x5U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_ECSPI2_MISO 0x020E00C0U, 0x8U, 0x020E0548U, 0x1U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_EPDC_PWRCTRL03 0x020E00C0U, 0x9U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_ENET1_RX_DATA0_ENET1_RDATA00 0x020E00C4U, 0x0U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_UART4_RTS_B 0x020E00C4U, 0x1U, 0x020E0638U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_UART4_CTS_B 0x020E00C4U, 0x1U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_PWM1_OUT 0x020E00C4U, 0x2U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_CSI_DATA16 0x020E00C4U, 0x3U, 0x020E0504U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_FLEXCAN1_TX 0x020E00C4U, 0x4U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_GPIO2_IO00 0x020E00C4U, 0x5U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_KPP_ROW00 0x020E00C4U, 0x6U, 0x020E05D0U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_USDHC1_LCTL 0x020E00C4U, 0x8U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_EPDC_SDCE04 0x020E00C4U, 0x9U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA1_ENET1_RDATA01 0x020E00C8U, 0x0U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_UART4_CTS_B 0x020E00C8U, 0x1U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_UART4_RTS_B 0x020E00C8U, 0x1U, 0x020E0638U, 0x1U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_PWM2_OUT 0x020E00C8U, 0x2U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_CSI_DATA17 0x020E00C8U, 0x3U, 0x020E0508U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_FLEXCAN1_RX 0x020E00C8U, 0x4U, 0x020E0584U, 0x1U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_GPIO2_IO01 0x020E00C8U, 0x5U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_KPP_COL00 0x020E00C8U, 0x6U, 0x020E05C4U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_USDHC2_LCTL 0x020E00C8U, 0x8U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_EPDC_SDCE05 0x020E00C8U, 0x9U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_EN_ENET1_RX_EN 0x020E00CCU, 0x0U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_UART5_RTS_B 0x020E00CCU, 0x1U, 0x020E0640U, 0x5U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_UART5_CTS_B 0x020E00CCU, 0x1U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_CSI_DATA18 0x020E00CCU, 0x3U, 0x020E050CU, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_FLEXCAN2_TX 0x020E00CCU, 0x4U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_GPIO2_IO02 0x020E00CCU, 0x5U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_KPP_ROW01 0x020E00CCU, 0x6U, 0x020E05D4U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_USDHC1_VSELECT 0x020E00CCU, 0x8U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_EPDC_SDCE06 0x020E00CCU, 0x9U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_TX_DATA0_ENET1_TDATA00 0x020E00D0U, 0x0U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_UART5_CTS_B 0x020E00D0U, 0x1U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_UART5_RTS_B 0x020E00D0U, 0x1U, 0x020E0640U, 0x6U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_CSI_DATA19 0x020E00D0U, 0x3U, 0x020E0510U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_FLEXCAN2_RX 0x020E00D0U, 0x4U, 0x020E0588U, 0x1U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_GPIO2_IO03 0x020E00D0U, 0x5U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_KPP_COL01 0x020E00D0U, 0x6U, 0x020E05C8U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_USDHC2_VSELECT 0x020E00D0U, 0x8U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_EPDC_SDCE07 0x020E00D0U, 0x9U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA1_ENET1_TDATA01 0x020E00D4U, 0x0U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_UART6_CTS_B 0x020E00D4U, 0x1U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_UART6_RTS_B 0x020E00D4U, 0x1U, 0x020E0648U, 0x2U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_PWM5_OUT 0x020E00D4U, 0x2U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_CSI_DATA20 0x020E00D4U, 0x3U, 0x020E0514U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_ENET2_MDIO 0x020E00D4U, 0x4U, 0x020E0580U, 0x1U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_GPIO2_IO04 0x020E00D4U, 0x5U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_KPP_ROW02 0x020E00D4U, 0x6U, 0x020E05D8U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_WDOG1_WDOG_RST_B_DEB 0x020E00D4U, 0x8U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_EPDC_SDCE08 0x020E00D4U, 0x9U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_EN_ENET1_TX_EN 0x020E00D8U, 0x0U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_UART6_RTS_B 0x020E00D8U, 0x1U, 0x020E0648U, 0x3U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_UART6_CTS_B 0x020E00D8U, 0x1U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_PWM6_OUT 0x020E00D8U, 0x2U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_CSI_DATA21 0x020E00D8U, 0x3U, 0x020E0518U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_ENET2_MDC 0x020E00D8U, 0x4U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_GPIO2_IO05 0x020E00D8U, 0x5U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_KPP_COL02 0x020E00D8U, 0x6U, 0x020E05CCU, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_WDOG2_WDOG_RST_B_DEB 0x020E00D8U, 0x8U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_EPDC_SDCE09 0x020E00D8U, 0x9U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_CLK_ENET1_TX_CLK 0x020E00DCU, 0x0U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_UART7_CTS_B 0x020E00DCU, 0x1U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_UART7_RTS_B 0x020E00DCU, 0x1U, 0x020E0650U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_PWM7_OUT 0x020E00DCU, 0x2U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_CSI_DATA22 0x020E00DCU, 0x3U, 0x020E051CU, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_ENET1_REF_CLK1 0x020E00DCU, 0x4U, 0x020E0574U, 0x2U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_GPIO2_IO06 0x020E00DCU, 0x5U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_KPP_ROW03 0x020E00DCU, 0x6U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_GPT1_CLK 0x020E00DCU, 0x8U, 0x020E0594U, 0x1U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_EPDC_SDOED 0x020E00DCU, 0x9U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_RX_ER_ENET1_RX_ER 0x020E00E0U, 0x0U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_UART7_RTS_B 0x020E00E0U, 0x1U, 0x020E0650U, 0x1U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_UART7_CTS_B 0x020E00E0U, 0x1U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_PWM8_OUT 0x020E00E0U, 0x2U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_CSI_DATA23 0x020E00E0U, 0x3U, 0x020E0520U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_EIM_CRE 0x020E00E0U, 0x4U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_GPIO2_IO07 0x020E00E0U, 0x5U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_KPP_COL03 0x020E00E0U, 0x6U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_GPT1_CAPTURE2 0x020E00E0U, 0x8U, 0x020E0590U, 0x1U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_EPDC_SDOEZ 0x020E00E0U, 0x9U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET2_RX_DATA0_ENET2_RDATA00 0x020E00E4U, 0x0U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_UART6_TX 0x020E00E4U, 0x1U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_UART6_RX 0x020E00E4U, 0x1U, 0x020E064CU, 0x1U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_I2C3_SCL 0x020E00E4U, 0x3U, 0x020E05B4U, 0x1U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_ENET1_MDIO 0x020E00E4U, 0x4U, 0x020E0578U, 0x1U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_GPIO2_IO08 0x020E00E4U, 0x5U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_KPP_ROW04 0x020E00E4U, 0x6U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_USB_OTG1_PWR 0x020E00E4U, 0x8U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_EPDC_SDDO08 0x020E00E4U, 0x9U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA1_ENET2_RDATA01 0x020E00E8U, 0x0U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_UART6_RX 0x020E00E8U, 0x1U, 0x020E064CU, 0x2U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_UART6_TX 0x020E00E8U, 0x1U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_I2C3_SDA 0x020E00E8U, 0x3U, 0x020E05B8U, 0x1U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_ENET1_MDC 0x020E00E8U, 0x4U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_GPIO2_IO09 0x020E00E8U, 0x5U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_KPP_COL04 0x020E00E8U, 0x6U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_USB_OTG1_OC 0x020E00E8U, 0x8U, 0x020E0664U, 0x1U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_EPDC_SDDO09 0x020E00E8U, 0x9U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_EN_ENET2_RX_EN 0x020E00ECU, 0x0U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_UART7_TX 0x020E00ECU, 0x1U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_UART7_RX 0x020E00ECU, 0x1U, 0x020E0654U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_I2C4_SCL 0x020E00ECU, 0x3U, 0x020E05BCU, 0x1U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_EIM_ADDR26 0x020E00ECU, 0x4U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_GPIO2_IO10 0x020E00ECU, 0x5U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_KPP_ROW05 0x020E00ECU, 0x6U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_ENET1_REF_CLK_25M 0x020E00ECU, 0x8U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_EPDC_SDDO10 0x020E00ECU, 0x9U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_TX_DATA0_ENET2_TDATA00 0x020E00F0U, 0x0U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_UART7_RX 0x020E00F0U, 0x1U, 0x020E0654U, 0x1U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_UART7_TX 0x020E00F0U, 0x1U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_I2C4_SDA 0x020E00F0U, 0x3U, 0x020E05C0U, 0x1U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_EIM_EB_B02 0x020E00F0U, 0x4U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_GPIO2_IO11 0x020E00F0U, 0x5U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_KPP_COL05 0x020E00F0U, 0x6U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_EPDC_SDDO11 0x020E00F0U, 0x9U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA1_ENET2_TDATA01 0x020E00F4U, 0x0U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_UART8_TX 0x020E00F4U, 0x1U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_UART8_RX 0x020E00F4U, 0x1U, 0x020E065CU, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_ECSPI4_SCLK 0x020E00F4U, 0x3U, 0x020E0564U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_EIM_EB_B03 0x020E00F4U, 0x4U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_GPIO2_IO12 0x020E00F4U, 0x5U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_KPP_ROW06 0x020E00F4U, 0x6U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_USB_OTG2_PWR 0x020E00F4U, 0x8U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_EPDC_SDDO12 0x020E00F4U, 0x9U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_EN_ENET2_TX_EN 0x020E00F8U, 0x0U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_UART8_RX 0x020E00F8U, 0x1U, 0x020E065CU, 0x1U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_UART8_TX 0x020E00F8U, 0x1U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_ECSPI4_MOSI 0x020E00F8U, 0x3U, 0x020E056CU, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_EIM_ACLK_FREERUN 0x020E00F8U, 0x4U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_GPIO2_IO13 0x020E00F8U, 0x5U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_KPP_COL06 0x020E00F8U, 0x6U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_USB_OTG2_OC 0x020E00F8U, 0x8U, 0x020E0660U, 0x1U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_EPDC_SDDO13 0x020E00F8U, 0x9U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_CLK_ENET2_TX_CLK 0x020E00FCU, 0x0U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_UART8_CTS_B 0x020E00FCU, 0x1U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_UART8_RTS_B 0x020E00FCU, 0x1U, 0x020E0658U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_ECSPI4_MISO 0x020E00FCU, 0x3U, 0x020E0568U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_ENET2_REF_CLK2 0x020E00FCU, 0x4U, 0x020E057CU, 0x2U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_GPIO2_IO14 0x020E00FCU, 0x5U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_KPP_ROW07 0x020E00FCU, 0x6U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_ANATOP_OTG2_ID 0x020E00FCU, 0x8U, 0x020E04BCU, 0x1U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_EPDC_SDDO14 0x020E00FCU, 0x9U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_RX_ER_ENET2_RX_ER 0x020E0100U, 0x0U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_UART8_RTS_B 0x020E0100U, 0x1U, 0x020E0658U, 0x1U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_UART8_CTS_B 0x020E0100U, 0x1U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_ECSPI4_SS0 0x020E0100U, 0x3U, 0x020E0570U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_EIM_ADDR25 0x020E0100U, 0x4U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_GPIO2_IO15 0x020E0100U, 0x5U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_KPP_COL07 0x020E0100U, 0x6U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_WDOG1_WDOG_ANY 0x020E0100U, 0x8U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_EPDC_SDDO15 0x020E0100U, 0x9U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_LCD_CLK_LCDIF_CLK 0x020E0104U, 0x0U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_LCDIF_WR_RWN 0x020E0104U, 0x1U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_UART4_TX 0x020E0104U, 0x2U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_UART4_RX 0x020E0104U, 0x2U, 0x020E063CU, 0x2U, 0x020E0390U +#define IOMUXC_LCD_CLK_SAI3_MCLK 0x020E0104U, 0x3U, 0x020E0600U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_EIM_CS2_B 0x020E0104U, 0x4U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_GPIO3_IO00 0x020E0104U, 0x5U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_WDOG1_WDOG_RST_B_DEB 0x020E0104U, 0x8U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_EPDC_SDCLK 0x020E0104U, 0x9U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_ENABLE_LCDIF_ENABLE 0x020E0108U, 0x0U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_LCDIF_RD_E 0x020E0108U, 0x1U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_UART4_RX 0x020E0108U, 0x2U, 0x020E063CU, 0x3U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_UART4_TX 0x020E0108U, 0x2U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_SAI3_TX_SYNC 0x020E0108U, 0x3U, 0x020E060CU, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_EIM_CS3_B 0x020E0108U, 0x4U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_GPIO3_IO01 0x020E0108U, 0x5U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_ECSPI2_RDY 0x020E0108U, 0x8U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_EPDC_SDLE 0x020E0108U, 0x9U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_HSYNC_LCDIF_HSYNC 0x020E010CU, 0x0U, 0x020E05DCU, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_LCDIF_RS 0x020E010CU, 0x1U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_UART4_CTS_B 0x020E010CU, 0x2U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_UART4_RTS_B 0x020E010CU, 0x2U, 0x020E0638U, 0x2U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_SAI3_TX_BCLK 0x020E010CU, 0x3U, 0x020E0608U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_WDOG3_WDOG_RST_B_DEB 0x020E010CU, 0x4U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_GPIO3_IO02 0x020E010CU, 0x5U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_ECSPI2_SS1 0x020E010CU, 0x8U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_EPDC_SDOE 0x020E010CU, 0x9U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_VSYNC_LCDIF_VSYNC 0x020E0110U, 0x0U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_LCDIF_BUSY 0x020E0110U, 0x1U, 0x020E05DCU, 0x1U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_UART4_RTS_B 0x020E0110U, 0x2U, 0x020E0638U, 0x3U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_UART4_CTS_B 0x020E0110U, 0x2U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_SAI3_RX_DATA 0x020E0110U, 0x3U, 0x020E0604U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_WDOG2_WDOG_B 0x020E0110U, 0x4U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_GPIO3_IO03 0x020E0110U, 0x5U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_ECSPI2_SS2 0x020E0110U, 0x8U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_EPDC_SDCE00 0x020E0110U, 0x9U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_RESET_LCDIF_RESET 0x020E0114U, 0x0U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_LCDIF_CS 0x020E0114U, 0x1U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_CA7_MX6ULL_EVENTI 0x020E0114U, 0x2U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_SAI3_TX_DATA 0x020E0114U, 0x3U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_WDOG1_WDOG_ANY 0x020E0114U, 0x4U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_GPIO3_IO04 0x020E0114U, 0x5U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_ECSPI2_SS3 0x020E0114U, 0x8U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_EPDC_GDOE 0x020E0114U, 0x9U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_DATA00_LCDIF_DATA00 0x020E0118U, 0x0U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_PWM1_OUT 0x020E0118U, 0x1U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_ENET1_1588_EVENT2_IN 0x020E0118U, 0x3U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_I2C3_SDA 0x020E0118U, 0x4U, 0x020E05B8U, 0x2U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_GPIO3_IO05 0x020E0118U, 0x5U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_SRC_BT_CFG00 0x020E0118U, 0x6U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_SAI1_MCLK 0x020E0118U, 0x8U, 0x020E05E0U, 0x1U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_EPDC_SDDO00 0x020E0118U, 0x9U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA01_LCDIF_DATA01 0x020E011CU, 0x0U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_PWM2_OUT 0x020E011CU, 0x1U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_ENET1_1588_EVENT2_OUT 0x020E011CU, 0x3U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_I2C3_SCL 0x020E011CU, 0x4U, 0x020E05B4U, 0x2U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_GPIO3_IO06 0x020E011CU, 0x5U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_SRC_BT_CFG01 0x020E011CU, 0x6U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_SAI1_TX_SYNC 0x020E011CU, 0x8U, 0x020E05ECU, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_EPDC_SDDO01 0x020E011CU, 0x9U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA02_LCDIF_DATA02 0x020E0120U, 0x0U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_PWM3_OUT 0x020E0120U, 0x1U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_ENET1_1588_EVENT3_IN 0x020E0120U, 0x3U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_I2C4_SDA 0x020E0120U, 0x4U, 0x020E05C0U, 0x2U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_GPIO3_IO07 0x020E0120U, 0x5U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_SRC_BT_CFG02 0x020E0120U, 0x6U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_SAI1_TX_BCLK 0x020E0120U, 0x8U, 0x020E05E8U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_EPDC_SDDO02 0x020E0120U, 0x9U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA03_LCDIF_DATA03 0x020E0124U, 0x0U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_PWM4_OUT 0x020E0124U, 0x1U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_ENET1_1588_EVENT3_OUT 0x020E0124U, 0x3U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_I2C4_SCL 0x020E0124U, 0x4U, 0x020E05BCU, 0x2U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_GPIO3_IO08 0x020E0124U, 0x5U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_SRC_BT_CFG03 0x020E0124U, 0x6U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_SAI1_RX_DATA 0x020E0124U, 0x8U, 0x020E05E4U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_EPDC_SDDO03 0x020E0124U, 0x9U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA04_LCDIF_DATA04 0x020E0128U, 0x0U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_UART8_CTS_B 0x020E0128U, 0x1U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_UART8_RTS_B 0x020E0128U, 0x1U, 0x020E0658U, 0x2U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_ENET2_1588_EVENT2_IN 0x020E0128U, 0x3U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_SPDIF_SR_CLK 0x020E0128U, 0x4U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_GPIO3_IO09 0x020E0128U, 0x5U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_SRC_BT_CFG04 0x020E0128U, 0x6U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_SAI1_TX_DATA 0x020E0128U, 0x8U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_EPDC_SDDO04 0x020E0128U, 0x9U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA05_LCDIF_DATA05 0x020E012CU, 0x0U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_UART8_RTS_B 0x020E012CU, 0x1U, 0x020E0658U, 0x3U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_UART8_CTS_B 0x020E012CU, 0x1U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_ENET2_1588_EVENT2_OUT 0x020E012CU, 0x3U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_SPDIF_OUT 0x020E012CU, 0x4U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_GPIO3_IO10 0x020E012CU, 0x5U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_SRC_BT_CFG05 0x020E012CU, 0x6U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_ECSPI1_SS1 0x020E012CU, 0x8U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_EPDC_SDDO05 0x020E012CU, 0x9U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA06_LCDIF_DATA06 0x020E0130U, 0x0U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_UART7_CTS_B 0x020E0130U, 0x1U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_UART7_RTS_B 0x020E0130U, 0x1U, 0x020E0650U, 0x2U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_ENET2_1588_EVENT3_IN 0x020E0130U, 0x3U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_SPDIF_LOCK 0x020E0130U, 0x4U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_GPIO3_IO11 0x020E0130U, 0x5U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_SRC_BT_CFG06 0x020E0130U, 0x6U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_ECSPI1_SS2 0x020E0130U, 0x8U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_EPDC_SDDO06 0x020E0130U, 0x9U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA07_LCDIF_DATA07 0x020E0134U, 0x0U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_UART7_RTS_B 0x020E0134U, 0x1U, 0x020E0650U, 0x3U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_UART7_CTS_B 0x020E0134U, 0x1U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_ENET2_1588_EVENT3_OUT 0x020E0134U, 0x3U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_SPDIF_EXT_CLK 0x020E0134U, 0x4U, 0x020E061CU, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_GPIO3_IO12 0x020E0134U, 0x5U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_SRC_BT_CFG07 0x020E0134U, 0x6U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_ECSPI1_SS3 0x020E0134U, 0x8U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_EPDC_SDDO07 0x020E0134U, 0x9U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA08_LCDIF_DATA08 0x020E0138U, 0x0U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_SPDIF_IN 0x020E0138U, 0x1U, 0x020E0618U, 0x2U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_CSI_DATA16 0x020E0138U, 0x3U, 0x020E0504U, 0x1U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_EIM_DATA00 0x020E0138U, 0x4U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_GPIO3_IO13 0x020E0138U, 0x5U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_SRC_BT_CFG08 0x020E0138U, 0x6U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_FLEXCAN1_TX 0x020E0138U, 0x8U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_EPDC_PWRIRQ 0x020E0138U, 0x9U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA09_LCDIF_DATA09 0x020E013CU, 0x0U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_SAI3_MCLK 0x020E013CU, 0x1U, 0x020E0600U, 0x1U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_CSI_DATA17 0x020E013CU, 0x3U, 0x020E0508U, 0x1U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_EIM_DATA01 0x020E013CU, 0x4U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_GPIO3_IO14 0x020E013CU, 0x5U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_SRC_BT_CFG09 0x020E013CU, 0x6U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_FLEXCAN1_RX 0x020E013CU, 0x8U, 0x020E0584U, 0x2U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_EPDC_PWRWAKE 0x020E013CU, 0x9U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA10_LCDIF_DATA10 0x020E0140U, 0x0U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_SAI3_RX_SYNC 0x020E0140U, 0x1U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_CSI_DATA18 0x020E0140U, 0x3U, 0x020E050CU, 0x1U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_EIM_DATA02 0x020E0140U, 0x4U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_GPIO3_IO15 0x020E0140U, 0x5U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_SRC_BT_CFG10 0x020E0140U, 0x6U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_FLEXCAN2_TX 0x020E0140U, 0x8U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_EPDC_PWRCOM 0x020E0140U, 0x9U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA11_LCDIF_DATA11 0x020E0144U, 0x0U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_SAI3_RX_BCLK 0x020E0144U, 0x1U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_CSI_DATA19 0x020E0144U, 0x3U, 0x020E0510U, 0x1U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_EIM_DATA03 0x020E0144U, 0x4U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_GPIO3_IO16 0x020E0144U, 0x5U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_SRC_BT_CFG11 0x020E0144U, 0x6U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_FLEXCAN2_RX 0x020E0144U, 0x8U, 0x020E0588U, 0x2U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_EPDC_PWRSTAT 0x020E0144U, 0x9U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA12_LCDIF_DATA12 0x020E0148U, 0x0U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_SAI3_TX_SYNC 0x020E0148U, 0x1U, 0x020E060CU, 0x1U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_CSI_DATA20 0x020E0148U, 0x3U, 0x020E0514U, 0x1U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_EIM_DATA04 0x020E0148U, 0x4U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_GPIO3_IO17 0x020E0148U, 0x5U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_SRC_BT_CFG12 0x020E0148U, 0x6U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_ECSPI1_RDY 0x020E0148U, 0x8U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_EPDC_PWRCTRL00 0x020E0148U, 0x9U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA13_LCDIF_DATA13 0x020E014CU, 0x0U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_SAI3_TX_BCLK 0x020E014CU, 0x1U, 0x020E0608U, 0x1U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_CSI_DATA21 0x020E014CU, 0x3U, 0x020E0518U, 0x1U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_EIM_DATA05 0x020E014CU, 0x4U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_GPIO3_IO18 0x020E014CU, 0x5U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_SRC_BT_CFG13 0x020E014CU, 0x6U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_USDHC2_RESET_B 0x020E014CU, 0x8U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_EPDC_BDR00 0x020E014CU, 0x9U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA14_LCDIF_DATA14 0x020E0150U, 0x0U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_SAI3_RX_DATA 0x020E0150U, 0x1U, 0x020E0604U, 0x1U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_CSI_DATA22 0x020E0150U, 0x3U, 0x020E051CU, 0x1U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_EIM_DATA06 0x020E0150U, 0x4U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_GPIO3_IO19 0x020E0150U, 0x5U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_SRC_BT_CFG14 0x020E0150U, 0x6U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_USDHC2_DATA4 0x020E0150U, 0x8U, 0x020E068CU, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_EPDC_SDSHR 0x020E0150U, 0x9U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA15_LCDIF_DATA15 0x020E0154U, 0x0U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_SAI3_TX_DATA 0x020E0154U, 0x1U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_CSI_DATA23 0x020E0154U, 0x3U, 0x020E0520U, 0x1U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_EIM_DATA07 0x020E0154U, 0x4U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_GPIO3_IO20 0x020E0154U, 0x5U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_SRC_BT_CFG15 0x020E0154U, 0x6U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_USDHC2_DATA5 0x020E0154U, 0x8U, 0x020E0690U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_EPDC_GDRL 0x020E0154U, 0x9U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA16_LCDIF_DATA16 0x020E0158U, 0x0U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_UART7_TX 0x020E0158U, 0x1U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_UART7_RX 0x020E0158U, 0x1U, 0x020E0654U, 0x2U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_CSI_DATA01 0x020E0158U, 0x3U, 0x020E04D4U, 0x1U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_EIM_DATA08 0x020E0158U, 0x4U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_GPIO3_IO21 0x020E0158U, 0x5U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_SRC_BT_CFG24 0x020E0158U, 0x6U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_USDHC2_DATA6 0x020E0158U, 0x8U, 0x020E0694U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_EPDC_GDCLK 0x020E0158U, 0x9U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA17_LCDIF_DATA17 0x020E015CU, 0x0U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_UART7_RX 0x020E015CU, 0x1U, 0x020E0654U, 0x3U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_UART7_TX 0x020E015CU, 0x1U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_CSI_DATA00 0x020E015CU, 0x3U, 0x020E04D0U, 0x1U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_EIM_DATA09 0x020E015CU, 0x4U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_GPIO3_IO22 0x020E015CU, 0x5U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_SRC_BT_CFG25 0x020E015CU, 0x6U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_USDHC2_DATA7 0x020E015CU, 0x8U, 0x020E0698U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_EPDC_GDSP 0x020E015CU, 0x9U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA18_LCDIF_DATA18 0x020E0160U, 0x0U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_PWM5_OUT 0x020E0160U, 0x1U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_CA7_MX6ULL_EVENTO 0x020E0160U, 0x2U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_CSI_DATA10 0x020E0160U, 0x3U, 0x020E04ECU, 0x1U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_EIM_DATA10 0x020E0160U, 0x4U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_GPIO3_IO23 0x020E0160U, 0x5U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_SRC_BT_CFG26 0x020E0160U, 0x6U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_USDHC2_CMD 0x020E0160U, 0x8U, 0x020E0678U, 0x1U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_EPDC_BDR01 0x020E0160U, 0x9U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA19_EIM_DATA11 0x020E0164U, 0x4U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_GPIO3_IO24 0x020E0164U, 0x5U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_SRC_BT_CFG27 0x020E0164U, 0x6U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_USDHC2_CLK 0x020E0164U, 0x8U, 0x020E0670U, 0x1U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_EPDC_VCOM00 0x020E0164U, 0x9U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_LCDIF_DATA19 0x020E0164U, 0x0U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_PWM6_OUT 0x020E0164U, 0x1U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_WDOG1_WDOG_ANY 0x020E0164U, 0x2U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_CSI_DATA11 0x020E0164U, 0x3U, 0x020E04F0U, 0x1U, 0x020E03F0U +#define IOMUXC_LCD_DATA20_EIM_DATA12 0x020E0168U, 0x4U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_GPIO3_IO25 0x020E0168U, 0x5U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_SRC_BT_CFG28 0x020E0168U, 0x6U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_USDHC2_DATA0 0x020E0168U, 0x8U, 0x020E067CU, 0x1U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_EPDC_VCOM01 0x020E0168U, 0x9U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_LCDIF_DATA20 0x020E0168U, 0x0U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_UART8_TX 0x020E0168U, 0x1U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_UART8_RX 0x020E0168U, 0x1U, 0x020E065CU, 0x2U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_ECSPI1_SCLK 0x020E0168U, 0x2U, 0x020E0534U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_CSI_DATA12 0x020E0168U, 0x3U, 0x020E04F4U, 0x1U, 0x020E03F4U +#define IOMUXC_LCD_DATA21_LCDIF_DATA21 0x020E016CU, 0x0U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_UART8_RX 0x020E016CU, 0x1U, 0x020E065CU, 0x3U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_UART8_TX 0x020E016CU, 0x1U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_ECSPI1_SS0 0x020E016CU, 0x2U, 0x020E0540U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_CSI_DATA13 0x020E016CU, 0x3U, 0x020E04F8U, 0x1U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_EIM_DATA13 0x020E016CU, 0x4U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_GPIO3_IO26 0x020E016CU, 0x5U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_SRC_BT_CFG29 0x020E016CU, 0x6U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_USDHC2_DATA1 0x020E016CU, 0x8U, 0x020E0680U, 0x1U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_EPDC_SDCE01 0x020E016CU, 0x9U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA22_LCDIF_DATA22 0x020E0170U, 0x0U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_MQS_RIGHT 0x020E0170U, 0x1U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_ECSPI1_MOSI 0x020E0170U, 0x2U, 0x020E053CU, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_CSI_DATA14 0x020E0170U, 0x3U, 0x020E04FCU, 0x1U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_EIM_DATA14 0x020E0170U, 0x4U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_GPIO3_IO27 0x020E0170U, 0x5U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_SRC_BT_CFG30 0x020E0170U, 0x6U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_USDHC2_DATA2 0x020E0170U, 0x8U, 0x020E0684U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_EPDC_SDCE02 0x020E0170U, 0x9U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA23_EPDC_SDCE03 0x020E0174U, 0x9U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_LCDIF_DATA23 0x020E0174U, 0x0U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_MQS_LEFT 0x020E0174U, 0x1U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_ECSPI1_MISO 0x020E0174U, 0x2U, 0x020E0538U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_CSI_DATA15 0x020E0174U, 0x3U, 0x020E0500U, 0x1U, 0x020E0400U +#define IOMUXC_LCD_DATA23_EIM_DATA15 0x020E0174U, 0x4U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_GPIO3_IO28 0x020E0174U, 0x5U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_SRC_BT_CFG31 0x020E0174U, 0x6U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_USDHC2_DATA3 0x020E0174U, 0x8U, 0x020E0688U, 0x1U, 0x020E0400U +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x020E0178U, 0x0U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_RE_B_USDHC2_CLK 0x020E0178U, 0x1U, 0x020E0670U, 0x2U, 0x020E0404U +#define IOMUXC_NAND_RE_B_QSPI_B_SCLK 0x020E0178U, 0x2U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_RE_B_KPP_ROW00 0x020E0178U, 0x3U, 0x020E05D0U, 0x1U, 0x020E0404U +#define IOMUXC_NAND_RE_B_EIM_EB_B00 0x020E0178U, 0x4U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_RE_B_GPIO4_IO00 0x020E0178U, 0x5U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_RE_B_ECSPI3_SS2 0x020E0178U, 0x8U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x020E017CU, 0x0U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_WE_B_USDHC2_CMD 0x020E017CU, 0x1U, 0x020E0678U, 0x2U, 0x020E0408U +#define IOMUXC_NAND_WE_B_QSPI_B_SS0_B 0x020E017CU, 0x2U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_WE_B_KPP_COL00 0x020E017CU, 0x3U, 0x020E05C4U, 0x1U, 0x020E0408U +#define IOMUXC_NAND_WE_B_EIM_EB_B01 0x020E017CU, 0x4U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_WE_B_GPIO4_IO01 0x020E017CU, 0x5U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_WE_B_ECSPI3_SS3 0x020E017CU, 0x8U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x020E0180U, 0x0U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA00_USDHC2_DATA0 0x020E0180U, 0x1U, 0x020E067CU, 0x2U, 0x020E040CU +#define IOMUXC_NAND_DATA00_QSPI_B_SS1_B 0x020E0180U, 0x2U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA00_KPP_ROW01 0x020E0180U, 0x3U, 0x020E05D4U, 0x1U, 0x020E040CU +#define IOMUXC_NAND_DATA00_EIM_AD08 0x020E0180U, 0x4U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA00_GPIO4_IO02 0x020E0180U, 0x5U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA00_ECSPI4_RDY 0x020E0180U, 0x8U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x020E0184U, 0x0U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA01_USDHC2_DATA1 0x020E0184U, 0x1U, 0x020E0680U, 0x2U, 0x020E0410U +#define IOMUXC_NAND_DATA01_QSPI_B_DQS 0x020E0184U, 0x2U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA01_KPP_COL01 0x020E0184U, 0x3U, 0x020E05C8U, 0x1U, 0x020E0410U +#define IOMUXC_NAND_DATA01_EIM_AD09 0x020E0184U, 0x4U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA01_GPIO4_IO03 0x020E0184U, 0x5U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA01_ECSPI4_SS1 0x020E0184U, 0x8U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x020E0188U, 0x0U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA02_USDHC2_DATA2 0x020E0188U, 0x1U, 0x020E0684U, 0x1U, 0x020E0414U +#define IOMUXC_NAND_DATA02_QSPI_B_DATA00 0x020E0188U, 0x2U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA02_KPP_ROW02 0x020E0188U, 0x3U, 0x020E05D8U, 0x1U, 0x020E0414U +#define IOMUXC_NAND_DATA02_EIM_AD10 0x020E0188U, 0x4U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA02_GPIO4_IO04 0x020E0188U, 0x5U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA02_ECSPI4_SS2 0x020E0188U, 0x8U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x020E018CU, 0x0U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA03_USDHC2_DATA3 0x020E018CU, 0x1U, 0x020E0688U, 0x2U, 0x020E0418U +#define IOMUXC_NAND_DATA03_QSPI_B_DATA01 0x020E018CU, 0x2U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA03_KPP_COL02 0x020E018CU, 0x3U, 0x020E05CCU, 0x1U, 0x020E0418U +#define IOMUXC_NAND_DATA03_EIM_AD11 0x020E018CU, 0x4U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA03_GPIO4_IO05 0x020E018CU, 0x5U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA03_ECSPI4_SS3 0x020E018CU, 0x8U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x020E0190U, 0x0U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_USDHC2_DATA4 0x020E0190U, 0x1U, 0x020E068CU, 0x1U, 0x020E041CU +#define IOMUXC_NAND_DATA04_QSPI_B_DATA02 0x020E0190U, 0x2U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_ECSPI4_SCLK 0x020E0190U, 0x3U, 0x020E0564U, 0x1U, 0x020E041CU +#define IOMUXC_NAND_DATA04_EIM_AD12 0x020E0190U, 0x4U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_GPIO4_IO06 0x020E0190U, 0x5U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_UART2_TX 0x020E0190U, 0x8U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_UART2_RX 0x020E0190U, 0x8U, 0x020E062CU, 0x2U, 0x020E041CU +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x020E0194U, 0x0U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA05_USDHC2_DATA5 0x020E0194U, 0x1U, 0x020E0690U, 0x1U, 0x020E0420U +#define IOMUXC_NAND_DATA05_QSPI_B_DATA03 0x020E0194U, 0x2U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA05_ECSPI4_MOSI 0x020E0194U, 0x3U, 0x020E056CU, 0x1U, 0x020E0420U +#define IOMUXC_NAND_DATA05_EIM_AD13 0x020E0194U, 0x4U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA05_GPIO4_IO07 0x020E0194U, 0x5U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA05_UART2_RX 0x020E0194U, 0x8U, 0x020E062CU, 0x3U, 0x020E0420U +#define IOMUXC_NAND_DATA05_UART2_TX 0x020E0194U, 0x8U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x020E0198U, 0x0U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_USDHC2_DATA6 0x020E0198U, 0x1U, 0x020E0694U, 0x1U, 0x020E0424U +#define IOMUXC_NAND_DATA06_SAI2_RX_BCLK 0x020E0198U, 0x2U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_ECSPI4_MISO 0x020E0198U, 0x3U, 0x020E0568U, 0x1U, 0x020E0424U +#define IOMUXC_NAND_DATA06_EIM_AD14 0x020E0198U, 0x4U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_GPIO4_IO08 0x020E0198U, 0x5U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_UART2_CTS_B 0x020E0198U, 0x8U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_UART2_RTS_B 0x020E0198U, 0x8U, 0x020E0628U, 0x4U, 0x020E0424U +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x020E019CU, 0x0U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_DATA07_USDHC2_DATA7 0x020E019CU, 0x1U, 0x020E0698U, 0x1U, 0x020E0428U +#define IOMUXC_NAND_DATA07_QSPI_A_SS1_B 0x020E019CU, 0x2U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_DATA07_ECSPI4_SS0 0x020E019CU, 0x3U, 0x020E0570U, 0x1U, 0x020E0428U +#define IOMUXC_NAND_DATA07_EIM_AD15 0x020E019CU, 0x4U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_DATA07_GPIO4_IO09 0x020E019CU, 0x5U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_DATA07_UART2_RTS_B 0x020E019CU, 0x8U, 0x020E0628U, 0x5U, 0x020E0428U +#define IOMUXC_NAND_DATA07_UART2_CTS_B 0x020E019CU, 0x8U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x020E01A0U, 0x0U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_USDHC2_RESET_B 0x020E01A0U, 0x1U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_QSPI_A_DQS 0x020E01A0U, 0x2U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_PWM3_OUT 0x020E01A0U, 0x3U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_EIM_ADDR17 0x020E01A0U, 0x4U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_GPIO4_IO10 0x020E01A0U, 0x5U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_ECSPI3_SS1 0x020E01A0U, 0x8U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x020E01A4U, 0x0U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_USDHC1_RESET_B 0x020E01A4U, 0x1U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_QSPI_A_SCLK 0x020E01A4U, 0x2U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_PWM4_OUT 0x020E01A4U, 0x3U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_EIM_BCLK 0x020E01A4U, 0x4U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_GPIO4_IO11 0x020E01A4U, 0x5U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_ECSPI3_RDY 0x020E01A4U, 0x8U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x020E01A8U, 0x0U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_USDHC1_DATA4 0x020E01A8U, 0x1U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_QSPI_A_DATA00 0x020E01A8U, 0x2U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_ECSPI3_SS0 0x020E01A8U, 0x3U, 0x020E0560U, 0x1U, 0x020E0434U +#define IOMUXC_NAND_READY_B_EIM_CS1_B 0x020E01A8U, 0x4U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_GPIO4_IO12 0x020E01A8U, 0x5U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_UART3_TX 0x020E01A8U, 0x8U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_UART3_RX 0x020E01A8U, 0x8U, 0x020E0634U, 0x2U, 0x020E0434U +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x020E01ACU, 0x0U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_USDHC1_DATA5 0x020E01ACU, 0x1U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_QSPI_A_DATA01 0x020E01ACU, 0x2U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_ECSPI3_SCLK 0x020E01ACU, 0x3U, 0x020E0554U, 0x1U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_EIM_DTACK_B 0x020E01ACU, 0x4U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_GPIO4_IO13 0x020E01ACU, 0x5U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_UART3_RX 0x020E01ACU, 0x8U, 0x020E0634U, 0x3U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_UART3_TX 0x020E01ACU, 0x8U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x020E01B0U, 0x0U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_USDHC1_DATA6 0x020E01B0U, 0x1U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_QSPI_A_DATA02 0x020E01B0U, 0x2U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_ECSPI3_MOSI 0x020E01B0U, 0x3U, 0x020E055CU, 0x1U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_EIM_ADDR18 0x020E01B0U, 0x4U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_GPIO4_IO14 0x020E01B0U, 0x5U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_UART3_CTS_B 0x020E01B0U, 0x8U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_UART3_RTS_B 0x020E01B0U, 0x8U, 0x020E0630U, 0x2U, 0x020E043CU +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x020E01B4U, 0x0U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_USDHC1_DATA7 0x020E01B4U, 0x1U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_QSPI_A_DATA03 0x020E01B4U, 0x2U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_ECSPI3_MISO 0x020E01B4U, 0x3U, 0x020E0558U, 0x1U, 0x020E0440U +#define IOMUXC_NAND_CLE_EIM_ADDR16 0x020E01B4U, 0x4U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_GPIO4_IO15 0x020E01B4U, 0x5U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_UART3_RTS_B 0x020E01B4U, 0x8U, 0x020E0630U, 0x3U, 0x020E0440U +#define IOMUXC_NAND_CLE_UART3_CTS_B 0x020E01B4U, 0x8U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x020E01B8U, 0x0U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_CSI_FIELD 0x020E01B8U, 0x1U, 0x020E0530U, 0x1U, 0x020E0444U +#define IOMUXC_NAND_DQS_QSPI_A_SS0_B 0x020E01B8U, 0x2U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_PWM5_OUT 0x020E01B8U, 0x3U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_EIM_WAIT 0x020E01B8U, 0x4U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_GPIO4_IO16 0x020E01B8U, 0x5U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_SDMA_EXT_EVENT01 0x020E01B8U, 0x6U, 0x020E0614U, 0x1U, 0x020E0444U +#define IOMUXC_NAND_DQS_SPDIF_EXT_CLK 0x020E01B8U, 0x8U, 0x020E061CU, 0x1U, 0x020E0444U +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x020E01BCU, 0x0U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_GPT2_COMPARE1 0x020E01BCU, 0x1U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_SAI2_RX_SYNC 0x020E01BCU, 0x2U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_SPDIF_OUT 0x020E01BCU, 0x3U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_EIM_ADDR19 0x020E01BCU, 0x4U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_GPIO2_IO16 0x020E01BCU, 0x5U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_SDMA_EXT_EVENT00 0x020E01BCU, 0x6U, 0x020E0610U, 0x2U, 0x020E0448U +#define IOMUXC_SD1_CMD_USB_OTG1_PWR 0x020E01BCU, 0x8U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x020E01C0U, 0x0U, 0x00000000U, 0x0U, 0x020E044CU +#define IOMUXC_SD1_CLK_GPT2_COMPARE2 0x020E01C0U, 0x1U, 0x00000000U, 0x0U, 0x020E044CU +#define IOMUXC_SD1_CLK_SAI2_MCLK 0x020E01C0U, 0x2U, 0x020E05F0U, 0x1U, 0x020E044CU +#define IOMUXC_SD1_CLK_SPDIF_IN 0x020E01C0U, 0x3U, 0x020E0618U, 0x3U, 0x020E044CU +#define IOMUXC_SD1_CLK_EIM_ADDR20 0x020E01C0U, 0x4U, 0x00000000U, 0x0U, 0x020E044CU +#define IOMUXC_SD1_CLK_GPIO2_IO17 0x020E01C0U, 0x5U, 0x00000000U, 0x0U, 0x020E044CU +#define IOMUXC_SD1_CLK_USB_OTG1_OC 0x020E01C0U, 0x8U, 0x020E0664U, 0x2U, 0x020E044CU +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x020E01C4U, 0x0U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_GPT2_COMPARE3 0x020E01C4U, 0x1U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_SAI2_TX_SYNC 0x020E01C4U, 0x2U, 0x020E05FCU, 0x1U, 0x020E0450U +#define IOMUXC_SD1_DATA0_FLEXCAN1_TX 0x020E01C4U, 0x3U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_EIM_ADDR21 0x020E01C4U, 0x4U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_GPIO2_IO18 0x020E01C4U, 0x5U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_ANATOP_OTG1_ID 0x020E01C4U, 0x8U, 0x020E04B8U, 0x2U, 0x020E0450U +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x020E01C8U, 0x0U, 0x00000000U, 0x0U, 0x020E0454U +#define IOMUXC_SD1_DATA1_GPT2_CLK 0x020E01C8U, 0x1U, 0x020E05A0U, 0x1U, 0x020E0454U +#define IOMUXC_SD1_DATA1_SAI2_TX_BCLK 0x020E01C8U, 0x2U, 0x020E05F8U, 0x1U, 0x020E0454U +#define IOMUXC_SD1_DATA1_FLEXCAN1_RX 0x020E01C8U, 0x3U, 0x020E0584U, 0x3U, 0x020E0454U +#define IOMUXC_SD1_DATA1_EIM_ADDR22 0x020E01C8U, 0x4U, 0x00000000U, 0x0U, 0x020E0454U +#define IOMUXC_SD1_DATA1_GPIO2_IO19 0x020E01C8U, 0x5U, 0x00000000U, 0x0U, 0x020E0454U +#define IOMUXC_SD1_DATA1_USB_OTG2_PWR 0x020E01C8U, 0x8U, 0x00000000U, 0x0U, 0x020E0454U +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x020E01CCU, 0x0U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_GPT2_CAPTURE1 0x020E01CCU, 0x1U, 0x020E0598U, 0x1U, 0x020E0458U +#define IOMUXC_SD1_DATA2_SAI2_RX_DATA 0x020E01CCU, 0x2U, 0x020E05F4U, 0x1U, 0x020E0458U +#define IOMUXC_SD1_DATA2_FLEXCAN2_TX 0x020E01CCU, 0x3U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_EIM_ADDR23 0x020E01CCU, 0x4U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_GPIO2_IO20 0x020E01CCU, 0x5U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_CCM_CLKO1 0x020E01CCU, 0x6U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_USB_OTG2_OC 0x020E01CCU, 0x8U, 0x020E0660U, 0x2U, 0x020E0458U +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x020E01D0U, 0x0U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_GPT2_CAPTURE2 0x020E01D0U, 0x1U, 0x020E059CU, 0x1U, 0x020E045CU +#define IOMUXC_SD1_DATA3_SAI2_TX_DATA 0x020E01D0U, 0x2U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_FLEXCAN2_RX 0x020E01D0U, 0x3U, 0x020E0588U, 0x3U, 0x020E045CU +#define IOMUXC_SD1_DATA3_EIM_ADDR24 0x020E01D0U, 0x4U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_GPIO2_IO21 0x020E01D0U, 0x5U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_CCM_CLKO2 0x020E01D0U, 0x6U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_ANATOP_OTG2_ID 0x020E01D0U, 0x8U, 0x020E04BCU, 0x2U, 0x020E045CU +#define IOMUXC_CSI_MCLK_CSI_MCLK 0x020E01D4U, 0x0U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_USDHC2_CD_B 0x020E01D4U, 0x1U, 0x020E0674U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_RAWNAND_CE2_B 0x020E01D4U, 0x2U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_I2C1_SDA 0x020E01D4U, 0x3U, 0x020E05A8U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_EIM_CS0_B 0x020E01D4U, 0x4U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_GPIO4_IO17 0x020E01D4U, 0x5U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_SNVS_HP_VIO_5_CTL 0x020E01D4U, 0x6U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_UART6_TX 0x020E01D4U, 0x8U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_UART6_RX 0x020E01D4U, 0x8U, 0x020E064CU, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_ESAI_TX3_RX2 0x020E01D4U, 0x9U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_PIXCLK_CSI_PIXCLK 0x020E01D8U, 0x0U, 0x020E0528U, 0x1U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_USDHC2_WP 0x020E01D8U, 0x1U, 0x020E069CU, 0x2U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_RAWNAND_CE3_B 0x020E01D8U, 0x2U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_I2C1_SCL 0x020E01D8U, 0x3U, 0x020E05A4U, 0x2U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_EIM_OE 0x020E01D8U, 0x4U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_GPIO4_IO18 0x020E01D8U, 0x5U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_SNVS_HP_VIO_5 0x020E01D8U, 0x6U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_UART6_RX 0x020E01D8U, 0x8U, 0x020E064CU, 0x3U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_UART6_TX 0x020E01D8U, 0x8U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_ESAI_TX2_RX3 0x020E01D8U, 0x9U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_VSYNC_CSI_VSYNC 0x020E01DCU, 0x0U, 0x020E052CU, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_USDHC2_CLK 0x020E01DCU, 0x1U, 0x020E0670U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_I2C2_SDA 0x020E01DCU, 0x3U, 0x020E05B0U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_EIM_RW 0x020E01DCU, 0x4U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_GPIO4_IO19 0x020E01DCU, 0x5U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_PWM7_OUT 0x020E01DCU, 0x6U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_UART6_RTS_B 0x020E01DCU, 0x8U, 0x020E0648U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_UART6_CTS_B 0x020E01DCU, 0x8U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_ESAI_TX4_RX1 0x020E01DCU, 0x9U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_HSYNC_CSI_HSYNC 0x020E01E0U, 0x0U, 0x020E0524U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_USDHC2_CMD 0x020E01E0U, 0x1U, 0x020E0678U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_I2C2_SCL 0x020E01E0U, 0x3U, 0x020E05ACU, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_EIM_LBA_B 0x020E01E0U, 0x4U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_GPIO4_IO20 0x020E01E0U, 0x5U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_PWM8_OUT 0x020E01E0U, 0x6U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_UART6_CTS_B 0x020E01E0U, 0x8U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_UART6_RTS_B 0x020E01E0U, 0x8U, 0x020E0648U, 0x1U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_ESAI_TX1 0x020E01E0U, 0x9U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_DATA00_CSI_DATA02 0x020E01E4U, 0x0U, 0x020E04C4U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_USDHC2_DATA0 0x020E01E4U, 0x1U, 0x020E067CU, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_ECSPI2_SCLK 0x020E01E4U, 0x3U, 0x020E0544U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_EIM_AD00 0x020E01E4U, 0x4U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_GPIO4_IO21 0x020E01E4U, 0x5U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_SRC_INT_BOOT 0x020E01E4U, 0x6U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_UART5_TX 0x020E01E4U, 0x8U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_UART5_RX 0x020E01E4U, 0x8U, 0x020E0644U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_ESAI_TX_HF_CLK 0x020E01E4U, 0x9U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA01_CSI_DATA03 0x020E01E8U, 0x0U, 0x020E04C8U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_USDHC2_DATA1 0x020E01E8U, 0x1U, 0x020E0680U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_ECSPI2_SS0 0x020E01E8U, 0x3U, 0x020E0550U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_EIM_AD01 0x020E01E8U, 0x4U, 0x00000000U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_GPIO4_IO22 0x020E01E8U, 0x5U, 0x00000000U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_SAI1_MCLK 0x020E01E8U, 0x6U, 0x020E05E0U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_UART5_RX 0x020E01E8U, 0x8U, 0x020E0644U, 0x1U, 0x020E0474U +#define IOMUXC_CSI_DATA01_UART5_TX 0x020E01E8U, 0x8U, 0x00000000U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_ESAI_RX_HF_CLK 0x020E01E8U, 0x9U, 0x00000000U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA02_CSI_DATA04 0x020E01ECU, 0x0U, 0x020E04D8U, 0x1U, 0x020E0478U +#define IOMUXC_CSI_DATA02_USDHC2_DATA2 0x020E01ECU, 0x1U, 0x020E0684U, 0x2U, 0x020E0478U +#define IOMUXC_CSI_DATA02_ECSPI2_MOSI 0x020E01ECU, 0x3U, 0x020E054CU, 0x1U, 0x020E0478U +#define IOMUXC_CSI_DATA02_EIM_AD02 0x020E01ECU, 0x4U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA02_GPIO4_IO23 0x020E01ECU, 0x5U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA02_SAI1_RX_SYNC 0x020E01ECU, 0x6U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA02_UART5_RTS_B 0x020E01ECU, 0x8U, 0x020E0640U, 0x7U, 0x020E0478U +#define IOMUXC_CSI_DATA02_UART5_CTS_B 0x020E01ECU, 0x8U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA02_ESAI_RX_FS 0x020E01ECU, 0x9U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA03_CSI_DATA05 0x020E01F0U, 0x0U, 0x020E04CCU, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_USDHC2_DATA3 0x020E01F0U, 0x1U, 0x020E0688U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_ECSPI2_MISO 0x020E01F0U, 0x3U, 0x020E0548U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_EIM_AD03 0x020E01F0U, 0x4U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_GPIO4_IO24 0x020E01F0U, 0x5U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_SAI1_RX_BCLK 0x020E01F0U, 0x6U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_UART5_CTS_B 0x020E01F0U, 0x8U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_UART5_RTS_B 0x020E01F0U, 0x8U, 0x020E0640U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_ESAI_RX_CLK 0x020E01F0U, 0x9U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA04_CSI_DATA06 0x020E01F4U, 0x0U, 0x020E04DCU, 0x1U, 0x020E0480U +#define IOMUXC_CSI_DATA04_USDHC2_DATA4 0x020E01F4U, 0x1U, 0x020E068CU, 0x2U, 0x020E0480U +#define IOMUXC_CSI_DATA04_ECSPI1_SCLK 0x020E01F4U, 0x3U, 0x020E0534U, 0x1U, 0x020E0480U +#define IOMUXC_CSI_DATA04_EIM_AD04 0x020E01F4U, 0x4U, 0x00000000U, 0x0U, 0x020E0480U +#define IOMUXC_CSI_DATA04_GPIO4_IO25 0x020E01F4U, 0x5U, 0x00000000U, 0x0U, 0x020E0480U +#define IOMUXC_CSI_DATA04_SAI1_TX_SYNC 0x020E01F4U, 0x6U, 0x020E05ECU, 0x1U, 0x020E0480U +#define IOMUXC_CSI_DATA04_USDHC1_WP 0x020E01F4U, 0x8U, 0x020E066CU, 0x2U, 0x020E0480U +#define IOMUXC_CSI_DATA04_ESAI_TX_FS 0x020E01F4U, 0x9U, 0x00000000U, 0x0U, 0x020E0480U +#define IOMUXC_CSI_DATA05_CSI_DATA07 0x020E01F8U, 0x0U, 0x020E04E0U, 0x1U, 0x020E0484U +#define IOMUXC_CSI_DATA05_USDHC2_DATA5 0x020E01F8U, 0x1U, 0x020E0690U, 0x2U, 0x020E0484U +#define IOMUXC_CSI_DATA05_ECSPI1_SS0 0x020E01F8U, 0x3U, 0x020E0540U, 0x1U, 0x020E0484U +#define IOMUXC_CSI_DATA05_EIM_AD05 0x020E01F8U, 0x4U, 0x00000000U, 0x0U, 0x020E0484U +#define IOMUXC_CSI_DATA05_GPIO4_IO26 0x020E01F8U, 0x5U, 0x00000000U, 0x0U, 0x020E0484U +#define IOMUXC_CSI_DATA05_SAI1_TX_BCLK 0x020E01F8U, 0x6U, 0x020E05E8U, 0x1U, 0x020E0484U +#define IOMUXC_CSI_DATA05_USDHC1_CD_B 0x020E01F8U, 0x8U, 0x020E0668U, 0x2U, 0x020E0484U +#define IOMUXC_CSI_DATA05_ESAI_TX_CLK 0x020E01F8U, 0x9U, 0x00000000U, 0x0U, 0x020E0484U +#define IOMUXC_CSI_DATA06_CSI_DATA08 0x020E01FCU, 0x0U, 0x020E04E4U, 0x1U, 0x020E0488U +#define IOMUXC_CSI_DATA06_USDHC2_DATA6 0x020E01FCU, 0x1U, 0x020E0694U, 0x2U, 0x020E0488U +#define IOMUXC_CSI_DATA06_ECSPI1_MOSI 0x020E01FCU, 0x3U, 0x020E053CU, 0x1U, 0x020E0488U +#define IOMUXC_CSI_DATA06_EIM_AD06 0x020E01FCU, 0x4U, 0x00000000U, 0x0U, 0x020E0488U +#define IOMUXC_CSI_DATA06_GPIO4_IO27 0x020E01FCU, 0x5U, 0x00000000U, 0x0U, 0x020E0488U +#define IOMUXC_CSI_DATA06_SAI1_RX_DATA 0x020E01FCU, 0x6U, 0x020E05E4U, 0x1U, 0x020E0488U +#define IOMUXC_CSI_DATA06_USDHC1_RESET_B 0x020E01FCU, 0x8U, 0x00000000U, 0x0U, 0x020E0488U +#define IOMUXC_CSI_DATA06_ESAI_TX5_RX0 0x020E01FCU, 0x9U, 0x00000000U, 0x0U, 0x020E0488U +#define IOMUXC_CSI_DATA07_CSI_DATA09 0x020E0200U, 0x0U, 0x020E04E8U, 0x1U, 0x020E048CU +#define IOMUXC_CSI_DATA07_USDHC2_DATA7 0x020E0200U, 0x1U, 0x020E0698U, 0x2U, 0x020E048CU +#define IOMUXC_CSI_DATA07_ECSPI1_MISO 0x020E0200U, 0x3U, 0x020E0538U, 0x1U, 0x020E048CU +#define IOMUXC_CSI_DATA07_EIM_AD07 0x020E0200U, 0x4U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_CSI_DATA07_GPIO4_IO28 0x020E0200U, 0x5U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_CSI_DATA07_SAI1_TX_DATA 0x020E0200U, 0x6U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_CSI_DATA07_USDHC1_VSELECT 0x020E0200U, 0x8U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_CSI_DATA07_ESAI_TX0 0x020E0200U, 0x9U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_DRAM_ADDR00 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0204U +#define IOMUXC_DRAM_ADDR01 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0208U +#define IOMUXC_DRAM_ADDR02 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E020CU +#define IOMUXC_DRAM_ADDR03 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0210U +#define IOMUXC_DRAM_ADDR04 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0214U +#define IOMUXC_DRAM_ADDR05 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0218U +#define IOMUXC_DRAM_ADDR06 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E021CU +#define IOMUXC_DRAM_ADDR07 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0220U +#define IOMUXC_DRAM_ADDR08 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0224U +#define IOMUXC_DRAM_ADDR09 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0228U +#define IOMUXC_DRAM_ADDR10 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E022CU +#define IOMUXC_DRAM_ADDR11 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0230U +#define IOMUXC_DRAM_ADDR12 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0234U +#define IOMUXC_DRAM_ADDR13 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0238U +#define IOMUXC_DRAM_ADDR14 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E023CU +#define IOMUXC_DRAM_ADDR15 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0240U +#define IOMUXC_DRAM_DQM0 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0244U +#define IOMUXC_DRAM_DQM1 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0248U +#define IOMUXC_DRAM_RAS_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E024CU +#define IOMUXC_DRAM_CAS_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0250U +#define IOMUXC_DRAM_CS0_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0254U +#define IOMUXC_DRAM_CS1_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0258U +#define IOMUXC_DRAM_SDWE_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E025CU +#define IOMUXC_DRAM_ODT0 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0260U +#define IOMUXC_DRAM_ODT1 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0264U +#define IOMUXC_DRAM_SDBA0 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0268U +#define IOMUXC_DRAM_SDBA1 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E026CU +#define IOMUXC_DRAM_SDBA2 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0270U +#define IOMUXC_DRAM_SDCKE0 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0274U +#define IOMUXC_DRAM_SDCKE1 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0278U +#define IOMUXC_DRAM_SDCLK0_P 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E027CU +#define IOMUXC_DRAM_SDQS0_P 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0280U +#define IOMUXC_DRAM_SDQS1_P 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0284U +#define IOMUXC_DRAM_RESET 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0288U +#define IOMUXC_GRP_ADDDS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0490U +#define IOMUXC_GRP_DDRMODE_CTL 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0494U +#define IOMUXC_GRP_B0DS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0498U +#define IOMUXC_GRP_DDRPK 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E049CU +#define IOMUXC_GRP_CTLDS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04A0U +#define IOMUXC_GRP_B1DS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04A4U +#define IOMUXC_GRP_DDRHYS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04A8U +#define IOMUXC_GRP_DDRPKE 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04ACU +#define IOMUXC_GRP_DDRMODE 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04B0U +#define IOMUXC_GRP_DDR_TYPE 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04B4U + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the ENET1_RX_DATA0 Pad as FLEXCAN1_TX: + * @code + * IOMUXC_SetPinMux(IOMUXC_ENET1_RX_DATA0_FLEXCAN1_TX, 0); + * @endcode + * + * This is an example to set the GPIO1_IO02 Pad as I2C1_SCL: + * @code + * IOMUXC_SetPinMux(IOMUXC_GPIO1_IO02_I2C1_SCL, 0); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param inputOnfield Software input on field. + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} + +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_GPIO1_IO02_I2C1_SCL: + * @code + * IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO02_I2C1_SCL, IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(2U)); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param configValue The pin config value. + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_phy.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_phy.c new file mode 100644 index 0000000000..278676af35 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_phy.c @@ -0,0 +1,366 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_phy.h" +#include "fsl_gpio.h" +#include "ioremap.h" +#include +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines the timeout macro. */ +#define PHY_TIMEOUT_COUNT 0x4FFFFFFU +#define PHY_NEGOTIATION_DELAY 100 +#define PHY_ID 0X7 + +#ifdef BSP_USING_IMX6ULL_ART_PI +#define PHY_SW_GPIO GPIO5 +#define PHY_SW_GPIO_PIN 9U +#endif + +#ifdef BSP_USING_IMX6ULL_POR +#define PHY_SW_GPIO GPIO5 +#define PHY_SW_GPIO_PIN 6U +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +extern uint32_t ENET_GetInstance(ENET_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to enet clocks for each instance. */ +extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT]; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +status_t phy_reset() +{ + GPIO_Type *gpio_base = NULL; + gpio_pin_config_t sw_config = + { + kGPIO_DigitalOutput, + 0, + kGPIO_NoIntmode, + }; + + gpio_base = (GPIO_Type *)rt_ioremap((void *)PHY_SW_GPIO,0x1000); + GPIO_PinInit(gpio_base, PHY_SW_GPIO_PIN, &sw_config); + GPIO_WritePinOutput(gpio_base,PHY_SW_GPIO_PIN,0); + rt_thread_delay(50); + GPIO_WritePinOutput(gpio_base,PHY_SW_GPIO_PIN,1); + + return kStatus_Success; + +} + +status_t PHY_StartNegotiation(ENET_Type *base, uint32_t phyAddr) +{ + uint32_t counter = PHY_TIMEOUT_COUNT; + status_t result = kStatus_Success; + uint32_t bssReg; + uint32_t timeDelay; + + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); + if (result == kStatus_Success) + { + +#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE) + uint32_t data = 0; + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if ( result != kStatus_Success) + { + return result; + } + result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK)); + if (result != kStatus_Success) + { + return result; + } +#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */ + /* Set the negotiation. */ + result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, + (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | + PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); + if (result == kStatus_Success) + { + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, + (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); + if (result == kStatus_Success) + { + /* Check auto negotiation complete. */ + while (counter --) + { + result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); + if ( result == kStatus_Success) + { + if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) + { + /* Wait a moment for Phy status stable. */ + for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++) + { + __ASM("nop"); + } + break; + } + } + rt_thread_delay(PHY_NEGOTIATION_DELAY); + if (!counter) + { + return kStatus_PHY_AutoNegotiateFail; + } + } + } + } + } + return kStatus_Success; +} + +status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) +{ + uint32_t counter = PHY_TIMEOUT_COUNT; + uint32_t idReg = 0; + status_t result = kStatus_Success; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Set SMI first. */ + uint32_t instance = ENET_GetInstance(IMX6UL_ENET); + CLOCK_EnableClock(s_enetClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + ENET_SetSMI(base, srcClock_Hz, false); + PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); + while ((idReg != PHY_ID) && (counter != 0)) + { + PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); + counter --; + } + if (!counter) + { + return kStatus_Fail; + } + /* Reset PHY. */ + counter = PHY_TIMEOUT_COUNT; + return result; +} + +status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) +{ + uint32_t counter; + + /* Clear the SMI interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI write command. */ + ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data); + + /* Wait for SMI complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + return kStatus_PHY_SMIVisitTimeout; + } + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} + +status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr) +{ + RT_ASSERT(dataPtr); + + uint32_t counter; + + /* Clear the MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI read command operation. */ + ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame); + + /* Wait for MII complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + return kStatus_PHY_SMIVisitTimeout; + } + + /* Get data from MII register. */ + *dataPtr = ENET_ReadSMIData(base); + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} + +status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable) +{ + status_t result; + uint32_t data = 0; + + /* Set the loop mode. */ + if (enable) + { + if (mode == kPHY_LocalLoop) + { + /* First read the current status in control register. */ + result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_LOOP_MASK)); + } + } + else + { + /* First read the current status in control register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + else + { + /* Disable the loop mode. */ + if (mode == kPHY_LocalLoop) + { + /* First read the current status in the basic control register. */ + result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data & ~PHY_BCTL_LOOP_MASK)); + } + } + else + { + /* First read the current status in control one register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + return result; +} + +status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) +{ + RT_ASSERT(status); + + status_t result = kStatus_Success; + uint32_t data; + + /* Read the basic status register. */ + result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data); + if (result == kStatus_Success) + { + if (!(PHY_BSTATUS_LINKSTATUS_MASK & data)) + { + /* link down. */ + *status = false; + } + else + { + /* link up. */ + *status = true; + } + } + return result; +} + +status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex) +{ + RT_ASSERT(duplex); + + status_t result = kStatus_Success; + uint32_t data, ctlReg; + + /* Read the control two register. */ + + result = PHY_Read(base, phyAddr, 31, &ctlReg); + + data = ((ctlReg>>2) & 0x7); + switch (data) + { + case 1: + *speed = kPHY_Speed10M; + *duplex = kPHY_HalfDuplex; + break; + case 5: + *speed = kPHY_Speed10M; + *duplex = kPHY_FullDuplex; + break; + case 2: + *speed = kPHY_Speed100M; + *duplex = kPHY_HalfDuplex; + break; + case 6: + *speed = kPHY_Speed100M; + *duplex = kPHY_FullDuplex; + break; + default: + *speed = kPHY_Speed100M; + *duplex = kPHY_FullDuplex; + } + + return result; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_phy.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_phy.h new file mode 100644 index 0000000000..8e5adfb508 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_phy.h @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PHY_H_ +#define _FSL_PHY_H_ + +#include "fsl_enet.h" + +/*! + * @addtogroup phy_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief PHY driver version */ +#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + +/*! @brief Defines the PHY registers. */ +#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ +#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ +#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ +#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ +#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ +#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ +#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ + +#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ + +/*! @brief Defines the mask flag in basic control register. */ +#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ +#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ +#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ +#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ +#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ +#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ + +/*!@brief Defines the mask flag of operation mode in control two register*/ +#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ +#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ +#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ +#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ +#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ +#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ +#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ + +/*! @brief Defines the mask flag in basic status register. */ +#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ +#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ +#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ + +/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ +#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ +#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ +#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ + +/*! @brief Defines the PHY status. */ +enum _phy_status +{ + kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */ + kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */ +}; + +/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */ +typedef enum _phy_speed +{ + kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */ + kPHY_Speed100M /*!< ENET PHY 100M speed. */ +} phy_speed_t; + +/*! @brief Defines the PHY link duplex. */ +typedef enum _phy_duplex +{ + kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */ + kPHY_FullDuplex /*!< ENET PHY full duplex. */ +} phy_duplex_t; + +/*! @brief Defines the PHY loopback mode. */ +typedef enum _phy_loop +{ + kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */ + kPHY_RemoteLoop /*!< ENET PHY remote loopback. */ +} phy_loop_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name PHY Driver + * @{ + */ + +/*! + * @brief Initializes PHY. + * + * This function initialize the SMI interface and initialize PHY. + * The SMI is the MII management interface between PHY and MAC, which should be + * firstly initialized before any other operation for PHY. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. + * @retval kStatus_Success PHY initialize success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz); + +/*! + * @brief PHY Negotiation function. + * + * This function initialize the SMI interface and initialize PHY. + * The SMI is the MII management interface between PHY and MAC, which should be + * firstly initialized before any other operation for PHY. + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @retval kStatus_Success PHY negotiate success + * @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail + */ +status_t PHY_StartNegotiation(ENET_Type *base, uint32_t phyAddr); + +/*! + * @brief PHY Write function. This function write data over the SMI to + * the specified PHY register. This function is called by all PHY interfaces. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param data The data written to the PHY register. + * @retval kStatus_Success PHY write success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); + +/*! + * @brief PHY Read function. This interface read data over the SMI from the + * specified PHY register. This function is called by all PHY interfaces. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param dataPtr The address to store the data read from the PHY register. + * @retval kStatus_Success PHY read success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); + +/*! + * @brief Enables/disables PHY loopback. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param mode The loopback mode to be enabled, please see "phy_loop_t". + * the two loopback mode should not be both set. when one loopback mode is set + * the other one should be disabled. + * @param enable True to enable, false to disable. + * @retval kStatus_Success PHY loopback success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable); + +/*! + * @brief Gets the PHY link status. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param status The link up or down status of the PHY. + * - true the link is up. + * - false the link is down. + * @retval kStatus_Success PHY get link status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status); + +/*! + * @brief Gets the PHY link speed and duplex. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param speed The address of PHY link speed. + * @param duplex The link duplex of PHY. + * @retval kStatus_Success PHY get link speed and duplex success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex); + +/*! + * @brief hardware reset phy device. + */ +status_t phy_reset(); +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PHY_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_snvs_hp.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_snvs_hp.c new file mode 100644 index 0000000000..1f98dec45c --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_snvs_hp.c @@ -0,0 +1,532 @@ +/* + * Copyright (c) 2017, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Copyright (c) 2017, NXP Semiconductors, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_snvs_hp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SECONDS_IN_A_DAY (86400U) +#define SECONDS_IN_A_HOUR (3600U) +#define SECONDS_IN_A_MINUTE (60U) +#define DAYS_IN_A_YEAR (365U) +#define YEAR_RANGE_START (1970U) +#define YEAR_RANGE_END (2099U) + +#if !(defined(SNVS_HPCOMR_SW_SV_MASK)) +#define SNVS_HPCOMR_SW_SV_MASK (0x100U) +#endif +#if !(defined(SNVS_HPSR_PI_MASK)) +#define SNVS_HPSR_PI_MASK (0x2U) +#endif +#if !(defined(SNVS_HPSR_HPTA_MASK)) +#define SNVS_HPSR_HPTA_MASK (0x1U) +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Checks whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool SNVS_HP_CheckDatetimeFormat(const snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from datetime to seconds + * + * @param datetime Pointer to datetime structure where the date and time details are stored + * + * @return The result of the conversion in seconds + */ +static uint32_t SNVS_HP_ConvertDatetimeToSeconds(const snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from seconds to a datetime structure + * + * @param seconds Seconds value that needs to be converted to datetime format + * @param datetime Pointer to the datetime structure where the result of the conversion is stored + */ +static void SNVS_HP_ConvertSecondsToDatetime(uint32_t seconds, snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Returns RTC time in seconds. + * + * This function is used internally to get actual RTC time in seconds. + * + * @param base SNVS peripheral base address + * + * @return RTC time in seconds + */ +static uint32_t SNVS_HP_RTC_GetSeconds(SNVS_Type *base); + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) +/*! + * @brief Get the SNVS instance from peripheral base address. + * + * @param base SNVS peripheral base address. + * + * @return SNVS instance. + */ +static uint32_t SNVS_HP_GetInstance(SNVS_Type *base); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) +/*! @brief Pointer to snvs_hp clock. */ +const clock_ip_name_t s_snvsHpClock[] = SNVS_HP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool SNVS_HP_CheckDatetimeFormat(const snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) + { + /* If not correct then error*/ + return false; + } + + /* Adjust the days in February for a leap year */ + if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) + { + return false; + } + + return true; +} + +static uint32_t SNVS_HP_ConvertDatetimeToSeconds(const snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Number of days from begin of the non Leap-year*/ + /* Number of days from begin of the non Leap-year*/ + uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; + uint32_t seconds; + + /* Compute number of days from 1970 till given year*/ + seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; + /* Add leap year days */ + seconds += ((datetime->year / 4) - (1970U / 4)); + /* Add number of days till given month*/ + seconds += monthDays[datetime->month]; + /* Add days in given month. We subtract the current day as it is + * represented in the hours, minutes and seconds field*/ + seconds += (datetime->day - 1); + /* For leap year if month less than or equal to Febraury, decrement day counter*/ + if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) + { + seconds--; + } + + seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + + (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; + + return seconds; +} + +static void SNVS_HP_ConvertSecondsToDatetime(uint32_t seconds, snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t x; + uint32_t secondsRemaining, days; + uint16_t daysInYear; + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Start with the seconds value that is passed in to be converted to date time format */ + secondsRemaining = seconds; + + /* Calcuate the number of days, we add 1 for the current day which is represented in the + * hours and seconds field + */ + days = secondsRemaining / SECONDS_IN_A_DAY + 1; + + /* Update seconds left*/ + secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; + + /* Calculate the datetime hour, minute and second fields */ + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; + datetime->minute = secondsRemaining / 60U; + datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; + + /* Calculate year */ + daysInYear = DAYS_IN_A_YEAR; + datetime->year = YEAR_RANGE_START; + while (days > daysInYear) + { + /* Decrease day count by a year and increment year by 1 */ + days -= daysInYear; + datetime->year++; + + /* Adjust the number of days for a leap year */ + if (datetime->year & 3U) + { + daysInYear = DAYS_IN_A_YEAR; + } + else + { + daysInYear = DAYS_IN_A_YEAR + 1; + } + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + for (x = 1U; x <= 12U; x++) + { + if (days <= daysPerMonth[x]) + { + datetime->month = x; + break; + } + else + { + days -= daysPerMonth[x]; + } + } + + datetime->day = days; +} + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) +static uint32_t SNVS_HP_GetInstance(SNVS_Type *base) +{ + return 0U; +} +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config) +{ + assert(config); + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) + uint32_t instance = SNVS_HP_GetInstance(base); + CLOCK_EnableClock(s_snvsHpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->HPCOMR |= SNVS_HPCOMR_NPSWA_EN_MASK | SNVS_HPCOMR_SW_SV_MASK; + + base->HPCR = SNVS_HPCR_PI_FREQ(config->periodicInterruptFreq); + + if (config->rtcCalEnable) + { + base->HPCR = SNVS_HPCR_HPCALB_VAL_MASK & (config->rtcCalValue << SNVS_HPCR_HPCALB_VAL_SHIFT); + base->HPCR |= SNVS_HPCR_HPCALB_EN_MASK; + } +} + +void SNVS_HP_RTC_Deinit(SNVS_Type *base) +{ + base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK; + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) + uint32_t instance = SNVS_HP_GetInstance(base); + CLOCK_DisableClock(s_snvsHpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config) +{ + assert(config); + + config->rtcCalEnable = false; + config->rtcCalValue = 0U; + config->periodicInterruptFreq = 0U; +} + +static uint32_t SNVS_HP_RTC_GetSeconds(SNVS_Type *base) +{ + uint32_t seconds = 0; + uint32_t tmp = 0; + + /* Do consecutive reads until value is correct */ + do + { + seconds = tmp; + tmp = (base->HPRTCMR << 17U) | (base->HPRTCLR >> 15U); + } while (tmp != seconds); + + return seconds; +} + +status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t seconds = 0U; + uint32_t tmp = base->HPCR; + + /* disable RTC */ + SNVS_HP_RTC_StopTimer(base); + + /* Return error if the time provided is not valid */ + if (!(SNVS_HP_CheckDatetimeFormat(datetime))) + { + return kStatus_InvalidArgument; + } + + /* Set time in seconds */ + seconds = SNVS_HP_ConvertDatetimeToSeconds(datetime); + + base->HPRTCMR = (uint32_t)(seconds >> 17U); + base->HPRTCLR = (uint32_t)(seconds << 15U); + + /* reenable RTC in case that it was enabled before */ + if (tmp & SNVS_HPCR_RTC_EN_MASK) + { + SNVS_HP_RTC_StartTimer(base); + } + + return kStatus_Success; +} + +void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + SNVS_HP_ConvertSecondsToDatetime(SNVS_HP_RTC_GetSeconds(base), datetime); +} + +status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *alarmTime) +{ + assert(alarmTime); + + uint32_t alarmSeconds = 0U; + uint32_t currSeconds = 0U; + uint32_t tmp = base->HPCR; + + /* Return error if the alarm time provided is not valid */ + if (!(SNVS_HP_CheckDatetimeFormat(alarmTime))) + { + return kStatus_InvalidArgument; + } + + alarmSeconds = SNVS_HP_ConvertDatetimeToSeconds(alarmTime); + currSeconds = SNVS_HP_RTC_GetSeconds(base); + + /* Return error if the alarm time has passed */ + if (alarmSeconds < currSeconds) + { + return kStatus_Fail; + } + + /* disable RTC alarm interrupt */ + base->HPCR &= ~SNVS_HPCR_HPTA_EN_MASK; + while (base->HPCR & SNVS_HPCR_HPTA_EN_MASK) + { + } + + /* Set alarm in seconds*/ + base->HPTAMR = (uint32_t)(alarmSeconds >> 17U); + base->HPTALR = (uint32_t)(alarmSeconds << 15U); + + /* reenable RTC alarm interrupt in case that it was enabled before */ + base->HPCR = tmp; + + return kStatus_Success; +} + +void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t alarmSeconds = 0U; + + /* Get alarm in seconds */ + alarmSeconds = (base->HPTAMR << 17U) | (base->HPTALR >> 15U); + + SNVS_HP_ConvertSecondsToDatetime(alarmSeconds, datetime); +} + +#if (defined(FSL_FEATURE_SNVS_HAS_SRTC) && (FSL_FEATURE_SNVS_HAS_SRTC > 0)) +void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base) +{ + uint32_t tmp = base->HPCR; + + /* disable RTC */ + SNVS_HP_RTC_StopTimer(base); + + base->HPCR |= SNVS_HPCR_HP_TS_MASK; + + /* reenable RTC in case that it was enabled before */ + if (tmp & SNVS_HPCR_RTC_EN_MASK) + { + SNVS_HP_RTC_StartTimer(base); + } +} +#endif /* FSL_FEATURE_SNVS_HAS_SRTC */ + +uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base) +{ + uint32_t flags = 0U; + + if (base->HPSR & SNVS_HPSR_PI_MASK) + { + flags |= kSNVS_RTC_PeriodicInterruptFlag; + } + + if (base->HPSR & SNVS_HPSR_HPTA_MASK) + { + flags |= kSNVS_RTC_AlarmInterruptFlag; + } + + return flags; +} + +void SNVS_HP_RTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask) +{ + uint32_t wrMask = 0U; + + if (mask & kSNVS_RTC_PeriodicInterruptFlag) + { + wrMask |= SNVS_HPSR_PI_MASK; + } + + if (mask & kSNVS_RTC_AlarmInterruptFlag) + { + wrMask |= SNVS_HPSR_HPTA_MASK; + } + + base->HPSR |= wrMask; +} + +void SNVS_HP_RTC_EnableInterrupts(SNVS_Type *base, uint32_t mask) +{ + uint32_t wrMask = 0U; + + if (mask & kSNVS_RTC_PeriodicInterruptEnable) + { + wrMask |= SNVS_HPCR_PI_EN_MASK; + } + + if (mask & kSNVS_RTC_AlarmInterruptEnable) + { + wrMask |= SNVS_HPCR_HPTA_EN_MASK; + } + + base->HPCR |= wrMask; +} + +void SNVS_HP_RTC_DisableInterrupts(SNVS_Type *base, uint32_t mask) +{ + uint32_t wrMask = 0U; + + if (mask & kSNVS_RTC_PeriodicInterruptEnable) + { + wrMask |= SNVS_HPCR_PI_EN_MASK; + } + + if (mask & kSNVS_RTC_AlarmInterruptEnable) + { + wrMask |= SNVS_HPCR_HPTA_EN_MASK; + } + + base->HPCR &= ~wrMask; +} + +uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base) +{ + uint32_t val = 0U; + + if (base->HPCR & SNVS_HPCR_PI_EN_MASK) + { + val |= kSNVS_RTC_PeriodicInterruptFlag; + } + + if (base->HPCR & SNVS_HPCR_HPTA_EN_MASK) + { + val |= kSNVS_RTC_AlarmInterruptFlag; + } + + return val; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_snvs_hp.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_snvs_hp.h new file mode 100644 index 0000000000..d06b0233ec --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_snvs_hp.h @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2017, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Copyright (c) 2017, NXP Semiconductors, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SNVS_HP_H_ +#define _FSL_SNVS_HP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup snvs_hp + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief List of SNVS interrupts */ +typedef enum _snvs_hp_interrupt_enable +{ + kSNVS_RTC_PeriodicInterruptEnable = 1U, /*!< RTC periodic interrupt.*/ + kSNVS_RTC_AlarmInterruptEnable = 2U, /*!< RTC time alarm.*/ +} snvs_hp_interrupt_enable_t; + +/*! @brief List of SNVS flags */ +typedef enum _snvs_hp_status_flags +{ + kSNVS_RTC_PeriodicInterruptFlag = 1U, /*!< RTC periodic interrupt flag */ + kSNVS_RTC_AlarmInterruptFlag = 2U, /*!< RTC time alarm flag */ +} snvs_hp_status_flags_t; + +/*! @brief Structure is used to hold the date and time */ +typedef struct _snvs_hp_rtc_datetime +{ + uint16_t year; /*!< Range from 1970 to 2099.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} snvs_hp_rtc_datetime_t; + +/*! + * @brief SNVS config structure + * + * This structure holds the configuration settings for the SNVS peripheral. To initialize this + * structure to reasonable defaults, call the SNVS_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _snvs_hp_rtc_config +{ + bool rtcCalEnable; /*!< true: RTC calibration mechanism is enabled; + false:No calibration is used */ + uint32_t rtcCalValue; /*!< Defines signed calibration value for nonsecure RTC; + This is a 5-bit 2's complement value, range from -16 to +15 */ + uint32_t periodicInterruptFreq; /*!< Defines frequency of the periodic interrupt; + Range from 0 to 15 */ +} snvs_hp_rtc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the SNVS clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the SNVS driver. + * + * @param base SNVS peripheral base address + * @param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config); + +/*! + * @brief Stops the RTC and SRTC timers. + * + * @param base SNVS peripheral base address + */ +void SNVS_HP_RTC_Deinit(SNVS_Type *base); + +/*! + * @brief Fills in the SNVS config struct with the default settings. + * + * The default values are as follows. + * @code + * config->rtccalenable = false; + * config->rtccalvalue = 0U; + * config->PIFreq = 0U; + * @endcode + * @param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config); + +/*! @}*/ + +/*! + * @name Non secure RTC current Time & Alarm + * @{ + */ + +/*! + * @brief Sets the SNVS RTC date and time according to the given time structure. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the date and time details are stored. + * + * @return kStatus_Success: Success in setting the time and starting the SNVS RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Gets the SNVS RTC time and stores it in the given time structure. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the date and time details are stored. + */ +void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Sets the SNVS RTC alarm time. + * + * The function sets the RTC alarm. It also checks whether the specified alarm time + * is greater than the present time. If not, the function does not set the alarm + * and returns an error. + * + * @param base SNVS peripheral base address + * @param alarmTime Pointer to the structure where the alarm time is stored. + * + * @return kStatus_Success: success in setting the SNVS RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ +status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *alarmTime); + +/*! + * @brief Returns the SNVS RTC alarm time. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the alarm date and time details are stored. + */ +void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime); + +#if (defined(FSL_FEATURE_SNVS_HAS_SRTC) && (FSL_FEATURE_SNVS_HAS_SRTC > 0)) +/*! + * @brief The function synchronizes RTC counter value with SRTC. + * + * @param base SNVS peripheral base address + */ +void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base); +#endif /* FSL_FEATURE_SNVS_HAS_SRTC */ + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected SNVS interrupts. + * + * @param base SNVS peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +void SNVS_HP_RTC_EnableInterrupts(SNVS_Type *base, uint32_t mask); + +/*! + * @brief Disables the selected SNVS interrupts. + * + * @param base SNVS peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +void SNVS_HP_RTC_DisableInterrupts(SNVS_Type *base, uint32_t mask); + +/*! + * @brief Gets the enabled SNVS interrupts. + * + * @param base SNVS peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the SNVS status flags. + * + * @param base SNVS peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::snvs_status_flags_t + */ +uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base); + +/*! + * @brief Clears the SNVS status flags. + * + * @param base SNVS peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::snvs_status_flags_t + */ +void SNVS_HP_RTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the SNVS RTC time counter. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_RTC_StartTimer(SNVS_Type *base) +{ + base->HPCR |= SNVS_HPCR_RTC_EN_MASK; + while (!(base->HPCR & SNVS_HPCR_RTC_EN_MASK)) + { + } +} + +/*! + * @brief Stops the SNVS RTC time counter. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_RTC_StopTimer(SNVS_Type *base) +{ + base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK; + while (base->HPCR & SNVS_HPCR_RTC_EN_MASK) + { + } +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SNVS_HP_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_uart.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_uart.c new file mode 100644 index 0000000000..dc41551bb3 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_uart.c @@ -0,0 +1,1275 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* UART transfer state. */ +enum _uart_tansfer_states +{ + kUART_TxIdle, /* TX idle. */ + kUART_TxBusy, /* TX busy. */ + kUART_RxIdle, /* RX idle. */ + kUART_RxBusy, /* RX busy. */ + kUART_RxFramingError, /* Rx framing error */ + kUART_RxParityError /* Rx parity error */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*uart_isr_t)(UART_Type *base, uart_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the UART instance from peripheral base address. + * + * @param base UART peripheral base address. + * @return UART instance. + */ +uint32_t UART_GetInstance(UART_Type *base); + +/*! + * @brief Check whether the RX ring buffer is full. + * + * @param handle UART handle pointer. + * @retval true RX ring buffer is full. + * @retval false RX ring buffer is not full. + */ +static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle); + +/*! + * @brief Read RX register using non-blocking method. + * + * This function reads data from the TX register directly, upper layer must make + * sure the RX register is full or TX FIFO has data before calling this function. + * + * @param base UART peripheral base address. + * @param data Start addresss of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length); + +/*! + * @brief Write to TX register using non-blocking method. + * + * This function writes data to the TX register directly, upper layer must make + * sure the TX register is empty or TX FIFO has empty room before calling this function. + * + * @note This function does not check whether all the data has been sent out to bus, + * so before disable TX, check kUART_TransmissionCompleteFlag to ensure the TX is + * finished. + * + * @param base UART peripheral base address. + * @param data Start addresss of the data to write. + * @param length Size of the buffer to be sent. + */ +static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* ARRAY of UART handle */ +#if (defined(UART8)) +#define UART_HANDLE_ARRAY_SIZE 8 +#else /* UART8 */ +#if (defined(UART7)) +#define UART_HANDLE_ARRAY_SIZE 7 +#else /* UART7 */ +#if (defined(UART6)) +#define UART_HANDLE_ARRAY_SIZE 6 +#else /* UART6 */ +#if (defined(UART5)) +#define UART_HANDLE_ARRAY_SIZE 5 +#else /* UART5 */ +#if (defined(UART4)) +#define UART_HANDLE_ARRAY_SIZE 4 +#else /* UART4 */ +#if (defined(UART3)) +#define UART_HANDLE_ARRAY_SIZE 3 +#else /* UART3 */ +#if (defined(UART2)) +#define UART_HANDLE_ARRAY_SIZE 2 +#else /* UART2 */ +#if (defined(UART1)) +#define UART_HANDLE_ARRAY_SIZE 1 +#else /* UART1 */ +#error No UART instance. +#endif /* UART 1 */ +#endif /* UART 2 */ +#endif /* UART 3 */ +#endif /* UART 4 */ +#endif /* UART 5 */ +#endif /* UART 6 */ +#endif /* UART 7 */ +#endif /* UART 8 */ +static uart_handle_t *s_uartHandle[UART_HANDLE_ARRAY_SIZE]; + +/* Array of UART peripheral base address. */ +static UART_Type *const s_uartBases[] = UART_BASE_PTRS; + +/* Array of UART IRQ number. */ +static const IRQn_Type s_uartIRQ[] = UART_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of UART clock name. */ +static const clock_ip_name_t s_uartClock[] = UART_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* UART ISR for transactional APIs. */ +static uart_isr_t s_uartIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t UART_GetInstance(UART_Type *base) +{ + uint32_t instance; + uint32_t uartArrayCount = (sizeof(s_uartBases) / sizeof(s_uartBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < uartArrayCount; instance++) + { + if (s_uartBases[instance] == base) + { + break; + } + } + assert(instance < uartArrayCount); + + return instance; +} + +size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle) +{ + assert(handle); + + size_t size; + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + + return size; +} + +static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle) +{ + assert(handle); + + bool full; + + if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + + return full; +} + +status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz) +{ + /* Check argument */ + assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable uart clock */ + CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable UART Module. */ + UART_Disable(base); + /* Reset the transmit and receive state machines, all FIFOs and register + * USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD and UTS[6-3]. */ + UART_SoftwareReset(base); + + /* Set UART Module Register content to default value */ + base->UCR1 = 0x0; + base->UCR2 = UART_UCR2_SRST_MASK; + base->UCR3 = UART_UCR3_DSR_MASK | UART_UCR3_DCD_MASK | UART_UCR3_RI_MASK; + base->UCR4 = UART_UCR4_CTSTL(32); + base->UFCR = UART_UFCR_TXTL(2) | UART_UFCR_RXTL(1); + base->UESC = UART_UESC_ESC_CHAR(0x2B); + base->UTIM = 0x0; + base->ONEMS = 0x0; + base->UTS = UART_UTS_TXEMPTY_MASK | UART_UTS_RXEMPTY_MASK; + base->UMCR = 0x0; + + /* Set UART data word length, stop bit count, parity mode and communication + * direction according to uart init struct, disable RTS hardware flow control. + */ + base->UCR2 |= + ((uint32_t)UART_UCR2_WS(config->dataBitsCount) | (uint32_t)UART_UCR2_STPB(config->stopBitCount) | + (uint32_t)(((config->parityMode) << UART_UCR2_PROE_SHIFT) & (UART_UCR2_PREN_MASK | UART_UCR2_PROE_MASK)) | + (uint32_t)UART_UCR2_TXEN(config->enableTx) | (uint32_t)UART_UCR2_RXEN(config->enableRx) | UART_UCR2_IRTS_MASK); + + /* For imx family device, UARTs are used in MUXED mode, so that this bit should always be set.*/ + if (FSL_FEATURE_IUART_RXDMUXSEL) + { + base->UCR3 |= UART_UCR3_RXDMUXSEL_MASK; + } + /* Set TX/RX fifo water mark */ + UART_SetTxFifoWatermark(base, config->txFifoWatermark); + UART_SetRxFifoWatermark(base, config->rxFifoWatermark); + + if (config->enableAutoBaudRate) + { + /* Start automatic baud rate detection */ + UART_EnableAutoBaudRate(base, true); + } + else if (config->baudRate_Bps) + { + /* Stop automatic baud rate detection */ + UART_EnableAutoBaudRate(base, false); + /* Set BaudRate according to uart initialize struct. Baud Rate = Ref Freq / (16 * (UBMR + 1)/(UBIR+1)) */ + if (kStatus_Success != UART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz)) + { + return kStatus_UART_BaudrateNotSupport; + } + } + else + { + /* Stop automatic baud rate detection */ + UART_EnableAutoBaudRate(base, false); + } + + /* Enable UART module */ + UART_Enable(base); + + return kStatus_Success; +} + +void UART_Deinit(UART_Type *base) +{ + /* Wait transmit FIFO buffer and shift register empty */ + while (UART_USR2_TXDC_MASK != (base->USR2 & UART_USR2_TXDC_MASK)) + { + } + /* Disable UART Module */ + UART_Disable(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable uart clock */ + CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void UART_GetDefaultConfig(uart_config_t *config) +{ + assert(config); + + config->baudRate_Bps = 115200U; + config->parityMode = kUART_ParityDisabled; + config->dataBitsCount = kUART_EightDataBits; + config->stopBitCount = kUART_OneStopBit; + config->txFifoWatermark = 2; + config->rxFifoWatermark = 1; + config->enableAutoBaudRate = false; + config->enableTx = false; + config->enableRx = false; +} + +/* This UART instantiation uses a slightly different baud rate calculation. + * Baud Rate = Ref Freq / (16 * (UBMR + 1)/(UBIR+1)). + * To get a baud rate, three register need to be writen, UFCR,UBMR and UBIR + * At first, find the approximately maximum divisor of src_Clock and baudRate_Bps. + * If the numerator and denominator are larger then register maximum value(0xFFFF), + * both of numerator and denominator will be divided by the same value, which + * will ensure numerator and denominator range from 0~maximum value(0xFFFF). + * Then calculate UFCR and UBIR value from numerator, and get UBMR value from denominator. + */ +status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t numerator = 0u; + uint32_t denominator = 0U; + uint32_t divisor = 0U; + uint32_t refFreqDiv = 0U; + uint32_t divider = 1U; + uint64_t baudDiff = 0U; + uint64_t tempNumerator = 0U; + uint32_t tempDenominator = 0u; + + /* get the approximately maximum divisor */ + numerator = srcClock_Hz; + denominator = baudRate_Bps << 4; + divisor = 1; + + while (denominator != 0) + { + divisor = denominator; + denominator = numerator % denominator; + numerator = divisor; + } + + numerator = srcClock_Hz / divisor; + denominator = (baudRate_Bps << 4) / divisor; + + /* numerator ranges from 1 ~ 7 * 64k */ + /* denominator ranges from 1 ~ 64k */ + if ((numerator > (UART_UBIR_INC_MASK * 7)) || (denominator > UART_UBIR_INC_MASK)) + { + uint32_t m = (numerator - 1) / (UART_UBIR_INC_MASK * 7) + 1; + uint32_t n = (denominator - 1) / UART_UBIR_INC_MASK + 1; + uint32_t max = m > n ? m : n; + numerator /= max; + denominator /= max; + if (0 == numerator) + { + numerator = 1; + } + if (0 == denominator) + { + denominator = 1; + } + } + divider = (numerator - 1) / UART_UBIR_INC_MASK + 1; + + switch (divider) + { + case 1: + refFreqDiv = 0x05; + break; + case 2: + refFreqDiv = 0x04; + break; + case 3: + refFreqDiv = 0x03; + break; + case 4: + refFreqDiv = 0x02; + break; + case 5: + refFreqDiv = 0x01; + break; + case 6: + refFreqDiv = 0x00; + break; + case 7: + refFreqDiv = 0x06; + break; + default: + refFreqDiv = 0x05; + break; + } + /* Compare the difference between baudRate_Bps and calculated baud rate. + * Baud Rate = Ref Freq / (16 * (UBMR + 1)/(UBIR+1)). + * baudDiff = (srcClock_Hz/divider)/( 16 * ((numerator / divider)/ denominator). + */ + tempNumerator = srcClock_Hz; + tempDenominator = (numerator << 4); + divisor = 1; + /* get the approximately maximum divisor */ + while (tempDenominator != 0) + { + divisor = tempDenominator; + tempDenominator = tempNumerator % tempDenominator; + tempNumerator = divisor; + } + tempNumerator = srcClock_Hz / divisor; + tempDenominator = (numerator << 4) / divisor; + baudDiff = (tempNumerator * denominator) / tempDenominator; + baudDiff = (baudDiff >= baudRate_Bps) ? (baudDiff - baudRate_Bps) : (baudRate_Bps - baudDiff); + + if (baudDiff < (baudRate_Bps / 100) * 3) + { + base->UFCR &= ~UART_UFCR_RFDIV_MASK; + base->UFCR |= UART_UFCR_RFDIV(refFreqDiv); + base->UBIR = UART_UBIR_INC(denominator - 1); + base->UBMR = UART_UBMR_MOD(numerator / divider - 1); + base->ONEMS = UART_ONEMS_ONEMS(srcClock_Hz / (1000 * divider)); + + return kStatus_Success; + } + else + { + return kStatus_UART_BaudrateNotSupport; + } +} + +void UART_EnableInterrupts(UART_Type *base, uint32_t mask) +{ + assert(0x3F3FF73FU & mask); + + if (0X3F & mask) + { + base->UCR1 |= ((mask << UART_UCR1_ADEN_SHIFT) & UART_UCR1_ADEN_MASK) | + (((mask >> 1) << UART_UCR1_TRDYEN_SHIFT) & UART_UCR1_TRDYEN_MASK) | + (((mask >> 2) << UART_UCR1_IDEN_SHIFT) & UART_UCR1_IDEN_MASK) | + (((mask >> 3) << UART_UCR1_RRDYEN_SHIFT) & UART_UCR1_RRDYEN_MASK) | + (((mask >> 4) << UART_UCR1_TXMPTYEN_SHIFT) & UART_UCR1_TXMPTYEN_MASK) | + (((mask >> 5) << UART_UCR1_RTSDEN_SHIFT) & UART_UCR1_RTSDEN_MASK); + } + if (0X700U & mask) + { + base->UCR2 |= (((mask >> 8) << UART_UCR2_ESCI_SHIFT) & UART_UCR2_ESCI_MASK) | + (((mask >> 9) << UART_UCR2_RTSEN_SHIFT) & UART_UCR2_RTSEN_MASK) | + (((mask >> 10) << UART_UCR2_ATEN_SHIFT) & UART_UCR2_ATEN_MASK); + } + if (0x3FF000 & mask) + { + base->UCR3 |= (((mask >> 12) << UART_UCR3_DTREN_SHIFT) & UART_UCR3_DTREN_MASK) | + (((mask >> 13) << UART_UCR3_PARERREN_SHIFT) & UART_UCR3_PARERREN_MASK) | + (((mask >> 14) << UART_UCR3_FRAERREN_SHIFT) & UART_UCR3_FRAERREN_MASK) | + (((mask >> 15) << UART_UCR3_DCD_SHIFT) & UART_UCR3_DCD_MASK) | + (((mask >> 16) << UART_UCR3_RI_SHIFT) & UART_UCR3_RI_MASK) | + (((mask >> 17) << UART_UCR3_RXDSEN_SHIFT) & UART_UCR3_RXDSEN_MASK) | + (((mask >> 18) << UART_UCR3_AIRINTEN_SHIFT) & UART_UCR3_AIRINTEN_MASK) | + (((mask >> 19) << UART_UCR3_AWAKEN_SHIFT) & UART_UCR3_AWAKEN_MASK) | + (((mask >> 20) << UART_UCR3_DTRDEN_SHIFT) & UART_UCR3_DTRDEN_MASK) | + (((mask >> 21) << UART_UCR3_ACIEN_SHIFT) & UART_UCR3_ACIEN_MASK); + } + if (0x3F000000 & mask) + { + base->UCR4 |= (((mask >> 24) << UART_UCR4_ENIRI_SHIFT) & UART_UCR4_ENIRI_MASK) | + (((mask >> 25) << UART_UCR4_WKEN_SHIFT) & UART_UCR4_WKEN_MASK) | + (((mask >> 26) << UART_UCR4_TCEN_SHIFT) & UART_UCR4_TCEN_MASK) | + (((mask >> 27) << UART_UCR4_BKEN_SHIFT) & UART_UCR4_BKEN_MASK) | + (((mask >> 28) << UART_UCR4_OREN_SHIFT) & UART_UCR4_OREN_MASK) | + (((mask >> 29) << UART_UCR4_DREN_SHIFT) & UART_UCR4_DREN_MASK); + } +} + +void UART_DisableInterrupts(UART_Type *base, uint32_t mask) +{ + assert(0x3F3FF73FU & mask); + + if (0X3F & mask) + { + base->UCR1 &= ~(((mask << UART_UCR1_ADEN_SHIFT) & UART_UCR1_ADEN_MASK) | + (((mask >> 1) << UART_UCR1_TRDYEN_SHIFT) & UART_UCR1_TRDYEN_MASK) | + (((mask >> 2) << UART_UCR1_IDEN_SHIFT) & UART_UCR1_IDEN_MASK) | + (((mask >> 3) << UART_UCR1_RRDYEN_SHIFT) & UART_UCR1_RRDYEN_MASK) | + (((mask >> 4) << UART_UCR1_TXMPTYEN_SHIFT) & UART_UCR1_TXMPTYEN_MASK) | + (((mask >> 5) << UART_UCR1_RTSDEN_SHIFT) & UART_UCR1_RTSDEN_MASK)); + } + if (0X700U & mask) + { + base->UCR2 &= ~((((mask >> 8) << UART_UCR2_ESCI_SHIFT) & UART_UCR2_ESCI_MASK) | + (((mask >> 9) << UART_UCR2_RTSEN_SHIFT) & UART_UCR2_RTSEN_MASK) | + (((mask >> 10) << UART_UCR2_ATEN_SHIFT) & UART_UCR2_ATEN_MASK)); + } + if (0x3FF000 & mask) + { + base->UCR3 &= ~((((mask >> 12) << UART_UCR3_DTREN_SHIFT) & UART_UCR3_DTREN_MASK) | + (((mask >> 13) << UART_UCR3_PARERREN_SHIFT) & UART_UCR3_PARERREN_MASK) | + (((mask >> 14) << UART_UCR3_FRAERREN_SHIFT) & UART_UCR3_FRAERREN_MASK) | + (((mask >> 15) << UART_UCR3_DCD_SHIFT) & UART_UCR3_DCD_MASK) | + (((mask >> 16) << UART_UCR3_RI_SHIFT) & UART_UCR3_RI_MASK) | + (((mask >> 17) << UART_UCR3_RXDSEN_SHIFT) & UART_UCR3_RXDSEN_MASK) | + (((mask >> 18) << UART_UCR3_AIRINTEN_SHIFT) & UART_UCR3_AIRINTEN_MASK) | + (((mask >> 19) << UART_UCR3_AWAKEN_SHIFT) & UART_UCR3_AWAKEN_MASK) | + (((mask >> 20) << UART_UCR3_DTRDEN_SHIFT) & UART_UCR3_DTRDEN_MASK) | + (((mask >> 21) << UART_UCR3_ACIEN_SHIFT) & UART_UCR3_ACIEN_MASK)); + } + if (0x3F000000 & mask) + { + base->UCR4 &= ~((((mask >> 24) << UART_UCR4_ENIRI_SHIFT) & UART_UCR4_ENIRI_MASK) | + (((mask >> 25) << UART_UCR4_WKEN_SHIFT) & UART_UCR4_WKEN_MASK) | + (((mask >> 26) << UART_UCR4_TCEN_SHIFT) & UART_UCR4_TCEN_MASK) | + (((mask >> 27) << UART_UCR4_BKEN_SHIFT) & UART_UCR4_BKEN_MASK) | + (((mask >> 28) << UART_UCR4_OREN_SHIFT) & UART_UCR4_OREN_MASK) | + (((mask >> 29) << UART_UCR4_DREN_SHIFT) & UART_UCR4_DREN_MASK)); + } +} + +uint32_t UART_GetEnabledInterrupts(UART_Type *base) +{ + assert(base); + uint32_t temp = 0U; + /* Get enabled interrupts from UCR1 */ + temp |= ((base->UCR1 & UART_UCR1_ADEN_MASK) >> UART_UCR1_ADEN_SHIFT) | + (((base->UCR1 & UART_UCR1_TRDYEN_MASK) >> UART_UCR1_TRDYEN_SHIFT) << 1) | + (((base->UCR1 & UART_UCR1_IDEN_MASK) >> UART_UCR1_IDEN_SHIFT) << 2) | + (((base->UCR1 & UART_UCR1_RRDYEN_MASK) >> UART_UCR1_RRDYEN_SHIFT) << 3) | + (((base->UCR1 & UART_UCR1_TXMPTYEN_MASK) >> UART_UCR1_TXMPTYEN_SHIFT) << 4) | + (((base->UCR1 & UART_UCR1_RTSDEN_MASK) >> UART_UCR1_RTSDEN_SHIFT) << 5); + /* Get enabled interrupts from UCR2 */ + temp |= (((base->UCR2 & UART_UCR2_ESCI_MASK) >> UART_UCR2_ESCI_SHIFT) << 8) | + (((base->UCR2 & UART_UCR2_RTSEN_MASK) >> UART_UCR2_RTSEN_SHIFT) << 9) | + (((base->UCR2 & UART_UCR2_ATEN_MASK) >> UART_UCR2_ATEN_SHIFT) << 10); + /* Get enabled interrupts from UCR3 */ + temp |= (((base->UCR3 & UART_UCR3_DTREN_MASK) >> UART_UCR3_DTREN_SHIFT) << 12) | + (((base->UCR3 & UART_UCR3_PARERREN_MASK) >> UART_UCR3_PARERREN_SHIFT) << 13) | + (((base->UCR3 & UART_UCR3_FRAERREN_MASK) >> UART_UCR3_FRAERREN_SHIFT) << 14) | + (((base->UCR3 & UART_UCR3_DCD_MASK) >> UART_UCR3_DCD_SHIFT) << 15) | + (((base->UCR3 & UART_UCR3_RI_MASK) >> UART_UCR3_RI_SHIFT) << 16) | + (((base->UCR3 & UART_UCR3_RXDSEN_MASK) >> UART_UCR3_RXDSEN_SHIFT) << 17) | + (((base->UCR3 & UART_UCR3_AIRINTEN_MASK) >> UART_UCR3_AIRINTEN_SHIFT) << 18) | + (((base->UCR3 & UART_UCR3_AWAKEN_MASK) >> UART_UCR3_AWAKEN_SHIFT) << 19) | + (((base->UCR3 & UART_UCR3_DTRDEN_MASK) >> UART_UCR3_DTRDEN_SHIFT) << 20) | + (((base->UCR3 & UART_UCR3_ACIEN_MASK) >> UART_UCR3_ACIEN_SHIFT) << 21); + /* Get enabled interrupts from UCR4 */ + temp |= (((base->UCR4 & UART_UCR4_ENIRI_MASK) >> UART_UCR4_ENIRI_SHIFT) << 24) | + (((base->UCR4 & UART_UCR4_WKEN_MASK) >> UART_UCR4_WKEN_SHIFT) << 25) | + (((base->UCR4 & UART_UCR4_TCEN_MASK) >> UART_UCR4_TCEN_SHIFT) << 26) | + (((base->UCR4 & UART_UCR4_BKEN_MASK) >> UART_UCR4_BKEN_SHIFT) << 27) | + (((base->UCR4 & UART_UCR4_OREN_MASK) >> UART_UCR4_OREN_SHIFT) << 28) | + (((base->UCR4 & UART_UCR4_DREN_MASK) >> UART_UCR4_DREN_SHIFT) << 29); + + return temp; +} + +bool UART_GetStatusFlag(UART_Type *base, uint32_t flag) +{ + volatile uint32_t *uart_reg; + + uart_reg = (uint32_t *)((uint32_t)base + (flag >> 16)); + return (bool)(((*uart_reg) >> (flag & 0x1FU)) & 0x1U); +} + +void UART_ClearStatusFlag(UART_Type *base, uint32_t flag) +{ + volatile uint32_t *uart_reg = 0; + uint32_t uart_mask = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (flag >> 16)); + uart_mask = (1U << (flag & 0x1FU)); + + *uart_reg = uart_mask; +} + +void UART_EnableDMA(UART_Type *base, uint32_t dmaSource, bool enable) +{ + volatile uint32_t *uart_reg = 0; + uint32_t uart_mask = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (dmaSource >> 16)); + uart_mask = (1U << (dmaSource & 0x1FU)); + if (enable) + { + *uart_reg |= uart_mask; + } + else + { + *uart_reg &= ~uart_mask; + } +} + +void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length) +{ + assert(data); + + while (length--) + { + /* Wait for TX fifo valid. + * This API can only ensure that the data is written into the data buffer but can't + * ensure all data in the data buffer are sent into the transmit shift buffer. + */ + while (!(base->USR2 & UART_USR2_TXDC_MASK)) + { + } + UART_WriteByte(base, *(data++)); + } +} + +status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length) +{ + assert(data); + + while (length--) + { + /* Wait for receive data in URXD register is ready */ + while (!(base->USR2 & UART_USR2_RDR_MASK)) + { + /* Parity error check for receiving character */ + if (base->USR1 & UART_USR1_PARITYERR_MASK) + { + UART_ClearStatusFlag(base, kUART_ParityErrorFlag); + return kStatus_UART_ParityError; + } + /* Framing error check for receiving character */ + if (base->USR1 & UART_USR1_FRAMERR_MASK) + { + UART_ClearStatusFlag(base, kUART_FrameErrorFlag); + return kStatus_UART_FramingError; + } + /* Over run check for receiving character */ + if (base->USR2 & UART_USR2_ORE_MASK) + { + UART_ClearStatusFlag(base, kUART_RxOverrunFlag); + return kStatus_UART_RxHardwareOverrun; + } + } + /* Read data from URXD */ + *(data++) = UART_ReadByte(base); + } + + return kStatus_Success; +} + +static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length) +{ + assert(data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + * peripheral to write. UTXD register holds the parallel transmit data inputs. In 7-bit mode, + * D7 is ignored. In 8-bit mode, all bits are used. + */ + for (i = 0; i < length; i++) + { + base->UTXD = data[i] & UART_UTXD_TX_DATA_MASK; + } +} + +static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length) +{ + assert(data); + + size_t i; + + /* The Non Blocking read data API assume user have ensured there is enough space in + * peripheral to write. The URXD holds the received character,In 7-bit mode, + * the most significant bit (MSB) is forced to 0.In 8-bit mode, all bits are active. + */ + for (i = 0; i < length; i++) + { + data[i] = (uint8_t)((base->URXD & UART_URXD_RX_DATA_MASK) >> UART_URXD_RX_DATA_SHIFT); + } +} + +void UART_TransferCreateHandle(UART_Type *base, + uart_handle_t *handle, + uart_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the TX/RX state. */ + handle->rxState = kUART_RxIdle; + handle->txState = kUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Get instance from peripheral base address. */ + instance = UART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_uartHandle[instance - 1] = handle; + + s_uartIsr = UART_TransferHandleIRQ; + + /* Enable interrupt in NVIC. */ + EnableIRQ(s_uartIRQ[instance]); +} + +void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + assert(handle); + assert(ringBuffer); + + /* Setup the ringbuffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + UART_EnableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable); +} + +void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + if (handle->rxState == kUART_RxIdle) + { + UART_DisableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + assert(xfer->dataSize); + assert(xfer->data); + + status_t status; + + /* Return error if current TX busy. */ + if (kUART_TxBusy == handle->txState) + { + status = kStatus_UART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kUART_TxBusy; + + /* Enable transmiter interrupt. */ + UART_EnableInterrupts(base, kUART_TxReadyEnable); + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + UART_DisableInterrupts(base, kUART_TxEmptyEnable); + + handle->txDataSize = 0; + handle->txState = kUART_TxIdle; +} + +status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(count); + + if (kUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +status_t UART_TransferReceiveNonBlocking(UART_Type *base, + uart_handle_t *handle, + uart_transfer_t *xfer, + size_t *receivedBytes) +{ + assert(handle); + assert(xfer); + assert(xfer->data); + assert(xfer->dataSize); + + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + + if (kUART_RxBusy == handle->rxState) + { + status = kStatus_UART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable UART RX IRQ, protect ring buffer. */ + UART_DisableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = UART_TransferGetRxRingBufferLength(handle); + + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUART_RxBusy; + } + + /* Enable UART RX IRQ if previously enabled. */ + UART_EnableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable); + + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUART_RxBusy; + + /* Enable RX/Rx overrun/framing error interrupt. */ + UART_EnableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable); + } + + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + UART_DisableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = kUART_RxIdle; +} + +status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(count); + + if (kUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + uint8_t count; + uint8_t tempCount; + + /* If RX framing error */ + if (UART_USR1_FRAMERR_MASK & base->USR1) + { + /* Write 1 to clear framing error flag */ + base->USR1 |= UART_USR1_FRAMERR_MASK; + + handle->rxState = kUART_RxFramingError; + handle->rxDataSize = 0U; + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_FramingError, handle->userData); + } + } + + /* If RX parity error */ + if (UART_USR1_PARITYERR_MASK & base->USR1) + { + /* Write 1 to clear parity error flag. */ + base->USR1 |= UART_USR1_PARITYERR_MASK; + + handle->rxState = kUART_RxParityError; + handle->rxDataSize = 0U; + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_ParityError, handle->userData); + } + } + + /* If RX overrun. */ + if (UART_USR2_ORE_MASK & base->USR2) + { + /* Write 1 to clear overrun flag. */ + base->USR2 |= UART_USR2_ORE_MASK; + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData); + } + } + + /* Receive data FIFO buffer reach the trigger level */ + if (((UART_USR1_RRDY_MASK)&base->USR1) && (UART_UCR1_RRDYEN_MASK & base->UCR1)) + { + /* Get the size that stored in receive FIFO buffer for this interrupt. */ + count = ((base->UFCR & UART_UFCR_RXTL_MASK) >> UART_UFCR_RXTL_SHIFT); + + /* If count and handle->rxDataSize are not 0, first save data to handle->rxData. */ + while ((count) && (handle->rxDataSize)) + { + tempCount = MIN(handle->rxDataSize, count); + /* Using non block API to read the data from the registers. */ + UART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData += tempCount; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kUART_RxIdle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (handle->rxRingBuffer) + { + while (count--) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = + (uint8_t)((base->URXD & UART_URXD_RX_DATA_MASK) >> UART_URXD_RX_DATA_SHIFT); + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + + else if (!handle->rxDataSize) + { + /* Disable RX interrupt/overrun interrupt/framing error interrupt */ + UART_DisableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable); + } + else + { + } + } + /* Receive FIFO buffer has been idle for a time of 8 characters, and FIFO data level + * is less than RxFIFO threshold level. + */ + if (((UART_USR1_AGTIM_MASK)&base->USR1) && (UART_UCR2_ATEN_MASK & base->UCR2)) + { + /* If count and handle->rxDataSize are not 0, first save data to handle->rxData. */ + while ((base->USR2 & UART_USR2_RDR_MASK) && (handle->rxDataSize)) + { + /* Read one data from the URXD registers. */ + *handle->rxData = UART_ReadByte(base); + handle->rxData += 1; + handle->rxDataSize -= 1; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kUART_RxIdle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (handle->rxRingBuffer) + { + while (base->USR2 & UART_USR2_RDR_MASK) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + /* Read one data from URXD register. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = UART_ReadByte(base); + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If ring buffer is not used and rxDataSize is 0 */ + else if (!handle->rxDataSize) + { + /* Disable RX interrupt/overrun interrupt/framing error interrupt */ + UART_DisableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable); + } + else + { + } + /* Clear aging timer flag for next interrupt */ + UART_ClearStatusFlag(base, kUART_AgingTimerFlag); + } + /* If frame error or parity error happened, stop the RX interrupt when ues no ring buffer */ + if (((handle->rxState == kUART_RxFramingError) || (handle->rxState == kUART_RxParityError)) && + (!handle->rxRingBuffer)) + { + /* Disable Receive ready interrupt, aging timer interrupt, receive over run interrupt, + * parity error interrupt and frame error interrupt. + */ + UART_DisableInterrupts(base, kUART_RxReadyEnable | kUART_AgingTimerEnable | kUART_RxOverrunEnable | + kUART_ParityErrorEnable | kUART_FrameErrorEnable); + } + + /* Send data register empty and the interrupt is enabled. */ + if ((UART_USR1_TRDY_MASK & base->USR1) && (UART_UCR1_TRDYEN_MASK & base->UCR1)) + { + /* Get the bytes that available at this moment. */ + if (0U != ((base->UFCR & UART_UFCR_TXTL_MASK) >> UART_UFCR_TXTL_SHIFT)) + { + if (UART_UTS_TXEMPTY_MASK & (base->UTS)) + { + count = FSL_FEATURE_IUART_FIFO_SIZEn(base); + } + else + { + count = + FSL_FEATURE_IUART_FIFO_SIZEn(base) - ((base->UFCR & UART_UFCR_TXTL_MASK) >> UART_UFCR_TXTL_SHIFT); + } + } + else + { + count = 1; + } + + while ((count) && (handle->txDataSize)) + { + if (0U != ((base->UFCR & UART_UFCR_TXTL_MASK) >> UART_UFCR_TXTL_SHIFT)) + { + tempCount = MIN(handle->txDataSize, count); + } + else + { + tempCount = 1; + } + /* Using non block API to write the data to the registers. */ + UART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData += tempCount; + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, TX finished. */ + if (!handle->txDataSize) + { + handle->txState = kUART_TxIdle; + /* Disable TX FIFO buffer empty interrupt. */ + UART_DisableInterrupts(base, kUART_TxReadyEnable); + /* Trigger callback. + * Note: This callback is called when all data have been send to TX FIFO, + * but this not mean transmit has completed, some data may still in + * FIFO buffer. + */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData); + } + } + } + } +} + +#if defined(UART1) +void UART1_DriverIRQHandler(void) +{ + s_uartIsr(UART1, s_uartHandle[0]); +} +#endif + +#if defined(UART2) +void UART2_DriverIRQHandler(void) +{ + s_uartIsr(UART2, s_uartHandle[1]); +} +#endif + +#if defined(UART3) +void UART3_DriverIRQHandler(void) +{ + s_uartIsr(UART3, s_uartHandle[2]); +} +#endif + +#if defined(UART4) +void UART4_DriverIRQHandler(void) +{ + s_uartIsr(UART4, s_uartHandle[3]); +} +#endif + +#if defined(UART5) +void UART5_DriverIRQHandler(void) +{ + s_uartIsr(UART5, s_uartHandle[4]); +} +#endif + +#if defined(UART6) +void UART6_DriverIRQHandler(void) +{ + s_uartIsr(UART6, s_uartHandle[5]); +} +#endif + +#if defined(UART7) +void UART7_DriverIRQHandler(void) +{ + s_uartIsr(UART7, s_uartHandle[6]); +} +#endif + +#if defined(UART8) +void UART8_DriverIRQHandler(void) +{ + s_uartIsr(UART8, s_uartHandle[7]); +} +#endif diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_uart.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_uart.h new file mode 100644 index 0000000000..0dd8ed8200 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_uart.h @@ -0,0 +1,870 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_UART_H_ +#define _FSL_UART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup uart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief UART driver version 2.0.0. */ +#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief Error codes for the UART driver. */ +enum _uart_status +{ + kStatus_UART_TxBusy = MAKE_STATUS(kStatusGroup_IUART, 0), /*!< Transmitter is busy. */ + kStatus_UART_RxBusy = MAKE_STATUS(kStatusGroup_IUART, 1), /*!< Receiver is busy. */ + kStatus_UART_TxIdle = MAKE_STATUS(kStatusGroup_IUART, 2), /*!< UART transmitter is idle. */ + kStatus_UART_RxIdle = MAKE_STATUS(kStatusGroup_IUART, 3), /*!< UART receiver is idle. */ + kStatus_UART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_IUART, 4), /*!< TX FIFO watermark too large */ + kStatus_UART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_IUART, 5), /*!< RX FIFO watermark too large */ + kStatus_UART_FlagCannotClearManually = + MAKE_STATUS(kStatusGroup_IUART, 6), /*!< UART flag can't be manually cleared. */ + kStatus_UART_Error = MAKE_STATUS(kStatusGroup_IUART, 7), /*!< Error happens on UART. */ + kStatus_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_IUART, 8), /*!< UART RX software ring buffer overrun. */ + kStatus_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_IUART, 9), /*!< UART RX receiver overrun. */ + kStatus_UART_NoiseError = MAKE_STATUS(kStatusGroup_IUART, 10), /*!< UART noise error. */ + kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_IUART, 11), /*!< UART framing error. */ + kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_IUART, 12), /*!< UART parity error. */ + kStatus_UART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_IUART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_UART_BreakDetect = MAKE_STATUS(kStatusGroup_IUART, 14), /*!< Receiver detect BREAK signal */ +}; + +/*! @brief UART data bits count. */ +typedef enum _uart_data_bits +{ + kUART_SevenDataBits = 0x0U, /*!< Seven data bit */ + kUART_EightDataBits = 0x1U, /*!< Eight data bit */ +} uart_data_bits_t; + +/*! @brief UART parity mode. */ +typedef enum _uart_parity_mode +{ + kUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUART_ParityEven = 0x2U, /*!< Even error check is selected */ + kUART_ParityOdd = 0x3U, /*!< Odd error check is selected */ +} uart_parity_mode_t; + +/*! @brief UART stop bit count. */ +typedef enum _uart_stop_bit_count +{ + kUART_OneStopBit = 0x0U, /*!< One stop bit */ + kUART_TwoStopBit = 0x1U, /*!< Two stop bits */ +} uart_stop_bit_count_t; + +/*! @brief This structure contains the settings for all of the UART interrupt configurations. */ +enum _uart_interrupt_enable +{ + kUART_AutoBaudEnable = 0x1U, /* !< Automatic baud rate detection Interrupt Enable. */ + kUART_TxReadyEnable = (0X1U << 1), /* !< transmitter ready Interrupt Enable. */ + kUART_IdleEnable = (0x1U << 2), /* !< IDLE Interrupt Enable. */ + kUART_RxReadyEnable = (0x1U << 3), /* !< Receiver Ready Interrupt Enable. */ + kUART_TxEmptyEnable = (0x1U << 4), /* !< Transmitter Empty Interrupt Enable. */ + kUART_RtsDeltaEnable = (0x1U << 5), /* !< RTS Delta Interrupt Enable. */ + kUART_EscapeEnable = (0x1U << 8), /* !< Escape Sequence Interrupt Enable. */ + kUART_RtsEnable = (0x1U << 9), /* !< Request to Send Interrupt Enable. */ + kUART_AgingTimerEnable = (0x1U << 10), /* !< Aging Timer Interrupt Enable. */ + kUART_DtrEnable = (0x1U << 12), /* !< Data Terminal Ready Interrupt Enable. */ + kUART_ParityErrorEnable = (0x1U << 13), /* !< Parity Error Interrupt Enable. */ + kUART_FrameErrorEnable = (0x1U << 14), /* !< Frame Error Interrupt Enable. */ + kUART_DcdEnable = (0x1U << 15), /* !< Data Carrier Detect Interrupt Enable. */ + kUART_RiEnable = (0x1U << 16), /* !< Ring Indicator Interrupt Enable. */ + kUART_RxDsEnable = (0x1U << 17), /* !< Receive Status Interrupt Enable. */ + kUART_tAirWakeEnable = (0x1U << 18), /* !< Asynchronous IR WAKE Interrupt Enable. */ + kUART_AwakeEnable = (0x1U << 19), /* !< Asynchronous WAKE Interrupt Enable. */ + kUART_DtrDeltaEnable = (0x1U << 20), /* !< Data Terminal Ready Delta Interrupt Enable. */ + kUART_AutoBaudCntEnable = (0x1U << 21), /* !< Auto-baud Counter Interrupt Enable. */ + kUART_IrEnable = (0X1U << 24), /* !< Serial Infrared Interrupt Enable. */ + kUART_WakeEnable = (0X1U << 25), /* !< WAKE Interrupt Enable. */ + kUART_TxCompleteEnable = (0X1U << 26), /* !< TransmitComplete Interrupt Enable. */ + kUART_BreakDetectEnable = (0X1U << 27), /* !< BREAK Condition Detected Interrupt Enable. */ + kUART_RxOverrunEnable = (0X1U << 28), /* !< Receiver Overrun Interrupt Enable. */ + kUART_RxDataReadyEnable = (0X1U << 29), /* !< Receive Data Ready Interrupt Enable. */ + kUART_AllInterruptsEnable = kUART_AutoBaudEnable | kUART_TxReadyEnable | kUART_IdleEnable | kUART_RxReadyEnable | + kUART_TxEmptyEnable | kUART_RtsDeltaEnable | kUART_EscapeEnable | kUART_RtsEnable | + kUART_AgingTimerEnable | kUART_DtrEnable | kUART_ParityErrorEnable | + kUART_FrameErrorEnable | kUART_DcdEnable | kUART_RiEnable | kUART_RxDsEnable | + kUART_tAirWakeEnable | kUART_AwakeEnable | kUART_DtrDeltaEnable | + kUART_AutoBaudCntEnable | kUART_IrEnable | kUART_WakeEnable | kUART_TxCompleteEnable | + kUART_BreakDetectEnable | kUART_RxOverrunEnable | kUART_RxDataReadyEnable, +}; + +/*! + * @brief UART status flags. + * + * This provides constants for the UART status flags for use in the UART functions. + */ +enum _uart_flags +{ + kUART_RxCharReadyFlag = 0x0000000FU, /*!< Rx Character Ready Flag. */ + kUART_RxErrorFlag = 0x0000000EU, /*!< Rx Error Detect Flag. */ + kUART_RxOverrunErrorFlag = 0x0000000DU, /*!< Rx Overrun Flag. */ + kUART_RxFrameErrorFlag = 0x0000000CU, /*!< Rx Frame Error Flag. */ + kUART_RxBreakDetectFlag = 0x0000000BU, /*!< Rx Break Detect Flag. */ + kUART_RxParityErrorFlag = 0x0000000AU, /*!< Rx Parity Error Flag. */ + kUART_ParityErrorFlag = 0x0094000FU, /*!< Parity Error Interrupt Flag. */ + kUART_RtsStatusFlag = 0x0094000EU, /*!< RTS_B Pin Status Flag. */ + kUART_TxReadyFlag = 0x0094000DU, /*!< Transmitter Ready Interrupt/DMA Flag. */ + kUART_RtsDeltaFlag = 0x0094000CU, /*!< RTS Delta Flag. */ + kUART_EscapeFlag = 0x0094000BU, /*!< Escape Sequence Interrupt Flag. */ + kUART_FrameErrorFlag = 0x0094000AU, /*!< Frame Error Interrupt Flag. */ + kUART_RxReadyFlag = 0x00940009U, /*!< Receiver Ready Interrupt/DMA Flag. */ + kUART_AgingTimerFlag = 0x00940008U, /*!< Aging Timer Interrupt Flag. */ + kUART_DtrDeltaFlag = 0x00940007U, /*!< DTR Delta Flag. */ + kUART_RxDsFlag = 0x00940006U, /*!< Receiver IDLE Interrupt Flag. */ + kUART_tAirWakeFlag = 0x00940005U, /*!< Asynchronous IR WAKE Interrupt Flag. */ + kUART_AwakeFlag = 0x00940004U, /*!< Asynchronous WAKE Interrupt Flag. */ + kUART_Rs485SlaveAddrMatchFlag = 0x00940003U, /*!< RS-485 Slave Address Detected Interrupt Flag. */ + kUART_AutoBaudFlag = 0x0098000FU, /*!< Automatic Baud Rate Detect Complete Flag. */ + kUART_TxEmptyFlag = 0x0098000EU, /*!< Transmit Buffer FIFO Empty. */ + kUART_DtrFlag = 0x0098000DU, /*!< DTR edge triggered interrupt flag. */ + kUART_IdleFlag = 0x0098000CU, /*!< Idle Condition Flag. */ + kUART_AutoBaudCntStopFlag = 0x0098000BU, /*!< Auto-baud Counter Stopped Flag. */ + kUART_RiDeltaFlag = 0x0098000AU, /*!< Ring Indicator Delta Flag. */ + kUART_RiFlag = 0x00980009U, /*!< Ring Indicator Input Flag. */ + kUART_IrFlag = 0x00980008U, /*!< Serial Infrared Interrupt Flag. */ + kUART_WakeFlag = 0x00980007U, /*!< Wake Flag. */ + kUART_DcdDeltaFlag = 0x00980006U, /*!< Data Carrier Detect Delta Flag. */ + kUART_DcdFlag = 0x00980005U, /*!< Data Carrier Detect Input Flag. */ + kUART_RtsFlag = 0x00980004U, /*!< RTS Edge Triggered Interrupt Flag. */ + kUART_TxCompleteFlag = 0x00980003U, /*!< Transmitter Complete Flag. */ + kUART_BreakDetectFlag = 0x00980002U, /*!< BREAK Condition Detected Flag. */ + kUART_RxOverrunFlag = 0x00980001U, /*!< Overrun Error Flag. */ + kUART_RxDataReadyFlag = 0x00980000U, /*!< Receive Data Ready Flag. */ +}; + +/*! @brief UART configuration structure. */ +typedef struct _uart_config +{ + uint32_t baudRate_Bps; /*!< UART baud rate. */ + uart_parity_mode_t parityMode; /*!< Parity error check mode of this module. */ + uart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ + uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits in one frame. */ + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ + bool enableAutoBaudRate; /*!< Enable automatic baud rate detection */ + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} uart_config_t; + +/*! @brief UART transfer structure. */ +typedef struct _uart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} uart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _uart_handle uart_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData); + +/*! @brief UART handle structure. */ +struct _uart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + uart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Resets the UART using software. + * + * This function resets the transmit and receive state machines, all FIFOs and register + * USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3] + * + * @param base UART peripheral base address. + */ +static inline void UART_SoftwareReset(UART_Type *base) +{ + base->UCR2 &= ~UART_UCR2_SRST_MASK; + while ((base->UCR2 & UART_UCR2_SRST_MASK) == 0) + { + } +} + +/* @} */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an UART instance with the user configuration structure and the peripheral clock. + * + * This function configures the UART module with user-defined settings. Call the UART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the UART. + * @code + * uart_config_t uartConfig; + * uartConfig.baudRate_Bps = 115200U; + * uartConfig.parityMode = kUART_ParityDisabled; + * uartConfig.dataBitsCount = kUART_EightDataBits; + * uartConfig.stopBitCount = kUART_OneStopBit; + * uartConfig.txFifoWatermark = 2; + * uartConfig.rxFifoWatermark = 1; + * uartConfig.enableAutoBaudrate = false; + * uartConfig.enableTx = true; + * uartConfig.enableRx = true; + * UART_Init(UART1, &uartConfig, 24000000U); + * @endcode + * + * @param base UART peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @param srcClock_Hz UART clock source frequency in HZ. + * @retval kStatus_Success UART initialize succeed + */ +status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a UART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the UART clock. + * + * @param base UART peripheral base address. + */ +void UART_Deinit(UART_Type *base); + +/*!l + * @brief Gets the default configuration structure. + * + * This function initializes the UART configuration structure to a default value. The default + * values are: + * uartConfig->baudRate_Bps = 115200U; + * uartConfig->parityMode = kUART_ParityDisabled; + * uartConfig->dataBitsCount = kUART_EightDataBits; + * uartConfig->stopBitCount = kUART_OneStopBit; + * uartConfig->txFifoWatermark = 2; + * uartConfig->rxFifoWatermark = 1; + * uartConfig->enableAutoBaudrate = flase; + * uartConfig->enableTx = false; + * uartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void UART_GetDefaultConfig(uart_config_t *config); + +/*! + * @brief Sets the UART instance baud rate. + * + * This function configures the UART module baud rate. This function is used to update + * the UART module baud rate after the UART module is initialized by the UART_Init. + * @code + * UART_SetBaudRate(UART1, 115200U, 20000000U); + * @endcode + * + * @param base UART peripheral base address. + * @param baudRate_Bps UART baudrate to be set. + * @param srcClock_Hz UART clock source freqency in Hz. + * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in the current clock source. + * @retval kStatus_Success Set baudrate succeeded. + */ +status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); +/*! + * @brief This function is used to Enable the UART Module. + * + * @param base UART base pointer. + */ +static inline void UART_Enable(UART_Type *base) +{ + base->UCR1 |= UART_UCR1_UARTEN_MASK; +} + +/*! + * @brief This function is used to Disable the UART Module. + * + * @param base UART base pointer. + */ +static inline void UART_Disable(UART_Type *base) +{ + base->UCR1 &= ~UART_UCR1_UARTEN_MASK; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief This function is used to get the current status of specific + * UART status flag(including interrupt flag). The available + * status flag can be select from @ref uart_status_flag_t enumeration. + * + * @param base UART base pointer. + * @param flag Status flag to check. + * @retval current state of corresponding status flag. + */ +bool UART_GetStatusFlag(UART_Type *base, uint32_t flag); + +/*! + * @brief This function is used to clear the current status + * of specific UART status flag. The available status + * flag can be select from @ref uart_status_flag_t enumeration. + * + * @param base UART base pointer. + * @param flag Status flag to clear. + */ +void UART_ClearStatusFlag(UART_Type *base, uint32_t flag); + +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables UART interrupts according to the provided mask. + * + * This function enables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. + * For example, to enable TX empty interrupt and RX data ready interrupt, do the following. + * @code + * UART_EnableInterrupts(UART1,kUART_TxEmptyEnable | kUART_RxDataReadyEnable); + * @endcode + * + * @param base UART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. + */ +void UART_EnableInterrupts(UART_Type *base, uint32_t mask); + +/*! + * @brief Disables the UART interrupts according to the provided mask. + * + * This function disables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. + * For example, to disable TX empty interrupt and RX data ready interrupt do the following. + * @code + * UART_EnableInterrupts(UART1,kUART_TxEmptyEnable | kUART_RxDataReadyEnable); + * @endcode + * + * @param base UART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _uart_interrupt_enable. + */ +void UART_DisableInterrupts(UART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled UART interrupts. + * + * This function gets the enabled UART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _uart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _uart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1); + * + * if (kUART_TxEmptyEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base UART peripheral base address. + * @return UART interrupt flags which are logical OR of the enumerators in @ref _uart_interrupt_enable. + */ +uint32_t UART_GetEnabledInterrupts(UART_Type *base); + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the UART transmitter. + * + * This function enables or disables the UART transmitter. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableTx(UART_Type *base, bool enable) +{ + if (enable) + { + base->UCR2 |= UART_UCR2_TXEN_MASK; + } + else + { + base->UCR2 &= ~UART_UCR2_TXEN_MASK; + } +} + +/*! + * @brief Enables or disables the UART receiver. + * + * This function enables or disables the UART receiver. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableRx(UART_Type *base, bool enable) +{ + if (enable) + { + base->UCR2 |= UART_UCR2_RXEN_MASK; + } + else + { + base->UCR2 &= ~UART_UCR2_RXEN_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function is used to write data to transmitter register. + * The upper layer must ensure that the TX register is empty or that + * the TX FIFO has room before calling this function. + * + * @param base UART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void UART_WriteByte(UART_Type *base, uint8_t data) +{ + base->UTXD = data & UART_UTXD_TX_DATA_MASK; +} + +/*! + * @brief Reads the receiver register. + * + * This function is used to read data from receiver register. + * The upper layer must ensure that the receiver register is full or that + * the RX FIFO has data before calling this function. + * + * @param base UART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t UART_ReadByte(UART_Type *base) +{ + return (uint8_t)((base->URXD & UART_URXD_RX_DATA_MASK) >> UART_URXD_RX_DATA_SHIFT); +} + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @note This function does not check whether all data is sent out to the bus. + * Before disabling the TX, check kUART_TransmissionCompleteFlag to ensure that the TX is + * finished. + * + * @param base UART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data, and reads data from the TX register. + * + * @param base UART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data. + * @retval kStatus_UART_NoiseError A noise error occurred while receiving data. + * @retval kStatus_UART_FramingError A framing error occurred while receiving data. + * @retval kStatus_UART_ParityError A parity error occurred while receiving data. + * @retval kStatus_Success Successfully received all data. + */ +status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle. + * + * This function initializes the UART handle which can be used for other UART + * transactional APIs. Usually, for a specified UART instance, + * call this API once to get the initialized handle. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void UART_TransferCreateHandle(UART_Type *base, + uart_handle_t *handle, + uart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the UART_TransferReceiveNonBlocking() API. If data is already received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize Size of the ring buffer. + */ +void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle UART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_UART_TxIdle as status parameter. + * + * @note The kStatus_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX, + * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART transfer structure. See #uart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_UART_TxBusy Previous transmission still not finished; data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out + * how many bytes are not sent out. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the interrupt method. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument The parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the UART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART transfer structure, see #uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_UART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferReceiveNonBlocking(UART_Type *base, + uart_handle_t *handle, + uart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes are not received yet. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); + +/*! + * @brief UART IRQ handle function. + * + * This function handles the UART transmit and receive IRQ request. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle); + +/*@}*/ + +/*! + * @name DMA control functions. + * @{ + */ + +/*! + * @brief Enables or disables the UART transmitter DMA request. + * + * This function enables or disables the transmit request when the transmitter + * has one or more slots available in the TxFIFO. The fill level in the TxFIFO + * that generates the DMA request is controlled by the TXTL bits. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableTxDMA(UART_Type *base, bool enable) +{ + assert(base); + + if (enable) + { + base->UCR1 |= UART_UCR1_TXDMAEN_MASK; + } + else + { + base->UCR1 &= ~UART_UCR1_TXDMAEN_MASK; + } +} + +/*! + * @brief Enables or disables the UART receiver DMA request. + * + * This function enables or disables the receive request when the receiver + * has data in the RxFIFO. The fill level in the RxFIFO at which a DMA request + * is generated is controlled by the RXTL bits . + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableRxDMA(UART_Type *base, bool enable) +{ + assert(base); + + if (enable) + { + base->UCR1 |= UART_UCR1_RXDMAEN_MASK; + } + else + { + base->UCR1 &= ~UART_UCR1_RXDMAEN_MASK; + } +} + +/*@}*/ + +/*! + * @name FIFO control functions. + * @{ + */ + +/*! + * @brief This function is used to set the watermark of UART Tx FIFO. + * A maskable interrupt is generated whenever the data level in + * the TxFIFO falls below the Tx FIFO watermark. + * + * @param base UART base pointer. + * @param watermark The Tx FIFO watermark. + */ +static inline void UART_SetTxFifoWatermark(UART_Type *base, uint8_t watermark) +{ + assert((watermark >= 2) && (watermark <= FSL_FEATURE_IUART_FIFO_SIZEn(base))); + base->UFCR = (base->UFCR & ~UART_UFCR_TXTL_MASK) | UART_UFCR_TXTL(watermark); +} + +/*! + * @brief This function is used to set the watermark of UART Rx FIFO. + * A maskable interrupt is generated whenever the data level in + * the RxFIFO reaches the Rx FIFO watermark. + * + * @param base UART base pointer. + * @param watermark The Rx FIFO watermark. + */ +static inline void UART_SetRxFifoWatermark(UART_Type *base, uint8_t watermark) +{ + assert(watermark <= FSL_FEATURE_IUART_FIFO_SIZEn(base)); + base->UFCR = (base->UFCR & ~UART_UFCR_RXTL_MASK) | UART_UFCR_RXTL(watermark); +} + +/*@}*/ + +/*! + * @name Auto baud rate detection. + * @{ + */ + +/*! + * @brief This function is used to set the enable condition of + * Automatic Baud Rate Detection feature. + * + * @param base UART base pointer. + * @param enable Enable/Disable Automatic Baud Rate Detection feature. + * - true: Enable Automatic Baud Rate Detection feature. + * - false: Disable Automatic Baud Rate Detection feature. + */ +static inline void UART_EnableAutoBaudRate(UART_Type *base, bool enable) +{ + if (enable) + { + /* When ADET=0 and ADBR=1, automatic baud rate detection starts */ + /* Enable automatic baud rate detection */ + base->UCR1 |= UART_UCR1_ADBR_MASK; + /* Clear ADET brfore start automatic baud rate detection*/ + base->USR2 |= UART_USR2_ADET_MASK; + } + else + { + /* Disable automatic baud rate detection */ + base->UCR1 &= ~UART_UCR1_ADBR_MASK; + } +} +/*! + * @brief This function is used to read if the automatic baud rate detection + * has finished. + * + * @param base UART base pointer. + * @return - true: Automatic baud rate detection has finished. + * - false: Automatic baud rate detection has not finished. + */ +static inline bool UART_IsAutoBaudRateComplete(UART_Type *base) +{ + if (UART_USR2_ACST_MASK & base->USR2) + { + base->USR2 |= UART_USR2_ACST_MASK; + return true; + } + else + { + return false; + } +} + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* _FSL_UART_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.c new file mode 100644 index 0000000000..35e37e7cb3 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.c @@ -0,0 +1,1654 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_usdhc.h" +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL +#include "fsl_cache.h" +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + +#ifdef RT_USING_USERSPACE +#include "imx6ull.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Clock setting */ +/* Max SD clock divisor from base clock */ +#define USDHC_MAX_DVS ((USDHC_SYS_CTRL_DVS_MASK >> USDHC_SYS_CTRL_DVS_SHIFT) + 1U) +#define USDHC_PREV_DVS(x) ((x) -= 1U) +#define USDHC_PREV_CLKFS(x, y) ((x) >>= (y)) + +/* Typedef for interrupt handler. */ +typedef void (*usdhc_isr_t)(USDHC_Type *base, usdhc_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance. + * + * @param base USDHC peripheral base address. + * @return Instance number. + */ +static uint32_t USDHC_GetInstance(USDHC_Type *base); + +/*! + * @brief Set transfer interrupt. + * + * @param base USDHC peripheral base address. + * @param usingInterruptSignal True to use IRQ signal. + */ +static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSignal); + +/*! + * @brief Start transfer according to current transfer state + * + * @param base USDHC peripheral base address. + * @param command Command to be sent. + * @param data Data to be transferred. + */ +static status_t USDHC_SetTransferConfig(USDHC_Type *base, usdhc_command_t *command, usdhc_data_t *data); + +/*! + * @brief Receive command response + * + * @param base USDHC peripheral base address. + * @param command Command to be sent. + */ +static status_t USDHC_ReceiveCommandResponse(USDHC_Type *base, usdhc_command_t *command); + +/*! + * @brief Read DATAPORT when buffer enable bit is set. + * + * @param base USDHC peripheral base address. + * @param data Data to be read. + * @param transferredWords The number of data words have been transferred last time transaction. + * @return The number of total data words have been transferred after this time transaction. + */ +static uint32_t USDHC_ReadDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords); + +/*! + * @brief Read data by using DATAPORT polling way. + * + * @param base USDHC peripheral base address. + * @param data Data to be read. + * @retval kStatus_Fail Read DATAPORT failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data); + +/*! + * @brief Write DATAPORT when buffer enable bit is set. + * + * @param base USDHC peripheral base address. + * @param data Data to be read. + * @param transferredWords The number of data words have been transferred last time. + * @return The number of total data words have been transferred after this time transaction. + */ +static uint32_t USDHC_WriteDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords); + +/*! + * @brief Write data by using DATAPORT polling way. + * + * @param base USDHC peripheral base address. + * @param data Data to be transferred. + * @retval kStatus_Fail Write DATAPORT failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data); + +/*! + * @brief Transfer data by polling way. + * + * @param base USDHC peripheral base address. + * @param data Data to be transferred. + * @param use DMA flag. + * @retval kStatus_Fail Transfer data failed. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_Success Operate successfully. + */ +static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, bool enDMA); + +/*! + * @brief Handle card detect interrupt. + * + * @param handle USDHC handle. + * @param interruptFlags Card detect related interrupt flags. + */ +static void USDHC_TransferHandleCardDetect(usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle command interrupt. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param interruptFlags Command related interrupt flags. + */ +static void USDHC_TransferHandleCommand(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle data interrupt. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param interruptFlags Data related interrupt flags. + */ +static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle SDIO card interrupt signal. + * + * @param handle USDHC handle. + */ +static void USDHC_TransferHandleSdioInterrupt(usdhc_handle_t *handle); + +/*! + * @brief Handle SDIO block gap event. + * + * @param handle USDHC handle. + */ +static void USDHC_TransferHandleSdioBlockGap(usdhc_handle_t *handle); + +/*! +* @brief Handle retuning +* +* @param interrupt flags +*/ +static void USDHC_TransferHandleReTuning(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! +* @brief wait command done +* +* @param base USDHC peripheral base address. +* @param command configuration +* @param execute tuning flag +*/ +static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command, bool executeTuning); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief USDHC base pointer array */ +static USDHC_Type *const s_usdhcBase[] = USDHC_BASE_PTRS; + +/*! @brief USDHC internal handle pointer array */ +static usdhc_handle_t *s_usdhcHandle[ARRAY_SIZE(s_usdhcBase)] = {NULL}; + +/*! @brief USDHC IRQ name array */ +static const IRQn_Type s_usdhcIRQ[] = USDHC_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief USDHC clock array name */ +static const clock_ip_name_t s_usdhcClock[] = USDHC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* USDHC ISR for transactional APIs. */ +static usdhc_isr_t s_usdhcIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t USDHC_GetInstance(USDHC_Type *base) +{ + uint8_t instance = 0; + +#ifdef RT_USING_USERSPACE + while ((instance < ARRAY_SIZE(s_usdhcBase)) && (s_usdhcBase[instance] != rt_hw_kernel_virt_to_phys(base))) +#else + while ((instance < ARRAY_SIZE(s_usdhcBase)) && (s_usdhcBase[instance] != base)) +#endif + { + instance++; + } + + assert(instance < ARRAY_SIZE(s_usdhcBase)); + + return instance; +} + +static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSignal) +{ + uint32_t interruptEnabled; /* The Interrupt status flags to be enabled */ + + /* Disable all interrupts */ + USDHC_DisableInterruptStatus(base, (uint32_t)kUSDHC_AllInterruptFlags); + USDHC_DisableInterruptSignal(base, (uint32_t)kUSDHC_AllInterruptFlags); + DisableIRQ(s_usdhcIRQ[USDHC_GetInstance(base)]); + + interruptEnabled = (kUSDHC_CommandFlag | kUSDHC_CardInsertionFlag | kUSDHC_DataFlag | kUSDHC_CardRemovalFlag | + kUSDHC_SDR104TuningFlag); + + USDHC_EnableInterruptStatus(base, interruptEnabled); + + if (usingInterruptSignal) + { + USDHC_EnableInterruptSignal(base, interruptEnabled); + } +} + +static status_t USDHC_SetTransferConfig(USDHC_Type *base, usdhc_command_t *command, usdhc_data_t *data) +{ + assert(NULL != command); + + if ((data != NULL) && (data->blockCount > USDHC_MAX_BLOCK_COUNT)) + { + return kStatus_InvalidArgument; + } + + /* Define the flag corresponding to each response type. */ + switch (command->responseType) + { + case kCARD_ResponseTypeNone: + break; + case kCARD_ResponseTypeR1: /* Response 1 */ + case kCARD_ResponseTypeR5: /* Response 5 */ + case kCARD_ResponseTypeR6: /* Response 6 */ + case kCARD_ResponseTypeR7: /* Response 7 */ + + command->flags |= (kUSDHC_ResponseLength48Flag | kUSDHC_EnableCrcCheckFlag | kUSDHC_EnableIndexCheckFlag); + break; + + case kCARD_ResponseTypeR1b: /* Response 1 with busy */ + case kCARD_ResponseTypeR5b: /* Response 5 with busy */ + command->flags |= + (kUSDHC_ResponseLength48BusyFlag | kUSDHC_EnableCrcCheckFlag | kUSDHC_EnableIndexCheckFlag); + break; + + case kCARD_ResponseTypeR2: /* Response 2 */ + command->flags |= (kUSDHC_ResponseLength136Flag | kUSDHC_EnableCrcCheckFlag); + break; + + case kCARD_ResponseTypeR3: /* Response 3 */ + case kCARD_ResponseTypeR4: /* Response 4 */ + command->flags |= (kUSDHC_ResponseLength48Flag); + break; + + default: + break; + } + + if (command->type == kCARD_CommandTypeAbort) + { + command->flags |= kUSDHC_CommandTypeAbortFlag; + } + + if (data) + { + command->flags |= kUSDHC_DataPresentFlag; + + if (data->rxData) + { + command->flags |= kUSDHC_DataReadFlag; + } + if (data->blockCount > 1U) + { + command->flags |= (kUSDHC_MultipleBlockFlag | kUSDHC_EnableBlockCountFlag); + /* auto command 12 */ + if (data->enableAutoCommand12) + { + /* Enable Auto command 12. */ + command->flags |= kUSDHC_EnableAutoCommand12Flag; + } + /* auto command 23 */ + if (data->enableAutoCommand23) + { + command->flags |= kUSDHC_EnableAutoCommand23Flag; + } + } + /* config data block size/block count */ + base->BLK_ATT = ((base->BLK_ATT & ~(USDHC_BLK_ATT_BLKSIZE_MASK | USDHC_BLK_ATT_BLKCNT_MASK)) | + (USDHC_BLK_ATT_BLKSIZE(data->blockSize) | USDHC_BLK_ATT_BLKCNT(data->blockCount))); + + /* auto command 23, auto send set block count cmd before multiple read/write */ + if (((command->flags & kUSDHC_EnableAutoCommand23Flag) != 0U)) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_AC23EN_MASK; + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK; + /* config the block count to DS_ADDR */ + base->DS_ADDR = data->blockCount; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_AC23EN_MASK; + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK; + } + } + + return kStatus_Success; +} + +static status_t USDHC_ReceiveCommandResponse(USDHC_Type *base, usdhc_command_t *command) +{ + uint32_t i; + + if (command->responseType != kCARD_ResponseTypeNone) + { + command->response[0U] = base->CMD_RSP0; + if (command->responseType == kCARD_ResponseTypeR2) + { + command->response[1U] = base->CMD_RSP1; + command->response[2U] = base->CMD_RSP2; + command->response[3U] = base->CMD_RSP3; + + i = 4U; + /* R3-R2-R1-R0(lowest 8 bit is invalid bit) has the same format as R2 format in SD specification document + after removed internal CRC7 and end bit. */ + do + { + command->response[i - 1U] <<= 8U; + if (i > 1U) + { + command->response[i - 1U] |= ((command->response[i - 2U] & 0xFF000000U) >> 24U); + } + } while (i--); + } + } + /* check response error flag */ + if ((command->responseErrorFlags != 0U) && + ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) || + (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5))) + { + if (((command->responseErrorFlags) & (command->response[0U])) != 0U) + { + return kStatus_USDHC_SendCommandFailed; + } + } + + return kStatus_Success; +} + +static uint32_t USDHC_ReadDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords) +{ + uint32_t i; + uint32_t totalWords; + uint32_t wordsCanBeRead; /* The words can be read at this time. */ + uint32_t readWatermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_RD_WML_MASK) >> USDHC_WTMK_LVL_RD_WML_SHIFT); + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ + if (readWatermark >= totalWords) + { + wordsCanBeRead = totalWords; + } + /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark, + transfers watermark level words. */ + else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark)) + { + wordsCanBeRead = readWatermark; + } + /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers left + words. */ + else + { + wordsCanBeRead = (totalWords - transferredWords); + } + + i = 0U; + while (i < wordsCanBeRead) + { + data->rxData[transferredWords++] = USDHC_ReadData(base); + i++; + } + + return transferredWords; +} + +static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data) +{ + uint32_t totalWords; + uint32_t transferredWords = 0U, interruptStatus = 0U; + status_t error = kStatus_Success; + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + while ((error == kStatus_Success) && (transferredWords < totalWords)) + { + while (!(USDHC_GetInterruptStatusFlags(base) & + (kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) + { + } + + interruptStatus = USDHC_GetInterruptStatusFlags(base); + /* during std tuning process, software do not need to read data, but wait BRR is enough */ + if ((data->executeTuning) && (interruptStatus & kUSDHC_BufferReadReadyFlag)) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferReadReadyFlag | kUSDHC_TuningPassFlag); + return kStatus_Success; + } + else if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_TuningErrorFlag); + /* if tuning error occur ,return directly */ + error = kStatus_USDHC_TuningError; + } + else if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + /* clear data error flag */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataErrorFlag); + } + else + { + } + + if (error == kStatus_Success) + { + transferredWords = USDHC_ReadDataPort(base, data, transferredWords); + /* clear buffer read ready */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferReadReadyFlag); + } + } + + /* Clear data complete flag after the last read operation. */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataCompleteFlag); + + return error; +} + +static uint32_t USDHC_WriteDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords) +{ + uint32_t i; + uint32_t totalWords; + uint32_t wordsCanBeWrote; /* Words can be wrote at this time. */ + uint32_t writeWatermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_WR_WML_MASK) >> USDHC_WTMK_LVL_WR_WML_SHIFT); + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + /* If watermark level is equal or bigger than totalWords, transfers totalWords data.*/ + if (writeWatermark >= totalWords) + { + wordsCanBeWrote = totalWords; + } + /* If watermark level is less than totalWords and left words to be sent is equal or bigger than watermark, + transfers watermark level words. */ + else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark)) + { + wordsCanBeWrote = writeWatermark; + } + /* If watermark level is less than totalWords and left words to be sent is less than watermark, transfers left + words. */ + else + { + wordsCanBeWrote = (totalWords - transferredWords); + } + + i = 0U; + while (i < wordsCanBeWrote) + { + USDHC_WriteData(base, data->txData[transferredWords++]); + i++; + } + + return transferredWords; +} + +static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data) +{ + uint32_t totalWords; + + uint32_t transferredWords = 0U, interruptStatus = 0U; + status_t error = kStatus_Success; + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = (data->blockCount * data->blockSize) / sizeof(uint32_t); + + while ((error == kStatus_Success) && (transferredWords < totalWords)) + { + while (!(USDHC_GetInterruptStatusFlags(base) & + (kUSDHC_BufferWriteReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) + { + } + + interruptStatus = USDHC_GetInterruptStatusFlags(base); + + if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_TuningErrorFlag); + /* if tuning error occur ,return directly */ + return kStatus_USDHC_TuningError; + } + else if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + /* clear data error flag */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataErrorFlag); + } + else + { + } + + if (error == kStatus_Success) + { + transferredWords = USDHC_WriteDataPort(base, data, transferredWords); + /* clear buffer write ready */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferWriteReadyFlag); + } + } + + /* Wait write data complete or data transfer error after the last writing operation. */ + while (!(USDHC_GetInterruptStatusFlags(base) & (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag))) + { + } + + if ((USDHC_GetInterruptStatusFlags(base) & kUSDHC_DataErrorFlag) != 0U) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + } + USDHC_ClearInterruptStatusFlags(base, (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag)); + + return error; +} + +void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command) +{ + assert(NULL != command); + + uint32_t mixCtrl, xferType; + + mixCtrl = base->MIX_CTRL; + xferType = base->CMD_XFR_TYP; + + /* config mix parameter */ + mixCtrl &= ~(USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK | + USDHC_MIX_CTRL_AC12EN_MASK); + mixCtrl |= ((command->flags) & (USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK | + USDHC_MIX_CTRL_AC12EN_MASK)); + + /* config cmd index */ + xferType &= ~(USDHC_CMD_XFR_TYP_CMDINX_MASK | USDHC_CMD_XFR_TYP_DPSEL_MASK | USDHC_CMD_XFR_TYP_CMDTYP_MASK | + USDHC_CMD_XFR_TYP_CICEN_MASK | USDHC_CMD_XFR_TYP_CCCEN_MASK | USDHC_CMD_XFR_TYP_RSPTYP_MASK); + + xferType = (((command->index << USDHC_CMD_XFR_TYP_CMDINX_SHIFT) & USDHC_CMD_XFR_TYP_CMDINX_MASK) | + ((command->flags) & + (USDHC_CMD_XFR_TYP_DPSEL_MASK | USDHC_CMD_XFR_TYP_CMDTYP_MASK | USDHC_CMD_XFR_TYP_CICEN_MASK | + USDHC_CMD_XFR_TYP_CCCEN_MASK | USDHC_CMD_XFR_TYP_RSPTYP_MASK))); + /* config the mix parameter */ + base->MIX_CTRL = mixCtrl; + /* config the command xfertype and argument */ + base->CMD_ARG = command->argument; + base->CMD_XFR_TYP = xferType; +} + +static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command, bool executeTuning) +{ + assert(NULL != command); + + status_t error = kStatus_Success; + uint32_t interruptStatus = 0U; + /* tuning cmd do not need to wait command done */ + if (!executeTuning) + { + /* Wait command complete or USDHC encounters error. */ + while (!(USDHC_GetInterruptStatusFlags(base) & (kUSDHC_CommandCompleteFlag | kUSDHC_CommandErrorFlag))) + { + } + + interruptStatus = USDHC_GetInterruptStatusFlags(base); + + if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + error = kStatus_USDHC_TuningError; + } + else if ((interruptStatus & kUSDHC_CommandErrorFlag) != 0U) + { + error = kStatus_Fail; + } + else + { + } + /* Receive response when command completes successfully. */ + if (error == kStatus_Success) + { + error = USDHC_ReceiveCommandResponse(base, command); + } + + USDHC_ClearInterruptStatusFlags( + base, (kUSDHC_CommandCompleteFlag | kUSDHC_CommandErrorFlag | kUSDHC_TuningErrorFlag)); + } + + return error; +} + +static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, bool enDMA) +{ + status_t error = kStatus_Success; + uint32_t interruptStatus = 0U; + + if (enDMA) + { + /* Wait data complete or USDHC encounters error. */ + while (!(USDHC_GetInterruptStatusFlags(base) & + (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | kUSDHC_TuningErrorFlag))) + { + } + + interruptStatus = USDHC_GetInterruptStatusFlags(base); + + if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + error = kStatus_USDHC_TuningError; + } + else if ((interruptStatus & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag)) != 0U) + { + if (!(data->enableIgnoreError) || (interruptStatus & kUSDHC_DataTimeoutFlag)) + { + error = kStatus_Fail; + } + } + else + { + } + + USDHC_ClearInterruptStatusFlags(base, (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | + kUSDHC_TuningPassFlag | kUSDHC_TuningErrorFlag)); + } + else + { + if (data->rxData) + { + error = USDHC_ReadByDataPortBlocking(base, data); + } + else + { + error = USDHC_WriteByDataPortBlocking(base, data); + } + } + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* invalidate cache for read */ + if ((data != NULL) && (data->rxData != NULL)) + { + /* invalidate the DCACHE */ + DCACHE_InvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); + } +#endif + + return error; +} + +void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config) +{ + assert(config); + assert((config->writeWatermarkLevel >= 1U) && (config->writeWatermarkLevel <= 128U)); + assert((config->readWatermarkLevel >= 1U) && (config->readWatermarkLevel <= 128U)); + assert(config->writeBurstLen <= 16U); + + uint32_t proctl, sysctl, wml; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable USDHC clock. */ + CLOCK_EnableClock(s_usdhcClock[USDHC_GetInstance(base)]); +#endif + + /* Reset USDHC. */ + USDHC_Reset(base, kUSDHC_ResetAll, 100U); + + proctl = base->PROT_CTRL; + wml = base->WTMK_LVL; + sysctl = base->SYS_CTRL; + + proctl &= ~(USDHC_PROT_CTRL_EMODE_MASK | USDHC_PROT_CTRL_DMASEL_MASK); + /* Endian mode*/ + proctl |= USDHC_PROT_CTRL_EMODE(config->endianMode); + + /* Watermark level */ + wml &= ~(USDHC_WTMK_LVL_RD_WML_MASK | USDHC_WTMK_LVL_WR_WML_MASK | USDHC_WTMK_LVL_RD_BRST_LEN_MASK | + USDHC_WTMK_LVL_WR_BRST_LEN_MASK); + wml |= (USDHC_WTMK_LVL_RD_WML(config->readWatermarkLevel) | USDHC_WTMK_LVL_WR_WML(config->writeWatermarkLevel) | + USDHC_WTMK_LVL_RD_BRST_LEN(config->readBurstLen) | USDHC_WTMK_LVL_WR_BRST_LEN(config->writeBurstLen)); + + /* config the data timeout value */ + sysctl &= ~USDHC_SYS_CTRL_DTOCV_MASK; + sysctl |= USDHC_SYS_CTRL_DTOCV(config->dataTimeout); + + base->SYS_CTRL = sysctl; + base->WTMK_LVL = wml; + base->PROT_CTRL = proctl; + +#if FSL_FEATURE_USDHC_HAS_EXT_DMA + /* disable external DMA */ + base->VEND_SPEC &= ~USDHC_VEND_SPEC_EXT_DMA_EN_MASK; +#endif + /* disable internal DMA */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; + + /* Enable interrupt status but doesn't enable interrupt signal. */ + USDHC_SetTransferInterrupt(base, false); +} + +void USDHC_Deinit(USDHC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable clock. */ + CLOCK_DisableClock(s_usdhcClock[USDHC_GetInstance(base)]); +#endif +} + +bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout) +{ + base->SYS_CTRL |= (mask & (USDHC_SYS_CTRL_RSTA_MASK | USDHC_SYS_CTRL_RSTC_MASK | USDHC_SYS_CTRL_RSTD_MASK)); + /* Delay some time to wait reset success. */ + while ((base->SYS_CTRL & mask) != 0U) + { + if (timeout == 0U) + { + break; + } + timeout--; + } + + return ((!timeout) ? false : true); +} + +void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability) +{ + assert(capability); + + uint32_t htCapability; + uint32_t maxBlockLength; + + htCapability = base->HOST_CTRL_CAP; + + /* Get the capability of USDHC. */ + maxBlockLength = ((htCapability & USDHC_HOST_CTRL_CAP_MBL_MASK) >> USDHC_HOST_CTRL_CAP_MBL_SHIFT); + capability->maxBlockLength = (512U << maxBlockLength); + /* Other attributes not in HTCAPBLT register. */ + capability->maxBlockCount = USDHC_MAX_BLOCK_COUNT; + capability->flags = (htCapability & (kUSDHC_SupportAdmaFlag | kUSDHC_SupportHighSpeedFlag | kUSDHC_SupportDmaFlag | + kUSDHC_SupportSuspendResumeFlag | kUSDHC_SupportV330Flag)); + capability->flags |= (htCapability & kUSDHC_SupportV300Flag); + capability->flags |= (htCapability & kUSDHC_SupportV180Flag); + capability->flags |= + (htCapability & (kUSDHC_SupportDDR50Flag | kUSDHC_SupportSDR104Flag | kUSDHC_SupportSDR50Flag)); + /* USDHC support 4/8 bit data bus width. */ + capability->flags |= (kUSDHC_Support4BitFlag | kUSDHC_Support8BitFlag); +} + +uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz) +{ + assert(srcClock_Hz != 0U); + assert((busClock_Hz != 0U) && (busClock_Hz <= srcClock_Hz)); + + uint32_t totalDiv = 0U; + uint32_t divisor = 0U; + uint32_t prescaler = 0U; + uint32_t sysctl = 0U; + uint32_t nearestFrequency = 0U; + uint32_t maxClKFS = ((USDHC_SYS_CTRL_SDCLKFS_MASK >> USDHC_SYS_CTRL_SDCLKFS_SHIFT) + 1U); + bool enDDR = false; + /* DDR mode max clkfs can reach 512 */ + if ((base->MIX_CTRL & USDHC_MIX_CTRL_DDR_EN_MASK) != 0U) + { + enDDR = true; + maxClKFS *= 2U; + } + /* calucate total divisor first */ + totalDiv = srcClock_Hz / busClock_Hz; + + if (totalDiv != 0U) + { + /* calucate the divisor (srcClock_Hz / divisor) <= busClock_Hz */ + if ((srcClock_Hz / totalDiv) > busClock_Hz) + { + totalDiv++; + } + + /* divide the total divisor to div and prescaler */ + if (totalDiv > USDHC_MAX_DVS) + { + prescaler = totalDiv / USDHC_MAX_DVS; + /* prescaler must be a value which equal 2^n and smaller than SDHC_MAX_CLKFS */ + while (((maxClKFS % prescaler) != 0U) || (prescaler == 1U)) + { + prescaler++; + } + /* calucate the divisor */ + divisor = totalDiv / prescaler; + /* fine tuning the divisor until divisor * prescaler >= totalDiv */ + while ((divisor * prescaler) < totalDiv) + { + divisor++; + } + nearestFrequency = srcClock_Hz / divisor / prescaler; + } + else + { + /* in this situation , divsior and SDCLKFS can generate same clock + use SDCLKFS*/ + if ((USDHC_MAX_DVS % totalDiv) == 0U) + { + divisor = 0U; + prescaler = totalDiv; + } + else + { + divisor = totalDiv; + prescaler = 0U; + } + nearestFrequency = srcClock_Hz / totalDiv; + } + } + /* in this condition , srcClock_Hz = busClock_Hz, */ + else + { + /* in DDR mode , set SDCLKFS to 0, divisor = 0, actually the + totoal divider = 2U */ + divisor = 0U; + prescaler = 0U; + nearestFrequency = srcClock_Hz; + } + + /* calucate the value write to register */ + if (divisor != 0U) + { + USDHC_PREV_DVS(divisor); + } + /* calucate the value write to register */ + if (prescaler != 0U) + { + USDHC_PREV_CLKFS(prescaler, (enDDR ? 2U : 1U)); + } + + /* Set the SD clock frequency divisor, SD clock frequency select, data timeout counter value. */ + sysctl = base->SYS_CTRL; + sysctl &= ~(USDHC_SYS_CTRL_DVS_MASK | USDHC_SYS_CTRL_SDCLKFS_MASK); + sysctl |= (USDHC_SYS_CTRL_DVS(divisor) | USDHC_SYS_CTRL_SDCLKFS(prescaler)); + base->SYS_CTRL = sysctl; + + /* Wait until the SD clock is stable. */ + while (!(base->PRES_STATE & USDHC_PRES_STATE_SDSTB_MASK)) + { + } + + return nearestFrequency; +} + +bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout) +{ + base->SYS_CTRL |= USDHC_SYS_CTRL_INITA_MASK; + /* Delay some time to wait card become active state. */ + while ((base->SYS_CTRL & USDHC_SYS_CTRL_INITA_MASK) == USDHC_SYS_CTRL_INITA_MASK) + { + if (!timeout) + { + break; + } + timeout--; + } + + return ((!timeout) ? false : true); +} + +void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config) +{ + assert(config); + assert(config->ackTimeoutCount <= (USDHC_MMC_BOOT_DTOCV_ACK_MASK >> USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)); + assert(config->blockCount <= (USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK >> USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)); + + uint32_t mmcboot = 0U; + + mmcboot = (USDHC_MMC_BOOT_DTOCV_ACK(config->ackTimeoutCount) | USDHC_MMC_BOOT_BOOT_MODE(config->bootMode) | + USDHC_MMC_BOOT_BOOT_BLK_CNT(config->blockCount)); + + if (config->enableBootAck) + { + mmcboot |= USDHC_MMC_BOOT_BOOT_ACK_MASK; + } + if (config->enableBoot) + { + mmcboot |= USDHC_MMC_BOOT_BOOT_EN_MASK; + } + if (config->enableAutoStopAtBlockGap) + { + mmcboot |= USDHC_MMC_BOOT_AUTO_SABG_EN_MASK; + } + + base->MMC_BOOT = mmcboot; +} + +status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, + usdhc_adma_config_t *dmaConfig, + usdhc_data_t *dataConfig, + uint32_t flags) +{ + assert(NULL != dmaConfig); + assert(NULL != dmaConfig->admaTable); + assert(NULL != dataConfig); + + const uint32_t *startAddress; + uint32_t entries; + uint32_t i, dmaBufferLen = 0U; + usdhc_adma1_descriptor_t *adma1EntryAddress; + usdhc_adma2_descriptor_t *adma2EntryAddress; + uint32_t dataBytes = dataConfig->blockSize * dataConfig->blockCount; + const uint32_t *data = (dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData; + + /* check DMA data buffer address align or not */ + if (((dmaConfig->dmaMode == kUSDHC_DmaModeAdma1) && (((uint32_t)data % USDHC_ADMA1_ADDRESS_ALIGN) != 0U)) || + ((dmaConfig->dmaMode == kUSDHC_DmaModeAdma2) && (((uint32_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0U)) || + ((dmaConfig->dmaMode == kUSDHC_DmaModeSimple) && (((uint32_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0U))) + { + return kStatus_USDHC_DMADataAddrNotAlign; + } + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (dataBytes % sizeof(uint32_t) != 0U) + { + /* make the data length as word-aligned */ + dataBytes += sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); + } + + startAddress = data; + + switch (dmaConfig->dmaMode) + { +#if FSL_FEATURE_USDHC_HAS_EXT_DMA + case kUSDHC_ExternalDMA: + /* enable the external DMA */ + base->VEND_SPEC |= USDHC_VEND_SPEC_EXT_DMA_EN_MASK; + break; +#endif + case kUSDHC_DmaModeSimple: + /* in simple DMA mode if use auto CMD23, address should load to ADMA addr, + and block count should load to DS_ADDR*/ + if ((flags & kUSDHC_EnableAutoCommand23Flag) != 0U) + { + base->ADMA_SYS_ADDR = (uint32_t)data; + } + else + { + base->DS_ADDR = (uint32_t)data; + } + + break; + + case kUSDHC_DmaModeAdma1: + + /* Check if ADMA descriptor's number is enough. */ + if ((dataBytes % USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) + { + entries = dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + } + else + { + entries = ((dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); + } + + /* ADMA1 needs two descriptors to finish a transfer */ + entries <<= 1U; + + if (entries > ((dmaConfig->admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma1_descriptor_t))) + { + return kStatus_OutOfRange; + } + + adma1EntryAddress = (usdhc_adma1_descriptor_t *)(dmaConfig->admaTable); + for (i = 0U; i < entries; i += 2U) + { + if (dataBytes > USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + { + dmaBufferLen = USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + dataBytes -= dmaBufferLen; + } + else + { + dmaBufferLen = dataBytes; + } + + adma1EntryAddress[i] = (dmaBufferLen << USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT); + adma1EntryAddress[i] |= kUSDHC_Adma1DescriptorTypeSetLength; + adma1EntryAddress[i + 1U] = ((uint32_t)(startAddress) << USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT); + adma1EntryAddress[i + 1U] |= kUSDHC_Adma1DescriptorTypeTransfer; + startAddress += dmaBufferLen / sizeof(uint32_t); + } + /* the end of the descriptor */ + adma1EntryAddress[i - 1U] |= kUSDHC_Adma1DescriptorEndFlag; + /* When use ADMA, disable simple DMA */ + base->DS_ADDR = 0U; + base->ADMA_SYS_ADDR = (uint32_t)(dmaConfig->admaTable); + break; + + case kUSDHC_DmaModeAdma2: + /* Check if ADMA descriptor's number is enough. */ + if ((dataBytes % USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) + { + entries = dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + } + else + { + entries = ((dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); + } + + if (entries > ((dmaConfig->admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma2_descriptor_t))) + { + return kStatus_OutOfRange; + } + + adma2EntryAddress = (usdhc_adma2_descriptor_t *)(dmaConfig->admaTable); + for (i = 0U; i < entries; i++) + { + if (dataBytes > USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + { + dmaBufferLen = USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + dataBytes -= dmaBufferLen; + } + else + { + dmaBufferLen = dataBytes; + } + + /* Each descriptor for ADMA2 is 64-bit in length */ + adma2EntryAddress[i].address = startAddress; + adma2EntryAddress[i].attribute = (dmaBufferLen << USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT); + adma2EntryAddress[i].attribute |= kUSDHC_Adma2DescriptorTypeTransfer; + startAddress += (dmaBufferLen / sizeof(uint32_t)); + } + /* set the end bit */ + adma2EntryAddress[i - 1U].attribute |= kUSDHC_Adma2DescriptorEndFlag; + /* When use ADMA, disable simple DMA */ + base->DS_ADDR = 0U; + base->ADMA_SYS_ADDR = (uint32_t)(dmaConfig->admaTable); + + break; + default: + return kStatus_USDHC_PrepareAdmaDescriptorFailed; + } + + /* for external dma */ + if (dmaConfig->dmaMode != kUSDHC_ExternalDMA) + { +#if FSL_FEATURE_USDHC_HAS_EXT_DMA + /* disable the external DMA if support */ + base->VEND_SPEC &= ~USDHC_VEND_SPEC_EXT_DMA_EN_MASK; +#endif + /* select DMA mode and config the burst length */ + base->PROT_CTRL &= ~(USDHC_PROT_CTRL_DMASEL_MASK | USDHC_PROT_CTRL_BURST_LEN_EN_MASK); + base->PROT_CTRL |= + USDHC_PROT_CTRL_DMASEL(dmaConfig->dmaMode) | USDHC_PROT_CTRL_BURST_LEN_EN(dmaConfig->burstLen); + /* enable DMA */ + base->MIX_CTRL |= USDHC_MIX_CTRL_DMAEN_MASK; + } + + /* disable the interrupt signal for interrupt mode */ + USDHC_DisableInterruptSignal(base, kUSDHC_BufferReadReadyFlag | kUSDHC_BufferWriteReadyFlag); + + return kStatus_Success; +} + +status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer) +{ + assert(transfer); + + status_t error = kStatus_Success; + usdhc_command_t *command = transfer->command; + usdhc_data_t *data = transfer->data; + bool enDMA = false; + + /* Wait until command/data bus out of busy status. */ + while (USDHC_GetPresentStatusFlags(base) & kUSDHC_CommandInhibitFlag) + { + } + while (data && (USDHC_GetPresentStatusFlags(base) & kUSDHC_DataInhibitFlag)) + { + } + /*check re-tuning request*/ + if ((USDHC_GetInterruptStatusFlags(base) & kUSDHC_ReTuningEventFlag) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_ReTuningEventFlag); + return kStatus_USDHC_ReTuningRequest; + } + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + if ((data != NULL) && (!(data->executeTuning))) + { + if (data->txData != NULL) + { + /* clear the DCACHE */ + DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); + } + else + { + /* clear the DCACHE */ + DCACHE_CleanByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); + } + } +#endif + + /* config the transfer parameter */ + if (kStatus_Success != USDHC_SetTransferConfig(base, command, data)) + { + return kStatus_InvalidArgument; + } + + /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ + if ((data != NULL) && (dmaConfig != NULL) && (!data->executeTuning)) + { +#if 0 //not use adma. there are some error not solved! + error = USDHC_SetAdmaTableConfig(base, dmaConfig, data, command->flags); + /* if the target data buffer address is not align , we change the transfer mode + * to polling automatically, other DMA config error will not cover by driver, user + * should handle it + */ + if ((error != kStatus_USDHC_DMADataAddrNotAlign) && (error != kStatus_Success)) + { + return kStatus_USDHC_PrepareAdmaDescriptorFailed; + } + else if (error == kStatus_USDHC_DMADataAddrNotAlign) + { + enDMA = false; + /* disable DMA, using polling mode in this situation */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; + } + else + { + enDMA = true; + } +#else + enDMA = false; + /* disable DMA, using polling mode in this situation */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; +#endif + } + else + { + /* disable DMA */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; + } + /* send command */ + USDHC_SendCommand(base, command); + /* wait command done */ + error = USDHC_WaitCommandDone(base, command, ((data == NULL) ? false : data->executeTuning)); + /* transfer data */ + if ((data != NULL) && (error == kStatus_Success)) + { + return USDHC_TransferDataBlocking(base, data, enDMA); + } + + return error; +} + +status_t USDHC_TransferNonBlocking(USDHC_Type *base, + usdhc_handle_t *handle, + usdhc_adma_config_t *dmaConfig, + usdhc_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + status_t error = kStatus_Success; + usdhc_command_t *command = transfer->command; + usdhc_data_t *data = transfer->data; + + /* Wait until command/data bus out of busy status. */ + if ((USDHC_GetPresentStatusFlags(base) & kUSDHC_CommandInhibitFlag) || + (data && (USDHC_GetPresentStatusFlags(base) & kUSDHC_DataInhibitFlag))) + { + return kStatus_USDHC_BusyTransferring; + } + + /*check re-tuning request*/ + if ((USDHC_GetInterruptStatusFlags(base) & (kUSDHC_ReTuningEventFlag)) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_ReTuningEventFlag); + return kStatus_USDHC_ReTuningRequest; + } + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + if ((data != NULL) && (!(data->executeTuning))) + { + if (data->txData != NULL) + { + /* clear the DCACHE */ + DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); + } + else + { + /* clear the DCACHE */ + DCACHE_CleanByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); + } + } +#endif + + /* Save command and data into handle before transferring. */ + handle->command = command; + handle->data = data; + handle->interruptFlags = 0U; + /* transferredWords will only be updated in ISR when transfer way is DATAPORT. */ + handle->transferredWords = 0U; + + if (kStatus_Success != USDHC_SetTransferConfig(base, command, data)) + { + return kStatus_InvalidArgument; + } + + /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ + if ((data != NULL) && (dmaConfig != NULL) && (!data->executeTuning)) + { + error = USDHC_SetAdmaTableConfig(base, dmaConfig, data, command->flags); + /* if the target data buffer address is not align , we change the transfer mode + * to polling automatically, other DMA config error will not cover by driver, user + * should handle it + */ + if ((error != kStatus_USDHC_DMADataAddrNotAlign) && (error != kStatus_Success)) + { + return kStatus_USDHC_PrepareAdmaDescriptorFailed; + } + else if (error == kStatus_USDHC_DMADataAddrNotAlign) + { + /* disable DMA, using polling mode in this situation */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; + /* enable the interrupt signal for interrupt mode */ + USDHC_EnableInterruptSignal(base, kUSDHC_BufferReadReadyFlag | kUSDHC_BufferWriteReadyFlag); + } + else + { + } + } + else + { + /* disable DMA */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; + } + + /* enable the buffer read ready for std tuning */ + if ((data != NULL) && (data->executeTuning)) + { + USDHC_EnableInterruptSignal(base, kUSDHC_BufferReadReadyFlag); + } + + /* send command */ + USDHC_SendCommand(base, command); + + return kStatus_Success; +} + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) +#else +void USDHC_EnableManualTuning(USDHC_Type *base, bool enable) +{ + if (enable) + { + /* make sure std_tun_en bit is clear */ + base->TUNING_CTRL &= ~USDHC_TUNING_CTRL_STD_TUNING_EN_MASK; + /* disable auto tuning here */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; + /* execute tuning for SDR104 mode */ + base->MIX_CTRL |= + USDHC_MIX_CTRL_EXE_TUNE_MASK | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK | USDHC_MIX_CTRL_FBCLK_SEL_MASK; + } + else + { /* abort the tuning */ + base->MIX_CTRL &= ~(USDHC_MIX_CTRL_EXE_TUNE_MASK | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK); + } +} + +status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay) +{ + uint32_t clkTuneCtrl = 0U; + + clkTuneCtrl = base->CLK_TUNE_CTRL_STATUS; + + clkTuneCtrl &= ~USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK; + + clkTuneCtrl |= USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(delay); + + /* load the delay setting */ + base->CLK_TUNE_CTRL_STATUS = clkTuneCtrl; + /* check delat setting error */ + if (base->CLK_TUNE_CTRL_STATUS & + (USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)) + { + return kStatus_Fail; + } + + return kStatus_Success; +} + +void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable) +{ + uint32_t tuningCtrl = 0U; + + if (enable) + { + /* feedback clock */ + base->MIX_CTRL |= USDHC_MIX_CTRL_FBCLK_SEL_MASK; + /* config tuning start and step */ + tuningCtrl = base->TUNING_CTRL; + tuningCtrl &= ~(USDHC_TUNING_CTRL_TUNING_START_TAP_MASK | USDHC_TUNING_CTRL_TUNING_STEP_MASK); + tuningCtrl |= (USDHC_TUNING_CTRL_TUNING_START_TAP(tuningStartTap) | USDHC_TUNING_CTRL_TUNING_STEP(step) | + USDHC_TUNING_CTRL_STD_TUNING_EN_MASK); + base->TUNING_CTRL = tuningCtrl; + + /* excute tuning */ + base->AUTOCMD12_ERR_STATUS |= + (USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); + } + else + { + /* disable the standard tuning */ + base->TUNING_CTRL &= ~USDHC_TUNING_CTRL_STD_TUNING_EN_MASK; + /* clear excute tuning */ + base->AUTOCMD12_ERR_STATUS &= + ~(USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); + } +} + +void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base) +{ + uint32_t busWidth = 0U; + + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK; + busWidth = (base->PROT_CTRL & USDHC_PROT_CTRL_DTW_MASK) >> USDHC_PROT_CTRL_DTW_SHIFT; + if (busWidth == kUSDHC_DataBusWidth1Bit) + { + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; + } + else if (busWidth == kUSDHC_DataBusWidth4Bit) + { + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; + } + else if (busWidth == kUSDHC_DataBusWidth8Bit) + { + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; + } + else + { + } +} +#endif + +static void USDHC_TransferHandleCardDetect(usdhc_handle_t *handle, uint32_t interruptFlags) +{ + if (interruptFlags & kUSDHC_CardInsertionFlag) + { + if (handle->callback.CardInserted) + { + handle->callback.CardInserted(); + } + } + else + { + if (handle->callback.CardRemoved) + { + handle->callback.CardRemoved(); + } + } +} + +static void USDHC_TransferHandleCommand(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->command); + + if ((interruptFlags & kUSDHC_CommandErrorFlag) && (!(handle->data)) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_USDHC_SendCommandFailed, handle->userData); + } + else + { + /* Receive response */ + if (kStatus_Success != USDHC_ReceiveCommandResponse(base, handle->command)) + { + handle->callback.TransferComplete(base, handle, kStatus_USDHC_SendCommandFailed, handle->userData); + } + else if ((!(handle->data)) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + else + { + } + } +} + +static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->data); + + if ((!(handle->data->enableIgnoreError) || (interruptFlags & kUSDHC_DataTimeoutFlag)) && + (interruptFlags & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag)) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_USDHC_TransferDataFailed, handle->userData); + } + else + { + if (interruptFlags & kUSDHC_BufferReadReadyFlag) + { + /* std tuning process only need to wait BRR */ + if (handle->data->executeTuning) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + else + { + handle->transferredWords = USDHC_ReadDataPort(base, handle->data, handle->transferredWords); + } + } + else if (interruptFlags & kUSDHC_BufferWriteReadyFlag) + { + handle->transferredWords = USDHC_WriteDataPort(base, handle->data, handle->transferredWords); + } + else if ((interruptFlags & kUSDHC_DataCompleteFlag) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + else + { + /* Do nothing when DMA complete flag is set. Wait until data complete flag is set. */ + } +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* invalidate cache for read */ + if ((handle->data != NULL) && (handle->data->rxData != NULL)) + { + /* invalidate the DCACHE */ + DCACHE_InvalidateByRange((uint32_t)handle->data->rxData, + (handle->data->blockSize) * (handle->data->blockCount)); + } +#endif + } +} + +static void USDHC_TransferHandleSdioInterrupt(usdhc_handle_t *handle) +{ + if (handle->callback.SdioInterrupt) + { + handle->callback.SdioInterrupt(); + } +} + +static void USDHC_TransferHandleReTuning(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->callback.ReTuning); + /* retuning request */ + if ((interruptFlags & kUSDHC_TuningErrorFlag) == kUSDHC_TuningErrorFlag) + { + handle->callback.ReTuning(); /* retuning fail */ + } +} + +static void USDHC_TransferHandleSdioBlockGap(usdhc_handle_t *handle) +{ + if (handle->callback.SdioBlockGap) + { + handle->callback.SdioBlockGap(); + } +} + +void USDHC_TransferCreateHandle(USDHC_Type *base, + usdhc_handle_t *handle, + const usdhc_transfer_callback_t *callback, + void *userData) +{ + assert(handle); + assert(callback); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the callback. */ + handle->callback.CardInserted = callback->CardInserted; + handle->callback.CardRemoved = callback->CardRemoved; + handle->callback.SdioInterrupt = callback->SdioInterrupt; + handle->callback.SdioBlockGap = callback->SdioBlockGap; + handle->callback.TransferComplete = callback->TransferComplete; + handle->callback.ReTuning = callback->ReTuning; + handle->userData = userData; + + /* Save the handle in global variables to support the double weak mechanism. */ + s_usdhcHandle[USDHC_GetInstance(base)] = handle; + + /* Enable interrupt in NVIC. */ + USDHC_SetTransferInterrupt(base, true); + /* disable the tuning pass interrupt */ + USDHC_DisableInterruptSignal(base, kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag); + /* save IRQ handler */ + s_usdhcIsr = USDHC_TransferHandleIRQ; + + EnableIRQ(s_usdhcIRQ[USDHC_GetInstance(base)]); +} + +void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle) +{ + assert(handle); + + uint32_t interruptFlags; + + interruptFlags = USDHC_GetInterruptStatusFlags(base); + handle->interruptFlags = interruptFlags; + + if (interruptFlags & kUSDHC_CardDetectFlag) + { + USDHC_TransferHandleCardDetect(handle, (interruptFlags & kUSDHC_CardDetectFlag)); + } + if (interruptFlags & kUSDHC_CommandFlag) + { + USDHC_TransferHandleCommand(base, handle, (interruptFlags & kUSDHC_CommandFlag)); + } + if (interruptFlags & kUSDHC_DataFlag) + { + USDHC_TransferHandleData(base, handle, (interruptFlags & kUSDHC_DataFlag)); + } + if (interruptFlags & kUSDHC_CardInterruptFlag) + { + USDHC_TransferHandleSdioInterrupt(handle); + } + if (interruptFlags & kUSDHC_BlockGapEventFlag) + { + USDHC_TransferHandleSdioBlockGap(handle); + } + if (interruptFlags & kUSDHC_SDR104TuningFlag) + { + USDHC_TransferHandleReTuning(base, handle, (interruptFlags & kUSDHC_SDR104TuningFlag)); + } + + USDHC_ClearInterruptStatusFlags(base, interruptFlags); +} + +#ifdef USDHC0 +void USDHC0_DriverIRQHandler(void) +{ + s_usdhcIsr(s_usdhcBase[0U], s_usdhcHandle[0U]); +} +#endif + +#ifdef USDHC1 +void USDHC1_DriverIRQHandler(void) +{ + s_usdhcIsr(s_usdhcBase[1U], s_usdhcHandle[1U]); +} +#endif + +#ifdef USDHC2 +void USDHC2_DriverIRQHandler(void) +{ + s_usdhcIsr(s_usdhcBase[2U], s_usdhcHandle[2U]); +} + +#endif diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.h new file mode 100644 index 0000000000..bde8df88ba --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_usdhc.h @@ -0,0 +1,1380 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_USDHC_H_ +#define _FSL_USDHC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup usdhc + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.1.1. */ +#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 1U)) +/*@}*/ + +/*! @brief Maximum block count can be set one time */ +#define USDHC_MAX_BLOCK_COUNT (USDHC_BLK_ATT_BLKCNT_MASK >> USDHC_BLK_ATT_BLKCNT_SHIFT) + +/*! @brief USDHC status */ +enum _usdhc_status +{ + kStatus_USDHC_BusyTransferring = MAKE_STATUS(kStatusGroup_USDHC, 0U), /*!< Transfer is on-going */ + kStatus_USDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_USDHC, 1U), /*!< Set DMA descriptor failed */ + kStatus_USDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_USDHC, 2U), /*!< Send command failed */ + kStatus_USDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_USDHC, 3U), /*!< Transfer data failed */ + kStatus_USDHC_DMADataAddrNotAlign = MAKE_STATUS(kStatusGroup_USDHC, 4U), /*!< data address not align */ + kStatus_USDHC_ReTuningRequest = MAKE_STATUS(kStatusGroup_USDHC, 5U), /*!< re-tuning request */ + kStatus_USDHC_TuningError = MAKE_STATUS(kStatusGroup_USDHC, 6U), /*!< tuning error */ + +}; + +/*! @brief Host controller capabilities flag mask */ +enum _usdhc_capability_flag +{ + kUSDHC_SupportAdmaFlag = USDHC_HOST_CTRL_CAP_ADMAS_MASK, /*!< Support ADMA */ + kUSDHC_SupportHighSpeedFlag = USDHC_HOST_CTRL_CAP_HSS_MASK, /*!< Support high-speed */ + kUSDHC_SupportDmaFlag = USDHC_HOST_CTRL_CAP_DMAS_MASK, /*!< Support DMA */ + kUSDHC_SupportSuspendResumeFlag = USDHC_HOST_CTRL_CAP_SRS_MASK, /*!< Support suspend/resume */ + kUSDHC_SupportV330Flag = USDHC_HOST_CTRL_CAP_VS33_MASK, /*!< Support voltage 3.3V */ + kUSDHC_SupportV300Flag = USDHC_HOST_CTRL_CAP_VS30_MASK, /*!< Support voltage 3.0V */ + kUSDHC_SupportV180Flag = USDHC_HOST_CTRL_CAP_VS18_MASK, /*!< Support voltage 1.8V */ + /* Put additional two flags in HTCAPBLT_MBL's position. */ + kUSDHC_Support4BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 0U), /*!< Support 4 bit mode */ + kUSDHC_Support8BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 1U), /*!< Support 8 bit mode */ + /* sd version 3.0 new feature */ + kUSDHC_SupportDDR50Flag = USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK, /*!< support DDR50 mode */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR104_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR104_MODE) + kUSDHC_SupportSDR104Flag = 0, /*!< not support SDR104 mode */ +#else + kUSDHC_SupportSDR104Flag = USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK, /*!< support SDR104 mode */ +#endif +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_SupportSDR50Flag = 0U, /*!< not support SDR50 mode */ +#else + kUSDHC_SupportSDR50Flag = USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK, /*!< support SDR50 mode */ +#endif +}; + +/*! @brief Wakeup event mask */ +enum _usdhc_wakeup_event +{ + kUSDHC_WakeupEventOnCardInt = USDHC_PROT_CTRL_WECINT_MASK, /*!< Wakeup on card interrupt */ + kUSDHC_WakeupEventOnCardInsert = USDHC_PROT_CTRL_WECINS_MASK, /*!< Wakeup on card insertion */ + kUSDHC_WakeupEventOnCardRemove = USDHC_PROT_CTRL_WECRM_MASK, /*!< Wakeup on card removal */ + + kUSDHC_WakeupEventsAll = (kUSDHC_WakeupEventOnCardInt | kUSDHC_WakeupEventOnCardInsert | + kUSDHC_WakeupEventOnCardRemove), /*!< All wakeup events */ +}; + +/*! @brief Reset type mask */ +enum _usdhc_reset +{ + kUSDHC_ResetAll = USDHC_SYS_CTRL_RSTA_MASK, /*!< Reset all except card detection */ + kUSDHC_ResetCommand = USDHC_SYS_CTRL_RSTC_MASK, /*!< Reset command line */ + kUSDHC_ResetData = USDHC_SYS_CTRL_RSTD_MASK, /*!< Reset data line */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ResetTuning = 0U, /*!< no reset tuning circuit bit */ +#else + kUSDHC_ResetTuning = USDHC_SYS_CTRL_RSTT_MASK, /*!< reset tuning circuit */ +#endif + + kUSDHC_ResetsAll = + (kUSDHC_ResetAll | kUSDHC_ResetCommand | kUSDHC_ResetData | kUSDHC_ResetTuning), /*!< All reset types */ +}; + +/*! @brief Transfer flag mask */ +enum _usdhc_transfer_flag +{ + kUSDHC_EnableDmaFlag = USDHC_MIX_CTRL_DMAEN_MASK, /*!< Enable DMA */ + + kUSDHC_CommandTypeSuspendFlag = (USDHC_CMD_XFR_TYP_CMDTYP(1U)), /*!< Suspend command */ + kUSDHC_CommandTypeResumeFlag = (USDHC_CMD_XFR_TYP_CMDTYP(2U)), /*!< Resume command */ + kUSDHC_CommandTypeAbortFlag = (USDHC_CMD_XFR_TYP_CMDTYP(3U)), /*!< Abort command */ + + kUSDHC_EnableBlockCountFlag = USDHC_MIX_CTRL_BCEN_MASK, /*!< Enable block count */ + kUSDHC_EnableAutoCommand12Flag = USDHC_MIX_CTRL_AC12EN_MASK, /*!< Enable auto CMD12 */ + kUSDHC_DataReadFlag = USDHC_MIX_CTRL_DTDSEL_MASK, /*!< Enable data read */ + kUSDHC_MultipleBlockFlag = USDHC_MIX_CTRL_MSBSEL_MASK, /*!< Multiple block data read/write */ + kUSDHC_EnableAutoCommand23Flag = USDHC_MIX_CTRL_AC23EN_MASK, /*!< Enable auto CMD23 */ + + kUSDHC_ResponseLength136Flag = USDHC_CMD_XFR_TYP_RSPTYP(1U), /*!< 136 bit response length */ + kUSDHC_ResponseLength48Flag = USDHC_CMD_XFR_TYP_RSPTYP(2U), /*!< 48 bit response length */ + kUSDHC_ResponseLength48BusyFlag = USDHC_CMD_XFR_TYP_RSPTYP(3U), /*!< 48 bit response length with busy status */ + + kUSDHC_EnableCrcCheckFlag = USDHC_CMD_XFR_TYP_CCCEN_MASK, /*!< Enable CRC check */ + kUSDHC_EnableIndexCheckFlag = USDHC_CMD_XFR_TYP_CICEN_MASK, /*!< Enable index check */ + kUSDHC_DataPresentFlag = USDHC_CMD_XFR_TYP_DPSEL_MASK, /*!< Data present flag */ +}; + +/*! @brief Present status flag mask */ +enum _usdhc_present_status_flag +{ + kUSDHC_CommandInhibitFlag = USDHC_PRES_STATE_CIHB_MASK, /*!< Command inhibit */ + kUSDHC_DataInhibitFlag = USDHC_PRES_STATE_CDIHB_MASK, /*!< Data inhibit */ + kUSDHC_DataLineActiveFlag = USDHC_PRES_STATE_DLA_MASK, /*!< Data line active */ + kUSDHC_SdClockStableFlag = USDHC_PRES_STATE_SDSTB_MASK, /*!< SD bus clock stable */ + kUSDHC_WriteTransferActiveFlag = USDHC_PRES_STATE_WTA_MASK, /*!< Write transfer active */ + kUSDHC_ReadTransferActiveFlag = USDHC_PRES_STATE_RTA_MASK, /*!< Read transfer active */ + kUSDHC_BufferWriteEnableFlag = USDHC_PRES_STATE_BWEN_MASK, /*!< Buffer write enable */ + kUSDHC_BufferReadEnableFlag = USDHC_PRES_STATE_BREN_MASK, /*!< Buffer read enable */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_DelaySettingFinishedFlag = 0U, /*!< not support */ + kUSDHC_ReTuningRequestFlag = 0U, /*!< not support */ +#else + kUSDHC_ReTuningRequestFlag = USDHC_PRES_STATE_RTR_MASK, /*!< re-tuning request flag ,only used for SDR104 mode */ + kUSDHC_DelaySettingFinishedFlag = USDHC_PRES_STATE_TSCD_MASK, /*!< delay setting finished flag */ +#endif + + kUSDHC_CardInsertedFlag = USDHC_PRES_STATE_CINST_MASK, /*!< Card inserted */ + kUSDHC_CommandLineLevelFlag = USDHC_PRES_STATE_CLSL_MASK, /*!< Command line signal level */ + + kUSDHC_Data0LineLevelFlag = (1U << USDHC_PRES_STATE_DLSL_SHIFT), /*!< Data0 line signal level */ + kUSDHC_Data1LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 1U)), /*!< Data1 line signal level */ + kUSDHC_Data2LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 2U)), /*!< Data2 line signal level */ + kUSDHC_Data3LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 3U)), /*!< Data3 line signal level */ + kUSDHC_Data4LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 4U)), /*!< Data4 line signal level */ + kUSDHC_Data5LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 5U)), /*!< Data5 line signal level */ + kUSDHC_Data6LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 6U)), /*!< Data6 line signal level */ + kUSDHC_Data7LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 7U)), /*!< Data7 line signal level */ +}; + +/*! @brief Interrupt status flag mask */ +enum _usdhc_interrupt_status_flag +{ + kUSDHC_CommandCompleteFlag = USDHC_INT_STATUS_CC_MASK, /*!< Command complete */ + kUSDHC_DataCompleteFlag = USDHC_INT_STATUS_TC_MASK, /*!< Data complete */ + kUSDHC_BlockGapEventFlag = USDHC_INT_STATUS_BGE_MASK, /*!< Block gap event */ + kUSDHC_DmaCompleteFlag = USDHC_INT_STATUS_DINT_MASK, /*!< DMA interrupt */ + kUSDHC_BufferWriteReadyFlag = USDHC_INT_STATUS_BWR_MASK, /*!< Buffer write ready */ + kUSDHC_BufferReadReadyFlag = USDHC_INT_STATUS_BRR_MASK, /*!< Buffer read ready */ + kUSDHC_CardInsertionFlag = USDHC_INT_STATUS_CINS_MASK, /*!< Card inserted */ + kUSDHC_CardRemovalFlag = USDHC_INT_STATUS_CRM_MASK, /*!< Card removed */ + kUSDHC_CardInterruptFlag = USDHC_INT_STATUS_CINT_MASK, /*!< Card interrupt */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ReTuningEventFlag = 0U, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */ + kUSDHC_TuningPassFlag = 0U, /*!< SDR104 mode tuning pass flag */ + kUSDHC_TuningErrorFlag = 0U, /*!< SDR104 tuning error flag */ +#else + kUSDHC_ReTuningEventFlag = USDHC_INT_STATUS_RTE_MASK, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */ + kUSDHC_TuningPassFlag = USDHC_INT_STATUS_TP_MASK, /*!< SDR104 mode tuning pass flag */ + kUSDHC_TuningErrorFlag = USDHC_INT_STATUS_TNE_MASK, /*!< SDR104 tuning error flag */ +#endif + + kUSDHC_CommandTimeoutFlag = USDHC_INT_STATUS_CTOE_MASK, /*!< Command timeout error */ + kUSDHC_CommandCrcErrorFlag = USDHC_INT_STATUS_CCE_MASK, /*!< Command CRC error */ + kUSDHC_CommandEndBitErrorFlag = USDHC_INT_STATUS_CEBE_MASK, /*!< Command end bit error */ + kUSDHC_CommandIndexErrorFlag = USDHC_INT_STATUS_CIE_MASK, /*!< Command index error */ + kUSDHC_DataTimeoutFlag = USDHC_INT_STATUS_DTOE_MASK, /*!< Data timeout error */ + kUSDHC_DataCrcErrorFlag = USDHC_INT_STATUS_DCE_MASK, /*!< Data CRC error */ + kUSDHC_DataEndBitErrorFlag = USDHC_INT_STATUS_DEBE_MASK, /*!< Data end bit error */ + kUSDHC_AutoCommand12ErrorFlag = USDHC_INT_STATUS_AC12E_MASK, /*!< Auto CMD12 error */ + kUSDHC_DmaErrorFlag = USDHC_INT_STATUS_DMAE_MASK, /*!< DMA error */ + + kUSDHC_CommandErrorFlag = (kUSDHC_CommandTimeoutFlag | kUSDHC_CommandCrcErrorFlag | kUSDHC_CommandEndBitErrorFlag | + kUSDHC_CommandIndexErrorFlag), /*!< Command error */ + kUSDHC_DataErrorFlag = (kUSDHC_DataTimeoutFlag | kUSDHC_DataCrcErrorFlag | kUSDHC_DataEndBitErrorFlag | + kUSDHC_AutoCommand12ErrorFlag), /*!< Data error */ + kUSDHC_ErrorFlag = (kUSDHC_CommandErrorFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< All error */ + kUSDHC_DataFlag = (kUSDHC_DataCompleteFlag | kUSDHC_DmaCompleteFlag | kUSDHC_BufferWriteReadyFlag | + kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< Data interrupts */ + kUSDHC_CommandFlag = (kUSDHC_CommandErrorFlag | kUSDHC_CommandCompleteFlag), /*!< Command interrupts */ + kUSDHC_CardDetectFlag = (kUSDHC_CardInsertionFlag | kUSDHC_CardRemovalFlag), /*!< Card detection interrupts */ + kUSDHC_SDR104TuningFlag = (kUSDHC_TuningErrorFlag | kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag), + + kUSDHC_AllInterruptFlags = (kUSDHC_BlockGapEventFlag | kUSDHC_CardInterruptFlag | kUSDHC_CommandFlag | + kUSDHC_DataFlag | kUSDHC_ErrorFlag | kUSDHC_SDR104TuningFlag), /*!< All flags mask */ +}; + +/*! @brief Auto CMD12 error status flag mask */ +enum _usdhc_auto_command12_error_status_flag +{ + kUSDHC_AutoCommand12NotExecutedFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK, /*!< Not executed error */ + kUSDHC_AutoCommand12TimeoutFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK, /*!< Timeout error */ + kUSDHC_AutoCommand12EndBitErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK, /*!< End bit error */ + kUSDHC_AutoCommand12CrcErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK, /*!< CRC error */ + kUSDHC_AutoCommand12IndexErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK, /*!< Index error */ + kUSDHC_AutoCommand12NotIssuedFlag = USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK, /*!< Not issued error */ +}; + +/*! @brief standard tuning flag */ +enum _usdhc_standard_tuning +{ +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ExecuteTuning = 0U, /*!< not support */ + kUSDHC_TuningSampleClockSel = 0U, /*!< not support */ +#else + kUSDHC_ExecuteTuning = USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK, /*!< used to start tuning procedure */ + kUSDHC_TuningSampleClockSel = + USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK, /*!< when std_tuning_en bit is set, this bit is used + select sampleing clock */ +#endif +}; + +/*! @brief ADMA error status flag mask */ +enum _usdhc_adma_error_status_flag +{ + kUSDHC_AdmaLenghMismatchFlag = USDHC_ADMA_ERR_STATUS_ADMALME_MASK, /*!< Length mismatch error */ + kUSDHC_AdmaDescriptorErrorFlag = USDHC_ADMA_ERR_STATUS_ADMADCE_MASK, /*!< Descriptor error */ +}; + +/*! + * @brief ADMA error state + * + * This state is the detail state when ADMA error has occurred. + */ +typedef enum _usdhc_adma_error_state +{ + kUSDHC_AdmaErrorStateStopDma = 0x00U, /*!< Stop DMA */ + kUSDHC_AdmaErrorStateFetchDescriptor = 0x01U, /*!< Fetch descriptor */ + kUSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address */ + kUSDHC_AdmaErrorStateTransferData = 0x03U, /*!< Transfer data */ +} usdhc_adma_error_state_t; + +/*! @brief Force event mask */ +enum _usdhc_force_event +{ + kUSDHC_ForceEventAutoCommand12NotExecuted = USDHC_FORCE_EVENT_FEVTAC12NE_MASK, /*!< Auto CMD12 not executed error */ + kUSDHC_ForceEventAutoCommand12Timeout = USDHC_FORCE_EVENT_FEVTAC12TOE_MASK, /*!< Auto CMD12 timeout error */ + kUSDHC_ForceEventAutoCommand12CrcError = USDHC_FORCE_EVENT_FEVTAC12CE_MASK, /*!< Auto CMD12 CRC error */ + kUSDHC_ForceEventEndBitError = USDHC_FORCE_EVENT_FEVTAC12EBE_MASK, /*!< Auto CMD12 end bit error */ + kUSDHC_ForceEventAutoCommand12IndexError = USDHC_FORCE_EVENT_FEVTAC12IE_MASK, /*!< Auto CMD12 index error */ + kUSDHC_ForceEventAutoCommand12NotIssued = USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK, /*!< Auto CMD12 not issued error */ + kUSDHC_ForceEventCommandTimeout = USDHC_FORCE_EVENT_FEVTCTOE_MASK, /*!< Command timeout error */ + kUSDHC_ForceEventCommandCrcError = USDHC_FORCE_EVENT_FEVTCCE_MASK, /*!< Command CRC error */ + kUSDHC_ForceEventCommandEndBitError = USDHC_FORCE_EVENT_FEVTCEBE_MASK, /*!< Command end bit error */ + kUSDHC_ForceEventCommandIndexError = USDHC_FORCE_EVENT_FEVTCIE_MASK, /*!< Command index error */ + kUSDHC_ForceEventDataTimeout = USDHC_FORCE_EVENT_FEVTDTOE_MASK, /*!< Data timeout error */ + kUSDHC_ForceEventDataCrcError = USDHC_FORCE_EVENT_FEVTDCE_MASK, /*!< Data CRC error */ + kUSDHC_ForceEventDataEndBitError = USDHC_FORCE_EVENT_FEVTDEBE_MASK, /*!< Data end bit error */ + kUSDHC_ForceEventAutoCommand12Error = USDHC_FORCE_EVENT_FEVTAC12E_MASK, /*!< Auto CMD12 error */ + kUSDHC_ForceEventCardInt = USDHC_FORCE_EVENT_FEVTCINT_MASK, /*!< Card interrupt */ + kUSDHC_ForceEventDmaError = USDHC_FORCE_EVENT_FEVTDMAE_MASK, /*!< Dma error */ +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ForceEventTuningError = 0U, /*!< not support */ +#else + kUSDHC_ForceEventTuningError = USDHC_FORCE_EVENT_FEVTTNE_MASK, /*!< Tuning error */ +#endif + kUSDHC_ForceEventsAll = + (kUSDHC_ForceEventAutoCommand12NotExecuted | kUSDHC_ForceEventAutoCommand12Timeout | + kUSDHC_ForceEventAutoCommand12CrcError | kUSDHC_ForceEventEndBitError | + kUSDHC_ForceEventAutoCommand12IndexError | kUSDHC_ForceEventAutoCommand12NotIssued | + kUSDHC_ForceEventCommandTimeout | kUSDHC_ForceEventCommandCrcError | kUSDHC_ForceEventCommandEndBitError | + kUSDHC_ForceEventCommandIndexError | kUSDHC_ForceEventDataTimeout | kUSDHC_ForceEventDataCrcError | + kUSDHC_ForceEventDataEndBitError | kUSDHC_ForceEventAutoCommand12Error | kUSDHC_ForceEventCardInt | + kUSDHC_ForceEventDmaError | kUSDHC_ForceEventTuningError), /*!< All force event flags mask */ +}; + +/*! @brief Data transfer width */ +typedef enum _usdhc_data_bus_width +{ + kUSDHC_DataBusWidth1Bit = 0U, /*!< 1-bit mode */ + kUSDHC_DataBusWidth4Bit = 1U, /*!< 4-bit mode */ + kUSDHC_DataBusWidth8Bit = 2U, /*!< 8-bit mode */ +} usdhc_data_bus_width_t; + +/*! @brief Endian mode */ +typedef enum _usdhc_endian_mode +{ + kUSDHC_EndianModeBig = 0U, /*!< Big endian mode */ + kUSDHC_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ + kUSDHC_EndianModeLittle = 2U, /*!< Little endian mode */ +} usdhc_endian_mode_t; + +/*! @brief DMA mode */ +typedef enum _usdhc_dma_mode +{ + kUSDHC_DmaModeSimple = 0U, /*!< external DMA */ + kUSDHC_DmaModeAdma1 = 1U, /*!< ADMA1 is selected */ + kUSDHC_DmaModeAdma2 = 2U, /*!< ADMA2 is selected */ + kUSDHC_ExternalDMA = 3U, /*!< external dma mode select */ +} usdhc_dma_mode_t; + +/*! @brief SDIO control flag mask */ +enum _usdhc_sdio_control_flag +{ + kUSDHC_StopAtBlockGapFlag = USDHC_PROT_CTRL_SABGREQ_MASK, /*!< Stop at block gap */ + kUSDHC_ReadWaitControlFlag = USDHC_PROT_CTRL_RWCTL_MASK, /*!< Read wait control */ + kUSDHC_InterruptAtBlockGapFlag = USDHC_PROT_CTRL_IABG_MASK, /*!< Interrupt at block gap */ + kUSDHC_ReadDoneNo8CLK = USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK, /*!< read done without 8 clk for block gap */ + kUSDHC_ExactBlockNumberReadFlag = USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK, /*!< Exact block number read */ +}; + +/*! @brief MMC card boot mode */ +typedef enum _usdhc_boot_mode +{ + kUSDHC_BootModeNormal = 0U, /*!< Normal boot */ + kUSDHC_BootModeAlternative = 1U, /*!< Alternative boot */ +} usdhc_boot_mode_t; + +/*! @brief The command type */ +typedef enum _usdhc_card_command_type +{ + kCARD_CommandTypeNormal = 0U, /*!< Normal command */ + kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */ + kCARD_CommandTypeResume = 2U, /*!< Resume command */ + kCARD_CommandTypeAbort = 3U, /*!< Abort command */ +} usdhc_card_command_type_t; + +/*! + * @brief The command response type. + * + * Define the command response type from card to host controller. + */ +typedef enum _usdhc_card_response_type +{ + kCARD_ResponseTypeNone = 0U, /*!< Response type: none */ + kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */ + kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */ + kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */ + kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */ + kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */ + kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */ + kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */ + kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */ + kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */ +} usdhc_card_response_type_t; + +/*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */ +#define USDHC_ADMA1_ADDRESS_ALIGN (4096U) +/*! @brief The alignment size for LENGTH field in ADMA1's descriptor */ +#define USDHC_ADMA1_LENGTH_ALIGN (4096U) +/*! @brief The alignment size for ADDRESS field in ADMA2's descriptor */ +#define USDHC_ADMA2_ADDRESS_ALIGN (4U) +/*! @brief The alignment size for LENGTH filed in ADMA2's descriptor */ +#define USDHC_ADMA2_LENGTH_ALIGN (4U) + +/* ADMA1 descriptor table + * |------------------------|---------|--------------------------| + * | Address/page field |Reserved | Attribute | + * |------------------------|---------|--------------------------| + * |31 12|11 6|05 |04 |03|02 |01 |00 | + * |------------------------|---------|----|----|--|---|---|-----| + * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid| + * |------------------------|---------|----|----|--|---|---|-----| + * + * + * |------|------|-----------------|-------|-------------| + * | Act2 | Act1 | Comment | 31-28 | 27 - 12 | + * |------|------|-----------------|---------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------|-------------| + * | 0 | 1 | Set data length | 0000 | Data Length | + * |------|------|-----------------|-------|-------------| + * | 1 | 0 | Transfer data | Data address | + * |------|------|-----------------|---------------------| + * | 1 | 1 | Link descriptor | Descriptor address | + * |------|------|-----------------|---------------------| + */ +/*! @brief The bit shift for ADDRESS filed in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT (12U) +/*! @brief The bit mask for ADDRESS field in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU) +/*! @brief The bit shift for LENGTH filed in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U) +/*! @brief The mask for LENGTH field in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The maximum value of LENGTH filed in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK - 3U) + +/*! @brief The mask for the control/status field in ADMA1 descriptor */ +enum _usdhc_adma1_descriptor_flag +{ + kUSDHC_Adma1DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ + kUSDHC_Adma1DescriptorEndFlag = (1U << 1U), /*!< End flag */ + kUSDHC_Adma1DescriptorInterrupFlag = (1U << 2U), /*!< Interrupt flag */ + kUSDHC_Adma1DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 flag */ + kUSDHC_Adma1DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 flag */ + kUSDHC_Adma1DescriptorTypeNop = (kUSDHC_Adma1DescriptorValidFlag), /*!< No operation */ + kUSDHC_Adma1DescriptorTypeTransfer = + (kUSDHC_Adma1DescriptorActivity2Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Transfer data */ + kUSDHC_Adma1DescriptorTypeLink = (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorActivity2Flag | + kUSDHC_Adma1DescriptorValidFlag), /*!< Link descriptor */ + kUSDHC_Adma1DescriptorTypeSetLength = + (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Set data length */ +}; + +/* ADMA2 descriptor table + * |----------------|---------------|-------------|--------------------------| + * | Address field | Length | Reserved | Attribute | + * |----------------|---------------|-------------|--------------------------| + * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 | + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid| + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * + * + * | Act2 | Act1 | Comment | Operation | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 1 | Reserved | Read this line and go to next one | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 1 | Link descriptor | Link to another descriptor | + * |------|------|-----------------|-------------------------------------------------------------------| + */ +/*! @brief The bit shift for LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U) +/*! @brief The bit mask for LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The maximum value of LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK - 3U) + +/*! @brief ADMA1 descriptor control and status mask */ +enum _usdhc_adma2_descriptor_flag +{ + kUSDHC_Adma2DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ + kUSDHC_Adma2DescriptorEndFlag = (1U << 1U), /*!< End flag */ + kUSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), /*!< Interrupt flag */ + kUSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 mask */ + kUSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 mask */ + + kUSDHC_Adma2DescriptorTypeNop = (kUSDHC_Adma2DescriptorValidFlag), /*!< No operation */ + kUSDHC_Adma2DescriptorTypeReserved = + (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Reserved */ + kUSDHC_Adma2DescriptorTypeTransfer = + (kUSDHC_Adma2DescriptorActivity2Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Transfer type */ + kUSDHC_Adma2DescriptorTypeLink = (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorActivity2Flag | + kUSDHC_Adma2DescriptorValidFlag), /*!< Link type */ +}; + +/*! @brief dma transfer burst len config. */ +typedef enum _usdhc_burst_len +{ + kUSDHC_EnBurstLenForINCR = 0x01U, /*!< enable burst len for INCR */ + kUSDHC_EnBurstLenForINCR4816 = 0x02U, /*!< enable burst len for INCR4/INCR8/INCR16 */ + kUSDHC_EnBurstLenForINCR4816WRAP = 0x04U, /*!< enable burst len for INCR4/8/16 WRAP */ +} usdhc_burst_len_t; + +/*! @brief Defines the adma1 descriptor structure. */ +typedef uint32_t usdhc_adma1_descriptor_t; + +/*! @brief Defines the ADMA2 descriptor structure. */ +typedef struct _usdhc_adma2_descriptor +{ + uint32_t attribute; /*!< The control and status field */ + const uint32_t *address; /*!< The address field */ +} usdhc_adma2_descriptor_t; + +/*! + * @brief USDHC capability information. + * + * Defines a structure to save the capability information of USDHC. + */ +typedef struct _usdhc_capability +{ + uint32_t sdVersion; /*!< support SD card/sdio version */ + uint32_t mmcVersion; /*!< support emmc card version */ + uint32_t maxBlockLength; /*!< Maximum block length united as byte */ + uint32_t maxBlockCount; /*!< Maximum block count can be set one time */ + uint32_t flags; /*!< Capability flags to indicate the support information(_usdhc_capability_flag) */ +} usdhc_capability_t; + +/*! @brief Data structure to configure the MMC boot feature */ +typedef struct _usdhc_boot_config +{ + uint32_t ackTimeoutCount; /*!< Timeout value for the boot ACK. The available range is 0 ~ 15. */ + usdhc_boot_mode_t bootMode; /*!< Boot mode selection. */ + uint32_t blockCount; /*!< Stop at block gap value of automatic mode. Available range is 0 ~ 65535. */ + bool enableBootAck; /*!< Enable or disable boot ACK */ + bool enableBoot; /*!< Enable or disable fast boot */ + bool enableAutoStopAtBlockGap; /*!< Enable or disable auto stop at block gap function in boot period */ +} usdhc_boot_config_t; + +/*! @brief Data structure to initialize the USDHC */ +typedef struct _usdhc_config +{ + uint32_t dataTimeout; /*!< Data timeout value */ + usdhc_endian_mode_t endianMode; /*!< Endian mode */ + uint8_t readWatermarkLevel; /*!< Watermark level for DMA read operation. Available range is 1 ~ 128. */ + uint8_t writeWatermarkLevel; /*!< Watermark level for DMA write operation. Available range is 1 ~ 128. */ + uint8_t readBurstLen; /*!< Read burst len */ + uint8_t writeBurstLen; /*!< Write burst len */ +} usdhc_config_t; + +/*! + * @brief Card data descriptor + * + * Defines a structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card + * driver + * want to ignore the error event to read/write all the data not to stop read/write immediately when error event + * happen for example bus testing procedure for MMC card. + */ +typedef struct _usdhc_data +{ + bool enableAutoCommand12; /*!< Enable auto CMD12 */ + bool enableAutoCommand23; /*!< Enable auto CMD23 */ + bool enableIgnoreError; /*!< Enable to ignore error event to read/write all the data */ + bool executeTuning; /*!< execute tuning flag */ + + size_t blockSize; /*!< Block size */ + uint32_t blockCount; /*!< Block count */ + uint32_t *rxData; /*!< Buffer to save data read */ + const uint32_t *txData; /*!< Data buffer to write */ +} usdhc_data_t; + +/*! + * @brief Card command descriptor + * + * Define card command-related attribute. + */ +typedef struct _usdhc_command +{ + uint32_t index; /*!< Command index */ + uint32_t argument; /*!< Command argument */ + usdhc_card_command_type_t type; /*!< Command type */ + usdhc_card_response_type_t responseType; /*!< Command response type */ + uint32_t response[4U]; /*!< Response for this command */ + uint32_t responseErrorFlags; /*!< response error flag, the flag which need to check + the command reponse*/ + uint32_t flags; /*!< Cmd flags */ +} usdhc_command_t; + +/*! @brief ADMA configuration */ +typedef struct _usdhc_adma_config +{ + usdhc_dma_mode_t dmaMode; /*!< DMA mode */ + + usdhc_burst_len_t burstLen; /*!< burst len config */ + + uint32_t *admaTable; /*!< ADMA table address, can't be null if transfer way is ADMA1/ADMA2 */ + uint32_t admaTableWords; /*!< ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2 */ +} usdhc_adma_config_t; + +/*! @brief Transfer state */ +typedef struct _usdhc_transfer +{ + usdhc_data_t *data; /*!< Data to transfer */ + usdhc_command_t *command; /*!< Command to send */ +} usdhc_transfer_t; + +/*! @brief USDHC handle typedef */ +typedef struct _usdhc_handle usdhc_handle_t; + +/*! @brief USDHC callback functions. */ +typedef struct _usdhc_transfer_callback +{ + void (*CardInserted)(void); /*!< Card inserted occurs when DAT3/CD pin is for card detect */ + void (*CardRemoved)(void); /*!< Card removed occurs */ + void (*SdioInterrupt)(void); /*!< SDIO card interrupt occurs */ + void (*SdioBlockGap)(void); /*!< SDIO card stopped at block gap occurs */ + void (*TransferComplete)(USDHC_Type *base, + usdhc_handle_t *handle, + status_t status, + void *userData); /*!< Transfer complete callback */ + void (*ReTuning)(void); /*!< handle the re-tuning */ +} usdhc_transfer_callback_t; + +/*! + * @brief USDHC handle + * + * Defines the structure to save the USDHC state information and callback function. The detailed interrupt status when + * sending a command or transfering data can be obtained from the interruptFlags field by using the mask defined in + * usdhc_interrupt_flag_t. + * + * @note All the fields except interruptFlags and transferredWords must be allocated by the user. + */ +struct _usdhc_handle +{ + /* Transfer parameter */ + usdhc_data_t *volatile data; /*!< Data to transfer */ + usdhc_command_t *volatile command; /*!< Command to send */ + + /* Transfer status */ + volatile uint32_t interruptFlags; /*!< Interrupt flags of last transaction */ + volatile uint32_t transferredWords; /*!< Words transferred by DATAPORT way */ + + /* Callback functions */ + usdhc_transfer_callback_t callback; /*!< Callback function */ + void *userData; /*!< Parameter for transfer complete callback */ +}; + +/*! @brief USDHC transfer function. */ +typedef status_t (*usdhc_transfer_function_t)(USDHC_Type *base, usdhc_transfer_t *content); + +/*! @brief USDHC host descriptor */ +typedef struct _usdhc_host +{ + USDHC_Type *base; /*!< USDHC peripheral base address */ + uint32_t sourceClock_Hz; /*!< USDHC source clock frequency united in Hz */ + usdhc_config_t config; /*!< USDHC configuration */ + usdhc_capability_t capability; /*!< USDHC capability information */ + usdhc_transfer_function_t transfer; /*!< USDHC transfer function */ +} usdhc_host_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief USDHC module initialization function. + * + * Configures the USDHC according to the user configuration. + * + * Example: + @code + usdhc_config_t config; + config.cardDetectDat3 = false; + config.endianMode = kUSDHC_EndianModeLittle; + config.dmaMode = kUSDHC_DmaModeAdma2; + config.readWatermarkLevel = 128U; + config.writeWatermarkLevel = 128U; + USDHC_Init(USDHC, &config); + @endcode + * + * @param base USDHC peripheral base address. + * @param config USDHC configuration information. + * @retval kStatus_Success Operate successfully. + */ +void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config); + +/*! + * @brief Deinitializes the USDHC. + * + * @param base USDHC peripheral base address. + */ +void USDHC_Deinit(USDHC_Type *base); + +/*! + * @brief Resets the USDHC. + * + * @param base USDHC peripheral base address. + * @param mask The reset type mask(_usdhc_reset). + * @param timeout Timeout for reset. + * @retval true Reset successfully. + * @retval false Reset failed. + */ +bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout); + +/* @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Sets the ADMA descriptor table configuration. + * + * @param base USDHC peripheral base address. + * @param adma configuration + * @param data Data descriptor + * @param command flags + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, + usdhc_adma_config_t *dmaConfig, + usdhc_data_t *dataConfig, + uint32_t flags); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt status. + * + * @param base USDHC peripheral base address. + * @param mask Interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_EnableInterruptStatus(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS_EN |= mask; +} + +/*! + * @brief Disables the interrupt status. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_DisableInterruptStatus(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS_EN &= ~mask; +} + +/*! + * @brief Enables the interrupt signal corresponding to the interrupt status flag. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_EnableInterruptSignal(USDHC_Type *base, uint32_t mask) +{ + base->INT_SIGNAL_EN |= mask; +} + +/*! + * @brief Disables the interrupt signal corresponding to the interrupt status flag. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_DisableInterruptSignal(USDHC_Type *base, uint32_t mask) +{ + base->INT_SIGNAL_EN &= ~mask; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the current interrupt status. + * + * @param base USDHC peripheral base address. + * @return Current interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline uint32_t USDHC_GetInterruptStatusFlags(USDHC_Type *base) +{ + return base->INT_STATUS; +} + +/*! + * @brief Clears a specified interrupt status. + * write 1 clears + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_ClearInterruptStatusFlags(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS = mask; +} + +/*! + * @brief Gets the status of auto command 12 error. + * + * @param base USDHC peripheral base address. + * @return Auto command 12 error status flags mask(_usdhc_auto_command12_error_status_flag). + */ +static inline uint32_t USDHC_GetAutoCommand12ErrorStatusFlags(USDHC_Type *base) +{ + return base->AUTOCMD12_ERR_STATUS; +} + +/*! + * @brief Gets the status of the ADMA error. + * + * @param base USDHC peripheral base address. + * @return ADMA error status flags mask(_usdhc_adma_error_status_flag). + */ +static inline uint32_t USDHC_GetAdmaErrorStatusFlags(USDHC_Type *base) +{ + return base->ADMA_ERR_STATUS; +} + +/*! + * @brief Gets a present status. + * + * This function gets the present USDHC's status except for an interrupt status and an error status. + * + * @param base USDHC peripheral base address. + * @return Present USDHC's status flags mask(_usdhc_present_status_flag). + */ +static inline uint32_t USDHC_GetPresentStatusFlags(USDHC_Type *base) +{ + return base->PRES_STATE; +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Gets the capability information. + * + * @param base USDHC peripheral base address. + * @param capability Structure to save capability information. + */ +void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability); + +/*! + * @brief force the card clock on. + * + * @param base USDHC peripheral base address. + * @param enable/disable flag. + */ +static inline void USDHC_ForceClockOn(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->VEND_SPEC |= USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK; + } + else + { + base->VEND_SPEC &= ~USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK; + } +} + +/*! + * @brief Sets the SD bus clock frequency. + * + * @param base USDHC peripheral base address. + * @param srcClock_Hz USDHC source clock frequency united in Hz. + * @param busClock_Hz SD bus clock frequency united in Hz. + * + * @return The nearest frequency of busClock_Hz configured to SD bus. + */ +uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz); + +/*! + * @brief Sends 80 clocks to the card to set it to the active state. + * + * This function must be called each time the card is inserted to ensure that the card can receive the command + * correctly. + * + * @param base USDHC peripheral base address. + * @param timeout Timeout to initialize card. + * @retval true Set card active successfully. + * @retval false Set card active failed. + */ +bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout); + +/*! + * @brief trigger a hardware reset. + * + * @param base USDHC peripheral base address. + * @param 1 or 0 level + */ +static inline void USDHC_AssertHardwareReset(USDHC_Type *base, bool high) +{ + if (high) + { + base->SYS_CTRL |= USDHC_SYS_CTRL_IPP_RST_N_MASK; + } + else + { + base->SYS_CTRL &= ~USDHC_SYS_CTRL_IPP_RST_N_MASK; + } +} + +/*! + * @brief Sets the data transfer width. + * + * @param base USDHC peripheral base address. + * @param width Data transfer width. + */ +static inline void USDHC_SetDataBusWidth(USDHC_Type *base, usdhc_data_bus_width_t width) +{ + base->PROT_CTRL = ((base->PROT_CTRL & ~USDHC_PROT_CTRL_DTW_MASK) | USDHC_PROT_CTRL_DTW(width)); +} + +/*! + * @brief Fills the the data port. + * + * This function is used to implement the data transfer by Data Port instead of DMA. + * + * @param base USDHC peripheral base address. + * @param data The data about to be sent. + */ +static inline void USDHC_WriteData(USDHC_Type *base, uint32_t data) +{ + base->DATA_BUFF_ACC_PORT = data; +} + +/*! + * @brief Retrieves the data from the data port. + * + * This function is used to implement the data transfer by Data Port instead of DMA. + * + * @param base USDHC peripheral base address. + * @return The data has been read. + */ +static inline uint32_t USDHC_ReadData(USDHC_Type *base) +{ + return base->DATA_BUFF_ACC_PORT; +} + +/*! +* @brief send command function +* +* @param base USDHC peripheral base address. +* @param command configuration +*/ +void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command); + +/*! + * @brief Enables or disables a wakeup event in low-power mode. + * + * @param base USDHC peripheral base address. + * @param mask Wakeup events mask(_usdhc_wakeup_event). + * @param enable True to enable, false to disable. + */ +static inline void USDHC_EnableWakeupEvent(USDHC_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= mask; + } + else + { + base->PROT_CTRL &= ~mask; + } +} + +/*! + * @brief detect card insert status. + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_CardDetectByData3(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= USDHC_PROT_CTRL_D3CD_MASK; + } + else + { + base->PROT_CTRL &= ~USDHC_PROT_CTRL_D3CD_MASK; + } +} + +/*! + * @brief detect card insert status. + * + * @param base USDHC peripheral base address. + */ +static inline bool USDHC_DetectCardInsert(USDHC_Type *base) +{ + return (base->PRES_STATE & kUSDHC_CardInsertedFlag) ? true : false; +} + +/*! + * @brief Enables or disables the SDIO card control. + * + * @param base USDHC peripheral base address. + * @param mask SDIO card control flags mask(_usdhc_sdio_control_flag). + * @param enable True to enable, false to disable. + */ +static inline void USDHC_EnableSdioControl(USDHC_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= mask; + } + else + { + base->PROT_CTRL &= ~mask; + } +} +/*! + * @brief Restarts a transaction which has stopped at the block GAP for the SDIO card. + * + * @param base USDHC peripheral base address. + */ +static inline void USDHC_SetContinueRequest(USDHC_Type *base) +{ + base->PROT_CTRL |= USDHC_PROT_CTRL_CREQ_MASK; +} + +/*! + * @brief Configures the MMC boot feature. + * + * Example: + @code + usdhc_boot_config_t config; + config.ackTimeoutCount = 4; + config.bootMode = kUSDHC_BootModeNormal; + config.blockCount = 5; + config.enableBootAck = true; + config.enableBoot = true; + config.enableAutoStopAtBlockGap = true; + USDHC_SetMmcBootConfig(USDHC, &config); + @endcode + * + * @param base USDHC peripheral base address. + * @param config The MMC boot configuration information. + */ +void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config); + +/*! + * @brief Forces generating events according to the given mask. + * + * @param base USDHC peripheral base address. + * @param mask The force events mask(_usdhc_force_event). + */ +static inline void USDHC_SetForceEvent(USDHC_Type *base, uint32_t mask) +{ + base->FORCE_EVENT = mask; +} + +/*! + * @brief select the usdhc output voltage + * + * @param base USDHC peripheral base address. + * @param true 1.8V, false 3.0V + */ +static inline void UDSHC_SelectVoltage(USDHC_Type *base, bool en18v) +{ + if (en18v) + { + base->VEND_SPEC |= USDHC_VEND_SPEC_VSELECT_MASK; + } + else + { + base->VEND_SPEC &= ~USDHC_VEND_SPEC_VSELECT_MASK; + } +} + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) +#else + /*! + * @brief check the SDR50 mode request tuning bit + * When this bit set, user should call USDHC_StandardTuning function + * @param base USDHC peripheral base address. + */ +static inline bool USDHC_RequestTuningForSDR50(USDHC_Type *base) +{ + return base->HOST_CTRL_CAP & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK ? true : false; +} + +/*! + * @brief check the request re-tuning bit + * When this bit is set, user should do manual tuning or standard tuning function + * @param base USDHC peripheral base address. + */ +static inline bool USDHC_RequestReTuning(USDHC_Type *base) +{ + return base->PRES_STATE & USDHC_PRES_STATE_RTR_MASK ? true : false; +} + +/*! + * @brief the SDR104 mode auto tuning enable and disable + * This function should call after tuning function execute pass, auto tuning will handle + * by hardware + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_EnableAutoTuning(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; + } +} + +/*! + * @brief the config the re-tuning timer for mode 1 and mode 3 + * This timer is used for standard tuning auto re-tuning, + * @param base USDHC peripheral base address. + * @param timer counter value + */ +static inline void USDHC_SetRetuningTimer(USDHC_Type *base, uint32_t counter) +{ + base->HOST_CTRL_CAP &= ~USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK; + base->HOST_CTRL_CAP |= USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(counter); +} + +/*! + * @brief the auto tuning enbale for CMD/DATA line + * + * @param base USDHC peripheral base address. + */ +void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base); + +/*! + * @brief manual tuning trigger or abort + * User should handle the tuning cmd and find the boundary of the delay + * then calucate a average value which will be config to the CLK_TUNE_CTRL_STATUS + * This function should called before USDHC_AdjustDelayforSDR104 function + * @param base USDHC peripheral base address. + * @param tuning enable flag + */ +void USDHC_EnableManualTuning(USDHC_Type *base, bool enable); + +/*! + * @brief the SDR104 mode delay setting adjust + * This function should called after USDHC_ManualTuningForSDR104 + * @param base USDHC peripheral base address. + * @param delay setting configuration + * @retval kStatus_Fail config the delay setting fail + * @retval kStatus_Success config the delay setting success + */ +status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay); + +/*! + * @brief the enable standard tuning function + * The standard tuning window and tuning counter use the default config + * tuning cmd is send by the software, user need to check the tuning result + * can be used for SDR50,SDR104,HS200 mode tuning + * @param base USDHC peripheral base address. + * @param tuning start tap + * @param tuning step + * @param enable/disable flag + */ +void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable); + +/*! + * @brief Get execute std tuning status + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_GetExecuteStdTuningStatus(USDHC_Type *base) +{ + return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK); +} + +/*! + * @brief check std tuning result + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_CheckStdTuningResult(USDHC_Type *base) +{ + return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); +} + +/*! + * @brief check tuning error + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_CheckTuningError(USDHC_Type *base) +{ + return (base->CLK_TUNE_CTRL_STATUS & + (USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)); +} + +#endif +/*! + * @brief the enable/disable DDR mode + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + * @param nibble position + */ +static inline void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos) +{ + if (enable) + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_NIBBLE_POS_MASK; + base->MIX_CTRL |= (USDHC_MIX_CTRL_DDR_EN_MASK | USDHC_MIX_CTRL_NIBBLE_POS(nibblePos)); + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DDR_EN_MASK; + } +} + +/*! + * @brief the enable/disable HS400 mode + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +#if FSL_FEATURE_USDHC_HAS_HS400_MODE +static inline void USDHC_EnableHS400Mode(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_HS400_MODE_MASK; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_HS400_MODE_MASK; + } +} + +/*! + * @brief reset the strobe DLL + * + * @param base USDHC peripheral base address. + */ +static inline void USDHC_ResetStrobeDLL(USDHC_Type *base) +{ + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK; +} + +/*! + * @brief enable/disable the strobe DLL + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_EnableStrobeDLL(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK; + } + else + { + base->STROBE_DLL_CTRL &= ~USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK; + } +} + +/*! + * @brief config the strobe DLL delay target and update interval + * + * @param base USDHC peripheral base address. + * @param delay target + * @param update interval + */ +static inline void USDHC_ConfigStrobeDLL(USDHC_Type *base, uint32_t delayTarget, uint32_t updateInterval) +{ + base->STROBE_DLL_CTRL &= (USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK | + USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK); + + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(updateInterval) | + USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(delayTarget); +} + +/*! + * @brief get the strobe DLL status + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_GetStrobeDLLStatus(USDHC_Type *base) +{ + return base->STROBE_DLL_STATUS; +} + +#endif + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Transfers the command/data using a blocking method. + * + * This function waits until the command response/data is received or the USDHC encounters an error by polling the + * status + * flag. + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support + * the re-entry mechanism. + * + * @note There is no need to call the API 'USDHC_TransferCreateHandle' when calling this API. + * + * @param base USDHC peripheral base address. + * @param adma configuration + * @param transfer Transfer content. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * @retval kStatus_USDHC_SendCommandFailed Send command failed. + * @retval kStatus_USDHC_TransferDataFailed Transfer data failed. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer); + +/*! + * @brief Creates the USDHC handle. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle pointer. + * @param callback Structure pointer to contain all callback functions. + * @param userData Callback function parameter. + */ +void USDHC_TransferCreateHandle(USDHC_Type *base, + usdhc_handle_t *handle, + const usdhc_transfer_callback_t *callback, + void *userData); + +/*! + * @brief Transfers the command/data using an interrupt and an asynchronous method. + * + * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an + * error. + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support + * the re-entry mechanism. + * + * @note Call the API 'USDHC_TransferCreateHandle' when calling this API. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param adma configuration. + * @param transfer Transfer content. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_USDHC_BusyTransferring Busy transferring. + * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_TransferNonBlocking(USDHC_Type *base, + usdhc_handle_t *handle, + usdhc_adma_config_t *dmaConfig, + usdhc_transfer_t *transfer); + +/*! + * @brief IRQ handler for the USDHC. + * + * This function deals with the IRQs on the given host controller. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + */ +void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @} */ + +#endif /* _FSL_USDHC_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_wdog.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_wdog.c new file mode 100644 index 0000000000..c7ca61fdfc --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_wdog.c @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_wdog.h" + +#ifdef RT_USING_USERSPACE +#include "imx6ull.h" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +static WDOG_Type *const s_wdogBases[] = WDOG_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of WDOG clock name. */ +static const clock_ip_name_t s_wdogClock[] = WDOG_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t WDOG_GetInstance(WDOG_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_wdogBases); instance++) + { +#ifdef RT_USING_USERSPACE + if (s_wdogBases[instance] == rt_hw_kernel_virt_to_phys(base)) +#else + if (s_wdogBases[instance] == base) +#endif + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_wdogBases)); + + return instance; +} + +void WDOG_GetDefaultConfig(wdog_config_t *config) +{ + assert(config); + + config->enableWdog = true; + config->workMode.enableWait = false; + config->workMode.enableStop = false; + config->workMode.enableDebug = false; + config->enableInterrupt = false; + config->softwareResetExtension = false; + config->enablePowerDown = false; + config->softwareAssertion= true; + config->softwareResetSignal = true; + config->timeoutValue = 0xffu; + config->interruptTimeValue = 0x04u; +} + +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) +{ + assert(config); + + uint16_t value = 0u; + + value = WDOG_WCR_WDE(config->enableWdog) | WDOG_WCR_WDW(config->workMode.enableWait) | + WDOG_WCR_WDZST(config->workMode.enableStop) | WDOG_WCR_WDBG(config->workMode.enableDebug) | + WDOG_WCR_SRE(config->softwareResetExtension) | WDOG_WCR_WT(config->timeoutValue) | + WDOG_WCR_WDA(config->softwareAssertion) | WDOG_WCR_SRS(config->softwareResetSignal); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Set configruation */ + CLOCK_EnableClock(s_wdogClock[WDOG_GetInstance(base)]); +#endif + base->WICR = WDOG_WICR_WICT(config->interruptTimeValue) | WDOG_WICR_WIE(config->enableInterrupt); + base->WMCR = WDOG_WMCR_PDE(config->enablePowerDown); + base->WCR = value; +} + +void WDOG_Deinit(WDOG_Type *base) +{ + if (base->WCR & WDOG_WCR_WDBG_MASK) + { + WDOG_Disable(base); + } +} + +uint16_t WDOG_GetStatusFlags(WDOG_Type *base) +{ + uint16_t status_flag = 0U; + + status_flag |= (base->WCR & WDOG_WCR_WDE_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_POR_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_TOUT_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_SFTW_MASK); + status_flag |= (base->WICR & WDOG_WICR_WTIS_MASK); + + return status_flag; +} + +void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask) +{ + if (mask & kWDOG_InterruptFlag) + { + base->WICR |= WDOG_WICR_WTIS_MASK; + } +} + +void WDOG_Refresh(WDOG_Type *base) +{ + base->WSR = WDOG_REFRESH_KEY & 0xFFFFU; + base->WSR = (WDOG_REFRESH_KEY >> 16U) & 0xFFFFU; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_wdog.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_wdog.h new file mode 100644 index 0000000000..d2bb5576d3 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/fsl_wdog.h @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_WDOG_H_ +#define _FSL_WDOG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wdog + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WDOG driver version */ +#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ +/*! @name Refresh sequence */ +/*@{*/ +#define WDOG_REFRESH_KEY (0xAAAA5555U) +/*@}*/ + +/*! @brief Defines WDOG work mode. */ +typedef struct _wdog_work_mode +{ + bool enableWait; /*!< continue or suspend WDOG in wait mode */ + bool enableStop; /*!< continue or suspend WDOG in stop mode */ + bool enableDebug; /*!< continue or suspend WDOG in debug mode */ +} wdog_work_mode_t; + +/*! @brief Describes WDOG configuration structure. */ +typedef struct _wdog_config +{ + bool enableWdog; /*!< Enables or disables WDOG */ + wdog_work_mode_t workMode; /*!< Configures WDOG work mode in debug stop and wait mode */ + bool enableInterrupt; /*!< Enables or disables WDOG interrupt */ + uint16_t timeoutValue; /*!< Timeout value */ + uint16_t interruptTimeValue; /*!< Interrupt count timeout value */ + bool softwareResetExtension; /*!< software reset extension */ + bool enablePowerDown; /*!< power down enable bit */ + bool softwareAssertion; /*!< software assertion bit*/ + bool softwareResetSignal; /*!< software reset signalbit*/ +} wdog_config_t; + +/*! + * @brief WDOG interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the WDOG interrupt configurations. + */ +enum _wdog_interrupt_enable +{ + kWDOG_InterruptEnable = WDOG_WICR_WIE_MASK /*!< WDOG timeout generates an interrupt before reset*/ +}; + +/*! + * @brief WDOG status flags. + * + * This structure contains the WDOG status flags for use in the WDOG functions. + */ +enum _wdog_status_flags +{ + kWDOG_RunningFlag = WDOG_WCR_WDE_MASK, /*!< Running flag, set when WDOG is enabled*/ + kWDOG_PowerOnResetFlag = WDOG_WRSR_POR_MASK, /*!< Power On flag, set when reset is the result of a powerOnReset*/ + kWDOG_TimeoutResetFlag = WDOG_WRSR_TOUT_MASK, /*!< Timeout flag, set when reset is the result of a timeout*/ + kWDOG_SoftwareResetFlag = WDOG_WRSR_SFTW_MASK, /*!< Software flag, set when reset is the result of a software*/ + kWDOG_InterruptFlag = WDOG_WICR_WTIS_MASK /*!< interrupt flag,whether interrupt has occurred or not*/ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WDOG Initialization and De-initialization. + * @{ + */ + +/*! + * @brief Initializes the WDOG configuration sturcture. + * + * This function initializes the WDOG configuration structure to default values. The default + * values are as follows. + * @code + * wdogConfig->enableWdog = true; + * wdogConfig->workMode.enableWait = true; + * wdogConfig->workMode.enableStop = false; + * wdogConfig->workMode.enableDebug = false; + * wdogConfig->enableInterrupt = false; + * wdogConfig->enablePowerdown = false; + * wdogConfig->resetExtension = flase; + * wdogConfig->timeoutValue = 0xFFU; + * wdogConfig->interruptTimeValue = 0x04u; + * @endcode + * + * @param config Pointer to the WDOG configuration structure. + * @see wdog_config_t + */ +void WDOG_GetDefaultConfig(wdog_config_t *config); + +/*! + * @brief Initializes the WDOG. + * + * This function initializes the WDOG. When called, the WDOG runs according to the configuration. + * + * This is an example. + * @code + * wdog_config_t config; + * WDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0xffU; + * config->interruptTimeValue = 0x04u; + * WDOG_Init(wdog_base,&config); + * @endcode + * + * @param base WDOG peripheral base address + * @param config The configuration of WDOG + */ +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config); + +/*! + * @brief Shuts down the WDOG. + * + * This function shuts down the WDOG. + * Watchdog Enable bit is a write one once only bit. It is not + * possible to clear this bit by a software write, once the bit is set. + * This bit(WDE) can be set/reset only in debug mode(exception). + */ +void WDOG_Deinit(WDOG_Type *base); + +/*! + * @brief Enables the WDOG module. + * + * This function writes a value into the WDOG_WCR register to enable the WDOG. + * This is a write one once only bit. It is not possible to clear this bit by a software write, + * once the bit is set. only debug mode exception. + * @param base WDOG peripheral base address + */ +static inline void WDOG_Enable(WDOG_Type *base) +{ + base->WCR |= WDOG_WCR_WDE_MASK; +} + +/*! + * @brief Disables the WDOG module. + * + * This function writes a value into the WDOG_WCR register to disable the WDOG. + * This is a write one once only bit. It is not possible to clear this bit by a software write,once the bit is set. + * only debug mode exception + * @param base WDOG peripheral base address + */ +static inline void WDOG_Disable(WDOG_Type *base) +{ + base->WCR &= ~WDOG_WCR_WDE_MASK; +} + +/*! + * @brief Enables the WDOG interrupt. + * + *This bit is a write once only bit. Once the software does a write access to this bit, it will get + *locked and cannot be reprogrammed until the next system reset assertion + * + * @param base WDOG peripheral base address + * @param mask The interrupts to enable + * The parameter can be combination of the following source if defined. + * @arg kWDOG_InterruptEnable + */ +static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint16_t mask) +{ + base->WICR |= mask; +} + +/*! + * @brief Gets the WDOG all reset status flags. + * + * This function gets all reset status flags. + * + * @code + * uint16_t status; + * status = WDOG_GetStatusFlags (wdog_base); + * @endcode + * @param base WDOG peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags + * - true: a related status flag has been set. + * - false: a related status flag is not set. + */ +uint16_t WDOG_GetStatusFlags(WDOG_Type *base); + +/*! + * @brief Clears the WDOG flag. + * + * This function clears the WDOG status flag. + * + * This is an example for clearing the interrupt flag. + * @code + * WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag); + * @endcode + * @param base WDOG peripheral base address + * @param mask The status flags to clear. + * The parameter could be any combination of the following values. + * kWDOG_TimeoutFlag + */ +void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask); + +/*! + * @brief Sets the WDOG timeout value. + * + * This function sets the timeout value. + * This function writes a value into WCR registers. + * The time-out value can be written at any point of time but it is loaded to the counter at the time + * when WDOG is enabled or after the service routine has been performed. + * + * @param base WDOG peripheral base address + * @param timeoutCount WDOG timeout value; count of WDOG clock tick. + */ +static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint16_t timeoutCount) +{ + base->WCR = (base->WCR & ~WDOG_WCR_WT_MASK) | WDOG_WCR_WT(timeoutCount); +} + +/*! + * @brief Sets the WDOG interrupt count timeout value. + * + * This function sets the interrupt count timeout value. + * This function writes a value into WIC registers which are wirte-once. + * This field is write once only. Once the software does a write access to this field, it will get locked + * and cannot be reprogrammed until the next system reset assertion. + * @param base WDOG peripheral base address + * @param timeoutCount WDOG timeout value; count of WDOG clock tick. + */ +static inline void WDOG_SetInterrputTimeoutValue(WDOG_Type *base, uint16_t timeoutCount) +{ + base->WICR = (base->WICR & ~WDOG_WICR_WICT_MASK) | WDOG_WICR_WICT(timeoutCount); +} + +/*! + * @brief Disable the WDOG power down enable bit. + * + * This function disable the WDOG power down enable(PDE). + * This function writes a value into WMCR registers which are wirte-once. + * This field is write once only. Once software sets this bit it cannot be reset until the next system reset. + * @param base WDOG peripheral base address + */ +static inline void WDOG_DisablePowerDownEnable(WDOG_Type *base) +{ + base->WMCR &= ~WDOG_WMCR_PDE_MASK; +} + +/*! + * @brief Refreshes the WDOG timer. + * + * This function feeds the WDOG. + * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WDOG peripheral base address + */ +void WDOG_Refresh(WDOG_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_WDOG_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/event.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/event.c new file mode 100644 index 0000000000..8125c45499 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/event.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "event.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get event instance. + * @param eventType The event type + * @return The event instance's pointer. + */ +static volatile uint32_t *EVENT_GetInstance(event_t eventType); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Card detect event. */ +static volatile uint32_t g_eventCardDetect; + +/*! @brief transfer complete event. */ +static volatile uint32_t g_eventTransferComplete; + +/******************************************************************************* + * Code + ******************************************************************************/ +void EVENT_InitTimer(void) +{ +} + +static volatile uint32_t *EVENT_GetInstance(event_t eventType) +{ + volatile uint32_t *event; + + switch (eventType) + { + case kEVENT_TransferComplete: + event = &g_eventTransferComplete; + break; + case kEVENT_CardDetect: + event = &g_eventCardDetect; + break; + default: + event = NULL; + break; + } + + return event; +} + +bool EVENT_Create(event_t eventType) +{ + volatile uint32_t *event = EVENT_GetInstance(eventType); + + if (event) + { + *event = 0; + return true; + } + else + { + return false; + } +} + +bool EVENT_Wait(event_t eventType, uint32_t timeoutMilliseconds) +{ + uint32_t currentTime; + + volatile uint32_t *event = EVENT_GetInstance(eventType); + + if (timeoutMilliseconds && event) + { + currentTime = 0; + do + { + rt_hw_us_delay(1000); + currentTime++; + } while ((*event == 0U) && (currentTime < timeoutMilliseconds)); + *event = 0U; + + return ((currentTime < timeoutMilliseconds) ? true : false); + } + else + { + return false; + } +} + +bool EVENT_Notify(event_t eventType) +{ + volatile uint32_t *event = EVENT_GetInstance(eventType); + + if (event) + { + *event = 1U; + return true; + } + else + { + return false; + } +} + +void EVENT_Delete(event_t eventType) +{ + volatile uint32_t *event = EVENT_GetInstance(eventType); + + if (event) + { + *event = 0U; + } +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/event.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/event.h new file mode 100644 index 0000000000..e173ddf52f --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/event.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _EVENT_H_ +#define _EVENT_H_ + +#include "fsl_common.h" +#include "bsp_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Event type */ +typedef enum _event +{ + kEVENT_TransferComplete = 0U, /*!< Transfer complete event */ + kEVENT_CardDetect = 1U, /*!< Card detect event */ +} event_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Event Function + * @{ + */ + +/*! + * @brief Initialize timer to implement wait event timeout. + */ +void EVENT_InitTimer(void); + +/* Callback function for SDHC */ + +/*! + * @brief Create event. + * @param eventType The event type + * @retval true Create event successfully. + * @retval false Create event failed. + */ +bool EVENT_Create(event_t eventType); + +/*! + * @brief Wait event. + * + * @param eventType The event type + * @param timeoutMilliseconds Timeout time in milliseconds. + * @retval true Wait event successfully. + * @retval false Wait event failed. + */ +bool EVENT_Wait(event_t eventType, uint32_t timeoutMilliseconds); + +/*! + * @brief Notify event. + * @param eventType The event type + * @retval true Notify event successfully. + * @retval false Notify event failed. + */ +bool EVENT_Notify(event_t eventType); + +/*! + * @brief Delete event. + * @param eventType The event type + */ +void EVENT_Delete(event_t eventType); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _EVENT_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_card.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_card.h new file mode 100644 index 0000000000..5136b98329 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_card.h @@ -0,0 +1,668 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CARD_H_ +#define _FSL_CARD_H_ + +#include "fsl_common.h" +#include "fsl_specification.h" +#include "fsl_host.h" +#include "stdlib.h" +/*! + * @addtogroup CARD + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Driver version. */ +#define FSL_SDMMC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 4U)) /*2.1.4*/ + +/*! @brief Default block size */ +#define FSL_SDMMC_DEFAULT_BLOCK_SIZE (512U) +/*! @brief SDMMC global data buffer size, word unit*/ +#define SDMMC_GLOBAL_BUFFER_SIZE (64U) + +/*! @brief SD/MMC card API's running status. */ +enum _sdmmc_status +{ + kStatus_SDMMC_NotSupportYet = MAKE_STATUS(kStatusGroup_SDMMC, 0U), /*!< Haven't supported */ + kStatus_SDMMC_TransferFailed = MAKE_STATUS(kStatusGroup_SDMMC, 1U), /*!< Send command failed */ + kStatus_SDMMC_SetCardBlockSizeFailed = MAKE_STATUS(kStatusGroup_SDMMC, 2U), /*!< Set block size failed */ + kStatus_SDMMC_HostNotSupport = MAKE_STATUS(kStatusGroup_SDMMC, 3U), /*!< Host doesn't support */ + kStatus_SDMMC_CardNotSupport = MAKE_STATUS(kStatusGroup_SDMMC, 4U), /*!< Card doesn't support */ + kStatus_SDMMC_AllSendCidFailed = MAKE_STATUS(kStatusGroup_SDMMC, 5U), /*!< Send CID failed */ + kStatus_SDMMC_SendRelativeAddressFailed = MAKE_STATUS(kStatusGroup_SDMMC, 6U), /*!< Send relative address failed */ + kStatus_SDMMC_SendCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 7U), /*!< Send CSD failed */ + kStatus_SDMMC_SelectCardFailed = MAKE_STATUS(kStatusGroup_SDMMC, 8U), /*!< Select card failed */ + kStatus_SDMMC_SendScrFailed = MAKE_STATUS(kStatusGroup_SDMMC, 9U), /*!< Send SCR failed */ + kStatus_SDMMC_SetDataBusWidthFailed = MAKE_STATUS(kStatusGroup_SDMMC, 10U), /*!< Set bus width failed */ + kStatus_SDMMC_GoIdleFailed = MAKE_STATUS(kStatusGroup_SDMMC, 11U), /*!< Go idle failed */ + kStatus_SDMMC_HandShakeOperationConditionFailed = + MAKE_STATUS(kStatusGroup_SDMMC, 12U), /*!< Send Operation Condition failed */ + kStatus_SDMMC_SendApplicationCommandFailed = + MAKE_STATUS(kStatusGroup_SDMMC, 13U), /*!< Send application command failed */ + kStatus_SDMMC_SwitchFailed = MAKE_STATUS(kStatusGroup_SDMMC, 14U), /*!< Switch command failed */ + kStatus_SDMMC_StopTransmissionFailed = MAKE_STATUS(kStatusGroup_SDMMC, 15U), /*!< Stop transmission failed */ + kStatus_SDMMC_WaitWriteCompleteFailed = MAKE_STATUS(kStatusGroup_SDMMC, 16U), /*!< Wait write complete failed */ + kStatus_SDMMC_SetBlockCountFailed = MAKE_STATUS(kStatusGroup_SDMMC, 17U), /*!< Set block count failed */ + kStatus_SDMMC_SetRelativeAddressFailed = MAKE_STATUS(kStatusGroup_SDMMC, 18U), /*!< Set relative address failed */ + kStatus_SDMMC_SwitchBusTimingFailed = MAKE_STATUS(kStatusGroup_SDMMC, 19U), /*!< Switch high speed failed */ + kStatus_SDMMC_SendExtendedCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 20U), /*!< Send EXT_CSD failed */ + kStatus_SDMMC_ConfigureBootFailed = MAKE_STATUS(kStatusGroup_SDMMC, 21U), /*!< Configure boot failed */ + kStatus_SDMMC_ConfigureExtendedCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 22U), /*!< Configure EXT_CSD failed */ + kStatus_SDMMC_EnableHighCapacityEraseFailed = + MAKE_STATUS(kStatusGroup_SDMMC, 23U), /*!< Enable high capacity erase failed */ + kStatus_SDMMC_SendTestPatternFailed = MAKE_STATUS(kStatusGroup_SDMMC, 24U), /*!< Send test pattern failed */ + kStatus_SDMMC_ReceiveTestPatternFailed = MAKE_STATUS(kStatusGroup_SDMMC, 25U), /*!< Receive test pattern failed */ + kStatus_SDMMC_SDIO_ResponseError = MAKE_STATUS(kStatusGroup_SDMMC, 26U), /*!< sdio response error */ + kStatus_SDMMC_SDIO_InvalidArgument = + MAKE_STATUS(kStatusGroup_SDMMC, 27U), /*!< sdio invalid argument response error */ + kStatus_SDMMC_SDIO_SendOperationConditionFail = + MAKE_STATUS(kStatusGroup_SDMMC, 28U), /*!< sdio send operation condition fail */ + kStatus_SDMMC_InvalidVoltage = MAKE_STATUS(kStatusGroup_SDMMC, 29U), /*!< invaild voltage */ + kStatus_SDMMC_SDIO_SwitchHighSpeedFail = MAKE_STATUS(kStatusGroup_SDMMC, 30U), /*!< switch to high speed fail */ + kStatus_SDMMC_SDIO_ReadCISFail = MAKE_STATUS(kStatusGroup_SDMMC, 31U), /*!< read CIS fail */ + kStatus_SDMMC_SDIO_InvalidCard = MAKE_STATUS(kStatusGroup_SDMMC, 32U), /*!< invaild SDIO card */ + kStatus_SDMMC_TuningFail = MAKE_STATUS(kStatusGroup_SDMMC, 33U), /*!< tuning fail */ + kStatus_SDMMC_SwitchVoltageFail = MAKE_STATUS(kStatusGroup_SDMMC, 34U), /*!< switch voltage fail*/ + kStatus_SDMMC_ReTuningRequest = MAKE_STATUS(kStatusGroup_SDMMC, 35U), /*!< retuning request */ + kStatus_SDMMC_SetDriverStrengthFail = MAKE_STATUS(kStatusGroup_SDMMC, 36U), /*!< set driver strength fail */ + kStatus_SDMMC_SetPowerClassFail = MAKE_STATUS(kStatusGroup_SDMMC, 37U), /*!< set power class fail */ +}; + +/*! @brief SD card flags */ +enum _sd_card_flag +{ + kSD_SupportHighCapacityFlag = (1U << 1U), /*!< Support high capacity */ + kSD_Support4BitWidthFlag = (1U << 2U), /*!< Support 4-bit data width */ + kSD_SupportSdhcFlag = (1U << 3U), /*!< Card is SDHC */ + kSD_SupportSdxcFlag = (1U << 4U), /*!< Card is SDXC */ + kSD_SupportVoltage180v = (1U << 5U), /*!< card support 1.8v voltage*/ + kSD_SupportSetBlockCountCmd = (1U << 6U), /*!< card support cmd23 flag*/ + kSD_SupportSpeedClassControlCmd = (1U << 7U), /*!< card support speed class control flag */ +}; + +/*! @brief MMC card flags */ +enum _mmc_card_flag +{ + kMMC_SupportHighSpeed26MHZFlag = (1U << 0U), /*!< Support high speed 26MHZ */ + kMMC_SupportHighSpeed52MHZFlag = (1U << 1U), /*!< Support high speed 52MHZ */ + kMMC_SupportHighSpeedDDR52MHZ180V300VFlag = (1 << 2U), /*!< ddr 52MHZ 1.8V or 3.0V */ + kMMC_SupportHighSpeedDDR52MHZ120VFlag = (1 << 3U), /*!< DDR 52MHZ 1.2V */ + kMMC_SupportHS200200MHZ180VFlag = (1 << 4U), /*!< HS200 ,200MHZ,1.8V */ + kMMC_SupportHS200200MHZ120VFlag = (1 << 5U), /*!< HS200, 200MHZ, 1.2V */ + kMMC_SupportHS400DDR200MHZ180VFlag = (1 << 6U), /*!< HS400, DDR, 200MHZ,1.8V */ + kMMC_SupportHS400DDR200MHZ120VFlag = (1 << 7U), /*!< HS400, DDR, 200MHZ,1.2V */ + kMMC_SupportHighCapacityFlag = (1U << 8U), /*!< Support high capacity */ + kMMC_SupportAlternateBootFlag = (1U << 9U), /*!< Support alternate boot */ + kMMC_SupportDDRBootFlag = (1U << 10U), /*!< support DDR boot flag*/ + kMMC_SupportHighSpeedBootFlag = (1U << 11U), /*!< support high speed boot flag*/ + + kMMC_DataBusWidth4BitFlag = (1U << 12U), /*!< current data bus is 4 bit mode*/ + kMMC_DataBusWidth8BitFlag = (1U << 13U), /*!< current data bus is 8 bit mode*/ + kMMC_DataBusWidth1BitFlag = (1U << 14U), /*!< current data bus is 1 bit mode */ + +}; + +/*! @brief card operation voltage */ +typedef enum _card_operation_voltage +{ + kCARD_OperationVoltageNone = 0U, /*!< indicate current voltage setting is not setting bu suser*/ + kCARD_OperationVoltage330V = 1U, /*!< card operation voltage around 3.3v */ + kCARD_OperationVoltage300V = 2U, /*!< card operation voltage around 3.0v */ + kCARD_OperationVoltage180V = 3U, /*!< card operation voltage around 31.8v */ +} card_operation_voltage_t; + +/*! + * @brief SD card state + * + * Define the card structure including the necessary fields to identify and describe the card. + */ +typedef struct _sd_card +{ + HOST_CONFIG host; /*!< Host information */ + + bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ + uint32_t busClock_Hz; /*!< SD bus clock frequency united in Hz */ + uint32_t relativeAddress; /*!< Relative address of the card */ + uint32_t version; /*!< Card version */ + uint32_t flags; /*!< Flags in _sd_card_flag */ + uint32_t rawCid[4U]; /*!< Raw CID content */ + uint32_t rawCsd[4U]; /*!< Raw CSD content */ + uint32_t rawScr[2U]; /*!< Raw CSD content */ + uint32_t ocr; /*!< Raw OCR content */ + sd_cid_t cid; /*!< CID */ + sd_csd_t csd; /*!< CSD */ + sd_scr_t scr; /*!< SCR */ + uint32_t blockCount; /*!< Card total block number */ + uint32_t blockSize; /*!< Card block size */ + sd_timing_mode_t currentTiming; /*!< current timing mode */ + sd_driver_strength_t driverStrength; /*!< driver strength */ + sd_max_current_t maxCurrent; /*!< card current limit */ + card_operation_voltage_t operationVoltage; /*!< card operation voltage */ +} sd_card_t; + +/*! + * @brief SDIO card state + * + * Define the card structure including the necessary fields to identify and describe the card. + */ +typedef struct _sdio_card +{ + HOST_CONFIG host; /*!< Host information */ + + bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ + bool memPresentFlag; /*!< indicate if memory present */ + + uint32_t busClock_Hz; /*!< SD bus clock frequency united in Hz */ + uint32_t relativeAddress; /*!< Relative address of the card */ + uint8_t sdVersion; /*!< SD version */ + uint8_t sdioVersion; /*!< SDIO version */ + uint8_t cccrVersioin; /*!< CCCR version */ + uint8_t ioTotalNumber; /*!< total number of IO function */ + uint32_t cccrflags; /*!< Flags in _sd_card_flag */ + uint32_t io0blockSize; /*!< record the io0 block size*/ + uint32_t ocr; /*!< Raw OCR content, only 24bit avalible for SDIO card */ + uint32_t commonCISPointer; /*!< point to common CIS */ + + sdio_fbr_t ioFBR[7U]; /*!< FBR table */ + + sdio_common_cis_t commonCIS; /*!< CIS table */ + sdio_func_cis_t funcCIS[7U]; /*!< function CIS table*/ + +} sdio_card_t; + +/*! + * @brief SD card state + * + * Define the card structure including the necessary fields to identify and describe the card. + */ +typedef struct _mmc_card +{ + HOST_CONFIG host; /*!< Host information */ + + bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ + uint32_t busClock_Hz; /*!< MMC bus clock united in Hz */ + uint32_t relativeAddress; /*!< Relative address of the card */ + bool enablePreDefinedBlockCount; /*!< Enable PRE-DEFINED block count when read/write */ + uint32_t flags; /*!< Capability flag in _mmc_card_flag */ + uint32_t rawCid[4U]; /*!< Raw CID content */ + uint32_t rawCsd[4U]; /*!< Raw CSD content */ + uint32_t rawExtendedCsd[MMC_EXTENDED_CSD_BYTES / 4U]; /*!< Raw MMC Extended CSD content */ + uint32_t ocr; /*!< Raw OCR content */ + mmc_cid_t cid; /*!< CID */ + mmc_csd_t csd; /*!< CSD */ + mmc_extended_csd_t extendedCsd; /*!< Extended CSD */ + uint32_t blockSize; /*!< Card block size */ + uint32_t userPartitionBlocks; /*!< Card total block number in user partition */ + uint32_t bootPartitionBlocks; /*!< Boot partition size united as block size */ + uint32_t eraseGroupBlocks; /*!< Erase group size united as block size */ + mmc_access_partition_t currentPartition; /*!< Current access partition */ + mmc_voltage_window_t hostVoltageWindowVCCQ; /*!< Host IO voltage window */ + mmc_voltage_window_t hostVoltageWindowVCC; /*!< application must set this value according to board specific */ + mmc_high_speed_timing_t currentTiming; /*!< indicate the current host timing mode*/ + +} mmc_card_t; + +/*! @brief MMC card boot configuration definition. */ +typedef struct _mmc_boot_config +{ + bool enableBootAck; /*!< Enable boot ACK */ + mmc_boot_partition_enable_t bootPartition; /*!< Boot partition */ + bool retainBootBusWidth; /*!< If retain boot bus width */ + mmc_data_bus_width_t bootDataBusWidth; /*!< Boot data bus width */ +} mmc_boot_config_t; + +/* define a function pointer for tuning */ +typedef status_t (*card_send_tuning_func)(void *cardType); + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SDCARD Function + * @{ + */ + +/*! + * @brief Initializes the card on a specific host controller. + * + * This function initializes the card on a specific host controller. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. + * @retval kStatus_SDMMC_NotSupportYet Card not support. + * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. + * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. + * @retval kStatus_SDMMC_SendRelativeAddressFailed Send relative address failed. + * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. + * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. + * @retval kStatus_SDMMC_SendScrFailed Send SCR failed. + * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. + * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. + * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_Init(sd_card_t *card); + +/*! + * @brief Deinitializes the card. + * + * This function deinitializes the specific card. + * + * @param card Card descriptor. + */ +void SD_Deinit(sd_card_t *card); + +/*! + * @brief Checks whether the card is write-protected. + * + * This function checks if the card is write-protected via the CSD register. + * + * @param card The specific card. + * @retval true Card is read only. + * @retval false Card isn't read only. + */ +bool SD_CheckReadOnly(sd_card_t *card); + +/*! + * @brief Reads blocks from the specific card. + * + * This function reads blocks from the specific card with default block size defined by the + * SDHC_CARD_DEFAULT_BLOCK_SIZE. + * + * @param card Card descriptor. + * @param buffer The buffer to save the data read from card. + * @param startBlock The start block index. + * @param blockCount The number of blocks to read. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_NotSupportYet Not support now. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_ReadBlocks(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Writes blocks of data to the specific card. + * + * This function writes blocks to the specific card with default block size 512 bytes. + * + * @param card Card descriptor. + * @param buffer The buffer holding the data to be written to the card. + * @param startBlock The start block index. + * @param blockCount The number of blocks to write. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_NotSupportYet Not support now. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_WriteBlocks(sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Erases blocks of the specific card. + * + * This function erases blocks of the specific card with default block size 512 bytes. + * + * @param card Card descriptor. + * @param startBlock The start block index. + * @param blockCount The number of blocks to erase. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SD_EraseBlocks(sd_card_t *card, uint32_t startBlock, uint32_t blockCount); + +/* @} */ + +/*! + * @name MMCCARD Function + * @{ + */ + +/*! + * @brief Initializes the MMC card. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. + * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. + * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. + * @retval kStatus_SDMMC_SetRelativeAddressFailed Set relative address failed. + * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. + * @retval kStatus_SDMMC_SendExtendedCsdFailed Send EXT_CSD failed. + * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. + * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. + * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_Init(mmc_card_t *card); + +/*! + * @brief Deinitializes the card. + * + * @param card Card descriptor. + */ + +void MMC_Deinit(mmc_card_t *card); + +/*! + * @brief Checks if the card is read-only. + * + * @param card Card descriptor. + * @retval true Card is read only. + * @retval false Card isn't read only. + */ +bool MMC_CheckReadOnly(mmc_card_t *card); + +/*! + * @brief Reads data blocks from the card. + * + * @param card Card descriptor. + * @param buffer The buffer to save data. + * @param startBlock The start block index. + * @param blockCount The number of blocks to read. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_ReadBlocks(mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Writes data blocks to the card. + * + * @param card Card descriptor. + * @param buffer The buffer to save data blocks. + * @param startBlock Start block number to write. + * @param blockCount Block count. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_NotSupportYet Not support now. + * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_WriteBlocks(mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Erases groups of the card. + * + * Erase group is the smallest erase unit in MMC card. The erase range is [startGroup, endGroup]. + * + * @param card Card descriptor. + * @param startGroup Start group number. + * @param endGroup End group number. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_EraseGroups(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup); + +/*! + * @brief Selects the partition to access. + * + * @param card Card descriptor. + * @param partitionNumber The partition number. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure EXT_CSD failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_SelectPartition(mmc_card_t *card, mmc_access_partition_t partitionNumber); + +/*! + * @brief Configures the boot activity of the card. + * + * @param card Card descriptor. + * @param config Boot configuration structure. + * @retval kStatus_SDMMC_NotSupportYet Not support now. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure EXT_CSD failed. + * @retval kStatus_SDMMC_ConfigureBootFailed Configure boot failed. + * @retval kStatus_Success Operate successfully. + */ +status_t MMC_SetBootConfig(mmc_card_t *card, const mmc_boot_config_t *config); + +/*! + * @brief set SDIO card to inactive state + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_CardInActive(sdio_card_t *card); + +/*! + * @brief IO direct write transfer function + * + * @param card Card descriptor. + * @param function IO numner + * @param register address + * @param the data pinter to write + * @param raw flag, indicate read after write or write only + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_IO_Write_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data, bool raw); + +/*! + * @brief IO direct read transfer function + * + * @param card Card descriptor. + * @param function IO number + * @param register address + * @param data pointer to read + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_IO_Read_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data); + +/*! + * @brief IO extended write transfer function + * + * @param card Card descriptor. + * @param function IO number + * @param register address + * @param data buffer to write + * @param data count + * @param write flags + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_SDMMC_SDIO_InvalidArgument + * @retval kStatus_Success + */ +status_t SDIO_IO_Write_Extended( + sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags); +/*! + * @brief IO extended read transfer function + * + * @param card Card descriptor. + * @param function IO number + * @param register address + * @param data buffer to read + * @param data count + * @param write flags + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_SDMMC_SDIO_InvalidArgument + * @retval kStatus_Success + */ +status_t SDIO_IO_Read_Extended( + sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags); +/*! + * @brief get SDIO card capability + * + * @param card Card descriptor. + * @param function IO number + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_GetCardCapability(sdio_card_t *card, sdio_func_num_t func); + +/*! + * @brief set SDIO card block size + * + * @param card Card descriptor. + * @param function io number + * @param block size + * @retval kStatus_SDMMC_SetCardBlockSizeFailed + * @retval kStatus_SDMMC_SDIO_InvalidArgument + * @retval kStatus_Success + */ +status_t SDIO_SetBlockSize(sdio_card_t *card, sdio_func_num_t func, uint32_t blockSize); + +/*! + * @brief set SDIO card reset + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_CardReset(sdio_card_t *card); + +/*! + * @brief set SDIO card data bus width + * + * @param card Card descriptor. + * @param data bus width + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_SetDataBusWidth(sdio_card_t *card, sdio_bus_width_t busWidth); + +/*! + * @brief switch the card to high speed + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_SDMMC_SDIO_SwitchHighSpeedFail + * @retval kStatus_Success + */ +status_t SDIO_SwitchToHighSpeed(sdio_card_t *card); + +/*! + * @brief read SDIO card CIS for each function + * + * @param card Card descriptor. + * @param function io number + * @param tuple code list + * @param tuple code number + * @retval kStatus_SDMMC_SDIO_ReadCISFail + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_ReadCIS(sdio_card_t *card, sdio_func_num_t func, const uint32_t *tupleList, uint32_t tupleNum); + +/*! + * @brief SDIO card init function + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_GoIdleFailed + * @retval kStatus_SDMMC_HandShakeOperationConditionFailed + * @retval kStatus_SDMMC_SDIO_InvalidCard + * @retval kStatus_SDMMC_SDIO_InvalidVoltage + * @retval kStatus_SDMMC_SendRelativeAddressFailed + * @retval kStatus_SDMMC_SelectCardFailed + * @retval kStatus_SDMMC_SDIO_SwitchHighSpeedFail + * @retval kStatus_SDMMC_SDIO_ReadCISFail + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_Init(sdio_card_t *card); + +/*! + * @brief enable IO interrupt + * + * @param card Card descriptor. + * @param function IO number + * @param enable/disable flag + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_EnableIOInterrupt(sdio_card_t *card, sdio_func_num_t func, bool enable); + +/*! + * @brief enable IO and wait IO ready + * + * @param card Card descriptor. + * @param function IO number + * @param enable/disable flag + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_EnableIO(sdio_card_t *card, sdio_func_num_t func, bool enable); + +/*! + * @brief select IO + * + * @param card Card descriptor. + * @param function IO number + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_SelectIO(sdio_card_t *card, sdio_func_num_t func); + +/*! + * @brief Abort IO transfer + * + * @param card Card descriptor. + * @param function IO number + * @retval kStatus_SDMMC_TransferFailed + * @retval kStatus_Success + */ +status_t SDIO_AbortIO(sdio_card_t *card, sdio_func_num_t func); + +/*! + * @brief SDIO card deinit + * + * @param card Card descriptor. + */ +void SDIO_DeInit(sdio_card_t *card); + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! @} */ +#endif /* _FSL_CARD_H_*/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_host.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_host.c new file mode 100644 index 0000000000..aa2e2d3ceb --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_host.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_host.h" +#include "fsl_gpio.h" +#include "event.h" +#ifdef BOARD_USDHC_CD_PORT_BASE +#include "fsl_port.h" +#endif +/******************************************************************************* +* Definitions +******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief host controller error recovery. + * @param host base address. + */ +static void Host_ErrorRecovery(HOST_TYPE *hostBase); +/******************************************************************************* + * Variables + ******************************************************************************/ +/* DMA descriptor should allocate at non-cached memory */ +AT_NONCACHEABLE_SECTION_ALIGN(uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS], USDHC_ADMA2_ADDR_ALIGN); +extern volatile uint32_t g_timeMilliseconds; +static volatile bool g_sdInsertedFlag; +/******************************************************************************* + * Code + ******************************************************************************/ +static void DetectCardByGpio(void) +{ + g_sdInsertedFlag = true; //always return linked status! +} + +/* Card detect. */ +status_t CardInsertDetect(HOST_TYPE *hostBase) +{ + return kStatus_Success; //always return linked status! +} + +/* Card detect pin port interrupt handler. */ +void HOST_CARD_DETECT_INTERRUPT_HANDLER(void) +{ + if (HOST_CARD_DETECT_INTERRUPT_STATUS() & (1U << BOARD_USDHC_CD_GPIO_PIN)) + { + DetectCardByGpio(); + } + /* Clear interrupt flag.*/ + HOST_CARD_DETECT_INTERRUPT_CLEAR(~0U); + EVENT_Notify(kEVENT_CardDetect); +} + +/* User defined transfer function. */ +static status_t USDHC_TransferFunction(USDHC_Type *base, usdhc_transfer_t *content) +{ + usdhc_adma_config_t dmaConfig; + status_t error = kStatus_Success; + + if (content->data != NULL) + { + memset(&dmaConfig, 0, sizeof(usdhc_adma_config_t)); + /* config adma */ + dmaConfig.dmaMode = USDHC_DMA_MODE; + dmaConfig.burstLen = kUSDHC_EnBurstLenForINCR; + dmaConfig.admaTable = g_usdhcAdma2Table; + dmaConfig.admaTableWords = USDHC_ADMA_TABLE_WORDS; + } + + error = USDHC_TransferBlocking(base, &dmaConfig, content); + + if (error == kStatus_Fail) + { + /* host error recovery */ + Host_ErrorRecovery(base); + } + + return error; +} + +static void Host_ErrorRecovery(HOST_TYPE *hostBase) +{ + uint32_t status = 0U; + /* get host present status */ + status = USDHC_GetPresentStatusFlags(hostBase); + /* check command inhibit status flag */ + if ((status & kUSDHC_CommandInhibitFlag) != 0U) + { + /* reset command line */ + USDHC_Reset(hostBase, kUSDHC_ResetCommand, 100U); + } + /* check data inhibit status flag */ + if ((status & kUSDHC_DataInhibitFlag) != 0U) + { + /* reset data line */ + USDHC_Reset(hostBase, kUSDHC_ResetData, 100U); + } +} + +status_t HOST_Init(void *host) +{ + usdhc_host_t *usdhcHost = (usdhc_host_t *)host; + + /* init card power control */ + HOST_INIT_SD_POWER(); + HOST_INIT_MMC_POWER(); + + /* Initializes SDHC. */ + usdhcHost->config.dataTimeout = USDHC_DATA_TIMEOUT; + usdhcHost->config.endianMode = USDHC_ENDIAN_MODE; + usdhcHost->config.readWatermarkLevel = USDHC_READ_WATERMARK_LEVEL; + usdhcHost->config.writeWatermarkLevel = USDHC_WRITE_WATERMARK_LEVEL; + usdhcHost->config.readBurstLen = USDHC_READ_BURST_LEN; + usdhcHost->config.writeBurstLen = USDHC_WRITE_BURST_LEN; + + USDHC_Init(usdhcHost->base, &(usdhcHost->config)); + + /* Define transfer function. */ + usdhcHost->transfer = USDHC_TransferFunction; + /* event init timer */ + EVENT_InitTimer(); + + return kStatus_Success; +} + +void HOST_Reset(HOST_TYPE *hostBase) +{ + /* voltage switch to normal but not 1.8V */ + HOST_SWITCH_VOLTAGE180V(hostBase, false); + /* Disable DDR mode */ + HOST_ENABLE_DDR_MODE(hostBase, false); + /* disable tuning */ + HOST_EXECUTE_STANDARD_TUNING_ENABLE(hostBase, false); + /* Disable HS400 mode */ + HOST_ENABLE_HS400_MODE(hostBase, false); + /* Disable DLL */ + HOST_ENABLE_STROBE_DLL(hostBase, false); +} + +void HOST_Deinit(void *host) +{ + usdhc_host_t *usdhcHost = (usdhc_host_t *)host; + USDHC_Deinit(usdhcHost->base); +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_host.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_host.h new file mode 100644 index 0000000000..7d5350ed9c --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_host.h @@ -0,0 +1,646 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_HOST_H +#define _FSL_HOST_H + +#include "fsl_common.h" +#include "usdhc_config.h" +#if defined(FSL_FEATURE_SOC_SDHC_COUNT) && FSL_FEATURE_SOC_SDHC_COUNT > 0U +#include "fsl_sdhc.h" +#elif defined(FSL_FEATURE_SOC_SDIF_COUNT) && FSL_FEATURE_SOC_SDIF_COUNT > 0U +#include "fsl_sdif.h" +#elif defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT > 0U +#include "fsl_usdhc.h" +#if (FSL_FEATURE_SOC_IOMUXC_COUNT != 0U) +#include "fsl_iomuxc.h" +#else +#include "fsl_port.h" +#endif +#endif + +/*! + * @addtogroup CARD + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* add cache line size align */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#if defined(FSL_FEATURE_L2DCACHE_LINESIZE_BYTE) +#define SDMMC_DATA_BUFFER_ALIGN_CAHCE MAX(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE, FSL_FEATURE_L2DCACHE_LINESIZE_BYTE) +#else +#define SDMMC_DATA_BUFFER_ALIGN_CAHCE FSL_FEATURE_L1DCACHE_LINESIZE_BYTE +#endif +#else +#define SDMMC_DATA_BUFFER_ALIGN_CAHCE 1 +#endif +#else +#define SDMMC_DATA_BUFFER_ALIGN_CAHCE 1 +#endif + +#define HOST_NOT_SUPPORT 0U /*!< use this define to indicate the host not support feature*/ +#define HOST_SUPPORT 1U /*!< use this define to indicate the host support feature*/ +/* select host */ +#if defined(FSL_FEATURE_SOC_SDHC_COUNT) && FSL_FEATURE_SOC_SDHC_COUNT > 0U + +/* SDR104 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ +#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ +#else +#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ +#endif +/* HS200 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ +#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 +#else +#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 +#endif +/* HS400 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ +#define HOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ /* host do not support HS400 */ +#else +#define HOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400 +#endif + +/*define host baseaddr ,clk freq, IRQ number*/ +#define MMC_HOST_BASEADDR BOARD_SDHC_BASEADDR +#define MMC_HOST_CLK_FREQ BOARD_SDHC_CLK_FREQ +#define MMC_HOST_IRQ BOARD_SDHC_IRQ +#define SD_HOST_BASEADDR BOARD_SDHC_BASEADDR +#define SD_HOST_CLK_FREQ BOARD_SDHC_CLK_FREQ +#define SD_HOST_IRQ BOARD_SDHC_IRQ + +/* define for card bus speed/strength cnofig */ +#define CARD_BUS_FREQ_50MHZ (0U) +#define CARD_BUS_FREQ_100MHZ0 (0U) +#define CARD_BUS_FREQ_100MHZ1 (0U) +#define CARD_BUS_FREQ_200MHZ (0U) + +#define CARD_BUS_STRENGTH_0 (0U) +#define CARD_BUS_STRENGTH_1 (0U) +#define CARD_BUS_STRENGTH_2 (0U) +#define CARD_BUS_STRENGTH_3 (0U) +#define CARD_BUS_STRENGTH_4 (0U) +#define CARD_BUS_STRENGTH_5 (0U) +#define CARD_BUS_STRENGTH_6 (0U) +#define CARD_BUS_STRENGTH_7 (0U) + +#define HOST_TYPE SDHC_Type +#define HOST_CONFIG sdhc_host_t +#define HOST_TRANSFER sdhc_transfer_t +#define HOST_COMMAND sdhc_command_t +#define HOST_DATA sdhc_data_t +#define HOST_BUS_WIDTH_TYPE sdhc_data_bus_width_t +#define HOST_CAPABILITY sdhc_capability_t + +#define CARD_DATA0_STATUS_MASK kSDHC_Data0LineLevelFlag +#define CARD_DATA0_NOT_BUSY kSDHC_Data0LineLevelFlag +#define CARD_DATA1_STATUS_MASK kSDHC_Data1LineLevelFlag +#define CARD_DATA2_STATUS_MASK kSDHC_Data2LineLevelFlag +#define CARD_DATA3_STATUS_MASK kSDHC_Data3LineLevelFlag + +#define kHOST_DATABUSWIDTH1BIT kSDHC_DataBusWidth1Bit /*!< 1-bit mode */ +#define kHOST_DATABUSWIDTH4BIT kSDHC_DataBusWidth4Bit /*!< 4-bit mode */ +#define kHOST_DATABUSWIDTH8BIT kSDHC_DataBusWidth8Bit /*!< 8-bit mode */ + +#define HOST_STANDARD_TUNING_START (0U) /*!< standard tuning start point */ +#define HOST_TUINIG_STEP (1U) /*!< standard tuning step */ +#define HOST_RETUNING_TIMER_COUNT (4U) /*!< Re-tuning timer */ +#define HOST_TUNING_DELAY_MAX (0x7FU) +#define HOST_RETUNING_REQUEST (1U) +#define HOST_TUNING_ERROR (2U) + +/* function pointer define */ +#define HOST_TRANSFER_FUNCTION sdhc_transfer_function_t +#define GET_HOST_CAPABILITY(base, capability) (SDHC_GetCapability(base, capability)) +#define GET_HOST_STATUS(base) (SDHC_GetPresentStatusFlags(base)) +#define HOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (SDHC_SetSdClock(base, sourceClock_HZ, busClock_HZ)) +#define HOST_SET_CARD_BUS_WIDTH(base, busWidth) (SDHC_SetDataBusWidth(base, busWidth)) +#define HOST_SEND_CARD_ACTIVE(base, timeout) (SDHC_SetCardActive(base, timeout)) +#define HOST_SWITCH_VOLTAGE180V(base, enable18v) +#define HOST_SWITCH_VOLTAGE120V(base, enable12v) +#define HOST_CONFIG_IO_STRENGTH(speed, strength) +#define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) +#define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U) +#define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U) +#define HOST_CONFIG_SD_IO(speed, strength) +#define HOST_CONFIG_MMC_IO(speed, strength) +#define HOST_ENABLE_DDR_MODE(base, flag) +#define HOST_FORCE_SDCLOCK_ON(base, enable) +#define HOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) +#define HOST_ADJUST_MANUAL_TUNING_DELAY(base, delay) +#define HOST_AUTO_MANUAL_TUNING_ENABLE(base, flag) +#define HOST_ENABLE_CARD_CLOCK(base, enable) (SDHC_EnableSdClock(base, enable)) +#define HOST_RESET_TUNING(base, timeout) +#define HOST_CHECK_TUNING_ERROR(base) (0U) +#define HOST_ADJUST_TUNING_DELAY(base, delay) +#define HOST_AUTO_STANDARD_RETUNING_TIMER(base) + +#define HOST_ENABLE_HS400_MODE(base, flag) +#define HOST_RESET_STROBE_DLL(base) +#define HOST_ENABLE_STROBE_DLL(base, flag) +#define HOST_CONFIG_STROBE_DLL(base, delay, updateInterval) +#define HOST_GET_STROBE_DLL_STATUS(base) +/* sd card power */ +#define HOST_INIT_SD_POWER() +#define HOST_ENABLE_SD_POWER(enable) +#define HOST_SWITCH_VCC_TO_180V() +#define HOST_SWITCH_VCC_TO_330V() +/* mmc card power */ +#define HOST_INIT_MMC_POWER() +#define HOST_ENABLE_MMC_POWER(enable) +#define HOST_ENABLE_TUNING_FLAG(data) +#define HOST_CARD_DETECT_INTERRUPT_HANDLER BOARD_SDHC_CD_PORT_IRQ_HANDLER +#define HOST_CARD_DETECT_IRQ BOARD_SDHC_CD_PORT_IRQ + +/*! @brief SDHC host capability*/ +enum _host_capability +{ + kHOST_SupportAdma = kSDHC_SupportAdmaFlag, + kHOST_SupportHighSpeed = kSDHC_SupportHighSpeedFlag, + kHOST_SupportDma = kSDHC_SupportDmaFlag, + kHOST_SupportSuspendResume = kSDHC_SupportSuspendResumeFlag, + kHOST_SupportV330 = kSDHC_SupportV330Flag, + kHOST_SupportV300 = HOST_NOT_SUPPORT, + kHOST_SupportV180 = HOST_NOT_SUPPORT, + kHOST_SupportV120 = HOST_NOT_SUPPORT, + kHOST_Support4BitBusWidth = kSDHC_Support4BitFlag, + kHOST_Support8BitBusWidth = kSDHC_Support8BitFlag, + kHOST_SupportDDR50 = HOST_NOT_SUPPORT, + kHOST_SupportSDR104 = HOST_NOT_SUPPORT, + kHOST_SupportSDR50 = HOST_NOT_SUPPORT, + kHOST_SupportHS200 = HOST_NOT_SUPPORT, + kHOST_SupportHS400 = HOST_NOT_SUPPORT, + +}; + +/* Endian mode. */ +#define SDHC_ENDIAN_MODE kSDHC_EndianModeLittle + +/* DMA mode */ +#define SDHC_DMA_MODE kSDHC_DmaModeAdma2 +/* address align */ +#define HOST_DMA_BUFFER_ADDR_ALIGN (SDHC_ADMA2_ADDRESS_ALIGN) + +/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */ +#define SDHC_READ_WATERMARK_LEVEL (0x80U) +#define SDHC_WRITE_WATERMARK_LEVEL (0x80U) + +/* ADMA table length united as word. + * + * SD card driver can't support ADMA1 transfer mode currently. + * One ADMA2 table item occupy two words which can transfer maximum 0xFFFFU bytes one time. + * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. + */ +#define SDHC_ADMA_TABLE_WORDS (8U) + +#elif defined(FSL_FEATURE_SOC_SDIF_COUNT) && FSL_FEATURE_SOC_SDIF_COUNT > 0U + +/* SDR104 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ +#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ +#else +#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ +#endif +/* HS200 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ +#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 +#else +#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 +#endif +/* HS400 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ +#define HOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ /* host do not support HS400 */ +#else +#define HOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400 +#endif + +/*define host baseaddr ,clk freq, IRQ number*/ +#define MMC_HOST_BASEADDR BOARD_SDIF_BASEADDR +#define MMC_HOST_CLK_FREQ BOARD_SDIF_CLK_FREQ +#define MMC_HOST_IRQ BOARD_SDIF_IRQ +#define SD_HOST_BASEADDR BOARD_SDIF_BASEADDR +#define SD_HOST_CLK_FREQ BOARD_SDIF_CLK_FREQ +#define SD_HOST_IRQ BOARD_SDIF_IRQ + +/* define for card bus speed/strength cnofig */ +#define CARD_BUS_FREQ_50MHZ (0U) +#define CARD_BUS_FREQ_100MHZ0 (0U) +#define CARD_BUS_FREQ_100MHZ1 (0U) +#define CARD_BUS_FREQ_200MHZ (0U) + +#define CARD_BUS_STRENGTH_0 (0U) +#define CARD_BUS_STRENGTH_1 (0U) +#define CARD_BUS_STRENGTH_2 (0U) +#define CARD_BUS_STRENGTH_3 (0U) +#define CARD_BUS_STRENGTH_4 (0U) +#define CARD_BUS_STRENGTH_5 (0U) +#define CARD_BUS_STRENGTH_6 (0U) +#define CARD_BUS_STRENGTH_7 (0U) + +#define HOST_TYPE SDIF_Type +#define HOST_CONFIG sdif_host_t +#define HOST_TRANSFER sdif_transfer_t +#define HOST_COMMAND sdif_command_t +#define HOST_DATA sdif_data_t +#define HOST_BUS_WIDTH_TYPE sdif_bus_width_t +#define HOST_CAPABILITY sdif_capability_t + +#define CARD_DATA0_STATUS_MASK SDIF_STATUS_DATA_BUSY_MASK +#define CARD_DATA0_NOT_BUSY 0U + +#define CARD_DATA1_STATUS_MASK (0U) +#define CARD_DATA2_STATUS_MASK (0U) +#define CARD_DATA3_STATUS_MASK (0U) + +#define kHOST_DATABUSWIDTH1BIT kSDIF_Bus1BitWidth /*!< 1-bit mode */ +#define kHOST_DATABUSWIDTH4BIT kSDIF_Bus4BitWidth /*!< 4-bit mode */ +#define kHOST_DATABUSWIDTH8BIT kSDIF_Bus8BitWidth /*!< 8-bit mode */ + +#define HOST_STANDARD_TUNING_START (0U) /*!< standard tuning start point */ +#define HOST_TUINIG_STEP (1U) /*!< standard tuning step */ +#define HOST_RETUNING_TIMER_COUNT (4U) /*!< Re-tuning timer */ +#define HOST_TUNING_DELAY_MAX (0x7FU) +#define HOST_RETUNING_REQUEST (1U) +#define HOST_TUNING_ERROR (2U) +/* function pointer define */ +#define HOST_TRANSFER_FUNCTION sdif_transfer_function_t +#define GET_HOST_CAPABILITY(base, capability) (SDIF_GetCapability(base, capability)) +#define GET_HOST_STATUS(base) (SDIF_GetControllerStatus(base)) +#define HOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (SDIF_SetCardClock(base, sourceClock_HZ, busClock_HZ)) +#define HOST_SET_CARD_BUS_WIDTH(base, busWidth) (SDIF_SetCardBusWidth(base, busWidth)) +#define HOST_SEND_CARD_ACTIVE(base, timeout) (SDIF_SendCardActive(base, timeout)) +#define HOST_SWITCH_VOLTAGE180V(base, enable18v) +#define HOST_SWITCH_VOLTAGE120V(base, enable12v) +#define HOST_CONFIG_IO_STRENGTH(speed, strength) +#define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) +#define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U) +#define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U) +#define HOST_CONFIG_SD_IO(speed, strength) +#define HOST_CONFIG_MMC_IO(speed, strength) +#define HOST_ENABLE_DDR_MODE(base, flag) +#define HOST_FORCE_SDCLOCK_ON(base, enable) +#define HOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) +#define HOST_ADJUST_MANUAL_TUNING_DELAY(base, delay) +#define HOST_AUTO_MANUAL_TUNING_ENABLE(base, flag) +#define HOST_ENABLE_CARD_CLOCK(base, enable) (SDIF_EnableCardClock(base, enable)) +#define HOST_RESET_TUNING(base, timeout) +#define HOST_CHECK_TUNING_ERROR(base) (0U) +#define HOST_ADJUST_TUNING_DELAY(base, delay) +#define HOST_AUTO_STANDARD_RETUNING_TIMER(base) + +#define HOST_ENABLE_HS400_MODE(base, flag) +#define HOST_RESET_STROBE_DLL(base) +#define HOST_ENABLE_STROBE_DLL(base, flag) +#define HOST_CONFIG_STROBE_DLL(base, delay, updateInterval) +#define HOST_GET_STROBE_DLL_STATUS(base) +/* sd card power */ +#define HOST_INIT_SD_POWER() +#define HOST_ENABLE_SD_POWER(enable) +#define HOST_SWITCH_VCC_TO_180V() +#define HOST_SWITCH_VCC_TO_330V() +/* mmc card power */ +#define HOST_INIT_MMC_POWER() +#define HOST_ENABLE_MMC_POWER(enable) +#define HOST_ENABLE_TUNING_FLAG(data) +/*! @brief SDIF host capability*/ +enum _host_capability +{ + kHOST_SupportHighSpeed = kSDIF_SupportHighSpeedFlag, + kHOST_SupportDma = kSDIF_SupportDmaFlag, + kHOST_SupportSuspendResume = kSDIF_SupportSuspendResumeFlag, + kHOST_SupportV330 = kSDIF_SupportV330Flag, + kHOST_SupportV300 = HOST_NOT_SUPPORT, + kHOST_SupportV180 = HOST_NOT_SUPPORT, + kHOST_SupportV120 = HOST_NOT_SUPPORT, + kHOST_Support4BitBusWidth = kSDIF_Support4BitFlag, + kHOST_Support8BitBusWidth = HOST_NOT_SUPPORT, /* mask the 8 bit here,user can change depend on your board */ + kHOST_SupportDDR50 = HOST_NOT_SUPPORT, + kHOST_SupportSDR104 = HOST_NOT_SUPPORT, + kHOST_SupportSDR50 = HOST_NOT_SUPPORT, + kHOST_SupportHS200 = HOST_NOT_SUPPORT, + kHOST_SupportHS400 = HOST_NOT_SUPPORT, + +}; + +/*! @brief DMA table length united as word + * One dma table item occupy four words which can transfer maximum 2*8188 bytes in dual DMA mode + * and 8188 bytes in chain mode + * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. + * user need check the DMA descriptor table lenght if bigger enough. + */ +#define SDIF_DMA_TABLE_WORDS (0x40U) +/* address align */ +#define HOST_DMA_BUFFER_ADDR_ALIGN (4U) + +#elif defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT > 0U +/* SDR104 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ +#define HOST_SUPPORT_SDR104_FREQ BOARD_SD_HOST_SUPPORT_SDR104_FREQ +#else +#define HOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ +#endif +/* HS200 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ +#define HOST_SUPPORT_HS200_FREQ BOARD_SD_HOST_SUPPORT_HS200_FREQ +#else +#define HOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 +#endif +/* HS400 mode freq */ +#if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ +#define HOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ +#else +#define HOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400 +#endif + +/*define host baseaddr ,clk freq, IRQ number*/ +#define MMC_HOST_BASEADDR BOARD_MMC_HOST_BASEADDR +#define MMC_HOST_CLK_FREQ BOARD_MMC_HOST_CLK_FREQ +#define MMC_HOST_IRQ BOARD_MMC_HOST_IRQ +#define SD_HOST_BASEADDR BOARD_SD_HOST_BASEADDR +#define SD_HOST_CLK_FREQ BOARD_SD_HOST_CLK_FREQ +#define SD_HOST_IRQ BOARD_SD_HOST_IRQ + +#define HOST_TYPE USDHC_Type +#define HOST_CONFIG usdhc_host_t +#define HOST_TRANSFER usdhc_transfer_t +#define HOST_COMMAND usdhc_command_t +#define HOST_DATA usdhc_data_t + +#define CARD_DATA0_STATUS_MASK kUSDHC_Data0LineLevelFlag +#define CARD_DATA1_STATUS_MASK kUSDHC_Data1LineLevelFlag +#define CARD_DATA2_STATUS_MASK kUSDHC_Data2LineLevelFlag +#define CARD_DATA3_STATUS_MASK kUSDHC_Data3LineLevelFlag +#define CARD_DATA0_NOT_BUSY kUSDHC_Data0LineLevelFlag + +#define HOST_BUS_WIDTH_TYPE usdhc_data_bus_width_t +#define HOST_CAPABILITY usdhc_capability_t + +#define kHOST_DATABUSWIDTH1BIT kUSDHC_DataBusWidth1Bit /*!< 1-bit mode */ +#define kHOST_DATABUSWIDTH4BIT kUSDHC_DataBusWidth4Bit /*!< 4-bit mode */ +#define kHOST_DATABUSWIDTH8BIT kUSDHC_DataBusWidth8Bit /*!< 8-bit mode */ + +#define HOST_STANDARD_TUNING_START (10U) /*!< standard tuning start point */ +#define HOST_TUINIG_STEP (2U) /*!< standard tuning step */ +#define HOST_RETUNING_TIMER_COUNT (0U) /*!< Re-tuning timer */ +#define HOST_TUNING_DELAY_MAX (0x7FU) +#define HOST_RETUNING_REQUEST kStatus_USDHC_ReTuningRequest +#define HOST_TUNING_ERROR kStatus_USDHC_TuningError +/* define for card bus speed/strength cnofig */ +#define CARD_BUS_FREQ_50MHZ (0U) +#define CARD_BUS_FREQ_100MHZ0 (1U) +#define CARD_BUS_FREQ_100MHZ1 (2U) +#define CARD_BUS_FREQ_200MHZ (3U) + +#define CARD_BUS_STRENGTH_0 (0U) +#define CARD_BUS_STRENGTH_1 (1U) +#define CARD_BUS_STRENGTH_2 (2U) +#define CARD_BUS_STRENGTH_3 (3U) +#define CARD_BUS_STRENGTH_4 (4U) +#define CARD_BUS_STRENGTH_5 (5U) +#define CARD_BUS_STRENGTH_6 (6U) +#define CARD_BUS_STRENGTH_7 (7U) + +#define HOST_STROBE_DLL_DELAY_TARGET (7U) +#define HOST_STROBE_DLL_DELAY_UPDATE_INTERVAL (4U) + +/* function pointer define */ +#define HOST_TRANSFER_FUNCTION usdhc_transfer_function_t +#define GET_HOST_CAPABILITY(base, capability) (USDHC_GetCapability(base, capability)) +#define GET_HOST_STATUS(base) (USDHC_GetPresentStatusFlags(base)) +#define HOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (USDHC_SetSdClock(base, sourceClock_HZ, busClock_HZ)) +#define HOST_ENABLE_CARD_CLOCK(base, enable) +#define HOST_FORCE_SDCLOCK_ON(base, enable) (USDHC_ForceClockOn(base, enable)) +#define HOST_SET_CARD_BUS_WIDTH(base, busWidth) (USDHC_SetDataBusWidth(base, busWidth)) +#define HOST_SEND_CARD_ACTIVE(base, timeout) (USDHC_SetCardActive(base, timeout)) +#define HOST_SWITCH_VOLTAGE180V(base, enable18v) (UDSHC_SelectVoltage(base, enable18v)) +#define HOST_SWITCH_VOLTAGE120V(base, enable12v) +#define HOST_CONFIG_SD_IO(speed, strength) BOARD_SD_PIN_CONFIG(speed, strength) +#define HOST_CONFIG_MMC_IO(speed, strength) BOARD_MMC_PIN_CONFIG(speed, strength) +#define HOST_SWITCH_VCC_TO_180V() +#define HOST_SWITCH_VCC_TO_330V() + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) +#define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U) +#define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U) +#define HOST_AUTO_STANDARD_RETUNING_TIMER(base) +#define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) +#define HOST_CHECK_TUNING_ERROR(base) (0U) +#define HOST_ADJUST_TUNING_DELAY(base, delay) +#else +#define HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) \ + (USDHC_EnableStandardTuning(base, HOST_STANDARD_TUNING_START, HOST_TUINIG_STEP, flag)) +#define HOST_EXECUTE_STANDARD_TUNING_STATUS(base) (USDHC_GetExecuteStdTuningStatus(base)) +#define HOST_EXECUTE_STANDARD_TUNING_RESULT(base) (USDHC_CheckStdTuningResult(base)) +#define HOST_AUTO_STANDARD_RETUNING_TIMER(base) (USDHC_SetRetuningTimer(base, HOST_RETUNING_TIMER_COUNT)) +#define HOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) (USDHC_EnableManualTuning(base, flag)) +#define HOST_ADJUST_TUNING_DELAY(base, delay) (USDHC_AdjustDelayForManualTuning(base, delay)) +#define HOST_AUTO_TUNING_ENABLE(base, flag) (USDHC_EnableAutoTuning(base, flag)) +#define HOST_CHECK_TUNING_ERROR(base) (USDHC_CheckTuningError(base)) +#endif + +#define HOST_AUTO_TUNING_CONFIG(base) (USDHC_EnableAutoTuningForCmdAndData(base)) +#define HOST_RESET_TUNING(base, timeout) \ + { \ + (USDHC_Reset(base, kUSDHC_ResetTuning | kUSDHC_ResetData | kUSDHC_ResetCommand, timeout)); \ + } + +#define HOST_ENABLE_DDR_MODE(base, flag) (USDHC_EnableDDRMode(base, flag, 1U)) + +#if FSL_FEATURE_USDHC_HAS_HS400_MODE +#define HOST_ENABLE_HS400_MODE(base, flag) (USDHC_EnableHS400Mode(base, flag)) +#define HOST_RESET_STROBE_DLL(base) (USDHC_ResetStrobeDLL(base)) +#define HOST_ENABLE_STROBE_DLL(base, flag) (USDHC_EnableStrobeDLL(base, flag)) +#define HOST_CONFIG_STROBE_DLL(base, delay, updateInterval) (USDHC_ConfigStrobeDLL(base, delay, updateInterval)) +#define HOST_GET_STROBE_DLL_STATUS (base)(USDHC_GetStrobeDLLStatus(base)) +#else +#define HOST_ENABLE_HS400_MODE(base, flag) +#define HOST_RESET_STROBE_DLL(base) +#define HOST_ENABLE_STROBE_DLL(base, flag) +#define HOST_CONFIG_STROBE_DLL(base, delay, updateInterval) +#define HOST_GET_STROBE_DLL_STATUS(base) +#endif + +/* sd card power */ +#define HOST_INIT_SD_POWER() BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() +#define HOST_ENABLE_SD_POWER(enable) BOARD_USDHC_SDCARD_POWER_CONTROL(enable) +/* mmc card power */ +#define HOST_INIT_MMC_POWER() BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() +#define HOST_ENABLE_MMC_POWER(enable) BOARD_USDHC_MMCCARD_POWER_CONTROL(enable) +/* sd card detect */ +#define HOST_CARD_DETECT_STATUS() BOARD_USDHC_CD_STATUS() +#define HOST_CARD_DETECT_INIT() BOARD_USDHC_CD_GPIO_INIT() +#define HOST_CARD_DETECT_INTERRUPT_STATUS() BOARD_USDHC_CD_INTERRUPT_STATUS() +#define HOST_CARD_DETECT_INTERRUPT_CLEAR(flag) BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) +#define HOST_CARD_DETECT_INTERRUPT_HANDLER BOARD_USDHC_CD_PORT_IRQ_HANDLER +#define HOST_CARD_DETECT_IRQ BOARD_USDHC_CD_PORT_IRQ +/* define card detect pin voltage level when card inserted */ +#if defined BOARD_USDHC_CARD_INSERT_CD_LEVEL +#define HOST_CARD_INSERT_CD_LEVEL BOARD_USDHC_CARD_INSERT_CD_LEVEL +#else +#define HOST_CARD_INSERT_CD_LEVEL (0U) +#endif +#define HOST_ENABLE_TUNING_FLAG(data) (data.executeTuning = true) +/*! @brief USDHC host capability*/ +enum _host_capability +{ + kHOST_SupportAdma = kUSDHC_SupportAdmaFlag, + kHOST_SupportHighSpeed = kUSDHC_SupportHighSpeedFlag, + kHOST_SupportDma = kUSDHC_SupportDmaFlag, + kHOST_SupportSuspendResume = kUSDHC_SupportSuspendResumeFlag, + kHOST_SupportV330 = kUSDHC_SupportV330Flag, /* this define should depend on your board config */ + kHOST_SupportV300 = kUSDHC_SupportV300Flag, /* this define should depend on your board config */ +#if defined(BOARD_SD_SUPPORT_180V) && !BOARD_SD_SUPPORT_180V + kHOST_SupportV180 = HOST_NOT_SUPPORT, /* this define should depend on you board config */ +#else + kHOST_SupportV180 = kUSDHC_SupportV180Flag, /* this define should depend on you board config */ +#endif + kHOST_SupportV120 = HOST_NOT_SUPPORT, + kHOST_Support4BitBusWidth = kUSDHC_Support4BitFlag, +#if defined(BOARD_MMC_SUPPORT_8BIT_BUS) +#if BOARD_MMC_SUPPORT_8BIT_BUS + kHOST_Support8BitBusWidth = kUSDHC_Support8BitFlag, +#else + kHOST_Support8BitBusWidth = HOST_NOT_SUPPORT, +#endif +#else + kHOST_Support8BitBusWidth = kUSDHC_Support8BitFlag, +#endif + kHOST_SupportDDR50 = kUSDHC_SupportDDR50Flag, + kHOST_SupportSDR104 = kUSDHC_SupportSDR104Flag, + kHOST_SupportSDR50 = kUSDHC_SupportSDR50Flag, + kHOST_SupportHS200 = kUSDHC_SupportSDR104Flag, +#if FSL_FEATURE_USDHC_HAS_HS400_MODE + kHOST_SupportHS400 = HOST_SUPPORT +#else + kHOST_SupportHS400 = HOST_NOT_SUPPORT, +#endif +}; + +/* Endian mode. */ +#define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle + +/* DMA mode */ +#define USDHC_DMA_MODE kUSDHC_DmaModeAdma2 +/* address align */ +#define HOST_DMA_BUFFER_ADDR_ALIGN (USDHC_ADMA2_ADDRESS_ALIGN) + +/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */ +#define USDHC_READ_WATERMARK_LEVEL (0x80U) +#define USDHC_WRITE_WATERMARK_LEVEL (0x80U) + +/* ADMA table length united as word. + * + * One ADMA2 table item occupy two words which can transfer maximum 0xFFFFU bytes one time. + * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. + */ +#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */ +#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ +#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */ +#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */ +#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */ + +#endif + +/*! @brief host Endian mode +* corresponding to driver define +*/ +enum _host_endian_mode +{ + kHOST_EndianModeBig = 0U, /*!< Big endian mode */ + kHOST_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ + kHOST_EndianModeLittle = 2U, /*!< Little endian mode */ +}; + +#define EVENT_TIMEOUT_TRANSFER_COMPLETE (1000U) +#define EVENT_TIMEOUT_CARD_DETECT (~0U) + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name adaptor function + * @{ + */ + +/*! + * @brief host not support function, this function is used for host not support feature + * @param void parameter ,used to avoid build warning + * @retval kStatus_Fail ,host do not suppport + */ +static inline status_t HOST_NotSupport(void *parameter) +{ + parameter = parameter; + return kStatus_Success; +} + +/*! + * @brief Detect card insert, only need for SD cases. + * @param hostBase the pointer to host base address + * @retval kStatus_Success detect card insert + * @retval kStatus_Fail card insert event fail + */ +status_t CardInsertDetect(HOST_TYPE *hostBase); + +/*! + * @brief Init host controller. + * @param host the pointer to host structure in card structure. + * @retval kStatus_Success host init success + * @retval kStatus_Fail event fail + */ +status_t HOST_Init(void *host); + +/*! + * @brief reset host controller. + * @param host base address. + */ +void HOST_Reset(HOST_TYPE *hostBase); + +/*! + * @brief Deinit host controller. + * @param host the pointer to host structure in card structure. + */ +void HOST_Deinit(void *host); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +#endif diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sd.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sd.c new file mode 100644 index 0000000000..8cac2ffc51 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sd.c @@ -0,0 +1,1688 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_card.h" +#include "fsl_sdmmc.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Send SELECT_CARD command to set the card to be transfer state or not. + * + * @param card Card descriptor. + * @param isSelected True to set the card into transfer state. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline SD_SelectCard(sd_card_t *card, bool isSelected); + +/*! + * @brief Wait write process complete. + * + * @param card Card descriptor. + * @retval kStatus_Timeout Send command timeout. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_WaitWriteComplete(sd_card_t *card); + +/*! + * @brief Send SEND_APPLICATION_COMMAND command. + * + * @param card Card descriptor. + * @param relativeaddress + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline SD_SendApplicationCmd(sd_card_t *card, uint32_t relativeAddress); + +/*! + * @brief Send GO_IDLE command to set the card to be idle state. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline SD_GoIdle(sd_card_t *card); + +/*! + * @brief Send STOP_TRANSMISSION command after multiple blocks read/write. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_StopTransmission(sd_card_t *card); + +/*! + * @brief Send SET_BLOCK_SIZE command. + * + * @param card Card descriptor. + * @param blockSize Block size. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t inline SD_SetBlockSize(sd_card_t *card, uint32_t blockSize); + +/*! + * @brief Send GET_RCA command to get card relative address. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendRca(sd_card_t *card); + +/*! + * @brief Send SWITCH_FUNCTION command to switch the card function group. + * + * @param card Card descriptor. + * @param mode 0 to check function group. 1 to switch function group + * @param group Function group + * @param number Function number in the function group. + * @param status Switch function status. + * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SwitchFunction(sd_card_t *card, uint32_t mode, uint32_t group, uint32_t number, uint32_t *status); + +/*! + * @brief Decode raw SCR register content in the data blocks. + * + * @param card Card descriptor. + * @param rawScr Raw SCR register content. + */ +static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr); + +/*! + * @brief Send GET_SCR command. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_NotSupportYet Not support yet. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendScr(sd_card_t *card); + +/*! + * @brief Switch the card to be high speed mode. + * + * @param card Card descriptor. + * @param group Group number. + * @param functio Function number. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_SwitchFailed Switch failed. + * @retval kStatus_SDMMC_NotSupportYet Not support yet. + * @retval kStatus_Fail Switch failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SelectFunction(sd_card_t *card, uint32_t group, uint32_t function); + +/*! + * @brief Send SET_DATA_WIDTH command to set SD bus width. + * + * @param card Card descriptor. + * @param width Data bus width. + * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SetDataBusWidth(sd_card_t *card, sd_data_bus_width_t width); + +/*! + * @brief Decode raw CSD register content in the data blocks. + * + * @param card Card descriptor. + * @param rawCsd Raw CSD register content. + */ +static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd); + +/*! + * @brief Send SEND_CSD command to get CSD register content from Card. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendCsd(sd_card_t *card); + +/*! + * @brief Decode raw CID register content in the data blocks. + * + * @param rawCid raw CID register content. + * @param card Card descriptor. + */ +static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid); + +/*! + * @brief Send GET_CID command to get CID from card. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_AllSendCid(sd_card_t *card); + +/*! + * @brief Send SEND_OPERATION_CONDITION command. + * + * This function sends host capacity support information and asks the accessed card to send its operating condition + * register content. + * + * @param card Card descriptor. + * @param argument The argument of the send operation condition ncomamnd. + * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Timeout Timeout. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument); + +/*! + * @brief Send GET_INTERFACE_CONDITION command to get card interface condition. + * + * This function checks card interface condition, which includes host supply voltage information and asks the card + * whether card supports the specified host voltage. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendInterfaceCondition(sd_card_t *card); + +/*! + * @brief Send switch voltage command + * switch card voltage to 1.8v + * + * @param card Card descriptor. + */ +static status_t SD_SwitchVoltage(sd_card_t *card); + +/*! + * @brief select bus timing + * select card timing + * @param card Card descriptor. + */ +static status_t SD_SelectBusTiming(sd_card_t *card); + +/*! + * @brief select card driver strength + * select card driver strength + * @param card Card descriptor. + * @param driverStrength Driver strength + */ +static status_t SD_SetDriverStrength(sd_card_t *card, sd_driver_strength_t driverStrength); + +/*! + * @brief select max current + * select max operation current + * @param card Card descriptor. + * @param maxCurrent Max current + */ +static status_t SD_SetMaxCurrent(sd_card_t *card, sd_max_current_t maxCurrent); + +/*! + * @brief Read data from specific SD card. + * + * @param card Card descriptor. + * @param buffer Buffer to save data blocks read. + * @param startBlock Card start block number to be read. + * @param blockSize Block size. + * @param blockCount Block count. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Wait write complete failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_Read(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); + +/*! + * @brief Write data to specific card + * + * @param card Card descriptor. + * @param buffer Buffer to be sent. + * @param startBlock Card start block number to be written. + * @param blockSize Block size. + * @param blockCount Block count. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_Write( + sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); + +/*! + * @brief Erase data for the given block range. + * + * @param card Card descriptor. + * @param startBlock Card start block number to be erased. + * @param blockCount The block count to be erased. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_Erase(sd_card_t *card, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief card transfer function. + * + * @param card Card descriptor. + * @param content Transfer content. + * @param retry Retry times + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + * @retval kStatus_SDMMC_TuningFail tuning fail + */ +static status_t SD_Transfer(sd_card_t *card, HOST_TRANSFER *content, uint32_t retry); + +/*! + * @brief card execute tuning function. + * + * @param card Card descriptor. + * @retval kStatus_Success Operate successfully. + * @retval kStatus_SDMMC_TuningFail tuning fail. + * @retval kStatus_SDMMC_TransferFailed transfer fail + */ +static status_t inline SD_ExecuteTuning(sd_card_t *card); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* g_sdmmc statement */ +extern uint32_t g_sdmmc[SDK_SIZEALIGN(SDMMC_GLOBAL_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CAHCE)]; +/******************************************************************************* + * Code + ******************************************************************************/ +static status_t inline SD_SelectCard(sd_card_t *card, bool isSelected) +{ + assert(card); + + return SDMMC_SelectCard(card->host.base, card->host.transfer, card->relativeAddress, isSelected); +} + +static status_t inline SD_SendApplicationCmd(sd_card_t *card, uint32_t relativeAddress) +{ + assert(card); + + return SDMMC_SendApplicationCommand(card->host.base, card->host.transfer, relativeAddress); +} + +static status_t inline SD_GoIdle(sd_card_t *card) +{ + assert(card); + + return SDMMC_GoIdle(card->host.base, card->host.transfer); +} + +static status_t inline SD_SetBlockSize(sd_card_t *card, uint32_t blockSize) +{ + assert(card); + + return SDMMC_SetBlockSize(card->host.base, card->host.transfer, blockSize); +} + +static status_t inline SD_ExecuteTuning(sd_card_t *card) +{ + assert(card); + + return SDMMC_ExecuteTuning(card->host.base, card->host.transfer, kSD_SendTuningBlock, 64U); +} + +static status_t SD_SwitchVoltage(sd_card_t *card) +{ + assert(card); + + return SDMMC_SwitchVoltage(card->host.base, card->host.transfer); +} + +static status_t SD_Transfer(sd_card_t *card, HOST_TRANSFER *content, uint32_t retry) +{ + assert(card->host.transfer); + assert(content); + status_t error; + + do + { + error = card->host.transfer(card->host.base, content); + if (((error == HOST_RETUNING_REQUEST) || (error == HOST_TUNING_ERROR) || + (content->command->response[0U] & kSDMMC_R1ErrorAllFlag)) && + ((card->currentTiming == kSD_TimingSDR104Mode) || (card->currentTiming == kSD_TimingSDR50Mode))) + { + /* tuning error need reset tuning circuit */ + if (error == HOST_TUNING_ERROR) + { + HOST_RESET_TUNING(card->host.base, 100U); + } + + /* execute re-tuning */ + if (SD_ExecuteTuning(card) != kStatus_Success) + { + error = kStatus_SDMMC_TuningFail; + } + else + { + continue; + } + } + else if (error != kStatus_Success) + { + error = kStatus_SDMMC_TransferFailed; + } + + if (retry != 0U) + { + retry--; + } + else + { + break; + } + + } while ((error != kStatus_Success) && (error != kStatus_SDMMC_TuningFail)); + + return error; +} + +static status_t SD_WaitWriteComplete(sd_card_t *card) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_SendStatus; + command.argument = card->relativeAddress << 16U; + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; + + do + { + content.command = &command; + content.data = 0U; + if (kStatus_Success != SD_Transfer(card, &content, 2U)) + { + return kStatus_SDMMC_TransferFailed; + } + + if ((command.response[0U] & kSDMMC_R1ReadyForDataFlag) && + (SDMMC_R1_CURRENT_STATE(command.response[0U]) != kSDMMC_R1StateProgram)) + { + break; + } + } while (true); + + return kStatus_Success; +} + +static status_t SD_StopTransmission(sd_card_t *card) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_StopTransmission; + command.argument = 0U; + command.type = kCARD_CommandTypeAbort; + command.responseType = kCARD_ResponseTypeR1b; + command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; + + content.command = &command; + content.data = 0U; + if (kStatus_Success != SD_Transfer(card, &content, 1U)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static status_t SD_SendRca(sd_card_t *card) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSD_SendRelativeAddress; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR6; + + content.command = &command; + content.data = NULL; + if (kStatus_Success == card->host.transfer(card->host.base, &content)) + { + card->relativeAddress = (command.response[0U] >> 16U); + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static status_t SD_SwitchFunction(sd_card_t *card, uint32_t mode, uint32_t group, uint32_t number, uint32_t *status) +{ + assert(card); + assert(status); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + HOST_DATA data = {0}; + + command.index = kSD_Switch; + command.argument = (mode << 31U | 0x00FFFFFFU); + command.argument &= ~((uint32_t)(0xFU) << (group * 4U)); + command.argument |= (number << (group * 4U)); + command.responseType = kCARD_ResponseTypeR1; + + data.blockSize = 64U; + data.blockCount = 1U; + data.rxData = status; + + if (kStatus_Success != SD_SetBlockSize(card, data.blockSize)) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + content.command = &command; + content.data = &data; + if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || + ((command.response[0U]) & kSDMMC_R1ErrorAllFlag)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr) +{ + assert(card); + assert(rawScr); + + sd_scr_t *scr; + + scr = &(card->scr); + scr->scrStructure = (uint8_t)((rawScr[0U] & 0xF0000000U) >> 28U); + scr->sdSpecification = (uint8_t)((rawScr[0U] & 0xF000000U) >> 24U); + if ((uint8_t)((rawScr[0U] & 0x800000U) >> 23U)) + { + scr->flags |= kSD_ScrDataStatusAfterErase; + } + scr->sdSecurity = (uint8_t)((rawScr[0U] & 0x700000U) >> 20U); + scr->sdBusWidths = (uint8_t)((rawScr[0U] & 0xF0000U) >> 16U); + if ((uint8_t)((rawScr[0U] & 0x8000U) >> 15U)) + { + scr->flags |= kSD_ScrSdSpecification3; + } + scr->extendedSecurity = (uint8_t)((rawScr[0U] & 0x7800U) >> 10U); + scr->commandSupport = (uint8_t)(rawScr[0U] & 0x3U); + scr->reservedForManufacturer = rawScr[1U]; + /* Get specification version. */ + switch (scr->sdSpecification) + { + case 0U: + card->version = kSD_SpecificationVersion1_0; + break; + case 1U: + card->version = kSD_SpecificationVersion1_1; + break; + case 2U: + card->version = kSD_SpecificationVersion2_0; + if (card->scr.flags & kSD_ScrSdSpecification3) + { + card->version = kSD_SpecificationVersion3_0; + } + break; + default: + break; + } + if (card->scr.sdBusWidths & 0x4U) + { + card->flags |= kSD_Support4BitWidthFlag; + } + /* speed class control cmd */ + if (card->scr.commandSupport & 0x01U) + { + card->flags |= kSD_SupportSpeedClassControlCmd; + } + /* set block count cmd */ + if (card->scr.commandSupport & 0x02U) + { + card->flags |= kSD_SupportSetBlockCountCmd; + } +} + +static status_t SD_SendScr(sd_card_t *card) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + HOST_DATA data = {0}; + uint32_t *rawScr = g_sdmmc; + + /* memset the global buffer */ + memset(g_sdmmc, 0U, sizeof(g_sdmmc)); + + if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) + { + return kStatus_SDMMC_SendApplicationCommandFailed; + } + + command.index = kSD_ApplicationSendScr; + command.responseType = kCARD_ResponseTypeR1; + command.argument = 0U; + + data.blockSize = 8U; + data.blockCount = 1U; + data.rxData = rawScr; + + content.data = &data; + content.command = &command; + if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || + ((command.response[0U]) & kSDMMC_R1ErrorAllFlag)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* SCR register data byte sequence from card is big endian(MSB first). */ + switch (card->host.config.endianMode) + { + case kHOST_EndianModeLittle: + /* In little endian mode, SD bus byte transferred first is the byte stored in lowest byte position in a + word which will cause 4 byte's sequence in a word is not consistent with their original sequence from + card. So the sequence of 4 bytes received in a word should be converted. */ + rawScr[0U] = SWAP_WORD_BYTE_SEQUENCE(rawScr[0U]); + rawScr[1U] = SWAP_WORD_BYTE_SEQUENCE(rawScr[1U]); + break; + case kHOST_EndianModeBig: + break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ + case kHOST_EndianModeHalfWordBig: + rawScr[0U] = SWAP_HALF_WROD_BYTE_SEQUENCE(rawScr[0U]); + rawScr[1U] = SWAP_HALF_WROD_BYTE_SEQUENCE(rawScr[1U]); + break; + default: + return kStatus_SDMMC_NotSupportYet; + } + memcpy(card->rawScr, rawScr, sizeof(card->rawScr)); + SD_DecodeScr(card, rawScr); + + return kStatus_Success; +} + +static status_t SD_SelectFunction(sd_card_t *card, uint32_t group, uint32_t function) +{ + assert(card); + + uint32_t *functionStatus = g_sdmmc; + uint16_t functionGroupInfo[6U] = {0}; + uint32_t currentFunctionStatus = 0U; + + /* memset the global buffer */ + memset(g_sdmmc, 0, sizeof(g_sdmmc)); + + /* check if card support CMD6 */ + if ((card->version < kSD_SpecificationVersion1_0) || (!(card->csd.cardCommandClass & kSDMMC_CommandClassSwitch))) + { + return kStatus_SDMMC_NotSupportYet; + } + + /* Check if card support high speed mode. */ + if (kStatus_Success != SD_SwitchFunction(card, kSD_SwitchCheck, group, function, functionStatus)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Switch function status byte sequence from card is big endian(MSB first). */ + switch (card->host.config.endianMode) + { + case kHOST_EndianModeLittle: + /* In little endian mode, SD bus byte transferred first is the byte stored in lowest byte position in + a word which will cause 4 byte's sequence in a word is not consistent with their original sequence from + card. So the sequence of 4 bytes received in a word should be converted. */ + functionStatus[0U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[0U]); + functionStatus[1U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[1U]); + functionStatus[2U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[2U]); + functionStatus[3U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[3U]); + functionStatus[4U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[4U]); + break; + case kHOST_EndianModeBig: + break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ + case kHOST_EndianModeHalfWordBig: + functionStatus[0U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[0U]); + functionStatus[1U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[1U]); + functionStatus[2U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[2U]); + functionStatus[3U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[3U]); + functionStatus[4U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[4U]); + break; + default: + return kStatus_SDMMC_NotSupportYet; + } + /* -functionStatus[0U]---bit511~bit480; + -functionStatus[1U]---bit479~bit448; + -functionStatus[2U]---bit447~bit416; + -functionStatus[3U]---bit415~bit384; + -functionStatus[4U]---bit383~bit352; + According to the "switch function status[bits 511~0]" return by switch command in mode "check function": + -Check if function 1(high speed) in function group 1 is supported by checking if bit 401 is set; + -check if function 1 is ready and can be switched by checking if bits 379~376 equal value 1; + */ + functionGroupInfo[5U] = (uint16_t)functionStatus[0U]; + functionGroupInfo[4U] = (uint16_t)(functionStatus[1U] >> 16U); + functionGroupInfo[3U] = (uint16_t)(functionStatus[1U]); + functionGroupInfo[2U] = (uint16_t)(functionStatus[2U] >> 16U); + functionGroupInfo[1U] = (uint16_t)(functionStatus[2U]); + functionGroupInfo[0U] = (uint16_t)(functionStatus[3U] >> 16U); + currentFunctionStatus = ((functionStatus[3U] & 0xFFU) << 8U) | (functionStatus[4U] >> 24U); + + /* check if function is support */ + if (((functionGroupInfo[group] & (1 << function)) == 0U) || + ((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) + { + return kStatus_SDMMC_NotSupportYet; + } + + /* Switch to high speed mode. */ + if (kStatus_Success != SD_SwitchFunction(card, kSD_SwitchSet, group, function, functionStatus)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Switch function status byte sequence from card is big endian(MSB first). */ + switch (card->host.config.endianMode) + { + case kHOST_EndianModeLittle: + /* In little endian mode is little endian, SD bus byte transferred first is the byte stored in lowest byte + position in a word which will cause 4 byte's sequence in a word is not consistent with their original + sequence from card. So the sequence of 4 bytes received in a word should be converted. */ + functionStatus[3U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[3U]); + functionStatus[4U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[4U]); + break; + case kHOST_EndianModeBig: + break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ + case kHOST_EndianModeHalfWordBig: + functionStatus[3U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[3U]); + functionStatus[4U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[4U]); + break; + default: + return kStatus_SDMMC_NotSupportYet; + } + /* According to the "switch function status[bits 511~0]" return by switch command in mode "set function": + -check if group 1 is successfully changed to function 1 by checking if bits 379~376 equal value 1; + */ + currentFunctionStatus = ((functionStatus[3U] & 0xFFU) << 8U) | (functionStatus[4U] >> 24U); + + if (((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) + { + return kStatus_SDMMC_SwitchFailed; + } + + return kStatus_Success; +} + +static status_t SD_SetDataBusWidth(sd_card_t *card, sd_data_bus_width_t width) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) + { + return kStatus_SDMMC_SendApplicationCommandFailed; + } + + command.index = kSD_ApplicationSetBusWdith; + command.responseType = kCARD_ResponseTypeR1; + switch (width) + { + case kSD_DataBusWidth1Bit: + command.argument = 0U; + break; + case kSD_DataBusWidth4Bit: + command.argument = 2U; + break; + default: + return kStatus_InvalidArgument; + } + + content.command = &command; + content.data = NULL; + if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || + ((command.response[0U]) & kSDMMC_R1ErrorAllFlag)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd) +{ + assert(card); + assert(rawCsd); + + sd_csd_t *csd; + + csd = &(card->csd); + csd->csdStructure = (uint8_t)((rawCsd[3U] & 0xC0000000U) >> 30U); + csd->dataReadAccessTime1 = (uint8_t)((rawCsd[3U] & 0xFF0000U) >> 16U); + csd->dataReadAccessTime2 = (uint8_t)((rawCsd[3U] & 0xFF00U) >> 8U); + csd->transferSpeed = (uint8_t)(rawCsd[3U] & 0xFFU); + csd->cardCommandClass = (uint16_t)((rawCsd[2U] & 0xFFF00000U) >> 20U); + csd->readBlockLength = (uint8_t)((rawCsd[2U] & 0xF0000U) >> 16U); + if (rawCsd[2U] & 0x8000U) + { + csd->flags |= kSD_CsdReadBlockPartialFlag; + } + if (rawCsd[2U] & 0x4000U) + { + csd->flags |= kSD_CsdReadBlockPartialFlag; + } + if (rawCsd[2U] & 0x2000U) + { + csd->flags |= kSD_CsdReadBlockMisalignFlag; + } + if (rawCsd[2U] & 0x1000U) + { + csd->flags |= kSD_CsdDsrImplementedFlag; + } + switch (csd->csdStructure) + { + case 0: + csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3FFU) << 2U); + csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xC0000000U) >> 30U); + csd->readCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x38000000U) >> 27U); + csd->readCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x7000000U) >> 24U); + csd->writeCurrentVddMin = (uint8_t)((rawCsd[1U] & 0xE00000U) >> 20U); + csd->writeCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x1C0000U) >> 18U); + csd->deviceSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x38000U) >> 15U); + + /* Get card total block count and block size. */ + card->blockCount = ((csd->deviceSize + 1U) << (csd->deviceSizeMultiplier + 2U)); + card->blockSize = (1U << (csd->readBlockLength)); + if (card->blockSize != FSL_SDMMC_DEFAULT_BLOCK_SIZE) + { + card->blockCount = (card->blockCount * card->blockSize); + card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; + card->blockCount = (card->blockCount / card->blockSize); + } + break; + case 1: + card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; + + csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3FU) << 16U); + csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xFFFF0000U) >> 16U); + if (csd->deviceSize >= 0xFFFFU) + { + card->flags |= kSD_SupportSdxcFlag; + } + + card->blockCount = ((csd->deviceSize + 1U) * 1024U); + break; + default: + break; + } + if ((uint8_t)((rawCsd[1U] & 0x4000U) >> 14U)) + { + csd->flags |= kSD_CsdEraseBlockEnabledFlag; + } + csd->eraseSectorSize = (uint8_t)((rawCsd[1U] & 0x3F80U) >> 7U); + csd->writeProtectGroupSize = (uint8_t)(rawCsd[1U] & 0x7FU); + if ((uint8_t)(rawCsd[0U] & 0x80000000U)) + { + csd->flags |= kSD_CsdWriteProtectGroupEnabledFlag; + } + csd->writeSpeedFactor = (uint8_t)((rawCsd[0U] & 0x1C000000U) >> 26U); + csd->writeBlockLength = (uint8_t)((rawCsd[0U] & 0x3C00000U) >> 22U); + if ((uint8_t)((rawCsd[0U] & 0x200000U) >> 21U)) + { + csd->flags |= kSD_CsdWriteBlockPartialFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x8000U) >> 15U)) + { + csd->flags |= kSD_CsdFileFormatGroupFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x4000U) >> 14U)) + { + csd->flags |= kSD_CsdCopyFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x2000U) >> 13U)) + { + csd->flags |= kSD_CsdPermanentWriteProtectFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x1000U) >> 12U)) + { + csd->flags |= kSD_CsdTemporaryWriteProtectFlag; + } + csd->fileFormat = (uint8_t)((rawCsd[0U] & 0xC00U) >> 10U); +} + +static status_t SD_SendCsd(sd_card_t *card) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_SendCsd; + command.argument = (card->relativeAddress << 16U); + command.responseType = kCARD_ResponseTypeR2; + + content.command = &command; + content.data = NULL; + if (kStatus_Success == card->host.transfer(card->host.base, &content)) + { + memcpy(card->rawCsd, command.response, sizeof(card->rawCsd)); + /* The response is from bit 127:8 in R2, corrisponding to command.response[3U]:command.response[0U][31U:8]. */ + SD_DecodeCsd(card, command.response); + + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid) +{ + assert(card); + assert(rawCid); + + sd_cid_t *cid; + + cid = &(card->cid); + cid->manufacturerID = (uint8_t)((rawCid[3U] & 0xFF000000U) >> 24U); + cid->applicationID = (uint16_t)((rawCid[3U] & 0xFFFF00U) >> 8U); + + cid->productName[0U] = (uint8_t)((rawCid[3U] & 0xFFU)); + cid->productName[1U] = (uint8_t)((rawCid[2U] & 0xFF000000U) >> 24U); + cid->productName[2U] = (uint8_t)((rawCid[2U] & 0xFF0000U) >> 16U); + cid->productName[3U] = (uint8_t)((rawCid[2U] & 0xFF00U) >> 8U); + cid->productName[4U] = (uint8_t)((rawCid[2U] & 0xFFU)); + + cid->productVersion = (uint8_t)((rawCid[1U] & 0xFF000000U) >> 24U); + + cid->productSerialNumber = (uint32_t)((rawCid[1U] & 0xFFFFFFU) << 8U); + cid->productSerialNumber |= (uint32_t)((rawCid[0U] & 0xFF000000U) >> 24U); + + cid->manufacturerData = (uint16_t)((rawCid[0U] & 0xFFF00U) >> 8U); +} + +static status_t SD_AllSendCid(sd_card_t *card) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_AllSendCid; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR2; + + content.command = &command; + content.data = NULL; + if (kStatus_Success == card->host.transfer(card->host.base, &content)) + { + memcpy(card->rawCid, command.response, sizeof(card->rawCid)); + SD_DecodeCid(card, command.response); + + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + status_t error = kStatus_Fail; + uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; + + command.index = kSD_ApplicationSendOperationCondition; + command.argument = argument; + command.responseType = kCARD_ResponseTypeR3; + + while (i--) + { + if (kStatus_Success != SD_SendApplicationCmd(card, 0U)) + { + continue; + } + + content.command = &command; + content.data = NULL; + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Wait until card exit busy state. */ + if (command.response[0U] & kSD_OcrPowerUpBusyFlag) + { + /* high capacity check */ + if (command.response[0U] & kSD_OcrCardCapacitySupportFlag) + { + card->flags |= kSD_SupportHighCapacityFlag; + } + /* 1.8V support */ + if (command.response[0U] & kSD_OcrSwitch18AcceptFlag) + { + card->flags |= kSD_SupportVoltage180v; + } + error = kStatus_Success; + card->ocr = command.response[0U]; + break; + } + error = kStatus_Timeout; + } + + return error; +} + +static status_t SD_SendInterfaceCondition(sd_card_t *card) +{ + assert(card); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + uint32_t i = FSL_SDMMC_MAX_CMD_RETRIES; + status_t error; + + command.index = kSD_SendInterfaceCondition; + command.argument = 0x1AAU; + command.responseType = kCARD_ResponseTypeR7; + + content.command = &command; + content.data = NULL; + do + { + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + error = kStatus_SDMMC_TransferFailed; + } + else + { + if ((command.response[0U] & 0xFFU) != 0xAAU) + { + error = kStatus_SDMMC_CardNotSupport; + } + else + { + error = kStatus_Success; + } + } + } while (--i && (error != kStatus_Success)); + + return error; +} + +static status_t SD_SelectBusTiming(sd_card_t *card) +{ + assert(card); + + status_t error = kStatus_SDMMC_SwitchBusTimingFailed; + + if (card->operationVoltage != kCARD_OperationVoltage180V) + { + /* Switch the card to high speed mode */ + if (card->host.capability.flags & kHOST_SupportHighSpeed) + { + /* group 1, function 1 ->high speed mode*/ + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR25HighSpeed); + /* If the result isn't "switching to high speed mode(50MHZ) successfully or card doesn't support high speed + * mode". Return failed status. */ + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR25HighSpeedMode; + card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); + } + else if (error == kStatus_SDMMC_NotSupportYet) + { + /* if not support high speed, keep the card work at default mode */ + return kStatus_Success; + } + } + else + { + /* if not support high speed, keep the card work at default mode */ + return kStatus_Success; + } + } + /* card is in UHS_I mode */ + else if ((kHOST_SupportSDR104 != HOST_NOT_SUPPORT) || (kHOST_SupportSDR50 != HOST_NOT_SUPPORT) || + (kHOST_SupportDDR50 != HOST_NOT_SUPPORT)) + { + switch (card->currentTiming) + { + /* if not select timing mode, sdmmc will handle it automatically*/ + case kSD_TimingSDR12DefaultMode: + case kSD_TimingSDR104Mode: + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR104); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR104Mode; + card->busClock_Hz = + HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, HOST_SUPPORT_SDR104_FREQ); + break; + } + case kSD_TimingDDR50Mode: + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionDDR50); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingDDR50Mode; + card->busClock_Hz = + HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_100MHZ); + HOST_ENABLE_DDR_MODE(card->host.base, true); + } + break; + case kSD_TimingSDR50Mode: + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR50); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR50Mode; + card->busClock_Hz = + HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_100MHZ); + } + break; + case kSD_TimingSDR25HighSpeedMode: + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR25HighSpeed); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR25HighSpeedMode; + card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); + } + break; + + default: + break; + } + } + else + { + } + + /* SDR50 and SDR104 mode need tuning */ + if ((card->currentTiming == kSD_TimingSDR50Mode) || (card->currentTiming == kSD_TimingSDR104Mode)) + { + /* config IO strength in IOMUX*/ + if (card->currentTiming == kSD_TimingSDR50Mode) + { + HOST_CONFIG_SD_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_7); + } + else + { + HOST_CONFIG_SD_IO(CARD_BUS_FREQ_200MHZ, CARD_BUS_STRENGTH_7); + } + /* execute tuning */ + if (SD_ExecuteTuning(card) != kStatus_Success) + { + return kStatus_SDMMC_TuningFail; + } + } + else if (card->currentTiming == kSD_TimingDDR50Mode) + { + HOST_CONFIG_SD_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_3); + } + + return error; +} + +static status_t SD_SetDriverStrength(sd_card_t *card, sd_driver_strength_t driverStrength) +{ + assert(card); + + status_t error; + uint32_t strength = driverStrength; + + error = SD_SelectFunction(card, kSD_GroupDriverStrength, strength); + + return error; +} + +static status_t SD_SetMaxCurrent(sd_card_t *card, sd_max_current_t maxCurrent) +{ + assert(card); + + status_t error; + uint32_t current = maxCurrent; + + error = SD_SelectFunction(card, kSD_GroupCurrentLimit, current); + + return error; +} + +static status_t SD_Read(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) +{ + assert(card); + assert(buffer); + assert(blockCount); + assert(blockSize); + assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + HOST_DATA data = {0}; + status_t error; + + if (((card->flags & kSD_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || + (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4)) + { + return kStatus_SDMMC_CardNotSupport; + } + + /* Wait for the card write process complete because of that card read process and write process use one buffer. */ + if (kStatus_Success != SD_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + data.blockSize = blockSize; + data.blockCount = blockCount; + data.rxData = (uint32_t *)buffer; + + command.index = kSDMMC_ReadMultipleBlock; + if (data.blockCount == 1U) + { + command.index = kSDMMC_ReadSingleBlock; + } + command.argument = startBlock; + if (!(card->flags & kSD_SupportHighCapacityFlag)) + { + command.argument *= data.blockSize; + } + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; + + content.command = &command; + content.data = &data; + + error = SD_Transfer(card, &content, 1U); + if (kStatus_Success != error) + { + return error; + } + + /* Send STOP_TRANSMISSION command in multiple block transmission and host's AUTO_COMMAND12 isn't enabled. */ + if ((data.blockCount > 1U) && (!(data.enableAutoCommand12))) + { + if (kStatus_Success != SD_StopTransmission(card)) + { + return kStatus_SDMMC_StopTransmissionFailed; + } + } + + return kStatus_Success; +} + +static status_t SD_Write( + sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) +{ + assert(card); + assert(buffer); + assert(blockCount); + assert(blockSize); + assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + HOST_DATA data = {0}; + status_t error; + + if (((card->flags & kSD_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || + (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4U)) + { + return kStatus_SDMMC_CardNotSupport; + } + + /* Wait for the card's buffer to be not full to write to improve the write performance. */ + while ((GET_HOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) + { + } + + /* Wait for the card write process complete because of that card read process and write process use one buffer.*/ + if (kStatus_Success != SD_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + data.blockSize = blockSize; + data.blockCount = blockCount; + data.txData = (const uint32_t *)buffer; + + command.index = kSDMMC_WriteMultipleBlock; + if (data.blockCount == 1U) + { + command.index = kSDMMC_WriteSingleBlock; + } + command.argument = startBlock; + if (!(card->flags & kSD_SupportHighCapacityFlag)) + { + command.argument *= data.blockSize; + } + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; + + content.command = &command; + content.data = &data; + + error = SD_Transfer(card, &content, 1U); + if (kStatus_Success != error) + { + return error; + } + + /* Send STOP_TRANSMISSION command in multiple block transmission and host's AUTO_COMMAND12 isn't enabled. */ + if ((data.blockCount > 1U) && (!(data.enableAutoCommand12))) + { + if (kStatus_Success != SD_StopTransmission(card)) + { + return kStatus_SDMMC_StopTransmissionFailed; + } + } + + return kStatus_Success; +} + +static status_t SD_Erase(sd_card_t *card, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(blockCount); + + uint32_t eraseBlockStart; + uint32_t eraseBlockEnd; + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + /* Wait for the card's buffer to be not full to write to improve the write performance. */ + while ((GET_HOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) + { + } + + /* Wait for the card write process complete because of that card read process and write process use one buffer.*/ + if (kStatus_Success != SD_WaitWriteComplete(card)) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + eraseBlockStart = startBlock; + eraseBlockEnd = eraseBlockStart + blockCount - 1U; + if (!(card->flags & kSD_SupportHighCapacityFlag)) + { + eraseBlockStart = eraseBlockStart * FSL_SDMMC_DEFAULT_BLOCK_SIZE; + eraseBlockEnd = eraseBlockEnd * FSL_SDMMC_DEFAULT_BLOCK_SIZE; + } + + /* Send ERASE_WRITE_BLOCK_START command to set the start block number to erase. */ + command.index = kSD_EraseWriteBlockStart; + command.argument = eraseBlockStart; + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; + + content.command = &command; + content.data = NULL; + + if (kStatus_Success != SD_Transfer(card, &content, 1U)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Send ERASE_WRITE_BLOCK_END command to set the end block number to erase. */ + command.index = kSD_EraseWriteBlockEnd; + command.argument = eraseBlockEnd; + + content.command = &command; + content.data = NULL; + if (kStatus_Success != SD_Transfer(card, &content, 0U)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Send ERASE command to start erase process. */ + command.index = kSDMMC_Erase; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1b; + command.responseErrorFlags = kSDMMC_R1ErrorAllFlag; + + content.command = &command; + content.data = NULL; + if (kStatus_Success != SD_Transfer(card, &content, 0U)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SD_Init(sd_card_t *card) +{ + assert(card); + + uint32_t applicationCommand41Argument = 0U; + status_t error = kStatus_Success; + + if (!card->isHostReady) + { + error = HOST_Init(&(card->host)); + if (error != kStatus_Success) + { + return error; + } + /* set the host status flag, after the card re-plug in, don't need init host again */ + card->isHostReady = true; + } + else + { + /* reset the host */ + HOST_Reset(card->host.base); + } + + /*detect card insert*/ + error = CardInsertDetect(card->host.base); + if (error != kStatus_Success) + { + return error; + } + /* reset variables */ + card->flags = 0U; + /* set DATA bus width */ + HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH1BIT); + /*set card freq to 400KHZ*/ + card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMC_CLOCK_400KHZ); + /* send card active */ + HOST_SEND_CARD_ACTIVE(card->host.base, 100U); + /* Get host capability. */ + GET_HOST_CAPABILITY(card->host.base, &(card->host.capability)); + + /* card go idle */ + if (kStatus_Success != SD_GoIdle(card)) + { + return kStatus_SDMMC_GoIdleFailed; + } + + if (kHOST_SupportV330 != HOST_NOT_SUPPORT) + { + applicationCommand41Argument |= (kSD_OcrVdd32_33Flag | kSD_OcrVdd33_34Flag); + card->operationVoltage = kCARD_OperationVoltage330V; + } + else if (kHOST_SupportV300 != HOST_NOT_SUPPORT) + { + applicationCommand41Argument |= kSD_OcrVdd29_30Flag; + card->operationVoltage = kCARD_OperationVoltage330V; + } + + /* allow user select the work voltage, if not select, sdmmc will handle it automatically */ + if (kHOST_SupportV180 != HOST_NOT_SUPPORT) + { + applicationCommand41Argument |= kSD_OcrSwitch18RequestFlag; + } + + /* Check card's supported interface condition. */ + if (kStatus_Success == SD_SendInterfaceCondition(card)) + { + /* SDHC or SDXC card */ + applicationCommand41Argument |= kSD_OcrHostCapacitySupportFlag; + card->flags |= kSD_SupportSdhcFlag; + } + else + { + /* SDSC card */ + if (kStatus_Success != SD_GoIdle(card)) + { + return kStatus_SDMMC_GoIdleFailed; + } + } + /* Set card interface condition according to SDHC capability and card's supported interface condition. */ + if (kStatus_Success != SD_ApplicationSendOperationCondition(card, applicationCommand41Argument)) + { + return kStatus_SDMMC_HandShakeOperationConditionFailed; + } + + /* check if card support 1.8V */ + if ((card->flags & kSD_SupportVoltage180v)) + { + if (kStatus_Success != SD_SwitchVoltage(card)) + { + return kStatus_SDMMC_InvalidVoltage; + } + card->operationVoltage = kCARD_OperationVoltage180V; + } + + /* Initialize card if the card is SD card. */ + if (kStatus_Success != SD_AllSendCid(card)) + { + return kStatus_SDMMC_AllSendCidFailed; + } + if (kStatus_Success != SD_SendRca(card)) + { + return kStatus_SDMMC_SendRelativeAddressFailed; + } + if (kStatus_Success != SD_SendCsd(card)) + { + return kStatus_SDMMC_SendCsdFailed; + } + if (kStatus_Success != SD_SelectCard(card, true)) + { + return kStatus_SDMMC_SelectCardFailed; + } + + if (kStatus_Success != SD_SendScr(card)) + { + return kStatus_SDMMC_SendScrFailed; + } + + /* Set to max frequency in non-high speed mode. */ + card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_25MHZ); + + /* Set to 4-bit data bus mode. */ + if (((card->host.capability.flags) & kHOST_Support4BitBusWidth) && (card->flags & kSD_Support4BitWidthFlag)) + { + if (kStatus_Success != SD_SetDataBusWidth(card, kSD_DataBusWidth4Bit)) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH4BIT); + } + + /* set sd card driver strength */ + SD_SetDriverStrength(card, card->driverStrength); + /* set sd card current limit */ + SD_SetMaxCurrent(card, card->maxCurrent); + + /* set block size */ + if (SD_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE)) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + /* select bus timing */ + if (kStatus_Success != SD_SelectBusTiming(card)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + + return kStatus_Success; +} + +void SD_Deinit(sd_card_t *card) +{ + assert(card); + + SD_SelectCard(card, false); + HOST_Deinit(&(card->host)); + /* should re-init host */ + card->isHostReady = false; +} + +bool SD_CheckReadOnly(sd_card_t *card) +{ + assert(card); + + return ((card->csd.flags & kSD_CsdPermanentWriteProtectFlag) || + (card->csd.flags & kSD_CsdTemporaryWriteProtectFlag)); +} + +status_t SD_ReadBlocks(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(buffer); + assert(blockCount); + + uint32_t blockCountOneTime; + uint32_t blockLeft; + uint32_t blockDone; + uint8_t *nextBuffer; + status_t error; + + if ((blockCount + startBlock) > card->blockCount) + { + return kStatus_InvalidArgument; + } + + blockLeft = blockCount; + blockDone = 0U; + while (blockLeft) + { + if (blockLeft > card->host.capability.maxBlockCount) + { + blockLeft = (blockLeft - card->host.capability.maxBlockCount); + blockCountOneTime = card->host.capability.maxBlockCount; + } + else + { + blockCountOneTime = blockLeft; + blockLeft = 0U; + } + + nextBuffer = (buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + error = SD_Read(card, nextBuffer, (startBlock + blockDone), FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime); + if (error != kStatus_Success) + { + return error; + } + + blockDone += blockCountOneTime; + } + + return kStatus_Success; +} + +status_t SD_WriteBlocks(sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(buffer); + assert(blockCount); + + uint32_t blockCountOneTime; /* The block count can be wrote in one time sending WRITE_BLOCKS command. */ + uint32_t blockLeft; /* Left block count to be wrote. */ + uint32_t blockDone = 0U; /* The block count has been wrote. */ + const uint8_t *nextBuffer; + status_t error; + + if ((blockCount + startBlock) > card->blockCount) + { + return kStatus_InvalidArgument; + } + + blockLeft = blockCount; + while (blockLeft) + { + if (blockLeft > card->host.capability.maxBlockCount) + { + blockLeft = (blockLeft - card->host.capability.maxBlockCount); + blockCountOneTime = card->host.capability.maxBlockCount; + } + else + { + blockCountOneTime = blockLeft; + blockLeft = 0U; + } + + nextBuffer = (buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + error = SD_Write(card, nextBuffer, (startBlock + blockDone), FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime); + if (error != kStatus_Success) + { + return error; + } + + blockDone += blockCountOneTime; + } + + return kStatus_Success; +} + +status_t SD_EraseBlocks(sd_card_t *card, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(blockCount); + + uint32_t blockCountOneTime; /* The block count can be erased in one time sending ERASE_BLOCKS command. */ + uint32_t blockDone = 0U; /* The block count has been erased. */ + uint32_t blockLeft; /* Left block count to be erase. */ + status_t error; + + if ((blockCount + startBlock) > card->blockCount) + { + return kStatus_InvalidArgument; + } + + blockLeft = blockCount; + while (blockLeft) + { + if (blockLeft > (card->csd.eraseSectorSize + 1U)) + { + blockCountOneTime = card->csd.eraseSectorSize + 1U; + blockLeft = blockLeft - blockCountOneTime; + } + else + { + blockCountOneTime = blockLeft; + blockLeft = 0U; + } + + error = SD_Erase(card, (startBlock + blockDone), blockCountOneTime); + if (error != kStatus_Success) + { + return error; + } + + blockDone += blockCountOneTime; + } + + return kStatus_Success; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdio.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdio.c new file mode 100644 index 0000000000..4e88fb183e --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdio.c @@ -0,0 +1,1041 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_card.h" +#include "fsl_sdmmc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SDIO_COMMON_CIS_TUPLE_NUM (3U) /*!< define the tuple number will be read during init */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief send card operation condition + * @param card Card descriptor. + * @param command argment + * argument = 0U , means to get the operation condition + * argument !=0 , set the operation condition register + */ +static status_t SDIO_SendOperationCondition(sdio_card_t *card, uint32_t argument); + +/*! + * @brief card Send relative address + * @param card Card descriptor. + */ +static status_t SDIO_SendRca(sdio_card_t *card); + +/*! + * @brief card select card + * @param card Card descriptor. + * @param select/diselect flag + */ +static status_t inline SDIO_SelectCard(sdio_card_t *card, bool isSelected); + +/*! + * @brief card go idle + * @param card Card descriptor. + */ +static status_t inline SDIO_GoIdle(sdio_card_t *card); + +/*! + * @brief decode CIS + * @param card Card descriptor. + * @param func number + * @param data buffer pointer + * @param tuple code + * @param tuple link + */ +static status_t SDIO_DecodeCIS( + sdio_card_t *card, sdio_func_num_t func, uint8_t *dataBuffer, uint32_t tplCode, uint32_t tplLink); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* define the tuple list */ +static const uint32_t g_tupleList[SDIO_COMMON_CIS_TUPLE_NUM] = { + SDIO_TPL_CODE_MANIFID, SDIO_TPL_CODE_FUNCID, SDIO_TPL_CODE_FUNCE, +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +static status_t inline SDIO_SelectCard(sdio_card_t *card, bool isSelected) +{ + assert(card); + + return SDMMC_SelectCard(card->host.base, card->host.transfer, card->relativeAddress, isSelected); +} + +static status_t inline SDIO_GoIdle(sdio_card_t *card) +{ + assert(card); + + return SDMMC_GoIdle(card->host.base, card->host.transfer); +} + +static status_t SDIO_SendRca(sdio_card_t *card) +{ + assert(card); + + uint32_t i = FSL_SDMMC_MAX_CMD_RETRIES; + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDIO_SendRelativeAddress; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR6; + command.responseErrorFlags = kSDIO_StatusR6Error | kSDIO_StatusIllegalCmd | kSDIO_StatusCmdCRCError; + + content.command = &command; + content.data = NULL; + + while (--i) + { + if (kStatus_Success == card->host.transfer(card->host.base, &content)) + { + /* check illegal state and cmd CRC error, may be the voltage or clock not stable, retry the cmd*/ + if (command.response[0U] & (kSDIO_StatusIllegalCmd | kSDIO_StatusCmdCRCError)) + { + continue; + } + + card->relativeAddress = (command.response[0U] >> 16U); + + return kStatus_Success; + } + } + + return kStatus_SDMMC_TransferFailed; +} + +status_t SDIO_CardInActive(sdio_card_t *card) +{ + assert(card); + + return SDMMC_SetCardInactive(card->host.base, card->host.transfer); +} + +static status_t SDIO_SendOperationCondition(sdio_card_t *card, uint32_t argument) +{ + assert(card); + + HOST_TRANSFER content = {0U}; + HOST_COMMAND command = {0U}; + uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; + + command.index = kSDIO_SendOperationCondition; + command.argument = argument; + command.responseType = kCARD_ResponseTypeR4; + + content.command = &command; + content.data = NULL; + + while (--i) + { + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + continue; + } + + /* if argument equal 0, then should check and save the info */ + if (argument == 0U) + { + /* check if memory present */ + if ((command.response[0U] & kSDIO_OcrMemPresent) == kSDIO_OcrMemPresent) + { + card->memPresentFlag = true; + } + /* save the io number */ + card->ioTotalNumber = (command.response[0U] & kSDIO_OcrIONumber) >> 28U; + /* save the operation condition */ + card->ocr = command.response[0U] & 0xFFFFFFU; + + break; + } + /* wait the card is ready for after initialization */ + else if (command.response[0U] & kSDIO_OcrPowerUpBusyFlag) + { + break; + } + } + + return ((i != 0U) ? kStatus_Success : kStatus_Fail); +} + +status_t SDIO_IO_Write_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data, bool raw) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + HOST_TRANSFER content = {0U}; + HOST_COMMAND command = {0U}; + + command.index = kSDIO_RWIODirect; + command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | + (1U << SDIO_CMD_ARGUMENT_RW_POS) | ((raw ? 1U : 0U) << SDIO_DIRECT_CMD_ARGUMENT_RAW_POS) | + (*data & SDIO_DIRECT_CMD_DATA_MASK); + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + + content.command = &command; + content.data = NULL; + + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* read data from response */ + *data = command.response[0U] & SDIO_DIRECT_CMD_DATA_MASK; + + return kStatus_Success; +} + +status_t SDIO_IO_Read_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + HOST_TRANSFER content = {0U}; + HOST_COMMAND command = {0U}; + + command.index = kSDIO_RWIODirect; + command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS); + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + + content.command = &command; + content.data = NULL; + + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* read data from response */ + *data = command.response[0U] & SDIO_DIRECT_CMD_DATA_MASK; + + return kStatus_Success; +} + +status_t SDIO_IO_Write_Extended( + sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags) +{ + assert(card); + assert(buffer); + assert(func <= kSDIO_FunctionNum7); + + HOST_TRANSFER content = {0U}; + HOST_COMMAND command = {0U}; + HOST_DATA data = {0U}; + bool blockMode = false; + bool opCode = false; + + /* check if card support block mode */ + if ((card->cccrflags & kSDIO_CCCRSupportMultiBlock) && (flags & SDIO_EXTEND_CMD_BLOCK_MODE_MASK)) + { + blockMode = true; + } + + if (flags & SDIO_EXTEND_CMD_OP_CODE_MASK) + { + opCode = true; + } + + /* check the byte size counter in non-block mode + * so you need read CIS for each function first,before you do read/write + */ + if (!blockMode) + { + if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && + (count > card->commonCIS.fn0MaxBlkSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && + (count > card->funcCIS[func - 1U].ioMaxBlockSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + } + + command.index = kSDIO_RWIOExtended; + command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | + (1U << SDIO_CMD_ARGUMENT_RW_POS) | (count & SDIO_EXTEND_CMD_COUNT_MASK) | + ((blockMode ? 1 : 0) << SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS | + ((opCode ? 1 : 0) << SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS)); + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + + if (blockMode) + { + if (func == kSDIO_FunctionNum0) + { + data.blockSize = card->io0blockSize; + } + else + { + data.blockSize = card->ioFBR[func - 1U].ioBlockSize; + } + data.blockCount = count; + } + else + { + data.blockSize = count; + data.blockCount = 1U; + } + data.txData = (uint32_t *)buffer; + + content.command = &command; + content.data = &data; + + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_IO_Read_Extended( + sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags) +{ + assert(card); + assert(buffer); + assert(func <= kSDIO_FunctionNum7); + + HOST_TRANSFER content = {0U}; + HOST_COMMAND command = {0U}; + HOST_DATA data = {0U}; + bool blockMode = false; + bool opCode = false; + + /* check if card support block mode */ + if ((card->cccrflags & kSDIO_CCCRSupportMultiBlock) && (flags & SDIO_EXTEND_CMD_BLOCK_MODE_MASK)) + { + blockMode = true; + } + + /* op code =0 : read/write to fixed addr + * op code =1 :read/write addr incrementing + */ + if (flags & SDIO_EXTEND_CMD_OP_CODE_MASK) + { + opCode = true; + } + + /* check the byte size counter in non-block mode + * so you need read CIS for each function first,before you do read/write + */ + if (!blockMode) + { + if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && + (count > card->commonCIS.fn0MaxBlkSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && + (count > card->funcCIS[func - 1U].ioMaxBlockSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + } + + command.index = kSDIO_RWIOExtended; + command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | + (count & SDIO_EXTEND_CMD_COUNT_MASK) | + ((blockMode ? 1U : 0U) << SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS | + ((opCode ? 1U : 0U) << SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS)); + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | + kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); + + if (blockMode) + { + if (func == kSDIO_FunctionNum0) + { + data.blockSize = card->io0blockSize; + } + else + { + data.blockSize = card->ioFBR[func - 1U].ioBlockSize; + } + data.blockCount = count; + } + else + { + data.blockSize = count; + data.blockCount = 1U; + } + data.rxData = (uint32_t *)buffer; + + content.command = &command; + content.data = &data; + + if (kStatus_Success != card->host.transfer(card->host.base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_GetCardCapability(sdio_card_t *card, sdio_func_num_t func) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + uint8_t tempBuffer[20] = {0U}; + uint32_t i = 0U; + + for (i = 0U; i < 20U; i++) + { + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, SDIO_FBR_BASE(func) + i, &tempBuffer[i])) + { + return kStatus_SDMMC_TransferFailed; + } + } + + switch (func) + { + case kSDIO_FunctionNum0: + + card->sdVersion = tempBuffer[1U]; + card->sdioVersion = tempBuffer[0U] >> 4U; + card->cccrVersioin = tempBuffer[0U] & 0xFU; + /* continuous SPI interrupt */ + if (tempBuffer[7U] & 0x40U) + { + card->cccrflags |= kSDIO_CCCRSupportContinuousSPIInt; + } + /* card capability register */ + card->cccrflags |= (tempBuffer[8U] & 0xDFU); + /* master power control */ + if (tempBuffer[18U] & 0x01U) + { + card->cccrflags |= kSDIO_CCCRSupportMasterPowerControl; + } + /* high speed flag */ + if (tempBuffer[19U] & 0x01U) + { + card->cccrflags |= kSDIO_CCCRSupportHighSpeed; + } + /* common CIS pointer */ + card->commonCISPointer = tempBuffer[9U] | (tempBuffer[10U] << 8U) | (tempBuffer[11U] << 16U); + + break; + + case kSDIO_FunctionNum1: + case kSDIO_FunctionNum2: + case kSDIO_FunctionNum3: + case kSDIO_FunctionNum4: + case kSDIO_FunctionNum5: + case kSDIO_FunctionNum6: + case kSDIO_FunctionNum7: + card->ioFBR[func - 1U].ioStdFunctionCode = tempBuffer[0U] & 0x0FU; + card->ioFBR[func - 1U].ioExtFunctionCode = tempBuffer[1U]; + card->ioFBR[func - 1U].ioPointerToCIS = tempBuffer[9U] | (tempBuffer[10U] << 8U) | (tempBuffer[11U] << 16U); + card->ioFBR[func - 1U].ioPointerToCSA = + tempBuffer[12U] | (tempBuffer[13U] << 8U) | (tempBuffer[14U] << 16U); + if (tempBuffer[2U] & 0x01U) + { + card->ioFBR[func - 1U].flags |= kSDIO_FBRSupportPowerSelection; + } + if (tempBuffer[0U] & 0x40U) + { + card->ioFBR[func - 1U].flags |= kSDIO_FBRSupportCSA; + } + + break; + + default: + break; + } + + return kStatus_Success; +} + +status_t SDIO_SetBlockSize(sdio_card_t *card, sdio_func_num_t func, uint32_t blockSize) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + assert(blockSize <= SDIO_MAX_BLOCK_SIZE); + + uint8_t temp = 0U; + + /* check the block size for block mode + * so you need read CIS for each function first,before you do read/write + */ + if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && + (blockSize > card->commonCIS.fn0MaxBlkSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && + (blockSize > card->funcCIS[func - 1U].ioMaxBlockSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + + temp = blockSize & 0xFFU; + + if (kStatus_Success != + SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, SDIO_FBR_BASE(func) + kSDIO_RegFN0BlockSizeLow, &temp, true)) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + temp = (blockSize >> 8U) & 0xFFU; + + if (kStatus_Success != + SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, SDIO_FBR_BASE(func) + kSDIO_RegFN0BlockSizeHigh, &temp, true)) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + /* record the current block size */ + if (func == kSDIO_FunctionNum0) + { + card->io0blockSize = blockSize; + } + else + { + card->ioFBR[func - 1U].ioBlockSize = blockSize; + } + + return kStatus_Success; +} + +status_t SDIO_CardReset(sdio_card_t *card) +{ + uint8_t reset = 0x08U; + + return SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOAbort, &reset, false); +} + +status_t SDIO_SetDataBusWidth(sdio_card_t *card, sdio_bus_width_t busWidth) +{ + assert(card); + + uint8_t regBusInterface = 0U; + + /* load bus interface register */ + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, kSDIO_RegBusInterface, ®BusInterface)) + { + return kStatus_SDMMC_TransferFailed; + } + /* set bus width */ + regBusInterface |= busWidth; + + /* write to register */ + if (kStatus_Success != + SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegBusInterface, ®BusInterface, true)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_SwitchToHighSpeed(sdio_card_t *card) +{ + assert(card); + + uint8_t temp = 0U; + + if (card->cccrflags & kSDIO_CCCRSupportHighSpeed) + { + /* enable high speed mode */ + temp = 0x02U; + if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegHighSpeed, &temp, true)) + { + return kStatus_SDMMC_TransferFailed; + } + /* either EHS=0 and SHS=0 ,the card is still in default mode */ + if ((temp & 0x03U) == 0x03U) + { + /* set to 4bit data bus */ + SDIO_SetDataBusWidth(card, kSDIO_DataBus4Bit); + HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH4BIT); + /* high speed mode , set freq to 50MHZ */ + card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); + } + else + { + return kStatus_SDMMC_SDIO_SwitchHighSpeedFail; + } + } + + return kStatus_Success; +} + +static status_t SDIO_DecodeCIS( + sdio_card_t *card, sdio_func_num_t func, uint8_t *dataBuffer, uint32_t tplCode, uint32_t tplLink) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + if (func == kSDIO_FunctionNum0) + { + /* only decode MANIFID,FUNCID,FUNCE here */ + if (tplCode == SDIO_TPL_CODE_MANIFID) + { + card->commonCIS.mID = dataBuffer[0U] | (dataBuffer[1U] << 8U); + card->commonCIS.mInfo = dataBuffer[2U] | (dataBuffer[3U] << 8U); + } + else if (tplCode == SDIO_TPL_CODE_FUNCID) + { + card->commonCIS.funcID = dataBuffer[0U]; + } + else if (tplCode == SDIO_TPL_CODE_FUNCE) + { + /* max transfer block size and data size */ + card->commonCIS.fn0MaxBlkSize = dataBuffer[1U] | (dataBuffer[2U] << 8U); + /* max transfer speed */ + card->commonCIS.maxTransSpeed = dataBuffer[3U]; + } + else + { + /* reserved here */ + return kStatus_Fail; + } + } + else + { + /* only decode FUNCID,FUNCE here */ + if (tplCode == SDIO_TPL_CODE_FUNCID) + { + card->funcCIS[func].funcID = dataBuffer[0U]; + } + else if (tplCode == SDIO_TPL_CODE_FUNCE) + { + if (tplLink == 0x2A) + { + card->funcCIS[func - 1U].funcInfo = dataBuffer[1U]; + card->funcCIS[func - 1U].ioVersion = dataBuffer[2U]; + card->funcCIS[func - 1U].cardPSN = + dataBuffer[3U] | (dataBuffer[4U] << 8U) | (dataBuffer[5U] << 16U) | (dataBuffer[6U] << 24U); + card->funcCIS[func - 1U].ioCSASize = + dataBuffer[7U] | (dataBuffer[8U] << 8U) | (dataBuffer[9U] << 16U) | (dataBuffer[10U] << 24U); + card->funcCIS[func - 1U].ioCSAProperty = dataBuffer[11U]; + card->funcCIS[func - 1U].ioMaxBlockSize = dataBuffer[12U] | (dataBuffer[13U] << 8U); + card->funcCIS[func - 1U].ioOCR = + dataBuffer[14U] | (dataBuffer[15U] << 8U) | (dataBuffer[16U] << 16U) | (dataBuffer[17U] << 24U); + card->funcCIS[func - 1U].ioOPMinPwr = dataBuffer[18U]; + card->funcCIS[func - 1U].ioOPAvgPwr = dataBuffer[19U]; + card->funcCIS[func - 1U].ioOPMaxPwr = dataBuffer[20U]; + card->funcCIS[func - 1U].ioSBMinPwr = dataBuffer[21U]; + card->funcCIS[func - 1U].ioSBAvgPwr = dataBuffer[22U]; + card->funcCIS[func - 1U].ioSBMaxPwr = dataBuffer[23U]; + card->funcCIS[func - 1U].ioMinBandWidth = dataBuffer[24U] | (dataBuffer[25U] << 8U); + card->funcCIS[func - 1U].ioOptimumBandWidth = dataBuffer[26U] | (dataBuffer[27U] << 8U); + card->funcCIS[func - 1U].ioReadyTimeout = dataBuffer[28U] | (dataBuffer[29U] << 8U); + + card->funcCIS[func - 1U].ioHighCurrentAvgCurrent = dataBuffer[34U] | (dataBuffer[35U] << 8U); + card->funcCIS[func - 1U].ioHighCurrentMaxCurrent = dataBuffer[36U] | (dataBuffer[37U] << 8U); + card->funcCIS[func - 1U].ioLowCurrentAvgCurrent = dataBuffer[38U] | (dataBuffer[39U] << 8U); + card->funcCIS[func - 1U].ioLowCurrentMaxCurrent = dataBuffer[40U] | (dataBuffer[41U] << 8U); + } + else + { + return kStatus_Fail; + } + } + else + { + return kStatus_Fail; + } + } + + return kStatus_Success; +} + +status_t SDIO_ReadCIS(sdio_card_t *card, sdio_func_num_t func, const uint32_t *tupleList, uint32_t tupleNum) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + assert(tupleList); + + uint8_t tplCode = 0U; + uint8_t tplLink = 0U; + uint32_t cisPtr = 0U; + uint32_t i = 0U, num = 0U; + bool tupleMatch = false; + + uint8_t dataBuffer[255U] = {0U}; + + /* get the CIS pointer for each function */ + if (func == kSDIO_FunctionNum0) + { + cisPtr = card->commonCISPointer; + } + else + { + cisPtr = card->ioFBR[func - 1U].ioPointerToCIS; + } + + if (0U == cisPtr) + { + return kStatus_SDMMC_SDIO_ReadCISFail; + } + + do + { + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, cisPtr++, &tplCode)) + { + return kStatus_SDMMC_TransferFailed; + } + /* end of chain tuple */ + if (tplCode == 0xFFU) + { + break; + } + + if (tplCode == 0U) + { + continue; + } + + for (i = 0; i < tupleNum; i++) + { + if (tplCode == tupleList[i]) + { + tupleMatch = true; + break; + } + } + + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, cisPtr++, &tplLink)) + { + return kStatus_SDMMC_TransferFailed; + } + /* end of chain tuple */ + if (tplLink == 0xFFU) + { + break; + } + + if (tupleMatch) + { + memset(dataBuffer, 0U, 255U); + for (i = 0; i < tplLink; i++) + { + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, cisPtr++, &dataBuffer[i])) + { + return kStatus_SDMMC_TransferFailed; + } + } + tupleMatch = false; + /* pharse the data */ + SDIO_DecodeCIS(card, func, dataBuffer, tplCode, tplLink); + /* read finish then return */ + if (++num == tupleNum) + { + break; + } + } + else + { + /* move pointer */ + cisPtr += tplLink; + /* tuple code not match,continue read tuple code */ + continue; + } + } while (1); + return kStatus_Success; +} + +status_t SDIO_Init(sdio_card_t *card) +{ + assert(card); + assert(card->host.base); + + status_t error = kStatus_Success; + + if (!card->isHostReady) + { + error = HOST_Init(&(card->host)); + if (error != kStatus_Success) + { + return error; + } + /* set the host status flag, after the card re-plug in, don't need init host again */ + card->isHostReady = true; + } + else + { + /* reset the host */ + HOST_Reset(card->host.base); + } + + error = CardInsertDetect(card->host.base); + if (error != kStatus_Success) + { + return error; + } + + /* Identify mode ,set clock to 400KHZ. */ + card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMC_CLOCK_400KHZ); + HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH1BIT); + HOST_SEND_CARD_ACTIVE(card->host.base, 100U); + + /* get host capability */ + GET_HOST_CAPABILITY(card->host.base, &(card->host.capability)); + + /* card go idle */ + if (kStatus_Success != SDIO_GoIdle(card)) + { + return kStatus_SDMMC_GoIdleFailed; + } + + /* Get IO OCR-CMD5 with arg0 ,set new voltage if needed*/ + if (kStatus_Success != SDIO_SendOperationCondition(card, 0U)) + { + return kStatus_SDMMC_HandShakeOperationConditionFailed; + } + + /* there is a memonly card */ + if ((card->ioTotalNumber == 0U) && (card->memPresentFlag)) + { + return kStatus_SDMMC_SDIO_InvalidCard; + } + /* verify the voltage and set the new voltage */ + if (card->host.capability.flags & kHOST_SupportV330) + { + if (kStatus_Success != SDIO_SendOperationCondition(card, kSDIO_OcrVdd32_33Flag | kSDIO_OcrVdd33_34Flag)) + { + return kStatus_SDMMC_InvalidVoltage; + } + } + else + { + return kStatus_SDMMC_InvalidVoltage; + } + + /* send relative address ,cmd3*/ + if (kStatus_Success != SDIO_SendRca(card)) + { + return kStatus_SDMMC_SendRelativeAddressFailed; + } + /* select card cmd7 */ + if (kStatus_Success != SDIO_SelectCard(card, true)) + { + return kStatus_SDMMC_SelectCardFailed; + } + + /* get card capability */ + if (kStatus_Success != SDIO_GetCardCapability(card, kSDIO_FunctionNum0)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* read common CIS here */ + if (SDIO_ReadCIS(card, kSDIO_FunctionNum0, g_tupleList, SDIO_COMMON_CIS_TUPLE_NUM)) + { + return kStatus_SDMMC_SDIO_ReadCISFail; + } + + /* freq and bus width setting */ + if (card->cccrflags & kSDIO_CCCRSupportLowSpeed4Bit) + { + /* set to 4bit data bus */ + SDIO_SetDataBusWidth(card, kSDIO_DataBus4Bit); + HOST_SET_CARD_BUS_WIDTH(card->host.base, kHOST_DATABUSWIDTH4BIT); + } + else if (card->cccrflags & kSDIO_CCCRSupportHighSpeed) + { + if (kStatus_Success != SDIO_SwitchToHighSpeed(card)) + { + return kStatus_SDMMC_SDIO_SwitchHighSpeedFail; + } + + return kStatus_Success; + } + + /* default mode 25MHZ */ + card->busClock_Hz = HOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_25MHZ); + + return kStatus_Success; +} + +status_t SDIO_EnableIOInterrupt(sdio_card_t *card, sdio_func_num_t func, bool enable) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + uint8_t intEn = 0U; + + /* load io interrupt enable register */ + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOIntEnable, &intEn)) + { + return kStatus_SDMMC_TransferFailed; + } + + if (enable) + { + /* if already enable , do not need enable again */ + if ((((intEn >> func) & 0x01U) == 0x01U) && (intEn & 0x01U)) + { + return kStatus_Success; + } + + /* enable the interrupt and interrupt master */ + intEn |= (1U << func) | 0x01U; + } + else + { + /* if already disable , do not need enable again */ + if (((intEn >> func) & 0x01U) == 0x00U) + { + return kStatus_Success; + } + + /* disable the interrupt, don't disable the interrupt master here */ + intEn &= ~(1U << func); + } + + /* write to register */ + if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOIntEnable, &intEn, true)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_EnableIO(sdio_card_t *card, sdio_func_num_t func, bool enable) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + uint8_t ioEn = 0U, ioReady = 0U; + uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; + + /* load io enable register */ + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOEnable, &ioEn)) + { + return kStatus_SDMMC_TransferFailed; + } + /* if already enable/disable , do not need enable/disable again */ + if (((ioEn >> func) & 0x01U) == (enable ? 1U : 0U)) + { + return kStatus_Success; + } + + /* enable the io */ + if (enable) + { + ioEn |= (1U << func); + } + else + { + ioEn &= ~(1U << func); + } + + /* write to register */ + if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOEnable, &ioEn, true)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* if enable io, need check the IO ready status */ + if (enable) + { + while (i--) + { + /* wait IO ready */ + if (kStatus_Success != SDIO_IO_Read_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOReady, &ioReady)) + { + return kStatus_SDMMC_TransferFailed; + } + /* check if IO ready */ + if ((ioReady & (1 << func)) != 0U) + { + return kStatus_Success; + } + } + } + + return (i == 0U) ? kStatus_Fail : kStatus_Success; +} + +status_t SDIO_SelectIO(sdio_card_t *card, sdio_func_num_t func) +{ + assert(card); + assert(func <= kSDIO_FunctionMemory); + + uint8_t ioSel = func; + + /* write to register */ + if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegFunctionSelect, &ioSel, true)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_AbortIO(sdio_card_t *card, sdio_func_num_t func) +{ + assert(card); + assert(func <= kSDIO_FunctionNum7); + + uint8_t ioAbort = func; + + /* write to register */ + if (kStatus_Success != SDIO_IO_Write_Direct(card, kSDIO_FunctionNum0, kSDIO_RegIOAbort, &ioAbort, true)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +void SDIO_DeInit(sdio_card_t *card) +{ + assert(card); + /* disselect card */ + SDIO_CardReset(card); + SDIO_SelectCard(card, false); + HOST_Deinit(&(card->host)); + /* should re-init host */ + card->isHostReady = false; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdmmc.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdmmc.c new file mode 100644 index 0000000000..8cc9712c0d --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdmmc.c @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_specification.h" +#include "fsl_card.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +SDK_ALIGN(uint32_t g_sdmmc[SDK_SIZEALIGN(SDMMC_GLOBAL_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CAHCE)], + MAX(SDMMC_DATA_BUFFER_ALIGN_CAHCE, HOST_DMA_BUFFER_ADDR_ALIGN)); +/******************************************************************************* + * Code + ******************************************************************************/ + +void SDMMC_Delay(uint32_t num) +{ + volatile uint32_t i, j; + + for (i = 0U; i < num; i++) + { + for (j = 0U; j < 10000U; j++) + { + __asm("nop"); + } + } +} + +status_t SDMMC_SelectCard(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t relativeAddress, bool isSelected) +{ + assert(transfer); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_SelectCard; + if (isSelected) + { + command.argument = relativeAddress << 16U; + command.responseType = kCARD_ResponseTypeR1; + } + else + { + command.argument = 0U; + command.responseType = kCARD_ResponseTypeNone; + } + + content.command = &command; + content.data = NULL; + if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & kSDMMC_R1ErrorAllFlag)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Wait until card to transfer state */ + return kStatus_Success; +} + +status_t SDMMC_SendApplicationCommand(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t relativeAddress) +{ + assert(transfer); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_ApplicationCommand; + command.argument = (relativeAddress << 16U); + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = 0U; + if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & kSDMMC_R1ErrorAllFlag)) + { + return kStatus_SDMMC_TransferFailed; + } + + if (!(command.response[0U] & kSDMMC_R1ApplicationCommandFlag)) + { + return kStatus_SDMMC_CardNotSupport; + } + + return kStatus_Success; +} + +status_t SDMMC_SetBlockCount(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t blockCount) +{ + assert(transfer); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_SetBlockCount; + command.argument = blockCount; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = 0U; + if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & kSDMMC_R1ErrorAllFlag)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_GoIdle(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer) +{ + assert(transfer); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_GoIdleState; + + content.command = &command; + content.data = 0U; + if (kStatus_Success != transfer(base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_SetBlockSize(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t blockSize) +{ + assert(transfer); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_SetBlockLength; + command.argument = blockSize; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = 0U; + if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & kSDMMC_R1ErrorAllFlag)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_SetCardInactive(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer) +{ + assert(transfer); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSDMMC_GoInactiveState; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeNone; + + content.command = &command; + content.data = 0U; + if ((kStatus_Success != transfer(base, &content))) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_SwitchVoltage(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer) +{ + assert(transfer); + + HOST_TRANSFER content = {0}; + HOST_COMMAND command = {0}; + + command.index = kSD_VoltageSwitch; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = NULL; + if (kStatus_Success != transfer(base, &content)) + { + return kStatus_SDMMC_TransferFailed; + } + /* disable card clock */ + HOST_ENABLE_CARD_CLOCK(base, false); + + /* check data line and cmd line status */ + if ((GET_HOST_STATUS(base) & + (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) != 0U) + { + return kStatus_SDMMC_SwitchVoltageFail; + } + + /* host switch to 1.8V */ + HOST_SWITCH_VOLTAGE180V(base, true); + + SDMMC_Delay(100U); + + /*enable sd clock*/ + HOST_ENABLE_CARD_CLOCK(base, true); + /*enable force clock on*/ + HOST_FORCE_SDCLOCK_ON(base, true); + /* dealy 1ms,not exactly correct when use while */ + SDMMC_Delay(10U); + /*disable force clock on*/ + HOST_FORCE_SDCLOCK_ON(base, false); + + /* check data line and cmd line status */ + if ((GET_HOST_STATUS(base) & + (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) == 0U) + { + return kStatus_SDMMC_SwitchVoltageFail; + } + + return kStatus_Success; +} + +status_t SDMMC_ExecuteTuning(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t tuningCmd, uint32_t blockSize) +{ + HOST_TRANSFER content = {0U}; + HOST_COMMAND command = {0U}; + HOST_DATA data = {0U}; + uint32_t buffer[32U] = {0U}; + bool tuningError = true; + + command.index = tuningCmd; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1; + + data.blockSize = blockSize; + data.blockCount = 1U; + data.rxData = buffer; + /* add this macro for adpter to different driver */ + HOST_ENABLE_TUNING_FLAG(data); + + content.command = &command; + content.data = &data; + + /* enable the standard tuning */ + HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, true); + + while (true) + { + /* send tuning block */ + if ((kStatus_Success != transfer(base, &content))) + { + return kStatus_SDMMC_TransferFailed; + } + SDMMC_Delay(1U); + + /*wait excute tuning bit clear*/ + if ((HOST_EXECUTE_STANDARD_TUNING_STATUS(base) != 0U)) + { + continue; + } + + /* if tuning error , re-tuning again */ + if ((HOST_CHECK_TUNING_ERROR(base) != 0U) && tuningError) + { + tuningError = false; + /* enable the standard tuning */ + HOST_EXECUTE_STANDARD_TUNING_ENABLE(base, true); + HOST_ADJUST_TUNING_DELAY(base, HOST_STANDARD_TUNING_START); + } + else + { + break; + } + } + + /* delay to wait the host controller stable */ + SDMMC_Delay(100U); + + /* check tuning result*/ + if (HOST_EXECUTE_STANDARD_TUNING_RESULT(base) == 0U) + { + return kStatus_SDMMC_TuningFail; + } + + HOST_AUTO_STANDARD_RETUNING_TIMER(base); + + return kStatus_Success; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdmmc.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdmmc.h new file mode 100644 index 0000000000..c616a95198 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdmmc.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SDMMC_H_ +#define _FSL_SDMMC_H_ + +#include "fsl_card.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Reverse byte sequence in uint32_t */ +#define SWAP_WORD_BYTE_SEQUENCE(x) (__REV(x)) +/*! @brief Reverse byte sequence for each half word in uint32_t */ +#define SWAP_HALF_WROD_BYTE_SEQUENCE(x) (__REV16(x)) + +/*! @brief Maximum loop count to check the card operation voltage range */ +#define FSL_SDMMC_MAX_VOLTAGE_RETRIES (1000U) +/*! @brief Maximum loop count to send the cmd */ +#define FSL_SDMMC_MAX_CMD_RETRIES (10U) +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Selects the card to put it into transfer state. + * + * @param base HOST peripheral base address. + * @param transfer HOST transfer function. + * @param relativeAddress Relative address. + * @param isSelected True to put card into transfer state. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SelectCard(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t relativeAddress, bool isSelected); + +/*! + * @brief Sends an application command. + * + * @param base HOST peripheral base address. + * @param transfer HOST transfer function. + * @param relativeAddress Card relative address. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SendApplicationCommand(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t relativeAddress); + +/*! + * @brief Sets the block count. + * + * @param base HOST peripheral base address. + * @param transfer HOST transfer function. + * @param blockCount Block count. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SetBlockCount(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t blockCount); + +/*! + * @brief Sets the card to be idle state. + * + * @param base HOST peripheral base address. + * @param transfer HOST transfer function. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_GoIdle(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer); + +/*! + * @brief Sets data block size. + * + * @param base HOST peripheral base address. + * @param transfer HOST transfer function. + * @param blockSize Block size. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SetBlockSize(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t blockSize); + +/*! + * @brief Sets card to inactive status + * + * @param base HOST peripheral base address. + * @param transfer HOST transfer function. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDMMC_SetCardInactive(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer); + +/*! + * @brief provide a simple delay function for sdmmc + * + * @param num Delay num*10000. + */ +void SDMMC_Delay(uint32_t num); + +/*! + * @brief provide a voltage switch function for SD/SDIO card + * + * @param base HOST peripheral base address. + * @param transfer HOST transfer function. + */ +status_t SDMMC_SwitchVoltage(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer); + +/*! + * @brief excute tuning + * + * @param base HOST peripheral base address. + * @param transfer Host transfer function + * @param tuningCmd Tuning cmd + * @param blockSize Tuning block size + */ +status_t SDMMC_ExecuteTuning(HOST_TYPE *base, HOST_TRANSFER_FUNCTION transfer, uint32_t tuningCmd, uint32_t blockSize); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_SDMMC_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdspi.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdspi.c new file mode 100644 index 0000000000..4055e16d8c --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdspi.c @@ -0,0 +1,1273 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "fsl_sdspi.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ +#define IS_BLOCK_ACCESS(x) ((x)->flags & kSDSPI_SupportHighCapacityFlag) + +/* Card command maximum timeout value */ +#define FSL_SDSPI_TIMEOUT (1000U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Wait card to be ready state. + * + * @param host Host state. + * @param milliseconds Timeout time in millseconds. + * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_WaitReady(sdspi_host_t *host, uint32_t milliseconds); + +/*! + * @brief Calculate CRC7 + * + * @param buffer Data buffer. + * @param length Data length. + * @param crc The orginal crc value. + * @return Generated CRC7. + */ +static uint32_t SDSPI_GenerateCRC7(uint8_t *buffer, uint32_t length, uint32_t crc); + +/*! + * @brief Send command. + * + * @param host Host state. + * @param command The command to be wrote. + * @param timeout The timeout value. + * @retval kStatus_SDSPI_WaitReadyFailed Wait ready failed. + * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_Fail Send command failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SendCommand(sdspi_host_t *host, sdspi_command_t *command, uint32_t timeout); + +/*! + * @brief Send GO_IDLE command. + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_ExchangeFailed Send timing byte failed. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_GoIdle(sdspi_card_t *card); + +/*! + * @brief Send GET_INTERFACE_CONDITION command. + * + * This function checks card interface condition, which includes host supply voltage information and asks the card + * whether it supports voltage. + * + * @param card Card descriptor. + * @param pattern The check pattern. + * @param response Buffer to save the command response. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SendInterfaceCondition(sdspi_card_t *card, uint8_t pattern, uint8_t *response); + +/*! + * @brief Send SEND_APPLICATION_COMMAND command. + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SendApplicationCmd(sdspi_card_t *card); + +/*! + * @brief Send GET_OPERATION_CONDITION command. + * + * @param card Card descriptor. + * @param argument Operation condition. + * @param response Buffer to save command response. + * @retval kStatus_Timeout Timeout. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_ApplicationSendOperationCondition(sdspi_card_t *card, uint32_t argument, uint8_t *response); + +/*! + * @brief Send READ_OCR command to get OCR register content. + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_ReadOcr(sdspi_card_t *card); + +/*! + * @brief Send SET_BLOCK_SIZE command. + * + * This function sets the block length in bytes for SDSC cards. For SDHC cards, it does not affect memory + * read or write commands, always 512 bytes fixed block length is used. + * @param card Card descriptor. + * @param blockSize Block size. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SetBlockSize(sdspi_card_t *card, uint32_t blockSize); + +/*! + * @brief Read data from card + * + * @param host Host state. + * @param buffer Buffer to save data. + * @param size The data size to read. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_Read(sdspi_host_t *host, uint8_t *buffer, uint32_t size); + +/*! + * @brief Decode CSD register + * + * @param card Card descriptor. + * @param rawCsd Raw CSD register content. + */ +static void SDSPI_DecodeCsd(sdspi_card_t *card, uint8_t *rawCsd); + +/*! + * @brief Send GET-CSD command. + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ReadFailed Read data blocks failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SendCsd(sdspi_card_t *card); + +/*! + * @brief Set card to max frequence in normal mode. + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_SetFrequencyFailed Set frequency failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SetMaxFrequencyNormalMode(sdspi_card_t *card); + +/*! + * @brief Check the capacity of the card + * + * @param card Card descriptor. + */ +static void SDSPI_CheckCapacity(sdspi_card_t *card); + +/*! + * @brief Decode raw CID register. + * + * @param card Card descriptor. + * @param rawCid Raw CID register content. + */ +static void SDSPI_DecodeCid(sdspi_card_t *card, uint8_t *rawCid); + +/*! + * @brief Send GET-CID command + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ReadFailed Read data blocks failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SendCid(sdspi_card_t *card); + +/*! + * @brief Decode SCR register. + * + * @param card Card descriptor. + * @param rawScr Raw SCR register content. + */ +static void SDSPI_DecodeScr(sdspi_card_t *card, uint8_t *rawScr); + +/*! + * @brief Send SEND_SCR command. + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ReadFailed Read data blocks failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_SendScr(sdspi_card_t *card); + +/*! + * @brief Send STOP_TRANSMISSION command to card to stop ongoing data transferring. + * + * @param card Card descriptor. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_StopTransmission(sdspi_card_t *card); + +/*! + * @brief Write data to card + * + * @param host Host state. + * @param buffer Data to send. + * @param size Data size. + * @param token The data token. + * @retval kStatus_SDSPI_WaitReadyFailed Card is busy error. + * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDSPI_Write(sdspi_host_t *host, uint8_t *buffer, uint32_t size, uint8_t token); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Rate unit(divided by 1000) of transfer speed in non-high-speed mode. */ +static const uint32_t g_transferSpeedRateUnit[] = { + /* 100Kbps, 1Mbps, 10Mbps, 100Mbps*/ + 100U, 1000U, 10000U, 100000U, +}; + +/* Multiplier factor(multiplied by 1000) of transfer speed in non-high-speed mode. */ +static const uint32_t g_transferSpeedMultiplierFactor[] = { + 0U, 1000U, 1200U, 1300U, 1500U, 2000U, 2500U, 3000U, 3500U, 4000U, 4500U, 5000U, 5500U, 6000U, 7000U, 8000U, +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +static status_t SDSPI_WaitReady(sdspi_host_t *host, uint32_t milliseconds) +{ + uint8_t response; + uint8_t timingByte = 0xFFU; /* The byte need to be sent as read/write data block timing requirement */ + uint32_t startTime; + uint32_t currentTime; + uint32_t elapsedTime; + + startTime = host->getCurrentMilliseconds(); + do + { + if (kStatus_Success != host->exchange(&timingByte, &response, 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + + currentTime = host->getCurrentMilliseconds(); + elapsedTime = (currentTime - startTime); + } while ((response != 0xFFU) && (elapsedTime < milliseconds)); + + /* Response 0xFF means card is still busy. */ + if (response != 0xFFU) + { + return kStatus_SDSPI_ResponseError; + } + + return kStatus_Success; +} + +static uint32_t SDSPI_GenerateCRC7(uint8_t *buffer, uint32_t length, uint32_t crc) +{ + uint32_t index; + + static const uint8_t crcTable[] = {0x00U, 0x09U, 0x12U, 0x1BU, 0x24U, 0x2DU, 0x36U, 0x3FU, + 0x48U, 0x41U, 0x5AU, 0x53U, 0x6CU, 0x65U, 0x7EU, 0x77U}; + + while (length) + { + index = (((crc >> 3U) & 0x0FU) ^ ((*buffer) >> 4U)); + crc = ((crc << 4U) ^ crcTable[index]); + + index = (((crc >> 3U) & 0x0FU) ^ ((*buffer) & 0x0FU)); + crc = ((crc << 4U) ^ crcTable[index]); + + buffer++; + length--; + } + + return (crc & 0x7FU); +} + +static status_t SDSPI_SendCommand(sdspi_host_t *host, sdspi_command_t *command, uint32_t timeout) +{ + assert(host); + assert(command); + + uint8_t buffer[6U]; + uint8_t response; + uint8_t i; + uint8_t timingByte = 0xFFU; /* The byte need to be sent as read/write data block timing requirement */ + + if ((kStatus_Success != SDSPI_WaitReady(host, timeout)) && (command->index != kSDMMC_GoIdleState)) + { + return kStatus_SDSPI_WaitReadyFailed; + } + + /* Send command. */ + buffer[0U] = (command->index | 0x40U); + buffer[1U] = ((command->argument >> 24U) & 0xFFU); + buffer[2U] = ((command->argument >> 16U) & 0xFFU); + buffer[3U] = ((command->argument >> 8U) & 0xFFU); + buffer[4U] = (command->argument & 0xFFU); + buffer[5U] = ((SDSPI_GenerateCRC7(buffer, 5U, 0U) << 1U) | 1U); + if (host->exchange(buffer, NULL, sizeof(buffer))) + { + return kStatus_SDSPI_ExchangeFailed; + } + + /* Wait for the response coming, the left most bit which is transfered first in first response byte is 0 */ + for (i = 0U; i < 9U; i++) + { + if (kStatus_Success != host->exchange(&timingByte, &response, 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + + /* Check if response 0 coming. */ + if (!(response & 0x80U)) + { + break; + } + } + if (response & 0x80U) /* Max index byte is high means response comming. */ + { + return kStatus_SDSPI_ResponseError; + } + + /* Receve all the response content. */ + command->response[0U] = response; + switch (command->responseType) + { + case kSDSPI_ResponseTypeR1: + break; + case kSDSPI_ResponseTypeR1b: + if (kStatus_Success != SDSPI_WaitReady(host, timeout)) + { + return kStatus_SDSPI_WaitReadyFailed; + } + break; + case kSDSPI_ResponseTypeR2: + if (kStatus_Success != host->exchange(&timingByte, &(command->response[1U]), 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + break; + case kSDSPI_ResponseTypeR3: + case kSDSPI_ResponseTypeR7: + /* Left 4 bytes in response type R3 and R7(total 5 bytes in SPI mode) */ + if (kStatus_Success != host->exchange(&timingByte, &(command->response[1U]), 4U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + break; + default: + return kStatus_Fail; + } + + return kStatus_Success; +} + +static status_t SDSPI_GoIdle(sdspi_card_t *card) +{ + assert(card); + assert(card->host); + + sdspi_host_t *host; + sdspi_command_t command = {0}; + uint32_t retryCount = 200U; + + host = card->host; + /* SD card will enter SPI mode if the CS is asserted (negative) during the reception of the reset command (CMD0) + and the card will be IDLE state. */ + while (retryCount--) + { + command.index = kSDMMC_GoIdleState; + command.responseType = kSDSPI_ResponseTypeR1; + if ((kStatus_Success == SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) && + (command.response[0U] == kSDSPI_R1InIdleStateFlag)) + { + break; + } + } + + return kStatus_Success; +} + +static status_t SDSPI_SendInterfaceCondition(sdspi_card_t *card, uint8_t pattern, uint8_t *response) +{ + assert(card); + assert(card->host); + + sdspi_command_t command = {0}; + sdspi_host_t *host; + + host = card->host; + command.index = kSD_SendInterfaceCondition; + command.argument = (0x100U | (pattern & 0xFFU)); + command.responseType = kSDSPI_ResponseTypeR7; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + memcpy(response, command.response, sizeof(command.response)); + + return kStatus_Success; +} + +static status_t SDSPI_SendApplicationCmd(sdspi_card_t *card) +{ + assert(card); + assert(card->host); + + sdspi_host_t *host; + sdspi_command_t command = {0}; + + host = card->host; + command.index = kSDMMC_ApplicationCommand; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if ((command.response[0U]) && (!(command.response[0U] & kSDSPI_R1InIdleStateFlag))) + { + return kStatus_SDSPI_ResponseError; + } + + return kStatus_Success; +} + +static status_t SDSPI_ApplicationSendOperationCondition(sdspi_card_t *card, uint32_t argument, uint8_t *response) +{ + assert(card); + assert(card->host); + assert(response); + + sdspi_command_t command = {0}; + uint32_t startTime; + uint32_t currentTime; + uint32_t elapsedTime = 0U; + sdspi_host_t *host; + + host = card->host; + command.index = kSD_ApplicationSendOperationCondition; + command.argument = argument; + command.responseType = kSDSPI_ResponseTypeR1; + startTime = host->getCurrentMilliseconds(); + do + { + if (kStatus_Success == SDSPI_SendApplicationCmd(card)) + { + if (kStatus_Success == SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + if (!command.response[0U]) + { + break; + } + } + } + + currentTime = host->getCurrentMilliseconds(); + elapsedTime = (currentTime - startTime); + } while (elapsedTime < FSL_SDSPI_TIMEOUT); + + if (response) + { + memcpy(response, command.response, sizeof(command.response)); + } + if (elapsedTime < FSL_SDSPI_TIMEOUT) + { + return kStatus_Success; + } + + return kStatus_Timeout; +} + +static status_t SDSPI_ReadOcr(sdspi_card_t *card) +{ + assert(card); + assert(card->host); + + uint32_t i; + sdspi_host_t *host; + sdspi_command_t command = {0}; + + host = card->host; + command.index = kSDMMC_ReadOcr; + command.responseType = kSDSPI_ResponseTypeR3; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (command.response[0U]) + { + return kStatus_SDSPI_ResponseError; + } + + /* Switch the bytes sequence. All register's content is transferred from highest byte to lowest byte. */ + card->ocr = 0U; + for (i = 4U; i > 0U; i--) + { + card->ocr |= (uint32_t)command.response[i] << ((4U - i) * 8U); + } + + return kStatus_Success; +} + +static status_t SDSPI_SetBlockSize(sdspi_card_t *card, uint32_t blockSize) +{ + assert(card); + assert(card->host); + + sdspi_command_t command = {0}; + sdspi_host_t *host; + + host = card->host; + command.index = kSDMMC_SetBlockLength; + command.argument = blockSize; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + return kStatus_Success; +} + +static status_t SDSPI_Read(sdspi_host_t *host, uint8_t *buffer, uint32_t size) +{ + assert(host); + assert(host->exchange); + assert(buffer); + assert(size); + + uint32_t startTime; + uint32_t currentTime; + uint32_t elapsedTime; + uint8_t response, i; + uint8_t timingByte = 0xFFU; /* The byte need to be sent as read/write data block timing requirement */ + + memset(buffer, 0xFFU, size); + + /* Wait data token comming */ + startTime = host->getCurrentMilliseconds(); + do + { + if (kStatus_Success != host->exchange(&timingByte, &response, 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + + currentTime = host->getCurrentMilliseconds(); + elapsedTime = (currentTime - startTime); + } while ((response == 0xFFU) && (elapsedTime < 100U)); + + /* Check data token and exchange data. */ + if (response != kSDSPI_DataTokenBlockRead) + { + return kStatus_SDSPI_ResponseError; + } + if (host->exchange(buffer, buffer, size)) + { + return kStatus_SDSPI_ExchangeFailed; + } + + /* Get 16 bit CRC */ + for (i = 0U; i < 2U; i++) + { + if (kStatus_Success != host->exchange(&timingByte, &response, 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + } + + return kStatus_Success; +} + +static void SDSPI_DecodeCsd(sdspi_card_t *card, uint8_t *rawCsd) +{ + assert(rawCsd); + assert(card); + + sd_csd_t *csd; + + csd = &(card->csd); + csd->csdStructure = (rawCsd[0U] >> 6U); + csd->dataReadAccessTime1 = rawCsd[1U]; + csd->dataReadAccessTime2 = rawCsd[2U]; + csd->transferSpeed = rawCsd[3U]; + csd->cardCommandClass = (((uint32_t)rawCsd[4U] << 4U) | ((uint32_t)rawCsd[5U] >> 4U)); + csd->readBlockLength = ((rawCsd)[5U] & 0xFU); + if (rawCsd[6U] & 0x80U) + { + csd->flags |= kSD_CsdReadBlockPartialFlag; + } + if (rawCsd[6U] & 0x40U) + { + csd->flags |= kSD_CsdWriteBlockMisalignFlag; + } + if (rawCsd[6U] & 0x20U) + { + csd->flags |= kSD_CsdReadBlockMisalignFlag; + } + if (rawCsd[6U] & 0x10U) + { + csd->flags |= kSD_CsdDsrImplementedFlag; + } + + /* Some fileds is different when csdStructure is different. */ + if (csd->csdStructure == 0U) /* Decode the bits when CSD structure is version 1.0 */ + { + csd->deviceSize = + ((((uint32_t)rawCsd[6] & 0x3U) << 10U) | ((uint32_t)rawCsd[7U] << 2U) | ((uint32_t)rawCsd[8U] >> 6U)); + csd->readCurrentVddMin = ((rawCsd[8U] >> 3U) & 7U); + csd->readCurrentVddMax = (rawCsd[8U] >> 7U); + csd->writeCurrentVddMin = ((rawCsd[9U] >> 5U) & 7U); + csd->writeCurrentVddMax = (rawCsd[9U] >> 2U); + csd->deviceSizeMultiplier = (((rawCsd[9U] & 3U) << 1U) | (rawCsd[10U] >> 7U)); + card->blockCount = (csd->deviceSize + 1U) << (csd->deviceSizeMultiplier + 2U); + card->blockSize = (1U << (csd->readBlockLength)); + if (card->blockSize != FSL_SDSPI_DEFAULT_BLOCK_SIZE) + { + card->blockCount = (card->blockCount * card->blockSize); + card->blockSize = FSL_SDSPI_DEFAULT_BLOCK_SIZE; + card->blockCount = (card->blockCount / card->blockSize); + } + } + else if (csd->csdStructure == 1U) /* Decode the bits when CSD structure is version 2.0 */ + { + card->blockSize = FSL_SDSPI_DEFAULT_BLOCK_SIZE; + csd->deviceSize = + ((((uint32_t)rawCsd[7U] & 0x3FU) << 16U) | ((uint32_t)rawCsd[8U] << 8U) | ((uint32_t)rawCsd[9U])); + if (csd->deviceSize >= 0xFFFFU) + { + card->flags |= kSDSPI_SupportSdxcFlag; + } + card->blockCount = ((csd->deviceSize + 1U) * 1024U); + } + else + { + } + + if ((rawCsd[10U] >> 6U) & 1U) + { + csd->flags |= kSD_CsdEraseBlockEnabledFlag; + } + csd->eraseSectorSize = (((rawCsd[10U] & 0x3FU) << 1U) | (rawCsd[11U] >> 7U)); + csd->writeProtectGroupSize = (rawCsd[11U] & 0x7FU); + if (rawCsd[12U] >> 7U) + { + csd->flags |= kSD_CsdWriteProtectGroupEnabledFlag; + } + csd->writeSpeedFactor = ((rawCsd[12U] >> 2U) & 7U); + csd->writeBlockLength = (((rawCsd[12U] & 3U) << 2U) | (rawCsd[13U] >> 6U)); + if ((rawCsd[13U] >> 5U) & 1U) + { + csd->flags |= kSD_CsdWriteBlockPartialFlag; + } + if (rawCsd[14U] >> 7U) + { + csd->flags |= kSD_CsdFileFormatGroupFlag; + } + if ((rawCsd[14U] >> 6U) & 1U) + { + csd->flags |= kSD_CsdCopyFlag; + } + if ((rawCsd[14U] >> 5U) & 1U) + { + csd->flags |= kSD_CsdPermanentWriteProtectFlag; + } + if ((rawCsd[14U] >> 4U) & 1U) + { + csd->flags |= kSD_CsdTemporaryWriteProtectFlag; + } + csd->fileFormat = ((rawCsd[14U] >> 2U) & 3U); +} + +static status_t SDSPI_SendCsd(sdspi_card_t *card) +{ + assert(card); + assert(card->host); + + sdspi_command_t command = {0}; + sdspi_host_t *host; + + host = card->host; + command.index = kSDMMC_SendCsd; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (kStatus_Success != SDSPI_Read(host, card->rawCsd, sizeof(card->rawCsd))) + { + return kStatus_SDSPI_ReadFailed; + } + + SDSPI_DecodeCsd(card, card->rawCsd); + + return kStatus_Success; +} + +static status_t SDSPI_SetMaxFrequencyNormalMode(sdspi_card_t *card) +{ + uint32_t maxFrequency; + + /* Calculate max frequency card supported in non-high-speed mode. */ + maxFrequency = g_transferSpeedRateUnit[SD_RD_TRANSFER_SPEED_RATE_UNIT(card->csd)] * + g_transferSpeedMultiplierFactor[SD_RD_TRANSFER_SPEED_TIME_VALUE(card->csd)]; + if (maxFrequency > card->host->busBaudRate) + { + maxFrequency = card->host->busBaudRate; + } + + if (kStatus_Success != card->host->setFrequency(maxFrequency)) + { + return kStatus_SDSPI_SetFrequencyFailed; + } + + return kStatus_Success; +} + +static void SDSPI_CheckCapacity(sdspi_card_t *card) +{ + uint32_t deviceSize; + uint32_t deviceSizeMultiplier; + uint32_t readBlockLength; + + if (card->csd.csdStructure) + { + /* SD CSD structure v2.xx */ + deviceSize = card->csd.deviceSize; + if (deviceSize >= 0xFFFFU) /* Bigger than 32GB */ + { + /* extended capacity */ + card->flags |= kSDSPI_SupportSdxcFlag; + } + else + { + card->flags |= kSDSPI_SupportSdhcFlag; + } + deviceSizeMultiplier = 10U; + deviceSize += 1U; + readBlockLength = 9U; + } + else + { + /* SD CSD structure v1.xx */ + deviceSize = (card->csd.deviceSize + 1U); + deviceSizeMultiplier = (card->csd.deviceSizeMultiplier + 2U); + readBlockLength = card->csd.readBlockLength; + /* Card maximum capacity is 2GB when CSD structure version is 1.0 */ + card->flags |= kSDSPI_SupportSdscFlag; + } + if (readBlockLength != 9U) + { + /* Force to use 512-byte length block */ + deviceSizeMultiplier += (readBlockLength - 9U); + readBlockLength = 9U; + } + + card->blockSize = (1U << readBlockLength); + card->blockCount = (deviceSize << deviceSizeMultiplier); +} + +static void SDSPI_DecodeCid(sdspi_card_t *card, uint8_t *rawCid) +{ + assert(card); + assert(rawCid); + + sd_cid_t *cid = &(card->cid); + cid->manufacturerID = rawCid[0U]; + cid->applicationID = (((uint32_t)rawCid[1U] << 8U) | (uint32_t)(rawCid[2U])); + memcpy(cid->productName, &rawCid[3U], SD_PRODUCT_NAME_BYTES); + cid->productVersion = rawCid[8U]; + cid->productSerialNumber = (((uint32_t)rawCid[9U] << 24U) | ((uint32_t)rawCid[10U] << 16U) | + ((uint32_t)rawCid[11U] << 8U) | ((uint32_t)rawCid[12U])); + cid->manufacturerData = ((((uint32_t)rawCid[13U] & 0x0FU) << 8U) | ((uint32_t)rawCid[14U])); +} + +static status_t SDSPI_SendCid(sdspi_card_t *card) +{ + assert(card); + assert(card->host); + + sdspi_command_t command = {0}; + sdspi_host_t *host; + + host = card->host; + command.index = kSDMMC_SendCid; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (kStatus_Success != (SDSPI_Read(host, card->rawCid, sizeof(card->rawCid)))) + { + return kStatus_SDSPI_ReadFailed; + } + + SDSPI_DecodeCid(card, card->rawCid); + + return kStatus_Success; +} + +static void SDSPI_DecodeScr(sdspi_card_t *card, uint8_t *rawScr) +{ + assert(card); + assert(rawScr); + + sd_scr_t *scr = &(card->scr); + scr->scrStructure = ((rawScr[0U] & 0xF0U) >> 4U); + scr->sdSpecification = (rawScr[0U] & 0x0FU); + if (rawScr[1U] & 0x80U) + { + scr->flags |= kSD_ScrDataStatusAfterErase; + } + scr->sdSecurity = ((rawScr[1U] & 0x70U) >> 4U); + scr->sdBusWidths = (rawScr[1U] & 0x0FU); + if (rawScr[2U] & 0x80U) + { + scr->flags |= kSD_ScrSdSpecification3; + } + scr->extendedSecurity = ((rawScr[2U] & 0x78U) >> 3U); + scr->commandSupport = (rawScr[3U] & 0x03U); + scr->reservedForManufacturer = (((uint32_t)rawScr[4U] << 24U) | ((uint32_t)rawScr[5U] << 16U) | + ((uint32_t)rawScr[6U] << 8U) | (uint32_t)rawScr[7U]); +} + +static status_t SDSPI_SendScr(sdspi_card_t *card) +{ + assert(card); + assert(card->host); + + sdspi_command_t command = {0}; + sdspi_host_t *host; + + host = card->host; + if (kStatus_Success != SDSPI_SendApplicationCmd(card)) + { + return kStatus_SDSPI_SendApplicationCommandFailed; + } + + command.index = kSD_ApplicationSendScr; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (kStatus_Success != (SDSPI_Read(host, card->rawScr, sizeof(card->rawScr)))) + { + return kStatus_SDSPI_ReadFailed; + } + + SDSPI_DecodeScr(card, card->rawScr); + + return kStatus_Success; +} + +static status_t SDSPI_StopTransmission(sdspi_card_t *card) +{ + sdspi_command_t command = {0}; + sdspi_host_t *host; + + host = card->host; + command.index = kSDMMC_StopTransmission; + command.responseType = kSDSPI_ResponseTypeR1b; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + return kStatus_Success; +} + +static status_t SDSPI_Write(sdspi_host_t *host, uint8_t *buffer, uint32_t size, uint8_t token) +{ + assert(host); + assert(host->exchange); + + uint8_t response; + uint8_t i; + uint8_t timingByte = 0xFFU; /* The byte need to be sent as read/write data block timing requirement */ + + if (kStatus_Success != SDSPI_WaitReady(host, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_WaitReadyFailed; + } + + /* Write data token. */ + if (host->exchange(&token, NULL, 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + if (token == kSDSPI_DataTokenStopTransfer) + { + return kStatus_Success; + } + + if ((!size) || (!buffer)) + { + return kStatus_InvalidArgument; + } + + /* Write data. */ + if (kStatus_Success != host->exchange(buffer, NULL, size)) + { + return kStatus_SDSPI_ExchangeFailed; + } + + /* Get the last two bytes CRC */ + for (i = 0U; i < 2U; i++) + { + if (host->exchange(&timingByte, NULL, 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + } + + /* Get the response token. */ + if (host->exchange(&timingByte, &response, 1U)) + { + return kStatus_SDSPI_ExchangeFailed; + } + if ((response & SDSPI_DATA_RESPONSE_TOKEN_MASK) != kSDSPI_DataResponseTokenAccepted) + { + return kStatus_SDSPI_ResponseError; + } + + return kStatus_Success; +} + +status_t SDSPI_Init(sdspi_card_t *card) +{ + assert(card); + assert(card->host); + assert(card->host->setFrequency); + assert(card->host->exchange); + assert(card->host->getCurrentMilliseconds); + + sdspi_host_t *host; + uint32_t applicationCommand41Argument = 0U; + uint32_t startTime; + uint32_t currentTime; + uint32_t elapsedTime; + uint8_t response[5U]; + uint8_t applicationCommand41Response[5U]; + bool likelySdV1 = false; + + host = card->host; + /* Card must be initialized in 400KHZ. */ + if (host->setFrequency(SDMMC_CLOCK_400KHZ)) + { + return kStatus_SDSPI_SetFrequencyFailed; + } + + /* Reset the card by CMD0. */ + if (kStatus_Success != SDSPI_GoIdle(card)) + { + return kStatus_SDSPI_GoIdleFailed; + } + + /* Check the card's supported interface condition. */ + if (kStatus_Success != SDSPI_SendInterfaceCondition(card, 0xAAU, response)) + { + likelySdV1 = true; + } + else if ((response[3U] == 0x1U) || (response[4U] == 0xAAU)) + { + applicationCommand41Argument |= kSD_OcrHostCapacitySupportFlag; + } + else + { + return kStatus_SDSPI_SendInterfaceConditionFailed; + } + + /* Set card's interface condition according to host's capability and card's supported interface condition */ + startTime = host->getCurrentMilliseconds(); + do + { + if (kStatus_Success != + SDSPI_ApplicationSendOperationCondition(card, applicationCommand41Argument, applicationCommand41Response)) + { + return kStatus_SDSPI_SendOperationConditionFailed; + } + + currentTime = host->getCurrentMilliseconds(); + elapsedTime = (currentTime - startTime); + if (elapsedTime > 500U) + { + return kStatus_Timeout; + } + + if (!applicationCommand41Response[0U]) + { + break; + } + } while (applicationCommand41Response[0U] & kSDSPI_R1InIdleStateFlag); + + if (!likelySdV1) + { + if (kStatus_Success != SDSPI_ReadOcr(card)) + { + return kStatus_SDSPI_ReadOcrFailed; + } + if (card->ocr & kSD_OcrCardCapacitySupportFlag) + { + card->flags |= kSDSPI_SupportHighCapacityFlag; + } + } + + /* Force to use 512-byte length block, no matter which version. */ + if (kStatus_Success != SDSPI_SetBlockSize(card, 512U)) + { + return kStatus_SDSPI_SetBlockSizeFailed; + } + if (kStatus_Success != SDSPI_SendCsd(card)) + { + return kStatus_SDSPI_SendCsdFailed; + } + + /* Set to max frequency according to the max frequency information in CSD register. */ + SDSPI_SetMaxFrequencyNormalMode(card); + + /* Save capacity, read only attribute and CID, SCR registers. */ + SDSPI_CheckCapacity(card); + SDSPI_CheckReadOnly(card); + if (kStatus_Success != SDSPI_SendCid(card)) + { + return kStatus_SDSPI_SendCidFailed; + } + if (kStatus_Success != SDSPI_SendScr(card)) + { + return kStatus_SDSPI_SendCidFailed; + } + + return kStatus_Success; +} + +void SDSPI_Deinit(sdspi_card_t *card) +{ + assert(card); + + memset(card, 0, sizeof(sdspi_card_t)); +} + +bool SDSPI_CheckReadOnly(sdspi_card_t *card) +{ + assert(card); + + if ((card->csd.flags & kSD_CsdPermanentWriteProtectFlag) || (card->csd.flags & kSD_CsdTemporaryWriteProtectFlag)) + { + return true; + } + + return false; +} + +status_t SDSPI_ReadBlocks(sdspi_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(card->host); + assert(buffer); + assert(blockCount); + + uint32_t offset; + uint32_t i; + sdspi_command_t command = {0}; + sdspi_host_t *host; + + offset = startBlock; + if (!IS_BLOCK_ACCESS(card)) + { + offset *= card->blockSize; + } + + /* Send command and reads data. */ + host = card->host; + command.argument = offset; + command.responseType = kSDSPI_ResponseTypeR1; + if (blockCount == 1U) + { + command.index = kSDMMC_ReadSingleBlock; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (kStatus_Success != SDSPI_Read(host, buffer, card->blockSize)) + { + return kStatus_SDSPI_ReadFailed; + } + } + else + { + command.index = kSDMMC_ReadMultipleBlock; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + for (i = 0U; i < blockCount; i++) + { + if (kStatus_Success != SDSPI_Read(host, buffer, card->blockSize)) + { + return kStatus_SDSPI_ReadFailed; + } + buffer += card->blockSize; + } + + /* Write stop transmission command after the last data block. */ + if (kStatus_Success != SDSPI_StopTransmission(card)) + { + return kStatus_SDSPI_StopTransmissionFailed; + } + } + + return kStatus_Success; +} + +status_t SDSPI_WriteBlocks(sdspi_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card); + assert(card->host); + assert(buffer); + assert(blockCount); + + uint32_t offset; + uint32_t i; + sdspi_host_t *host; + sdspi_command_t command = {0}; + + if (SDSPI_CheckReadOnly(card)) + { + return kStatus_SDSPI_WriteProtected; + } + + offset = startBlock; + if (!IS_BLOCK_ACCESS(card)) + { + offset *= card->blockSize; + } + + /* Send command and writes data. */ + host = card->host; + if (blockCount == 1U) + { + command.index = kSDMMC_WriteSingleBlock; + command.argument = offset; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (command.response[0U]) + { + return kStatus_SDSPI_ResponseError; + } + + if (kStatus_Success != SDSPI_Write(host, buffer, card->blockSize, kSDSPI_DataTokenSingleBlockWrite)) + { + return kStatus_SDSPI_WriteFailed; + } + } + else + { +#if defined FSL_SDSPI_ENABLE_PRE_ERASE_ON_WRITE + /* Pre-erase before writing data */ + if (kStatus_Success != SDSPI_SendApplicationCmd(card)) + { + return kStatus_SDSPI_SendApplicationCommandFailed; + } + + command.index = kSDAppSetWrBlkEraseCount; + command.argument = blockCount; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host->base, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (req->response[0U]) + { + return kStatus_SDSPI_ResponseError; + } +#endif + + memset(&command, 0U, sizeof(sdspi_command_t)); + command.index = kSDMMC_WriteMultipleBlock; + command.argument = offset; + command.responseType = kSDSPI_ResponseTypeR1; + if (kStatus_Success != SDSPI_SendCommand(host, &command, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_SendCommandFailed; + } + + if (command.response[0U]) + { + return kStatus_SDSPI_ResponseError; + } + + for (i = 0U; i < blockCount; i++) + { + if (kStatus_Success != SDSPI_Write(host, buffer, card->blockSize, kSDSPI_DataTokenMultipleBlockWrite)) + { + return kStatus_SDSPI_WriteFailed; + } + buffer += card->blockSize; + } + if (kStatus_Success != SDSPI_Write(host, 0U, 0U, kSDSPI_DataTokenStopTransfer)) + { + return kStatus_SDSPI_WriteFailed; + } + + /* Wait the card programming end. */ + if (kStatus_Success != SDSPI_WaitReady(host, FSL_SDSPI_TIMEOUT)) + { + return kStatus_SDSPI_WaitReadyFailed; + } + } + + return kStatus_Success; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdspi.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdspi.h new file mode 100644 index 0000000000..ee5c8a71f7 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_sdspi.h @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SDSPI_H_ +#define _FSL_SDSPI_H_ + +#include "fsl_common.h" +#include "fsl_specification.h" + +/****************************************************************************** + * Definitions + *****************************************************************************/ +/*! @brief Driver version. */ +#define FSL_SDSPI_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 1U)) /*2.1.1*/ + +/*! @brief Default block size */ +#define FSL_SDSPI_DEFAULT_BLOCK_SIZE (512U) + +/*! + * @addtogroup SDSPI + * @{ + */ + +/*! @brief SDSPI API status */ +enum _sdspi_status +{ + kStatus_SDSPI_SetFrequencyFailed = MAKE_STATUS(kStatusGroup_SDSPI, 0U), /*!< Set frequency failed */ + kStatus_SDSPI_ExchangeFailed = MAKE_STATUS(kStatusGroup_SDSPI, 1U), /*!< Exchange data on SPI bus failed */ + kStatus_SDSPI_WaitReadyFailed = MAKE_STATUS(kStatusGroup_SDSPI, 2U), /*!< Wait card ready failed */ + kStatus_SDSPI_ResponseError = MAKE_STATUS(kStatusGroup_SDSPI, 3U), /*!< Response is error */ + kStatus_SDSPI_WriteProtected = MAKE_STATUS(kStatusGroup_SDSPI, 4U), /*!< Write protected */ + kStatus_SDSPI_GoIdleFailed = MAKE_STATUS(kStatusGroup_SDSPI, 5U), /*!< Go idle failed */ + kStatus_SDSPI_SendCommandFailed = MAKE_STATUS(kStatusGroup_SDSPI, 6U), /*!< Send command failed */ + kStatus_SDSPI_ReadFailed = MAKE_STATUS(kStatusGroup_SDSPI, 7U), /*!< Read data failed */ + kStatus_SDSPI_WriteFailed = MAKE_STATUS(kStatusGroup_SDSPI, 8U), /*!< Write data failed */ + kStatus_SDSPI_SendInterfaceConditionFailed = + MAKE_STATUS(kStatusGroup_SDSPI, 9U), /*!< Send interface condition failed */ + kStatus_SDSPI_SendOperationConditionFailed = + MAKE_STATUS(kStatusGroup_SDSPI, 10U), /*!< Send operation condition failed */ + kStatus_SDSPI_ReadOcrFailed = MAKE_STATUS(kStatusGroup_SDSPI, 11U), /*!< Read OCR failed */ + kStatus_SDSPI_SetBlockSizeFailed = MAKE_STATUS(kStatusGroup_SDSPI, 12U), /*!< Set block size failed */ + kStatus_SDSPI_SendCsdFailed = MAKE_STATUS(kStatusGroup_SDSPI, 13U), /*!< Send CSD failed */ + kStatus_SDSPI_SendCidFailed = MAKE_STATUS(kStatusGroup_SDSPI, 14U), /*!< Send CID failed */ + kStatus_SDSPI_StopTransmissionFailed = MAKE_STATUS(kStatusGroup_SDSPI, 15U), /*!< Stop transmission failed */ + kStatus_SDSPI_SendApplicationCommandFailed = + MAKE_STATUS(kStatusGroup_SDSPI, 16U), /*!< Send application command failed */ +}; + +/*! @brief SDSPI card flag */ +enum _sdspi_card_flag +{ + kSDSPI_SupportHighCapacityFlag = (1U << 0U), /*!< Card is high capacity */ + kSDSPI_SupportSdhcFlag = (1U << 1U), /*!< Card is SDHC */ + kSDSPI_SupportSdxcFlag = (1U << 2U), /*!< Card is SDXC */ + kSDSPI_SupportSdscFlag = (1U << 3U), /*!< Card is SDSC */ +}; + +/*! @brief SDSPI response type */ +typedef enum _sdspi_response_type +{ + kSDSPI_ResponseTypeR1 = 0U, /*!< Response 1 */ + kSDSPI_ResponseTypeR1b = 1U, /*!< Response 1 with busy */ + kSDSPI_ResponseTypeR2 = 2U, /*!< Response 2 */ + kSDSPI_ResponseTypeR3 = 3U, /*!< Response 3 */ + kSDSPI_ResponseTypeR7 = 4U, /*!< Response 7 */ +} sdspi_response_type_t; + +/*! @brief SDSPI command */ +typedef struct _sdspi_command +{ + uint8_t index; /*!< Command index */ + uint32_t argument; /*!< Command argument */ + uint8_t responseType; /*!< Response type */ + uint8_t response[5U]; /*!< Response content */ +} sdspi_command_t; + +/*! @brief SDSPI host state. */ +typedef struct _sdspi_host +{ + uint32_t busBaudRate; /*!< Bus baud rate */ + + status_t (*setFrequency)(uint32_t frequency); /*!< Set frequency of SPI */ + status_t (*exchange)(uint8_t *in, uint8_t *out, uint32_t size); /*!< Exchange data over SPI */ + uint32_t (*getCurrentMilliseconds)(void); /*!< Get current time in milliseconds */ +} sdspi_host_t; + +/*! + * @brief SD Card Structure + * + * Define the card structure including the necessary fields to identify and describe the card. + */ +typedef struct _sdspi_card +{ + sdspi_host_t *host; /*!< Host state information */ + uint32_t relativeAddress; /*!< Relative address of the card */ + uint32_t flags; /*!< Flags defined in _sdspi_card_flag. */ + uint8_t rawCid[16U]; /*!< Raw CID content */ + uint8_t rawCsd[16U]; /*!< Raw CSD content */ + uint8_t rawScr[8U]; /*!< Raw SCR content */ + uint32_t ocr; /*!< Raw OCR content */ + sd_cid_t cid; /*!< CID */ + sd_csd_t csd; /*!< CSD */ + sd_scr_t scr; /*!< SCR */ + uint32_t blockCount; /*!< Card total block number */ + uint32_t blockSize; /*!< Card block size */ +} sdspi_card_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SDSPI Function + * @{ + */ + +/*! + * @brief Initializes the card on a specific SPI instance. + * + * This function initializes the card on a specific SPI instance. + * + * @param card Card descriptor + * @retval kStatus_SDSPI_SetFrequencyFailed Set frequency failed. + * @retval kStatus_SDSPI_GoIdleFailed Go idle failed. + * @retval kStatus_SDSPI_SendInterfaceConditionFailed Send interface condition failed. + * @retval kStatus_SDSPI_SendOperationConditionFailed Send operation condition failed. + * @retval kStatus_Timeout Send command timeout. + * @retval kStatus_SDSPI_NotSupportYet Not support yet. + * @retval kStatus_SDSPI_ReadOcrFailed Read OCR failed. + * @retval kStatus_SDSPI_SetBlockSizeFailed Set block size failed. + * @retval kStatus_SDSPI_SendCsdFailed Send CSD failed. + * @retval kStatus_SDSPI_SendCidFailed Send CID failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDSPI_Init(sdspi_card_t *card); + +/*! + * @brief Deinitializes the card. + * + * This function deinitializes the specific card. + * + * @param card Card descriptor + */ +void SDSPI_Deinit(sdspi_card_t *card); + +/*! + * @brief Checks whether the card is write-protected. + * + * This function checks if the card is write-protected via CSD register. + * + * @param card Card descriptor. + * @retval true Card is read only. + * @retval false Card isn't read only. + */ +bool SDSPI_CheckReadOnly(sdspi_card_t *card); + +/*! + * @brief Reads blocks from the specific card. + * + * This function reads blocks from specific card. + * + * @param card Card descriptor. + * @param buffer the buffer to hold the data read from card + * @param startBlock the start block index + * @param blockCount the number of blocks to read + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ReadFailed Read data failed. + * @retval kStatus_SDSPI_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDSPI_ReadBlocks(sdspi_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Writes blocks of data to the specific card. + * + * This function writes blocks to specific card + * + * @param card Card descriptor. + * @param buffer the buffer holding the data to be written to the card + * @param startBlock the start block index + * @param blockCount the number of blocks to write + * @retval kStatus_SDSPI_WriteProtected Card is write protected. + * @retval kStatus_SDSPI_SendCommandFailed Send command failed. + * @retval kStatus_SDSPI_ResponseError Response is error. + * @retval kStatus_SDSPI_WriteFailed Write data failed. + * @retval kStatus_SDSPI_ExchangeFailed Exchange data over SPI failed. + * @retval kStatus_SDSPI_WaitReadyFailed Wait card to be ready status failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDSPI_WriteBlocks(sdspi_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! @} */ +#endif /* _FSL_SDSPI_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_specification.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_specification.h new file mode 100644 index 0000000000..1320b20229 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/fsl_specification.h @@ -0,0 +1,1080 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SPECIFICATION_H_ +#define _FSL_SPECIFICATION_H_ + +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief SD/MMC card initialization clock frequency */ +#define SDMMC_CLOCK_400KHZ (400000U) +/*! @brief SD card bus frequency 1 in high-speed mode */ +#define SD_CLOCK_25MHZ (25000000U) +/*! @brief SD card bus frequency 2 in high-speed mode */ +#define SD_CLOCK_50MHZ (50000000U) +/*! @brief SD card bus frequency in SDR50 mode */ +#define SD_CLOCK_100MHZ (100000000U) +/*! @brief SD card bus frequency in SDR104 mode */ +#define SD_CLOCK_208MHZ (208000000U) +/*! @brief MMC card bus frequency 1 in high-speed mode */ +#define MMC_CLOCK_26MHZ (26000000U) +/*! @brief MMC card bus frequency 2 in high-speed mode */ +#define MMC_CLOCK_52MHZ (52000000U) +/*! @brief MMC card bus frequency in high-speed DDR52 mode */ +#define MMC_CLOCK_DDR52 (104000000U) +/*! @brief MMC card bus frequency in high-speed HS200 mode */ +#define MMC_CLOCK_HS200 (200000000U) +/*! @brief MMC card bus frequency in high-speed HS400 mode */ +#define MMC_CLOCK_HS400 (400000000U) + +/*! @brief Card status bit in R1 */ +enum _sdmmc_r1_card_status_flag +{ + kSDMMC_R1OutOfRangeFlag = (1U << 31U), /*!< Out of range status bit */ + kSDMMC_R1AddressErrorFlag = (1U << 30U), /*!< Address error status bit */ + kSDMMC_R1BlockLengthErrorFlag = (1U << 29U), /*!< Block length error status bit */ + kSDMMC_R1EraseSequenceErrorFlag = (1U << 28U), /*!< Erase sequence error status bit */ + kSDMMC_R1EraseParameterErrorFlag = (1U << 27U), /*!< Erase parameter error status bit */ + kSDMMC_R1WriteProtectViolationFlag = (1U << 26U), /*!< Write protection violation status bit */ + kSDMMC_R1CardIsLockedFlag = (1U << 25U), /*!< Card locked status bit */ + kSDMMC_R1LockUnlockFailedFlag = (1U << 24U), /*!< lock/unlock error status bit */ + kSDMMC_R1CommandCrcErrorFlag = (1U << 23U), /*!< CRC error status bit */ + kSDMMC_R1IllegalCommandFlag = (1U << 22U), /*!< Illegal command status bit */ + kSDMMC_R1CardEccFailedFlag = (1U << 21U), /*!< Card ecc error status bit */ + kSDMMC_R1CardControllerErrorFlag = (1U << 20U), /*!< Internal card controller error status bit */ + kSDMMC_R1ErrorFlag = (1U << 19U), /*!< A general or an unknown error status bit */ + kSDMMC_R1CidCsdOverwriteFlag = (1U << 16U), /*!< Cid/csd overwrite status bit */ + kSDMMC_R1WriteProtectEraseSkipFlag = (1U << 15U), /*!< Write protection erase skip status bit */ + kSDMMC_R1CardEccDisabledFlag = (1U << 14U), /*!< Card ecc disabled status bit */ + kSDMMC_R1EraseResetFlag = (1U << 13U), /*!< Erase reset status bit */ + kSDMMC_R1ReadyForDataFlag = (1U << 8U), /*!< Ready for data status bit */ + kSDMMC_R1SwitchErrorFlag = (1U << 7U), /*!< Switch error status bit */ + kSDMMC_R1ApplicationCommandFlag = (1U << 5U), /*!< Application command enabled status bit */ + kSDMMC_R1AuthenticationSequenceErrorFlag = (1U << 3U), /*!< error in the sequence of authentication process */ + + kSDMMC_R1ErrorAllFlag = + (kSDMMC_R1OutOfRangeFlag | kSDMMC_R1AddressErrorFlag | kSDMMC_R1BlockLengthErrorFlag | + kSDMMC_R1EraseSequenceErrorFlag | kSDMMC_R1EraseParameterErrorFlag | kSDMMC_R1WriteProtectViolationFlag | + kSDMMC_R1CardIsLockedFlag | kSDMMC_R1LockUnlockFailedFlag | kSDMMC_R1CommandCrcErrorFlag | + kSDMMC_R1IllegalCommandFlag | kSDMMC_R1CardEccFailedFlag | kSDMMC_R1CardControllerErrorFlag | + kSDMMC_R1ErrorFlag | kSDMMC_R1CidCsdOverwriteFlag | + kSDMMC_R1AuthenticationSequenceErrorFlag), /*!< Card error status */ +}; + +/*! @brief R1: current state */ +#define SDMMC_R1_CURRENT_STATE(x) (((x)&0x00001E00U) >> 9U) + +/*! @brief CURRENT_STATE filed in R1 */ +typedef enum _sdmmc_r1_current_state +{ + kSDMMC_R1StateIdle = 0U, /*!< R1: current state: idle */ + kSDMMC_R1StateReady = 1U, /*!< R1: current state: ready */ + kSDMMC_R1StateIdentify = 2U, /*!< R1: current state: identification */ + kSDMMC_R1StateStandby = 3U, /*!< R1: current state: standby */ + kSDMMC_R1StateTransfer = 4U, /*!< R1: current state: transfer */ + kSDMMC_R1StateSendData = 5U, /*!< R1: current state: sending data */ + kSDMMC_R1StateReceiveData = 6U, /*!< R1: current state: receiving data */ + kSDMMC_R1StateProgram = 7U, /*!< R1: current state: programming */ + kSDMMC_R1StateDisconnect = 8U, /*!< R1: current state: disconnect */ +} sdmmc_r1_current_state_t; + +/*! @brief Error bit in SPI mode R1 */ +enum _sdspi_r1_error_status_flag +{ + kSDSPI_R1InIdleStateFlag = (1U << 0U), /*!< In idle state */ + kSDSPI_R1EraseResetFlag = (1U << 1U), /*!< Erase reset */ + kSDSPI_R1IllegalCommandFlag = (1U << 2U), /*!< Illegal command */ + kSDSPI_R1CommandCrcErrorFlag = (1U << 3U), /*!< Com crc error */ + kSDSPI_R1EraseSequenceErrorFlag = (1U << 4U), /*!< Erase sequence error */ + kSDSPI_R1AddressErrorFlag = (1U << 5U), /*!< Address error */ + kSDSPI_R1ParameterErrorFlag = (1U << 6U), /*!< Parameter error */ +}; + +/*! @brief Error bit in SPI mode R2 */ +enum _sdspi_r2_error_status_flag +{ + kSDSPI_R2CardLockedFlag = (1U << 0U), /*!< Card is locked */ + kSDSPI_R2WriteProtectEraseSkip = (1U << 1U), /*!< Write protect erase skip */ + kSDSPI_R2LockUnlockFailed = (1U << 1U), /*!< Lock/unlock command failed */ + kSDSPI_R2ErrorFlag = (1U << 2U), /*!< Unknown error */ + kSDSPI_R2CardControllerErrorFlag = (1U << 3U), /*!< Card controller error */ + kSDSPI_R2CardEccFailedFlag = (1U << 4U), /*!< Card ecc failed */ + kSDSPI_R2WriteProtectViolationFlag = (1U << 5U), /*!< Write protect violation */ + kSDSPI_R2EraseParameterErrorFlag = (1U << 6U), /*!< Erase parameter error */ + kSDSPI_R2OutOfRangeFlag = (1U << 7U), /*!< Out of range */ + kSDSPI_R2CsdOverwriteFlag = (1U << 7U), /*!< CSD overwrite */ +}; + +/*! @brief The bit mask for COMMAND VERSION field in R7 */ +#define SDSPI_R7_VERSION_SHIFT (28U) +/*! @brief The bit mask for COMMAND VERSION field in R7 */ +#define SDSPI_R7_VERSION_MASK (0xFU) +/*! @brief The bit shift for VOLTAGE ACCEPTED field in R7 */ +#define SDSPI_R7_VOLTAGE_SHIFT (8U) +/*! @brief The bit mask for VOLTAGE ACCEPTED field in R7 */ +#define SDSPI_R7_VOLTAGE_MASK (0xFU) +/*! @brief The bit mask for VOLTAGE 2.7V to 3.6V field in R7 */ +#define SDSPI_R7_VOLTAGE_27_36_MASK (0x1U << SDSPI_R7_VOLTAGE_SHIFT) +/*! @brief The bit shift for ECHO field in R7 */ +#define SDSPI_R7_ECHO_SHIFT (0U) +/*! @brief The bit mask for ECHO field in R7 */ +#define SDSPI_R7_ECHO_MASK (0xFFU) + +/*! @brief Data error token mask */ +#define SDSPI_DATA_ERROR_TOKEN_MASK (0xFU) +/*! @brief Data Error Token mask bit */ +enum _sdspi_data_error_token +{ + kSDSPI_DataErrorTokenError = (1U << 0U), /*!< Data error */ + kSDSPI_DataErrorTokenCardControllerError = (1U << 1U), /*!< Card controller error */ + kSDSPI_DataErrorTokenCardEccFailed = (1U << 2U), /*!< Card ecc error */ + kSDSPI_DataErrorTokenOutOfRange = (1U << 3U), /*!< Out of range */ +}; + +/*! @brief Data Token */ +typedef enum _sdspi_data_token +{ + kSDSPI_DataTokenBlockRead = 0xFEU, /*!< Single block read, multiple block read */ + kSDSPI_DataTokenSingleBlockWrite = 0xFEU, /*!< Single block write */ + kSDSPI_DataTokenMultipleBlockWrite = 0xFCU, /*!< Multiple block write */ + kSDSPI_DataTokenStopTransfer = 0xFDU, /*!< Stop transmission */ +} sdspi_data_token_t; + +/* Data Response Token mask */ +#define SDSPI_DATA_RESPONSE_TOKEN_MASK (0x1FU) /*!< Mask for data response bits */ +/*! @brief Data Response Token */ +typedef enum _sdspi_data_response_token +{ + kSDSPI_DataResponseTokenAccepted = 0x05U, /*!< Data accepted */ + kSDSPI_DataResponseTokenCrcError = 0x0BU, /*!< Data rejected due to CRC error */ + kSDSPI_DataResponseTokenWriteError = 0x0DU, /*!< Data rejected due to write error */ +} sdspi_data_response_token_t; + +/*! @brief SD card individual commands */ +typedef enum _sd_command +{ + kSD_SendRelativeAddress = 3U, /*!< Send Relative Address */ + kSD_Switch = 6U, /*!< Switch Function */ + kSD_SendInterfaceCondition = 8U, /*!< Send Interface Condition */ + kSD_VoltageSwitch = 11U, /*!< Voltage Switch */ + kSD_SpeedClassControl = 20U, /*!< Speed Class control */ + kSD_EraseWriteBlockStart = 32U, /*!< Write Block Start */ + kSD_EraseWriteBlockEnd = 33U, /*!< Write Block End */ + kSD_SendTuningBlock = 19U, /*!< Send Tuning Block */ +} sd_command_t; + +/*! @brief SD card individual application commands */ +typedef enum _sd_application_command +{ + kSD_ApplicationSetBusWdith = 6U, /*!< Set Bus Width */ + kSD_ApplicationStatus = 13U, /*!< Send SD status */ + kSD_ApplicationSendNumberWriteBlocks = 22U, /*!< Send Number Of Written Blocks */ + kSD_ApplicationSetWriteBlockEraseCount = 23U, /*!< Set Write Block Erase Count */ + kSD_ApplicationSendOperationCondition = 41U, /*!< Send Operation Condition */ + kSD_ApplicationSetClearCardDetect = 42U, /*!< Set Connnect/Disconnect pull up on detect pin */ + kSD_ApplicationSendScr = 51U, /*!< Send Scr */ +} sd_application_command_t; + +/*! @brief SD card command class */ +enum _sdmmc_command_class +{ + kSDMMC_CommandClassBasic = (1U << 0U), /*!< Card command class 0 */ + kSDMMC_CommandClassBlockRead = (1U << 2U), /*!< Card command class 2 */ + kSDMMC_CommandClassBlockWrite = (1U << 4U), /*!< Card command class 4 */ + kSDMMC_CommandClassErase = (1U << 5U), /*!< Card command class 5 */ + kSDMMC_CommandClassWriteProtect = (1U << 6U), /*!< Card command class 6 */ + kSDMMC_CommandClassLockCard = (1U << 7U), /*!< Card command class 7 */ + kSDMMC_CommandClassApplicationSpecific = (1U << 8U), /*!< Card command class 8 */ + kSDMMC_CommandClassInputOutputMode = (1U << 9U), /*!< Card command class 9 */ + kSDMMC_CommandClassSwitch = (1U << 10U), /*!< Card command class 10 */ +}; + +/*! @brief OCR register in SD card */ +enum _sd_ocr_flag +{ + kSD_OcrPowerUpBusyFlag = (1U << 31U), /*!< Power up busy status */ + kSD_OcrHostCapacitySupportFlag = (1U << 30U), /*!< Card capacity status */ + kSD_OcrCardCapacitySupportFlag = kSD_OcrHostCapacitySupportFlag, /*!< Card capacity status */ + kSD_OcrSwitch18RequestFlag = (1U << 24U), /*!< Switch to 1.8V request */ + kSD_OcrSwitch18AcceptFlag = kSD_OcrSwitch18RequestFlag, /*!< Switch to 1.8V accepted */ + kSD_OcrVdd27_28Flag = (1U << 15U), /*!< VDD 2.7-2.8 */ + kSD_OcrVdd28_29Flag = (1U << 16U), /*!< VDD 2.8-2.9 */ + kSD_OcrVdd29_30Flag = (1U << 17U), /*!< VDD 2.9-3.0 */ + kSD_OcrVdd30_31Flag = (1U << 18U), /*!< VDD 2.9-3.0 */ + kSD_OcrVdd31_32Flag = (1U << 19U), /*!< VDD 3.0-3.1 */ + kSD_OcrVdd32_33Flag = (1U << 20U), /*!< VDD 3.1-3.2 */ + kSD_OcrVdd33_34Flag = (1U << 21U), /*!< VDD 3.2-3.3 */ + kSD_OcrVdd34_35Flag = (1U << 22U), /*!< VDD 3.3-3.4 */ + kSD_OcrVdd35_36Flag = (1U << 23U), /*!< VDD 3.4-3.5 */ +}; + +/*! @brief SD card specification version number */ +enum _sd_specification_version +{ + kSD_SpecificationVersion1_0 = (1U << 0U), /*!< SD card version 1.0-1.01 */ + kSD_SpecificationVersion1_1 = (1U << 1U), /*!< SD card version 1.10 */ + kSD_SpecificationVersion2_0 = (1U << 2U), /*!< SD card version 2.00 */ + kSD_SpecificationVersion3_0 = (1U << 3U), /*!< SD card version 3.0 */ +}; + +/*! @brief SD card bus width */ +typedef enum _sd_data_bus_width +{ + kSD_DataBusWidth1Bit = 0U, /*!< SD data bus width 1-bit mode */ + kSD_DataBusWidth4Bit = 1U, /*!< SD data bus width 4-bit mode */ +} sd_data_bus_width_t; + +/*! @brief SD card switch mode */ +typedef enum _sd_switch_mode +{ + kSD_SwitchCheck = 0U, /*!< SD switch mode 0: check function */ + kSD_SwitchSet = 1U, /*!< SD switch mode 1: set function */ +} sd_switch_mode_t; + +/*! @brief SD card CSD register flags */ +enum _sd_csd_flag +{ + kSD_CsdReadBlockPartialFlag = (1U << 0U), /*!< Partial blocks for read allowed [79:79] */ + kSD_CsdWriteBlockMisalignFlag = (1U << 1U), /*!< Write block misalignment [78:78] */ + kSD_CsdReadBlockMisalignFlag = (1U << 2U), /*!< Read block misalignment [77:77] */ + kSD_CsdDsrImplementedFlag = (1U << 3U), /*!< DSR implemented [76:76] */ + kSD_CsdEraseBlockEnabledFlag = (1U << 4U), /*!< Erase single block enabled [46:46] */ + kSD_CsdWriteProtectGroupEnabledFlag = (1U << 5U), /*!< Write protect group enabled [31:31] */ + kSD_CsdWriteBlockPartialFlag = (1U << 6U), /*!< Partial blocks for write allowed [21:21] */ + kSD_CsdFileFormatGroupFlag = (1U << 7U), /*!< File format group [15:15] */ + kSD_CsdCopyFlag = (1U << 8U), /*!< Copy flag [14:14] */ + kSD_CsdPermanentWriteProtectFlag = (1U << 9U), /*!< Permanent write protection [13:13] */ + kSD_CsdTemporaryWriteProtectFlag = (1U << 10U), /*!< Temporary write protection [12:12] */ +}; + +/*! @brief SD card SCR register flags */ +enum _sd_scr_flag +{ + kSD_ScrDataStatusAfterErase = (1U << 0U), /*!< Data status after erases [55:55] */ + kSD_ScrSdSpecification3 = (1U << 1U), /*!< Specification version 3.00 or higher [47:47]*/ +}; + +/*! @brief SD timing function number */ +enum _sd_timing_function +{ + kSD_FunctionSDR12Deafult = 0U, /*!< SDR12 mode & default*/ + kSD_FunctionSDR25HighSpeed = 1U, /*!< SDR25 & high speed*/ + kSD_FunctionSDR50 = 2U, /*!< SDR50 mode*/ + kSD_FunctionSDR104 = 3U, /*!< SDR104 mode*/ + kSD_FunctionDDR50 = 4U, /*!< DDR50 mode*/ +}; + +/*! @brief SD group number */ +enum _sd_group_num +{ + kSD_GroupTimingMode = 0U, /*!< acess mode group*/ + kSD_GroupCommandSystem = 1U, /*!< command system group*/ + kSD_GroupDriverStrength = 2U, /*!< driver strength group*/ + kSD_GroupCurrentLimit = 3U, /*!< current limit group*/ +}; + +/*! @brief SD card timing mode flags */ +typedef enum _sd_timing_mode +{ + kSD_TimingSDR12DefaultMode = 0U, /*!< Identification mode & SDR12 */ + kSD_TimingSDR25HighSpeedMode = 1U, /*!< High speed mode & SDR25 */ + kSD_TimingSDR50Mode = 2U, /*!< SDR50 mode*/ + kSD_TimingSDR104Mode = 3U, /*!< SDR104 mode */ + kSD_TimingDDR50Mode = 4U, /*!< DDR50 mode */ +} sd_timing_mode_t; + +/*! @brief SD card driver strength */ +typedef enum _sd_driver_strength +{ + kSD_DriverStrengthTypeB = 0U, /*!< default driver strength*/ + kSD_DriverStrengthTypeA = 1U, /*!< driver strength TYPE A */ + kSD_DriverStrengthTypeC = 2U, /*!< driver strength TYPE C */ + kSD_DriverStrengthTypeD = 3U, /*!< driver strength TYPE D */ +} sd_driver_strength_t; + +/*! @brief SD card current limit */ +typedef enum _sd_max_current +{ + kSD_CurrentLimit200MA = 0U, /*!< default current limit */ + kSD_CurrentLimit400MA = 1U, /*!< current limit to 400MA */ + kSD_CurrentLimit600MA = 2U, /*!< current limit to 600MA */ + kSD_CurrentLimit800MA = 3U, /*!< current limit to 800MA */ +} sd_max_current_t; + +/*! @brief SD/MMC card common commands */ +typedef enum _sdmmc_command +{ + kSDMMC_GoIdleState = 0U, /*!< Go Idle State */ + kSDMMC_AllSendCid = 2U, /*!< All Send CID */ + kSDMMC_SetDsr = 4U, /*!< Set DSR */ + kSDMMC_SelectCard = 7U, /*!< Select Card */ + kSDMMC_SendCsd = 9U, /*!< Send CSD */ + kSDMMC_SendCid = 10U, /*!< Send CID */ + kSDMMC_StopTransmission = 12U, /*!< Stop Transmission */ + kSDMMC_SendStatus = 13U, /*!< Send Status */ + kSDMMC_GoInactiveState = 15U, /*!< Go Inactive State */ + kSDMMC_SetBlockLength = 16U, /*!< Set Block Length */ + kSDMMC_ReadSingleBlock = 17U, /*!< Read Single Block */ + kSDMMC_ReadMultipleBlock = 18U, /*!< Read Multiple Block */ + kSDMMC_SetBlockCount = 23U, /*!< Set Block Count */ + kSDMMC_WriteSingleBlock = 24U, /*!< Write Single Block */ + kSDMMC_WriteMultipleBlock = 25U, /*!< Write Multiple Block */ + kSDMMC_ProgramCsd = 27U, /*!< Program CSD */ + kSDMMC_SetWriteProtect = 28U, /*!< Set Write Protect */ + kSDMMC_ClearWriteProtect = 29U, /*!< Clear Write Protect */ + kSDMMC_SendWriteProtect = 30U, /*!< Send Write Protect */ + kSDMMC_Erase = 38U, /*!< Erase */ + kSDMMC_LockUnlock = 42U, /*!< Lock Unlock */ + kSDMMC_ApplicationCommand = 55U, /*!< Send Application Command */ + kSDMMC_GeneralCommand = 56U, /*!< General Purpose Command */ + kSDMMC_ReadOcr = 58U, /*!< Read OCR */ +} sdmmc_command_t; + +/*! @brief sdio card cccr register addr */ +enum _sdio_cccr_reg +{ + kSDIO_RegCCCRSdioVer = 0x00U, /*!< CCCR & SDIO version*/ + kSDIO_RegSDVersion = 0x01U, /*!< SD version */ + kSDIO_RegIOEnable = 0x02U, /*!< io enable register */ + kSDIO_RegIOReady = 0x03U, /*!< io ready register */ + kSDIO_RegIOIntEnable = 0x04U, /*!< io interrupt enable register */ + kSDIO_RegIOIntPending = 0x05U, /*!< io interrupt pending register */ + kSDIO_RegIOAbort = 0x06U, /*!< io abort register */ + kSDIO_RegBusInterface = 0x07U, /*!< bus interface register */ + kSDIO_RegCardCapability = 0x08U, /*!< card capability register */ + kSDIO_RegCommonCISPointer = 0x09U, /*!< common CIS pointer register */ + kSDIO_RegBusSuspend = 0x0C, /*!< bus suspend register */ + kSDIO_RegFunctionSelect = 0x0DU, /*!< function select register */ + kSDIO_RegExecutionFlag = 0x0EU, /*!< execution flag register */ + kSDIO_RegReadyFlag = 0x0FU, /*!< ready flag register */ + kSDIO_RegFN0BlockSizeLow = 0x10U, /*!< FN0 block size register */ + kSDIO_RegFN0BlockSizeHigh = 0x11U, /*!< FN0 block size register */ + kSDIO_RegPowerControl = 0x12U, /*!< power control register */ + kSDIO_RegHighSpeed = 0x13U, /*!< high speed register */ +}; + +/*! @brief sdio card individual commands */ +typedef enum _sdio_command +{ + kSDIO_SendRelativeAddress = 3U, /*!< send relative address */ + kSDIO_SendOperationCondition = 5U, /*!< send operation condition */ + kSDIO_SendInterfaceCondition = 8U, /*!< send interface condition */ + kSDIO_RWIODirect = 52U, /*!< read/write IO direct command */ + kSDIO_RWIOExtended = 53U, /*!< read/write IO extended command */ +} sdio_command_t; + +/*! @brief sdio card individual commands */ +typedef enum _sdio_func_num +{ + kSDIO_FunctionNum0, /*!< sdio function0*/ + kSDIO_FunctionNum1, /*!< sdio function1*/ + kSDIO_FunctionNum2, /*!< sdio function2*/ + kSDIO_FunctionNum3, /*!< sdio function3*/ + kSDIO_FunctionNum4, /*!< sdio function4*/ + kSDIO_FunctionNum5, /*!< sdio function5*/ + kSDIO_FunctionNum6, /*!< sdio function6*/ + kSDIO_FunctionNum7, /*!< sdio function7*/ + kSDIO_FunctionMemory, /*!< for combo card*/ +} sdio_func_num_t; + +#define SDIO_CMD_ARGUMENT_RW_POS (31U) /*!< read/write flag position */ +#define SDIO_CMD_ARGUMENT_FUNC_NUM_POS (28U) /*!< function number position */ +#define SDIO_DIRECT_CMD_ARGUMENT_RAW_POS (27U) /*!< direct raw flag position */ +#define SDIO_CMD_ARGUMENT_REG_ADDR_POS (9U) /*!< direct reg addr position */ +#define SDIO_CMD_ARGUMENT_REG_ADDR_MASK (0x1FFFFU) /*!< direct reg addr mask */ +#define SDIO_DIRECT_CMD_DATA_MASK (0xFFU) /*!< data mask */ + +#define SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS (27U) /*!< extended command argument block mode bit position */ +#define SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS (26U) /*!< extended command argument OP Code bit position */ +#define SDIO_EXTEND_CMD_BLOCK_MODE_MASK (0x08000000U) /*!< block mode mask */ +#define SDIO_EXTEND_CMD_OP_CODE_MASK (0x04000000U) /*!< op code mask */ +#define SDIO_EXTEND_CMD_COUNT_MASK (0x1FFU) /*!< byte/block count mask */ +#define SDIO_MAX_BLOCK_SIZE (2048U) /*!< max block size */ +#define SDIO_FBR_BASE(x) (x * 0x100U) /*!< function basic register */ +#define SDIO_TPL_CODE_END (0xFFU) /*!< tuple end */ +#define SDIO_TPL_CODE_MANIFID (0x20U) /*!< manufacturer ID */ +#define SDIO_TPL_CODE_FUNCID (0x21U) /*!< function ID */ +#define SDIO_TPL_CODE_FUNCE (0x22U) /*!< function extension tuple*/ +/*! @brief sdio command response flag */ +enum _sdio_status_flag +{ + kSDIO_StatusCmdCRCError = 0x8000U, /*!< the CRC check of the previous cmd fail*/ + kSDIO_StatusIllegalCmd = 0x4000U, /*!< cmd illegal for the card state */ + kSDIO_StatusR6Error = 0x2000U, /*!< special for R6 error status */ + kSDIO_StatusError = 0x0800U, /*!< A general or an unknown error occurred */ + kSDIO_StatusFunctionNumError = 0x0200U, /*!< invail function error */ + kSDIO_StatusOutofRange = 0x0100U, /*!< cmd argument was out of the allowed range*/ +}; + +/*! @brief sdio operation condition flag */ +enum _sdio_ocr_flag +{ + kSDIO_OcrPowerUpBusyFlag = (1U << 31U), /*!< Power up busy status */ + kSDIO_OcrIONumber = (7U << 28U), /*!< number of IO function */ + kSDIO_OcrMemPresent = (1U << 27U), /*!< memory present flag */ + + kSDIO_OcrVdd20_21Flag = (1U << 8U), /*!< VDD 2.0-2.1 */ + kSDIO_OcrVdd21_22Flag = (1U << 9U), /*!< VDD 2.1-2.2 */ + kSDIO_OcrVdd22_23Flag = (1U << 10U), /*!< VDD 2.2-2.3 */ + kSDIO_OcrVdd23_24Flag = (1U << 11U), /*!< VDD 2.3-2.4 */ + kSDIO_OcrVdd24_25Flag = (1U << 12U), /*!< VDD 2.4-2.5 */ + kSDIO_OcrVdd25_26Flag = (1U << 13U), /*!< VDD 2.5-2.6 */ + kSDIO_OcrVdd26_27Flag = (1U << 14U), /*!< VDD 2.6-2.7 */ + kSDIO_OcrVdd27_28Flag = (1U << 15U), /*!< VDD 2.7-2.8 */ + kSDIO_OcrVdd28_29Flag = (1U << 16U), /*!< VDD 2.8-2.9 */ + kSDIO_OcrVdd29_30Flag = (1U << 17U), /*!< VDD 2.9-3.0 */ + kSDIO_OcrVdd30_31Flag = (1U << 18U), /*!< VDD 2.9-3.0 */ + kSDIO_OcrVdd31_32Flag = (1U << 19U), /*!< VDD 3.0-3.1 */ + kSDIO_OcrVdd32_33Flag = (1U << 20U), /*!< VDD 3.1-3.2 */ + kSDIO_OcrVdd33_34Flag = (1U << 21U), /*!< VDD 3.2-3.3 */ + kSDIO_OcrVdd34_35Flag = (1U << 22U), /*!< VDD 3.3-3.4 */ + kSDIO_OcrVdd35_36Flag = (1U << 23U), /*!< VDD 3.4-3.5 */ + +}; + +/*! @brief sdio capability flag */ +enum _sdio_capability_flag +{ + kSDIO_CCCRSupportDirectCmdDuringDataTrans = (1U << 0U), /*!< support direct cmd during data transfer */ + kSDIO_CCCRSupportMultiBlock = (1U << 1U), /*!< support multi block mode */ + kSDIO_CCCRSupportReadWait = (1U << 2U), /*!< support read wait */ + kSDIO_CCCRSupportSuspendResume = (1U << 3U), /*!< support suspend resume */ + kSDIO_CCCRSupportIntDuring4BitDataTrans = (1U << 4U), /*!< support interrupt during 4-bit data transfer */ + kSDIO_CCCRSupportLowSpeed1Bit = (1U << 6U), /*!< support low speed 1bit mode */ + kSDIO_CCCRSupportLowSpeed4Bit = (1U << 7U), /*!< support low speed 4bit mode */ + kSDIO_CCCRSupportMasterPowerControl = (1U << 8U), /*!< support master power control */ + kSDIO_CCCRSupportHighSpeed = (1U << 9U), /*!< support high speed */ + kSDIO_CCCRSupportContinuousSPIInt = (1U << 10U), /*!< support continuous SPI interrupt */ + kSDIO_FBRSupportCSA = (1U << 11U), /*!< function support CSA */ + kSDIO_FBRSupportPowerSelection = (1U << 12U), /*!< function support power selection */ + +}; + +/*! @brief sdio bus width */ +typedef enum _sdio_bus_width +{ + kSDIO_DataBus1Bit = 0x00U, /*!< 1bit bus mode */ + kSDIO_DataBus4Bit = 0X02U, /*!< 4 bit bus mode*/ +} sdio_bus_width_t; + +/*! @brief MMC card individual commands */ +typedef enum _mmc_command +{ + kMMC_SendOperationCondition = 1U, /*!< Send Operation Condition */ + kMMC_SetRelativeAddress = 3U, /*!< Set Relative Address */ + kMMC_SleepAwake = 5U, /*!< Sleep Awake */ + kMMC_Switch = 6U, /*!< Switch */ + kMMC_SendExtendedCsd = 8U, /*!< Send EXT_CSD */ + kMMC_ReadDataUntilStop = 11U, /*!< Read Data Until Stop */ + kMMC_BusTestRead = 14U, /*!< Test Read */ + kMMC_SendingBusTest = 19U, /*!< test bus width cmd*/ + kMMC_WriteDataUntilStop = 20U, /*!< Write Data Until Stop */ + kMMC_SendTuningBlock = 21U, /*!< MMC sending tuning block */ + kMMC_ProgramCid = 26U, /*!< Program CID */ + kMMC_EraseGroupStart = 35U, /*!< Erase Group Start */ + kMMC_EraseGroupEnd = 36U, /*!< Erase Group End */ + kMMC_FastInputOutput = 39U, /*!< Fast IO */ + kMMC_GoInterruptState = 40U, /*!< Go interrupt State */ +} mmc_command_t; + +/*! @brief MMC card classified as voltage range */ +typedef enum _mmc_classified_voltage +{ + kMMC_ClassifiedVoltageHigh = 0U, /*!< High-voltage MMC card */ + kMMC_ClassifiedVoltageDual = 1U, /*!< Dual-voltage MMC card */ +} mmc_classified_voltage_t; + +/*! @brief MMC card classified as density level */ +typedef enum _mmc_classified_density +{ + kMMC_ClassifiedDensityWithin2GB = 0U, /*!< Density byte is less than or equal 2GB */ + kMMC_ClassifiedDensityHigher2GB = 1U, /* Density byte is higher than 2GB */ +} mmc_classified_density_t; + +/*! @brief The bit mask for VOLTAGE WINDOW 1.70V to 1.95V field in OCR */ +#define MMC_OCR_V170TO195_SHIFT (7U) +/*! @brief The bit mask for VOLTAGE WINDOW 1.70V to 1.95V field in OCR */ +#define MMC_OCR_V170TO195_MASK (0x00000080U) +/*! @brief The bit shift for VOLTAGE WINDOW 2.00V to 2.60V field in OCR */ +#define MMC_OCR_V200TO260_SHIFT (8U) +/*! @brief The bit mask for VOLTAGE WINDOW 2.00V to 2.60V field in OCR */ +#define MMC_OCR_V200TO260_MASK (0x00007F00U) +/*! @brief The bit shift for VOLTAGE WINDOW 2.70V to 3.60V field in OCR */ +#define MMC_OCR_V270TO360_SHIFT (15U) +/*! @brief The bit mask for VOLTAGE WINDOW 2.70V to 3.60V field in OCR */ +#define MMC_OCR_V270TO360_MASK (0x00FF8000U) +/*! @brief The bit shift for ACCESS MODE field in OCR */ +#define MMC_OCR_ACCESS_MODE_SHIFT (29U) +/*! @brief The bit mask for ACCESS MODE field in OCR */ +#define MMC_OCR_ACCESS_MODE_MASK (0x60000000U) +/*! @brief The bit shift for BUSY field in OCR */ +#define MMC_OCR_BUSY_SHIFT (31U) +/*! @brief The bit mask for BUSY field in OCR */ +#define MMC_OCR_BUSY_MASK (1U << MMC_OCR_BUSY_SHIFT) + +/*! @brief MMC card access mode(Access mode in OCR). */ +typedef enum _mmc_access_mode +{ + kMMC_AccessModeByte = 0U, /*!< The card should be accessed as byte */ + kMMC_AccessModeSector = 2U, /*!< The card should be accessed as sector */ +} mmc_access_mode_t; + +/*! @brief MMC card voltage window(VDD voltage window in OCR). */ +typedef enum _mmc_voltage_window +{ + kMMC_VoltageWindowNone = 0U, /*!< voltage window is not define by user*/ + kMMC_VoltageWindow120 = 0x01U, /*!< Voltage window is 1.20V */ + kMMC_VoltageWindow170to195 = 0x02U, /*!< Voltage window is 1.70V to 1.95V */ + kMMC_VoltageWindows270to360 = 0x1FFU, /*!< Voltage window is 2.70V to 3.60V */ +} mmc_voltage_window_t; + +/*! @brief CSD structure version(CSD_STRUCTURE in CSD). */ +typedef enum _mmc_csd_structure_version +{ + kMMC_CsdStrucureVersion10 = 0U, /*!< CSD version No. 1.0 */ + kMMC_CsdStrucureVersion11 = 1U, /*!< CSD version No. 1.1 */ + kMMC_CsdStrucureVersion12 = 2U, /*!< CSD version No. 1.2 */ + kMMC_CsdStrucureVersionInExtcsd = 3U, /*!< Version coded in Extended CSD */ +} mmc_csd_structure_version_t; + +/*! @brief MMC card specification version(SPEC_VERS in CSD). */ +typedef enum _mmc_specification_version +{ + kMMC_SpecificationVersion0 = 0U, /*!< Allocated by MMCA */ + kMMC_SpecificationVersion1 = 1U, /*!< Allocated by MMCA */ + kMMC_SpecificationVersion2 = 2U, /*!< Allocated by MMCA */ + kMMC_SpecificationVersion3 = 3U, /*!< Allocated by MMCA */ + kMMC_SpecificationVersion4 = 4U, /*!< Version 4.1/4.2/4.3/4.41-4.5-4.51-5.0 */ +} mmc_specification_version_t; + +/*! @brief The bit shift for FREQUENCY UNIT field in TRANSFER SPEED(TRAN-SPEED in Extended CSD) */ +#define MMC_TRANSFER_SPEED_FREQUENCY_UNIT_SHIFT (0U) +/*! @brief The bit mask for FRQEUENCY UNIT in TRANSFER SPEED */ +#define MMC_TRANSFER_SPEED_FREQUENCY_UNIT_MASK (0x07U) +/*! @brief The bit shift for MULTIPLIER field in TRANSFER SPEED */ +#define MMC_TRANSFER_SPEED_MULTIPLIER_SHIFT (3U) +/*! @brief The bit mask for MULTIPLIER field in TRANSFER SPEED */ +#define MMC_TRANSFER_SPEED_MULTIPLIER_MASK (0x78U) + +/*! @brief Read the value of FREQUENCY UNIT in TRANSFER SPEED. */ +#define READ_MMC_TRANSFER_SPEED_FREQUENCY_UNIT(CSD) \ + (((CSD.transferSpeed) & MMC_TRANSFER_SPEED_FREQUENCY_UNIT_MASK) >> MMC_TRANSFER_SPEED_FREQUENCY_UNIT_SHIFT) +/*! @brief Read the value of MULTIPLER filed in TRANSFER SPEED. */ +#define READ_MMC_TRANSFER_SPEED_MULTIPLIER(CSD) \ + (((CSD.transferSpeed) & MMC_TRANSFER_SPEED_MULTIPLIER_MASK) >> MMC_TRANSFER_SPEED_MULTIPLIER_SHIFT) + +/*! @brief MMC card Extended CSD fix version(EXT_CSD_REV in Extended CSD) */ +enum _mmc_extended_csd_revision +{ + kMMC_ExtendedCsdRevision10 = 0U, /*!< Revision 1.0 */ + kMMC_ExtendedCsdRevision11 = 1U, /*!< Revision 1.1 */ + kMMC_ExtendedCsdRevision12 = 2U, /*!< Revision 1.2 */ + kMMC_ExtendedCsdRevision13 = 3U, /*!< Revision 1.3 MMC4.3*/ + kMMC_ExtendedCsdRevision14 = 4U, /*!< Revision 1.4 obsolete*/ + kMMC_ExtendedCsdRevision15 = 5U, /*!< Revision 1.5 MMC4.41*/ + kMMC_ExtendedCsdRevision16 = 6U, /*!< Revision 1.6 MMC4.5*/ + kMMC_ExtendedCsdRevision17 = 7U, /*!< Revision 1.7 MMC5.0 */ +}; + +/*! @brief MMC card command set(COMMAND_SET in Extended CSD) */ +typedef enum _mmc_command_set +{ + kMMC_CommandSetStandard = 0U, /*!< Standard MMC */ + kMMC_CommandSet1 = 1U, /*!< Command set 1 */ + kMMC_CommandSet2 = 2U, /*!< Command set 2 */ + kMMC_CommandSet3 = 3U, /*!< Command set 3 */ + kMMC_CommandSet4 = 4U, /*!< Command set 4 */ +} mmc_command_set_t; + +/*! @brief boot support(BOOT_INFO in Extended CSD) */ +enum _mmc_support_boot_mode +{ + kMMC_SupportAlternateBoot = 1U, /*!< support alternative boot mode*/ + kMMC_SupportDDRBoot = 2U, /*!< support DDR boot mode*/ + kMMC_SupportHighSpeedBoot = 4U, /*!< support high speed boot mode*/ +}; +/*! @brief The power class value bit mask when bus in 4 bit mode */ +#define MMC_POWER_CLASS_4BIT_MASK (0x0FU) +/*! @brief The power class current value bit mask when bus in 8 bit mode */ +#define MMC_POWER_CLASS_8BIT_MASK (0xF0U) + +/*! @brief MMC card high-speed timing(HS_TIMING in Extended CSD) */ +typedef enum _mmc_high_speed_timing +{ + kMMC_HighSpeedTimingNone = 0U, /*!< MMC card using none high-speed timing */ + kMMC_HighSpeedTiming = 1U, /*!< MMC card using high-speed timing */ + kMMC_HighSpeed200Timing = 2U, /*!< MMC card high speed 200 timing*/ + kMMC_HighSpeed400Timing = 3U, /*!< MMC card high speed 400 timing*/ + kMMC_HighSpeed26MHZTiming = 4U, /*!< MMC high speed 26MHZ timing */ + kMMC_HighSpeed52MHZTiming = 5U, /*!< MMC high speed 52MHZ timing */ + kMMC_HighSpeedDDR52Timing = 6U, /*!< MMC high speed timing DDR52 1.8V */ +} mmc_high_speed_timing_t; + +/*! @brief The number of data bus width type */ +#define MMC_DATA_BUS_WIDTH_TYPE_NUMBER (3U) +/*! @brief MMC card data bus width(BUS_WIDTH in Extended CSD) */ +typedef enum _mmc_data_bus_width +{ + kMMC_DataBusWidth1bit = 0U, /*!< MMC data bus width is 1 bit */ + kMMC_DataBusWidth4bit = 1U, /*!< MMC data bus width is 4 bits */ + kMMC_DataBusWidth8bit = 2U, /*!< MMC data bus width is 8 bits */ + kMMC_DataBusWidth4bitDDR = 5U, /*!< MMC data bus width is 4 bits ddr */ + kMMC_DataBusWidth8bitDDR = 6U, /*!< MMC data bus width is 8 bits ddr */ +} mmc_data_bus_width_t; + +/*! @brief MMC card boot partition enabled(BOOT_PARTITION_ENABLE in Extended CSD) */ +typedef enum _mmc_boot_partition_enable +{ + kMMC_BootPartitionEnableNot = 0U, /*!< Device not boot enabled (default) */ + kMMC_BootPartitionEnablePartition1 = 1U, /*!< Boot partition 1 enabled for boot */ + kMMC_BootPartitionEnablePartition2 = 2U, /*!< Boot partition 2 enabled for boot */ + kMMC_BootPartitionEnableUserAera = 7U, /*!< User area enabled for boot */ +} mmc_boot_partition_enable_t; + +/*! @brief MMC card partition to be accessed(BOOT_PARTITION_ACCESS in Extended CSD) */ +typedef enum _mmc_access_partition +{ + kMMC_AccessPartitionUserAera = 0U, /*!< No access to boot partition (default), normal partition */ + kMMC_AccessPartitionBoot1 = 1U, /*!< Read/Write boot partition 1 */ + kMMC_AccessPartitionBoot2 = 2U, /*!< Read/Write boot partition 2*/ + kMMC_AccessRPMB = 3U, /*!< Replay protected mem block */ + kMMC_AccessGeneralPurposePartition1 = 4U, /*!< access to general purpose partition 1 */ + kMMC_AccessGeneralPurposePartition2 = 5U, /*!< access to general purpose partition 2 */ + kMMC_AccessGeneralPurposePartition3 = 6U, /*!< access to general purpose partition 3 */ + kMMC_AccessGeneralPurposePartition4 = 7U, /*!< access to general purpose partition 4 */ +} mmc_access_partition_t; + +/*! @brief The bit shift for PARTITION ACCESS filed in BOOT CONFIG (BOOT_CONFIG in Extend CSD) */ +#define MMC_BOOT_CONFIG_PARTITION_ACCESS_SHIFT (0U) +/*! @brief The bit mask for PARTITION ACCESS field in BOOT CONFIG */ +#define MMC_BOOT_CONFIG_PARTITION_ACCESS_MASK (0x00000007U) +/*! @brief The bit shift for PARTITION ENABLE field in BOOT CONFIG */ +#define MMC_BOOT_CONFIG_PARTITION_ENABLE_SHIFT (3U) +/*! @brief The bit mask for PARTITION ENABLE field in BOOT CONFIG */ +#define MMC_BOOT_CONFIG_PARTITION_ENABLE_MASK (0x00000038U) +/*! @brief The bit shift for ACK field in BOOT CONFIG */ +#define MMC_BOOT_CONFIG_ACK_SHIFT (6U) +/*! @brief The bit mask for ACK field in BOOT CONFIG */ +#define MMC_BOOT_CONFIG_ACK_MASK (0x00000040U) +/*! @brief The bit shift for BOOT BUS WIDTH field in BOOT CONFIG */ +#define MMC_BOOT_BUS_WIDTH_WIDTH_SHIFT (8U) +/*! @brief The bit mask for BOOT BUS WIDTH field in BOOT CONFIG */ +#define MMC_BOOT_BUS_WIDTH_WIDTH_MASK (0x00000300U) +/*! @brief The bit shift for BOOT BUS WIDTH RESET field in BOOT CONFIG */ +#define MMC_BOOT_BUS_WIDTH_RESET_SHIFT (10U) +/*! @brief The bit mask for BOOT BUS WIDTH RESET field in BOOT CONFIG */ +#define MMC_BOOT_BUS_WIDTH_RESET_MASK (0x00000400U) + +/*! @brief MMC card CSD register flags */ +enum _mmc_csd_flag +{ + kMMC_CsdReadBlockPartialFlag = (1U << 0U), /*!< Partial blocks for read allowed */ + kMMC_CsdWriteBlockMisalignFlag = (1U << 1U), /*!< Write block misalignment */ + kMMC_CsdReadBlockMisalignFlag = (1U << 2U), /*!< Read block misalignment */ + kMMC_CsdDsrImplementedFlag = (1U << 3U), /*!< DSR implemented */ + kMMC_CsdWriteProtectGroupEnabledFlag = (1U << 4U), /*!< Write protect group enabled */ + kMMC_CsdWriteBlockPartialFlag = (1U << 5U), /*!< Partial blocks for write allowed */ + kMMC_ContentProtectApplicationFlag = (1U << 6U), /*!< Content protect application */ + kMMC_CsdFileFormatGroupFlag = (1U << 7U), /*!< File format group */ + kMMC_CsdCopyFlag = (1U << 8U), /*!< Copy flag */ + kMMC_CsdPermanentWriteProtectFlag = (1U << 9U), /*!< Permanent write protection */ + kMMC_CsdTemporaryWriteProtectFlag = (1U << 10U), /*!< Temporary write protection */ +}; + +/*! @brief Extended CSD register access mode(Access mode in CMD6). */ +typedef enum _mmc_extended_csd_access_mode +{ + kMMC_ExtendedCsdAccessModeCommandSet = 0U, /*!< Command set related setting */ + kMMC_ExtendedCsdAccessModeSetBits = 1U, /*!< Set bits in specific byte in Extended CSD */ + kMMC_ExtendedCsdAccessModeClearBits = 2U, /*!< Clear bits in specific byte in Extended CSD */ + kMMC_ExtendedCsdAccessModeWriteBits = 3U, /*!< Write a value to specific byte in Extended CSD */ +} mmc_extended_csd_access_mode_t; + +/*! @brief EXT CSD byte index */ +typedef enum _mmc_extended_csd_index +{ + kMMC_ExtendedCsdIndexEraseGroupDefinition = 175U, /*!< Erase Group Def */ + kMMC_ExtendedCsdIndexBootBusWidth = 177U, /*!< Boot Bus Width */ + kMMC_ExtendedCsdIndexBootConfig = 179U, /*!< Boot Config */ + kMMC_ExtendedCsdIndexBusWidth = 183U, /*!< Bus Width */ + kMMC_ExtendedCsdIndexHighSpeedTiming = 185U, /*!< High-speed Timing */ + kMMC_ExtendedCsdIndexPowerClass = 187U, /*!< Power Class */ + kMMC_ExtendedCsdIndexCommandSet = 191U, /*!< Command Set */ +} mmc_extended_csd_index_t; + +/*! @brief mmc driver strength */ +enum _mmc_driver_strength +{ + kMMC_DriverStrength0 = 0U, /*!< Driver type0 ,nominal impedance 50ohm */ + kMMC_DriverStrength1 = 1U, /*!< Driver type1 ,nominal impedance 33ohm */ + kMMC_DriverStrength2 = 2U, /*!< Driver type2 ,nominal impedance 66ohm */ + kMMC_DriverStrength3 = 3U, /*!< Driver type3 ,nominal impedance 100ohm */ + kMMC_DriverStrength4 = 4U, /*!< Driver type4 ,nominal impedance 40ohm */ +}; + +/*! @brief mmc extended csd flags*/ +typedef enum _mmc_extended_csd_flags +{ + kMMC_ExtCsdExtPartitionSupport = (1 << 0U), /*!< partitioning support[160] */ + kMMC_ExtCsdEnhancePartitionSupport = (1 << 1U), /*!< partitioning support[160] */ + kMMC_ExtCsdPartitioningSupport = (1 << 2U), /*!< partitioning support[160] */ + kMMC_ExtCsdPrgCIDCSDInDDRModeSupport = (1 << 3U), /*!< CMD26 and CMD27 are support dual data rate [130]*/ + kMMC_ExtCsdBKOpsSupport = (1 << 4U), /*!< background operation feature support [502]*/ + kMMC_ExtCsdDataTagSupport = (1 << 5U), /*!< data tag support[499]*/ + kMMC_ExtCsdModeOperationCodeSupport = (1 << 6U), /*!< mode operation code support[493]*/ +} mmc_extended_csd_flags_t; + +/*! @brief The length of Extended CSD register, unit as bytes. */ +#define MMC_EXTENDED_CSD_BYTES (512U) + +/*! @brief MMC card default relative address */ +#define MMC_DEFAULT_RELATIVE_ADDRESS (2U) + +/*! @brief SD card product name length united as bytes. */ +#define SD_PRODUCT_NAME_BYTES (5U) + +/*! @brief sdio card FBR register */ +typedef struct _sdio_fbr +{ + uint8_t flags; /*!< current io flags */ + uint8_t ioStdFunctionCode; /*!< current io standard function code */ + uint8_t ioExtFunctionCode; /*!< current io extended function code*/ + uint32_t ioPointerToCIS; /*!< current io pointer to CIS */ + uint32_t ioPointerToCSA; /*!< current io pointer to CSA*/ + uint16_t ioBlockSize; /*!< current io block size */ +} sdio_fbr_t; + +/*! @brief sdio card common CIS */ +typedef struct _sdio_common_cis +{ + /* manufacturer identification string tuple */ + uint16_t mID; /*!< manufacturer code */ + uint16_t mInfo; /*!< manufacturer information */ + + /*function identification tuple */ + uint8_t funcID; /*!< function ID */ + + /* function extension tuple */ + uint16_t fn0MaxBlkSize; /*!< function 0 max block size */ + uint8_t maxTransSpeed; /*!< max data transfer speed for all function */ + +} sdio_common_cis_t; + +/*! @brief sdio card function CIS */ +typedef struct _sdio_func_cis +{ + /*function identification tuple */ + uint8_t funcID; /*!< function ID */ + + /* function extension tuple */ + uint8_t funcInfo; /*!< function info */ + uint8_t ioVersion; /*!< level of application specification this io support */ + uint32_t cardPSN; /*!< product serial number */ + uint32_t ioCSASize; /*!< avaliable CSA size for io */ + uint8_t ioCSAProperty; /*!< CSA property */ + uint16_t ioMaxBlockSize; /*!< io max transfer data size */ + uint32_t ioOCR; /*!< io ioeration condition */ + uint8_t ioOPMinPwr; /*!< min current in operation mode */ + uint8_t ioOPAvgPwr; /*!< average current in operation mode */ + uint8_t ioOPMaxPwr; /*!< max current in operation mode */ + uint8_t ioSBMinPwr; /*!< min current in standby mode */ + uint8_t ioSBAvgPwr; /*!< average current in standby mode */ + uint8_t ioSBMaxPwr; /*!< max current in standby mode */ + + uint16_t ioMinBandWidth; /*!< io min transfer bandwidth */ + uint16_t ioOptimumBandWidth; /*!< io optimum transfer bandwidth */ + uint16_t ioReadyTimeout; /*!< timeout value from enalbe to ready */ + uint16_t ioHighCurrentAvgCurrent; /*!< the average peak current (mA) + when IO operating in high current mode */ + uint16_t ioHighCurrentMaxCurrent; /*!< the max peak current (mA) + when IO operating in high current mode */ + uint16_t ioLowCurrentAvgCurrent; /*!< the average peak current (mA) + when IO operating in lower current mode */ + uint16_t ioLowCurrentMaxCurrent; /*!< the max peak current (mA) + when IO operating in lower current mode */ +} sdio_func_cis_t; + +/*! @brief SD card CID register */ +typedef struct _sd_cid +{ + uint8_t manufacturerID; /*!< Manufacturer ID [127:120] */ + uint16_t applicationID; /*!< OEM/Application ID [119:104] */ + uint8_t productName[SD_PRODUCT_NAME_BYTES]; /*!< Product name [103:64] */ + uint8_t productVersion; /*!< Product revision [63:56] */ + uint32_t productSerialNumber; /*!< Product serial number [55:24] */ + uint16_t manufacturerData; /*!< Manufacturing date [19:8] */ +} sd_cid_t; + +/*! @brief SD card CSD register */ +typedef struct _sd_csd +{ + uint8_t csdStructure; /*!< CSD structure [127:126] */ + uint8_t dataReadAccessTime1; /*!< Data read access-time-1 [119:112] */ + uint8_t dataReadAccessTime2; /*!< Data read access-time-2 in clock cycles (NSAC*100) [111:104] */ + uint8_t transferSpeed; /*!< Maximum data transfer rate [103:96] */ + uint16_t cardCommandClass; /*!< Card command classes [95:84] */ + uint8_t readBlockLength; /*!< Maximum read data block length [83:80] */ + uint16_t flags; /*!< Flags in _sd_csd_flag */ + uint32_t deviceSize; /*!< Device size [73:62] */ + /* Following fields from 'readCurrentVddMin' to 'deviceSizeMultiplier' exist in CSD version 1 */ + uint8_t readCurrentVddMin; /*!< Maximum read current at VDD min [61:59] */ + uint8_t readCurrentVddMax; /*!< Maximum read current at VDD max [58:56] */ + uint8_t writeCurrentVddMin; /*!< Maximum write current at VDD min [55:53] */ + uint8_t writeCurrentVddMax; /*!< Maximum write current at VDD max [52:50] */ + uint8_t deviceSizeMultiplier; /*!< Device size multiplier [49:47] */ + + uint8_t eraseSectorSize; /*!< Erase sector size [45:39] */ + uint8_t writeProtectGroupSize; /*!< Write protect group size [38:32] */ + uint8_t writeSpeedFactor; /*!< Write speed factor [28:26] */ + uint8_t writeBlockLength; /*!< Maximum write data block length [25:22] */ + uint8_t fileFormat; /*!< File format [11:10] */ +} sd_csd_t; + +/*! @brief The bit shift for RATE UNIT field in TRANSFER SPEED */ +#define SD_TRANSFER_SPEED_RATE_UNIT_SHIFT (0U) +/*! @brief The bit mask for RATE UNIT field in TRANSFER SPEED */ +#define SD_TRANSFER_SPEED_RATE_UNIT_MASK (0x07U) +/*! @brief The bit shift for TIME VALUE field in TRANSFER SPEED */ +#define SD_TRANSFER_SPEED_TIME_VALUE_SHIFT (2U) +/*! @brief The bit mask for TIME VALUE field in TRANSFER SPEED */ +#define SD_TRANSFER_SPEED_TIME_VALUE_MASK (0x78U) +/*! @brief Read the value of FREQUENCY UNIT in TRANSFER SPEED field */ +#define SD_RD_TRANSFER_SPEED_RATE_UNIT(x) \ + (((x.transferSpeed) & SD_TRANSFER_SPEED_RATE_UNIT_MASK) >> SD_TRANSFER_SPEED_RATE_UNIT_SHIFT) +/*! @brief Read the value of TIME VALUE in TRANSFER SPEED field */ +#define SD_RD_TRANSFER_SPEED_TIME_VALUE(x) \ + (((x.transferSpeed) & SD_TRANSFER_SPEED_TIME_VALUE_MASK) >> SD_TRANSFER_SPEED_TIME_VALUE_SHIFT) + +/*! @brief SD card SCR register */ +typedef struct _sd_scr +{ + uint8_t scrStructure; /*!< SCR Structure [63:60] */ + uint8_t sdSpecification; /*!< SD memory card specification version [59:56] */ + uint16_t flags; /*!< SCR flags in _sd_scr_flag */ + uint8_t sdSecurity; /*!< Security specification supported [54:52] */ + uint8_t sdBusWidths; /*!< Data bus widths supported [51:48] */ + uint8_t extendedSecurity; /*!< Extended security support [46:43] */ + uint8_t commandSupport; /*!< Command support bits [33:32] 33-support CMD23, 32-support cmd20*/ + uint32_t reservedForManufacturer; /*!< reserved for manufacturer usage [31:0] */ +} sd_scr_t; + +/*! @brief MMC card product name length united as bytes. */ +#define MMC_PRODUCT_NAME_BYTES (6U) +/*! @brief MMC card CID register. */ +typedef struct _mmc_cid +{ + uint8_t manufacturerID; /*!< Manufacturer ID */ + uint16_t applicationID; /*!< OEM/Application ID */ + uint8_t productName[MMC_PRODUCT_NAME_BYTES]; /*!< Product name */ + uint8_t productVersion; /*!< Product revision */ + uint32_t productSerialNumber; /*!< Product serial number */ + uint8_t manufacturerData; /*!< Manufacturing date */ +} mmc_cid_t; + +/*! @brief MMC card CSD register. */ +typedef struct _mmc_csd +{ + uint8_t csdStructureVersion; /*!< CSD structure [127:126] */ + uint8_t systemSpecificationVersion; /*!< System specification version [125:122] */ + uint8_t dataReadAccessTime1; /*!< Data read access-time 1 [119:112] */ + uint8_t dataReadAccessTime2; /*!< Data read access-time 2 in CLOCK cycles (NSAC*100) [111:104] */ + uint8_t transferSpeed; /*!< Max. bus clock frequency [103:96] */ + uint16_t cardCommandClass; /*!< card command classes [95:84] */ + uint8_t readBlockLength; /*!< Max. read data block length [83:80] */ + uint16_t flags; /*!< Contain flags in _mmc_csd_flag */ + uint16_t deviceSize; /*!< Device size [73:62] */ + uint8_t readCurrentVddMin; /*!< Max. read current @ VDD min [61:59] */ + uint8_t readCurrentVddMax; /*!< Max. read current @ VDD max [58:56] */ + uint8_t writeCurrentVddMin; /*!< Max. write current @ VDD min [55:53] */ + uint8_t writeCurrentVddMax; /*!< Max. write current @ VDD max [52:50] */ + uint8_t deviceSizeMultiplier; /*!< Device size multiplier [49:47] */ + uint8_t eraseGroupSize; /*!< Erase group size [46:42] */ + uint8_t eraseGroupSizeMultiplier; /*!< Erase group size multiplier [41:37] */ + uint8_t writeProtectGroupSize; /*!< Write protect group size [36:32] */ + uint8_t defaultEcc; /*!< Manufacturer default ECC [30:29] */ + uint8_t writeSpeedFactor; /*!< Write speed factor [28:26] */ + uint8_t maxWriteBlockLength; /*!< Max. write data block length [25:22] */ + uint8_t fileFormat; /*!< File format [11:10] */ + uint8_t eccCode; /*!< ECC code [9:8] */ +} mmc_csd_t; + +/*! @brief MMC card Extended CSD register (unit: byte). */ +typedef struct _mmc_extended_csd +{ + uint32_t flags; + uint8_t SecureRemoveType; /*!< secure removal type[16]*/ + uint8_t enProductStateAware; /*!< product state awareness enablement[17]*/ + uint32_t maxPreLoadDataSize; /*!< max preload data size[21-18]*/ + uint32_t preLoadDataSize; /*!< pre-load data size[25-22]*/ + uint8_t ffuStatus; /*!< FFU status [26]*/ + uint8_t modeOperationCode; /*!< mode operation code[29]*/ + uint8_t modeConfig; /*!< mode config [30]*/ + uint8_t cacheCtrl; /*!< control to turn on/off cache[33]*/ + uint8_t pwroffNotify; /*!< power off notification[34]*/ + uint8_t packedCmdFailIndex; /*!< packed cmd fail index [35]*/ + uint8_t packedCmdStatus; /*!< packed cmd status[36]*/ + uint32_t contextConfig[4U]; /*!< context configuration[51-37]*/ + uint16_t extPartitionAttr; /*!< extended partitions attribut[53-52]*/ + uint16_t exceptEventStatus; /*!< exception events status[55-54]*/ + uint16_t exceptEventControl; /*!< exception events control[57-56]*/ + uint8_t toReleaseAddressedGroup; /*!< number of group to be released[58]*/ + uint8_t class6CmdCtrl; /*!< class 6 command control[59]*/ + uint8_t intTimeoutEmu; /*!< 1st initiallization after disabling sector size emu[60]*/ + uint8_t sectorSize; /*!< sector size[61] */ + uint8_t sectorSizeEmu; /*!< sector size emulation[62]*/ + uint8_t nativeSectorSize; /*!< native sector size[63]*/ + uint8_t periodWakeup; /*!< period wakeup [131]*/ + uint8_t tCASESupport; /*!< package case temperature is controlled[132]*/ + uint8_t productionStateAware; /*!< production state awareness[133]*/ + uint32_t enhanceUsrDataStartAddr; /*!< enhanced user data start addr [139-136]*/ + uint32_t enhanceUsrDataSize; /*!< enhanced user data area size[142-140]*/ + uint32_t generalPartitionSize[3]; /*!< general purpose partition size[154-143]*/ + uint8_t partitionAttribute; /*!< partition attribute [156]*/ + uint32_t maxEnhanceAreaSize; /*!< max enhance area size [159-157]*/ + uint8_t hpiManagementEn; /*!< HPI management [161]*/ + uint8_t writeReliabilityParameter; /*!< write reliability parameter register[166] */ + uint8_t writeReliabilitySet; /*!< write reliability setting register[167] */ + uint8_t rpmbSizeMult; /*!< RPMB size multi [168]*/ + uint8_t fwConfig; /*!< FW configuration[169]*/ + uint8_t userWPRegister; /*!< user write protect register[171] */ + uint8_t bootWPRegister; /*!< boot write protect register[173]*/ + uint8_t bootWPStatusRegister; /*!< boot write protect status register[174]*/ + uint8_t highDensityEraseGroupDefinition; /*!< High-density erase group definition [175] */ + uint8_t bootDataBusWidth; /*!< Boot bus width [177] */ + uint8_t bootConfigProtect; /*!< Boot config protection [178]*/ + uint8_t partitionConfig; /*!< Boot configuration [179] */ + uint8_t eraseMemoryContent; /*!< Erased memory content [181] */ + uint8_t dataBusWidth; /*!< Data bus width mode [183] */ + uint8_t highSpeedTiming; /*!< High-speed interface timing [185] */ + uint8_t powerClass; /*!< Power class [187] */ + uint8_t commandSetRevision; /*!< Command set revision [189] */ + uint8_t commandSet; /*!< Command set [191] */ + uint8_t extendecCsdVersion; /*!< Extended CSD revision [192] */ + uint8_t csdStructureVersion; /*!< CSD structure version [194] */ + uint8_t cardType; /*!< Card Type [196] */ + uint8_t ioDriverStrength; /*!< IO driver strength [197] */ + uint8_t OutofInterruptBusyTiming; /*!< out of interrupt busy timing [198] */ + uint8_t partitionSwitchTiming; /*!< partition switch timing [199] */ + uint8_t powerClass52MHz195V; /*!< Power Class for 52MHz @ 1.95V [200] */ + uint8_t powerClass26MHz195V; /*!< Power Class for 26MHz @ 1.95V [201] */ + uint8_t powerClass52MHz360V; /*!< Power Class for 52MHz @ 3.6V [202] */ + uint8_t powerClass26MHz360V; /*!< Power Class for 26MHz @ 3.6V [203] */ + uint8_t minimumReadPerformance4Bit26MHz; /*!< Minimum Read Performance for 4bit at 26MHz [205] */ + uint8_t minimumWritePerformance4Bit26MHz; /*!< Minimum Write Performance for 4bit at 26MHz [206] */ + uint8_t minimumReadPerformance8Bit26MHz4Bit52MHz; + /*!< Minimum read Performance for 8bit at 26MHz/4bit @52MHz [207] */ + uint8_t minimumWritePerformance8Bit26MHz4Bit52MHz; + /*!< Minimum Write Performance for 8bit at 26MHz/4bit @52MHz [208] */ + uint8_t minimumReadPerformance8Bit52MHz; /*!< Minimum Read Performance for 8bit at 52MHz [209] */ + uint8_t minimumWritePerformance8Bit52MHz; /*!< Minimum Write Performance for 8bit at 52MHz [210] */ + uint32_t sectorCount; /*!< Sector Count [215:212] */ + uint8_t sleepNotificationTimeout; /*!< sleep notification timeout [216]*/ + uint8_t sleepAwakeTimeout; /*!< Sleep/awake timeout [217] */ + uint8_t productionStateAwareTimeout; /*!< Production state awareness timeout [218]*/ + uint8_t sleepCurrentVCCQ; /*!< Sleep current (VCCQ) [219] */ + uint8_t sleepCurrentVCC; /*!< Sleep current (VCC) [220] */ + uint8_t highCapacityWriteProtectGroupSize; /*!< High-capacity write protect group size [221] */ + uint8_t reliableWriteSectorCount; /*!< Reliable write sector count [222] */ + uint8_t highCapacityEraseTimeout; /*!< High-capacity erase timeout [223] */ + uint8_t highCapacityEraseUnitSize; /*!< High-capacity erase unit size [224] */ + uint8_t accessSize; /*!< Access size [225] */ + uint8_t bootSizeMultiplier; /*!< Boot partition size [226] */ + uint8_t bootInformation; /*!< Boot information [228] */ + uint8_t secureTrimMultiplier; /*!< secure trim multiplier[229]*/ + uint8_t secureEraseMultiplier; /*!< secure erase multiplier[230]*/ + uint8_t secureFeatureSupport; /*!< secure feature support[231]*/ + uint32_t trimMultiplier; /*!< trim multiplier[232]*/ + uint8_t minReadPerformance8bitAt52MHZDDR; /*!< Minimum read performance for 8bit at DDR 52MHZ[234]*/ + uint8_t minWritePerformance8bitAt52MHZDDR; /*!< Minimum write performance for 8bit at DDR 52MHZ[235]*/ + uint8_t powerClass200MHZVCCQ130VVCC360V; /*!< power class for 200MHZ, at VCCQ= 1.3V,VCC=3.6V[236]*/ + uint8_t powerClass200MHZVCCQ195VVCC360V; /*!< power class for 200MHZ, at VCCQ= 1.95V,VCC=3.6V[237]*/ + uint8_t powerClass52MHZDDR195V; /*!< power class for 52MHZ,DDR at Vcc 1.95V[238]*/ + uint8_t powerClass52MHZDDR360V; /*!< power class for 52MHZ,DDR at Vcc 3.6V[239]*/ + uint8_t iniTimeoutAP; /*!< 1st initialization time after partitioning[241]*/ + uint32_t correctPrgSectorNum; /*!< correct prg sectors number[245-242]*/ + uint8_t bkOpsStatus; /*!< background operations status[246]*/ + uint8_t powerOffNotifyTimeout; /*!< power off notification timeout[247]*/ + uint8_t genericCMD6Timeout; /*!< generic CMD6 timeout[248]*/ + uint32_t cacheSize; /*!< cache size[252-249]*/ + uint8_t powerClass200MHZDDR360V; /*!< power class for 200MHZ, DDR at VCC=2.6V[253]*/ + uint32_t fwVer[2U]; /*!< fw VERSION [261-254]*/ + uint16_t deviveVer; /*!< device version[263-262]*/ + uint8_t optimalTrimSize; /*!< optimal trim size[264]*/ + uint8_t optimalWriteSize; /*!< optimal write size[265]*/ + uint8_t optimalReadSize; /*!< optimal read size[266]*/ + uint8_t preEolInfo; /*!< pre EOL information[267]*/ + uint8_t deviceLifeTimeEstimationA; /*!< device life time estimation typeA[268]*/ + uint8_t deviceLifeTimeEstimationB; /*!< device life time estimation typeB[269]*/ + uint32_t correctPrgFWSectorNum; /*!< number of FW sectors correctly programmed[305-302]*/ + uint32_t ffuArg; /*!< FFU argument[490-487]*/ + uint8_t operationCodeTimeout; /*!< operation code timeout[491]*/ + uint8_t supportMode; /*!< support mode [493]*/ + uint8_t extPartitionSupport; /*!< extended partition attribute support[494]*/ + uint8_t largeUnitSize; /*!< large unit size[495]*/ + uint8_t contextManageCap; /*!< context management capability[496]*/ + uint8_t tagResourceSize; /*!< tag resource size[497]*/ + uint8_t tagUnitSize; /*!< tag unit size[498]*/ + uint8_t maxPackedWriteCmd; /*!< max packed write cmd[500]*/ + uint8_t maxPackedReadCmd; /*!< max packed read cmd[501]*/ + uint8_t hpiFeature; /*!< HPI feature[503]*/ + uint8_t supportedCommandSet; /*!< Supported Command Sets [504] */ + uint8_t extSecurityCmdError; /*!< extended security commands error[505]*/ +} mmc_extended_csd_t; + +/*! @brief The bit shift for COMMAND SET field in SWITCH command. */ +#define MMC_SWITCH_COMMAND_SET_SHIFT (0U) +/*! @brief The bit mask for COMMAND set field in SWITCH command. */ +#define MMC_SWITCH_COMMAND_SET_MASK (0x00000007U) +/*! @brief The bit shift for VALUE field in SWITCH command */ +#define MMC_SWITCH_VALUE_SHIFT (8U) +/*! @brief The bit mask for VALUE field in SWITCH command */ +#define MMC_SWITCH_VALUE_MASK (0x0000FF00U) +/*! @brief The bit shift for BYTE INDEX field in SWITCH command */ +#define MMC_SWITCH_BYTE_INDEX_SHIFT (16U) +/*! @brief The bit mask for BYTE INDEX field in SWITCH command */ +#define MMC_SWITCH_BYTE_INDEX_MASK (0x00FF0000U) +/*! @brief The bit shift for ACCESS MODE field in SWITCH command */ +#define MMC_SWITCH_ACCESS_MODE_SHIFT (24U) +/*! @brief The bit mask for ACCESS MODE field in SWITCH command */ +#define MMC_SWTICH_ACCESS_MODE_MASK (0x03000000U) + +/*! @brief MMC Extended CSD configuration. */ +typedef struct _mmc_extended_csd_config +{ + mmc_command_set_t commandSet; /*!< Command set */ + uint8_t ByteValue; /*!< The value to set */ + uint8_t ByteIndex; /*!< The byte index in Extended CSD(mmc_extended_csd_index_t) */ + mmc_extended_csd_access_mode_t accessMode; /*!< Access mode */ +} mmc_extended_csd_config_t; + +#endif /* _FSL_SPECIFICATION_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/usdhc_config.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/usdhc_config.h new file mode 100644 index 0000000000..89aeab6769 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/drivers/usdhc/usdhc_config.h @@ -0,0 +1,49 @@ +/* + * SD-Card board config + * SD-Card board config file + * + * Change Logs: + * Date Author Notes + * 2021-04-23 Lyons first version + */ + +#ifndef _BOARD_SDCARD_H_ +#define _BOARD_SDCARD_H_ + +#define BOARD_SD_PIN_CONFIG(speed, strength) +#define BOARD_MMC_PIN_CONFIG(speed, strength) + +#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() +#define BOARD_USDHC_SDCARD_POWER_CONTROL(state) + +#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() +#define BOARD_USDHC_MMCCARD_POWER_CONTROL(state) + +/* + * Insert detection is not used + * Following setting no needed to care + */ +#define BOARD_USDHC_CD_STATUS() 0 +#define BOARD_USDHC_CD_GPIO_INIT() +#define BOARD_USDHC_CD_INTERRUPT_STATUS() 0 +#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) + +#define BOARD_USDHC_CD_GPIO_BASE GPIO1 +#define BOARD_USDHC_CD_GPIO_PIN 19 +#define BOARD_USDHC_CD_PORT_IRQ GPIO1_Combined_16_31_IRQn +#define BOARD_USDHC_CD_PORT_IRQ_HANDLER GPIO_IRQ_Handler + +#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U)) +#define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U)) + +#define BOARD_SD_HOST_BASEADDR USDHC1_BASE +#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC1_CLK_FREQ +#define BOARD_SD_HOST_IRQ USDHC1_IRQn + +#define BOARD_SD_SUPPORT_180V (0U) +#define BOARD_MMC_SUPPORT_8BIT_BUS (0U) + +#define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (130000000U) +#define BOARD_SD_HOST_SUPPORT_HS200_FREQ (150000000U) + +#endif /* _BOARD_SDCARD_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/fsl_device_registers.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/fsl_device_registers.h new file mode 100644 index 0000000000..d89474b8a1 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/fsl_device_registers.h @@ -0,0 +1,59 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +#include //define CPU Type here + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCIMX6Y2CVM05) || defined(CPU_MCIMX6Y2CVM08) || defined(CPU_MCIMX6Y2DVM05) || \ + defined(CPU_MCIMX6Y2DVM09)) + +#define MCIMX6Y2_SERIES + +/* CMSIS-style register definitions */ +#include "MCIMX6Y2.h" +/* CPU specific feature definitions */ +#include "MCIMX6Y2_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/system_MCIMX6Y2.c b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/system_MCIMX6Y2.c new file mode 100644 index 0000000000..d6717da2ac --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/system_MCIMX6Y2.c @@ -0,0 +1,489 @@ +/* +** ################################################################### +** Processors: MCIMX6Y2CVM05 +** MCIMX6Y2CVM08 +** MCIMX6Y2DVM05 +** MCIMX6Y2DVM09 +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: IMX6ULLRM, Rev. 1, Feb. 2017 +** Version: rev. 3.0, 2017-02-28 +** Build: b170410 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-12-18) +** Initial version. +** - rev. 2.0 (2016-08-02) +** Rev.B Header GA +** - rev. 3.0 (2017-02-28) +** Rev.1 Header GA +** +** ################################################################### +*/ + +/*! + * @file MCIMX6Y2 + * @version 3.0 + * @date 2017-02-28 + * @brief Device specific configuration file for MCIMX6Y2 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +/* Transaction Drivers Handler Declaration */ +extern void CAN1_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void CAN2_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void ECSPI1_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void ECSPI2_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void ECSPI3_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void ECSPI4_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void ENET1_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void ENET1_Driver1588IRQHandler (uint32_t giccIar, void *userParam); +extern void ENET2_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void ENET2_Driver1588IRQHandler (uint32_t giccIar, void *userParam); +extern void I2C1_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void I2C2_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void I2C3_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void I2C4_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void I2S1_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void I2S2_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void I2S3_Tx_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void I2S3_Rx_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART1_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART2_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART3_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART4_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART5_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART6_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART7_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void UART8_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void USDHC1_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void USDHC2_DriverIRQHandler (uint32_t giccIar, void *userParam); +extern void SDMA_DriverIRQHandler (uint32_t giccIar, void *userParam); + +#if defined(__IAR_SYSTEMS_ICC__) +#pragma weak CAN1_DriverIRQHandler=defaultIrqHandler +#pragma weak CAN2_DriverIRQHandler=defaultIrqHandler +#pragma weak ECSPI1_DriverIRQHandler=defaultIrqHandler +#pragma weak ECSPI2_DriverIRQHandler=defaultIrqHandler +#pragma weak ECSPI3_DriverIRQHandler=defaultIrqHandler +#pragma weak ECSPI4_DriverIRQHandler=defaultIrqHandler +#pragma weak ENET1_DriverIRQHandler=defaultIrqHandler +#pragma weak ENET2_DriverIRQHandler=defaultIrqHandler +#pragma weak ENET1_Driver1588IRQHandler=defaultIrqHandler +#pragma weak ENET2_Driver1588IRQHandler=defaultIrqHandler +#pragma weak I2C1_DriverIRQHandler=defaultIrqHandler +#pragma weak I2C2_DriverIRQHandler=defaultIrqHandler +#pragma weak I2C3_DriverIRQHandler=defaultIrqHandler +#pragma weak I2C4_DriverIRQHandler=defaultIrqHandler +#pragma weak I2S1_DriverIRQHandler=defaultIrqHandler +#pragma weak I2S2_DriverIRQHandler=defaultIrqHandler +#pragma weak I2S3_Tx_DriverIRQHandler=defaultIrqHandler +#pragma weak I2S3_Rx_DriverIRQHandler=defaultIrqHandler +#pragma weak UART1_DriverIRQHandler=defaultIrqHandler +#pragma weak UART2_DriverIRQHandler=defaultIrqHandler +#pragma weak UART3_DriverIRQHandler=defaultIrqHandler +#pragma weak UART4_DriverIRQHandler=defaultIrqHandler +#pragma weak UART5_DriverIRQHandler=defaultIrqHandler +#pragma weak UART6_DriverIRQHandler=defaultIrqHandler +#pragma weak UART7_DriverIRQHandler=defaultIrqHandler +#pragma weak UART8_DriverIRQHandler=defaultIrqHandler +#pragma weak USDHC1_DriverIRQHandler=defaultIrqHandler +#pragma weak USDHC2_DriverIRQHandler=defaultIrqHandler +#pragma weak SDMA_DriverIRQHandler=defaultIrqHandler +#elif defined(__GNUC__) +void CAN1_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void CAN2_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ECSPI1_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ECSPI2_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ECSPI3_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ECSPI4_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ENET1_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ENET2_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ENET1_Driver1588IRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void ENET2_Driver1588IRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2C1_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2C2_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2C3_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2C4_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2S1_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2S2_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2S3_Tx_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void I2S3_Rx_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART1_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART2_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART3_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART4_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART5_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART6_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART7_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void UART8_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void USDHC1_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void USDHC2_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +void SDMA_DriverIRQHandler() __attribute__((weak, alias("defaultIrqHandler"))); +#else + #error Not supported compiler type +#endif + +extern uint32_t __VECTOR_TABLE[]; + +/* Local irq table and nesting level value */ +static sys_irq_handle_t irqTable[NUMBER_OF_INT_VECTORS]; +static uint32_t irqNesting; + +/* Local IRQ functions */ +static void defaultIrqHandler (uint32_t giccIar, void *userParam) { + while(1) { + } +} + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { + uint32_t sctlr; + uint32_t actlr; +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + uint32_t cpacr; + uint32_t fpexc; +#endif + + L1C_InvalidateInstructionCacheAll(); + L1C_InvalidateDataCacheAll(); + + actlr = __get_ACTLR(); + actlr = (actlr | ACTLR_SMP_Msk); /* Change to SMP mode before enable DCache */ + __set_ACTLR(actlr); + + sctlr = __get_SCTLR(); + sctlr = (sctlr & ~(SCTLR_V_Msk | /* Use low vector */ + SCTLR_A_Msk | /* Disable alignment fault checking */ + SCTLR_M_Msk)) /* Disable MMU */ + | (SCTLR_I_Msk | /* Enable ICache */ + SCTLR_Z_Msk | /* Enable Prediction */ + SCTLR_CP15BEN_Msk | /* Enable CP15 barrier operations */ + SCTLR_C_Msk); /* Enable DCache */ + __set_SCTLR(sctlr); + + /* Set vector base address */ + GIC_Init(); + __set_VBAR((uint32_t)__VECTOR_TABLE); + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + cpacr = __get_CPACR(); + /* Enable NEON and FPU */ + cpacr = (cpacr & ~(CPACR_ASEDIS_Msk | CPACR_D32DIS_Msk)) + | (3UL << CPACR_cp10_Pos) | (3UL << CPACR_cp11_Pos); + __set_CPACR(cpacr); + + fpexc = __get_FPEXC(); + fpexc |= 0x40000000UL; /* Enable NEON and FPU */ + __set_FPEXC(fpexc); +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + /* i.MX6ULL systemCoreClockUpdate */ + uint32_t PLL1SWClock; + uint32_t PLL2MainClock; + if (CCM->CCSR & CCM_CCSR_PLL1_SW_CLK_SEL_MASK) + { + if (CCM->CCSR & CCM_CCSR_STEP_SEL_MASK) + { + /* Get SYS PLL clock*/ + if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) + { + PLL2MainClock = (24000000UL * 22UL + (uint64_t)(24000000UL) * (uint64_t)(CCM_ANALOG->PLL_SYS_NUM) / (uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + } + else + { + PLL2MainClock = (24000000UL * 20UL + (uint64_t)(24000000UL) * (uint64_t)(CCM_ANALOG->PLL_SYS_NUM) / (uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + } + + if (CCM->CCSR & CCM_CCSR_SECONDARY_CLK_SEL_MASK) + { + /* PLL2 ---> Secondary_clk ---> Step Clock ---> CPU Clock */ + PLL1SWClock = PLL2MainClock; + } + else + { + /* PLL2 PFD2 ---> Secondary_clk ---> Step Clock ---> CPU Clock */ + PLL1SWClock = ((uint64_t)PLL2MainClock * 18) / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT); + } + } + else + { + /* Osc_clk (24M) ---> Step Clock ---> CPU Clock */ + PLL1SWClock = 24000000UL; + } + } + else + { + /* ARM PLL ---> CPU Clock */ + PLL1SWClock = 24000000UL; + PLL1SWClock = ( PLL1SWClock * (CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT) >> 1UL; + } + + SystemCoreClock = PLL1SWClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1UL); +} + +/* ---------------------------------------------------------------------------- + -- SystemInitIrqTable() + ---------------------------------------------------------------------------- */ + +void SystemInitIrqTable (void) { + uint32_t i; + + /* First set all handler to default */ + for (i = 0; i < NUMBER_OF_INT_VECTORS; i++) { + SystemInstallIrqHandler((IRQn_Type)i, defaultIrqHandler, NULL); + } + + /* Then set transaction drivers handler */ + /* FlexCAN transaction drivers handler */ + SystemInstallIrqHandler(CAN1_IRQn, CAN1_DriverIRQHandler, NULL); + SystemInstallIrqHandler(CAN2_IRQn, CAN2_DriverIRQHandler, NULL); + /* ECSPI transaction drivers handler */ + SystemInstallIrqHandler(eCSPI1_IRQn, ECSPI1_DriverIRQHandler, NULL); + SystemInstallIrqHandler(eCSPI2_IRQn, ECSPI2_DriverIRQHandler, NULL); + SystemInstallIrqHandler(eCSPI3_IRQn, ECSPI3_DriverIRQHandler, NULL); + SystemInstallIrqHandler(eCSPI4_IRQn, ECSPI4_DriverIRQHandler, NULL); + /* ENET transaction drivers handler */ + SystemInstallIrqHandler(ENET1_IRQn, ENET1_DriverIRQHandler, NULL); + SystemInstallIrqHandler(ENET1_1588_IRQn, ENET1_Driver1588IRQHandler, NULL); + SystemInstallIrqHandler(ENET2_IRQn, ENET2_DriverIRQHandler, NULL); + SystemInstallIrqHandler(ENET2_1588_IRQn, ENET2_Driver1588IRQHandler, NULL); + /* I2C transaction drivers handler */ + SystemInstallIrqHandler(I2C1_IRQn, I2C1_DriverIRQHandler, NULL); + SystemInstallIrqHandler(I2C2_IRQn, I2C2_DriverIRQHandler, NULL); + SystemInstallIrqHandler(I2C3_IRQn, I2C3_DriverIRQHandler, NULL); + SystemInstallIrqHandler(I2C4_IRQn, I2C4_DriverIRQHandler, NULL); + /* I2S transaction drivers handler */ + SystemInstallIrqHandler(SAI1_IRQn, I2S1_DriverIRQHandler, NULL); + SystemInstallIrqHandler(SAI2_IRQn, I2S2_DriverIRQHandler, NULL); + SystemInstallIrqHandler(SAI3_TX_IRQn, I2S3_Tx_DriverIRQHandler, NULL); + SystemInstallIrqHandler(SAI3_RX_IRQn, I2S3_Rx_DriverIRQHandler, NULL); + /* UART transaction drivers handler */ + SystemInstallIrqHandler(UART1_IRQn, UART1_DriverIRQHandler, NULL); + SystemInstallIrqHandler(UART2_IRQn, UART2_DriverIRQHandler, NULL); + SystemInstallIrqHandler(UART3_IRQn, UART3_DriverIRQHandler, NULL); + SystemInstallIrqHandler(UART4_IRQn, UART4_DriverIRQHandler, NULL); + SystemInstallIrqHandler(UART5_IRQn, UART5_DriverIRQHandler, NULL); + SystemInstallIrqHandler(UART6_IRQn, UART6_DriverIRQHandler, NULL); + SystemInstallIrqHandler(UART7_IRQn, UART7_DriverIRQHandler, NULL); + SystemInstallIrqHandler(UART8_IRQn, UART8_DriverIRQHandler, NULL); + /* USDHC transaction drivers handler */ + SystemInstallIrqHandler(USDHC1_IRQn, USDHC1_DriverIRQHandler, NULL); + SystemInstallIrqHandler(USDHC2_IRQn, USDHC2_DriverIRQHandler, NULL); + /* SDMA transaction driver handler */ + SystemInstallIrqHandler(SDMA_IRQn, SDMA_DriverIRQHandler, NULL); +} + +/* ---------------------------------------------------------------------------- + -- SystemInstallIrqHandler() + ---------------------------------------------------------------------------- */ + +void SystemInstallIrqHandler(IRQn_Type irq, system_irq_handler_t handler, void *userParam) { + irqTable[irq].irqHandler = handler; + irqTable[irq].userParam = userParam; +} + +/* ---------------------------------------------------------------------------- + -- SystemIrqHandler() + ---------------------------------------------------------------------------- */ + +#if defined(__IAR_SYSTEMS_ICC__) +#pragma weak SystemIrqHandler +void SystemIrqHandler(uint32_t giccIar) { +#elif defined(__GNUC__) +__attribute__((weak)) void SystemIrqHandler(uint32_t giccIar) { +#else + #error Not supported compiler type +#endif + uint32_t intNum = giccIar & 0x3FFUL; + + /* Spurious interrupt ID or Wrong interrupt number */ + if ((intNum == 1023) || (intNum >= NUMBER_OF_INT_VECTORS)) + { + return; + } + + irqNesting++; + + __enable_irq(); /* Support nesting interrupt */ + + /* Now call the real irq handler for intNum */ + irqTable[intNum].irqHandler(giccIar, irqTable[intNum].userParam); + + __disable_irq(); + + irqNesting--; +} + +uint32_t SystemGetIRQNestingLevel(void) +{ + return irqNesting; +} + +/* Leverage GPT1 to provide Systick */ +void SystemSetupSystick(uint32_t tickRateHz, void *tickHandler, uint32_t intPriority) +{ + uint32_t clockFreq; + uint32_t spllTmp; + + /* Install IRQ handler for GPT1 */ + SystemInstallIrqHandler(GPT1_IRQn, (system_irq_handler_t)(uint32_t)tickHandler, NULL); + + /* Enable Systick all the time */ + CCM->CCGR1 |= CCM_CCGR1_CG10_MASK | CCM_CCGR1_CG11_MASK; + + GPT1->CR = GPT_CR_SWR_MASK; + /* Wait reset finished. */ + while (GPT1->CR == GPT_CR_SWR_MASK) + { + } + /* Use peripheral clock source IPG */ + GPT1->CR = GPT_CR_WAITEN_MASK | GPT_CR_STOPEN_MASK | GPT_CR_DOZEEN_MASK | + GPT_CR_DBGEN_MASK | GPT_CR_ENMOD_MASK | GPT_CR_CLKSRC(1UL); + /* Set clock divider to 1 */ + GPT1->PR = 0; + + /* Get IPG clock*/ + /* Periph_clk2_clk ---> Periph_clk */ + if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) + { + switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) + { + /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(0U): + clockFreq = (24000000UL * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + break; + + /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(1U): + clockFreq = 24000000UL; + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): + default: + clockFreq = 0U; + break; + } + + clockFreq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); + } + /* Pll2_main_clk ---> Periph_clk */ + else + { + /* Get SYS PLL clock*/ + if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) + { + spllTmp = (24000000UL * 22UL + (uint64_t)(24000000UL) * (uint64_t)(CCM_ANALOG->PLL_SYS_NUM) / (uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + } + else + { + spllTmp = (24000000UL * 20UL + (uint64_t)(24000000UL) * (uint64_t)(CCM_ANALOG->PLL_SYS_NUM) / (uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + } + + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + { + /* PLL2 ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): + clockFreq = spllTmp; + break; + + /* PLL2 PFD2 ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): + clockFreq = ((uint64_t)spllTmp * 18) / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT); + break; + + /* PLL2 PFD0 ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): + clockFreq = ((uint64_t)spllTmp * 18) / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT); + break; + + /* PLL2 PFD2 divided(/2) ---> Pll2_main_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): + clockFreq = ((((uint64_t)spllTmp * 18) / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) >> 1U); + break; + + default: + clockFreq = 0U; + break; + } + } + clockFreq /= (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); + clockFreq /= (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U); + + /* Set timeout value and enable interrupt */ + GPT1->OCR[0] = clockFreq / tickRateHz - 1UL; + GPT1->IR = GPT_IR_OF1IE_MASK; + + /* Set interrupt priority */ + GIC_SetPriority(GPT1_IRQn, intPriority); + /* Enable IRQ */ + GIC_EnableIRQ(GPT1_IRQn); + + /* Start GPT counter */ + GPT1->CR |= GPT_CR_EN_MASK; +} + +void SystemClearSystickFlag(void) +{ + GPT1->SR = GPT_SR_OF1_MASK; +} diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/system_MCIMX6Y2.h b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/system_MCIMX6Y2.h new file mode 100644 index 0000000000..c8b88e8c8c --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/MCIMX6Y2/system_MCIMX6Y2.h @@ -0,0 +1,176 @@ +/* +** ################################################################### +** Processors: MCIMX6Y2CVM05 +** MCIMX6Y2CVM08 +** MCIMX6Y2DVM05 +** MCIMX6Y2DVM09 +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: IMX6ULLRM, Rev. 1, Feb. 2017 +** Version: rev. 3.0, 2017-02-28 +** Build: b170410 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-12-18) +** Initial version. +** - rev. 2.0 (2016-08-02) +** Rev.B Header GA +** - rev. 3.0 (2017-02-28) +** Rev.1 Header GA +** +** ################################################################### +*/ + +/*! + * @file MCIMX6Y2 + * @version 3.0 + * @date 2017-02-28 + * @brief Device specific configuration file for MCIMX6Y2 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCIMX6Y2_H_ +#define _SYSTEM_MCIMX6Y2_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 528000000u /* Default System clock value */ + +typedef void (*system_irq_handler_t) (uint32_t giccIar, void *param); +/** + * @brief IRQ handle for specific IRQ + */ +typedef struct _sys_irq_handle +{ + system_irq_handler_t irqHandler; /**< IRQ handler for specific IRQ */ + void *userParam; /**< User param for handler callback */ +} sys_irq_handle_t; + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief Initialize IRQ table, set default handlers + */ +void SystemInitIrqTable (void); + +/** + * @brief Install IRQ handler for specific IRQ + * + * It can't be called at interrupt context to avoid IRQ table corrupt during interrupt preemption + * + * @param irq IRQ number corresponds to the installed handler + * @param handler IRQ handler for the IRQ number + * @param userParam User specified parameter for IRQ handler callback + */ +void SystemInstallIrqHandler (IRQn_Type irq, system_irq_handler_t handler, void *userParam); + +/** + * @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler. + * + * It is called from IRQ exception context and dispatches to registered handler according to + * GICC_IAR interrupt number. + * The default implementation is weak and user can override this function with his own SystemIrqHandler. + * + * @param giccIar IRQ acknowledge value read from GICC_IAR + */ +void SystemIrqHandler (uint32_t giccIar); + +/** + * @brief Get IRQ nesting level of current context. + * + * If the return value is 0, then the context is not ISR, otherwise the context is ISR. + * + * @return IRQ nesting level + */ +uint32_t SystemGetIRQNestingLevel (void); + +/** + * @brief Setup systick for RTOS system. + * + * @param tickRateHz Tick number per second + * @param tickHandler IRQ callback handler for tick + * @param intPriority IRQ interrupt priority (the smaller, the higher priority) + */ +void SystemSetupSystick (uint32_t tickRateHz, void *tickHandler, uint32_t intPriority); + +/** + * @brief Clear systick flag status so that next tick interrupt may occur. + */ +void SystemClearSystickFlag (void); +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCIMX6Y2_H_ */ diff --git a/bsp/imx6ull-artpi-smart/libraries/sdk/devices/SConscript b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/SConscript new file mode 100644 index 0000000000..4c815c49b8 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/libraries/sdk/devices/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imx6ull-artpi-smart/link.lds b/bsp/imx6ull-artpi-smart/link.lds new file mode 100644 index 0000000000..8814055cdb --- /dev/null +++ b/bsp/imx6ull-artpi-smart/link.lds @@ -0,0 +1,104 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SECTIONS +{ + . = 0x80001000; + + __text_start = .; + .text : + { + *(.vectors) + *(.text) + *(.text.*) + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } =0 + __text_end = .; + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } + __rodata_end = .; + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(8); + __data_start = .; + .data : + { + *(.data) + *(.data.*) + } + __data_end = .; + + . = ALIGN(8); + __bss_start = .; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } + . = ALIGN(4); + __bss_end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + _end = .; +} diff --git a/bsp/imx6ull-artpi-smart/link_smart.lds b/bsp/imx6ull-artpi-smart/link_smart.lds new file mode 100644 index 0000000000..e9227757c8 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/link_smart.lds @@ -0,0 +1,105 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SECTIONS +{ + /*. = 0x80001000; */ + . = 0xc0001000; + + __text_start = .; + .text : + { + *(.vectors) + *(.text) + *(.text.*) + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } =0 + __text_end = .; + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } + __rodata_end = .; + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(8); + __data_start = .; + .data : + { + *(.data) + *(.data.*) + } + __data_end = .; + + . = ALIGN(8); + __bss_start = .; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } + . = ALIGN(4); + __bss_end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + _end = .; +} diff --git a/bsp/imx6ull-artpi-smart/mkimage.py b/bsp/imx6ull-artpi-smart/mkimage.py new file mode 100644 index 0000000000..592f7bb8c0 --- /dev/null +++ b/bsp/imx6ull-artpi-smart/mkimage.py @@ -0,0 +1,235 @@ +# @Time : 2020/12/31 +# @Author : David Dai +# @File : mkimage.py +#!/usr/bin/python2 + +import os +import argparse +import struct + +parser = argparse.ArgumentParser() + +parser.add_argument('-t', '--type') +parser.add_argument('-b', '--bin') +parser.add_argument('-o', '--out', default = "load.bin") +parser.add_argument('-g', '--img', default = "load.img") +parser.add_argument('-a', '--addr', default = "0x00000000") +parser.add_argument('-e', '--ep', default = "0x00000000") + +args = parser.parse_args() + +args.addr = int(args.addr, 16) +args.ep = int(args.ep, 16) + +def stm32image(): + checksum = 0 + + with open(args.out, 'wb') as f: + #write head 'STM32' + f.write(struct.pack('H', 32)) + f.write(struct.pack('H', (len(dcdConfig) << 3) + 8)) + f.write(struct.pack('H', (len(dcdConfig) << 3) + 4)) + f.write(struct.pack('I', int(d[0], 16))) + f.write(struct.pack('>I', int(d[1], 16))) + + #padding data + for i in range(0x27B): + f.write(struct.pack(' rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +\ + 'python mkimage.py ' + MKIMAGE + '\n' -- Gitee