diff --git a/components/finsh/msh.c b/components/finsh/msh.c index 690ffcc86f2255a13016b45506a27bed10c61d1d..1ebb21df087c62e09806f30e7b1a9018f53fc953 100644 --- a/components/finsh/msh.c +++ b/components/finsh/msh.c @@ -296,8 +296,18 @@ static int _msh_exec_cmd(char *cmd, rt_size_t length, int *retp) return 0; } +#ifdef RT_USING_GDBSERVER +pid_t exec(char*, int, int, char**); +#else +pid_t exec(char*, int, char**); +#endif + #if defined(RT_USING_LWP) && defined(RT_USING_DFS) -static int _msh_exec_lwp(char *cmd, rt_size_t length) +#ifdef RT_USING_GDBSERVER +int _msh_exec_lwp(int debug, char *cmd, rt_size_t length) +#else +int _msh_exec_lwp(char *cmd, rt_size_t length) +#endif { int argc; int cmd0_size = 0; @@ -305,8 +315,6 @@ static int _msh_exec_lwp(char *cmd, rt_size_t length) int fd = -1; char *pg_name; - extern int exec(char*, int, char**); - /* find the size of first command */ while ((cmd[cmd0_size] != ' ' && cmd[cmd0_size] != '\t') && cmd0_size < length) cmd0_size ++; @@ -354,8 +362,12 @@ static int _msh_exec_lwp(char *cmd, rt_size_t length) /* found program */ close(fd); - exec(pg_name, argc, argv); +#ifdef RT_USING_GDBSERVER + exec(pg_name, debug, argc, argv); +#else + exec(pg_name, argc, argv); +#endif if (pg_name != argv[0]) rt_free(pg_name); @@ -529,7 +541,12 @@ int msh_exec(char *cmd, rt_size_t length) #endif #ifdef RT_USING_LWP +#ifdef RT_USING_GDBSERVER + /* exec from msh_exec , debug = 0*/ + if (_msh_exec_lwp(0, cmd, length) == 0) +#else if (_msh_exec_lwp(cmd, length) == 0) +#endif { return 0; } diff --git a/components/lwp/Kconfig b/components/lwp/Kconfig index 855360334393da362180a61914f309dc578f0583..da5ca2a1906ad0a6b73c559cdc7d33ca6d758d13 100644 --- a/components/lwp/Kconfig +++ b/components/lwp/Kconfig @@ -19,11 +19,6 @@ config LWP_TASK_STACK_SIZE default 16384 depends on RT_USING_LWP -config RT_USING_GDBSERVER - bool "Using gdbserver" - default y - depends on RT_USING_USERSPACE - config RT_CH_MSG_MAX_NR int "The maximum number of channel messages" default 1024 @@ -66,4 +61,4 @@ config LWP_PTY_USING_DEBUG default n depends on RT_USING_LWP depends on LWP_UNIX98_PTY - \ No newline at end of file + diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S b/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S index ccd3254255a7cb89b6b8124fb4d82c44efed48d5..d5d2ade5bc33ae58779002390e26a62c9cf46b66 100644 --- a/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S +++ b/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S @@ -198,9 +198,10 @@ SVC_Handler: bl lwp_user_setting_save ldp x8, x9, [sp, #(CONTEXT_OFFSET_X8)] - uxtb x0, w8 - cmp x0, #0xfe + and x0, x8, #0xf000 + cmp x0, #0xe000 beq lwp_signal_quit + uxtb x0, w8 bl lwp_get_sys_api cmp x0, xzr mov x30, x0 @@ -395,7 +396,7 @@ user_do_signal: eret lwp_sigreturn: - mov x8, #0xfe + mov x8, #0xe000 svc #0 lwp_thread_return: diff --git a/components/lwp/arch/arm/cortex-a/lwp_arch.h b/components/lwp/arch/arm/cortex-a/lwp_arch.h index efae56651ccf51f0a3820c57bc791834c1ea365e..90b2ded273e9d540a1510885ee7732a4d9bcb9e5 100644 --- a/components/lwp/arch/arm/cortex-a/lwp_arch.h +++ b/components/lwp/arch/arm/cortex-a/lwp_arch.h @@ -38,6 +38,11 @@ rt_inline unsigned long ffz(unsigned long x) return __builtin_ffs(~x) - 1; } +rt_inline void icache_invalid_all(void) +{ + asm volatile ("mcr p15, 0, r0, c7, c5, 0\ndsb\nisb":::"memory");//iciallu +} + #ifdef __cplusplus } #endif diff --git a/components/lwp/arch/arm/cortex-a/lwp_gcc.S b/components/lwp/arch/arm/cortex-a/lwp_gcc.S index e1240ad1b3fc43091e70f998dacad79b51b0df9e..45eeea3933476b25098913487fbef7f10342cbef 100644 --- a/components/lwp/arch/arm/cortex-a/lwp_gcc.S +++ b/components/lwp/arch/arm/cortex-a/lwp_gcc.S @@ -153,13 +153,15 @@ vector_swi: bl rt_thread_self bl lwp_user_setting_save - and r0, r7, #0xff - cmp r0, #0xfe + and r0, r7, #0xf000 + cmp r0, #0xe000 beq lwp_signal_quit + #ifdef RT_USING_GDBSERVER - cmp r0, #0xff + cmp r0, #0xf000 beq ret_from_user #endif + and r0, r7, #0xff bl lwp_get_sys_api cmp r0, #0 /* r0 = api */ mov lr, r0 @@ -304,11 +306,11 @@ user_do_signal: movs pc, lr lwp_debugreturn: - mov r7, #0xff + mov r7, #0xf000 svc #0 lwp_sigreturn: - mov r7, #0xfe + mov r7, #0xe000 svc #0 lwp_thread_return: diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c index b52fab776fbe95ab8511a82491b2569caa6b98da..706f809e5f53d4e3c3f187ea16fce19faafcb8fa 100644 --- a/libcpu/arm/cortex-a/trap.c +++ b/libcpu/arm/cortex-a/trap.c @@ -35,83 +35,86 @@ static int check_debug_event(struct rt_hw_exp_stack *regs, uint32_t pc_adj) { uint32_t mode = regs->cpsr; - if ((mode & 0x1f) == 0x10) + if ((mode & 0x1f) == 0x10) /* is user mode */ { - /* + struct rt_channel_msg msg; + gdb_thread_info thread_info; uint32_t ifsr, dfar, dfsr; - */ - uint32_t ifsr, dfar; int ret; - asm volatile ("MRC p15, 0, %0, c5, c0, 1":"=r"(ifsr)); - ifsr &= ((1UL << 10) | 0xfUL); - if (ifsr == 0x2UL) + if (pc_adj == 4) /* pabt */ { - uint32_t dbgdscr; - struct rt_channel_msg msg; - gdb_thread_info thread_info; - - regs->pc -= pc_adj; - - asm volatile ("MRC p14, 0, %0, c0, c1, 0":"=r"(dbgdscr)); - switch ((dbgdscr & (0xfUL << 2))) + /* check breakpoint event */ + asm volatile ("MRC p15, 0, %0, c5, c0, 1":"=r"(ifsr)); + ifsr &= ((1UL << 12) | 0x3fUL); /* status */ + if (ifsr == 0x2UL) { - case (0x1UL << 2): //breadkpoint - case (0x3UL << 2): //bkpt - do { - struct rt_lwp *gdb_lwp = gdb_get_dbg_lwp(); - struct rt_lwp *lwp; - - if (!gdb_lwp) - { - break; - } - lwp = lwp_self(); - if (lwp == gdb_lwp) - { - break; - } - *(uint32_t*)regs->pc = lwp->bak_first_ins; - rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void*)regs->pc, 4); - icache_invalid_all(); - lwp->debug = 0; - return 1; - } while (0); - - thread_info.notify_type = GDB_NOTIFIY_BREAKPOINT; - thread_info.abt_ins = *(uint32_t*)regs->pc; - ret = 1; - break; - case (0xaUL << 2): //watchpoint - asm volatile ("MRC p15, 0, %0, c6, c0, 0":"=r"(dfar)); - thread_info.watch_addr = (void*)dfar; - /* - asm volatile ("MRC p15, 0, %0, c5, c0, 0":"=r"(dfsr)); - thread_info.rw = (1UL << ((dfsr >> 11) & 1UL)); - */ - thread_info.rw = (1UL << (((~*(uint32_t*)regs->pc) >> 20) & 1UL)); - thread_info.notify_type = GDB_NOTIFIY_WATCHPOINT; - ret = 2; - break; - default: - return 0; + /* is breakpoint event */ + regs->pc -= pc_adj; + do { + struct rt_lwp *gdb_lwp = gdb_get_dbg_lwp(); + struct rt_lwp *lwp; + + if (!gdb_lwp) + { + break; + } + lwp = lwp_self(); + if (lwp == gdb_lwp) + { + break; + } + *(uint32_t *)regs->pc = lwp->bak_first_ins; + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)regs->pc, 4); + icache_invalid_all(); + lwp->debug = 0; + return 1; + } while (0); + + thread_info.notify_type = GDB_NOTIFIY_BREAKPOINT; + thread_info.abt_ins = *(uint32_t *)regs->pc; + ret = 1; } - thread_info.thread = rt_thread_self(); - thread_info.thread->regs = regs; - msg.u.d = (void*)&thread_info; - dmb(); - thread_info.thread->debug_suspend = 1; - dsb(); - rt_thread_suspend_witch_flag(thread_info.thread, RT_UNINTERRUPTIBLE); - rt_raw_channel_send(gdb_get_server_channel(), &msg); - rt_schedule(); - while (thread_info.thread->debug_suspend) + else + { + return 0; /* not debug pabt */ + } + } + else + { + /* watchpoing event */ + asm volatile ("MRC p15, 0, %0, c5, c0, 0":"=r"(dfsr)); + dfsr = (((dfsr & (1UL << 10)) >> 6) | (dfsr & 0xfUL)); /* status */ + if (dfsr == 0x2UL) + { + /* is watchpoint event */ + regs->pc -= pc_adj; + asm volatile ("MRC p15, 0, %0, c6, c0, 0":"=r"(dfar)); + thread_info.watch_addr = (void *)dfar; + thread_info.rw = (1UL << (((~*(uint32_t *)regs->pc) >> 20) & 1UL)); + thread_info.notify_type = GDB_NOTIFIY_WATCHPOINT; + ret = 2; + } + else { - rt_thread_suspend_witch_flag(thread_info.thread, RT_UNINTERRUPTIBLE); - rt_schedule(); + return 0; /* not debug dabt */ } - return ret; } + thread_info.thread = rt_thread_self(); + thread_info.thread->regs = regs; + msg.u.d = (void *)&thread_info; + rt_hw_dmb(); + thread_info.thread->debug_suspend = 1; + rt_hw_dsb(); + rt_thread_suspend_with_flag(thread_info.thread, RT_UNINTERRUPTIBLE); + rt_raw_channel_send(gdb_get_server_channel(), &msg); + rt_schedule(); + while (thread_info.thread->debug_suspend) + { + rt_thread_suspend_with_flag(thread_info.thread, RT_UNINTERRUPTIBLE); + rt_schedule(); + } + return ret; } return 0; } @@ -169,7 +172,7 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs) rt_kprintf("ttbr0:0x%08x\n", v); asm volatile ("MRC p15, 0, %0, c6, c0, 0":"=r"(v)); rt_kprintf("dfar:0x%08x\n", v); - rt_kprintf("0x%08x -> 0x%08x\n", v, rt_hw_mmu_v2p(&mmu_info, (void*)v)); + rt_kprintf("0x%08x -> 0x%08x\n", v, rt_hw_mmu_v2p(&mmu_info, (void *)v)); } #endif } @@ -196,18 +199,18 @@ void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) { /* thumb mode */ addr = regs->pc - 2; - ins = (uint32_t)*(uint16_t*)addr; + ins = (uint32_t)*(uint16_t *)addr; if ((ins & (3 << 11)) != 0) { /* 32 bit ins */ ins <<= 16; - ins += *(uint16_t*)(addr + 2); + ins += *(uint16_t *)(addr + 2); } } else { addr = regs->pc - 4; - ins = *(uint32_t*)addr; + ins = *(uint32_t *)addr; } if ((ins & 0xe00) == 0xa00) {