From e789a1f367b54f002f6970b1e031d8dec9aa461d Mon Sep 17 00:00:00 2001
From: shaojinchun <shaojinchun@rt-thread.com>
Date: Wed, 26 May 2021 09:11:45 +0800
Subject: [PATCH 1/2] add SIG_IGN support

---
 components/lwp/lwp_signal.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/components/lwp/lwp_signal.c b/components/lwp/lwp_signal.c
index 0ec1c6eb0e..33eb0d6a77 100644
--- a/components/lwp/lwp_signal.c
+++ b/components/lwp/lwp_signal.c
@@ -303,6 +303,11 @@ lwp_sighandler_t lwp_sighandler_get(int sig)
     }
 out:
     rt_hw_interrupt_enable(level);
+
+    if (func == (lwp_sighandler_t)SIG_IGN)
+    {
+        func = RT_NULL;
+    }
     return func;
 }
 
-- 
Gitee


From 94fab9654298b4732c049bd0cb207d9ef65df2e9 Mon Sep 17 00:00:00 2001
From: shaojinchun <shaojinchun@rt-thread.com>
Date: Wed, 26 May 2021 09:52:57 +0800
Subject: [PATCH 2/2] =?UTF-8?q?lwp=E6=A0=88=E6=89=A7=E8=A1=8C=E4=BB=A3?=
 =?UTF-8?q?=E7=A0=81=E7=94=9F=E6=88=90=E6=97=B6=E5=A2=9E=E5=8A=A0dc?=
 =?UTF-8?q?=E6=93=8D=E4=BD=9C?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 .../lwp/arch/aarch64/cortex-a/lwp_gcc.S       | 14 ++++++--
 components/lwp/arch/arm/cortex-a/lwp_gcc.S    | 33 ++++++++++++++++---
 2 files changed, 41 insertions(+), 6 deletions(-)

diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S b/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S
index e139652205..ccd3254255 100644
--- a/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S
+++ b/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S
@@ -123,8 +123,15 @@ set_user_context:
     str x1, [x2, #4]
     ldr x1, [x0, #8]
     str x1, [x2, #8]
+
+    mov x3, x2
+    dc cvau, x3
+    add x3, x3, #8
+    dc cvau, x3
+    dsb sy
     ic ialluis
     dsb sy
+
     msr sp_el0, x2
     ret
 /*
@@ -361,12 +368,15 @@ user_do_signal:
     str w1, [sp]
     ldr w1, [x0, #4]
     str w1, [sp, #4]
-    ic ialluis
-    dsb sy
 
     mov x9, sp /* lwp_sigreturn */
     mov x0, sp
 
+    dc cvau, x0
+    dsb sy
+    ic ialluis
+    dsb sy
+
     msr spsel, #1
 
     mrs x1, elr_el1
diff --git a/components/lwp/arch/arm/cortex-a/lwp_gcc.S b/components/lwp/arch/arm/cortex-a/lwp_gcc.S
index 2c0d78abc1..e1240ad1b3 100644
--- a/components/lwp/arch/arm/cortex-a/lwp_gcc.S
+++ b/components/lwp/arch/arm/cortex-a/lwp_gcc.S
@@ -56,10 +56,21 @@ set_user_context:
     str r1, [sp, #4]
     ldr r1, [r0, #8]
     str r1, [sp, #8]
-    mov lr, sp
-    mov r0, #0
+
+    mov r1, sp
+    mcr p15, 0, r1, c7, c11, 1   ;//dc cmvau
+    add r1, #4
+    mcr p15, 0, r1, c7, c11, 1   ;//dc cmvau
+    add r1, #4
+    mcr p15, 0, r1, c7, c11, 1   ;//dc cmvau
+    dsb
+    isb
     mcr p15, 0, r0, c7, c5, 0   ;//iciallu
     dsb
+    isb
+
+    mov lr, sp
+    mov r0, #0
     cps #Mode_SVC
     mov pc, lr
 
@@ -201,10 +212,17 @@ lwp_check_debug:
     str r1, [sp]
     ldr r1, [r0, #4]
     str r1, [sp, #4]
-    mov r0, #0
+
+    mov r1, sp
+    mcr p15, 0, r1, c7, c11, 1   ;//dc cmvau
+    add r1, #4
+    mcr p15, 0, r1, c7, c11, 1   ;//dc cmvau
+    dsb
+    isb
     mcr p15, 0, r0, c7, c5, 0   ;//iciallu
     dsb
     isb
+
     mov r0, sp /* lwp_debugreturn */
     cps #Mode_SVC
 
@@ -257,9 +275,16 @@ user_do_signal:
     str r1, [sp]
     ldr r1, [r0, #4]
     str r1, [sp, #4]
-    mov r0, #0
+
+    mov r1, sp
+    mcr p15, 0, r1, c7, c11, 1   ;//dc cmvau
+    add r1, #4
+    mcr p15, 0, r1, c7, c11, 1   ;//dc cmvau
+    dsb
+    isb
     mcr p15, 0, r0, c7, c5, 0   ;//iciallu
     dsb
+    isb
 
     mov r5, sp  ;//if func is 0
     mov lr, sp
-- 
Gitee