diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000000000000000000000000000000000000..1d5da22e0ba50c72dc3396995dbae42af131c90e --- /dev/null +++ b/.clang-format @@ -0,0 +1,428 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# clang-format configuration file. Intended for clang-format >= 4. +# +# For more information, see: +# +# Documentation/process/clang-format.rst +# https://clang.llvm.org/docs/ClangFormat.html +# https://clang.llvm.org/docs/ClangFormatStyleOptions.html +# +--- +AccessModifierOffset: -4 +AlignAfterOpenBracket: Align +AlignConsecutiveAssignments: false +AlignConsecutiveDeclarations: false +#AlignEscapedNewlines: Left # Unknown to clang-format-4.0 +AlignOperands: true +AlignTrailingComments: false +AllowAllParametersOfDeclarationOnNextLine: false +AllowShortBlocksOnASingleLine: false +AllowShortCaseLabelsOnASingleLine: false +AllowShortFunctionsOnASingleLine: None +AllowShortIfStatementsOnASingleLine: false +AllowShortLoopsOnASingleLine: false +AlwaysBreakAfterDefinitionReturnType: None +AlwaysBreakAfterReturnType: None +AlwaysBreakBeforeMultilineStrings: false +AlwaysBreakTemplateDeclarations: false +BinPackArguments: true +BinPackParameters: true +BraceWrapping: + AfterClass: false + AfterControlStatement: false + AfterEnum: false + AfterFunction: true + AfterNamespace: true + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + #AfterExternBlock: false # Unknown to clang-format-5.0 + BeforeCatch: false + BeforeElse: false + IndentBraces: false + #SplitEmptyFunction: true # Unknown to clang-format-4.0 + #SplitEmptyRecord: true # Unknown to clang-format-4.0 + #SplitEmptyNamespace: true # Unknown to clang-format-4.0 +BreakBeforeBinaryOperators: None +BreakBeforeBraces: Custom +#BreakBeforeInheritanceComma: false # Unknown to clang-format-4.0 +BreakBeforeTernaryOperators: false +BreakConstructorInitializersBeforeComma: false +#BreakConstructorInitializers: BeforeComma # Unknown to clang-format-4.0 +BreakAfterJavaFieldAnnotations: false +BreakStringLiterals: false +ColumnLimit: 80 +CommentPragmas: '^ IWYU pragma:' +#CompactNamespaces: false # Unknown to clang-format-4.0 +ConstructorInitializerAllOnOneLineOrOnePerLine: false +ConstructorInitializerIndentWidth: 8 +ContinuationIndentWidth: 8 +Cpp11BracedListStyle: false +DerivePointerAlignment: false +DisableFormat: false +ExperimentalAutoDetectBinPacking: false +#FixNamespaceComments: false # Unknown to clang-format-4.0 + +# Taken from: +# git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ \ +# | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$, - '\1'," \ +# | sort | uniq +ForEachMacros: + - 'apei_estatus_for_each_section' + - 'ata_for_each_dev' + - 'ata_for_each_link' + - 'ax25_for_each' + - 'ax25_uid_for_each' + - 'bio_for_each_integrity_vec' + - '__bio_for_each_segment' + - 'bio_for_each_segment' + - 'bio_for_each_segment_all' + - 'bio_list_for_each' + - 'bip_for_each_vec' + - 'blkg_for_each_descendant_post' + - 'blkg_for_each_descendant_pre' + - 'blk_queue_for_each_rl' + - 'bond_for_each_slave' + - 'bond_for_each_slave_rcu' + - 'btree_for_each_safe128' + - 'btree_for_each_safe32' + - 'btree_for_each_safe64' + - 'btree_for_each_safel' + - 'card_for_each_dev' + - 'cgroup_taskset_for_each' + - 'cgroup_taskset_for_each_leader' + - 'cpufreq_for_each_entry' + - 'cpufreq_for_each_entry_idx' + - 'cpufreq_for_each_valid_entry' + - 'cpufreq_for_each_valid_entry_idx' + - 'css_for_each_child' + - 'css_for_each_descendant_post' + - 'css_for_each_descendant_pre' + - 'device_for_each_child_node' + - 'drm_atomic_crtc_for_each_plane' + - 'drm_atomic_crtc_state_for_each_plane' + - 'drm_atomic_crtc_state_for_each_plane_state' + - 'drm_for_each_connector_iter' + - 'drm_for_each_crtc' + - 'drm_for_each_encoder' + - 'drm_for_each_encoder_mask' + - 'drm_for_each_fb' + - 'drm_for_each_legacy_plane' + - 'drm_for_each_plane' + - 'drm_for_each_plane_mask' + - 'drm_mm_for_each_hole' + - 'drm_mm_for_each_node' + - 'drm_mm_for_each_node_in_range' + - 'drm_mm_for_each_node_safe' + - 'for_each_active_drhd_unit' + - 'for_each_active_iommu' + - 'for_each_available_child_of_node' + - 'for_each_bio' + - 'for_each_board_func_rsrc' + - 'for_each_bvec' + - 'for_each_child_of_node' + - 'for_each_clear_bit' + - 'for_each_clear_bit_from' + - 'for_each_cmsghdr' + - 'for_each_compatible_node' + - 'for_each_console' + - 'for_each_cpu' + - 'for_each_cpu_and' + - 'for_each_cpu_not' + - 'for_each_cpu_wrap' + - 'for_each_dev_addr' + - 'for_each_dma_cap_mask' + - 'for_each_drhd_unit' + - 'for_each_dss_dev' + - 'for_each_efi_memory_desc' + - 'for_each_efi_memory_desc_in_map' + - 'for_each_endpoint_of_node' + - 'for_each_evictable_lru' + - 'for_each_fib6_node_rt_rcu' + - 'for_each_fib6_walker_rt' + - 'for_each_free_mem_range' + - 'for_each_free_mem_range_reverse' + - 'for_each_func_rsrc' + - 'for_each_hstate' + - 'for_each_if' + - 'for_each_iommu' + - 'for_each_ip_tunnel_rcu' + - 'for_each_irq_nr' + - 'for_each_lru' + - 'for_each_matching_node' + - 'for_each_matching_node_and_match' + - 'for_each_memblock' + - 'for_each_memblock_type' + - 'for_each_memcg_cache_index' + - 'for_each_mem_pfn_range' + - 'for_each_mem_range' + - 'for_each_mem_range_rev' + - 'for_each_migratetype_order' + - 'for_each_msi_entry' + - 'for_each_net' + - 'for_each_netdev' + - 'for_each_netdev_continue' + - 'for_each_netdev_continue_rcu' + - 'for_each_netdev_feature' + - 'for_each_netdev_in_bond_rcu' + - 'for_each_netdev_rcu' + - 'for_each_netdev_reverse' + - 'for_each_netdev_safe' + - 'for_each_net_rcu' + - 'for_each_new_connector_in_state' + - 'for_each_new_crtc_in_state' + - 'for_each_new_plane_in_state' + - 'for_each_new_private_obj_in_state' + - 'for_each_node' + - 'for_each_node_by_name' + - 'for_each_node_by_type' + - 'for_each_node_mask' + - 'for_each_node_state' + - 'for_each_node_with_cpus' + - 'for_each_node_with_property' + - 'for_each_of_allnodes' + - 'for_each_of_allnodes_from' + - 'for_each_of_pci_range' + - 'for_each_old_connector_in_state' + - 'for_each_old_crtc_in_state' + - 'for_each_oldnew_connector_in_state' + - 'for_each_oldnew_crtc_in_state' + - 'for_each_oldnew_plane_in_state' + - 'for_each_oldnew_private_obj_in_state' + - 'for_each_old_plane_in_state' + - 'for_each_old_private_obj_in_state' + - 'for_each_online_cpu' + - 'for_each_online_node' + - 'for_each_online_pgdat' + - 'for_each_pci_bridge' + - 'for_each_pci_dev' + - 'for_each_pci_msi_entry' + - 'for_each_populated_zone' + - 'for_each_possible_cpu' + - 'for_each_present_cpu' + - 'for_each_prime_number' + - 'for_each_prime_number_from' + - 'for_each_process' + - 'for_each_process_thread' + - 'for_each_property_of_node' + - 'for_each_reserved_mem_region' + - 'for_each_resv_unavail_range' + - 'for_each_rtdcom' + - 'for_each_rtdcom_safe' + - 'for_each_set_bit' + - 'for_each_set_bit_from' + - 'for_each_sg' + - 'for_each_sg_page' + - '__for_each_thread' + - 'for_each_thread' + - 'for_each_zone' + - 'for_each_zone_zonelist' + - 'for_each_zone_zonelist_nodemask' + - 'fwnode_for_each_available_child_node' + - 'fwnode_for_each_child_node' + - 'fwnode_graph_for_each_endpoint' + - 'gadget_for_each_ep' + - 'hash_for_each' + - 'hash_for_each_possible' + - 'hash_for_each_possible_rcu' + - 'hash_for_each_possible_rcu_notrace' + - 'hash_for_each_possible_safe' + - 'hash_for_each_rcu' + - 'hash_for_each_safe' + - 'hctx_for_each_ctx' + - 'hlist_bl_for_each_entry' + - 'hlist_bl_for_each_entry_rcu' + - 'hlist_bl_for_each_entry_safe' + - 'hlist_for_each' + - 'hlist_for_each_entry' + - 'hlist_for_each_entry_continue' + - 'hlist_for_each_entry_continue_rcu' + - 'hlist_for_each_entry_continue_rcu_bh' + - 'hlist_for_each_entry_from' + - 'hlist_for_each_entry_from_rcu' + - 'hlist_for_each_entry_rcu' + - 'hlist_for_each_entry_rcu_bh' + - 'hlist_for_each_entry_rcu_notrace' + - 'hlist_for_each_entry_safe' + - '__hlist_for_each_rcu' + - 'hlist_for_each_safe' + - 'hlist_nulls_for_each_entry' + - 'hlist_nulls_for_each_entry_from' + - 'hlist_nulls_for_each_entry_rcu' + - 'hlist_nulls_for_each_entry_safe' + - 'ide_host_for_each_port' + - 'ide_port_for_each_dev' + - 'ide_port_for_each_present_dev' + - 'idr_for_each_entry' + - 'idr_for_each_entry_continue' + - 'idr_for_each_entry_ul' + - 'inet_bind_bucket_for_each' + - 'inet_lhash2_for_each_icsk_rcu' + - 'iov_for_each' + - 'key_for_each' + - 'key_for_each_safe' + - 'klp_for_each_func' + - 'klp_for_each_object' + - 'kvm_for_each_memslot' + - 'kvm_for_each_vcpu' + - 'list_for_each' + - 'list_for_each_entry' + - 'list_for_each_entry_continue' + - 'list_for_each_entry_continue_rcu' + - 'list_for_each_entry_continue_reverse' + - 'list_for_each_entry_from' + - 'list_for_each_entry_from_reverse' + - 'list_for_each_entry_lockless' + - 'list_for_each_entry_rcu' + - 'list_for_each_entry_reverse' + - 'list_for_each_entry_safe' + - 'list_for_each_entry_safe_continue' + - 'list_for_each_entry_safe_from' + - 'list_for_each_entry_safe_reverse' + - 'list_for_each_prev' + - 'list_for_each_prev_safe' + - 'list_for_each_safe' + - 'llist_for_each' + - 'llist_for_each_entry' + - 'llist_for_each_entry_safe' + - 'llist_for_each_safe' + - 'media_device_for_each_entity' + - 'media_device_for_each_intf' + - 'media_device_for_each_link' + - 'media_device_for_each_pad' + - 'netdev_for_each_lower_dev' + - 'netdev_for_each_lower_private' + - 'netdev_for_each_lower_private_rcu' + - 'netdev_for_each_mc_addr' + - 'netdev_for_each_uc_addr' + - 'netdev_for_each_upper_dev_rcu' + - 'netdev_hw_addr_list_for_each' + - 'nft_rule_for_each_expr' + - 'nla_for_each_attr' + - 'nla_for_each_nested' + - 'nlmsg_for_each_attr' + - 'nlmsg_for_each_msg' + - 'nr_neigh_for_each' + - 'nr_neigh_for_each_safe' + - 'nr_node_for_each' + - 'nr_node_for_each_safe' + - 'of_for_each_phandle' + - 'of_property_for_each_string' + - 'of_property_for_each_u32' + - 'pci_bus_for_each_resource' + - 'ping_portaddr_for_each_entry' + - 'plist_for_each' + - 'plist_for_each_continue' + - 'plist_for_each_entry' + - 'plist_for_each_entry_continue' + - 'plist_for_each_entry_safe' + - 'plist_for_each_safe' + - 'pnp_for_each_card' + - 'pnp_for_each_dev' + - 'protocol_for_each_card' + - 'protocol_for_each_dev' + - 'queue_for_each_hw_ctx' + - 'radix_tree_for_each_contig' + - 'radix_tree_for_each_slot' + - 'radix_tree_for_each_tagged' + - 'rbtree_postorder_for_each_entry_safe' + - 'resource_list_for_each_entry' + - 'resource_list_for_each_entry_safe' + - 'rhl_for_each_entry_rcu' + - 'rhl_for_each_rcu' + - 'rht_for_each' + - 'rht_for_each_continue' + - 'rht_for_each_entry' + - 'rht_for_each_entry_continue' + - 'rht_for_each_entry_rcu' + - 'rht_for_each_entry_rcu_continue' + - 'rht_for_each_entry_safe' + - 'rht_for_each_rcu' + - 'rht_for_each_rcu_continue' + - '__rq_for_each_bio' + - 'rq_for_each_segment' + - 'scsi_for_each_prot_sg' + - 'scsi_for_each_sg' + - 'sctp_for_each_hentry' + - 'sctp_skb_for_each' + - 'shdma_for_each_chan' + - '__shost_for_each_device' + - 'shost_for_each_device' + - 'sk_for_each' + - 'sk_for_each_bound' + - 'sk_for_each_entry_offset_rcu' + - 'sk_for_each_from' + - 'sk_for_each_rcu' + - 'sk_for_each_safe' + - 'sk_nulls_for_each' + - 'sk_nulls_for_each_from' + - 'sk_nulls_for_each_rcu' + - 'snd_pcm_group_for_each_entry' + - 'snd_soc_dapm_widget_for_each_path' + - 'snd_soc_dapm_widget_for_each_path_safe' + - 'snd_soc_dapm_widget_for_each_sink_path' + - 'snd_soc_dapm_widget_for_each_source_path' + - 'tb_property_for_each' + - 'udp_portaddr_for_each_entry' + - 'udp_portaddr_for_each_entry_rcu' + - 'usb_hub_for_each_child' + - 'v4l2_device_for_each_subdev' + - 'v4l2_m2m_for_each_dst_buf' + - 'v4l2_m2m_for_each_dst_buf_safe' + - 'v4l2_m2m_for_each_src_buf' + - 'v4l2_m2m_for_each_src_buf_safe' + - 'zorro_for_each_dev' + +#IncludeBlocks: Preserve # Unknown to clang-format-5.0 +IncludeCategories: + - Regex: '.*' + Priority: 1 +IncludeIsMainRegex: '(Test)?$' +IndentCaseLabels: false +#IndentPPDirectives: None # Unknown to clang-format-5.0 +IndentWidth: 8 +IndentWrappedFunctionNames: false +JavaScriptQuotes: Leave +JavaScriptWrapImports: true +KeepEmptyLinesAtTheStartOfBlocks: false +MacroBlockBegin: '' +MacroBlockEnd: '' +MaxEmptyLinesToKeep: 1 +NamespaceIndentation: Inner +#ObjCBinPackProtocolList: Auto # Unknown to clang-format-5.0 +ObjCBlockIndentWidth: 8 +ObjCSpaceAfterProperty: true +ObjCSpaceBeforeProtocolList: true + +# Taken from git's rules +#PenaltyBreakAssignment: 10 # Unknown to clang-format-4.0 +PenaltyBreakBeforeFirstCallParameter: 30 +PenaltyBreakComment: 10 +PenaltyBreakFirstLessLess: 0 +PenaltyBreakString: 10 +PenaltyExcessCharacter: 100 +PenaltyReturnTypeOnItsOwnLine: 60 + +PointerAlignment: Right +ReflowComments: false +SortIncludes: false +#SortUsingDeclarations: false # Unknown to clang-format-4.0 +SpaceAfterCStyleCast: false +SpaceAfterTemplateKeyword: true +SpaceBeforeAssignmentOperators: true +#SpaceBeforeCtorInitializerColon: true # Unknown to clang-format-5.0 +#SpaceBeforeInheritanceColon: true # Unknown to clang-format-5.0 +SpaceBeforeParens: ControlStatements +#SpaceBeforeRangeBasedForLoopColon: true # Unknown to clang-format-5.0 +SpaceInEmptyParentheses: false +SpacesBeforeTrailingComments: 1 +SpacesInAngles: false +SpacesInContainerLiterals: false +SpacesInCStyleCastParentheses: false +SpacesInParentheses: false +SpacesInSquareBrackets: false +Standard: Cpp03 +TabWidth: 8 +UseTab: Always +... diff --git a/.cocciconfig b/.cocciconfig new file mode 100644 index 0000000000000000000000000000000000000000..43967c6b20151ee126db08e24758e3c789bcb844 --- /dev/null +++ b/.cocciconfig @@ -0,0 +1,3 @@ +[spatch] + options = --timeout 200 + options = --use-gitgrep diff --git a/.get_maintainer.ignore b/.get_maintainer.ignore new file mode 100644 index 0000000000000000000000000000000000000000..cca6d870f7a57499ffd8be4b3abacaf9fccde9c1 --- /dev/null +++ b/.get_maintainer.ignore @@ -0,0 +1 @@ +Christoph Hellwig diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000000000000000000000000000000000000..89c411b5ce6bb081976d7efb48c2158bb4b2bb86 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,2 @@ +*.c diff=cpp +*.h diff=cpp diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..7f4c5a5ef92dccb5d5e2e21070bf690fb2e2f32f --- /dev/null +++ b/.gitignore @@ -0,0 +1,138 @@ +# +# NOTE! Don't add files that are generated in specific +# subdirectories here. Add them in the ".gitignore" file +# in that subdirectory instead. +# +# NOTE! Please use 'git ls-files -i --exclude-standard' +# command after changing this file, to see if there are +# any tracked files which get ignored after the change. +# +# Normal rules (sorted alphabetically) +# +.* +*.a +*.asn1.[ch] +*.bin +*.bz2 +*.c.[012]*.* +*.dtb +*.dtbo +*.dtb.S +*.dwo +*.elf +*.gcno +*.gz +*.i +*.ko +*.lex.c +*.ll +*.lst +*.lz4 +*.lzma +*.lzo +*.mod.c +*.o +*.o.* +*.order +*.patch +*.s +*.so +*.so.dbg +*.su +*.symtypes +*.tab.[ch] +*.tar +*.xz +Module.symvers +modules.builtin + +# +# Top-level generic files +# +/tags +/TAGS +/linux +/vmlinux +/vmlinux.32 +/vmlinux-gdb.py +/vmlinuz +/System.map +/Module.markers + +# +# RPM spec file (make rpm-pkg) +# +/*.spec + +# +# Debian directory (make deb-pkg) +# +/debian/ + +# +# Snap directory (make snap-pkg) +# +/snap/ + +# +# tar directory (make tar*-pkg) +# +/tar-install/ + +# +# git files that we don't want to ignore even if they are dot-files +# +!.gitignore +!.mailmap +!.cocciconfig +!.clang-format + +# +# Generated include files +# +include/config +include/generated +include/ksym +arch/*/include/generated + +# stgit generated dirs +patches-* + +# quilt's files +patches +series + +# cscope files +cscope.* +ncscope.* + +# gnu global files +GPATH +GRTAGS +GSYMS +GTAGS + +# id-utils files +ID + +*.orig +*~ +\#*# + +# +# Leavings from module signing +# +extra_certificates +signing_key.pem +signing_key.priv +signing_key.x509 +x509.genkey + +# Kconfig presets +all.config + +# Kdevelop4 +*.kdev4 + +# Clang's compilation database file +/compile_commands.json diff --git a/.mailmap b/.mailmap new file mode 100644 index 0000000000000000000000000000000000000000..285e09645b31485d7bc314fb1fa7d055ec50fb46 --- /dev/null +++ b/.mailmap @@ -0,0 +1,208 @@ +# +# This list is used by git-shortlog to fix a few botched name translations +# in the git archive, either because the author's full name was messed up +# and/or not always written the same way, making contributions from the +# same person appearing not to be so or badly displayed. +# +# repo-abbrev: /pub/scm/linux/kernel/git/ +# + +Aaron Durbin +Adam Oldham +Adam Radford +Adrian Bunk +Adriana Reus +Alan Cox +Alan Cox +Aleksey Gorelov +Aleksandar Markovic +Al Viro +Al Viro +Andi Shyti +Andreas Herrmann +Andrey Ryabinin +Andrew Morton +Andrew Vasquez +Andy Adamson +Antoine Tenart +Antonio Ospite +Archit Taneja +Arnaud Patard +Arnd Bergmann +Axel Dyks +Axel Lin +Bart Van Assche +Bart Van Assche +Ben Gardner +Ben M Cahill +Björn Steinbrink +Boris Brezillon +Boris Brezillon +Boris Brezillon +Brian Avery +Brian King +Christoph Hellwig +Christophe Ricard +Corey Minyard +Damian Hobson-Garcia +David Brownell +David Woodhouse +Deng-Cheng Zhu +Dmitry Eremin-Solenikov +Domen Puncer +Douglas Gilbert +Ed L. Cashin +Evgeniy Polyakov +Felipe W Damasio +Felix Kuhling +Felix Moeller +Filipe Lautert +Franck Bui-Huu +Frank Rowand +Frank Rowand +Frank Rowand +Frank Zago +Greg Kroah-Hartman +Greg Kroah-Hartman +Greg Kroah-Hartman +Gregory CLEMENT +Henk Vergonet +Henrik Kretzschmar +Henrik Rydberg +Herbert Xu +Jacob Shin +James Bottomley +James Bottomley +James E Wilson +James Hogan +James Hogan +James Ketrenos +Jason Gunthorpe +Jason Gunthorpe +Javi Merino + +Jean Tourrilhes +Jeff Garzik +Jeff Layton +Jeff Layton +Jeff Layton +Jens Axboe +Jens Osterkamp +Johan Hovold +Johan Hovold +John Paul Adrian Glaubitz +John Stultz + + + + + +Juha Yrjola +Juha Yrjola +Juha Yrjola +Kay Sievers +Kenneth W Chen +Konstantin Khlebnikov +Koushik +Krzysztof Kozlowski +Krzysztof Kozlowski +Kuninori Morimoto +Leon Romanovsky +Leon Romanovsky +Leonid I Ananiev +Linas Vepstas +Linus Lüssing +Linus Lüssing +Maciej W. Rozycki +Marcin Nowakowski +Mark Brown +Mark Yao +Martin Kepplinger +Martin Kepplinger +Matthieu CASTET +Mauro Carvalho Chehab +Mauro Carvalho Chehab +Mauro Carvalho Chehab +Mauro Carvalho Chehab +Mauro Carvalho Chehab +Mauro Carvalho Chehab +Mauro Carvalho Chehab +Matt Ranostay Matthew Ranostay +Matt Ranostay +Matt Ranostay +Matt Redfearn +Mayuresh Janorkar +Michael Buesch +Michel Dänzer +Miodrag Dinic +Miquel Raynal +Mitesh shah +Mohit Kumar +Morten Welinder +Morten Welinder +Morten Welinder +Morten Welinder +Mythri P K +Nguyen Anh Quynh +Paolo 'Blaisorblade' Giarrusso +Patrick Mochel +Paul Burton +Peter A Jonsson +Peter Oruba +Peter Oruba +Pratyush Anand +Praveen BP +Qais Yousef +Rajesh Shah +Ralf Baechle +Ralf Wildenhues +Randy Dunlap +Rémi Denis-Courmont +Ricardo Ribalda Delgado +Ross Zwisler +Rudolf Marek +Rui Saraiva +Sachin P Sant +Sarangdhar Joshi +Sam Ravnborg +Santosh Shilimkar +Santosh Shilimkar +Sascha Hauer +S.Çağlar Onur +Sebastian Reichel +Sebastian Reichel +Shiraz Hashim +Shuah Khan +Shuah Khan +Shuah Khan +Shuah Khan +Simon Kelley +Stéphane Witzmann +Stephen Hemminger +Subash Abhinov Kasiviswanathan +Subhash Jadavani +Sudeep Holla Sudeep KarkadaNagesha +Sumit Semwal +Tejun Heo +Thomas Graf +Thomas Pedersen +Tony Luck +Tsuneo Yoshioka +Uwe Kleine-König +Uwe Kleine-König +Uwe Kleine-König +Valdis Kletnieks +Vinod Koul +Vinod Koul +Vinod Koul +Viresh Kumar +Viresh Kumar +Viresh Kumar +Vlad Dogaru +Vladimir Davydov +Vladimir Davydov +Takashi YOSHII +Yakir Yang +Yusuke Goda +Gustavo Padovan +Gustavo Padovan diff --git a/Documentation/devicetree/bindings/sound/phytium,hda.yaml b/Documentation/devicetree/bindings/sound/phytium,hda.yaml new file mode 100644 index 0000000000000000000000000000000000000000..7aa5371127d67ca599f0ea9da8ebb3ac8f4d1841 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/phytium,hda.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/phytium,hda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Phytium HDA Controller + +maintainers: + - Dai Jingtao + +properties: + compatible: + enum: + - phytium,hda + + + reg: + items: + - description: HDA registers + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + + clock-names: + items: + - const: phytium_hda_clk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + + +examples: + - | + hda@28002000 { + compatible = "phytium,hda"; + reg = <0x0 0x28002000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_48mhz>; + clock-names = "phytium_hda_clk"; + }; diff --git a/Documentation/devicetree/configfs-overlays.txt b/Documentation/devicetree/configfs-overlays.txt new file mode 100644 index 0000000000000000000000000000000000000000..5fa43e0643072c7963daddc18cec7772910378ad --- /dev/null +++ b/Documentation/devicetree/configfs-overlays.txt @@ -0,0 +1,31 @@ +Howto use the configfs overlay interface. + +A device-tree configfs entry is created in /config/device-tree/overlays +and and it is manipulated using standard file system I/O. +Note that this is a debug level interface, for use by developers and +not necessarily something accessed by normal users due to the +security implications of having direct access to the kernel's device tree. + +* To create an overlay you mkdir the directory: + + # mkdir /config/device-tree/overlays/foo + +* Either you echo the overlay firmware file to the path property file. + + # echo foo.dtbo >/config/device-tree/overlays/foo/path + +* Or you cat the contents of the overlay to the dtbo file + + # cat foo.dtbo >/config/device-tree/overlays/foo/dtbo + +The overlay file will be applied, and devices will be created/destroyed +as required. + +To remove it simply rmdir the directory. + + # rmdir /config/device-tree/overlays/foo + +The rationalle of the dual interface (firmware & direct copy) is that each is +better suited to different use patterns. The firmware interface is what's +intended to be used by hardware managers in the kernel, while the copy interface +make sense for developers (since it avoids problems with namespaces). diff --git a/Makefile b/Makefile index a144a7117a1bd7916e5320349994069400d64df2..d5a4b9942082193373b81835ef4de90ca1be7f78 100644 --- a/Makefile +++ b/Makefile @@ -1593,7 +1593,7 @@ clean: $(clean-dirs) $(call cmd,rmfiles) @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \ \( -name '*.[aios]' -o -name '*.ko' -o -name '.*.cmd' \ - -o -name '*.ko.*' -o -name '*.dtb' -o -name '*.dtb.S' \ + -o -name '*.ko.*' -o -name '*.dtb' -o -name '*.dtbo' -o -name '*.dtb.S' \ -o -name '*.dwo' -o -name '*.lst' \ -o -name '*.su' \ -o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \ diff --git a/README.md b/README.md index 9847768e9295942e37488e0e66f632a0f4381287..fe94b83cbda80ce4e37edc54257c4f2e47679b56 100644 --- a/README.md +++ b/README.md @@ -1,22 +1,12 @@ # linux-kernel-xenomai ## 1 项目简介 -Xenomai在Phytium CPU配套的开发板上配套的Linux kernel。
-本开源仓库的内核代码只支持Phytium E2000Q。对于FT2000/4和D2000，其内核源代码还没有开源，需要联系飞腾软件生态部获取内核源码。
+Xenomai在Phytium CPU配套的开发板上配套的Linux kernel，推荐使用Linux kernel 5.10.153-dovetail3和Xenomai v3.2.2。
+本开源仓库的内核代码支持E2000Q，飞腾派等飞腾CPU。
## 2 安装和使用教程 -### 2.1 Xenomai配套Linux kernel 4.19.209-cip59的用户手册和源代码获取路径 -Xenomai用户手册名称为xenomai_user_manual-v2.x.x.pdf，获取方法如下:
-https://gitee.com/phytium_embedded/phytium-embedded-docs/tree/master/xenomai
- -Linux kernel源代码链接如下:
-https://gitee.com/phytium_embedded/linux-kernel-xenomai/tree/4.19.209-cip59
- -Xenomai版本是3.1.3，源代码链接如下:
-https://source.denx.de/Xenomai/xenomai/-/tree/v3.1.3
- -### 2.2 Xenomai配套Linux kernel 5.10.153-dovetail3的用户手册和源代码获取路径 +### 2.1 Xenomai配套Linux kernel 5.10.153-dovetail3的用户手册和源代码获取路径 Xenomai用户手册名称为xenomai_user_manual-v3.x.x.pdf，获取方法如下:
-https://gitee.com/phytium_embedded/phytium-embedded-docs/tree/master/xenomai
+https://gitee.com/phytium_embedded/phytium-embedded-docs/tree/master/linux/xenomai
Linux kernel源代码链接如下:
https://gitee.com/phytium_embedded/linux-kernel-xenomai
@@ -24,6 +14,16 @@ https://gitee.com/phytium_embedded/linux-kernel-xenomai
Xenomai版本是3.2.2，源代码链接如下:
https://source.denx.de/Xenomai/xenomai/-/tree/v3.2.2
+### 2.2 Xenomai配套Linux kernel 4.19.209-cip59的用户手册和源代码获取路径 +Xenomai用户手册名称为xenomai_user_manual-v2.x.x.pdf，获取方法如下:
+https://gitee.com/phytium_embedded/phytium-embedded-docs/tree/master/linux/xenomai
+ +Linux kernel源代码链接如下:
+https://gitee.com/phytium_embedded/linux-kernel-xenomai/tree/4.19.209-cip59
+ +Xenomai版本是3.1.3，源代码链接如下:
+https://source.denx.de/Xenomai/xenomai/-/tree/v3.1.3
+ ## 3 贡献人员 该项目的开发成员列表如下：
diff --git a/arch/arm64/boot/dts/phytium/Makefile b/arch/arm64/boot/dts/phytium/Makefile index 9c9c63b7b81abaeb8b37204263ebaed7cd6cee9c..40913b143762ec0bda344d7bdcadfb12d1e34677 100644 --- a/arch/arm64/boot/dts/phytium/Makefile +++ b/arch/arm64/boot/dts/phytium/Makefile @@ -11,3 +11,6 @@ dtb-$(CONFIG_ARCH_PHYTIUM) += e2000d-power-board.dtb dtb-$(CONFIG_ARCH_PHYTIUM) += e2000q-hanwei-board.dtb dtb-$(CONFIG_ARCH_PHYTIUM) += phytiumpi_firefly.dtb dtb-$(CONFIG_ARCH_PHYTIUM) += e2000d-chillipi-edu-board.dtb + +#Enable support for device-tree overlay +DTC_FLAGS += -@ diff --git a/arch/arm64/boot/dts/phytium/e2000d-chillipi-edu-board.dts b/arch/arm64/boot/dts/phytium/e2000d-chillipi-edu-board.dts index 28a1f0d47b743be27b687646b032a7e528623ee9..0ab55a50ffd179c72884e3dbce2ae0505d99d492 100644 --- a/arch/arm64/boot/dts/phytium/e2000d-chillipi-edu-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000d-chillipi-edu-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2202 chillipi education board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm64/boot/dts/phytium/e2000d-demo-board.dts b/arch/arm64/boot/dts/phytium/e2000d-demo-board.dts index cde22bf16111cd431569522b71dc609dbc78ba3a..067f658054e71ce7babb640f3e2cb7809f6933a1 100644 --- a/arch/arm64/boot/dts/phytium/e2000d-demo-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000d-demo-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2202 demo board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/phytium/e2000d-miniitx-board.dts b/arch/arm64/boot/dts/phytium/e2000d-miniitx-board.dts index 1760a910d8dcac0e8cd0a41b15bbf295af0ae6a0..9250d63b924ee23e7614402d155cc3a28c77e03f 100644 --- a/arch/arm64/boot/dts/phytium/e2000d-miniitx-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000d-miniitx-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2202 miniitx board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * Hongmin Qi */ diff --git a/arch/arm64/boot/dts/phytium/e2000d-power-board.dts b/arch/arm64/boot/dts/phytium/e2000d-power-board.dts index 099dace5410f3d569568ad4e391765fae326afa4..99656b8568369d64aaf7f1d18e65bc5a135bf807 100755 --- a/arch/arm64/boot/dts/phytium/e2000d-power-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000d-power-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2202 power board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * Hongmin Qi */ diff --git a/arch/arm64/boot/dts/phytium/e2000q-come-board.dts b/arch/arm64/boot/dts/phytium/e2000q-come-board.dts index 3d803602f8aabcc494155032162fb0b1d0357a74..03d93de63abe3139b4df0ccd2723416b10c6be82 100755 --- a/arch/arm64/boot/dts/phytium/e2000q-come-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000q-come-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2204 come board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * Hongmin Qi */ @@ -258,3 +258,6 @@ &pwm1 { status = "okay"; }; +&vpu0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/phytium/e2000q-demo-board.dts b/arch/arm64/boot/dts/phytium/e2000q-demo-board.dts index 52385239c530b5af47531f7a93a2a676e950211e..873b9cc2771ec7f8f44a440cd6215e858283bc50 100644 --- a/arch/arm64/boot/dts/phytium/e2000q-demo-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000q-demo-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2204 demo board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. */ /dts-v1/; @@ -239,3 +239,7 @@ &pmdk_dp { &rng0 { status = "okay"; }; + +&vpu0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/phytium/e2000q-edu-board.dts b/arch/arm64/boot/dts/phytium/e2000q-edu-board.dts index 27039933ac1459a672f3265cfb291ae23ee597b5..e9631df6b9bc21054b59879eaa224e6388d746c9 100755 --- a/arch/arm64/boot/dts/phytium/e2000q-edu-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000q-edu-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2204 edu board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * Hongmin Qi */ @@ -264,6 +264,10 @@ &dc0 { edp_mask = [00]; }; +&vpu0 { + status = "okay"; +}; + &i2s0 { #sound-dai-cells = <0>; dai-name = "phytium-i2s-lsd"; diff --git a/arch/arm64/boot/dts/phytium/e2000q-hanwei-board.dts b/arch/arm64/boot/dts/phytium/e2000q-hanwei-board.dts index e5902d612d2cfbaecc50285796c8de10b2219fa4..d1fc912ee2d22549b26eddff0452d415355df6cd 100755 --- a/arch/arm64/boot/dts/phytium/e2000q-hanwei-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000q-hanwei-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2204 hanwei board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * Hongmin Qi */ @@ -208,3 +208,6 @@ &gpio5 { status = "okay"; }; +&vpu0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/phytium/e2000q-miniitx-board.dts b/arch/arm64/boot/dts/phytium/e2000q-miniitx-board.dts index 4ef260940fd22cc03d07eb7008a102d3758a42a9..3f0487291bf169283e1258c3732dc03ec10a75a4 100644 --- a/arch/arm64/boot/dts/phytium/e2000q-miniitx-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000q-miniitx-board.dts @@ -2,14 +2,13 @@ /* * DTS file for Phytium miniITX-Pe2204 development board. * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * Shaojun Yang */ /dts-v1/; /memreserve/ 0x80000000 0x10000; -/memreserve/ 0xf4000000 0x4000000; #include "pe2204.dtsi" @@ -33,17 +32,30 @@ memory@00{ reg = <0x0 0x80000000 0x2 0x00000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + display_reserved: share@f4000000 { + no-map; + reg = <0x00 0xf4000000 0x0 0x4000000>; + }; + }; + sound_card: sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "phytium,pe220x-i2s-audio"; - simple-audio-card,cpu { - sound-dai = <&i2s0>; - }; - simple-audio-card,codec{ - sound-dai = <&codec0>; - }; - }; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "phytium,pe220x-i2s-audio"; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + simple-audio-card,codec{ + sound-dai = <&codec0>; + }; + }; }; &soc { @@ -63,22 +75,22 @@ rtc@68 { }; mio14: i2c@28030000 { - compatible = "phytium,i2c"; - reg = <0x0 0x28030000 0x0 0x1000>; - interrupts = ; - clocks = <&sysclk_50mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - codec0: es8336@10 { - det-gpios = <&gpio2 5 0>; - sel-gpios = <&gpio2 6 0>; - #sound-dai-cells = <0>; - compatible = "everest,es8336"; - reg = <0x10>; - mic-src = [20]; - }; + compatible = "phytium,i2c"; + reg = <0x0 0x28030000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + codec0: es8336@10 { + det-gpios = <&gpio2 5 0>; + sel-gpios = <&gpio2 6 0>; + #sound-dai-cells = <0>; + compatible = "everest,es8336"; + reg = <0x10>; + mic-src = [20]; + }; }; @@ -129,27 +141,27 @@ mio15: uart@28032000 { }; &gpio0 { - status = "okay"; + status = "okay"; }; &gpio1 { - status = "okay"; + status = "okay"; }; &gpio2 { - status = "okay"; + status = "okay"; }; &gpio3 { - status = "okay"; + status = "okay"; }; &gpio4 { - status = "okay"; + status = "okay"; }; &gpio5 { - status = "okay"; + status = "okay"; }; &watchdog0 { @@ -214,10 +226,9 @@ &macb2 { }; &dc0 { - reg = <0x0 0x32000000 0x0 0x8000>, - <0x0 0xf4000000 0x0 0x4000000>; // (optional) - pipe_mask = [03]; - edp_mask = [00]; + memory-region = <&display_reserved>; + pipe_mask = /bits/ 8 <0x3>; + edp_mask = /bits/ 8 <0x0>; status = "okay"; }; @@ -322,3 +333,6 @@ &rng0 { status = "okay"; }; +&vpu0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/phytium/e2000q-vpx-board.dts b/arch/arm64/boot/dts/phytium/e2000q-vpx-board.dts index c2c0b9e711907c4609d690062013b3d70788e9fa..f934dddbc754e7274cdbd4d04eff58d7ed8fb199 100755 --- a/arch/arm64/boot/dts/phytium/e2000q-vpx-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000q-vpx-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2204 vpx board. * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * Tianyu Liu */ @@ -315,3 +315,6 @@ &rng0 { status = "okay"; }; +&vpu0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/phytium/e2000s-demo-board.dts b/arch/arm64/boot/dts/phytium/e2000s-demo-board.dts index ebaec1a5911c20bab18b88a270adccce7545102d..192910a33c9a5e68801d97bf91c329454ed237ce 100644 --- a/arch/arm64/boot/dts/phytium/e2000s-demo-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000s-demo-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2201 demo board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/phytium/pe2201.dtsi b/arch/arm64/boot/dts/phytium/pe2201.dtsi index 29d46a1b2d6bff88448ecc5ff730152713f54477..eb24c34d0619f2dfaafd0a095500b921357ed27d 100644 --- a/arch/arm64/boot/dts/phytium/pe2201.dtsi +++ b/arch/arm64/boot/dts/phytium/pe2201.dtsi @@ -2,7 +2,7 @@ /* * dts file for Phytium Pe2201 SoC * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. */ #include "pe220x.dtsi" diff --git a/arch/arm64/boot/dts/phytium/pe2202.dtsi b/arch/arm64/boot/dts/phytium/pe2202.dtsi index c61a5cbbdcba6245fd6794c5ff0e6f69a24d711d..691bc065a4823a94789c6180100349512801d9f9 100644 --- a/arch/arm64/boot/dts/phytium/pe2202.dtsi +++ b/arch/arm64/boot/dts/phytium/pe2202.dtsi @@ -2,7 +2,7 @@ /* * dts file for Phytium Pe2202 SoC * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. */ #include "pe220x.dtsi" diff --git a/arch/arm64/boot/dts/phytium/pe2204.dtsi b/arch/arm64/boot/dts/phytium/pe2204.dtsi index 0d226430bd6b93073e2026e65f2f5cbacff84a12..88076d0c3300d55231a9fca34eaa4e4707a0d24c 100644 --- a/arch/arm64/boot/dts/phytium/pe2204.dtsi +++ b/arch/arm64/boot/dts/phytium/pe2204.dtsi @@ -2,7 +2,7 @@ /* * dts file for Phytium Pe2204 SoC * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. */ #include "pe220x.dtsi" @@ -209,4 +209,11 @@ macb3: ethernet@32012000 { status = "disabled"; }; + vpu0: vpu@32b00000 { + compatible = "phytium,vpu"; + reg = <0x0 0x32b00000 0x0 0x20000>; + interrupts = ; + status = "disabled"; + }; + }; diff --git a/arch/arm64/boot/dts/phytium/pe220x.dtsi b/arch/arm64/boot/dts/phytium/pe220x.dtsi index 39e19cafb3f4a6ca99c138f387059dd11d92f885..6cc44897f07df81099ed6681917c67648b37ea8b 100644 --- a/arch/arm64/boot/dts/phytium/pe220x.dtsi +++ b/arch/arm64/boot/dts/phytium/pe220x.dtsi @@ -2,7 +2,7 @@ /* * dts file for Phytium Pe220x SoC * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -164,15 +164,15 @@ sysclk_1200mhz: clk1200mhz { }; smmu: iommu@30000000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0x30000000 0x0 0x800000>; - interrupts = , - , - , - ; - interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; - dma-coherent; - #iommu-cells = <1>; + compatible = "arm,smmu-v3"; + reg = <0x0 0x30000000 0x0 0x800000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + dma-coherent; + #iommu-cells = <1>; }; soc: soc { diff --git a/arch/arm64/boot/dts/phytium/phytiumpi_firefly.dts b/arch/arm64/boot/dts/phytium/phytiumpi_firefly.dts index d935c7d9d2f70208c15107e7b6f489f651650055..6a1275dc4a0919535f1c7f01223d4affa5c64d4a 100644 --- a/arch/arm64/boot/dts/phytium/phytiumpi_firefly.dts +++ b/arch/arm64/boot/dts/phytium/phytiumpi_firefly.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pi development board. * - * Copyright (C) 2023, Phytium Technology Co., Ltd. + * Copyright (c) 2023-2024 Phytium Technology Co., Ltd. * * Shaojun Yang */ @@ -314,3 +314,7 @@ &pmdk_dp { &rng0 { status = "okay"; }; + +&vpu0 { + status = "okay"; +}; diff --git a/arch/arm64/configs/phytium_defconfig b/arch/arm64/configs/phytium_defconfig index 6b30baaaedfe8b7bc21f47e57e9cde530570cda1..8d481046d5be2ef71c3aea9115fe2009965f3f08 100644 --- a/arch/arm64/configs/phytium_defconfig +++ b/arch/arm64/configs/phytium_defconfig @@ -1,4 +1,4 @@ -CONFIG_LOCALVERSION="-phytium-embeded-v2.0" +CONFIG_LOCALVERSION="-phytium-embeded-v2.1" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -176,6 +176,7 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_PHYTIUM_PLAT=y CONFIG_MTD_SPI_NOR=y CONFIG_SPI_PHYTIUM_QUADSPI=y +CONFIG_OF_CONFIGFS=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y @@ -483,6 +484,8 @@ CONFIG_ARM_SMMU_V3=y CONFIG_REMOTEPROC=y CONFIG_HOMO_REMOTEPROC=y CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_EXTCON_USB_GPIO=y CONFIG_MEMORY=y CONFIG_IIO=y diff --git a/arch/arm64/configs/phytiumpi_firefly_defconfig b/arch/arm64/configs/phytiumpi_firefly_defconfig deleted file mode 100644 index 5a06d486eac9944fc835437104c44619d82f5e13..0000000000000000000000000000000000000000 --- a/arch/arm64/configs/phytiumpi_firefly_defconfig +++ /dev/null @@ -1,537 +0,0 @@ -CONFIG_LOCALVERSION="-phytium-embeded-2023-v1.0-GA" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_USELIB=y -CONFIG_AUDIT=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y -CONFIG_BLK_CGROUP=y -CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_HUGETLB=y -CONFIG_CPUSETS=y -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y -CONFIG_USER_NS=y -CONFIG_SCHED_AUTOGROUP=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y -CONFIG_ARCH_PHYTIUM=y -CONFIG_PCI=y -CONFIG_PCIEPORTBUS=y -CONFIG_HOTPLUG_PCI_PCIE=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_REALLOC_ENABLE_AUTO=y -CONFIG_PCI_IOV=y -CONFIG_HOTPLUG_PCI=y -CONFIG_HOTPLUG_PCI_ACPI=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCIE_PHYTIUM_EP=y -CONFIG_PCI_ENDPOINT=y -CONFIG_ARM64_VA_BITS_48=y -CONFIG_SCHED_MC=y -CONFIG_SECCOMP=y -CONFIG_KEXEC=y -CONFIG_CRASH_DUMP=y -CONFIG_XEN=y -CONFIG_COMPAT=y -CONFIG_HIBERNATION=y -CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_ARM_CPUIDLE=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPUFREQ_DT=y -CONFIG_ACPI_CPPC_CPUFREQ=y -CONFIG_ARM_BIG_LITTLE_CPUFREQ=y -CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_SCMI_CPUFREQ=y -CONFIG_ARM_SCMI_PROTOCOL=y -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_DMI_SYSFS=y -CONFIG_EFI_CAPSULE_LOADER=y -CONFIG_ACPI=y -CONFIG_ACPI_APEI=y -CONFIG_ACPI_APEI_GHES=y -CONFIG_ACPI_APEI_MEMORY_FAILURE=y -CONFIG_ACPI_APEI_EINJ=y -CONFIG_VIRTUALIZATION=y -CONFIG_KVM=y -CONFIG_ARM64_CRYPTO=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64_CE=m -CONFIG_CRYPTO_SHA3_ARM64=m -CONFIG_CRYPTO_SM3_ARM64_CE=m -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -CONFIG_CRYPTO_CRC32_ARM64_CE=m -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y -CONFIG_CRYPTO_CHACHA20_NEON=m -CONFIG_CRYPTO_AES_ARM64_BS=m -CONFIG_JUMP_LABEL=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_CMDLINE_PARTITION=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_KSM=y -CONFIG_MEMORY_FAILURE=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_CMA=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_MANGLE=m -CONFIG_BRIDGE=m -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y -CONFIG_BPF_JIT=y -CONFIG_CAN=y -CONFIG_CAN_RAW=m -CONFIG_CAN_BCM=m -CONFIG_CAN_GW=m -CONFIG_CAN_PHYTIUM=m -CONFIG_CAN_PHYTIUM_PLATFORM=m -CONFIG_BT=y -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_HIDP=m -# CONFIG_BT_HS is not set -CONFIG_BT_LEDS=y -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_3WIRE=y -CONFIG_CFG80211=y -CONFIG_CFG80211_WEXT=y -CONFIG_MAC80211=y -CONFIG_MAC80211_LEDS=y -CONFIG_RFKILL=y -CONFIG_NET_9P=m -CONFIG_NET_9P_VIRTIO=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_DMA_CMA=y -CONFIG_CMA_SIZE_MBYTES=32 -CONFIG_BRCMSTB_GISB_ARB=y -CONFIG_SIMPLE_PM_BUS=y -CONFIG_VEXPRESS_CONFIG=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_PHYTIUM_PLAT=y -CONFIG_MTD_SPI_NOR=y -CONFIG_SPI_PHYTIUM_QUADSPI=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_RAM=y -CONFIG_VIRTIO_BLK=y -CONFIG_BLK_DEV_NVME=y -CONFIG_NVME_MULTIPATH=y -CONFIG_NVME_FC=y -CONFIG_NVME_TARGET=y -CONFIG_NVME_TARGET_LOOP=y -CONFIG_NVME_TARGET_FC=y -CONFIG_NVME_TARGET_FCLOOP=y -CONFIG_SRAM=y -CONFIG_EEPROM_AT25=m -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -CONFIG_SCSI_SAS_LIBSAS=y -CONFIG_SCSI_SAS_ATA=y -CONFIG_SCSI_UFSHCD=m -CONFIG_SCSI_UFSHCD_PLATFORM=m -CONFIG_ATA=y -CONFIG_SATA_AHCI=y -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_AHCI_CEVA=y -CONFIG_AHCI_QORIQ=y -CONFIG_SATA_SIL24=y -CONFIG_PATA_PLATFORM=y -CONFIG_PATA_OF_PLATFORM=y -CONFIG_NETDEVICES=y -CONFIG_MACVLAN=m -CONFIG_MACVTAP=m -CONFIG_TUN=y -CONFIG_VETH=m -CONFIG_VIRTIO_NET=y -CONFIG_AMD_XGBE=y -CONFIG_ATL1C=m -CONFIG_MACB=y -CONFIG_THUNDER_NIC_PF=y -# CONFIG_NET_VENDOR_HISILICON is not set -# CONFIG_NET_VENDOR_HUAWEI is not set -CONFIG_E1000=m -CONFIG_E1000E=m -CONFIG_IGB=m -CONFIG_IGBVF=m -CONFIG_IXGB=m -CONFIG_IXGBE=m -CONFIG_IXGBEVF=m -CONFIG_I40E=m -CONFIG_I40EVF=m -CONFIG_MVMDIO=y -CONFIG_SKY2=y -# CONFIG_NET_VENDOR_NVIDIA is not set -# CONFIG_NET_VENDOR_QUALCOMM is not set -# CONFIG_NET_VENDOR_SAMSUNG is not set -CONFIG_STMMAC_ETH=m -# CONFIG_NET_VENDOR_SYNOPSYS is not set -# CONFIG_NET_VENDOR_TEHUTI is not set -# CONFIG_NET_VENDOR_TI is not set -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_AT803X_PHY=m -CONFIG_MARVELL_PHY=m -CONFIG_MARVELL_10G_PHY=m -CONFIG_MICREL_PHY=y -CONFIG_MOTORCOMM_PHY=y -CONFIG_REALTEK_PHY=m -CONFIG_PPP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=y -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_SR9800=m -CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_USB_NET_QMI_WWAN=y -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m -CONFIG_BRCMFMAC=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_PCIE=m -CONFIG_WL18XX=m -CONFIG_WLCORE_SDIO=m -CONFIG_RTL8821CS=m -CONFIG_INPUT_MATRIXKMAP=y -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_ADC=m -CONFIG_KEYBOARD_GPIO=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=m -CONFIG_INPUT_MISC=y -# CONFIG_SERIO_PHYTIUM_PS2 is not set -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIO_AMBAKMI=y -CONFIG_LEGACY_PTY_COUNT=16 -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_CAVIUM is not set -CONFIG_HW_RANDOM_PHYTIUM=y -CONFIG_TCG_TPM=y -CONFIG_TCG_TIS_I2C_INFINEON=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y -CONFIG_I2C_PHYTIUM_PLATFORM=y -CONFIG_I2C_SLAVE_EEPROM=y -CONFIG_SPI=y -CONFIG_SPI_PHYTIUM_PLAT=y -CONFIG_SPI_SPIDEV=y -CONFIG_SPMI=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_SINGLE=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -# CONFIG_GPIO_PHYTIUM_SGPIO is not set -CONFIG_POWER_AVS=y -CONFIG_POWER_RESET_BRCMSTB=y -CONFIG_POWER_RESET_VEXPRESS=y -CONFIG_POWER_RESET_XGENE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_SYSCON_REBOOT_MODE=y -CONFIG_BATTERY_SBS=m -CONFIG_BATTERY_BQ27XXX=y -CONFIG_SENSORS_ARM_SCMI=y -CONFIG_SENSORS_ARM_SCPI=y -CONFIG_SENSORS_PHYTIUM=y -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -CONFIG_CPU_THERMAL=y -CONFIG_THERMAL_EMULATION=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_SYSFS=y -CONFIG_ARM_SBSA_WATCHDOG=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_VCTRL=m -CONFIG_RC_CORE=m -CONFIG_RC_DECODERS=y -CONFIG_RC_DEVICES=y -CONFIG_MEDIA_SUPPORT=m -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -# CONFIG_DVB_NET is not set -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_VIDEO_PHYTIUM_JPEG=m -CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_DRM=y -CONFIG_DRM_RCAR_LVDS=m -CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_DRM_I2C_ADV7511=m -CONFIG_DRM_PHYTIUM=y -CONFIG_FB_ARMCLCD=y -CONFIG_BACKLIGHT_GENERIC=m -CONFIG_BACKLIGHT_PWM=m -CONFIG_BACKLIGHT_LP855X=m -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_PHYTIUM_I2S=y -CONFIG_SND_PMDK_ES8388=y -CONFIG_SND_PMDK_ES8336=y -CONFIG_SND_PMDK_DP=y -CONFIG_SND_SIMPLE_CARD=m -CONFIG_SND_AUDIO_GRAPH_CARD=m -CONFIG_I2C_HID=m -CONFIG_USB=y -CONFIG_USB_OTG=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_ACM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC2=y -CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_UDC=y -CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_ISP1760=y -CONFIG_USB_PHYTIUM=y -CONFIG_USB_SERIAL=y -CONFIG_USB_SERIAL_CH341=y -CONFIG_USB_SERIAL_OPTION=y -CONFIG_USB_HSIC_USB3503=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_SNP_UDC_PLAT=y -CONFIG_USB_BDC_UDC=y -CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_ACM=y -CONFIG_USB_CONFIGFS_OBEX=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_ECM=y -CONFIG_USB_CONFIGFS_ECM_SUBSET=y -CONFIG_USB_CONFIGFS_RNDIS=y -CONFIG_USB_CONFIGFS_EEM=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_F_UAC1=y -CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y -CONFIG_USB_CONFIGFS_F_UAC2=y -CONFIG_USB_CONFIGFS_F_MIDI=y -CONFIG_USB_CONFIGFS_F_HID=y -CONFIG_USB_CONFIGFS_F_UVC=y -CONFIG_USB_CONFIGFS_F_PRINTER=y -CONFIG_USB_ROLE_SWITCH=m -CONFIG_MMC=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_ARMMMCI=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ACPI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SPI=y -CONFIG_MMC_CQHCI=y -# CONFIG_MMC_PHYTIUM_MCI_PCI is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_EDAC=y -CONFIG_EDAC_GHES=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1307=y -CONFIG_RTC_DRV_DS3232=y -CONFIG_RTC_DRV_EFI=y -CONFIG_RTC_DRV_PL031=y -CONFIG_DMADEVICES=y -CONFIG_MV_XOR_V2=y -CONFIG_PL330_DMA=y -CONFIG_UIO=m -CONFIG_UIO_CIF=m -CONFIG_UIO_PDRV_GENIRQ=m -CONFIG_UIO_DMEM_GENIRQ=m -CONFIG_UIO_AEC=m -CONFIG_UIO_SERCOS3=m -CONFIG_UIO_PCI_GENERIC=m -CONFIG_UIO_NETX=m -CONFIG_UIO_PRUSS=m -CONFIG_UIO_MF624=m -CONFIG_VFIO=y -CONFIG_VFIO_PCI=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_MMIO=y -CONFIG_XEN_GNTDEV=y -CONFIG_XEN_GRANT_DEV_ALLOC=y -CONFIG_STAGING=y -CONFIG_COMMON_CLK_VERSATILE=y -CONFIG_CLK_SP810=y -CONFIG_CLK_VEXPRESS_OSC=y -CONFIG_COMMON_CLK_SCPI=y -CONFIG_COMMON_CLK_CS2000_CP=y -CONFIG_CLK_QORIQ=y -CONFIG_COMMON_CLK_PWM=y -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_PHYTIUM=y -CONFIG_ARM_TIMER_SP804=y -CONFIG_ARM_MHU=y -CONFIG_PHYTIUM_MBOX=y -CONFIG_PLATFORM_MHU=y -CONFIG_ARM_SMMU=y -CONFIG_ARM_SMMU_V3=y -CONFIG_REMOTEPROC=y -CONFIG_RPMSG_CHAR=y -CONFIG_RPMSG_VIRTIO=y -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_EXTCON_USB_GPIO=y -CONFIG_MEMORY=y -CONFIG_IIO=y -CONFIG_PHYTIUM_ADC=y -CONFIG_PWM=y -CONFIG_PWM_PHYTIUM=y -CONFIG_GENERIC_PHY=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_EXT4_ENCRYPTION=y -CONFIG_EXT4_DEBUG=y -CONFIG_XFS_FS=m -CONFIG_XFS_QUOTA=y -CONFIG_XFS_POSIX_ACL=y -CONFIG_XFS_RT=y -CONFIG_XFS_ONLINE_SCRUB=y -CONFIG_XFS_ONLINE_REPAIR=y -CONFIG_XFS_DEBUG=y -CONFIG_FANOTIFY=y -CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -CONFIG_QUOTA=y -CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=m -CONFIG_CUSE=m -CONFIG_OVERLAY_FS=m -CONFIG_OVERLAY_FS_INDEX=y -CONFIG_OVERLAY_FS_XINO_AUTO=y -CONFIG_OVERLAY_FS_METACOPY=y -CONFIG_ISO9660_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_HUGETLBFS=y -CONFIG_EFIVAR_FS=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_XATTR=y -CONFIG_SQUASHFS_LZ4=y -CONFIG_SQUASHFS_LZO=y -CONFIG_SQUASHFS_XZ=y -CONFIG_SQUASHFS_ZSTD=y -CONFIG_NFS_FS=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_SECURITY=y -CONFIG_CRYPTO_USER=y -CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_ANSI_CPRNG=y -CONFIG_CRYPTO_DRBG_HASH=y -CONFIG_CRYPTO_USER_API_HASH=y -CONFIG_CRYPTO_USER_API_SKCIPHER=y -CONFIG_CRYPTO_USER_API_RNG=y -CONFIG_CRYPTO_USER_API_AEAD=y -CONFIG_INDIRECT_PIO=y -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_FS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_FTRACE is not set -CONFIG_MEMTEST=y diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 3cd936b1c79c1701a1c24ab924898ababf434b8b..8418bcfc70d1d86b5ca716566e115fc3e0ab8ed2 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -69,6 +69,7 @@ #define ARM_CPU_IMP_QCOM 0x51 #define ARM_CPU_IMP_NVIDIA 0x4E #define ARM_CPU_IMP_HISI 0x48 +#define ARM_CPU_IMP_PHYTIUM 0x70 #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 @@ -98,6 +99,8 @@ #define NVIDIA_CPU_PART_DENVER 0x003 #define NVIDIA_CPU_PART_CARMEL 0x004 +#define PHYTIUM_CPU_PART_FTC662 0x662 + #define HISI_CPU_PART_TSV110 0xD01 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) @@ -120,6 +123,7 @@ #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) +#define MIDR_PHYTIUM_PS17064 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC662) #ifndef __ASSEMBLY__ diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index f43519b710610ec3d2d2cdf08ff1403cab01d111..b212cb265b7a8fef8f59b162d99e2a2016187f3b 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -526,6 +526,7 @@ static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) { WRITE_ONCE(*pgdp, pgd); dsb(ishst); + isb(); } static inline void pgd_clear(pgd_t *pgdp) diff --git a/drivers/char/hw_random/phytium-rng.c b/drivers/char/hw_random/phytium-rng.c index 5b5e896516b934288ac9f69605069112f3a37fc4..f8ab17f33d0b7a49263abecd977f4201a7757630 100644 --- a/drivers/char/hw_random/phytium-rng.c +++ b/drivers/char/hw_random/phytium-rng.c @@ -2,7 +2,7 @@ /* * Phytium SoC RNG Driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/char/ipmi/bt_bmc_phytium.c b/drivers/char/ipmi/bt_bmc_phytium.c index a4d009ddf4a22e73637ef5d2b0f302df2469391b..1d4a50c14fa3001315a8e3291b5c221fbc157a62 100644 --- a/drivers/char/ipmi/bt_bmc_phytium.c +++ b/drivers/char/ipmi/bt_bmc_phytium.c @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (c) 2021-2022 phytium + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. + * + * Derived from drivers/char/ipmi/bt-bmc.c + * Copyright (c) 2015-2016, IBM Corporation. */ #include diff --git a/drivers/char/ipmi/kcs_bmc_phytium.c b/drivers/char/ipmi/kcs_bmc_phytium.c index abce5f21ae9534e2a462608eccc2a10c2ffbd078..03b6ea3d02cded0c197bd645956dfa11000a5bf3 100644 --- a/drivers/char/ipmi/kcs_bmc_phytium.c +++ b/drivers/char/ipmi/kcs_bmc_phytium.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #define pr_fmt(fmt) "phytium-kcs-bmc: " fmt diff --git a/drivers/dma/phytium/Makefile b/drivers/dma/phytium/Makefile index 71ba9b9fcd4062f7841be505dde68dde679288e0..1dcd89b5c7923852f423c3f239ca99f1088d7a51 100644 --- a/drivers/dma/phytium/Makefile +++ b/drivers/dma/phytium/Makefile @@ -1 +1,3 @@ -obj-$(CONFIG_PHYTIUM_DDMA) += phytium-ddmac.o +// SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_PHYTIUM_DDMA) += phytium-ddmac.o diff --git a/drivers/dma/phytium/phytium-ddmac.c b/drivers/dma/phytium/phytium-ddmac.c index 9ff66bdc96e5821fed02b3379955bdbdb67de64b..734c8a9c680b847f6f848e34657d02338dc68ef1 100644 --- a/drivers/dma/phytium/phytium-ddmac.c +++ b/drivers/dma/phytium/phytium-ddmac.c @@ -2,7 +2,7 @@ /* * Phytium Device DDMA Controller driver. * - * Copyright (c) 2023 Phytium Technology Co., Ltd. + * Copyright (c) 2023-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/dma/phytium/phytium-ddmac.h b/drivers/dma/phytium/phytium-ddmac.h index 81bc0e19e64961ad83abe8ba1f3462eeca50d473..3f02cfd741516ffbdf321764e3c48cd618d18d4f 100644 --- a/drivers/dma/phytium/phytium-ddmac.h +++ b/drivers/dma/phytium/phytium-ddmac.h @@ -2,7 +2,7 @@ /* * Phytium Device DDMA Controller driver. * - * Copyright (c) 2023 Phytium Technology Co., Ltd. + * Copyright (c) 2023-2024 Phytium Technology Co., Ltd. */ #ifndef _PHYTIUM_DDMAC_H diff --git a/drivers/edac/phytium_edac.c b/drivers/edac/phytium_edac.c index 9d63a23fe2e69375cb4fd09a7cf9a13cb6ad5913..55a0f968b78e52a0a039cc10bf78d48ef17cf471 100644 --- a/drivers/edac/phytium_edac.c +++ b/drivers/edac/phytium_edac.c @@ -2,7 +2,7 @@ /* * Phytium Pe220x EDAC (error detection and correction) * - * Copyright (c) 2023 Phytium Technology Co., Ltd. + * Copyright (c) 2023-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/firmware/arm_scmi/common.h b/drivers/firmware/arm_scmi/common.h index 937a930ce87de63d45d7e8d44434efbe62a9d3de..c619582368c857dca952661743aa8c34bccb590c 100644 --- a/drivers/firmware/arm_scmi/common.h +++ b/drivers/firmware/arm_scmi/common.h @@ -91,6 +91,7 @@ struct scmi_xfer { struct scmi_msg tx; struct scmi_msg rx; struct completion done; + spinlock_t lock; }; void scmi_xfer_put(const struct scmi_handle *h, struct scmi_xfer *xfer); diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index bd3113abb598f70de7ba8cf16b4f9b93e904bdbf..fc5d110b0fd95b75c231d5a12b2c7aa679a7c388 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -84,10 +84,6 @@ struct scmi_desc { int max_msg_size; }; -#ifdef CONFIG_ARM_SCMI_TRANSPORT_FORCE_POLLING -static bool scmi_force_polling; -#endif - /** * struct scmi_chan_info - Structure representing a SCMI channel informfation * @@ -383,8 +379,6 @@ scmi_xfer_poll_done(const struct scmi_chan_info *cinfo, struct scmi_xfer *xfer) SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE); } -#define SCMI_MAX_POLL_TO_NS (100 * NSEC_PER_USEC) - static bool scmi_xfer_done_no_timeout(const struct scmi_chan_info *cinfo, struct scmi_xfer *xfer, ktime_t stop) { @@ -393,14 +387,6 @@ static bool scmi_xfer_done_no_timeout(const struct scmi_chan_info *cinfo, return scmi_xfer_poll_done(cinfo, xfer) || ktime_after(__cur, stop); } -#ifdef CONFIG_ARM_SCMI_TRANSPORT_FORCE_POLLING -static int __init scmi_set_force_polling(char *str) -{ - return kstrtobool(str, &scmi_force_polling); -} -early_param("scmi.force_polling", scmi_set_force_polling); -#endif - /** * scmi_do_xfer() - Do one transfer * @@ -418,14 +404,14 @@ int scmi_do_xfer(const struct scmi_handle *handle, struct scmi_xfer *xfer) struct scmi_info *info = handle_to_scmi_info(handle); struct device *dev = info->dev; struct scmi_chan_info *cinfo; + unsigned long flags; cinfo = idr_find(&info->tx_idr, xfer->hdr.protocol_id); if (unlikely(!cinfo)) return -EINVAL; #ifdef CONFIG_ARM_SCMI_TRANSPORT_FORCE_POLLING - if (scmi_force_polling) - xfer->hdr.poll_completion = true; + xfer->hdr.poll_completion = true; #endif ret = mbox_send_message(cinfo->chan, xfer); @@ -438,7 +424,11 @@ int scmi_do_xfer(const struct scmi_handle *handle, struct scmi_xfer *xfer) ret = 0; if (xfer->hdr.poll_completion) { - ktime_t stop = ktime_add_ns(ktime_get(), SCMI_MAX_POLL_TO_NS); + ktime_t stop; + + spin_lock_irqsave(&xfer->lock, flags); + stop = ktime_add_ms(ktime_get(), + info->desc->max_rx_timeout_ms); spin_until_cond(scmi_xfer_done_no_timeout(cinfo, xfer, stop)); @@ -446,6 +436,7 @@ int scmi_do_xfer(const struct scmi_handle *handle, struct scmi_xfer *xfer) scmi_fetch_response(xfer, cinfo->payload); else ret = -ETIMEDOUT; + spin_unlock_irqrestore(&xfer->lock, flags); } else { /* And we wait for the response. */ timeout = msecs_to_jiffies(info->desc->max_rx_timeout_ms); @@ -681,6 +672,7 @@ static int scmi_xfer_info_init(struct scmi_info *sinfo) xfer->tx.buf = xfer->rx.buf; init_completion(&xfer->done); + spin_lock_init(&xfer->lock); } spin_lock_init(&info->xfer_lock); diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c index c00287b5f2c237f8c73eb4ad482df6dc5ba3fd9d..0e94ab56f679834ca0fb89b772c01861a6a8768c 100644 --- a/drivers/firmware/arm_scmi/sensors.c +++ b/drivers/firmware/arm_scmi/sensors.c @@ -34,6 +34,8 @@ struct scmi_msg_resp_sensor_description { __le32 attributes_high; #define SENSOR_TYPE(x) ((x) & 0xff) #define SENSOR_SCALE(x) (((x) >> 11) & 0x1f) +#define SENSOR_SCALE_SIGN BIT(4) +#define SENSOR_SCALE_EXTEND GENMASK(7, 5) #define SENSOR_UPDATE_SCALE(x) (((x) >> 22) & 0x1f) #define SENSOR_UPDATE_BASE(x) (((x) >> 27) & 0x1f) u8 name[SCMI_MAX_STR_SIZE]; @@ -140,6 +142,10 @@ static int scmi_sensor_description_get(const struct scmi_handle *handle, s = &si->sensors[desc_index + cnt]; s->id = le32_to_cpu(buf->desc[cnt].id); s->type = SENSOR_TYPE(attrh); + s->scale = SENSOR_SCALE(attrh); + /* Sign extend to a full s8 */ + if (s->scale & SENSOR_SCALE_SIGN) + s->scale |= SENSOR_SCALE_EXTEND; strlcpy(s->name, buf->desc[cnt].name, SCMI_MAX_STR_SIZE); } diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index c32ae93eaa31e7d3b5b898e41428abc44c5420cb..c0929a1fc5a176caea81aa6b43f4b9b3bdb41984 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -417,7 +417,8 @@ config GPIO_PHYTIUM_PLAT select GENERIC_IRQ_CHIP select GPIOLIB_IRQCHIP help - Say yes here to enable GPIO support for Phytium SoCs. + Say yes here to support the on-chip GPIO controller for the + Phytium SoC family. config GPIO_PHYTIUM_SGPIO tristate "Phytium SGPIO support" diff --git a/drivers/gpio/gpio-phytium-core.c b/drivers/gpio/gpio-phytium-core.c index 6c19c64f79c8f48476445803abc5c721c6fcfb8e..29b422667dc56ea48b1afda72400ed7adeef69e4 100644 --- a/drivers/gpio/gpio-phytium-core.c +++ b/drivers/gpio/gpio-phytium-core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. */ #include @@ -148,7 +148,7 @@ void phytium_gpio_irq_ack(struct irq_data *d) raw_spin_lock(&gpio->lock); - writel(val, gpio->regs + GPIO_PORTA_EOI); + writel(val | 0xffffffff, gpio->regs + GPIO_PORTA_EOI); raw_spin_unlock(&gpio->lock); } diff --git a/drivers/gpio/gpio-phytium-core.h b/drivers/gpio/gpio-phytium-core.h index a308a8aedba34c705c05ff701f991b321eacd10b..e165d4c66f450e98ca56415122b93b302dfbb63c 100644 --- a/drivers/gpio/gpio-phytium-core.h +++ b/drivers/gpio/gpio-phytium-core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. */ #ifndef _GPIO_PHYTIUM_H diff --git a/drivers/gpio/gpio-phytium-pci.c b/drivers/gpio/gpio-phytium-pci.c index c2c336b7c7bf9ee55d6e27208f6cb65cab69de52..46d4cf58d53fb124fd5b86a4e8ee94eacc6a060b 100644 --- a/drivers/gpio/gpio-phytium-pci.c +++ b/drivers/gpio/gpio-phytium-pci.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpio/gpio-phytium-platform.c b/drivers/gpio/gpio-phytium-platform.c index 092fd2489809602fcafb57e31d16c23ec047ae04..61ee2a4a5fda49f149cd0b824c0a77a1e448f4c9 100644 --- a/drivers/gpio/gpio-phytium-platform.c +++ b/drivers/gpio/gpio-phytium-platform.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. * Derived from drivers/gpio/gpio-pl061.c * Copyright (C) 2008, 2009 Provigent Ltd. */ diff --git a/drivers/gpio/gpio-phytium-sgpio.c b/drivers/gpio/gpio-phytium-sgpio.c index e7d7bb1c83761c5ca4c31d0413ccedd4220f8124..74ec3a98347909ae516588cf020a63b1f9ace64e 100644 --- a/drivers/gpio/gpio-phytium-sgpio.c +++ b/drivers/gpio/gpio-phytium-sgpio.c @@ -2,7 +2,7 @@ /* * Phytium SGPIO Support * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/pe220x_dc.c b/drivers/gpu/drm/phytium/pe220x_dc.c index 7fa323d65c853a69b9621e8669372e0d4976312c..5f7f527a744cdeed50a7df7f34c6551c20f64e61 100644 --- a/drivers/gpu/drm/phytium/pe220x_dc.c +++ b/drivers/gpu/drm/phytium/pe220x_dc.c @@ -2,7 +2,7 @@ /* * Phytium PE220X display controller DRM driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/pe220x_dc.h b/drivers/gpu/drm/phytium/pe220x_dc.h index 0fbe31dd15cf105d90c47dd7232849b15ece2f81..af17f99a0b12ae35b3d5e116d058dd5d6194997e 100644 --- a/drivers/gpu/drm/phytium/pe220x_dc.h +++ b/drivers/gpu/drm/phytium/pe220x_dc.h @@ -2,7 +2,7 @@ /* * Phytium PE220X display controller DRM driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PE220X_DC_H__ diff --git a/drivers/gpu/drm/phytium/pe220x_dp.c b/drivers/gpu/drm/phytium/pe220x_dp.c index 19f38fc01106cc3ae33f42f9ee37407df13b3c4f..08597ae2f2aac1b934cf8c1e063622dbd25b5d40 100644 --- a/drivers/gpu/drm/phytium/pe220x_dp.c +++ b/drivers/gpu/drm/phytium/pe220x_dp.c @@ -2,7 +2,7 @@ /* * Phytium display port DRM driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include "phytium_display_drv.h" diff --git a/drivers/gpu/drm/phytium/pe220x_dp.h b/drivers/gpu/drm/phytium/pe220x_dp.h index a79bf5b5e3ab8d70ccd1d2f683e916a96fee2ae7..78bb26c7b75cc3fb90bee1e85a30dd269a582adc 100644 --- a/drivers/gpu/drm/phytium/pe220x_dp.h +++ b/drivers/gpu/drm/phytium/pe220x_dp.h @@ -2,7 +2,7 @@ /* * Phytium display port DRM driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PE220X_DP_H__ diff --git a/drivers/gpu/drm/phytium/pe220x_reg.h b/drivers/gpu/drm/phytium/pe220x_reg.h index 7ec9620f5cbff628ee985faf34af682737e3a7b5..f4a0090cd5b63ec14090270dc1ad0df7593673c3 100644 --- a/drivers/gpu/drm/phytium/pe220x_reg.h +++ b/drivers/gpu/drm/phytium/pe220x_reg.h @@ -2,7 +2,7 @@ /* * Phytium PE220X display engine register * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PE220X_REG_H__ diff --git a/drivers/gpu/drm/phytium/phytium_crtc.c b/drivers/gpu/drm/phytium/phytium_crtc.c index c7869f0f57ee0c85b48fa0ec8b2ed669b28c4c64..f220c9a35cd55963de8e55939e37c1e76e092ff8 100644 --- a/drivers/gpu/drm/phytium/phytium_crtc.c +++ b/drivers/gpu/drm/phytium/phytium_crtc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/phytium_crtc.h b/drivers/gpu/drm/phytium/phytium_crtc.h index 86f894ba5d7068277f11630ae1922f2be1a6d6a4..8c5b2eb0ec0a25d0ca9df18a3f6684387d8e0a91 100644 --- a/drivers/gpu/drm/phytium/phytium_crtc.h +++ b/drivers/gpu/drm/phytium/phytium_crtc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_CRTC_H__ diff --git a/drivers/gpu/drm/phytium/phytium_debugfs.c b/drivers/gpu/drm/phytium/phytium_debugfs.c index dc0d42f001361e7a4d6bf180bef2b33612dcfdeb..32779be377cf980b5e728f0c52be25bdd217fe3c 100644 --- a/drivers/gpu/drm/phytium/phytium_debugfs.c +++ b/drivers/gpu/drm/phytium/phytium_debugfs.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/phytium_debugfs.h b/drivers/gpu/drm/phytium/phytium_debugfs.h index aa8e2922ec257ec465d02657c0c81d40405f2177..7e632bf9c521cc02340b439b9e7e106389e03794 100644 --- a/drivers/gpu/drm/phytium/phytium_debugfs.h +++ b/drivers/gpu/drm/phytium/phytium_debugfs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_DEBUGFS_H__ diff --git a/drivers/gpu/drm/phytium/phytium_display_drv.c b/drivers/gpu/drm/phytium/phytium_display_drv.c index 22e94fa874891fcce7a52dd6ceaa6c691d550f7b..9e7261064a6806680bc148788b4a883f9c111412 100644 --- a/drivers/gpu/drm/phytium/phytium_display_drv.c +++ b/drivers/gpu/drm/phytium/phytium_display_drv.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -275,7 +275,7 @@ static int phytium_display_load(struct drm_device *dev, unsigned long flags) goto failed_modeset_init; } - if (priv->support_memory_type & MEMORY_TYPE_VRAM) + if (priv->support_memory_type & (MEMORY_TYPE_VRAM_WC | MEMORY_TYPE_VRAM_DEVICE)) priv->vram_hw_init(priv); ret = drm_irq_install(dev, priv->irq); @@ -311,8 +311,25 @@ static const struct vm_operations_struct phytium_vm_ops = { .close = drm_gem_vm_close, }; +/* phytium display specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_PHYTIUM_VRAM_TYPE_DEVICE 0x0 +#define DRM_IOCTL_PHYTIUM_VRAM_TYPE_DEVICE DRM_IO(DRM_COMMAND_BASE\ + + DRM_PHYTIUM_VRAM_TYPE_DEVICE) + +static int phytium_ioctl_check_vram_device(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + struct phytium_display_private *priv = dev->dev_private; + + return ((priv->support_memory_type == MEMORY_TYPE_VRAM_DEVICE) ? 1 : 0); +} + static const struct drm_ioctl_desc phytium_ioctls[] = { /* for test, none so far */ + DRM_IOCTL_DEF_DRV(PHYTIUM_VRAM_TYPE_DEVICE, phytium_ioctl_check_vram_device, + DRM_AUTH|DRM_UNLOCKED), }; static const struct file_operations phytium_drm_driver_fops = { @@ -421,7 +438,7 @@ static int phytium_display_pm_resume(struct drm_device *dev) phytium_crtc_resume(dev); phytium_gem_resume(dev); - if (priv->support_memory_type & MEMORY_TYPE_VRAM) + if (priv->support_memory_type & (MEMORY_TYPE_VRAM_WC | MEMORY_TYPE_VRAM_DEVICE)) priv->vram_hw_init(priv); ret = drm_atomic_helper_resume(dev, dev->mode_config.suspend_state); diff --git a/drivers/gpu/drm/phytium/phytium_display_drv.h b/drivers/gpu/drm/phytium/phytium_display_drv.h index df24138ed57819b28db9ccfd8f29748ed27e7067..973591a66e87449f312567b3d37808723d1ad156 100644 --- a/drivers/gpu/drm/phytium/phytium_display_drv.h +++ b/drivers/gpu/drm/phytium/phytium_display_drv.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_DISPLAY_DRV_H__ @@ -50,9 +50,10 @@ enum phytium_mem_state_type { PHYTIUM_MEM_STATE_TYPE_COUNT, }; -#define MEMORY_TYPE_VRAM 0x1 +#define MEMORY_TYPE_VRAM_WC 0x1 #define MEMORY_TYPE_SYSTEM_CARVEOUT 0x2 #define MEMORY_TYPE_SYSTEM_UNIFIED 0x4 +#define MEMORY_TYPE_VRAM_DEVICE 0x8 #define IS_PLATFORM(priv, p) ((priv)->info.platform_mask & BIT(p)) diff --git a/drivers/gpu/drm/phytium/phytium_dp.c b/drivers/gpu/drm/phytium/phytium_dp.c index 0f9824f7e32f385fd1453e2ec65f6146503c14a6..2af682d6a96811f37d8f99633cc769ee9f0620cd 100644 --- a/drivers/gpu/drm/phytium/phytium_dp.c +++ b/drivers/gpu/drm/phytium/phytium_dp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -1729,6 +1729,7 @@ static int phytium_dp_long_pulse(struct drm_connector *connector, bool hpd_raw_s enum drm_connector_status status = connector->status; bool video_enable = false; uint32_t index = 0; + struct edid *edid = NULL; if (phytium_dp->is_edp) status = connector_status_connected; @@ -1762,6 +1763,15 @@ static int phytium_dp_long_pulse(struct drm_connector *connector, bool hpd_raw_s mdelay(2); phytium_dp_hw_enable_video(phytium_dp); } + + edid = drm_get_edid(connector, &phytium_dp->aux.ddc); + + if (edid && drm_edid_is_valid(edid)) + phytium_dp->has_audio = drm_detect_monitor_audio(edid); + else + phytium_dp->has_audio = false; + + kfree(edid); } out: diff --git a/drivers/gpu/drm/phytium/phytium_dp.h b/drivers/gpu/drm/phytium/phytium_dp.h index 3433f294424bb5def8c798c857feb14a1ed28c6c..047357a0d523be1d073fe1c5192cce3f4aa8a447 100644 --- a/drivers/gpu/drm/phytium/phytium_dp.h +++ b/drivers/gpu/drm/phytium/phytium_dp.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_DP_H__ diff --git a/drivers/gpu/drm/phytium/phytium_fb.c b/drivers/gpu/drm/phytium/phytium_fb.c index bae872465065a4b0d3c65b457990387aa5adf601..15b8fb2c6638fb87495c7049b9d316acf05532d9 100644 --- a/drivers/gpu/drm/phytium/phytium_fb.c +++ b/drivers/gpu/drm/phytium/phytium_fb.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -66,9 +66,10 @@ phytium_fb_alloc(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd return ERR_PTR(ret); } - for (i = 0; i < num_planes; i++) + for (i = 0; i < num_planes; i++) { phytium_fb->phytium_gem_obj[i] = phytium_gem_obj[i]; - + phytium_fb->base.obj[i] = &phytium_gem_obj[i]->base; + } return phytium_fb; } diff --git a/drivers/gpu/drm/phytium/phytium_fb.h b/drivers/gpu/drm/phytium/phytium_fb.h index c5c9a860789fc75fe7878f437c0e093c942ba3a4..d909c39ffcc8b8129964f2fafc2adefb9f06dc6d 100644 --- a/drivers/gpu/drm/phytium/phytium_fb.h +++ b/drivers/gpu/drm/phytium/phytium_fb.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_FB_H__ diff --git a/drivers/gpu/drm/phytium/phytium_fbdev.c b/drivers/gpu/drm/phytium/phytium_fbdev.c index 22933029733f734b021d9e5e8039247a4c9a8e03..d55e613089a17288ca9275194455a61ecd8a44e0 100644 --- a/drivers/gpu/drm/phytium/phytium_fbdev.c +++ b/drivers/gpu/drm/phytium/phytium_fbdev.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/phytium_fbdev.h b/drivers/gpu/drm/phytium/phytium_fbdev.h index 81070502c8e07a210f50bf4f7b0a967afd388633..ff63ba84d7728c76635193db762b627ba4a0ac42 100644 --- a/drivers/gpu/drm/phytium/phytium_fbdev.h +++ b/drivers/gpu/drm/phytium/phytium_fbdev.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef _PHYTIUM_FBDEV_H diff --git a/drivers/gpu/drm/phytium/phytium_gem.c b/drivers/gpu/drm/phytium/phytium_gem.c index a386e28d8820460308c8741faa8607ba0183e490..2068bd40fa9eb852294599db7b39a3745d5e723d 100644 --- a/drivers/gpu/drm/phytium/phytium_gem.c +++ b/drivers/gpu/drm/phytium/phytium_gem.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -86,7 +86,8 @@ phytium_gem_prime_get_sg_table(struct drm_gem_object *obj) return ERR_PTR(-ENOMEM); } - if ((phytium_gem_obj->memory_type == MEMORY_TYPE_VRAM) || + if ((phytium_gem_obj->memory_type == MEMORY_TYPE_VRAM_WC) || + (phytium_gem_obj->memory_type == MEMORY_TYPE_VRAM_DEVICE) || (phytium_gem_obj->memory_type == MEMORY_TYPE_SYSTEM_CARVEOUT)) { ret = sg_alloc_table(sgt, 1, GFP_KERNEL); if (ret) { @@ -165,6 +166,7 @@ void *phytium_gem_prime_vmap(struct drm_gem_object *obj) void phytium_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr) { + return; } int phytium_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) @@ -279,7 +281,8 @@ int phytium_gem_suspend(struct drm_device *drm_dev) int ret = 0; list_for_each_entry(phytium_gem_obj, &priv->gem_list_head, list) { - if (phytium_gem_obj->memory_type != MEMORY_TYPE_VRAM) + if ((phytium_gem_obj->memory_type != MEMORY_TYPE_VRAM_WC) && + (phytium_gem_obj->memory_type != MEMORY_TYPE_VRAM_DEVICE)) continue; phytium_gem_obj->vaddr_save = vmalloc(phytium_gem_obj->size); @@ -298,7 +301,8 @@ int phytium_gem_suspend(struct drm_device *drm_dev) return 0; malloc_failed: list_for_each_entry(phytium_gem_obj, &priv->gem_list_head, list) { - if (phytium_gem_obj->memory_type != MEMORY_TYPE_VRAM) + if ((phytium_gem_obj->memory_type != MEMORY_TYPE_VRAM_WC) && + (phytium_gem_obj->memory_type != MEMORY_TYPE_VRAM_DEVICE)) continue; if (phytium_gem_obj->vaddr_save) { @@ -315,7 +319,8 @@ void phytium_gem_resume(struct drm_device *drm_dev) struct phytium_gem_object *phytium_gem_obj = NULL; list_for_each_entry(phytium_gem_obj, &priv->gem_list_head, list) { - if (phytium_gem_obj->memory_type != MEMORY_TYPE_VRAM) + if ((phytium_gem_obj->memory_type != MEMORY_TYPE_VRAM_WC) && + (phytium_gem_obj->memory_type != MEMORY_TYPE_VRAM_DEVICE)) continue; memcpy(phytium_gem_obj->vaddr, phytium_gem_obj->vaddr_save, phytium_gem_obj->size); @@ -334,7 +339,8 @@ void phytium_gem_free_object(struct drm_gem_object *obj) DRM_DEBUG_KMS("free phytium_gem_obj iova:0x%pa size:0x%lx\n", &phytium_gem_obj->iova, phytium_gem_obj->size); if (phytium_gem_obj->vaddr) { - if (phytium_gem_obj->memory_type == MEMORY_TYPE_VRAM) { + if ((phytium_gem_obj->memory_type == MEMORY_TYPE_VRAM_WC) || + (phytium_gem_obj->memory_type == MEMORY_TYPE_VRAM_DEVICE)) { phytium_memory_pool_free(priv, phytium_gem_obj->vaddr, size); priv->mem_state[PHYTIUM_MEM_VRAM_ALLOC] -= size; } else if (phytium_gem_obj->memory_type == MEMORY_TYPE_SYSTEM_CARVEOUT) { @@ -367,10 +373,14 @@ int phytium_gem_mmap_obj(struct drm_gem_object *obj, struct vm_area_struct *vma) vma->vm_pgoff = 0; vma->vm_page_prot = vm_get_page_prot(vma->vm_flags); - if (phytium_gem_obj->memory_type == MEMORY_TYPE_VRAM) { + if (phytium_gem_obj->memory_type == MEMORY_TYPE_VRAM_WC) { vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); ret = remap_pfn_range(vma, vma->vm_start, pfn, vma->vm_end - vma->vm_start, vma->vm_page_prot); + } else if (phytium_gem_obj->memory_type == MEMORY_TYPE_VRAM_DEVICE) { + vma->vm_page_prot = pgprot_device(vma->vm_page_prot); + ret = remap_pfn_range(vma, vma->vm_start, pfn, + vma->vm_end - vma->vm_start, vma->vm_page_prot); } else if (phytium_gem_obj->memory_type == MEMORY_TYPE_SYSTEM_CARVEOUT) { ret = remap_pfn_range(vma, vma->vm_start, pfn, vma->vm_end - vma->vm_start, vma->vm_page_prot); @@ -400,7 +410,6 @@ int phytium_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev, uint return drm_gem_dumb_destroy(file, dev, handle); } - struct phytium_gem_object *phytium_gem_create_object(struct drm_device *dev, unsigned long size) { struct phytium_gem_object *phytium_gem_obj = NULL; @@ -421,7 +430,7 @@ struct phytium_gem_object *phytium_gem_create_object(struct drm_device *dev, uns goto failed_object_init; } - if (priv->support_memory_type & MEMORY_TYPE_VRAM) { + if (priv->support_memory_type & (MEMORY_TYPE_VRAM_WC | MEMORY_TYPE_VRAM_DEVICE)) { ret = phytium_memory_pool_alloc(priv, &phytium_gem_obj->vaddr, &phytium_gem_obj->phys_addr, size); if (ret) { @@ -429,7 +438,7 @@ struct phytium_gem_object *phytium_gem_create_object(struct drm_device *dev, uns goto failed_dma_alloc; } phytium_gem_obj->iova = phytium_gem_obj->phys_addr; - phytium_gem_obj->memory_type = MEMORY_TYPE_VRAM; + phytium_gem_obj->memory_type = priv->support_memory_type; priv->mem_state[PHYTIUM_MEM_VRAM_ALLOC] += size; } else if (priv->support_memory_type & MEMORY_TYPE_SYSTEM_CARVEOUT) { ret = phytium_memory_pool_alloc(priv, &phytium_gem_obj->vaddr, diff --git a/drivers/gpu/drm/phytium/phytium_gem.h b/drivers/gpu/drm/phytium/phytium_gem.h index cd34f4a4539f97ef698b3a293863be6df23740fb..50fb4f4f7b6b6f80a77958671d0dc1bf677332b3 100644 --- a/drivers/gpu/drm/phytium/phytium_gem.h +++ b/drivers/gpu/drm/phytium/phytium_gem.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_GEM_H__ diff --git a/drivers/gpu/drm/phytium/phytium_panel.c b/drivers/gpu/drm/phytium/phytium_panel.c index 16783b24a4d374bdfaac23275ce1a36269544058..efb839ae02ea78a3092f5d098b13299da8217169 100644 --- a/drivers/gpu/drm/phytium/phytium_panel.c +++ b/drivers/gpu/drm/phytium/phytium_panel.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/phytium_panel.h b/drivers/gpu/drm/phytium/phytium_panel.h index 91760e26dcf18636b5ddea494b178daf7e383d35..ff4d760d8400766e932fe7657ed82412f9665e83 100644 --- a/drivers/gpu/drm/phytium/phytium_panel.h +++ b/drivers/gpu/drm/phytium/phytium_panel.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_PANEL_H__ diff --git a/drivers/gpu/drm/phytium/phytium_pci.c b/drivers/gpu/drm/phytium/phytium_pci.c index bc2f8a8cbf9801f6fdc4a4af039dd35231f99799..58f5f69336ea415f2a855d8f34b159253679add7 100644 --- a/drivers/gpu/drm/phytium/phytium_pci.c +++ b/drivers/gpu/drm/phytium/phytium_pci.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -27,6 +27,24 @@ void phytium_pci_vram_hw_init(struct phytium_display_private *priv) pci_priv->dc_hw_vram_init(priv, priv->pool_phys_addr, priv->pool_size); } +static bool phytium_pci_host_is_5c01(struct pci_bus *bus) +{ + struct pci_bus *child = bus; + struct pci_dev *root = NULL; + + while (child) { + if (child->parent->parent) + child = child->parent; + else + break; + } + + root = child->self; + if ((root->vendor == 0x1db7) && (root->device == 0x5c01)) + return true; + return false; +} + int phytium_pci_vram_init(struct pci_dev *pdev, struct phytium_display_private *priv) { int ret = 0; @@ -34,8 +52,15 @@ int phytium_pci_vram_init(struct pci_dev *pdev, struct phytium_display_private * priv->pool_phys_addr = pci_resource_start(pdev, 2); priv->pool_size = pci_resource_len(pdev, 2); if ((priv->pool_phys_addr != 0) && (priv->pool_size != 0)) { - priv->pool_virt_addr = devm_ioremap_wc(&pdev->dev, priv->pool_phys_addr, - priv->pool_size); + if ((pdev->device == 0xdc3e) && phytium_pci_host_is_5c01(pdev->bus)) { + priv->pool_virt_addr = devm_ioremap(&pdev->dev, priv->pool_phys_addr, + priv->pool_size); + priv->support_memory_type = MEMORY_TYPE_VRAM_DEVICE; + } else { + priv->pool_virt_addr = devm_ioremap_wc(&pdev->dev, priv->pool_phys_addr, + priv->pool_size); + priv->support_memory_type = MEMORY_TYPE_VRAM_WC; + } if (priv->pool_virt_addr == NULL) { DRM_ERROR("pci vram ioremap fail, addr:0x%llx, size:0x%llx\n", priv->pool_phys_addr, priv->pool_size); @@ -47,7 +72,6 @@ int phytium_pci_vram_init(struct pci_dev *pdev, struct phytium_display_private * goto failed_init_memory_pool; priv->mem_state[PHYTIUM_MEM_VRAM_TOTAL] = priv->pool_size; - priv->support_memory_type = MEMORY_TYPE_VRAM; priv->vram_hw_init = phytium_pci_vram_hw_init; } else { DRM_DEBUG_KMS("not support vram\n"); @@ -67,7 +91,8 @@ int phytium_pci_vram_init(struct pci_dev *pdev, struct phytium_display_private * void phytium_pci_vram_fini(struct pci_dev *pdev, struct phytium_display_private *priv) { - if (priv->support_memory_type == MEMORY_TYPE_VRAM) { + if ((priv->support_memory_type == MEMORY_TYPE_VRAM_WC) || + (priv->support_memory_type == MEMORY_TYPE_VRAM_DEVICE)) { phytium_memory_pool_fini(&pdev->dev, priv); devm_iounmap(&pdev->dev, priv->pool_virt_addr); } diff --git a/drivers/gpu/drm/phytium/phytium_pci.h b/drivers/gpu/drm/phytium/phytium_pci.h index ad116dfcb5e97921f06c2c5cf157f547106b4993..7ac37971759c812d67f9e22768745394d6ad020a 100644 --- a/drivers/gpu/drm/phytium/phytium_pci.h +++ b/drivers/gpu/drm/phytium/phytium_pci.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_PCI_H__ diff --git a/drivers/gpu/drm/phytium/phytium_plane.c b/drivers/gpu/drm/phytium/phytium_plane.c index bccfbc74c5e0b33df96b9ead1978440568b0d5c4..1ae2ac88475686faab7571d72c001987d6c02f8e 100644 --- a/drivers/gpu/drm/phytium/phytium_plane.c +++ b/drivers/gpu/drm/phytium/phytium_plane.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/phytium_plane.h b/drivers/gpu/drm/phytium/phytium_plane.h index ee8786ced54ca0a4ec20b8d7c9b8ebc651f80d3f..25b6bba6c87d3b815e6c30b6f4e553dde33b851e 100644 --- a/drivers/gpu/drm/phytium/phytium_plane.h +++ b/drivers/gpu/drm/phytium/phytium_plane.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_PLANE_H__ diff --git a/drivers/gpu/drm/phytium/phytium_platform.c b/drivers/gpu/drm/phytium/phytium_platform.c index 99d7cb5dc3e0658820d9c85a708295d73b3d48a5..d17a4ca947dbcf225c655ea6e93a82f779ea4a6f 100644 --- a/drivers/gpu/drm/phytium/phytium_platform.c +++ b/drivers/gpu/drm/phytium/phytium_platform.c @@ -2,10 +2,11 @@ /* * Phytium display engine DRM driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include +#include #include #include #include @@ -19,13 +20,29 @@ int phytium_platform_carveout_mem_init(struct platform_device *pdev, struct phytium_display_private *priv) { - struct resource *res; + struct device_node *np; + struct resource res; + struct resource *pres; int ret = 0; - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (res) { - priv->pool_size = resource_size(res); - priv->pool_phys_addr = res->start; + if (pdev->dev.of_node) { + np = of_parse_phandle(pdev->dev.of_node, "memory-region", 0); + if(!np) + goto next; + ret = of_address_to_resource(np, 0, &res); + if(ret) + DRM_ERROR("No memory address assigned to the region\n"); + else { + priv->pool_size = resource_size(&res); + priv->pool_phys_addr = res.start; + } + } + +next: + pres = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (pres) { + priv->pool_size = resource_size(pres); + priv->pool_phys_addr = pres->start; } if ((priv->pool_phys_addr != 0) && (priv->pool_size != 0)) { diff --git a/drivers/gpu/drm/phytium/phytium_platform.h b/drivers/gpu/drm/phytium/phytium_platform.h index e752f79130db5e4c4a1d525c79992b12aecff580..b754ef0a137a3a21a45c62c9aa313b0c6aee18d1 100644 --- a/drivers/gpu/drm/phytium/phytium_platform.h +++ b/drivers/gpu/drm/phytium/phytium_platform.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_PLATFORM_H__ diff --git a/drivers/gpu/drm/phytium/phytium_reg.h b/drivers/gpu/drm/phytium/phytium_reg.h index 28735acee149ac650956fb8dabf2c20d39969bc5..4dca6c02312792035be8bc57d1f68ebd0420011d 100644 --- a/drivers/gpu/drm/phytium/phytium_reg.h +++ b/drivers/gpu/drm/phytium/phytium_reg.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_REG_H__ diff --git a/drivers/gpu/drm/phytium/px210_dc.c b/drivers/gpu/drm/phytium/px210_dc.c index 4e737236d66833bfcd3faa83a4e7dfff46531c22..c9447ccaa98f3a0636fa349a64428bfbd07fe09c 100644 --- a/drivers/gpu/drm/phytium/px210_dc.c +++ b/drivers/gpu/drm/phytium/px210_dc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/px210_dc.h b/drivers/gpu/drm/phytium/px210_dc.h index d58819339f10fb3ca8a5176eff4c4f4f1d92b063..f2471fcb532e40b57a251e80d9d5578b3de7781f 100644 --- a/drivers/gpu/drm/phytium/px210_dc.h +++ b/drivers/gpu/drm/phytium/px210_dc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PX210_DC_H__ diff --git a/drivers/gpu/drm/phytium/px210_dp.c b/drivers/gpu/drm/phytium/px210_dp.c index d7bd04eac2a84714ece2694d94c04c37e3e39667..7c655563132a83c0b615ee12d1768d1b702f5056 100644 --- a/drivers/gpu/drm/phytium/px210_dp.c +++ b/drivers/gpu/drm/phytium/px210_dp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include "phytium_display_drv.h" diff --git a/drivers/gpu/drm/phytium/px210_dp.h b/drivers/gpu/drm/phytium/px210_dp.h index 4ad65397f1aa23a40e5591981563dcfd7baae527..07e40265f02c894f5e789250c29ec37622679ef8 100644 --- a/drivers/gpu/drm/phytium/px210_dp.h +++ b/drivers/gpu/drm/phytium/px210_dp.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PX210_DP_H__ diff --git a/drivers/gpu/drm/phytium/px210_reg.h b/drivers/gpu/drm/phytium/px210_reg.h index 5556b3ee5c1db894844687520371979380c20e70..dbe1e537fc4a9db8e0aa5bbfc6686751a5e0bd6b 100644 --- a/drivers/gpu/drm/phytium/px210_reg.h +++ b/drivers/gpu/drm/phytium/px210_reg.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PX210_REG_H__ diff --git a/drivers/hwmon/scmi-hwmon.c b/drivers/hwmon/scmi-hwmon.c index 91bfecdb3f5ba62b730dd4b62a0e00683ac6c62f..59d896e61a995ad1681ccf45ca9ce06d7d4b3216 100644 --- a/drivers/hwmon/scmi-hwmon.c +++ b/drivers/hwmon/scmi-hwmon.c @@ -18,6 +18,50 @@ struct scmi_sensors { const struct scmi_sensor_info **info[hwmon_max]; }; +static inline u64 __pow10(u8 x) +{ + u64 r = 1; + + while (x--) + r *= 10; + + return r; +} + +static int scmi_hwmon_scale(const struct scmi_sensor_info *sensor, u64 *value) +{ + s8 scale = sensor->scale; + u64 f; + + switch (sensor->type) { + case TEMPERATURE_C: + case VOLTAGE: + case CURRENT: + scale += 3; + break; + case POWER: + case ENERGY: + scale += 6; + break; + default: + break; + } + + if (scale == 0) + return 0; + + if (abs(scale) > 19) + return -E2BIG; + + f = __pow10(abs(scale)); + if (scale > 0) + *value *= f; + else + *value = div64_u64(*value, f); + + return 0; +} + static int scmi_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long *val) { @@ -29,6 +73,10 @@ static int scmi_hwmon_read(struct device *dev, enum hwmon_sensor_types type, sensor = *(scmi_sensors->info[type] + channel); ret = h->sensor_ops->reading_get(h, sensor->id, false, &value); + if (ret) + return ret; + + ret = scmi_hwmon_scale(sensor, &value); if (!ret) *val = value; diff --git a/drivers/hwmon/tacho-phytium.c b/drivers/hwmon/tacho-phytium.c index cbfbe0b8250f548463c1ffa159621fb58f8b74d2..c89251f3595a3a3146832e735d6ef06ebd932d46 100644 --- a/drivers/hwmon/tacho-phytium.c +++ b/drivers/hwmon/tacho-phytium.c @@ -2,7 +2,7 @@ /* * Hwmon driver for Phytium tachometer. * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/hwspinlock/phytium_hwspinlock.c b/drivers/hwspinlock/phytium_hwspinlock.c index ec057388726a8f43a3b92920486012403f08186a..0294c820a28f4170597249a5b9a6d3c47a04117e 100644 --- a/drivers/hwspinlock/phytium_hwspinlock.c +++ b/drivers/hwspinlock/phytium_hwspinlock.c @@ -2,7 +2,7 @@ /* * Phytium hardware spinlock driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/i2c/busses/i2c-phytium-common.c b/drivers/i2c/busses/i2c-phytium-common.c index 2af8689d861e62c3dcaaac39bd975a0bbda23672..78f2c8b21ebc536fe7d8bc69228e66590e2a2de9 100644 --- a/drivers/i2c/busses/i2c-phytium-common.c +++ b/drivers/i2c/busses/i2c-phytium-common.c @@ -4,7 +4,7 @@ * * Based on the TI DAVINCI I2C adapter driver. * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include #include @@ -30,7 +30,7 @@ static char *abort_sources[] = { [ABRT_TXDATA_NOACK] = "data not acknowledged", [ABRT_GCALL_NOACK] = - "no acknowledgement for a general call", + "no acknowledgment for a general call", [ABRT_GCALL_READ] = "read after general call", [ABRT_SBYTE_ACKDET] = diff --git a/drivers/i2c/busses/i2c-phytium-core.h b/drivers/i2c/busses/i2c-phytium-core.h index 7cf42787389ee2ed2337ae7421086d44c2ed2175..726a4f9f4f17285c1a60be38f047d4419df5c24c 100644 --- a/drivers/i2c/busses/i2c-phytium-core.h +++ b/drivers/i2c/busses/i2c-phytium-core.h @@ -2,7 +2,7 @@ /* * Phytium I2C adapter driver. * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -111,7 +111,7 @@ #define IC_ERR_TX_ABRT 0x1 -#define IC_TAR_10BITADDR_MASTER BIT(12) +#define IC_TAR_10BITADDR_MASTER BIT(12) #define IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3)) #define IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2) diff --git a/drivers/i2c/busses/i2c-phytium-master.c b/drivers/i2c/busses/i2c-phytium-master.c index b525b8e153b86d140e5247d42a5ff4aa17ba1a37..b8bf2612fddaa2e60bfb5afaad1dd7d8250b33fd 100644 --- a/drivers/i2c/busses/i2c-phytium-master.c +++ b/drivers/i2c/busses/i2c-phytium-master.c @@ -2,7 +2,7 @@ /* * Phytium I2C adapter driver. * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include #include diff --git a/drivers/i2c/busses/i2c-phytium-pci.c b/drivers/i2c/busses/i2c-phytium-pci.c index 0e0a72468bb55b121d5070d2991a8dfe23d4160d..23feee308d375cf3a773c6314de3295586162069 100644 --- a/drivers/i2c/busses/i2c-phytium-pci.c +++ b/drivers/i2c/busses/i2c-phytium-pci.c @@ -2,7 +2,7 @@ /* * PCI driver for Phytium I2C adapter. * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/i2c/busses/i2c-phytium-platform.c b/drivers/i2c/busses/i2c-phytium-platform.c index 66709bb91d69823ce19bb0cfaeed73ca72674c33..ea0a1a6437fbce7520a75b409e65130edbf9f83c 100644 --- a/drivers/i2c/busses/i2c-phytium-platform.c +++ b/drivers/i2c/busses/i2c-phytium-platform.c @@ -2,7 +2,7 @@ /* * Phytium I2C adapter driver. * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/i2c/busses/i2c-phytium-slave.c b/drivers/i2c/busses/i2c-phytium-slave.c index a9409f55c6522e15b1127cf793e89dd5d97b2c3f..e6d25ca1b6a5b5291db65b3e82be2b8c4632f14d 100644 --- a/drivers/i2c/busses/i2c-phytium-slave.c +++ b/drivers/i2c/busses/i2c-phytium-slave.c @@ -2,7 +2,7 @@ /* * Phytium I2C adapter driver (slave only). * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/iio/adc/phytium-adc.c b/drivers/iio/adc/phytium-adc.c old mode 100755 new mode 100644 index e8dfa4546326f4da11f6bcc2426d0343ba97d48a..5f6e7541685a213745a8c43c12bb0182565f64aa --- a/drivers/iio/adc/phytium-adc.c +++ b/drivers/iio/adc/phytium-adc.c @@ -2,7 +2,7 @@ /* * Phytium ADC device driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -579,7 +579,6 @@ static int phytium_adc_probe(struct platform_device *pdev) indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); if (!indio_dev) return -ENOMEM; - platform_set_drvdata(pdev, indio_dev); adc = iio_priv(indio_dev); adc->dev = dev; @@ -607,6 +606,8 @@ static int phytium_adc_probe(struct platform_device *pdev) indio_dev->channels = adc->data->channels; indio_dev->num_channels = adc->data->num_channels; + platform_set_drvdata(pdev, indio_dev); + ret = devm_request_threaded_irq(adc->dev, platform_get_irq(pdev, 0), NULL, phytium_adc_threaded_irq, IRQF_ONESHOT, dev_name(dev), adc); @@ -626,7 +627,7 @@ static int phytium_adc_probe(struct platform_device *pdev) return ret; } - return devm_iio_device_register(dev, indio_dev); + return iio_device_register(indio_dev); } static int phytium_adc_remove(struct platform_device *pdev) diff --git a/drivers/input/keyboard/phytium-keypad.c b/drivers/input/keyboard/phytium-keypad.c index 37750d78bc2d682bba3b4a0f9f0bc2cb5dea8cd2..c87e7ff6467c12f9142b90bcb175f64e7b4358ef 100644 --- a/drivers/input/keyboard/phytium-keypad.c +++ b/drivers/input/keyboard/phytium-keypad.c @@ -2,7 +2,7 @@ /* * Driver for the Phytium keypad port. * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/input/serio/phytium-ps2.c b/drivers/input/serio/phytium-ps2.c index 173866f396664f13630ee29e71e6194cea2dc91f..8f1e5fc5130f005c50ba3dfa232fa96bc805a138 100644 --- a/drivers/input/serio/phytium-ps2.c +++ b/drivers/input/serio/phytium-ps2.c @@ -2,7 +2,7 @@ /* * Phytium PS/2 keyboard controller driver. * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 9511b124a9b21f3c124d13b5c784fcfe78c705eb..cf7524c086268548c7b18129dd1c84e3295fef39 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -3035,8 +3035,8 @@ MODULE_DEVICE_TABLE(of, arm_smmu_of_match); #ifdef CONFIG_PM_SLEEP static const struct dev_pm_ops arm_smmu_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(arm_smmu_suspend, - arm_smmu_resume) + .suspend_noirq = arm_smmu_suspend, + .resume_noirq = arm_smmu_resume, }; #define ARM_SMMU_PM_OPS (&arm_smmu_pm_ops) #else diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 0c3b8f1c7225e8ec24db9cffa92c570b18b9e7c4..b4c75287d204a5b175d0096886411e169eec3326 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1402,6 +1402,7 @@ static int arm_smmu_add_device(struct device *dev) sid, smmu->streamid_mask); goto out_free; } + if (mask & ~smmu->smr_mask_mask) { dev_err(dev, "SMR mask 0x%x out of range for SMMU (0x%x)\n", mask, smmu->smr_mask_mask); diff --git a/drivers/irqchip/irq-phytium-ixic.c b/drivers/irqchip/irq-phytium-ixic.c index c33331a0e45a2dfebd5a546e8656f33c98cda436..72d37e3162ec046f59c8b8941d505309b878013e 100644 --- a/drivers/irqchip/irq-phytium-ixic.c +++ b/drivers/irqchip/irq-phytium-ixic.c @@ -2,7 +2,7 @@ /* * Driver for Phytium PCIe legacy INTx interrupt controller * - * Copyright (c) 2020-2023, Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/mailbox/phytium_mailbox.c b/drivers/mailbox/phytium_mailbox.c index e33eb82efa44184e331e898a11356d5d3387b1c4..e44e848134dfd18c2fd911e11091cc0e2a3fb6bb 100644 --- a/drivers/mailbox/phytium_mailbox.c +++ b/drivers/mailbox/phytium_mailbox.c @@ -2,7 +2,7 @@ /* * Phytium SoC mailbox driver * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. * * Derived from drivers/mailbox/arm_mhu.c * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd. diff --git a/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.c b/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.c index 37a5674a0dd1d64849a8358241618b96bfca88ae..35e2891af54fcc3702739cda8c5a0a277d944a09 100644 --- a/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.c +++ b/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.c @@ -2,7 +2,7 @@ /* * Driver for Phytium JPEG Encoder Engine * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include "phytium_jpeg_reg.h" diff --git a/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.h b/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.h index e398d974d928dd2addede501b933aaa872e64244..c2849278ce6011ed8afdb065cfbedd32a5a1a814 100644 --- a/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.h +++ b/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef _PHYTIUM_JPEG_CORE_H diff --git a/drivers/media/platform/phytium-jpeg/phytium_jpeg_reg.h b/drivers/media/platform/phytium-jpeg/phytium_jpeg_reg.h index 3567badf9eb50139e995beaa52ea9f540db782bb..b0a27e2b7e89b027d1293daa024fa7f13f748f5c 100644 --- a/drivers/media/platform/phytium-jpeg/phytium_jpeg_reg.h +++ b/drivers/media/platform/phytium-jpeg/phytium_jpeg_reg.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef _PHYTIUM_JPEG_REG_H diff --git a/drivers/mfd/phytium_px210_i2s_lsd.c b/drivers/mfd/phytium_px210_i2s_lsd.c index bfdbc9a4ebcd3b268539830eb7b98a21dd47522d..ab75113a2bd0d7669f536d29d820f58bf2e9f49e 100644 --- a/drivers/mfd/phytium_px210_i2s_lsd.c +++ b/drivers/mfd/phytium_px210_i2s_lsd.c @@ -2,7 +2,7 @@ /* * Phytium I2S LSD MFD driver over PCI bus * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any diff --git a/drivers/mfd/phytium_px210_i2s_mmd.c b/drivers/mfd/phytium_px210_i2s_mmd.c index 4020686d4ce2e847988246bb3adb3a27dfe5b2ab..c225741bbb9ceb59e4dbf2a7135e723b6915862f 100644 --- a/drivers/mfd/phytium_px210_i2s_mmd.c +++ b/drivers/mfd/phytium_px210_i2s_mmd.c @@ -2,7 +2,7 @@ /* * Phytium I2S MMD MFD driver over PCI bus * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/mmc/host/phytium-mci-pci.c b/drivers/mmc/host/phytium-mci-pci.c index 7e4ba4ac0a20dd40046c2169c376ffdbd548e979..08b20ad57deb6ac8092f3aa7155a806498050d06 100644 --- a/drivers/mmc/host/phytium-mci-pci.c +++ b/drivers/mmc/host/phytium-mci-pci.c @@ -2,7 +2,7 @@ /* * Phytium Multimedia Card Interface PCI driver * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. * */ diff --git a/drivers/mmc/host/phytium-mci-plat.c b/drivers/mmc/host/phytium-mci-plat.c index 966dbe3d96344d13ff9943c23fb029b264a1975c..b4a7b070902c30912dab8db400499f6ae887ad22 100644 --- a/drivers/mmc/host/phytium-mci-plat.c +++ b/drivers/mmc/host/phytium-mci-plat.c @@ -2,7 +2,7 @@ /* * Phytium Multimedia Card Interface platform driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -140,7 +140,7 @@ static int phytium_mci_remove(struct platform_device *pdev) } static const struct of_device_id phytium_mci_of_ids[] = { - { .compatible = "phytium,mci", }, + { .compatible = "phytium,mci", }, {} }; @@ -148,8 +148,8 @@ MODULE_DEVICE_TABLE(of, phytium_mci_of_ids); #ifdef CONFIG_ACPI static const struct acpi_device_id phytium_mci_acpi_ids[] = { - { .id = "PHYT0017" }, - { } + { .id = "PHYT0017" }, + { } }; MODULE_DEVICE_TABLE(acpi, phytium_mci_acpi_ids); diff --git a/drivers/mmc/host/phytium-mci.c b/drivers/mmc/host/phytium-mci.c index ce96fbd5968a117584d6b2b16126e591c4f477e1..943259e8780d86a7d02fd5d63682116e31e58faa 100644 --- a/drivers/mmc/host/phytium-mci.c +++ b/drivers/mmc/host/phytium-mci.c @@ -2,7 +2,7 @@ /* * Driver for Phytium Multimedia Card Interface * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -655,6 +655,8 @@ phytium_mci_start_data(struct phytium_mci_host *host, struct mmc_request *mrq, phytium_mci_data_sg_write_2_fifo(host, data); spin_lock_irqsave(&host->lock, flags); + mod_timer(&host->timeout_timer, + jiffies + msecs_to_jiffies(MMC_REQ_TIMEOUT_MS)); sdr_set_bits(host->base + MCI_INT_MASK, cmd_ints_mask | data_ints_mask); if (host->is_use_dma && host->adtc_type == BLOCK_RW_ADTC) { sdr_set_bits(host->base + MCI_DMAC_INT_ENA, dmac_ints_mask); @@ -670,9 +672,6 @@ phytium_mci_start_data(struct phytium_mci_host *host, struct mmc_request *mrq, wmb(); /* drain writebuffer */ writel(rawcmd, host->base + MCI_CMD); spin_unlock_irqrestore(&host->lock, flags); - - mod_timer(&host->timeout_timer, - jiffies + msecs_to_jiffies(MMC_REQ_TIMEOUT_MS)); } static void phytium_mci_track_cmd_data(struct phytium_mci_host *host, @@ -794,13 +793,12 @@ static void phytium_mci_start_command(struct phytium_mci_host *host, } spin_lock_irqsave(&host->lock, flags); + mod_timer(&host->timeout_timer, + jiffies + msecs_to_jiffies(MMC_REQ_TIMEOUT_MS)); sdr_set_bits(host->base + MCI_INT_MASK, cmd_ints_mask); writel(cmd->arg, host->base + MCI_CMDARG); writel(rawcmd, host->base + MCI_CMD); spin_unlock_irqrestore(&host->lock, flags); - - mod_timer(&host->timeout_timer, - jiffies + msecs_to_jiffies(MMC_REQ_TIMEOUT_MS)); } static void diff --git a/drivers/mmc/host/phytium-mci.h b/drivers/mmc/host/phytium-mci.h index 5423597ecb97b13bc85d0486ee2323debbb66363..c35e6f3b3a859872f9c0702ff715004163c21f91 100644 --- a/drivers/mmc/host/phytium-mci.h +++ b/drivers/mmc/host/phytium-mci.h @@ -2,7 +2,7 @@ /* * Driver for Phytium Multimedia Card Interface * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_MCI_H diff --git a/drivers/mmc/host/phytium-sdci.c b/drivers/mmc/host/phytium-sdci.c index 5b389a8c564249a82059f437a11d01c194e5a56e..2c10bf3e234b5013d964dfd67abb00644e3f2c31 100644 --- a/drivers/mmc/host/phytium-sdci.c +++ b/drivers/mmc/host/phytium-sdci.c @@ -2,7 +2,7 @@ /* * Phytium SDCI dirver * - * Copyright (c) 2019-2023, Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/mmc/host/phytium-sdci.h b/drivers/mmc/host/phytium-sdci.h index e15591a1c378cda27919b568ad8487b1ee489f15..0e85e4a7f0ce0ffa18b42d8d10c463d19e36ad5e 100644 --- a/drivers/mmc/host/phytium-sdci.h +++ b/drivers/mmc/host/phytium-sdci.h @@ -2,7 +2,7 @@ /* * File Name: phytium_sdci.h - Phytium FT SDCI dirver * - * Copyright (c) 2019-2023, Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/mtd/nand/raw/phytium_nand.c b/drivers/mtd/nand/raw/phytium_nand.c index f94ccd41221bd83136d8af1e68542d8ecd85be2b..fe91baecdc38348b3ab6467e82b21bdf6bde3b3c 100644 --- a/drivers/mtd/nand/raw/phytium_nand.c +++ b/drivers/mtd/nand/raw/phytium_nand.c @@ -2,7 +2,7 @@ /* * Core driver for Phytium NAND flash controller * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #include @@ -54,8 +54,6 @@ static u32 nfc_irq_st; static u32 nfc_irq_en; static u32 nfc_irq_complete; -static DECLARE_WAIT_QUEUE_HEAD(wait_done); - /* * Internal helper to conditionnally apply a delay (from the above structure, * most of the time). @@ -331,6 +329,8 @@ int phytium_nfc_send_cmd(struct nand_chip *chip, return 0; } + reinit_completion(&nfc->complete); + spin_lock(&nfc->spinlock); value = nfc->dsp_phy_addr & 0xFFFFFFFF; phytium_write(nfc, NDAR0, value); @@ -393,6 +393,8 @@ int phytium_nfc_send_cmd2(struct nand_chip *chip, return 0; } + reinit_completion(&nfc->complete); + spin_lock(&nfc->spinlock); value = nfc->dsp_phy_addr & 0xFFFFFFFF; phytium_write(nfc, NDAR0, value); @@ -426,9 +428,8 @@ int phytium_nfc_wait_op(struct nand_chip *chip, else if (timeout_ms < 100) timeout_ms = 100; - ret = wait_event_interruptible_timeout(wait_done, nfc_irq_complete, + ret = wait_for_completion_timeout(&nfc->complete, msecs_to_jiffies(timeout_ms)); - nfc_irq_complete = false; if (!ret) { dev_err(nfc->dev, "Timeout waiting for RB signal\n"); @@ -437,6 +438,7 @@ int phytium_nfc_wait_op(struct nand_chip *chip, phytium_read(nfc, NDIR), phytium_read(nfc, NDIR_MASK)); dev_err(nfc->dev, "NFC debug: %x\n", phytium_read(nfc, ND_DEBUG)); + complete_release(&nfc->complete); phytium_nfc_clear_int(nfc, NDIR_ALL_INT(nfc->caps->int_mask_bits)); return -ETIMEDOUT; } @@ -993,6 +995,21 @@ static void phytium_nfc_disable_hw_ecc(struct nand_chip *chip) phytium_write(nfc, NDCR0, ndcr0 & ~NDCR0_ECC_EN); } +static void nfc_irq_callback(struct work_struct *work) +{ + struct phytium_nfc *nfc = container_of(work, struct phytium_nfc, work); + + if (!nfc) + return; + + if (nfc_irq_complete) + complete_all(&nfc->complete); + + nfc_irq_st = 0; + nfc_irq_en = 0; + nfc_irq_complete = 0; +} + irqreturn_t phytium_nfc_isr(int irq, void *dev_id) { struct phytium_nfc *nfc = dev_id; @@ -1030,7 +1047,7 @@ irqreturn_t phytium_nfc_isr(int irq, void *dev_id) nfc_irq_complete = 1; } - wake_up(&wait_done); + schedule_work(&nfc->work); return IRQ_HANDLED; } @@ -1490,10 +1507,8 @@ static int phytium_nand_page_write_hwecc(struct mtd_info *mtd, struct nand_chip ecc_offset = phytium_nand->ecc.offset; nfc_op = kzalloc(2 * sizeof(struct phytium_nfc_op), GFP_KERNEL); - if (!nfc_op) { - dev_err(nfc->dev, "Can't malloc space for phytium_nfc_op\n"); + if (!nfc_op) return 0; - } nfc_op->cle_ale_delay_ns = PSEC_TO_NSEC(sdr->tWB_max); nfc_op->rdy_timeout_ms = PSEC_TO_MSEC(sdr->tR_max); @@ -2104,11 +2119,15 @@ int phytium_nand_init(struct phytium_nfc *nfc) nfc->controller.ops = &phytium_nand_controller_ops; INIT_LIST_HEAD(&nfc->chips); + init_completion(&nfc->complete); + /* Init the controller and then probe the chips */ ret = phytium_nfc_init(nfc); if (ret) goto out; + INIT_WORK(&nfc->work, nfc_irq_callback); + ret = phytium_nand_chip_init(nfc); if (ret) goto out; diff --git a/drivers/mtd/nand/raw/phytium_nand.h b/drivers/mtd/nand/raw/phytium_nand.h index 963d555a2aca009c7904b1d362d7b833483b507f..c1ef4b5b2fdb5e76dc32c2792c8e0f6180866bb5 100644 --- a/drivers/mtd/nand/raw/phytium_nand.h +++ b/drivers/mtd/nand/raw/phytium_nand.h @@ -2,7 +2,7 @@ /* * Phytium NAND flash controller driver * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #ifndef PHYTIUM_NAND_H #define PHYTIUM_NAND_H @@ -345,6 +345,7 @@ struct phytium_nfc { struct device *dev; void __iomem *regs; int irq; + struct completion complete; struct list_head chips; struct nand_chip *selected_chip; struct phytium_nfc_caps *caps; @@ -361,6 +362,7 @@ struct phytium_nfc { u32 timing_mode; spinlock_t spinlock; + struct work_struct work; }; /** diff --git a/drivers/mtd/nand/raw/phytium_nand_pci.c b/drivers/mtd/nand/raw/phytium_nand_pci.c index 6ce76dd15161a183bbad882ff7a1c333ecdb5095..a8f054d669cc60765e2a0887030185f3d36bc6d6 100644 --- a/drivers/mtd/nand/raw/phytium_nand_pci.c +++ b/drivers/mtd/nand/raw/phytium_nand_pci.c @@ -2,7 +2,7 @@ /* * PCI driver for Phytium NAND flash controller * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include #include diff --git a/drivers/mtd/nand/raw/phytium_nand_plat.c b/drivers/mtd/nand/raw/phytium_nand_plat.c index b3fde07b4aeb18b16db35fcd061716ff6c8c8d9f..65504785f33ba1b441e5fa06302a016f7be7d009 100644 --- a/drivers/mtd/nand/raw/phytium_nand_plat.c +++ b/drivers/mtd/nand/raw/phytium_nand_plat.c @@ -2,7 +2,7 @@ /* * Core driver for Phytium NAND flash controller * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/mtd/spi-nor/phytium-quadspi.c b/drivers/mtd/spi-nor/phytium-quadspi.c index cb3476e0ca88d0d2da0de0a504058eba42ebb69e..4a3c5e713cdba56f2bcb25e24683b9cfe1e67790 100644 --- a/drivers/mtd/spi-nor/phytium-quadspi.c +++ b/drivers/mtd/spi-nor/phytium-quadspi.c @@ -2,7 +2,7 @@ /* * Phytium QuadSPI driver. * - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. */ #include #include @@ -118,7 +118,7 @@ #define QSPI_WIP_W_CMD_MASK (0xFF << QSPI_WIP_W_CMD_SHIFT) #define QSPI_WIP_W_TRANSFER_SHIFT 3 #define QSPI_WIP_W_TRANSFER_MASK (0x3 << QSPI_WIP_W_TRANSFER_SHIFT) -#define QSPI_WIP_W_SCK_SEL_SHIFT 0 +#define QSPI_WIP_W_SCK_SEL_SHIFT 0 #define QSPI_WIP_W_SCK_SEL_MASK (0x7 << QSPI_WIP_W_SCK_SEL_SHIFT) #define QSPI_WP_EN_SHIFT 17 @@ -160,7 +160,7 @@ #define CMD_RDAR 0x65 #define CMD_P4E 0x20 #define CMD_4P4E 0x21 -#define CMD_BE 0x60 +#define CMD_BE 0x60 #define CMD_4BE 0xC7 #define CMD_READ 0x03 #define CMD_FAST_READ 0x0B @@ -232,7 +232,7 @@ static int memcpy_from_ftreg(struct phytium_qspi *qspi, u_char *buf, size_t len) return -EINVAL; for (i = 0; i < len; i++) { - if (0 == i % 4) + if (i % 4 == 0) val = readl_relaxed(qspi->io_base + QSPI_LD_PORT_REG); buf[i] = (u_char) (val >> (i % 4) * 8) & 0xFF; @@ -249,16 +249,16 @@ static int memcpy_to_ftreg(struct phytium_qspi *qspi, u_char *buf, size_t len) if (!qspi || !buf || (len >= 8)) return -EINVAL; - if (1 == len) { + if (len == 1) { val = buf[0]; - } else if (2 == len) { + } else if (len == 2) { val = buf[1]; val = (val << 8) + buf[0]; - } else if (3 == len) { + } else if (len == 3) { val = buf[2]; val = (val << 8) + buf[1]; val = (val << 8) + buf[0]; - } else if (4 == len) { + } else if (len == 4) { val = buf[3]; val = (val << 8) + buf[2]; val = (val << 8) + buf[1]; @@ -455,7 +455,7 @@ static int phytium_qspi_write_reg(struct spi_nor *nor, u8 opcode, dev_dbg(dev, "write_reg: cmd:%#.2x buf:%pK len:%#x\n", opcode, buf, len); - switch(opcode){ + switch (opcode) { case CMD_WREN: phytium_qspi_write_enable(qspi, flash); return 0; @@ -470,11 +470,10 @@ static int phytium_qspi_write_reg(struct spi_nor *nor, u8 opcode, cmd |= PHYTIUM_CMD_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT; cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT; - if ((len > 8) || (NULL == buf)) { - dev_err(dev, "data length exceed. commad %x, len:%d \n", opcode, len); + if (len > 8 || !buf) { + dev_err(dev, "data length exceed. commad %x, len:%d\n", opcode, len); return -EINVAL; - } - else if(len > 0){ + } else if (len > 0) { cmd |= ((len - 1) << QSPI_CMD_PORT_RW_NUM_SHIFT) & QSPI_CMD_PORT_RW_NUM_MASK; cmd |= BIT(QSPI_CMD_PORT_DATA_TRANSFER_SHIFT); } @@ -574,12 +573,11 @@ static ssize_t phytium_qspi_read(struct spi_nor *nor, loff_t from, size_t len, case 0x5A: cmd &= ~QSPI_RD_CFG_RD_ADDR_SEL_MASK; return phytium_qspi_read_flash_sfdp(qspi, flash, nor, from, buf, len); - break; default: break; } - if(nor->read_dummy != 0) { + if (nor->read_dummy != 0) { cmd |= BIT(QSPI_RD_CFG_RD_LATENCY_SHIFT); cmd &= ~QSPI_RD_CFG_DUMMY_MASK; @@ -640,9 +638,8 @@ static ssize_t phytium_qspi_write(struct spi_nor *nor, loff_t to, size_t len, dev_dbg(qspi->dev, "write cmd:%x\n", cmd); writel_relaxed(cmd, qspi->io_base + QSPI_WR_CFG_REG); - for (i = 0; i < len/4; i++) { + for (i = 0; i < len/4; i++) writel_relaxed(*(u32 *)(buf + 4*i), qspi->mm_base + addr + 4*i); - } if (len & mask) { addr = addr + (len & ~mask); @@ -872,7 +869,7 @@ static int phytium_qspi_flash_setup(struct phytium_qspi *qspi, flash->registered = true; - dev_dbg(qspi->dev, "read mm:%s %px cs:%d bus:%d clk-div:%d\n", + dev_dbg(qspi->dev, "read mm:%s %p cs:%d bus:%d clk-div:%d\n", flash->read_mode == PHYTIUM_FMODE_MM ? "yes" : "no", qspi->mm_base, cs_num, width, clk_div); @@ -910,7 +907,7 @@ static ssize_t clk_div_store(struct device *dev, char *token; ssize_t status; - token = strsep ((char **)&buf, " "); + token = strsep((char **)&buf, " "); if (!token) return -EINVAL; @@ -1042,7 +1039,7 @@ MODULE_DEVICE_TABLE(acpi, phytium_qspi_acpi_ids); #endif static const struct of_device_id phytium_qspi_match[] = { - {.compatible = "phytium,qspi"}, + { .compatible = "phytium,qspi" }, { } }; MODULE_DEVICE_TABLE(of, phytium_qspi_match); diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index b6bb1f9350cd574af88fca6fb0bd4018d58f2b6c..f081ec4f70ab9ee3266e8b7eba4d3ff7ed1e05d1 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1270,9 +1270,12 @@ static const struct flash_info spi_nor_ids[] = { { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) }, /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ - { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "XM25QH128B", INFO(0x205018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { "XM25QH128B", INFO(0x205018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { }, }; diff --git a/drivers/net/can/phytium/phytium_can.c b/drivers/net/can/phytium/phytium_can.c index 95ec7311bfcb738632329c9a5a4d22b283ed8822..1b2859ac106751b9bb80293d0199cf7be30c3ca5 100644 --- a/drivers/net/can/phytium/phytium_can.c +++ b/drivers/net/can/phytium/phytium_can.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* CAN bus driver for Phytium CAN controller * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -85,8 +85,10 @@ enum phytium_can_reg { #define INTR_STATUS_MASK (INTR_BOIS | INTR_PWIS | INTR_PEIS | INTR_RFIS | \ INTR_TFIS | INTR_REIS | INTR_TEIS | INTR_EIS) -#define INTR_EN_MASK (INTR_BOIE | INTR_RFIE | INTR_REIE | INTR_TEIE | \ - INTR_EIE) + +#define INTR_EN_MASK (INTR_BOIE | INTR_PWIE | INTR_PEIE | INTR_RFIE | \ + INTR_REIE | INTR_TEIE | INTR_EIE) + #define INTR_CLEAR_MASK (INTR_BOIC | INTR_PWIC | INTR_PEIC | INTR_RFIC | \ INTR_TFIC | INTR_REIC | INTR_TEIC | INTR_EIC) @@ -282,7 +284,7 @@ static inline u32 phytium_can_read(const struct phytium_can_dev *cdev, enum phyt } static inline void phytium_can_write(const struct phytium_can_dev *cdev, enum phytium_can_reg reg, - u32 val) + u32 val) { writel(val, cdev->base + reg); } @@ -417,21 +419,6 @@ static int phytium_can_do_rx_poll(struct net_device *dev, int quota) return pkts; } -static int phytium_can_rx_handler(struct net_device *dev, int quota) -{ - int work_done = 0; - int rx_work_or_err; - - /* Handle RX IRQ */ - rx_work_or_err = phytium_can_do_rx_poll(dev, (quota - work_done)); - if (rx_work_or_err < 0) - return rx_work_or_err; - - work_done += rx_work_or_err; - - return 0; -} - static int phytium_can_poll(struct napi_struct *napi, int quota) { struct net_device *dev = napi->dev; @@ -441,13 +428,14 @@ static int phytium_can_poll(struct napi_struct *napi, int quota) netdev_dbg(dev, "The receive processing is going on !\n"); - work_done = phytium_can_rx_handler(dev, quota); + work_done = phytium_can_do_rx_poll(dev, quota); /* Don't re-enable interrupts if the driver had a fatal error * (e.g., FIFO read failure) */ if (work_done >= 0 && work_done < quota) { napi_complete_done(napi, work_done); + spin_lock_irqsave(&cdev->lock, flags); phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_REIE); spin_unlock_irqrestore(&cdev->lock, flags); @@ -550,6 +538,11 @@ static void phytium_can_write_frame(struct phytium_can_dev *cdev) stats->tx_bytes += cf->len; stats->tx_packets++; + + cdev->is_tx_done = false; + cdev->is_need_stop_xmit = true; + mod_timer(&cdev->timer, jiffies + HZ / 10); + netdev_dbg(dev, "Trigger send message!\n"); can_put_echo_skb(skb, dev, 0); can_get_echo_skb(dev, 0); @@ -563,7 +556,6 @@ static netdev_tx_t phytium_can_tx_handler(struct phytium_can_dev *cdev) unsigned long flags; phytium_can_write_frame(cdev); - /* Check if the TX buffer is full */ tx_fifo_used = 4 * ((phytium_can_read(cdev, CAN_FIFO_CNT) & FIFO_CNT_TFN) >> 16); if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { @@ -596,9 +588,8 @@ static void phytium_can_tx_interrupt(struct net_device *ndev, u32 isr) struct net_device_stats *stats = &ndev->stats; u32 tx_fifo_used = 0; - if (isr & INTR_TEIS) { + if (isr & INTR_TEIS) phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_TEIC); - } /* Check if the TX buffer is full */ if (cdev->is_stop_queue_flag) { @@ -615,8 +606,43 @@ static void phytium_can_tx_interrupt(struct net_device *ndev, u32 isr) } } } + + cdev->is_tx_done = true; + cdev->is_need_stop_xmit = false; + del_timer(&cdev->timer); + netdev_dbg(ndev, "Finish transform packets %lu\n", stats->tx_packets); + + + phytium_can_set_reg_bits(cdev, CAN_INTR, (INTR_BOIE | + INTR_PWIE | INTR_PEIE)); + can_led_event(ndev, CAN_LED_EVENT_TX); + +} + +static void phytium_can_tx_done_timeout(struct timer_list *t) +{ + struct phytium_can_dev *priv = from_timer(priv, t, timer); + struct net_device *ndev = priv->net; + + if (!priv->is_tx_done) { + if (priv->is_need_stop_xmit) { + netdev_dbg(ndev, "%s stop xmit\n", __func__); + priv->is_need_stop_xmit = false; + phytium_can_clr_reg_bits(priv, CAN_CTRL, CTRL_XFER); + phytium_can_clr_reg_bits(priv, CAN_INTR, (INTR_BOIE | + INTR_PWIE | INTR_PEIE)); + /* stop xmit and restart after 500ms */ + mod_timer(&priv->timer, jiffies + HZ / 2); + } else { + netdev_dbg(ndev, "%s start xmit\n", __func__); + priv->is_need_stop_xmit = true; + phytium_can_set_reg_bits(priv, CAN_CTRL, CTRL_XFER); + /* start xmit and stop after 250ms */ + mod_timer(&priv->timer, jiffies + HZ / 4); + } + } } static void phytium_can_err_interrupt(struct net_device *ndev, u32 isr) @@ -717,6 +743,7 @@ static irqreturn_t phytium_can_isr(int irq, void *dev_id) isr = phytium_can_read(cdev, CAN_INTR) & INTR_STATUS_MASK; if (!isr) return IRQ_NONE; + spin_lock(&cdev->lock); /* Check for FIFO full interrupt and alarm */ if ((isr & INTR_RFIS)) { @@ -726,25 +753,32 @@ static irqreturn_t phytium_can_isr(int irq, void *dev_id) napi_schedule(&cdev->napi); } + /* Check for FIFO empty interrupt and alarm */ + if ((isr & INTR_TFIS)) { + netdev_dbg(dev, "tx_fifo is empty!.\n"); + isr &= (~INTR_TFIS); + phytium_can_clr_reg_bits(cdev, CAN_INTR, INTR_TFIE); + phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_TFIC); + } + /* Check for the type of error interrupt and Processing it */ - if (isr & (INTR_EIS | INTR_RFIS | INTR_BOIS)) { - phytium_can_clr_reg_bits(cdev, CAN_INTR, (INTR_EIE - | INTR_RFIE | INTR_BOIE)); + if (isr & (INTR_EIS | INTR_RFIS | INTR_BOIS | INTR_PWIS | INTR_PEIS)) { + phytium_can_clr_reg_bits(cdev, CAN_INTR, (INTR_EIE | INTR_RFIE | + INTR_BOIE | INTR_PWIE | INTR_PEIE)); phytium_can_err_interrupt(dev, isr); - phytium_can_set_reg_bits(cdev, CAN_INTR, (INTR_EIC - | INTR_RFIC | INTR_BOIC)); - phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_EIE | INTR_BOIE); + phytium_can_set_reg_bits(cdev, CAN_INTR, (INTR_EIC | INTR_RFIC | + INTR_BOIC | INTR_PWIC | INTR_PEIC)); spin_unlock(&cdev->lock); return IRQ_HANDLED; } /* Check for Tx interrupt and Processing it */ - if (isr & INTR_TEIS) { + if ((isr & INTR_TEIS)) { phytium_can_tx_interrupt(dev, isr); } /* Check for the type of receive interrupt and Processing it */ - if (isr & INTR_REIS) { + if (isr & (INTR_REIS)) { phytium_can_clr_reg_bits(cdev, CAN_INTR, INTR_REIE); phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_REIC); napi_schedule(&cdev->napi); @@ -877,12 +911,14 @@ static void phytium_can_stop(struct net_device *dev) /* Disable all interrupts */ phytium_can_disable_all_interrupt(cdev); - + /* Disable transfer and switch to receive-only mode */ ctrl = phytium_can_read(cdev, CAN_CTRL); ctrl &= ~(CTRL_XFER | CTRL_TXREQ); phytium_can_write(cdev, CAN_CTRL, ctrl); + del_timer(&cdev->timer); + /* Set the state as STOPPED */ cdev->can.state = CAN_STATE_STOPPED; } @@ -927,9 +963,10 @@ static int phytium_can_open(struct net_device *dev) ret = pm_runtime_get_sync(cdev->dev); if (ret < 0) { netdev_err(dev, "%s: pm_runtime_get failed(%d)\n", - __func__, ret); + __func__, ret); return ret; } + /* Open the CAN device */ ret = open_candev(dev); if (ret) { @@ -948,6 +985,8 @@ static int phytium_can_open(struct net_device *dev) /* Start the controller */ phytium_can_start(dev); + netdev_dbg(dev, "%s is going on\n", __func__); + can_led_event(dev, CAN_LED_EVENT_OPEN); napi_enable(&cdev->napi); cdev->is_stop_queue_flag = STOP_QUEUE_FALSE; @@ -1085,6 +1124,10 @@ int phytium_can_register(struct phytium_can_dev *cdev) goto fail; } + cdev->is_tx_done = true; + cdev->is_need_stop_xmit = false; + timer_setup(&cdev->timer, phytium_can_tx_done_timeout, 0); + devm_can_led_init(cdev->net); dev_info(cdev->dev, "%s device registered (irq=%d)\n", diff --git a/drivers/net/can/phytium/phytium_can.h b/drivers/net/can/phytium/phytium_can.h index 400571b745dce625312e9d57bff6d1abfa32c5ed..52bddeddc5cfb13b5bf7a96fcd16f00cdc118848 100644 --- a/drivers/net/can/phytium/phytium_can.h +++ b/drivers/net/can/phytium/phytium_can.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium CAN controller driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef _PHYTIUM_CAN_H_ @@ -41,9 +41,7 @@ struct phytium_can_devtype { struct phytium_can_dev { struct can_priv can; - unsigned int tx_head; - unsigned int tx_tail; - unsigned int tx_max; + struct napi_struct napi; struct net_device *net; struct device *dev; @@ -52,13 +50,16 @@ struct phytium_can_dev { struct sk_buff *tx_skb; const struct can_bittiming_const *bit_timing; - spinlock_t lock; + spinlock_t lock; /*spinlock*/ int fdmode; u32 isr; u32 tx_fifo_depth; unsigned int is_stop_queue_flag; - struct completion comp; void __iomem *base; + + struct timer_list timer; /* xmit done timer */ + u32 is_tx_done; + u32 is_need_stop_xmit; }; struct phytium_can_dev *phytium_can_allocate_dev(struct device *dev, int sizeof_priv, diff --git a/drivers/net/can/phytium/phytium_can_pci.c b/drivers/net/can/phytium/phytium_can_pci.c index ae4a6f877432c1972bbab9358ba102f312333e35..a41833b7e8af67555142c6b2df54281e6983ccb4 100644 --- a/drivers/net/can/phytium/phytium_can_pci.c +++ b/drivers/net/can/phytium/phytium_can_pci.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Platform CAN bus driver for Phytium CAN controller * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -41,7 +41,7 @@ static const struct phytium_can_devtype phytium_can_pci = { static const struct phytium_can_pci_config phytium_can_pci_data = { .devtype = &phytium_can_pci, - .clock_freq = 600000000, + .clock_freq = 480000000, .tx_fifo_depth = 64, }; @@ -76,10 +76,6 @@ static int phytium_can_pci_probe(struct pci_dev *pdev, const struct pci_device_i cdev->can.clock.freq = cfg->clock_freq; cdev->tx_fifo_depth = cfg->tx_fifo_depth; - cdev->tx_head = 0; - cdev->tx_tail = 0; - cdev->tx_max = cfg->tx_fifo_depth; - cdev->base = priv->base; cdev->net->irq = pdev->irq; @@ -90,7 +86,7 @@ static int phytium_can_pci_probe(struct pci_dev *pdev, const struct pci_device_i ret = pm_runtime_get_sync(cdev->dev); if (ret < 0) { netdev_err(cdev->net, "%s: pm_runtime_get failed(%d)\n", - __func__, ret); + __func__, ret); goto err_pmdisable; } ret = phytium_can_register(cdev); diff --git a/drivers/net/can/phytium/phytium_can_platform.c b/drivers/net/can/phytium/phytium_can_platform.c index ce479af1116242d06afe61355538c571afb0f8ed..35a747ad76d008c1eef11cb29b6379b6e34e79de 100644 --- a/drivers/net/can/phytium/phytium_can_platform.c +++ b/drivers/net/can/phytium/phytium_can_platform.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Platform CAN bus driver for Phytium CAN controller * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -71,7 +71,6 @@ static const struct of_device_id phytium_can_of_ids[] = { MODULE_DEVICE_TABLE(of, phytium_can_of_ids); #endif - static int phytium_can_plat_probe(struct platform_device *pdev) { struct phytium_can_dev *cdev; @@ -81,7 +80,7 @@ static int phytium_can_plat_probe(struct platform_device *pdev) const struct phytium_can_devtype *devtype = &phytium_can_data; u32 tx_fifo_depth; int ret; - const char *mode; + const char *str = "can"; ret = fwnode_property_read_u32(dev_fwnode(&pdev->dev), "tx-fifo-depth", &tx_fifo_depth); if (ret) @@ -122,16 +121,11 @@ static int phytium_can_plat_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failed to get clock frequency.\n"); goto fail; } - ret = fwnode_property_read_string(dev_fwnode(&pdev->dev), "mode-select", &mode); - if (ret < 0) { - dev_info(&pdev->dev, "get mode-select ret: %d\n", ret); - } - else { - if (strncmp("canfd", mode, strlen("canfd")) == 0) { - dev_info(&pdev->dev, "use mode-select: canfd\n"); - devtype = &phytium_canfd_data; - } - } + + fwnode_property_read_string(dev_fwnode(&pdev->dev), + "mode-select", &str); + if (!(strcmp(str, "canfd"))) + devtype = &phytium_canfd_data; } cdev->tx_fifo_depth = tx_fifo_depth; @@ -151,7 +145,15 @@ static int phytium_can_plat_probe(struct platform_device *pdev) platform_set_drvdata(pdev, cdev->net); - pm_runtime_enable(cdev->dev); + if (!pm_runtime_enabled(cdev->dev)) + pm_runtime_enable(cdev->dev); + ret = pm_runtime_get_sync(cdev->dev); + if (ret < 0) { + netdev_err(cdev->net, "%s: pm_runtime_get failed(%d)\n", + __func__, ret); + goto out_runtime_disable; + } + ret = phytium_can_register(cdev); if (ret) goto out_runtime_disable; diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index c3c0c8ca082cab4901058f467413d2315f26d828..40afa7278753092ebade14a5373063b9c9d206e3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -47,8 +47,8 @@ #define STMMAC_CHAN0 0 /* Always supported and default for all chips */ /* These need to be power of two, and >= 4 */ -#define DMA_TX_SIZE 512 -#define DMA_RX_SIZE 512 +#define DMA_TX_SIZE 1024 +#define DMA_RX_SIZE 1024 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1)) #undef FRAME_FILTER_DEBUG diff --git a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c index 6d690678c20e11bf8594729524fafa238bb1c4bb..131563ca72fab3ceb06be53469e7b2e1e83984b1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c +++ b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c @@ -217,6 +217,10 @@ static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len, else norm_set_tx_desc_len_on_ring(p, len); + /* The own bit must be the latest setting done when prepare the + * descriptor and then barrier is needed to make sure that all is coherent. + */ + wmb(); if (tx_own) p->des0 |= cpu_to_le32(TDES0_OWN); } diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index a4485ea0d2b13d34c6c569bf268116d1725b5f43..5025e87997f524f94bea7275f11e043e8b65e5f8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -611,13 +611,11 @@ EXPORT_SYMBOL_GPL(stmmac_probe_config_dt); EXPORT_SYMBOL_GPL(stmmac_remove_config_dt); #ifdef CONFIG_ACPI -/* - * Parse ACPI _DSD to setup AXI register - */ -static struct stmmac_axi * stmmac_axi_setup_acpi(struct platform_device *pdev) +/* Parse ACPI _DSD to setup AXI register */ +static struct stmmac_axi *stmmac_axi_setup_acpi(struct platform_device *pdev) { - struct fwnode_handle *np = dev_fwnode(&(pdev->dev)); - struct stmmac_axi * axi; + struct fwnode_handle *np = dev_fwnode(&pdev->dev); + struct stmmac_axi *axi; axi = devm_kzalloc(&pdev->dev, sizeof(*axi), GFP_KERNEL); if (!axi) @@ -730,7 +728,7 @@ int stmmac_acpi_clock_setup(struct plat_stmmacenet_data *plat, plat->clk_ptp_ref = NULL; } - plat->stmmac_rst = devm_reset_control_get(dev,STMMAC_RESOURCE_NAME); + plat->stmmac_rst = devm_reset_control_get(dev, STMMAC_RESOURCE_NAME); if (IS_ERR(plat->stmmac_rst)) { dev_info(dev, "no reset control found\n"); plat->stmmac_rst = NULL; @@ -753,7 +751,7 @@ stmmac_probe_config_acpi(struct platform_device *pdev, const char **mac) if (!plat) return ERR_PTR(-ENOMEM); - np = dev_fwnode(&(pdev->dev)); + np = dev_fwnode(&pdev->dev); plat->interface = fw_get_phy_mode(np); @@ -769,7 +767,7 @@ stmmac_probe_config_acpi(struct platform_device *pdev, const char **mac) /* "snps,phy-addr" is not a standard property. Mark it as deprecated * and warn of its use. Remove this when PHY node support is added. - */ + */ if (fwnode_property_read_u32(np, "snps,phy-addr", &plat->phy_addr) == 0) dev_warn(&pdev->dev, "snps,phy-addr property is deprecated\n"); @@ -805,10 +803,10 @@ stmmac_probe_config_acpi(struct platform_device *pdev, const char **mac) &plat->multicast_filter_bins); fwnode_property_read_u32(np, "snps,perfect-filter-entries", &plat->unicast_filter_entries); - plat->unicast_filter_entries = dwmac1000_validate_ucast_entries( - plat->unicast_filter_entries); - plat->multicast_filter_bins = dwmac1000_validate_mcast_bins( - plat->multicast_filter_bins); + plat->unicast_filter_entries = + dwmac1000_validate_ucast_entries(plat->unicast_filter_entries); + plat->multicast_filter_bins = + dwmac1000_validate_mcast_bins(plat->multicast_filter_bins); plat->has_gmac = 1; plat->pmt = 1; @@ -839,7 +837,7 @@ stmmac_probe_config_acpi(struct platform_device *pdev, const char **mac) stmmac_mtl_setup_acpi(pdev, plat); - stmmac_acpi_clock_setup(plat,pdev); + stmmac_acpi_clock_setup(plat, pdev); return plat; } diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig index 5e131590056230cb82c54ddaacd771c4195149ac..7c906e2925a96616b35863666fd613283270a6fe 100644 --- a/drivers/of/Kconfig +++ b/drivers/of/Kconfig @@ -107,4 +107,11 @@ config OF_DMA_DEFAULT_COHERENT # arches should select this if DMA is coherent by default for OF devices bool +config OF_CONFIGFS + bool "Device Tree Overlay ConfigFS interface" + select CONFIGFS_FS + select OF_OVERLAY + help + Enable a simple user-space driven DT overlay interface. + endif # OF diff --git a/drivers/of/Makefile b/drivers/of/Makefile index 663a4af0cccd5cc5a91210a9983c1817c5f219ab..b00a95adf5199885c7a0f5e3f8f2722db0ff8b34 100644 --- a/drivers/of/Makefile +++ b/drivers/of/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-y = base.o device.o platform.o property.o obj-$(CONFIG_OF_KOBJ) += kobj.o +obj-$(CONFIG_OF_CONFIGFS) += configfs.o obj-$(CONFIG_OF_DYNAMIC) += dynamic.o obj-$(CONFIG_OF_FLATTREE) += fdt.o obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c new file mode 100644 index 0000000000000000000000000000000000000000..ac04301dabe134ee007d733766b07d1abb600b50 --- /dev/null +++ b/drivers/of/configfs.c @@ -0,0 +1,277 @@ +/* + * Configfs entries for device-tree + * + * Copyright (C) 2013 - Pantelis Antoniou + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "of_private.h" + +struct cfs_overlay_item { + struct config_item item; + + char path[PATH_MAX]; + + const struct firmware *fw; + struct device_node *overlay; + int ov_id; + + void *dtbo; + int dtbo_size; +}; + +static inline struct cfs_overlay_item *to_cfs_overlay_item( + struct config_item *item) +{ + return item ? container_of(item, struct cfs_overlay_item, item) : NULL; +} + +static ssize_t cfs_overlay_item_path_show(struct config_item *item, + char *page) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + return sprintf(page, "%s\n", overlay->path); +} + +static ssize_t cfs_overlay_item_path_store(struct config_item *item, + const char *page, size_t count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + const char *p = page; + char *s; + int err; + + /* if it's set do not allow changes */ + if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) + return -EPERM; + + /* copy to path buffer (and make sure it's always zero terminated */ + count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p); + overlay->path[sizeof(overlay->path) - 1] = '\0'; + + /* strip trailing newlines */ + s = overlay->path + strlen(overlay->path); + while (s > overlay->path && *--s == '\n') + *s = '\0'; + + pr_debug("%s: path is '%s'\n", __func__, overlay->path); + + err = request_firmware(&overlay->fw, overlay->path, NULL); + if (err != 0) + goto out_err; + + err = of_overlay_fdt_apply((void *)overlay->fw->data, + (u32)overlay->fw->size, &overlay->ov_id); + if (err != 0) + goto out_err; + + return count; + +out_err: + + release_firmware(overlay->fw); + overlay->fw = NULL; + + overlay->path[0] = '\0'; + return err; +} + +static ssize_t cfs_overlay_item_status_show(struct config_item *item, + char *page) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + return sprintf(page, "%s\n", + overlay->ov_id > 0 ? "applied" : "unapplied"); +} + +CONFIGFS_ATTR(cfs_overlay_item_, path); +CONFIGFS_ATTR_RO(cfs_overlay_item_, status); + +static struct configfs_attribute *cfs_overlay_attrs[] = { + &cfs_overlay_item_attr_path, + &cfs_overlay_item_attr_status, + NULL, +}; + +ssize_t cfs_overlay_item_dtbo_read(struct config_item *item, + void *buf, size_t max_count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + pr_debug("%s: buf=%p max_count=%zu\n", __func__, + buf, max_count); + + if (overlay->dtbo == NULL) + return 0; + + /* copy if buffer provided */ + if (buf != NULL) { + /* the buffer must be large enough */ + if (overlay->dtbo_size > max_count) + return -ENOSPC; + + memcpy(buf, overlay->dtbo, overlay->dtbo_size); + } + + return overlay->dtbo_size; +} + +ssize_t cfs_overlay_item_dtbo_write(struct config_item *item, + const void *buf, size_t count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + int err; + + /* if it's set do not allow changes */ + if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) + return -EPERM; + + /* copy the contents */ + overlay->dtbo = kmemdup(buf, count, GFP_KERNEL); + if (overlay->dtbo == NULL) + return -ENOMEM; + + overlay->dtbo_size = count; + + err = of_overlay_fdt_apply(overlay->dtbo, overlay->dtbo_size, + &overlay->ov_id); + if (err != 0) + goto out_err; + + return count; + +out_err: + kfree(overlay->dtbo); + overlay->dtbo = NULL; + overlay->dtbo_size = 0; + overlay->ov_id = 0; + + return err; +} + +CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M); + +static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = { + &cfs_overlay_item_attr_dtbo, + NULL, +}; + +static void cfs_overlay_release(struct config_item *item) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + if (overlay->ov_id > 0) + of_overlay_remove(&overlay->ov_id); + if (overlay->fw) + release_firmware(overlay->fw); + /* kfree with NULL is safe */ + kfree(overlay->dtbo); + kfree(overlay); +} + +static struct configfs_item_operations cfs_overlay_item_ops = { + .release = cfs_overlay_release, +}; + +static struct config_item_type cfs_overlay_type = { + .ct_item_ops = &cfs_overlay_item_ops, + .ct_attrs = cfs_overlay_attrs, + .ct_bin_attrs = cfs_overlay_bin_attrs, + .ct_owner = THIS_MODULE, +}; + +static struct config_item *cfs_overlay_group_make_item( + struct config_group *group, const char *name) +{ + struct cfs_overlay_item *overlay; + + overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); + if (!overlay) + return ERR_PTR(-ENOMEM); + + config_item_init_type_name(&overlay->item, name, &cfs_overlay_type); + return &overlay->item; +} + +static void cfs_overlay_group_drop_item(struct config_group *group, + struct config_item *item) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + config_item_put(&overlay->item); +} + +static struct configfs_group_operations overlays_ops = { + .make_item = cfs_overlay_group_make_item, + .drop_item = cfs_overlay_group_drop_item, +}; + +static struct config_item_type overlays_type = { + .ct_group_ops = &overlays_ops, + .ct_owner = THIS_MODULE, +}; + +static struct configfs_group_operations of_cfs_ops = { + /* empty - we don't allow anything to be created */ +}; + +static struct config_item_type of_cfs_type = { + .ct_group_ops = &of_cfs_ops, + .ct_owner = THIS_MODULE, +}; + +struct config_group of_cfs_overlay_group; + +static struct configfs_subsystem of_cfs_subsys = { + .su_group = { + .cg_item = { + .ci_namebuf = "device-tree", + .ci_type = &of_cfs_type, + }, + }, + .su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex), +}; + +static int __init of_cfs_init(void) +{ + int ret; + + pr_info("%s\n", __func__); + + config_group_init(&of_cfs_subsys.su_group); + config_group_init_type_name(&of_cfs_overlay_group, "overlays", + &overlays_type); + configfs_add_default_group(&of_cfs_overlay_group, + &of_cfs_subsys.su_group); + + ret = configfs_register_subsystem(&of_cfs_subsys); + if (ret != 0) { + pr_err("%s: failed to register subsys\n", __func__); + goto out; + } + pr_info("%s: OK\n", __func__); +out: + return ret; +} +late_initcall(of_cfs_init); diff --git a/drivers/pci/controller/pcie-phytium-ep.c b/drivers/pci/controller/pcie-phytium-ep.c index 0b6effe8865b48ac790bea28537279a3d9d21cd7..545d987ec001398b5fc0d3a9a3a7ff79ea02f622 100644 --- a/drivers/pci/controller/pcie-phytium-ep.c +++ b/drivers/pci/controller/pcie-phytium-ep.c @@ -2,7 +2,7 @@ /* * Phytium PCIe Endpoint controller driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -467,4 +467,4 @@ module_platform_driver(phytium_pcie_ep_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Yang Xun "); -MODULE_DESCRIPTION("Phytium Pcie Controller Endpoint driver"); +MODULE_DESCRIPTION("Phytium PCIe Controller Endpoint driver"); diff --git a/drivers/pci/controller/pcie-phytium-ep.h b/drivers/pci/controller/pcie-phytium-ep.h index bfdc062b165fad15d44bbdf40d1fb1ce6f63cc52..a3768558d58ad086c87cc807a8fa03ef0a3f8273 100644 --- a/drivers/pci/controller/pcie-phytium-ep.h +++ b/drivers/pci/controller/pcie-phytium-ep.h @@ -2,7 +2,7 @@ /* * Phytium pcie endpoint driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PCIE_PHYTIUM_EP_H__ diff --git a/drivers/pci/controller/pcie-phytium-register.h b/drivers/pci/controller/pcie-phytium-register.h index 7dc181b4b1822d3189a92a14995cc826488dbac0..59593956bae7ae71c1a91c8fd63471ab47e29fdc 100644 --- a/drivers/pci/controller/pcie-phytium-register.h +++ b/drivers/pci/controller/pcie-phytium-register.h @@ -2,7 +2,7 @@ /* * Phytium pcie endpoint driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PCIE_PHYTIUM_REGISTER_H__ diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index f65800d63856be1125bd4c6e2dabce81c2f96977..4bcb765087636aa92b34a7cbc9a23ffd53ee79a0 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -597,11 +597,11 @@ static int msi_verify_entries(struct pci_dev *dev) struct msi_desc *entry; for_each_pci_msi_entry(entry, dev) { - if (!dev->no_64bit_msi || !entry->msg.address_hi) - continue; - pci_err(dev, "Device has broken 64-bit MSI but arch" - " tried to assign one above 4G\n"); - return -EIO; + if (entry->msg.address_hi && dev->no_64bit_msi) { + pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n", + entry->msg.address_hi, entry->msg.address_lo); + return -EIO; + } } return 0; } diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 113b7bdf86dd92f446d352f1780c2e68896c129b..e7e78afe2892110d357aaafdfc295e0936e0d58a 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1563,6 +1563,8 @@ static u8 pci_hdr_type(struct pci_dev *dev) static void pci_msi_setup_pci_dev(struct pci_dev *dev) { + u16 ctrl; + /* * Disable the MSI hardware to avoid screaming interrupts * during boot. This is the power on reset default so @@ -1572,6 +1574,10 @@ static void pci_msi_setup_pci_dev(struct pci_dev *dev) if (dev->msi_cap) pci_msi_set_enable(dev, 0); + pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl); + if (!(ctrl & PCI_MSI_FLAGS_64BIT)) + dev->no_64bit_msi = 1; + dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); if (dev->msix_cap) pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 9a6271fdfb8d5490bd0db326f2c9d4b640b7726c..a1707065150564b5ec5f2338efd2f3819bc8a69d 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4798,6 +4798,7 @@ static const struct pci_dev_acs_enabled { /* Broadcom multi-function device */ { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, + { PCI_VENDOR_ID_PHYTIUM, 0xDC01, pci_quirk_xgene_acs}, { 0 } }; diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 87c8190de622fe1c290c93b1495113b0a7677496..613dcc4f552bbe42bf26298ef671f4242e05f163 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -582,6 +582,9 @@ static void pci_setup_bridge_io(struct pci_dev *bridge) u8 io_base_lo, io_limit_lo; u16 l; u32 io_upper16; +#ifdef CONFIG_ARCH_PHYTIUM + u32 io_base_limit = 0; +#endif io_mask = PCI_IO_RANGE_MASK; if (bridge->io_window_1k) @@ -609,6 +612,19 @@ static void pci_setup_bridge_io(struct pci_dev *bridge) pci_write_config_word(bridge, PCI_IO_BASE, l); /* Update upper 16 bits of I/O base/limit. */ pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); + +#ifdef CONFIG_ARCH_PHYTIUM + if (bridge->dev.parent) { + if (!fwnode_property_read_u32(dev_fwnode(bridge->dev.parent), + "io-upper", &io_base_limit)) + pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_base_limit); + } + if (bridge->dev.parent->parent) { + if (!fwnode_property_read_u32(dev_fwnode(bridge->dev.parent->parent), + "io-upper", &io_base_limit)) + pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_base_limit); + } +#endif } static void pci_setup_bridge_mmio(struct pci_dev *bridge) diff --git a/drivers/pwm/pwm-phytium.c b/drivers/pwm/pwm-phytium.c index 76ddf5d1816131d90b7742e2603b5a1ea96eb576..10b74e13ccb65dc10628f395c8f1c550a7039a9a 100644 --- a/drivers/pwm/pwm-phytium.c +++ b/drivers/pwm/pwm-phytium.c @@ -2,7 +2,7 @@ /* * Phytium PWM driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/remoteproc/homo_remoteproc.c b/drivers/remoteproc/homo_remoteproc.c index 5b3588b368a2d9a60d0632238321612ba5e12f35..8de3184987ec82ed3f885498601ac35a6635f157 100644 --- a/drivers/remoteproc/homo_remoteproc.c +++ b/drivers/remoteproc/homo_remoteproc.c @@ -1,7 +1,7 @@ /* * Homogeneous Remote Processor Control Driver * - * Copyright (C) 2022 Phytium Technology Co., Ltd. - All Rights Reserved + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * Author: Shaojun Yang * * This program is free software; you can redistribute it and/or modify it under the terms diff --git a/drivers/scsi/megaraid/megaraid_sas.h b/drivers/scsi/megaraid/megaraid_sas.h index 67d356d84717631eb7f1c85726a6eff334e2da7f..9064a3cf583f6ab1ced9a52d0271ec31bc817399 100644 --- a/drivers/scsi/megaraid/megaraid_sas.h +++ b/drivers/scsi/megaraid/megaraid_sas.h @@ -62,7 +62,10 @@ #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C - +#define PCI_DEVICE_ID_LSI_AERO_10E1 0x10e1 +#define PCI_DEVICE_ID_LSI_AERO_10E2 0x10e2 +#define PCI_DEVICE_ID_LSI_AERO_10E5 0x10e5 +#define PCI_DEVICE_ID_LSI_AERO_10E6 0x10e6 /* * Intel HBA SSDIDs */ diff --git a/drivers/scsi/megaraid/megaraid_sas_base.c b/drivers/scsi/megaraid/megaraid_sas_base.c index 8877a21102f1dd486446aa36d72557d71787bfcc..f2af75f7d0a0a24e400461a83fd5433664536671 100644 --- a/drivers/scsi/megaraid/megaraid_sas_base.c +++ b/drivers/scsi/megaraid/megaraid_sas_base.c @@ -165,6 +165,10 @@ static struct pci_device_id megasas_pci_table[] = { {PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_TOMCAT)}, {PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_VENTURA_4PORT)}, {PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_CRUSADER_4PORT)}, + {PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_AERO_10E1)}, + {PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_AERO_10E2)}, + {PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_AERO_10E5)}, + {PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_AERO_10E6)}, {} }; @@ -6138,6 +6142,10 @@ static inline void megasas_set_adapter_type(struct megasas_instance *instance) instance->adapter_type = MFI_SERIES; } else { switch (instance->pdev->device) { + case PCI_DEVICE_ID_LSI_AERO_10E1: + case PCI_DEVICE_ID_LSI_AERO_10E2: + case PCI_DEVICE_ID_LSI_AERO_10E5: + case PCI_DEVICE_ID_LSI_AERO_10E6: case PCI_DEVICE_ID_LSI_VENTURA: case PCI_DEVICE_ID_LSI_CRUSADER: case PCI_DEVICE_ID_LSI_HARPOON: @@ -6490,6 +6498,12 @@ static int megasas_probe_one(struct pci_dev *pdev, struct Scsi_Host *host; struct megasas_instance *instance; u16 control = 0; + switch (pdev->device) { + case PCI_DEVICE_ID_LSI_AERO_10E1: + case PCI_DEVICE_ID_LSI_AERO_10E5: + dev_info(&pdev->dev, "Adapter is in configurable secure mode\n"); + break; + } /* Reset MSI-X in the kdump kernel */ if (reset_devices) { diff --git a/drivers/spi/spi-phytium-pci.c b/drivers/spi/spi-phytium-pci.c index ab312ef1024854c1a9162e1e9826490509391671..f6bec235442bba3506acca6969fcf4c3dd6b68d3 100644 --- a/drivers/spi/spi-phytium-pci.c +++ b/drivers/spi/spi-phytium-pci.c @@ -2,7 +2,7 @@ /* * Phytium SPI core controller PCI driver. * - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. * * Derived from drivers/spi/spi-dw-pci.c * Copyright (c) 2009, 2014 Intel Corporation. diff --git a/drivers/spi/spi-phytium-plat.c b/drivers/spi/spi-phytium-plat.c index dd4d1a9e6a12f641b2a92f565457907dddeb0578..6993741161a99eaa0361f301d8c9457b70dc9b39 100644 --- a/drivers/spi/spi-phytium-plat.c +++ b/drivers/spi/spi-phytium-plat.c @@ -2,7 +2,7 @@ /* * Phytium SPI core controller platform driver. * - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. * * Derived from drivers/spi/spi-dw-pci.c * Copyright (c) 2009, 2014 Intel Corporation. @@ -29,8 +29,14 @@ #define DRIVER_NAME "phytium_spi" +struct phytium_spi_clk { + struct phytium_spi fts; + struct clk *clk; +}; + static int phytium_spi_probe(struct platform_device *pdev) { + struct phytium_spi_clk *ftsc; struct phytium_spi *fts; struct resource *mem; int ret; @@ -39,11 +45,13 @@ static int phytium_spi_probe(struct platform_device *pdev) int global_cs; int i; - fts = devm_kzalloc(&pdev->dev, sizeof(struct phytium_spi), + ftsc = devm_kzalloc(&pdev->dev, sizeof(struct phytium_spi_clk), GFP_KERNEL); - if (!fts) + if (!ftsc) return -ENOMEM; + fts = &ftsc->fts; + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!mem) { dev_err(&pdev->dev, "no mem resource?\n"); @@ -64,15 +72,15 @@ static int phytium_spi_probe(struct platform_device *pdev) } if (pdev->dev.of_node) { - fts->clk = devm_clk_get(&pdev->dev, NULL); + ftsc->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(fts->clk)) - return PTR_ERR(fts->clk); - ret = clk_prepare_enable(fts->clk); + if (IS_ERR(ftsc->clk)) + return PTR_ERR(ftsc->clk); + ret = clk_prepare_enable(ftsc->clk); if (ret) return ret; - fts->max_freq = clk_get_rate(fts->clk); + fts->max_freq = clk_get_rate(ftsc->clk); } else if (has_acpi_companion(&pdev->dev)) { fts->max_freq = 48000000; } @@ -103,7 +111,7 @@ static int phytium_spi_probe(struct platform_device *pdev) goto out; } } - } else if(has_acpi_companion(&pdev->dev)) { + } else if (has_acpi_companion(&pdev->dev)) { int n; int *cs; struct gpio_desc *gpiod; @@ -142,20 +150,20 @@ static int phytium_spi_probe(struct platform_device *pdev) if (ret) goto out; - platform_set_drvdata(pdev, fts); + platform_set_drvdata(pdev, ftsc); return 0; out: - clk_disable_unprepare(fts->clk); + clk_disable_unprepare(ftsc->clk); return ret; } static int phytium_spi_remove(struct platform_device *pdev) { - struct phytium_spi *fts = platform_get_drvdata(pdev); + struct phytium_spi_clk *ftsc = platform_get_drvdata(pdev); - phytium_spi_remove_host(fts); - clk_disable_unprepare(fts->clk); + phytium_spi_remove_host(&ftsc->fts); + clk_disable_unprepare(ftsc->clk); return 0; } @@ -163,16 +171,16 @@ static int phytium_spi_remove(struct platform_device *pdev) #ifdef CONFIG_PM_SLEEP static int spi_suspend(struct device *dev) { - struct phytium_spi *fts = dev_get_drvdata(dev); + struct phytium_spi_clk *ftsc = dev_get_drvdata(dev); - return phytium_spi_suspend_host(fts); + return phytium_spi_suspend_host(&ftsc->fts); } static int spi_resume(struct device *dev) { - struct phytium_spi *fts = dev_get_drvdata(dev); + struct phytium_spi_clk *ftsc = dev_get_drvdata(dev); - return phytium_spi_resume_host(fts); + return phytium_spi_resume_host(&ftsc->fts); } #endif diff --git a/drivers/spi/spi-phytium.c b/drivers/spi/spi-phytium.c index c8e1d9c78f3b67446a6c070c6242954a0c5271e4..e185aafb99af59212005c62fca6d57a990756da2 100644 --- a/drivers/spi/spi-phytium.c +++ b/drivers/spi/spi-phytium.c @@ -1,7 +1,7 @@ /* * Phytium SPI core controller driver. * - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. * * Derived from drivers/spi/spi-dw-pci.c * Copyright (c) 2009, 2014 Intel Corporation. @@ -417,6 +417,8 @@ int phytium_spi_add_host(struct device *dev, struct phytium_spi *fts) fts->dma_addr = (dma_addr_t)(fts->paddr + DR); snprintf(fts->name, sizeof(fts->name), "phytium_spi%d", fts->bus_num); + spi_hw_init(dev, fts); + ret = request_irq(fts->irq, phytium_spi_irq, IRQF_SHARED, fts->name, master); if (ret < 0) { dev_err(dev, "can not get IRQ\n"); @@ -438,9 +440,6 @@ int phytium_spi_add_host(struct device *dev, struct phytium_spi *fts) master->flags = SPI_MASTER_GPIO_SS; master->cs_gpios = fts->cs; - spi_hw_init(dev, fts); - - if (fts->dma_ops && fts->dma_ops->dma_init) { ret = fts->dma_ops->dma_init(dev, fts); if (ret) { diff --git a/drivers/spi/spi-phytium.h b/drivers/spi/spi-phytium.h index 77b90ae44f78d1493a6e303c0596c6e1e8ae6e06..c8ec40435e444ce764aaa7e36529345e9baa6104 100644 --- a/drivers/spi/spi-phytium.h +++ b/drivers/spi/spi-phytium.h @@ -2,7 +2,7 @@ /* * Phytium SPI controller driver. * - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. */ #ifndef PHYTIUM_SPI_HEADER_H #define PHYTIUM_SPI_HEADER_H diff --git a/drivers/tty/serial/phytium-uart.c b/drivers/tty/serial/phytium-uart.c index 6166e82c4eb0d4a67d30ed312a50c0bc05889f84..8a5153550734077148ae0f3ff432699fbb93b555 100644 --- a/drivers/tty/serial/phytium-uart.c +++ b/drivers/tty/serial/phytium-uart.c @@ -2,7 +2,7 @@ /* * Driver for Phytium PCI UART controller * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. * * Derived from drivers/tty/serial/amba-pl011.c * Copyright 1999 ARM Limited diff --git a/drivers/usb/phytium/dma.c b/drivers/usb/phytium/dma.c index 2e0d6df3eb344e386c649f2fc2dab7e774969137..e23f01f7c1729077c4006c518d3ef546573b50bd 100644 --- a/drivers/usb/phytium/dma.c +++ b/drivers/usb/phytium/dma.c @@ -416,7 +416,7 @@ static int32_t phytium_dma_channelRelease(struct DMA_CONTROLLER *priv, struct DM } } - channel->status = DMA_STATUS_UNKNOW; + channel->status = DMA_STATUS_UNKNOWN; return 0; } @@ -646,7 +646,7 @@ static enum DMA_Status phytium_dma_getChannelStatus(struct DMA_CONTROLLER *priv, uint32_t ep_cmd, ep_sts; if (!priv || !channel) - return DMA_STATUS_UNKNOW; + return DMA_STATUS_UNKNOWN; if (channel->status >= DMA_STATUS_BUSY) { phytium_write32(&priv->regs->ep_sel, channel->isDirTx | channel->hwUsbEppNum); @@ -692,7 +692,7 @@ static int32_t phytium_dma_channelAbort(struct DMA_CONTROLLER *priv, struct DMA_ } } } - if (channel->status != DMA_STATUS_UNKNOW) + if (channel->status != DMA_STATUS_UNKNOWN) channel->status = DMA_STATUS_FREE; return 0; diff --git a/drivers/usb/phytium/dma.h b/drivers/usb/phytium/dma.h index 073a078c1289625ce4bec236498aa49e651c7375..793d53943122491e4d88ee00a1fbbc398949e35b 100644 --- a/drivers/usb/phytium/dma.h +++ b/drivers/usb/phytium/dma.h @@ -61,7 +61,7 @@ struct DMA_Trb { }; enum DMA_Status { - DMA_STATUS_UNKNOW, + DMA_STATUS_UNKNOWN, DMA_STATUS_FREE, DMA_STATUS_ABORT, DMA_STATUS_BUSY, diff --git a/drivers/usb/phytium/host.c b/drivers/usb/phytium/host.c index 75bcaa2a71477f2fc727769b95b897ea6808fa81..73059131bf3f68d43b718f3354fb3c48098df5e0 100644 --- a/drivers/usb/phytium/host.c +++ b/drivers/usb/phytium/host.c @@ -11,7 +11,7 @@ #define DRV_NAME "phytium_usb" -#define HOST_GENERIC_EP_CONTROLL 0x00 +#define HOST_GENERIC_EP_CONTROL 0x00 #define HOST_GENERIC_EP_ISOC 0x01 #define HOST_GENERIC_EP_BULK 0x02 #define HOST_GENERIC_EP_INT 0x03 @@ -724,7 +724,7 @@ static void hostStartReq(struct HOST_CTRL *priv, struct HOST_REQ *req) case USB_ENDPOINT_XFER_CONTROL: usbReq = getNextReq(hostEp); - priv->in[HOST_GENERIC_EP_CONTROLL].scheduledUsbHEp = hostEp; + priv->in[HOST_GENERIC_EP_CONTROL].scheduledUsbHEp = hostEp; priv->ep0State = HOST_EP0_STAGE_SETUP; hostEpPriv->currentHwEp = hostEpPriv->genericHwEp; hostEpPriv->genericHwEp->scheduledUsbHEp = hostEp; @@ -778,6 +778,38 @@ static void hostStartReq(struct HOST_CTRL *priv, struct HOST_REQ *req) } } +static void abortTransfer(struct HOST_CTRL *priv, + struct HOST_REQ *usbReq, struct HostEp *hwEp) +{ + struct HOST_EP *usbEp; + struct HOST_EP_PRIV *usbHEpPriv; + uint32_t status; + + if (!priv || !usbReq || !hwEp || !hwEp->scheduledUsbHEp) + return; + + usbEp = hwEp->scheduledUsbHEp; + usbHEpPriv = (struct HOST_EP_PRIV *)usbEp->hcPriv; + if (!usbHEpPriv) + return; + + status = (usbReq->status == EINPROGRESS) ? 0 : usbReq->status; + givebackRequest(priv, usbReq, status); + + if (list_empty(&usbEp->reqList)) { + usbHEpPriv->epIsReady = 0; + usbHEpPriv->currentHwEp = NULL; + hwEp->scheduledUsbHEp = NULL; + + if (hwEp->channel) { + priv->dmaDrv->dma_channelRelease(priv->dmaController, hwEp->channel); + hwEp->channel = NULL; + } + + if (usb_endpoint_xfer_int(&usbEp->desc)) + list_del(&usbHEpPriv->node); + } +} static void scheduleNextTransfer(struct HOST_CTRL *priv, struct HOST_REQ *usbReq, struct HostEp *hwEp) @@ -877,7 +909,7 @@ static int32_t hostEp0Irq(struct HOST_CTRL *priv, uint8_t isIn) if (!priv) return -EINVAL; - hwEp = isIn ? &priv->in[HOST_GENERIC_EP_CONTROLL] : &priv->out[HOST_GENERIC_EP_CONTROLL]; + hwEp = isIn ? &priv->in[HOST_GENERIC_EP_CONTROL] : &priv->out[HOST_GENERIC_EP_CONTROL]; hostEp = hwEp->scheduledUsbHEp; usbHEpPriv = (struct HOST_EP_PRIV *)hostEp->hcPriv; @@ -913,13 +945,13 @@ static int32_t hostEp0Irq(struct HOST_CTRL *priv, uint8_t isIn) switch (priv->ep0State) { case HOST_EP0_STAGE_IN: pr_debug("Ep0 Data IN\n"); - usbHEpPriv->currentHwEp = &priv->out[HOST_GENERIC_EP_CONTROLL]; + usbHEpPriv->currentHwEp = &priv->out[HOST_GENERIC_EP_CONTROL]; usbReq->actualLength = length; priv->ep0State = HOST_EP0_STAGE_STATUSOUT; break; case HOST_EP0_STAGE_OUT: pr_debug("Ep0 Data OUT\n"); - usbHEpPriv->currentHwEp = &priv->in[HOST_GENERIC_EP_CONTROLL]; + usbHEpPriv->currentHwEp = &priv->in[HOST_GENERIC_EP_CONTROL]; usbReq->actualLength = length; priv->ep0State = HOST_EP0_STAGE_STATUSIN; break; @@ -928,12 +960,12 @@ static int32_t hostEp0Irq(struct HOST_CTRL *priv, uint8_t isIn) if (!usbReq->setup->wLength) { pr_debug("EP0_STAGE_STATUSIN\n"); priv->ep0State = HOST_EP0_STAGE_STATUSIN; - usbHEpPriv->currentHwEp = &priv->in[HOST_GENERIC_EP_CONTROLL]; + usbHEpPriv->currentHwEp = &priv->in[HOST_GENERIC_EP_CONTROL]; break; } else if (usbReq->setup->bRequestType & USB_DIR_IN) { pr_debug("EP0_STAGE_STAGE_IN\n"); priv->ep0State = HOST_EP0_STAGE_IN; - usbHEpPriv->currentHwEp = &priv->in[HOST_GENERIC_EP_CONTROLL]; + usbHEpPriv->currentHwEp = &priv->in[HOST_GENERIC_EP_CONTROL]; nextStage = 1; break; } @@ -1917,11 +1949,58 @@ int32_t hostEpDisable(struct HOST_CTRL *priv, struct HOST_EP *ep) return 0; } +unsigned int get_endpoint_interval(struct usb_endpoint_descriptor desc, int speed) +{ + unsigned int interval = 0; + + switch (speed) { + case USB_SPEED_HIGH: + if (usb_endpoint_xfer_control(&desc) || usb_endpoint_xfer_bulk(&desc)) { + if (desc.bInterval == 0) + return interval; + interval = fls(desc.bInterval) - 1; + interval = clamp_val(interval, 0, 15); + interval = 1 << interval; + if (interval != desc.bInterval) + pr_debug("rounding to %d microframes, desc %d microframes\n", + interval, desc.bInterval); + break; + } + + if (usb_endpoint_xfer_isoc(&desc) || usb_endpoint_xfer_int(&desc)) { + interval = clamp_val(desc.bInterval, 1, 16) - 1; + interval = 1 << interval; + if (interval != desc.bInterval - 1) + pr_debug("rounding to %d %sframes\n", interval, + speed == USB_SPEED_FULL ? "" : "micro"); + } + break; + case USB_SPEED_FULL: + if (usb_endpoint_xfer_isoc(&desc)) { + interval = clamp_val(desc.bInterval, 1, 16); + if (interval != desc.bInterval) + pr_debug("rounding to %d %sframes\n", 1 << interval, + speed == USB_SPEED_FULL ? "" : "micro"); + break; + } + /* fall through */ + case USB_SPEED_LOW: + if (usb_endpoint_xfer_int(&desc) || usb_endpoint_xfer_isoc(&desc)) { + interval = fls(desc.bInterval * 8) - 1; + interval = clamp_val(interval, 3, 10); + if ((1 << interval) != desc.bInterval * 8) + pr_debug("rounding to %d microframes, desc %d microframes\n", + 1 << interval, desc.bInterval); + } + } + + return interval; +} + int32_t hostReqQueue(struct HOST_CTRL *priv, struct HOST_REQ *req) { struct HOST_EP_PRIV *hostEpPriv; struct list_head *hEpQueue = NULL; - uint32_t interval = 0; uint8_t idleQueue = 0; if (!priv || !req) @@ -1946,6 +2025,8 @@ int32_t hostReqQueue(struct HOST_CTRL *priv, struct HOST_REQ *req) hostEpPriv->usbHEp = req->usbEp; hostEpPriv->isIn = req->epIsIn; + hostEpPriv->frame = get_endpoint_interval(req->usbEp->desc, req->usbDev->speed); + hostEpPriv->interval = hostEpPriv->frame; switch (usb_endpoint_type(&req->usbEp->desc)) { case USB_ENDPOINT_XFER_CONTROL: hostEpPriv->isIn = 0; @@ -1958,41 +2039,14 @@ int32_t hostReqQueue(struct HOST_CTRL *priv, struct HOST_REQ *req) hostEpPriv->type = USB_ENDPOINT_XFER_BULK; break; case USB_ENDPOINT_XFER_INT: - if (req->usbDev->speed < USB_SPEED_FULL) - interval = (req->usbEp->desc.bInterval < 10) ? 10 : req->usbEp->desc.bInterval; - else if (req->usbDev->speed == USB_SPEED_FULL) - interval = (req->usbEp->desc.bInterval < 1) ? - 1 : req->usbEp->desc.bInterval; - else { - if (req->usbEp->desc.bInterval < 1) - interval = 1; - else if (req->usbEp->desc.bInterval > 16) - interval = 16; - else - interval = req->usbEp->desc.bInterval; - - interval = 1 << (interval - 1); - } hEpQueue = hostEpPriv->isIn ? &priv->intInHEpQueue[req->epNum - 1] : &priv->intOutHEpQueue[req->epNum - 1]; hostEpPriv->type = USB_ENDPOINT_XFER_INT; - hostEpPriv->frame = interval; - hostEpPriv->interval = interval; break; case USB_ENDPOINT_XFER_ISOC: - if (req->usbEp->desc.bInterval < 1) - interval = 1; - else if (req->usbEp->desc.bInterval > 16) - interval = 16; - else - interval = req->usbEp->desc.bInterval; - - interval = 1 << (interval - 1); hEpQueue = hostEpPriv->isIn ? &priv->isoInHEpQueue[req->epNum - 1] : &priv->isoOutHEpQueue[req->epNum - 1]; hostEpPriv->type = USB_ENDPOINT_XFER_ISOC; - hostEpPriv->frame = interval; - hostEpPriv->interval = interval; break; default: break; @@ -2029,8 +2083,6 @@ static int abortActuallyUsbRequest(struct HOST_CTRL *priv, { struct HOST_EP_PRIV *usbEpPriv; struct HostEp *hostEp; - uint16_t rxerrien = 0; - uint16_t txerrien = 0; uint8_t rxcon, txcon; if (!priv || !req || !usbEp) @@ -2040,31 +2092,20 @@ static int abortActuallyUsbRequest(struct HOST_CTRL *priv, hostEp = usbEpPriv->currentHwEp; usbEpPriv->transferFinished = 1; - if (hostEp->isInEp) { if (hostEp->hwEpNum) { rxcon = phytium_read8(&priv->regs->ep[hostEp->hwEpNum - 1].rxcon); rxcon = rxcon & (~BIT(7)); phytium_write8(&priv->regs->ep[hostEp->hwEpNum - 1].rxcon, rxcon); } - rxerrien = phytium_read16(&priv->regs->rxerrien); - rxerrien &= ~(1 << hostEp->hwEpNum); - phytium_write16(&priv->regs->rxerrien, rxerrien); - phytium_write8(&priv->regs->endprst, ENDPRST_FIFORST | - ENDPRST_IO_TX | hostEp->hwEpNum); } else { if (hostEp->hwEpNum) { txcon = phytium_read8(&priv->regs->ep[hostEp->hwEpNum - 1].txcon); txcon = txcon & (~BIT(7)); phytium_write8(&priv->regs->ep[hostEp->hwEpNum - 1].txcon, txcon); } - txerrien = phytium_read16(&priv->regs->txerrien); - txerrien &= ~(1 << hostEp->hwEpNum); - phytium_write16(&priv->regs->txerrien, txerrien); - phytium_write8(&priv->regs->endprst, ENDPRST_FIFORST | hostEp->hwEpNum); } - - scheduleNextTransfer(priv, req, hostEp); + abortTransfer(priv, req, hostEp); return 0; } diff --git a/drivers/w1/masters/phytium_w1.c b/drivers/w1/masters/phytium_w1.c index 9a84802ac2fb7045d6defe935f23eb178d393edc..6a7a7fe312adcd8f9d599a0b1c952595c8496866 100644 --- a/drivers/w1/masters/phytium_w1.c +++ b/drivers/w1/masters/phytium_w1.c @@ -2,7 +2,7 @@ /* * drivers/w1/masters/phytium_w1m.c * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index f4c9fc0fc7555a226a7607758b816b1c9486d5f6..8247a4934fd8a0982dd7df422e383421b40630f3 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -140,6 +140,7 @@ struct scmi_power_ops { struct scmi_sensor_info { u32 id; u8 type; + s8 scale; char name[SCMI_MAX_STR_SIZE]; }; diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h index 935f53b9b77178f3c04976af9545ae950c2fb2d1..917117c8f6907d0e92c8200e1873c2cbb2fd3b40 100644 --- a/include/sound/hdaudio.h +++ b/include/sound/hdaudio.h @@ -354,7 +354,7 @@ struct hdac_bus { bool align_bdle_4k:1; /* BDLE align 4K boundary */ bool reverse_assign:1; /* assign devices in reverse order */ bool corbrp_self_clear:1; /* CORBRP clears itself after reset */ - bool cmd_resend:1; /* command resend */ + bool cmd_resend; /* command resend */ int bdl_pos_adj; /* BDL position adjustment */ diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst index 7301ab5e2e066b458fcadfe47bc2574af769155d..da2af04a6d7da2cd4a324632a281246e0972d54c 100644 --- a/scripts/Makefile.dtbinst +++ b/scripts/Makefile.dtbinst @@ -20,6 +20,7 @@ include scripts/Kbuild.include include $(src)/Makefile dtbinst-files := $(sort $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS), $(dtb-))) +dtboinst-files := $(sort $(dtbo-y) $(if $(CONFIG_OF_ALL_DTBS), $(dtb-))) dtbinst-dirs := $(subdir-y) $(subdir-m) # Helper targets for Installing DTBs into the boot directory @@ -31,10 +32,13 @@ install-dir = $(patsubst $(dtbinst_root)%,$(INSTALL_DTBS_PATH)%,$(obj)) $(dtbinst-files): %.dtb: $(obj)/%.dtb $(call cmd,dtb_install,$(install-dir)) +$(dtboinst-files): %.dtbo: $(obj)/%.dtbo + $(call cmd,dtb_install,$(install-dir)) + $(dtbinst-dirs): $(Q)$(MAKE) $(dtbinst)=$(obj)/$@ -PHONY += $(dtbinst-files) $(dtbinst-dirs) -__dtbs_install: $(dtbinst-files) $(dtbinst-dirs) +PHONY += $(dtbinst-files) $(dtboinst-files) $(dtbinst-dirs) +__dtbs_install: $(dtbinst-files) $(dtboinst-files) $(dtbinst-dirs) .PHONY: $(PHONY) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index a232741e3fd3bdf16594c5ff0e59e30c41cd518a..1d800cbc7ac95bae81158a182f2a2ac30ad14dcd 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -248,6 +248,7 @@ DTC ?= $(objtree)/scripts/dtc/dtc ifeq ($(findstring 1,$(KBUILD_ENABLE_EXTRA_GCC_CHECKS)),) DTC_FLAGS += -Wno-unit_address_vs_reg \ -Wno-unit_address_format \ + -Wno-gpios_property \ -Wno-avoid_unnecessary_addr_size \ -Wno-alias_paths \ -Wno-graph_child_address \ diff --git a/scripts/spdxcheck.py b/scripts/spdxcheck.py index e559c6294c39aef2819637125520a0721b14a95d..b42bcc7f832aae2d5138c9e5d898b2a01285f3eb 100755 --- a/scripts/spdxcheck.py +++ b/scripts/spdxcheck.py @@ -168,7 +168,6 @@ class id_parser(object): self.curline = 0 try: for line in fd: - line = line.decode(locale.getpreferredencoding(False), errors='ignore') self.curline += 1 if self.curline > maxlines: break diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c index 03ab50fd3482470b0eadd5c1e5be583e288c4abe..2def64e1586d8fc9bb2144bef81049f40587e6cd 100644 --- a/sound/pci/hda/hda_controller.c +++ b/sound/pci/hda/hda_controller.c @@ -172,9 +172,8 @@ static int azx_pcm_prepare(struct snd_pcm_substream *substream) struct hda_spdif_out *spdif = snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid); unsigned short ctls = spdif ? spdif->ctls : 0; + struct hda_ft *hda = container_of(chip, struct hda_ft, chip); - struct hda_ft *hda; - hda = container_of(chip, struct hda_ft, chip); hda->substream = substream; trace_azx_pcm_prepare(chip, azx_dev); diff --git a/sound/pci/hda/hda_phytium.c b/sound/pci/hda/hda_phytium.c index 6abe302e7e0b751fb28508ff29c041d4b0c83dd0..bc5282d1d51931e511973209fa9bad9d8020f73d 100644 --- a/sound/pci/hda/hda_phytium.c +++ b/sound/pci/hda/hda_phytium.c @@ -2,7 +2,7 @@ /* * Implementation of primary ALSA driver code base for Phytium HD Audio. * - * Copyright (c) 2018-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2018-2024 Phytium Technology Co., Ltd. */ #include @@ -257,6 +257,37 @@ static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) return 1; /* OK, it's fine */ } +static int hda_ft_dma_configure(struct device *dev) +{ + const struct of_device_id *match_of; + const struct acpi_device_id *match_acpi; + + if (dev->of_node) { + match_of = of_match_device(dev->driver->of_match_table, dev); + if (!match_of) { + dev_err(dev, "Error DT match data is missing\n"); + return -ENODEV; + } + set_dma_ops(dev, NULL); + /* + * Because there is no way to transfer to non-coherent dma in + * of_dma_configure if 'dma-coherent' is described in DT, + * use acpi_dma_configure to alloc dma_ops correctly. + */ + acpi_dma_configure(dev, DEV_DMA_NON_COHERENT); + } else if (has_acpi_companion(dev)) { + match_acpi = acpi_match_device(dev->driver->acpi_match_table, dev); + if (!match_acpi) { + dev_err(dev, "Error ACPI match data is missing\n"); + return -ENODEV; + } + set_dma_ops(dev, NULL); + acpi_dma_configure(dev, DEV_DMA_NON_COHERENT); + } + + return 0; +} + /* The work for pending PCM period updates. */ static void azx_irq_pending_work(struct work_struct *work) { @@ -278,9 +309,9 @@ static void azx_irq_pending_work(struct work_struct *work) spin_lock_irq(&bus->reg_lock); list_for_each_entry(s, &bus->stream_list, list) { struct azx_dev *azx_dev = stream_to_azx_dev(s); + if (!azx_dev->irq_pending || - !s->substream || - !s->running) + !s->substream || !s->running) continue; ok = azx_position_ok(chip, azx_dev); if (ok > 0) { @@ -290,13 +321,14 @@ static void azx_irq_pending_work(struct work_struct *work) spin_lock(&bus->reg_lock); } else if (ok < 0) { pending = 0; /* too early */ - } else + } else { pending++; + } } spin_unlock_irq(&bus->reg_lock); if (!pending) return; - msleep(1); + udelay(1000); } } @@ -309,6 +341,7 @@ static void azx_clear_irq_pending(struct azx *chip) spin_lock_irq(&bus->reg_lock); list_for_each_entry(s, &bus->stream_list, list) { struct azx_dev *azx_dev = stream_to_azx_dev(s); + azx_dev->irq_pending = 0; } spin_unlock_irq(&bus->reg_lock); @@ -402,6 +435,7 @@ static LIST_HEAD(card_list); static void azx_add_card_list(struct azx *chip) { struct hda_ft *hda = container_of(chip, struct hda_ft, chip); + mutex_lock(&card_list_lock); list_add(&hda->list, &card_list); mutex_unlock(&card_list_lock); @@ -410,6 +444,7 @@ static void azx_add_card_list(struct azx *chip) static void azx_del_card_list(struct azx *chip) { struct hda_ft *hda = container_of(chip, struct hda_ft, chip); + mutex_lock(&card_list_lock); list_del_init(&hda->list); mutex_unlock(&card_list_lock); @@ -485,10 +520,11 @@ static int azx_resume(struct device *dev) substream = hda->substream; if(substream->runtime->status->state == SNDRV_PCM_STATE_SUSPENDED){ - substream->runtime->status->state = substream->runtime->status->suspended_state; + substream->runtime->status->state = + substream->runtime->status->suspended_state; err = substream->ops->prepare(substream); if (err < 0) - return err; + return err; } azx_dev = get_azx_dev(substream); @@ -592,7 +628,7 @@ static const struct dev_pm_ops azx_pm = { SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) }; -#define hda_ft_pm &azx_pm +#define hda_ft_pm (&azx_pm) #else #define hda_ft_pm NULL #endif /* CONFIG_PM */ @@ -625,7 +661,7 @@ static int azx_free(struct azx *chip) } if (bus->irq >= 0) { - free_irq(bus->irq, (void*)chip); + free_irq(bus->irq, (void *)chip); bus->irq = -1; } @@ -635,7 +671,7 @@ static int azx_free(struct azx *chip) azx_free_streams(chip); snd_hdac_bus_exit(bus); - if (chip->region_requested){ + if (chip->region_requested) { res = platform_get_resource(pdev, IORESOURCE_MEM, 0); size = resource_size(res); devm_release_mem_region(hddev, res->start, size); @@ -717,6 +753,7 @@ static void check_probe_mask(struct azx *chip, int dev) static void azx_probe_work(struct work_struct *work) { struct hda_ft *hda = container_of(work, struct hda_ft, probe_work); + azx_probe_continue(&hda->chip); } @@ -782,6 +819,11 @@ static int hda_ft_create(struct snd_card *card, struct platform_device *pdev, return err; } + if (chip->driver_type == AZX_DRIVER_NVIDIA) { + dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); + chip->bus.needs_damn_long_delay = 1; + } + err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); if (err < 0) { dev_err(card->dev, "Error creating device [card]!\n"); @@ -849,6 +891,10 @@ static int azx_first_init(struct azx *chip) else chip->align_buffer_size = 1; } + + err = hda_ft_dma_configure(hddev); + if (err < 0) + return err; /* allow 64bit DMA address if supported by H/W */ if (!(gcap & AZX_GCAP_64OK)) @@ -1003,6 +1049,7 @@ static int substream_free_pages(struct azx *chip, struct snd_pcm_substream *substream) { struct azx_dev *azx_dev = get_azx_dev(substream); + mark_runtime_wc(chip, azx_dev, substream, false); return snd_pcm_lib_free_pages(substream); } @@ -1060,7 +1107,7 @@ static int hda_ft_probe(struct platform_device *pdev) return err; } - err = hda_ft_create(card, pdev,dev, driver_flags, &chip); + err = hda_ft_create(card, pdev, dev, driver_flags, &chip); if (err < 0) goto out_free; card->private_data = chip; @@ -1126,7 +1173,7 @@ static int azx_probe_continue(struct azx *chip) snd_hda_set_power_save(&chip->bus, power_save * 1000); if (azx_has_pm_runtime(chip)) - pm_runtime_put_noidle(hddev); + pm_runtime_put_noidle(hddev); return err; out_free: diff --git a/sound/pci/hda/hda_phytium.h b/sound/pci/hda/hda_phytium.h index edca12ec6fa7e36baed78f455367e73d1bfaa497..ec1f3e7f7b9cfa52ca5af33a376214efd2fb7947 100644 --- a/sound/pci/hda/hda_phytium.h +++ b/sound/pci/hda/hda_phytium.h @@ -2,7 +2,7 @@ /* * Implementation of primary ALSA driver code base for Phytium HD Audio. * - * Copyright (c) 2018-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2018-2024 Phytium Technology Co., Ltd. */ #ifndef __SOUND_HDA_PHYTIUM_H__ #define __SOUND_HDA_PHYTIUM_H__ diff --git a/sound/soc/codecs/es8336.c b/sound/soc/codecs/es8336.c index e82c3b5e2a687c6fb0b7fefd363dafefa7f06191..7b3f2fc15e423942391e0b4e37afcfe234f58b63 100644 --- a/sound/soc/codecs/es8336.c +++ b/sound/soc/codecs/es8336.c @@ -3,7 +3,7 @@ * es8336 ALSA SoC audio driver * * Copyright (C) Everest Semiconductor Co.,Ltd - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. */ #include @@ -1011,7 +1011,7 @@ static int es8336_i2c_probe(struct i2c_client *i2c, msecs_to_jiffies(es8336->debounce_time)); } - ret = snd_soc_register_component(&i2c->dev, + ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_es8336, &es8336_dai, 1); @@ -1020,7 +1020,7 @@ static int es8336_i2c_probe(struct i2c_client *i2c, static int es8336_i2c_remove(struct i2c_client *client) { - kfree(i2c_get_clientdata(client)); + return 0; } diff --git a/sound/soc/codecs/es8336.h b/sound/soc/codecs/es8336.h index d9eda8edaf1193ff1d849894907563e832db7620..2bcf67b8a4d27009be71eb1e1e82fe41e53cee27 100644 --- a/sound/soc/codecs/es8336.h +++ b/sound/soc/codecs/es8336.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) Everest Semiconductor Co.,Ltd - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. */ #ifndef _ES8336_H diff --git a/sound/soc/codecs/es8388.c b/sound/soc/codecs/es8388.c index 86d1120d3bb85f1b6f4d02e88bc5bd844afc5bd4..9ddc557328f9cac550cd60cb75570fcd2a4928cc 100644 --- a/sound/soc/codecs/es8388.c +++ b/sound/soc/codecs/es8388.c @@ -2,7 +2,7 @@ /* * es8388.c -- ES8388 ALSA SoC Audio driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. * Author: Yiqun Zhang * * This program is free software; you can redistribute it and/or modify diff --git a/sound/soc/phytium/local.h b/sound/soc/phytium/local.h index 9a9e5a1e1e1ca9d23d5e1050f127e4fd600c878e..753d0ef3a0c398524a707a52e1f58be23932b5b5 100644 --- a/sound/soc/phytium/local.h +++ b/sound/soc/phytium/local.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -13,9 +13,7 @@ #include #include #include -#include #include -#include /* I2S clk setting*/ #define CLK_CFG0 0xc00 @@ -133,6 +131,12 @@ #define azx_stream(dev) (&(dev)->core) +struct i2s_clk_config_data { + int chan_nr; + u32 data_width; + u32 sample_rate; +}; + struct i2sc_bus { struct device *dev; const struct i2s_bus_ops *ops; diff --git a/sound/soc/phytium/phytium_i2s.c b/sound/soc/phytium/phytium_i2s.c old mode 100755 new mode 100644 index 284b130540ffab213f3d1bdbd9eefbe26cfa69d3..67a932617013e0b104870b7a5d360b62b4cb2edb --- a/sound/soc/phytium/phytium_i2s.c +++ b/sound/soc/phytium/phytium_i2s.c @@ -2,7 +2,7 @@ /* * Phytium I2S ASoc driver * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. * * Derived from sound/soc/dwc/dwc-i2s.c * Copyright (C) 2010 ST Microelectronics @@ -1027,11 +1027,11 @@ static int phytium_configure_dai_by_dt(struct i2s_phytium *dev) if (COMP1_TX_ENABLED(comp1)) { idx2 = COMP1_TX_WORDSIZE_0(comp1); - dev->capability |= DWC_I2S_PLAY; + dev->capability |= PHYTIUM_I2S_PLAY; } if (COMP1_RX_ENABLED(comp1)) { idx2 = COMP2_RX_WORDSIZE_0(comp2); - dev->capability |= DWC_I2S_RECORD; + dev->capability |= PHYTIUM_I2S_RECORD; } return 0; @@ -1087,23 +1087,22 @@ static int stream_direction(struct azx *chip, unsigned char index) } -void snd_i2s_stream_init(struct i2sc_bus *bus, struct i2s_stream *azx_dev, +void snd_i2s_stream_init(struct i2sc_bus *bus, struct i2s_stream *stream, int idx, int direction, int tag) { - azx_dev->bus = bus; - azx_dev->sd_addr = bus->remap_addr; + stream->bus = bus; + stream->sd_addr = bus->remap_addr; if (idx == 0) - azx_dev->sd_int_sta_mask = 1 << idx; + stream->sd_int_sta_mask = 1 << idx; else - azx_dev->sd_int_sta_mask = 1 << 8; + stream->sd_int_sta_mask = 1 << 8; - azx_dev->index = idx; - azx_dev->direction = direction; - azx_dev->stream_tag = tag; - - list_add_tail(&azx_dev->list, &bus->stream_list); + stream->index = idx; + stream->direction = direction; + stream->stream_tag = tag; + list_add_tail(&stream->list, &bus->stream_list); } int azx_i2s_init_streams(struct azx *chip) @@ -1329,7 +1328,6 @@ static int phytium_i2s_probe(struct platform_device *pdev) err = i2s_phytium_create(pdev, card_num, &chip, i2s); if (err < 0) return err; - i2s = container_of(chip, struct i2s_phytium, chip); schedule_probe = !chip->disabled; dev_set_drvdata(&pdev->dev, i2s); diff --git a/sound/soc/phytium/pmdk_dp.c b/sound/soc/phytium/pmdk_dp.c old mode 100755 new mode 100644 index 55190bc42450e4297f1baf3674c4adb5e7b20cfc..28ad2efef73103676014162b8825e9249e3120d3 --- a/sound/soc/phytium/pmdk_dp.c +++ b/sound/soc/phytium/pmdk_dp.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -31,27 +31,6 @@ static const struct snd_soc_dapm_route pmdk_dp_audio_map[] = { {"DP", NULL, "TX"}, }; -static struct snd_soc_jack_pin dp0_pins[] = { - { - .pin = "HDMI/DP,pcm=0", - .mask = SND_JACK_LINEOUT, - }, -}; - -static struct snd_soc_jack_pin dp1_pins[] = { - { - .pin = "HDMI/DP,pcm=1", - .mask = SND_JACK_LINEOUT, - }, -}; - -static struct snd_soc_jack_pin dp2_pins[] = { - { - .pin = "HDMI/DP,pcm=2", - .mask = SND_JACK_LINEOUT, - }, -}; - #define SMDK_DAI_FMT (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | \ SND_SOC_DAIFMT_CBS_CFS) @@ -63,9 +42,8 @@ static int pmdk_dp0_init(struct snd_soc_pcm_runtime *runtime) int ret; ret = snd_soc_card_jack_new(card, "HDMI/DP,pcm=0", - SND_JACK_LINEOUT, - &priv->jack0, dp0_pins, - ARRAY_SIZE(dp0_pins)); + SND_JACK_LINEOUT, &priv->jack0, NULL, 0); + if (ret) { dev_err(card->dev, "Jack creation failed %d\n", ret); return ret; @@ -82,9 +60,8 @@ static int pmdk_dp1_init(struct snd_soc_pcm_runtime *runtime) int ret; ret = snd_soc_card_jack_new(card, "HDMI/DP,pcm=1", - SND_JACK_LINEOUT, - &priv->jack1, dp1_pins, - ARRAY_SIZE(dp1_pins)); + SND_JACK_LINEOUT, &priv->jack1, NULL, 0); + if (ret) { dev_err(card->dev, "Jack creation failed %d\n", ret); return ret; @@ -101,9 +78,8 @@ static int pmdk_dp2_init(struct snd_soc_pcm_runtime *runtime) int ret; ret = snd_soc_card_jack_new(card, "HDMI/DP,pcm=2", - SND_JACK_LINEOUT, - &priv->jack2, dp2_pins, - ARRAY_SIZE(dp2_pins)); + SND_JACK_LINEOUT, &priv->jack2, NULL, 0); + if (ret) { dev_err(card->dev, "Jack creation failed %d\n", ret); return ret; diff --git a/sound/soc/phytium/pmdk_es8336.c b/sound/soc/phytium/pmdk_es8336.c index 38919f40694c7f00fe27761b562d441df7da3ce5..c2e7891c0fffa1f2114c10a935e1a80e509ee92f 100644 --- a/sound/soc/phytium/pmdk_es8336.c +++ b/sound/soc/phytium/pmdk_es8336.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -66,7 +66,9 @@ static int pmdk_sound_probe(struct platform_device *pdev) { struct snd_soc_card *card = &pmdk; struct device *dev = &pdev->dev; + card->dev = dev; + return devm_snd_soc_register_card(&pdev->dev, card); } diff --git a/sound/soc/phytium/pmdk_es8388.c b/sound/soc/phytium/pmdk_es8388.c index 0a1bd3b52d3b6f72719423ff7a23cb652911cb8a..3c1d3ee9bfc3d5d41078deacf46cc1abef6d09c2 100644 --- a/sound/soc/phytium/pmdk_es8388.c +++ b/sound/soc/phytium/pmdk_es8388.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ @@ -82,8 +82,8 @@ static int pmdk_es8388_init(struct snd_soc_pcm_runtime *rtd) /* Jack detection API stuff */ ret = snd_soc_card_jack_new(rtd->card, "Headset Jack", SND_JACK_HEADSET, - &hs_jack, hs_jack_pins, - ARRAY_SIZE(hs_jack_pins)); + &hs_jack, hs_jack_pins, + ARRAY_SIZE(hs_jack_pins)); if (ret) goto err; @@ -138,7 +138,7 @@ static int pmdk_sound_probe(struct platform_device *pdev) hs_jack_gpios[0].gpiod_dev = dev; n = gpiod_count(dev, "det"); - if(n < 0) + if (n < 0) pmdk_dai[0].init = NULL; return devm_snd_soc_register_card(&pdev->dev, card); diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index 11103b75c596014aa49908c8a9654c57913ae7bb..2ef79785cb83d666929cd66f474bea6dc71286bf 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.c @@ -97,6 +97,28 @@ static bool kvm_is_device_pfn(unsigned long pfn) return !pfn_valid(pfn); } +#define KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR GENMASK(5, 2) +static bool stage2_pte_cacheable(u64 pte) +{ + u64 memattr = pte & KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR; + return memattr == PAGE_S2_MEMATTR(NORMAL); +} +#define KVM_PTE_LEAF_ATTR_HI_S2_XN BIT(54) +static bool stage2_pte_executable(u64 pte) +{ + return !(pte & KVM_PTE_LEAF_ATTR_HI_S2_XN); +} + +static void clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size) +{ + __clean_dcache_guest_page(pfn, size); +} + +static void invalidate_icache_guest_page(kvm_pfn_t pfn, unsigned long size) +{ + __invalidate_icache_guest_page(pfn, size); +} + /** * stage2_dissolve_pmd() - clear and flush huge PMD entry * @kvm: pointer to kvm structure. @@ -1083,6 +1105,13 @@ static int stage2_set_pmd_huge(struct kvm *kvm, struct kvm_mmu_memory_cache pmd_clear(pmd); kvm_tlb_flush_vmid_ipa(kvm, addr); } else { + /* Flush data cache before installation of the new PTE */ + if (stage2_pte_cacheable(pmd_val(*new_pmd))) + kvm_flush_dcache_pmd(*new_pmd); + + if (stage2_pte_executable(pmd_val(*new_pmd))) + invalidate_icache_guest_page(pmd_pfn(*new_pmd), S2_PMD_SIZE); + get_page(virt_to_page(pmd)); } @@ -1161,6 +1190,13 @@ static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, kvm_set_pte(pte, __pte(0)); kvm_tlb_flush_vmid_ipa(kvm, addr); } else { + /* Flush data cache before installation of the new PTE */ + if (stage2_pte_cacheable(pte_val(*new_pte))) + kvm_flush_dcache_pte(*new_pte); + + if (stage2_pte_executable(pte_val(*new_pte))) + invalidate_icache_guest_page(pte_pfn(*new_pte), PAGE_SIZE); + get_page(virt_to_page(pte)); } @@ -1453,16 +1489,6 @@ void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); } -static void clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size) -{ - __clean_dcache_guest_page(pfn, size); -} - -static void invalidate_icache_guest_page(kvm_pfn_t pfn, unsigned long size) -{ - __invalidate_icache_guest_page(pfn, size); -} - static void kvm_send_hwpoison_signal(unsigned long address, struct vm_area_struct *vma) { @@ -1596,12 +1622,9 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, kvm_set_pfn_dirty(pfn); } - if (fault_status != FSC_PERM) - clean_dcache_guest_page(pfn, PMD_SIZE); if (exec_fault) { new_pmd = kvm_s2pmd_mkexec(new_pmd); - invalidate_icache_guest_page(pfn, PMD_SIZE); } else if (fault_status == FSC_PERM) { /* Preserve execute if XN was already cleared */ if (stage2_is_exec(kvm, fault_ipa)) @@ -1618,12 +1641,9 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, mark_page_dirty(kvm, gfn); } - if (fault_status != FSC_PERM) - clean_dcache_guest_page(pfn, PAGE_SIZE); if (exec_fault) { new_pte = kvm_s2pte_mkexec(new_pte); - invalidate_icache_guest_page(pfn, PAGE_SIZE); } else if (fault_status == FSC_PERM) { /* Preserve execute if XN was already cleared */ if (stage2_is_exec(kvm, fault_ipa)) @@ -1878,7 +1898,6 @@ void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) * We've moved a page around, probably through CoW, so let's treat it * just like a translation fault and clean the cache to the PoC. */ - clean_dcache_guest_page(pfn, PAGE_SIZE); stage2_pte = pfn_pte(pfn, PAGE_S2); handle_hva_to_gpa(kvm, hva, end, &kvm_set_spte_handler, &stage2_pte); } @@ -2245,9 +2264,21 @@ void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled) * If switching it off, need to clean the caches. * Clean + invalidate does the trick always. */ - if (now_enabled != was_enabled) - stage2_flush_vm(vcpu->kvm); + if (now_enabled != was_enabled) { + /* + * Due to Phytium CPU's cache consistency support, + * just flush dcache on one vcpu not all vcpus in the VM. + * This can reduce the number of flush dcaches and + * improve the efficiency of SMP multi-core startup, + * especially for the large VM with hugepages. + */ + if (read_cpuid_implementor() == ARM_CPU_IMP_PHYTIUM) { + if (vcpu->vcpu_id == 0) + stage2_flush_vm(vcpu->kvm); + } else + stage2_flush_vm(vcpu->kvm); + } /* Caches are now on, stop trapping VM ops (until a S/W op) */ if (now_enabled) *vcpu_hcr(vcpu) &= ~HCR_TVM;