diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000000000000000000000000000000000000..10dc5a9a61b3e33ba3c82e2059db2275e34efa63 --- /dev/null +++ b/.clang-format @@ -0,0 +1,548 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# clang-format configuration file. Intended for clang-format >= 4. +# +# For more information, see: +# +# Documentation/process/clang-format.rst +# https://clang.llvm.org/docs/ClangFormat.html +# https://clang.llvm.org/docs/ClangFormatStyleOptions.html +# +--- +AccessModifierOffset: -4 +AlignAfterOpenBracket: Align +AlignConsecutiveAssignments: false +AlignConsecutiveDeclarations: false +#AlignEscapedNewlines: Left # Unknown to clang-format-4.0 +AlignOperands: true +AlignTrailingComments: false +AllowAllParametersOfDeclarationOnNextLine: false +AllowShortBlocksOnASingleLine: false +AllowShortCaseLabelsOnASingleLine: false +AllowShortFunctionsOnASingleLine: None +AllowShortIfStatementsOnASingleLine: false +AllowShortLoopsOnASingleLine: false +AlwaysBreakAfterDefinitionReturnType: None +AlwaysBreakAfterReturnType: None +AlwaysBreakBeforeMultilineStrings: false +AlwaysBreakTemplateDeclarations: false +BinPackArguments: true +BinPackParameters: true +BraceWrapping: + AfterClass: false + AfterControlStatement: false + AfterEnum: false + AfterFunction: true + AfterNamespace: true + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + #AfterExternBlock: false # Unknown to clang-format-5.0 + BeforeCatch: false + BeforeElse: false + IndentBraces: false + #SplitEmptyFunction: true # Unknown to clang-format-4.0 + #SplitEmptyRecord: true # Unknown to clang-format-4.0 + #SplitEmptyNamespace: true # Unknown to clang-format-4.0 +BreakBeforeBinaryOperators: None +BreakBeforeBraces: Custom +#BreakBeforeInheritanceComma: false # Unknown to clang-format-4.0 +BreakBeforeTernaryOperators: false +BreakConstructorInitializersBeforeComma: false +#BreakConstructorInitializers: BeforeComma # Unknown to clang-format-4.0 +BreakAfterJavaFieldAnnotations: false +BreakStringLiterals: false +ColumnLimit: 80 +CommentPragmas: '^ IWYU pragma:' +#CompactNamespaces: false # Unknown to clang-format-4.0 +ConstructorInitializerAllOnOneLineOrOnePerLine: false +ConstructorInitializerIndentWidth: 8 +ContinuationIndentWidth: 8 +Cpp11BracedListStyle: false +DerivePointerAlignment: false +DisableFormat: false +ExperimentalAutoDetectBinPacking: false +#FixNamespaceComments: false # Unknown to clang-format-4.0 + +# Taken from: +# git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ \ +# | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$, - '\1'," \ +# | sort | uniq +ForEachMacros: + - 'apei_estatus_for_each_section' + - 'ata_for_each_dev' + - 'ata_for_each_link' + - '__ata_qc_for_each' + - 'ata_qc_for_each' + - 'ata_qc_for_each_raw' + - 'ata_qc_for_each_with_internal' + - 'ax25_for_each' + - 'ax25_uid_for_each' + - '__bio_for_each_bvec' + - 'bio_for_each_bvec' + - 'bio_for_each_bvec_all' + - 'bio_for_each_integrity_vec' + - '__bio_for_each_segment' + - 'bio_for_each_segment' + - 'bio_for_each_segment_all' + - 'bio_list_for_each' + - 'bip_for_each_vec' + - 'bitmap_for_each_clear_region' + - 'bitmap_for_each_set_region' + - 'blkg_for_each_descendant_post' + - 'blkg_for_each_descendant_pre' + - 'blk_queue_for_each_rl' + - 'bond_for_each_slave' + - 'bond_for_each_slave_rcu' + - 'bpf_for_each_spilled_reg' + - 'btree_for_each_safe128' + - 'btree_for_each_safe32' + - 'btree_for_each_safe64' + - 'btree_for_each_safel' + - 'card_for_each_dev' + - 'cgroup_taskset_for_each' + - 'cgroup_taskset_for_each_leader' + - 'cpufreq_for_each_entry' + - 'cpufreq_for_each_entry_idx' + - 'cpufreq_for_each_valid_entry' + - 'cpufreq_for_each_valid_entry_idx' + - 'css_for_each_child' + - 'css_for_each_descendant_post' + - 'css_for_each_descendant_pre' + - 'device_for_each_child_node' + - 'dma_fence_chain_for_each' + - 'do_for_each_ftrace_op' + - 'drm_atomic_crtc_for_each_plane' + - 'drm_atomic_crtc_state_for_each_plane' + - 'drm_atomic_crtc_state_for_each_plane_state' + - 'drm_atomic_for_each_plane_damage' + - 'drm_client_for_each_connector_iter' + - 'drm_client_for_each_modeset' + - 'drm_connector_for_each_possible_encoder' + - 'drm_for_each_bridge_in_chain' + - 'drm_for_each_connector_iter' + - 'drm_for_each_crtc' + - 'drm_for_each_encoder' + - 'drm_for_each_encoder_mask' + - 'drm_for_each_fb' + - 'drm_for_each_legacy_plane' + - 'drm_for_each_plane' + - 'drm_for_each_plane_mask' + - 'drm_for_each_privobj' + - 'drm_mm_for_each_hole' + - 'drm_mm_for_each_node' + - 'drm_mm_for_each_node_in_range' + - 'drm_mm_for_each_node_safe' + - 'flow_action_for_each' + - 'for_each_active_dev_scope' + - 'for_each_active_drhd_unit' + - 'for_each_active_iommu' + - 'for_each_aggr_pgid' + - 'for_each_available_child_of_node' + - 'for_each_bio' + - 'for_each_board_func_rsrc' + - 'for_each_bvec' + - 'for_each_card_auxs' + - 'for_each_card_auxs_safe' + - 'for_each_card_components' + - 'for_each_card_dapms' + - 'for_each_card_pre_auxs' + - 'for_each_card_prelinks' + - 'for_each_card_rtds' + - 'for_each_card_rtds_safe' + - 'for_each_card_widgets' + - 'for_each_card_widgets_safe' + - 'for_each_cgroup_storage_type' + - 'for_each_child_of_node' + - 'for_each_clear_bit' + - 'for_each_clear_bit_from' + - 'for_each_cmsghdr' + - 'for_each_compatible_node' + - 'for_each_component_dais' + - 'for_each_component_dais_safe' + - 'for_each_comp_order' + - 'for_each_console' + - 'for_each_cpu' + - 'for_each_cpu_and' + - 'for_each_cpu_not' + - 'for_each_cpu_wrap' + - 'for_each_dapm_widgets' + - 'for_each_dev_addr' + - 'for_each_dev_scope' + - 'for_each_displayid_db' + - 'for_each_dma_cap_mask' + - 'for_each_dpcm_be' + - 'for_each_dpcm_be_rollback' + - 'for_each_dpcm_be_safe' + - 'for_each_dpcm_fe' + - 'for_each_drhd_unit' + - 'for_each_dss_dev' + - 'for_each_efi_memory_desc' + - 'for_each_efi_memory_desc_in_map' + - 'for_each_element' + - 'for_each_element_extid' + - 'for_each_element_id' + - 'for_each_endpoint_of_node' + - 'for_each_evictable_lru' + - 'for_each_fib6_node_rt_rcu' + - 'for_each_fib6_walker_rt' + - 'for_each_free_mem_pfn_range_in_zone' + - 'for_each_free_mem_pfn_range_in_zone_from' + - 'for_each_free_mem_range' + - 'for_each_free_mem_range_reverse' + - 'for_each_func_rsrc' + - 'for_each_hstate' + - 'for_each_if' + - 'for_each_iommu' + - 'for_each_ip_tunnel_rcu' + - 'for_each_irq_nr' + - 'for_each_link_codecs' + - 'for_each_link_cpus' + - 'for_each_link_platforms' + - 'for_each_lru' + - 'for_each_matching_node' + - 'for_each_matching_node_and_match' + - 'for_each_member' + - 'for_each_mem_region' + - 'for_each_memblock_type' + - 'for_each_memcg_cache_index' + - 'for_each_mem_pfn_range' + - '__for_each_mem_range' + - 'for_each_mem_range' + - '__for_each_mem_range_rev' + - 'for_each_mem_range_rev' + - 'for_each_migratetype_order' + - 'for_each_msi_entry' + - 'for_each_msi_entry_safe' + - 'for_each_net' + - 'for_each_net_continue_reverse' + - 'for_each_netdev' + - 'for_each_netdev_continue' + - 'for_each_netdev_continue_rcu' + - 'for_each_netdev_continue_reverse' + - 'for_each_netdev_feature' + - 'for_each_netdev_in_bond_rcu' + - 'for_each_netdev_rcu' + - 'for_each_netdev_reverse' + - 'for_each_netdev_safe' + - 'for_each_net_rcu' + - 'for_each_new_connector_in_state' + - 'for_each_new_crtc_in_state' + - 'for_each_new_mst_mgr_in_state' + - 'for_each_new_plane_in_state' + - 'for_each_new_private_obj_in_state' + - 'for_each_node' + - 'for_each_node_by_name' + - 'for_each_node_by_type' + - 'for_each_node_mask' + - 'for_each_node_state' + - 'for_each_node_with_cpus' + - 'for_each_node_with_property' + - 'for_each_nonreserved_multicast_dest_pgid' + - 'for_each_of_allnodes' + - 'for_each_of_allnodes_from' + - 'for_each_of_cpu_node' + - 'for_each_of_pci_range' + - 'for_each_old_connector_in_state' + - 'for_each_old_crtc_in_state' + - 'for_each_old_mst_mgr_in_state' + - 'for_each_oldnew_connector_in_state' + - 'for_each_oldnew_crtc_in_state' + - 'for_each_oldnew_mst_mgr_in_state' + - 'for_each_oldnew_plane_in_state' + - 'for_each_oldnew_plane_in_state_reverse' + - 'for_each_oldnew_private_obj_in_state' + - 'for_each_old_plane_in_state' + - 'for_each_old_private_obj_in_state' + - 'for_each_online_cpu' + - 'for_each_online_node' + - 'for_each_online_pgdat' + - 'for_each_pci_bridge' + - 'for_each_pci_dev' + - 'for_each_pci_msi_entry' + - 'for_each_pcm_streams' + - 'for_each_physmem_range' + - 'for_each_populated_zone' + - 'for_each_possible_cpu' + - 'for_each_present_cpu' + - 'for_each_prime_number' + - 'for_each_prime_number_from' + - 'for_each_process' + - 'for_each_process_thread' + - 'for_each_property_of_node' + - 'for_each_registered_fb' + - 'for_each_requested_gpio' + - 'for_each_requested_gpio_in_range' + - 'for_each_reserved_mem_range' + - 'for_each_reserved_mem_region' + - 'for_each_rtd_codec_dais' + - 'for_each_rtd_codec_dais_rollback' + - 'for_each_rtd_components' + - 'for_each_rtd_cpu_dais' + - 'for_each_rtd_cpu_dais_rollback' + - 'for_each_rtd_dais' + - 'for_each_set_bit' + - 'for_each_set_bit_from' + - 'for_each_set_clump8' + - 'for_each_sg' + - 'for_each_sg_dma_page' + - 'for_each_sg_page' + - 'for_each_sgtable_dma_page' + - 'for_each_sgtable_dma_sg' + - 'for_each_sgtable_page' + - 'for_each_sgtable_sg' + - 'for_each_sibling_event' + - 'for_each_subelement' + - 'for_each_subelement_extid' + - 'for_each_subelement_id' + - '__for_each_thread' + - 'for_each_thread' + - 'for_each_unicast_dest_pgid' + - 'for_each_wakeup_source' + - 'for_each_zone' + - 'for_each_zone_zonelist' + - 'for_each_zone_zonelist_nodemask' + - 'fwnode_for_each_available_child_node' + - 'fwnode_for_each_child_node' + - 'fwnode_graph_for_each_endpoint' + - 'gadget_for_each_ep' + - 'genradix_for_each' + - 'genradix_for_each_from' + - 'hash_for_each' + - 'hash_for_each_possible' + - 'hash_for_each_possible_rcu' + - 'hash_for_each_possible_rcu_notrace' + - 'hash_for_each_possible_safe' + - 'hash_for_each_rcu' + - 'hash_for_each_safe' + - 'hctx_for_each_ctx' + - 'hlist_bl_for_each_entry' + - 'hlist_bl_for_each_entry_rcu' + - 'hlist_bl_for_each_entry_safe' + - 'hlist_for_each' + - 'hlist_for_each_entry' + - 'hlist_for_each_entry_continue' + - 'hlist_for_each_entry_continue_rcu' + - 'hlist_for_each_entry_continue_rcu_bh' + - 'hlist_for_each_entry_from' + - 'hlist_for_each_entry_from_rcu' + - 'hlist_for_each_entry_rcu' + - 'hlist_for_each_entry_rcu_bh' + - 'hlist_for_each_entry_rcu_notrace' + - 'hlist_for_each_entry_safe' + - '__hlist_for_each_rcu' + - 'hlist_for_each_safe' + - 'hlist_nulls_for_each_entry' + - 'hlist_nulls_for_each_entry_from' + - 'hlist_nulls_for_each_entry_rcu' + - 'hlist_nulls_for_each_entry_safe' + - 'i3c_bus_for_each_i2cdev' + - 'i3c_bus_for_each_i3cdev' + - 'ide_host_for_each_port' + - 'ide_port_for_each_dev' + - 'ide_port_for_each_present_dev' + - 'idr_for_each_entry' + - 'idr_for_each_entry_continue' + - 'idr_for_each_entry_continue_ul' + - 'idr_for_each_entry_ul' + - 'in_dev_for_each_ifa_rcu' + - 'in_dev_for_each_ifa_rtnl' + - 'inet_bind_bucket_for_each' + - 'inet_lhash2_for_each_icsk_rcu' + - 'key_for_each' + - 'key_for_each_safe' + - 'klp_for_each_func' + - 'klp_for_each_func_safe' + - 'klp_for_each_func_static' + - 'klp_for_each_object' + - 'klp_for_each_object_safe' + - 'klp_for_each_object_static' + - 'kunit_suite_for_each_test_case' + - 'kvm_for_each_memslot' + - 'kvm_for_each_vcpu' + - 'list_for_each' + - 'list_for_each_codec' + - 'list_for_each_codec_safe' + - 'list_for_each_continue' + - 'list_for_each_entry' + - 'list_for_each_entry_continue' + - 'list_for_each_entry_continue_rcu' + - 'list_for_each_entry_continue_reverse' + - 'list_for_each_entry_from' + - 'list_for_each_entry_from_rcu' + - 'list_for_each_entry_from_reverse' + - 'list_for_each_entry_lockless' + - 'list_for_each_entry_rcu' + - 'list_for_each_entry_reverse' + - 'list_for_each_entry_safe' + - 'list_for_each_entry_safe_continue' + - 'list_for_each_entry_safe_from' + - 'list_for_each_entry_safe_reverse' + - 'list_for_each_prev' + - 'list_for_each_prev_safe' + - 'list_for_each_safe' + - 'llist_for_each' + - 'llist_for_each_entry' + - 'llist_for_each_entry_safe' + - 'llist_for_each_safe' + - 'mci_for_each_dimm' + - 'media_device_for_each_entity' + - 'media_device_for_each_intf' + - 'media_device_for_each_link' + - 'media_device_for_each_pad' + - 'nanddev_io_for_each_page' + - 'netdev_for_each_lower_dev' + - 'netdev_for_each_lower_private' + - 'netdev_for_each_lower_private_rcu' + - 'netdev_for_each_mc_addr' + - 'netdev_for_each_uc_addr' + - 'netdev_for_each_upper_dev_rcu' + - 'netdev_hw_addr_list_for_each' + - 'nft_rule_for_each_expr' + - 'nla_for_each_attr' + - 'nla_for_each_nested' + - 'nlmsg_for_each_attr' + - 'nlmsg_for_each_msg' + - 'nr_neigh_for_each' + - 'nr_neigh_for_each_safe' + - 'nr_node_for_each' + - 'nr_node_for_each_safe' + - 'of_for_each_phandle' + - 'of_property_for_each_string' + - 'of_property_for_each_u32' + - 'pci_bus_for_each_resource' + - 'pcm_for_each_format' + - 'ping_portaddr_for_each_entry' + - 'plist_for_each' + - 'plist_for_each_continue' + - 'plist_for_each_entry' + - 'plist_for_each_entry_continue' + - 'plist_for_each_entry_safe' + - 'plist_for_each_safe' + - 'pnp_for_each_card' + - 'pnp_for_each_dev' + - 'protocol_for_each_card' + - 'protocol_for_each_dev' + - 'queue_for_each_hw_ctx' + - 'radix_tree_for_each_slot' + - 'radix_tree_for_each_tagged' + - 'rbtree_postorder_for_each_entry_safe' + - 'rdma_for_each_block' + - 'rdma_for_each_port' + - 'rdma_umem_for_each_dma_block' + - 'resource_list_for_each_entry' + - 'resource_list_for_each_entry_safe' + - 'rhl_for_each_entry_rcu' + - 'rhl_for_each_rcu' + - 'rht_for_each' + - 'rht_for_each_entry' + - 'rht_for_each_entry_from' + - 'rht_for_each_entry_rcu' + - 'rht_for_each_entry_rcu_from' + - 'rht_for_each_entry_safe' + - 'rht_for_each_from' + - 'rht_for_each_rcu' + - 'rht_for_each_rcu_from' + - '__rq_for_each_bio' + - 'rq_for_each_bvec' + - 'rq_for_each_segment' + - 'scsi_for_each_prot_sg' + - 'scsi_for_each_sg' + - 'sctp_for_each_hentry' + - 'sctp_skb_for_each' + - 'shdma_for_each_chan' + - '__shost_for_each_device' + - 'shost_for_each_device' + - 'sk_for_each' + - 'sk_for_each_bound' + - 'sk_for_each_entry_offset_rcu' + - 'sk_for_each_from' + - 'sk_for_each_rcu' + - 'sk_for_each_safe' + - 'sk_nulls_for_each' + - 'sk_nulls_for_each_from' + - 'sk_nulls_for_each_rcu' + - 'snd_array_for_each' + - 'snd_pcm_group_for_each_entry' + - 'snd_soc_dapm_widget_for_each_path' + - 'snd_soc_dapm_widget_for_each_path_safe' + - 'snd_soc_dapm_widget_for_each_sink_path' + - 'snd_soc_dapm_widget_for_each_source_path' + - 'tb_property_for_each' + - 'tcf_exts_for_each_action' + - 'udp_portaddr_for_each_entry' + - 'udp_portaddr_for_each_entry_rcu' + - 'usb_hub_for_each_child' + - 'v4l2_device_for_each_subdev' + - 'v4l2_m2m_for_each_dst_buf' + - 'v4l2_m2m_for_each_dst_buf_safe' + - 'v4l2_m2m_for_each_src_buf' + - 'v4l2_m2m_for_each_src_buf_safe' + - 'virtio_device_for_each_vq' + - 'while_for_each_ftrace_op' + - 'xa_for_each' + - 'xa_for_each_marked' + - 'xa_for_each_range' + - 'xa_for_each_start' + - 'xas_for_each' + - 'xas_for_each_conflict' + - 'xas_for_each_marked' + - 'xbc_array_for_each_value' + - 'xbc_for_each_key_value' + - 'xbc_node_for_each_array_value' + - 'xbc_node_for_each_child' + - 'xbc_node_for_each_key_value' + - 'zorro_for_each_dev' + +#IncludeBlocks: Preserve # Unknown to clang-format-5.0 +IncludeCategories: + - Regex: '.*' + Priority: 1 +IncludeIsMainRegex: '(Test)?$' +IndentCaseLabels: false +#IndentPPDirectives: None # Unknown to clang-format-5.0 +IndentWidth: 8 +IndentWrappedFunctionNames: false +JavaScriptQuotes: Leave +JavaScriptWrapImports: true +KeepEmptyLinesAtTheStartOfBlocks: false +MacroBlockBegin: '' +MacroBlockEnd: '' +MaxEmptyLinesToKeep: 1 +NamespaceIndentation: None +#ObjCBinPackProtocolList: Auto # Unknown to clang-format-5.0 +ObjCBlockIndentWidth: 8 +ObjCSpaceAfterProperty: true +ObjCSpaceBeforeProtocolList: true + +# Taken from git's rules +#PenaltyBreakAssignment: 10 # Unknown to clang-format-4.0 +PenaltyBreakBeforeFirstCallParameter: 30 +PenaltyBreakComment: 10 +PenaltyBreakFirstLessLess: 0 +PenaltyBreakString: 10 +PenaltyExcessCharacter: 100 +PenaltyReturnTypeOnItsOwnLine: 60 + +PointerAlignment: Right +ReflowComments: false +SortIncludes: false +#SortUsingDeclarations: false # Unknown to clang-format-4.0 +SpaceAfterCStyleCast: false +SpaceAfterTemplateKeyword: true +SpaceBeforeAssignmentOperators: true +#SpaceBeforeCtorInitializerColon: true # Unknown to clang-format-5.0 +#SpaceBeforeInheritanceColon: true # Unknown to clang-format-5.0 +SpaceBeforeParens: ControlStatements +#SpaceBeforeRangeBasedForLoopColon: true # Unknown to clang-format-5.0 +SpaceInEmptyParentheses: false +SpacesBeforeTrailingComments: 1 +SpacesInAngles: false +SpacesInContainerLiterals: false +SpacesInCStyleCastParentheses: false +SpacesInParentheses: false +SpacesInSquareBrackets: false +Standard: Cpp03 +TabWidth: 8 +UseTab: Always +... diff --git a/.cocciconfig b/.cocciconfig new file mode 100644 index 0000000000000000000000000000000000000000..43967c6b20151ee126db08e24758e3c789bcb844 --- /dev/null +++ b/.cocciconfig @@ -0,0 +1,3 @@ +[spatch] + options = --timeout 200 + options = --use-gitgrep diff --git a/.get_maintainer.ignore b/.get_maintainer.ignore new file mode 100644 index 0000000000000000000000000000000000000000..a64d219137455f407a7b1f2c6b156c5575852e9e --- /dev/null +++ b/.get_maintainer.ignore @@ -0,0 +1,2 @@ +Christoph Hellwig +Marc Gonzalez diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000000000000000000000000000000000000..4b32eaa9571e64e47b51c43537063f56b204d8b3 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,4 @@ +*.c diff=cpp +*.h diff=cpp +*.dtsi diff=dts +*.dts diff=dts diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..8b0b16eeca881e2b5a028c95f7d588770d6711ee --- /dev/null +++ b/.gitignore @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# NOTE! Don't add files that are generated in specific +# subdirectories here. Add them in the ".gitignore" file +# in that subdirectory instead. +# +# NOTE! Please use 'git ls-files -i --exclude-standard' +# command after changing this file, to see if there are +# any tracked files which get ignored after the change. +# +# Normal rules (sorted alphabetically) +# +.* +*.a +*.asn1.[ch] +*.bin +*.bz2 +*.c.[012]*.* +*.dt.yaml +*.dtb +*.dtbo +*.dtb.S +*.dwo +*.elf +*.gcno +*.gz +*.i +*.ko +*.lex.c +*.ll +*.lst +*.lz4 +*.lzma +*.lzo +*.mod +*.mod.c +*.o +*.o.* +*.patch +*.s +*.so +*.so.dbg +*.su +*.symtypes +*.tab.[ch] +*.tar +*.xz +*.zst +Module.symvers +modules.builtin +modules.order + +# +# Top-level generic files +# +/tags +/TAGS +/linux +/modules-only.symvers +/vmlinux +/vmlinux.32 +/vmlinux.symvers +/vmlinux-gdb.py +/vmlinuz +/System.map +/Module.markers +/modules.builtin.modinfo +/modules.nsdeps + +# +# RPM spec file (make rpm-pkg) +# +/*.spec + +# +# Debian directory (make deb-pkg) +# +/debian/ + +# +# Snap directory (make snap-pkg) +# +/snap/ + +# +# tar directory (make tar*-pkg) +# +/tar-install/ + +# +# We don't want to ignore the following even if they are dot-files +# +!.clang-format +!.cocciconfig +!.get_maintainer.ignore +!.gitattributes +!.gitignore +!.mailmap + +# +# Generated include files +# +/include/config/ +/include/generated/ +/include/ksym/ +/arch/*/include/generated/ + +# stgit generated dirs +patches-* + +# quilt's files +patches +series + +# cscope files +cscope.* +ncscope.* + +# gnu global files +GPATH +GRTAGS +GSYMS +GTAGS + +# id-utils files +ID + +*.orig +*~ +\#*# + +# +# Leavings from module signing +# +extra_certificates +signing_key.pem +signing_key.priv +signing_key.x509 +x509.genkey + +# Kconfig presets +/all.config +/alldef.config +/allmod.config +/allno.config +/allrandom.config +/allyes.config + +# Kconfig savedefconfig output +/defconfig + +# Kdevelop4 +*.kdev4 + +# Clang's compilation database file +/compile_commands.json + +# Documentation toolchain +sphinx_*/ diff --git a/.mailmap b/.mailmap new file mode 100644 index 0000000000000000000000000000000000000000..225546cc80288a5b3af81251d3e39c8efd3a0926 --- /dev/null +++ b/.mailmap @@ -0,0 +1,345 @@ +# +# This list is used by git-shortlog to fix a few botched name translations +# in the git archive, either because the author's full name was messed up +# and/or not always written the same way, making contributions from the +# same person appearing not to be so or badly displayed. Also allows for +# old email addresses to map to new email addresses. +# +# For format details, see "MAPPING AUTHORS" in "man git-shortlog". +# +# Please keep this list dictionary sorted. +# +# This comment is parsed by git-shortlog: +# repo-abbrev: /pub/scm/linux/kernel/git/ +# +Aaron Durbin +Adam Oldham +Adam Radford +Adriana Reus +Adrian Bunk +Alan Cox +Alan Cox +Aleksandar Markovic +Aleksey Gorelov +Alexander Lobakin +Alexander Lobakin +Alexander Lobakin +Alexandre Belloni +Alexei Starovoitov +Alexei Starovoitov +Alexei Starovoitov +Alex Shi +Alex Shi +Al Viro +Al Viro +Andi Kleen +Andi Shyti +Andreas Herrmann +Andrew Morton +Andrew Murray +Andrew Murray +Andrew Vasquez +Andrey Ryabinin +Andy Adamson +Antoine Tenart +Antoine Tenart +Antonio Ospite +Archit Taneja +Ard Biesheuvel +Arnaud Patard +Arnd Bergmann +Axel Dyks +Axel Lin +Bart Van Assche +Bart Van Assche +Ben Gardner +Ben M Cahill +Björn Steinbrink +Boris Brezillon +Boris Brezillon +Boris Brezillon +Boris Brezillon +Brian Avery +Brian King +Changbin Du +Changbin Du +Chao Yu +Chao Yu +Christophe Ricard +Christoph Hellwig +Corey Minyard +Damian Hobson-Garcia +Daniel Borkmann +Daniel Borkmann +Daniel Borkmann +Daniel Borkmann +Daniel Borkmann +Daniel Borkmann +David Brownell +David Woodhouse +Dengcheng Zhu +Dengcheng Zhu +Dengcheng Zhu +Dengcheng Zhu + +Dmitry Baryshkov +Dmitry Baryshkov <[dbaryshkov@gmail.com]> +Dmitry Baryshkov +Dmitry Baryshkov +Dmitry Safonov <0x7f454c46@gmail.com> +Dmitry Safonov <0x7f454c46@gmail.com> +Dmitry Safonov <0x7f454c46@gmail.com> +Domen Puncer +Douglas Gilbert +Ed L. Cashin +Erik Kaneda +Evgeniy Polyakov +Felipe W Damasio +Felix Kuhling +Felix Moeller +Filipe Lautert +Franck Bui-Huu +Frank Rowand +Frank Rowand +Frank Rowand +Frank Zago +Gao Xiang +Gao Xiang +Gerald Schaefer +Gerald Schaefer +Gerald Schaefer +Greg Kroah-Hartman +Greg Kroah-Hartman +Greg Kroah-Hartman +Greg Kurz +Gregory CLEMENT +Gustavo Padovan +Gustavo Padovan +Hanjun Guo +Heiko Carstens +Heiko Carstens +Henk Vergonet +Henrik Kretzschmar +Henrik Rydberg +Herbert Xu +Jacob Shin +Jaegeuk Kim +Jaegeuk Kim +Jaegeuk Kim +Jakub Kicinski +James Bottomley +James Bottomley +James E Wilson +James Hogan +James Hogan +James Ketrenos +Jan Glauber +Jan Glauber +Jan Glauber +Jarkko Sakkinen +Jason Gunthorpe +Jason Gunthorpe +Jason Gunthorpe + +Javi Merino +Jayachandran C +Jayachandran C +Jayachandran C +Jayachandran C + +Jean Tourrilhes +Jeff Garzik +Jeff Layton +Jeff Layton +Jeff Layton +Jens Axboe +Jens Osterkamp +Jiri Slaby +Jiri Slaby +Jiri Slaby +Jiri Slaby +Jiri Slaby +Johan Hovold +Johan Hovold +John Paul Adrian Glaubitz +John Stultz + + + + + +Juha Yrjola +Juha Yrjola +Juha Yrjola +Julien Thierry +Kamil Konieczny +Kay Sievers +Kees Cook +Kees Cook +Kees Cook +Kees Cook +Kenneth W Chen +Konstantin Khlebnikov +Konstantin Khlebnikov +Koushik +Krzysztof Kozlowski +Krzysztof Kozlowski +Kuninori Morimoto +Leonardo Bras +Leonid I Ananiev +Leon Romanovsky +Leon Romanovsky +Leon Romanovsky +Linas Vepstas +Linus Lüssing +Linus Lüssing + +Li Yang +Li Yang +Lukasz Luba +Maciej W. Rozycki +Marcin Nowakowski +Marc Zyngier +Mark Brown +Mark Starovoytov +Mark Yao +Martin Kepplinger +Martin Kepplinger +Martin Kepplinger +Mathieu Othacehe +Matthew Wilcox +Matthew Wilcox +Matthew Wilcox +Matthew Wilcox +Matthew Wilcox +Matthew Wilcox +Matthew Wilcox +Matthieu CASTET +Matt Ranostay +Matt Ranostay Matthew Ranostay +Matt Ranostay +Matt Redfearn +Mauro Carvalho Chehab +Mauro Carvalho Chehab +Mauro Carvalho Chehab +Mauro Carvalho Chehab +Mauro Carvalho Chehab +Mauro Carvalho Chehab +Mauro Carvalho Chehab +Maxime Ripard +Maxime Ripard +Mayuresh Janorkar +Michael Buesch +Michel Dänzer +Mike Rapoport +Mike Rapoport +Mike Rapoport +Miodrag Dinic +Miquel Raynal +Mitesh shah +Mohit Kumar +Morten Welinder +Morten Welinder +Morten Welinder +Morten Welinder +Mythri P K +Nguyen Anh Quynh +Nicolas Ferre +Nicolas Pitre +Nicolas Pitre +Oleksij Rempel +Oleksij Rempel +Oleksij Rempel +Oleksij Rempel +Oleksij Rempel +Pali Rohár +Paolo 'Blaisorblade' Giarrusso +Patrick Mochel +Paul Burton +Paul Burton +Paul E. McKenney +Paul E. McKenney +Paul E. McKenney +Paul E. McKenney +Peter A Jonsson +Peter Oruba +Peter Oruba +Pratyush Anand +Praveen BP +Punit Agrawal +Qais Yousef +Quentin Monnet +Quentin Perret +Rafael J. Wysocki +Rajesh Shah +Ralf Baechle +Ralf Wildenhues +Randy Dunlap +Rémi Denis-Courmont +Ricardo Ribalda +Ricardo Ribalda Ricardo Ribalda Delgado +Ricardo Ribalda +Ross Zwisler +Rudolf Marek +Rui Saraiva +Sachin P Sant +Sakari Ailus +Sam Ravnborg +Santosh Shilimkar +Santosh Shilimkar +Sarangdhar Joshi +Sascha Hauer +S.Çağlar Onur +Sean Christopherson +Sean Nyekjaer +Sebastian Reichel +Sebastian Reichel +Sedat Dilek +Shiraz Hashim +Shuah Khan +Shuah Khan +Shuah Khan +Shuah Khan +Simon Arlott +Simon Kelley +Stéphane Witzmann +Stephen Hemminger +Steve Wise +Steve Wise +Subash Abhinov Kasiviswanathan +Subhash Jadavani +Sudeep Holla Sudeep KarkadaNagesha +Sumit Semwal +Takashi YOSHII +Tejun Heo +Thomas Graf +Thomas Pedersen +Tiezhu Yang +Todor Tomov +Tony Luck +TripleX Chung +TripleX Chung +Tsuneo Yoshioka +Tycho Andersen +Uwe Kleine-König +Uwe Kleine-König +Uwe Kleine-König +Uwe Kleine-König +Uwe Kleine-König +Valdis Kletnieks +Vinod Koul +Vinod Koul +Vinod Koul +Viresh Kumar +Viresh Kumar +Viresh Kumar +Vivien Didelot +Vlad Dogaru +Vladimir Davydov +Vladimir Davydov +WeiXiong Liao +Will Deacon +Wolfram Sang +Wolfram Sang +Yakir Yang +Yusuke Goda diff --git a/Documentation/devicetree/configfs-overlays.txt b/Documentation/devicetree/configfs-overlays.txt new file mode 100644 index 0000000000000000000000000000000000000000..5fa43e0643072c7963daddc18cec7772910378ad --- /dev/null +++ b/Documentation/devicetree/configfs-overlays.txt @@ -0,0 +1,31 @@ +Howto use the configfs overlay interface. + +A device-tree configfs entry is created in /config/device-tree/overlays +and and it is manipulated using standard file system I/O. +Note that this is a debug level interface, for use by developers and +not necessarily something accessed by normal users due to the +security implications of having direct access to the kernel's device tree. + +* To create an overlay you mkdir the directory: + + # mkdir /config/device-tree/overlays/foo + +* Either you echo the overlay firmware file to the path property file. + + # echo foo.dtbo >/config/device-tree/overlays/foo/path + +* Or you cat the contents of the overlay to the dtbo file + + # cat foo.dtbo >/config/device-tree/overlays/foo/dtbo + +The overlay file will be applied, and devices will be created/destroyed +as required. + +To remove it simply rmdir the directory. + + # rmdir /config/device-tree/overlays/foo + +The rationalle of the dual interface (firmware & direct copy) is that each is +better suited to different use patterns. The firmware interface is what's +intended to be used by hardware managers in the kernel, while the copy interface +make sense for developers (since it avoids problems with namespaces). diff --git a/Makefile b/Makefile index d1cd7539105dfa7bbe1230b7488e4b57ebf318bd..015c94b2e7730ec43895e32ab9416d5e96b4a518 100644 --- a/Makefile +++ b/Makefile @@ -1848,7 +1848,7 @@ clean: $(clean-dirs) @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \ \( -name '*.[aios]' -o -name '*.ko' -o -name '.*.cmd' \ -o -name '*.ko.*' \ - -o -name '*.dtb' -o -name '*.dtb.S' -o -name '*.dt.yaml' \ + -o -name '*.dtb' -o -name '*.dtbo' -o -name '*.dtb.S' -o -name '*.dt.yaml'\ -o -name '*.dwo' -o -name '*.lst' \ -o -name '*.su' -o -name '*.mod' \ -o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \ diff --git a/README.md b/README.md index 9847768e9295942e37488e0e66f632a0f4381287..fe94b83cbda80ce4e37edc54257c4f2e47679b56 100644 --- a/README.md +++ b/README.md @@ -1,22 +1,12 @@ # linux-kernel-xenomai ## 1 项目简介 -Xenomai在Phytium CPU配套的开发板上配套的Linux kernel。
-本开源仓库的内核代码只支持Phytium E2000Q。对于FT2000/4和D2000，其内核源代码还没有开源，需要联系飞腾软件生态部获取内核源码。
+Xenomai在Phytium CPU配套的开发板上配套的Linux kernel，推荐使用Linux kernel 5.10.153-dovetail3和Xenomai v3.2.2。
+本开源仓库的内核代码支持E2000Q，飞腾派等飞腾CPU。
## 2 安装和使用教程 -### 2.1 Xenomai配套Linux kernel 4.19.209-cip59的用户手册和源代码获取路径 -Xenomai用户手册名称为xenomai_user_manual-v2.x.x.pdf，获取方法如下:
-https://gitee.com/phytium_embedded/phytium-embedded-docs/tree/master/xenomai
- -Linux kernel源代码链接如下:
-https://gitee.com/phytium_embedded/linux-kernel-xenomai/tree/4.19.209-cip59
- -Xenomai版本是3.1.3，源代码链接如下:
-https://source.denx.de/Xenomai/xenomai/-/tree/v3.1.3
- -### 2.2 Xenomai配套Linux kernel 5.10.153-dovetail3的用户手册和源代码获取路径 +### 2.1 Xenomai配套Linux kernel 5.10.153-dovetail3的用户手册和源代码获取路径 Xenomai用户手册名称为xenomai_user_manual-v3.x.x.pdf，获取方法如下:
-https://gitee.com/phytium_embedded/phytium-embedded-docs/tree/master/xenomai
+https://gitee.com/phytium_embedded/phytium-embedded-docs/tree/master/linux/xenomai
Linux kernel源代码链接如下:
https://gitee.com/phytium_embedded/linux-kernel-xenomai
@@ -24,6 +14,16 @@ https://gitee.com/phytium_embedded/linux-kernel-xenomai
Xenomai版本是3.2.2，源代码链接如下:
https://source.denx.de/Xenomai/xenomai/-/tree/v3.2.2
+### 2.2 Xenomai配套Linux kernel 4.19.209-cip59的用户手册和源代码获取路径 +Xenomai用户手册名称为xenomai_user_manual-v2.x.x.pdf，获取方法如下:
+https://gitee.com/phytium_embedded/phytium-embedded-docs/tree/master/linux/xenomai
+ +Linux kernel源代码链接如下:
+https://gitee.com/phytium_embedded/linux-kernel-xenomai/tree/4.19.209-cip59
+ +Xenomai版本是3.1.3，源代码链接如下:
+https://source.denx.de/Xenomai/xenomai/-/tree/v3.1.3
+ ## 3 贡献人员 该项目的开发成员列表如下：
diff --git a/arch/arm64/boot/dts/phytium/Makefile b/arch/arm64/boot/dts/phytium/Makefile index 037b33ba929c23de8c7fee919b091fef53497f99..9f2f50346fdfb5f89253032cd5fff46717cb09ce 100644 --- a/arch/arm64/boot/dts/phytium/Makefile +++ b/arch/arm64/boot/dts/phytium/Makefile @@ -15,3 +15,14 @@ dtb-$(CONFIG_ARCH_PHYTIUM) += e2000d-power-board.dtb dtb-$(CONFIG_ARCH_PHYTIUM) += e2000q-hanwei-board.dtb dtb-$(CONFIG_ARCH_PHYTIUM) += phytiumpi_firefly.dtb dtb-$(CONFIG_ARCH_PHYTIUM) += e2000d-chillipi-edu-board.dtb + +dtbo-$(CONFIG_ARCH_PHYTIUM) += px210.dtbo +dtbo-$(CONFIG_ARCH_PHYTIUM) += usb2_host_for_pe220x.dtbo + +#Enable support for device-tree overlay +DTC_FLAGS += -@ + +targets += dtbs dtbs_install +targets += $(dtbo-y) + +always-y := $(dtbo-y) diff --git a/arch/arm64/boot/dts/phytium/e2000d-chillipi-edu-board.dts b/arch/arm64/boot/dts/phytium/e2000d-chillipi-edu-board.dts index 28a1f0d47b743be27b687646b032a7e528623ee9..0ab55a50ffd179c72884e3dbce2ae0505d99d492 100644 --- a/arch/arm64/boot/dts/phytium/e2000d-chillipi-edu-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000d-chillipi-edu-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2202 chillipi education board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm64/boot/dts/phytium/e2000d-demo-board.dts b/arch/arm64/boot/dts/phytium/e2000d-demo-board.dts index bcfeeb449da0e8b667cb511d1f25c88a0c82ab53..e2d3fc43e013dededf537f91f741742009d31167 100644 --- a/arch/arm64/boot/dts/phytium/e2000d-demo-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000d-demo-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2202 demo board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm64/boot/dts/phytium/e2000d-miniitx-board.dts b/arch/arm64/boot/dts/phytium/e2000d-miniitx-board.dts index e85d27a823155e17a8a0358e239435617b6181f7..6f38e532a2758cc53420238fea27ef14830cc9d6 100644 --- a/arch/arm64/boot/dts/phytium/e2000d-miniitx-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000d-miniitx-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2202 miniitx board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * Hongmin Qi * diff --git a/arch/arm64/boot/dts/phytium/e2000d-power-board.dts b/arch/arm64/boot/dts/phytium/e2000d-power-board.dts index afefcc7e7560f951d503e9bbcf907b31ff8277af..1726a84fa7b6f787f0ec4caee9d398ce012aec77 100755 --- a/arch/arm64/boot/dts/phytium/e2000d-power-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000d-power-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2202 power board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * Hongmin Qi * diff --git a/arch/arm64/boot/dts/phytium/e2000q-come-board.dts b/arch/arm64/boot/dts/phytium/e2000q-come-board.dts index f98655dd49e4730109c633595a726c54c381cd78..1ce5c0034d9274a3e76bc15e0e866370c962f83f 100755 --- a/arch/arm64/boot/dts/phytium/e2000q-come-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000q-come-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2204 come board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * Hongmin Qi * @@ -263,3 +263,6 @@ &pwm1 { status = "okay"; }; +&vpu0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/phytium/e2000q-demo-board.dts b/arch/arm64/boot/dts/phytium/e2000q-demo-board.dts index bee198e6674f9ae0a4e747cf75a0c70c662f1c50..87d8999ae20dcd572bba9c1fbc5e4bb43cd0da9b 100644 --- a/arch/arm64/boot/dts/phytium/e2000q-demo-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000q-demo-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2204 demo board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -244,3 +244,7 @@ &pmdk_dp { &rng0 { status = "okay"; }; + +&vpu0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/phytium/e2000q-edu-board.dts b/arch/arm64/boot/dts/phytium/e2000q-edu-board.dts index b0a043025a5f96e2ed40ef6d822a6952549e7185..96c84e5eabe7c2603eb09440c946d288806d4948 100755 --- a/arch/arm64/boot/dts/phytium/e2000q-edu-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000q-edu-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2204 edu board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * Hongmin Qi * @@ -269,6 +269,10 @@ &dc0 { edp_mask = [00]; }; +&vpu0 { + status = "okay"; +}; + &i2s0 { #sound-dai-cells = <0>; dai-name = "phytium-i2s-lsd"; diff --git a/arch/arm64/boot/dts/phytium/e2000q-hanwei-board.dts b/arch/arm64/boot/dts/phytium/e2000q-hanwei-board.dts index 0c58438e385e341bb9537069dcee143f5e10e41c..02b635dd48c2e2b9548222bbdf47b25ce191de2b 100755 --- a/arch/arm64/boot/dts/phytium/e2000q-hanwei-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000q-hanwei-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2204 hanwei board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * Hongmin Qi * @@ -213,3 +213,6 @@ &gpio5 { status = "okay"; }; +&vpu0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/phytium/e2000q-miniitx-board.dts b/arch/arm64/boot/dts/phytium/e2000q-miniitx-board.dts index 6829a30793d7ff01b93713c3bded0e24f9f8b163..26c25c1603cf746f42a2140e830468808ff58067 100644 --- a/arch/arm64/boot/dts/phytium/e2000q-miniitx-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000q-miniitx-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium miniITX-Pe2204 development board. * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * Shaojun Yang * @@ -14,7 +14,6 @@ /dts-v1/; /memreserve/ 0x80000000 0x10000; -/memreserve/ 0xf4000000 0x4000000; #include "pe2204.dtsi" @@ -38,17 +37,30 @@ memory@00{ reg = <0x0 0x80000000 0x2 0x00000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + display_reserved: share@f4000000 { + no-map; + reg = <0x00 0xf4000000 0x0 0x4000000>; + }; + }; + sound_card: sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "phytium,pe220x-i2s-audio"; - simple-audio-card,cpu { - sound-dai = <&i2s0>; - }; - simple-audio-card,codec{ - sound-dai = <&codec0>; - }; - }; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "phytium,pe220x-i2s-audio"; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + simple-audio-card,codec{ + sound-dai = <&codec0>; + }; + }; }; &soc { @@ -68,22 +80,22 @@ rtc@68 { }; mio14: i2c@28030000 { - compatible = "phytium,i2c"; - reg = <0x0 0x28030000 0x0 0x1000>; - interrupts = ; - clocks = <&sysclk_50mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - codec0: es8336@10 { - det-gpios = <&gpio2 5 0>; - sel-gpios = <&gpio2 6 0>; - #sound-dai-cells = <0>; - compatible = "everest,es8336"; - reg = <0x10>; - mic-src = [20]; - }; + compatible = "phytium,i2c"; + reg = <0x0 0x28030000 0x0 0x1000>; + interrupts = ; + clocks = <&sysclk_50mhz>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + codec0: es8336@10 { + det-gpios = <&gpio2 5 0>; + sel-gpios = <&gpio2 6 0>; + #sound-dai-cells = <0>; + compatible = "everest,es8336"; + reg = <0x10>; + mic-src = [20]; + }; }; @@ -134,27 +146,27 @@ mio15: uart@28032000 { }; &gpio0 { - status = "okay"; + status = "okay"; }; &gpio1 { - status = "okay"; + status = "okay"; }; &gpio2 { - status = "okay"; + status = "okay"; }; &gpio3 { - status = "okay"; + status = "okay"; }; &gpio4 { - status = "okay"; + status = "okay"; }; &gpio5 { - status = "okay"; + status = "okay"; }; &watchdog0 { @@ -219,10 +231,9 @@ &macb2 { }; &dc0 { - reg = <0x0 0x32000000 0x0 0x8000>, - <0x0 0xf4000000 0x0 0x4000000>; // (optional) - pipe_mask = [03]; - edp_mask = [00]; + memory-region = <&display_reserved>; + pipe_mask = /bits/ 8 <0x3>; + edp_mask = /bits/ 8 <0x0>; status = "okay"; }; @@ -327,3 +338,6 @@ &rng0 { status = "okay"; }; +&vpu0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/phytium/e2000q-vpx-board.dts b/arch/arm64/boot/dts/phytium/e2000q-vpx-board.dts index 3310647934e64dca1ec8e23f98e7593ef4db40f7..c3a6950a46d0645ce42335c83d10f0c191b3adcc 100755 --- a/arch/arm64/boot/dts/phytium/e2000q-vpx-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000q-vpx-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2204 vpx board. * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * Tianyu Liu * @@ -320,3 +320,6 @@ &rng0 { status = "okay"; }; +&vpu0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/phytium/e2000s-demo-board.dts b/arch/arm64/boot/dts/phytium/e2000s-demo-board.dts index 047d1c5d5bacc2e5e27fb5dbedb8e942b96462ef..ba6fd5cc7ddbec098bc4e71cc3981069c98be081 100644 --- a/arch/arm64/boot/dts/phytium/e2000s-demo-board.dts +++ b/arch/arm64/boot/dts/phytium/e2000s-demo-board.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pe2201 demo board * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm64/boot/dts/phytium/pe2201.dtsi b/arch/arm64/boot/dts/phytium/pe2201.dtsi index 04d07e0ef1bbef6a8a6235669dc825edc91656f1..031c9f9d6081145e3891497f4b8e57f8c89f4c78 100644 --- a/arch/arm64/boot/dts/phytium/pe2201.dtsi +++ b/arch/arm64/boot/dts/phytium/pe2201.dtsi @@ -2,7 +2,7 @@ /* * dts file for Phytium Pe2201 SoC * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. */ #include "pe220x.dtsi" diff --git a/arch/arm64/boot/dts/phytium/pe2202.dtsi b/arch/arm64/boot/dts/phytium/pe2202.dtsi index 65657a7adf4920443cedbae78bb6075eb3ec072d..1478ee40c2cb866151c37f0ef6418219142596b2 100644 --- a/arch/arm64/boot/dts/phytium/pe2202.dtsi +++ b/arch/arm64/boot/dts/phytium/pe2202.dtsi @@ -2,7 +2,7 @@ /* * dts file for Phytium Pe2202 SoC * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. */ #include "pe220x.dtsi" diff --git a/arch/arm64/boot/dts/phytium/pe2204.dtsi b/arch/arm64/boot/dts/phytium/pe2204.dtsi index 745faf1f863ebb0f142d0fb6b90c6b108718f7c0..4d5d7b29518c46cddf29bfc52ef5b73c29bcc461 100644 --- a/arch/arm64/boot/dts/phytium/pe2204.dtsi +++ b/arch/arm64/boot/dts/phytium/pe2204.dtsi @@ -2,7 +2,7 @@ /* * dts file for Phytium Pe2204 SoC * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. */ #include "pe220x.dtsi" @@ -213,4 +213,11 @@ macb3: ethernet@32012000 { status = "disabled"; }; + vpu0: vpu@32b00000 { + compatible = "phytium,vpu"; + reg = <0x0 0x32b00000 0x0 0x20000>; + interrupts = ; + status = "disabled"; + }; + }; diff --git a/arch/arm64/boot/dts/phytium/pe220x.dtsi b/arch/arm64/boot/dts/phytium/pe220x.dtsi index 0b2011f190d5de2576574b6429c25f37addac407..540fb2b93716352bfc3ea49462160c2b347d4c61 100644 --- a/arch/arm64/boot/dts/phytium/pe220x.dtsi +++ b/arch/arm64/boot/dts/phytium/pe220x.dtsi @@ -2,7 +2,7 @@ /* * dts file for Phytium Pe220x SoC * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/arch/arm64/boot/dts/phytium/phytiumpi_firefly.dts b/arch/arm64/boot/dts/phytium/phytiumpi_firefly.dts index ac55e231aa2785ee49ae8bc909596e6d4deac853..82ff32a36392a0e5b5ac3a93e08de428ddb4893e 100644 --- a/arch/arm64/boot/dts/phytium/phytiumpi_firefly.dts +++ b/arch/arm64/boot/dts/phytium/phytiumpi_firefly.dts @@ -2,7 +2,7 @@ /* * DTS file for Phytium Pi development board. * - * Copyright (C) 2023, Phytium Technology Co., Ltd. + * Copyright (c) 2023-2024 Phytium Technology Co., Ltd. * * Shaojun Yang */ @@ -314,3 +314,7 @@ &pmdk_dp { &rng0 { status = "okay"; }; + +&vpu0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/phytium/px210.dtso b/arch/arm64/boot/dts/phytium/px210.dtso new file mode 100644 index 0000000000000000000000000000000000000000..9ff812ebfb8d48e7f6c0c30ebb6f61103ac47b9f --- /dev/null +++ b/arch/arm64/boot/dts/phytium/px210.dtso @@ -0,0 +1,33 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "phytium,pe220x"; + + fragment@0 { + target = <&soc>; + __overlay__ { + dc0:dc@32000000 { + status = "disabled"; + }; + pmdk_dp { + num-dp = <3>; + dp-mask = [07]; + }; + vpu0: vpu@32b00000 { + status = "disabled"; + }; + }; + }; + + + + fragment@1 { + target-path = "/iommu@30000000"; + __overlay__ { + status = "disabled"; + }; + }; + + +}; diff --git a/arch/arm64/boot/dts/phytium/usb2_host_for_pe220x.dtso b/arch/arm64/boot/dts/phytium/usb2_host_for_pe220x.dtso new file mode 100644 index 0000000000000000000000000000000000000000..577966af9bb57af7e0f4c1d67726574770d078c0 --- /dev/null +++ b/arch/arm64/boot/dts/phytium/usb2_host_for_pe220x.dtso @@ -0,0 +1,23 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "phytium,pe220x"; + + fragment@0 { + target = <&soc>; + __overlay__ { + usb2_0: usb2@31800000 { + dr_mode = "host"; + }; + usb2_1: usb2@31880000 { + status = "disabled"; + }; + usb2_2: usb2@31900000 { + status = "disabled"; + }; + }; + + + }; +}; diff --git a/arch/arm64/configs/phytium_defconfig b/arch/arm64/configs/phytium_defconfig index 802985cfaefe4a2cfe29472842473db1fa7cf42f..b01cbc0361c1adb4c2dd798aed214084812015ef 100644 --- a/arch/arm64/configs/phytium_defconfig +++ b/arch/arm64/configs/phytium_defconfig @@ -1,4 +1,4 @@ -CONFIG_LOCALVERSION="-dovetail3-phytium-embeded-v2.0" +CONFIG_LOCALVERSION="-dovetail3-phytium-embeded-v2.1" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -205,7 +205,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_MTD_NAND_DENALI_DT=y CONFIG_MTD_NAND_PHYTIUM_PLAT=m CONFIG_MTD_SPI_NOR=y -CONFIG_SPI_PHYTIUM_QUADSPI=y +CONFIG_OF_CONFIGFS=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y @@ -469,7 +469,6 @@ CONFIG_DRM_I2C_SIL164=m CONFIG_DRM_I2C_NXP_TDA998X=m CONFIG_DRM_MALI_DISPLAY=m CONFIG_DRM_RCAR_DW_HDMI=m -CONFIG_DRM_RCAR_LVDS=m CONFIG_DRM_PANEL_LVDS=m CONFIG_DRM_PANEL_SIMPLE=m CONFIG_DRM_PANEL_RAYDIUM_RM67191=m @@ -490,6 +489,7 @@ CONFIG_DRM_DW_HDMI_CEC=m CONFIG_DRM_PHYTIUM=y CONFIG_DRM_LEGACY=y CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_EFI=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=m CONFIG_BACKLIGHT_LP855X=m @@ -585,7 +585,6 @@ CONFIG_MMC_DW_EXYNOS=y CONFIG_MMC_DW_HI3798CV200=y CONFIG_MMC_DW_K3=y CONFIG_MMC_SDHCI_XENON=y -CONFIG_MMC_SDHCI_AM654=y # CONFIG_MMC_PHYTIUM_MCI_PCI is not set CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y @@ -764,6 +763,5 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set # CONFIG_FTRACE is not set CONFIG_MEMTEST=y diff --git a/arch/arm64/configs/phytium_k8s.config b/arch/arm64/configs/phytium_k8s.config new file mode 100644 index 0000000000000000000000000000000000000000..2aa536c5528e4afac74556140e6921c3b98d28f8 --- /dev/null +++ b/arch/arm64/configs/phytium_k8s.config @@ -0,0 +1,40 @@ +CONFIG_BRIDGE_NETFILTER=m +CONFIG_CGROUP_FREEZER=y +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_IP_VS=m +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_SH=m +CONFIG_NF_CT_NETLINK=m +CONFIG_VXLAN=m +CONFIG_DUMMY=m +CONFIG_CFS_BANDWIDTH=y +CONFIG_BFQ_GROUP_IOSCHED=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_BPF_SYSCALL=y +CONFIG_CGROUP_BPF=y +CONFIG_NET_CLS_CGROUP=m +CONFIG_CGROUP_NET_PRIO=y +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +CONFIG_XFRM_ALGO=m +CONFIG_INET_ESP=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_IPVLAN=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_RT_GROUP_SCHED=y +CONFIG_IP_SET=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m diff --git a/arch/arm64/configs/phytiumpi_firefly_defconfig b/arch/arm64/configs/phytiumpi_firefly_defconfig deleted file mode 100644 index 57011071a89af54c91cf7df879b3835c9500e913..0000000000000000000000000000000000000000 --- a/arch/arm64/configs/phytiumpi_firefly_defconfig +++ /dev/null @@ -1,738 +0,0 @@ -CONFIG_LOCALVERSION="-dovetail3-phytium-embeded-2023-v1.0-GA" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_AUDIT=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_MEMCG=y -CONFIG_BLK_CGROUP=y -CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_HUGETLB=y -CONFIG_CPUSETS=y -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y -CONFIG_USER_NS=y -CONFIG_SCHED_AUTOGROUP=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y -CONFIG_ARCH_PHYTIUM=y -CONFIG_ARM64_VA_BITS_48=y -CONFIG_SCHED_MC=y -CONFIG_SCHED_SMT=y -CONFIG_KEXEC=y -CONFIG_KEXEC_FILE=y -CONFIG_CRASH_DUMP=y -CONFIG_XEN=y -CONFIG_COMPAT=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_HIBERNATION=y -CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -CONFIG_ENERGY_MODEL=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_PSCI_CPUIDLE=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=m -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -CONFIG_CPUFREQ_DT=y -CONFIG_ACPI_CPPC_CPUFREQ=m -CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_SCMI_CPUFREQ=y -CONFIG_ARM_SCMI_PROTOCOL=y -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_EFI_CAPSULE_LOADER=y -CONFIG_ACPI=y -CONFIG_ACPI_APEI=y -CONFIG_ACPI_APEI_GHES=y -CONFIG_ACPI_APEI_MEMORY_FAILURE=y -CONFIG_ACPI_APEI_EINJ=y -CONFIG_VIRTUALIZATION=y -CONFIG_KVM=y -CONFIG_ARM64_CRYPTO=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64_CE=m -CONFIG_CRYPTO_SHA3_ARM64=m -CONFIG_CRYPTO_SM3_ARM64_CE=m -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_CHACHA20_NEON=m -CONFIG_CRYPTO_AES_ARM64_BS=m -CONFIG_KPROBES=y -CONFIG_JUMP_LABEL=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_CMDLINE_PARTITION=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_KSM=y -CONFIG_MEMORY_FAILURE=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_CMA=y -CONFIG_CMA_AREAS=19 -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IPV6=m -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m -CONFIG_BRIDGE=m -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_NET_DSA=m -CONFIG_NET_DSA_TAG_OCELOT=m -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_CBS=m -CONFIG_NET_SCH_ETF=m -CONFIG_NET_SCH_TAPRIO=m -CONFIG_NET_SCH_MQPRIO=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_U32=m -CONFIG_NET_CLS_FLOWER=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_GACT=m -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_SKBEDIT=m -CONFIG_NET_ACT_GATE=m -CONFIG_QRTR=m -CONFIG_QRTR_SMD=m -CONFIG_QRTR_TUN=m -CONFIG_BPF_JIT=y -CONFIG_CAN=m -CONFIG_CAN_FLEXCAN=m -CONFIG_CAN_PHYTIUM=m -CONFIG_CAN_PHYTIUM_PLATFORM=m -CONFIG_BT=y -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_HIDP=m -# CONFIG_BT_LE is not set -CONFIG_BT_LEDS=y -# CONFIG_BT_DEBUGFS is not set -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_3WIRE=y -CONFIG_CFG80211=y -CONFIG_CFG80211_WEXT=y -CONFIG_MAC80211=y -CONFIG_MAC80211_LEDS=y -CONFIG_RFKILL=y -CONFIG_NET_9P=y -CONFIG_NET_9P_VIRTIO=y -CONFIG_NFC=m -CONFIG_NFC_NCI=m -CONFIG_NFC_S3FWRN5_I2C=m -CONFIG_PCI=y -CONFIG_PCIEPORTBUS=y -CONFIG_HOTPLUG_PCI_PCIE=y -CONFIG_PCI_IOV=y -CONFIG_PCI_PASID=y -CONFIG_HOTPLUG_PCI=y -CONFIG_HOTPLUG_PCI_ACPI=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCI_XGENE=y -CONFIG_PCIE_ALTERA=y -CONFIG_PCIE_ALTERA_MSI=y -CONFIG_PCI_HOST_THUNDER_PEM=y -CONFIG_PCI_HOST_THUNDER_ECAM=y -CONFIG_PCIE_LAYERSCAPE_GEN4=y -CONFIG_PCI_ENDPOINT=y -CONFIG_PCI_ENDPOINT_CONFIGFS=y -CONFIG_PCI_EPF_TEST=m -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_FW_LOADER_USER_HELPER=y -CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -CONFIG_BRCMSTB_GISB_ARB=y -CONFIG_SIMPLE_PM_BUS=y -CONFIG_VEXPRESS_CONFIG=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_DATAFLASH=y -CONFIG_MTD_SST25L=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_DENALI_DT=y -CONFIG_MTD_SPI_NOR=y -CONFIG_SPI_PHYTIUM_QUADSPI=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_RAM=y -CONFIG_VIRTIO_BLK=y -CONFIG_BLK_DEV_NVME=y -CONFIG_NVME_MULTIPATH=y -CONFIG_NVME_HWMON=y -CONFIG_NVME_FC=y -CONFIG_NVME_TCP=y -CONFIG_NVME_TARGET=y -CONFIG_NVME_TARGET_PASSTHRU=y -CONFIG_NVME_TARGET_LOOP=y -CONFIG_NVME_TARGET_FC=y -CONFIG_NVME_TARGET_FCLOOP=y -CONFIG_NVME_TARGET_TCP=y -CONFIG_SRAM=y -CONFIG_PCI_ENDPOINT_TEST=m -CONFIG_EEPROM_AT24=m -CONFIG_EEPROM_AT25=m -CONFIG_UACCE=m -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -CONFIG_SCSI_SAS_LIBSAS=y -CONFIG_SCSI_SAS_ATA=y -CONFIG_MEGARAID_SAS=y -CONFIG_SCSI_MPT3SAS=m -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_ATA=y -CONFIG_SATA_AHCI=y -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_AHCI_CEVA=y -CONFIG_AHCI_XGENE=y -CONFIG_AHCI_QORIQ=y -CONFIG_SATA_SIL24=y -CONFIG_PATA_PLATFORM=y -CONFIG_PATA_OF_PLATFORM=y -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_BLK_DEV_DM=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m -CONFIG_NETDEVICES=y -CONFIG_MACVLAN=m -CONFIG_MACVTAP=m -CONFIG_TUN=y -CONFIG_VETH=m -CONFIG_VIRTIO_NET=y -CONFIG_AMD_XGBE=y -CONFIG_ATL1C=m -CONFIG_BCMGENET=m -CONFIG_BNX2X=m -CONFIG_MACB=y -CONFIG_THUNDER_NIC_PF=y -# CONFIG_NET_VENDOR_HISILICON is not set -# CONFIG_NET_VENDOR_HUAWEI is not set -CONFIG_E1000=m -CONFIG_E1000E=m -CONFIG_IGB=m -CONFIG_IGBVF=m -CONFIG_IXGB=m -CONFIG_IXGBE=m -CONFIG_IXGBEVF=m -CONFIG_I40E=m -CONFIG_I40EVF=m -CONFIG_MVMDIO=y -CONFIG_SKY2=y -CONFIG_MLX4_EN=m -CONFIG_MLX5_CORE=m -CONFIG_MLX5_CORE_EN=y -CONFIG_QCOM_EMAC=m -CONFIG_RMNET=m -CONFIG_SMC91X=y -CONFIG_SMSC911X=y -CONFIG_STMMAC_ETH=m -CONFIG_AQUANTIA_PHY=y -CONFIG_BROADCOM_PHY=m -CONFIG_MARVELL_PHY=m -CONFIG_MARVELL_10G_PHY=m -CONFIG_MICREL_PHY=y -CONFIG_MICROSEMI_PHY=y -CONFIG_AT803X_PHY=y -CONFIG_REALTEK_PHY=m -CONFIG_ROCKCHIP_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_MOTORCOMM_PHY=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_PPP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=y -CONFIG_USB_NET_AX8817X=m -CONFIG_USB_NET_AX88179_178A=m -CONFIG_USB_NET_CDCETHER=m -CONFIG_USB_NET_CDC_NCM=m -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_SR9800=m -CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=m -CONFIG_USB_NET_NET1080=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_USB_NET_CDC_SUBSET=m -CONFIG_USB_NET_ZAURUS=m -CONFIG_USB_NET_QMI_WWAN=y -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m -CONFIG_BRCMFMAC=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_PCIE=m -CONFIG_RTL_CARDS=m -CONFIG_WL18XX=m -CONFIG_WLCORE_SDIO=m -CONFIG_RTL8821CS=m -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_ADC=m -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_CROS_EC=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=m -CONFIG_INPUT_MISC=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIO_AMBAKMI=y -CONFIG_LEGACY_PTY_COUNT=16 -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_XILINX_PS_UART=y -CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y -CONFIG_SERIAL_FSL_LPUART=y -CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -CONFIG_SERIAL_FSL_LINFLEXUART=y -CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_IPMI_HANDLER=m -CONFIG_IPMI_DEVICE_INTERFACE=m -CONFIG_IPMI_SI=m -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_HISI_V2 is not set -CONFIG_HW_RANDOM_PHYTIUM=y -CONFIG_TCG_TPM=y -CONFIG_TCG_TIS_I2C_INFINEON=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_I2C_GPIO=m -CONFIG_I2C_PHYTIUM_PLATFORM=y -CONFIG_I3C=m -CONFIG_SPI=y -CONFIG_SPI_BITBANG=m -CONFIG_SPI_PHYTIUM_PLAT=y -CONFIG_SPI_SPIDEV=y -CONFIG_SPMI=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_SINGLE=y -CONFIG_PINCTRL_MAX77620=y -CONFIG_GPIO_ALTERA=m -CONFIG_GPIO_DWAPB=y -CONFIG_GPIO_MB86S7X=y -CONFIG_GPIO_PL061=y -CONFIG_GPIO_WCD934X=m -CONFIG_GPIO_XGENE=y -# CONFIG_GPIO_PHYTIUM_SGPIO is not set -CONFIG_GPIO_MAX732X=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_BD9571MWV=m -CONFIG_GPIO_MAX77620=y -CONFIG_W1=m -CONFIG_W1_SLAVE_THERM=m -CONFIG_POWER_RESET_BRCMSTB=y -CONFIG_POWER_RESET_XGENE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_SYSCON_REBOOT_MODE=y -CONFIG_BATTERY_SBS=m -CONFIG_BATTERY_BQ27XXX=y -CONFIG_SENSORS_ARM_SCMI=y -CONFIG_SENSORS_ARM_SCPI=y -CONFIG_SENSORS_LM90=m -CONFIG_SENSORS_PWM_FAN=m -CONFIG_SENSORS_INA2XX=m -CONFIG_SENSORS_INA3221=m -CONFIG_SENSORS_PHYTIUM=m -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -CONFIG_CPU_THERMAL=y -CONFIG_THERMAL_EMULATION=y -CONFIG_WATCHDOG=y -CONFIG_ARM_SP805_WATCHDOG=y -CONFIG_ARM_SBSA_WATCHDOG=y -CONFIG_DW_WATCHDOG=y -CONFIG_ARM_SMC_WATCHDOG=y -CONFIG_MFD_BD9571MWV=y -CONFIG_MFD_AXP20X_I2C=y -CONFIG_MFD_HI6421_PMIC=y -CONFIG_MFD_MAX77620=y -CONFIG_MFD_RK808=y -CONFIG_MFD_SEC_CORE=y -CONFIG_MFD_ROHM_BD718XX=y -CONFIG_MFD_WCD934X=m -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_AXP20X=y -CONFIG_REGULATOR_BD718XX=y -CONFIG_REGULATOR_BD9571MWV=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_HI6421V530=y -CONFIG_REGULATOR_MAX77620=y -CONFIG_REGULATOR_MAX8973=y -CONFIG_REGULATOR_PCA9450=y -CONFIG_REGULATOR_PFUZE100=y -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_QCOM_SPMI=y -CONFIG_REGULATOR_RK808=y -CONFIG_REGULATOR_S2MPS11=y -CONFIG_REGULATOR_VCTRL=m -CONFIG_RC_CORE=m -CONFIG_RC_DECODERS=y -CONFIG_RC_DEVICES=y -CONFIG_MEDIA_SUPPORT=m -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -CONFIG_MEDIA_SDR_SUPPORT=y -CONFIG_MEDIA_PLATFORM_SUPPORT=y -# CONFIG_DVB_NET is not set -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_SDR_PLATFORM_DRIVERS=y -CONFIG_VIDEO_IMX219=m -CONFIG_VIDEO_OV5645=m -CONFIG_DRM=y -CONFIG_DRM_I2C_CH7006=m -CONFIG_DRM_I2C_SIL164=m -CONFIG_DRM_I2C_NXP_TDA998X=m -CONFIG_DRM_MALI_DISPLAY=m -CONFIG_DRM_RCAR_DW_HDMI=m -CONFIG_DRM_RCAR_LVDS=m -CONFIG_DRM_PANEL_LVDS=m -CONFIG_DRM_PANEL_SIMPLE=m -CONFIG_DRM_PANEL_RAYDIUM_RM67191=m -CONFIG_DRM_PANEL_SITRONIX_ST7703=m -CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m -CONFIG_DRM_DISPLAY_CONNECTOR=m -CONFIG_DRM_LONTIUM_LT9611=m -CONFIG_DRM_NWL_MIPI_DSI=m -CONFIG_DRM_SII902X=m -CONFIG_DRM_SIMPLE_BRIDGE=m -CONFIG_DRM_THINE_THC63LVD1024=m -CONFIG_DRM_TI_SN65DSI86=m -CONFIG_DRM_I2C_ADV7511=m -CONFIG_DRM_I2C_ADV7511_AUDIO=y -CONFIG_DRM_DW_HDMI_AHB_AUDIO=m -CONFIG_DRM_DW_HDMI_I2S_AUDIO=m -CONFIG_DRM_DW_HDMI_CEC=m -CONFIG_DRM_PHYTIUM=y -CONFIG_DRM_LEGACY=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_EFI=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=m -CONFIG_BACKLIGHT_LP855X=m -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_HDA_INTEL=m -CONFIG_SND_HDA_HWDEP=y -CONFIG_SND_HDA_INPUT_BEEP=y -CONFIG_SND_HDA_PATCH_LOADER=y -CONFIG_SND_HDA_CODEC_REALTEK=m -CONFIG_SND_HDA_CODEC_HDMI=m -CONFIG_SND_SOC=y -CONFIG_SND_SOC_FSL_SAI=m -CONFIG_SND_SOC_PHYTIUM_I2S=y -CONFIG_SND_PMDK_ES8388=y -CONFIG_SND_PMDK_ES8336=y -CONFIG_SND_PMDK_DP=y -CONFIG_SND_SOC_AK4613=m -CONFIG_SND_SOC_CROS_EC_CODEC=m -CONFIG_SND_SOC_DMIC=m -CONFIG_SND_SOC_ES7134=m -CONFIG_SND_SOC_ES7241=m -CONFIG_SND_SOC_MAX98357A=m -CONFIG_SND_SOC_MAX98927=m -CONFIG_SND_SOC_PCM3168A_I2C=m -CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m -CONFIG_SND_SOC_SPDIF=m -CONFIG_SND_SOC_TAS571X=m -CONFIG_SND_SOC_WCD934X=m -CONFIG_SND_SOC_WM8904=m -CONFIG_SND_SOC_WSA881X=m -CONFIG_SND_SIMPLE_CARD=y -CONFIG_SND_AUDIO_GRAPH_CARD=y -CONFIG_I2C_HID=m -CONFIG_USB_CONN_GPIO=y -CONFIG_USB=y -CONFIG_USB_OTG=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_ACM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC2=y -CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_UDC=y -CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_ISP1760=y -CONFIG_USB_PHYTIUM=y -CONFIG_USB_SERIAL=y -CONFIG_USB_SERIAL_CH341=y -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_OPTION=y -CONFIG_USB_HSIC_USB3503=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_SNP_UDC_PLAT=y -CONFIG_USB_BDC_UDC=y -CONFIG_USB_CONFIGFS=m -CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_ACM=y -CONFIG_USB_CONFIGFS_OBEX=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_ECM=y -CONFIG_USB_CONFIGFS_ECM_SUBSET=y -CONFIG_USB_CONFIGFS_RNDIS=y -CONFIG_USB_CONFIGFS_EEM=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_TYPEC=m -CONFIG_TYPEC_TCPM=m -CONFIG_TYPEC_FUSB302=m -CONFIG_TYPEC_HD3SS3220=m -CONFIG_MMC=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_ARMMMCI=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ACPI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_OF_ARASAN=y -CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_MMC_SDHCI_F_SDH30=y -CONFIG_MMC_SPI=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_EXYNOS=y -CONFIG_MMC_DW_HI3798CV200=y -CONFIG_MMC_DW_K3=y -CONFIG_MMC_SDHCI_XENON=y -CONFIG_MMC_SDHCI_AM654=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_EDAC=y -CONFIG_EDAC_GHES=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1307=m -CONFIG_RTC_DRV_MAX77686=y -CONFIG_RTC_DRV_RK808=m -CONFIG_RTC_DRV_PCF85363=m -CONFIG_RTC_DRV_RX8581=m -CONFIG_RTC_DRV_RV8803=m -CONFIG_RTC_DRV_S5M=y -CONFIG_RTC_DRV_SD3068=m -CONFIG_RTC_DRV_DS3232=y -CONFIG_RTC_DRV_PCF2127=m -CONFIG_RTC_DRV_EFI=y -CONFIG_RTC_DRV_CROS_EC=y -CONFIG_RTC_DRV_PL031=y -CONFIG_DMADEVICES=y -CONFIG_BCM_SBA_RAID=m -CONFIG_FSL_EDMA=y -CONFIG_MV_XOR_V2=y -CONFIG_PL330_DMA=y -CONFIG_UIO=m -CONFIG_UIO_CIF=m -CONFIG_UIO_PDRV_GENIRQ=m -CONFIG_UIO_DMEM_GENIRQ=m -CONFIG_UIO_AEC=m -CONFIG_UIO_SERCOS3=m -CONFIG_UIO_PCI_GENERIC=m -CONFIG_UIO_NETX=m -CONFIG_UIO_PRUSS=m -CONFIG_UIO_MF624=m -CONFIG_VFIO=y -CONFIG_VFIO_PCI=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_MMIO=y -CONFIG_XEN_GNTDEV=y -CONFIG_XEN_GRANT_DEV_ALLOC=y -CONFIG_STAGING=y -CONFIG_CHROME_PLATFORMS=y -CONFIG_CROS_EC=y -CONFIG_CROS_EC_I2C=y -CONFIG_CROS_EC_SPI=y -CONFIG_CROS_EC_CHARDEV=m -CONFIG_COMMON_CLK_RK808=y -CONFIG_COMMON_CLK_SCPI=y -CONFIG_COMMON_CLK_CS2000_CP=y -CONFIG_COMMON_CLK_S2MPS11=y -CONFIG_CLK_QORIQ=y -CONFIG_COMMON_CLK_XGENE=y -CONFIG_COMMON_CLK_PWM=y -CONFIG_COMMON_CLK_VC5=y -CONFIG_COMMON_CLK_BD718XX=m -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_PHYTIUM=y -CONFIG_ARM_MHU=y -CONFIG_PLATFORM_MHU=y -CONFIG_PHYTIUM_MBOX=y -CONFIG_ARM_SMMU=y -CONFIG_ARM_SMMU_V3=y -CONFIG_REMOTEPROC=y -CONFIG_RPMSG_QCOM_GLINK_RPM=y -CONFIG_SOUNDWIRE=m -CONFIG_SOUNDWIRE_QCOM=m -CONFIG_SOC_BRCMSTB=y -CONFIG_SOC_TI=y -CONFIG_EXTCON_PTN5150=m -CONFIG_EXTCON_USB_GPIO=y -CONFIG_EXTCON_USBC_CROS_EC=y -CONFIG_MEMORY=y -CONFIG_IIO=y -CONFIG_MAX9611=m -CONFIG_QCOM_SPMI_ADC5=m -CONFIG_PHYTIUM_ADC=m -CONFIG_IIO_CROS_EC_SENSORS_CORE=m -CONFIG_IIO_CROS_EC_SENSORS=m -CONFIG_IIO_CROS_EC_LIGHT_PROX=m -CONFIG_SENSORS_ISL29018=m -CONFIG_IIO_CROS_EC_BARO=m -CONFIG_MPL3115=m -CONFIG_PWM=y -CONFIG_PWM_CROS_EC=m -CONFIG_PWM_PHYTIUM=m -CONFIG_PHY_XGENE=y -CONFIG_PHY_FSL_IMX8MQ_USB=y -CONFIG_PHY_MIXEL_MIPI_DPHY=m -CONFIG_PHY_QCOM_USB_HS=y -CONFIG_PHY_SAMSUNG_USB2=y -CONFIG_ARM_SMMU_V3_PMU=m -CONFIG_FPGA=y -CONFIG_FPGA_BRIDGE=m -CONFIG_ALTERA_FREEZE_BRIDGE=m -CONFIG_FPGA_REGION=m -CONFIG_OF_FPGA_REGION=m -CONFIG_MUX_MMIO=y -CONFIG_SLIM_QCOM_CTRL=m -CONFIG_INTERCONNECT=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_BTRFS_FS=m -CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_EXPORTFS_BLOCK_OPS=y -CONFIG_FANOTIFY=y -CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -CONFIG_QUOTA=y -CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=m -CONFIG_CUSE=m -CONFIG_OVERLAY_FS=m -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_HUGETLBFS=y -CONFIG_EFIVAR_FS=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_XATTR=y -CONFIG_SQUASHFS_LZ4=y -CONFIG_SQUASHFS_LZO=y -CONFIG_SQUASHFS_XZ=y -CONFIG_SQUASHFS_ZSTD=y -CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y -CONFIG_SQUASHFS_EMBEDDED=y -CONFIG_NFS_FS=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_ROOT_NFS=y -CONFIG_9P_FS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_SECURITY=y -CONFIG_CRYPTO_USER=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_ANSI_CPRNG=y -CONFIG_CRYPTO_DRBG_HASH=y -CONFIG_CRYPTO_USER_API_HASH=y -CONFIG_CRYPTO_USER_API_SKCIPHER=y -CONFIG_CRYPTO_USER_API_RNG=m -CONFIG_CRYPTO_USER_API_AEAD=y -CONFIG_CRYPTO_DEV_CCREE=m -CONFIG_CRYPTO_DEV_HISI_SEC2=m -CONFIG_CRYPTO_DEV_HISI_ZIP=m -CONFIG_CRYPTO_DEV_HISI_HPRE=m -CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m -CONFIG_INDIRECT_PIO=y -CONFIG_DMA_CMA=y -CONFIG_DMA_PERNUMA_CMA=y -CONFIG_CMA_SIZE_MBYTES=32 -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_FTRACE is not set -CONFIG_MEMTEST=y diff --git a/drivers/char/hw_random/phytium-rng.c b/drivers/char/hw_random/phytium-rng.c index 5b5e896516b934288ac9f69605069112f3a37fc4..f8ab17f33d0b7a49263abecd977f4201a7757630 100644 --- a/drivers/char/hw_random/phytium-rng.c +++ b/drivers/char/hw_random/phytium-rng.c @@ -2,7 +2,7 @@ /* * Phytium SoC RNG Driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/char/ipmi/bt_bmc_phytium.c b/drivers/char/ipmi/bt_bmc_phytium.c index 8d650475b63581df2601c3aff025b5e2a52da3a4..d66b6b3dd9c6ac523d2bccb681caf3fe06d502be 100755 --- a/drivers/char/ipmi/bt_bmc_phytium.c +++ b/drivers/char/ipmi/bt_bmc_phytium.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. * * Derived from drivers/char/ipmi/bt-bmc.c * Copyright (c) 2015-2016, IBM Corporation. diff --git a/drivers/char/ipmi/kcs_bmc_phytium.c b/drivers/char/ipmi/kcs_bmc_phytium.c index 17e29f6e4e6370694c47492f453aeece66aa306a..f3f9f0aac2db9ff61c602d3bed68539f3aa56a57 100755 --- a/drivers/char/ipmi/kcs_bmc_phytium.c +++ b/drivers/char/ipmi/kcs_bmc_phytium.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. * * Derived from drivers/char/ipmi/kcs_bmc_aspeed.c * Copyright (c) 2015-2018, Intel Corporation. diff --git a/drivers/dma/phytium/phytium-ddmac.c b/drivers/dma/phytium/phytium-ddmac.c index 9ff66bdc96e5821fed02b3379955bdbdb67de64b..734c8a9c680b847f6f848e34657d02338dc68ef1 100644 --- a/drivers/dma/phytium/phytium-ddmac.c +++ b/drivers/dma/phytium/phytium-ddmac.c @@ -2,7 +2,7 @@ /* * Phytium Device DDMA Controller driver. * - * Copyright (c) 2023 Phytium Technology Co., Ltd. + * Copyright (c) 2023-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/dma/phytium/phytium-ddmac.h b/drivers/dma/phytium/phytium-ddmac.h index 81bc0e19e64961ad83abe8ba1f3462eeca50d473..3f02cfd741516ffbdf321764e3c48cd618d18d4f 100644 --- a/drivers/dma/phytium/phytium-ddmac.h +++ b/drivers/dma/phytium/phytium-ddmac.h @@ -2,7 +2,7 @@ /* * Phytium Device DDMA Controller driver. * - * Copyright (c) 2023 Phytium Technology Co., Ltd. + * Copyright (c) 2023-2024 Phytium Technology Co., Ltd. */ #ifndef _PHYTIUM_DDMAC_H diff --git a/drivers/edac/phytium_edac.c b/drivers/edac/phytium_edac.c index d16ac658d780b96c5632f016c6ef267b114dc19e..2d9b2dda1958b3bc24aeca291cccc539cc6983ab 100644 --- a/drivers/edac/phytium_edac.c +++ b/drivers/edac/phytium_edac.c @@ -2,7 +2,7 @@ /* * Phytium Pe220x EDAC (error detection and correction) * - * Copyright (c) 2023 Phytium Technology Co., Ltd. + * Copyright (c) 2023-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/firmware/arm_scmi/common.h b/drivers/firmware/arm_scmi/common.h index 34b7ae7980a3eba243b8521843155dbadaf03a90..70bdb9872ac58e1332d04c35c2d901b7fa34f6f3 100644 --- a/drivers/firmware/arm_scmi/common.h +++ b/drivers/firmware/arm_scmi/common.h @@ -139,6 +139,7 @@ struct scmi_xfer { struct scmi_msg rx; struct completion done; struct completion *async_done; + spinlock_t lock; }; void scmi_xfer_put(const struct scmi_handle *h, struct scmi_xfer *xfer); diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index 90f669ae8d9117a1f1cb3d4016d31c7cac5a1424..f2fcb76a77a259e577ce175d012bd4f282d2e7d5 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -98,10 +98,6 @@ struct scmi_info { int users; }; -#ifdef CONFIG_ARM_SCMI_TRANSPORT_FORCE_POLLING -static bool scmi_force_polling; -#endif - #define handle_to_scmi_info(h) container_of(h, struct scmi_info, handle) static const int scmi_linux_errmap[] = { @@ -337,8 +333,6 @@ void scmi_xfer_put(const struct scmi_handle *handle, struct scmi_xfer *xfer) __scmi_xfer_put(&info->tx_minfo, xfer); } -#define SCMI_MAX_POLL_TO_NS (100 * NSEC_PER_USEC) - static bool scmi_xfer_done_no_timeout(struct scmi_chan_info *cinfo, struct scmi_xfer *xfer, ktime_t stop) { @@ -348,15 +342,6 @@ static bool scmi_xfer_done_no_timeout(struct scmi_chan_info *cinfo, ktime_after(ktime_get(), stop); } - -#ifdef CONFIG_ARM_SCMI_TRANSPORT_FORCE_POLLING -static int __init scmi_set_force_polling(char *str) -{ - return kstrtobool(str, &scmi_force_polling); -} -early_param("scmi.force_polling", scmi_set_force_polling); -#endif - /** * scmi_do_xfer() - Do one transfer * @@ -374,14 +359,14 @@ int scmi_do_xfer(const struct scmi_handle *handle, struct scmi_xfer *xfer) struct scmi_info *info = handle_to_scmi_info(handle); struct device *dev = info->dev; struct scmi_chan_info *cinfo; + unsigned long flags; cinfo = idr_find(&info->tx_idr, xfer->hdr.protocol_id); if (unlikely(!cinfo)) return -EINVAL; #ifdef CONFIG_ARM_SCMI_TRANSPORT_FORCE_POLLING - if (scmi_force_polling) - xfer->hdr.poll_completion = true; + xfer->hdr.poll_completion = true; #endif trace_scmi_xfer_begin(xfer->transfer_id, xfer->hdr.id, @@ -395,7 +380,11 @@ int scmi_do_xfer(const struct scmi_handle *handle, struct scmi_xfer *xfer) } if (xfer->hdr.poll_completion) { - ktime_t stop = ktime_add_ns(ktime_get(), SCMI_MAX_POLL_TO_NS); + ktime_t stop; + + spin_lock_irqsave(&xfer->lock, flags); + stop = ktime_add_ms(ktime_get(), + info->desc->max_rx_timeout_ms); spin_until_cond(scmi_xfer_done_no_timeout(cinfo, xfer, stop)); @@ -403,6 +392,7 @@ int scmi_do_xfer(const struct scmi_handle *handle, struct scmi_xfer *xfer) info->desc->ops->fetch_response(cinfo, xfer); else ret = -ETIMEDOUT; + spin_unlock_irqrestore(&xfer->lock, flags); } else { /* And we wait for the response. */ timeout = msecs_to_jiffies(info->desc->max_rx_timeout_ms); @@ -663,6 +653,7 @@ static int __scmi_xfer_info_init(struct scmi_info *sinfo, xfer->tx.buf = xfer->rx.buf; init_completion(&xfer->done); + spin_lock_init(&xfer->lock); } spin_lock_init(&info->xfer_lock); diff --git a/drivers/gpio/gpio-phytium-core.c b/drivers/gpio/gpio-phytium-core.c index 648e564dffc0e9a3b548a90dcf5b23ea8b874dc6..a1794f55a5a01971c14f2eba779d9bf3c6847c8d 100644 --- a/drivers/gpio/gpio-phytium-core.c +++ b/drivers/gpio/gpio-phytium-core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpio/gpio-phytium-core.h b/drivers/gpio/gpio-phytium-core.h index cafca7807e278289b2a30913edcfd4b20bc5834f..d45a9ab11944bff8b98efdab1b80893831454b3d 100644 --- a/drivers/gpio/gpio-phytium-core.h +++ b/drivers/gpio/gpio-phytium-core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef _GPIO_PHYTIUM_H diff --git a/drivers/gpio/gpio-phytium-pci.c b/drivers/gpio/gpio-phytium-pci.c index 60563c59ae6028e8924206d505ed480f0117f032..e68772dd7a88be0628b72ebe5067f5ededa239f4 100644 --- a/drivers/gpio/gpio-phytium-pci.c +++ b/drivers/gpio/gpio-phytium-pci.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpio/gpio-phytium-platform.c b/drivers/gpio/gpio-phytium-platform.c index 86c67970053c738abce09f6eb113f961fde9b17c..81fb0846210a0d41c6474aa7a4ffc2d8e15701b4 100644 --- a/drivers/gpio/gpio-phytium-platform.c +++ b/drivers/gpio/gpio-phytium-platform.c @@ -2,7 +2,7 @@ /* * Support functions for Phytium GPIO * - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. * * Derived from drivers/gpio/gpio-pl061.c * Copyright (C) 2008, 2009 Provigent Ltd. diff --git a/drivers/gpio/gpio-phytium-sgpio.c b/drivers/gpio/gpio-phytium-sgpio.c index 689cb10843e681f8af74add647446211a00f5589..4785ca45f79ec4e0d1ef160cbf7a47b1a86dd2ea 100644 --- a/drivers/gpio/gpio-phytium-sgpio.c +++ b/drivers/gpio/gpio-phytium-sgpio.c @@ -2,7 +2,7 @@ /* * Phytium SGPIO Driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/pe220x_dc.c b/drivers/gpu/drm/phytium/pe220x_dc.c index 6bb18f0fdb19af730c428f4a2ba9275f59066d44..b465dbb615f16fe947564316141186cc0fe4e100 100644 --- a/drivers/gpu/drm/phytium/pe220x_dc.c +++ b/drivers/gpu/drm/phytium/pe220x_dc.c @@ -2,7 +2,7 @@ /* * Phytium Pe220x display controller DRM driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/pe220x_dc.h b/drivers/gpu/drm/phytium/pe220x_dc.h index 76b6700a40a1580af79c93bcdf0075e3a27f8978..5840795cbae61fa97140e5167d2bda960a5fdc65 100644 --- a/drivers/gpu/drm/phytium/pe220x_dc.h +++ b/drivers/gpu/drm/phytium/pe220x_dc.h @@ -2,7 +2,7 @@ /* * Phytium Pe220x display controller DRM driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PE220X_DC_H__ diff --git a/drivers/gpu/drm/phytium/pe220x_dp.c b/drivers/gpu/drm/phytium/pe220x_dp.c index 19f38fc01106cc3ae33f42f9ee37407df13b3c4f..08597ae2f2aac1b934cf8c1e063622dbd25b5d40 100644 --- a/drivers/gpu/drm/phytium/pe220x_dp.c +++ b/drivers/gpu/drm/phytium/pe220x_dp.c @@ -2,7 +2,7 @@ /* * Phytium display port DRM driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include "phytium_display_drv.h" diff --git a/drivers/gpu/drm/phytium/pe220x_dp.h b/drivers/gpu/drm/phytium/pe220x_dp.h index a79bf5b5e3ab8d70ccd1d2f683e916a96fee2ae7..78bb26c7b75cc3fb90bee1e85a30dd269a582adc 100644 --- a/drivers/gpu/drm/phytium/pe220x_dp.h +++ b/drivers/gpu/drm/phytium/pe220x_dp.h @@ -2,7 +2,7 @@ /* * Phytium display port DRM driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PE220X_DP_H__ diff --git a/drivers/gpu/drm/phytium/pe220x_reg.h b/drivers/gpu/drm/phytium/pe220x_reg.h index 8dfbd41a5350ff4b61c5714eb825fa78297e515d..696be3006734fb5633558e9dde25c78ffdcdfeb0 100644 --- a/drivers/gpu/drm/phytium/pe220x_reg.h +++ b/drivers/gpu/drm/phytium/pe220x_reg.h @@ -2,7 +2,7 @@ /* * Phytium Pe220x display engine register * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PE220X_REG_H__ diff --git a/drivers/gpu/drm/phytium/phytium_crtc.c b/drivers/gpu/drm/phytium/phytium_crtc.c index f2ed42d6bd87f37e1f9c0bb6f08463d3d0d227ad..567c5251db00fa28c7224351ead22c67f3958dbd 100644 --- a/drivers/gpu/drm/phytium/phytium_crtc.c +++ b/drivers/gpu/drm/phytium/phytium_crtc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/phytium_crtc.h b/drivers/gpu/drm/phytium/phytium_crtc.h index 86f894ba5d7068277f11630ae1922f2be1a6d6a4..8c5b2eb0ec0a25d0ca9df18a3f6684387d8e0a91 100644 --- a/drivers/gpu/drm/phytium/phytium_crtc.h +++ b/drivers/gpu/drm/phytium/phytium_crtc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_CRTC_H__ diff --git a/drivers/gpu/drm/phytium/phytium_debugfs.c b/drivers/gpu/drm/phytium/phytium_debugfs.c index 13657a76812f61de54ce631c500546b831a00965..8cd6c338d28c0e5efffd1af910399aae767e1222 100644 --- a/drivers/gpu/drm/phytium/phytium_debugfs.c +++ b/drivers/gpu/drm/phytium/phytium_debugfs.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/phytium_debugfs.h b/drivers/gpu/drm/phytium/phytium_debugfs.h index aa8e2922ec257ec465d02657c0c81d40405f2177..7e632bf9c521cc02340b439b9e7e106389e03794 100644 --- a/drivers/gpu/drm/phytium/phytium_debugfs.h +++ b/drivers/gpu/drm/phytium/phytium_debugfs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_DEBUGFS_H__ diff --git a/drivers/gpu/drm/phytium/phytium_display_drv.c b/drivers/gpu/drm/phytium/phytium_display_drv.c index d3c654b427c09b6b401fa4162932285ff9d93247..5a22116e1a73b584fa8c2ce440968a19aef1b654 100644 --- a/drivers/gpu/drm/phytium/phytium_display_drv.c +++ b/drivers/gpu/drm/phytium/phytium_display_drv.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/phytium_display_drv.h b/drivers/gpu/drm/phytium/phytium_display_drv.h index ee1d0e0fab86f968779166af89b35fd936588f63..f36fff9b875458dd79e4ac13bc6e9c6a660ee8f9 100644 --- a/drivers/gpu/drm/phytium/phytium_display_drv.h +++ b/drivers/gpu/drm/phytium/phytium_display_drv.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_DISPLAY_DRV_H__ diff --git a/drivers/gpu/drm/phytium/phytium_dp.c b/drivers/gpu/drm/phytium/phytium_dp.c index 96fe440cd06ca8ba58377e101fba700c7d1fb308..7eefd69766a7d8c2aa7dc21ca78094a1ae5bac97 100644 --- a/drivers/gpu/drm/phytium/phytium_dp.c +++ b/drivers/gpu/drm/phytium/phytium_dp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/phytium_dp.h b/drivers/gpu/drm/phytium/phytium_dp.h index 3433f294424bb5def8c798c857feb14a1ed28c6c..047357a0d523be1d073fe1c5192cce3f4aa8a447 100644 --- a/drivers/gpu/drm/phytium/phytium_dp.h +++ b/drivers/gpu/drm/phytium/phytium_dp.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_DP_H__ diff --git a/drivers/gpu/drm/phytium/phytium_fb.c b/drivers/gpu/drm/phytium/phytium_fb.c index 724c02720d6b2c0feb60eb35bce7be237e4f5cfe..feb17920a9861a45dc822fec7e0ee668ba4aaf18 100644 --- a/drivers/gpu/drm/phytium/phytium_fb.c +++ b/drivers/gpu/drm/phytium/phytium_fb.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -62,6 +62,9 @@ phytium_fb_alloc(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd drm_helper_mode_fill_fb_struct(dev, &phytium_fb->base, mode_cmd); + /* In UEFI, efifb may also use dc hardware, remove it and use dcdrmfb */ + drm_fb_helper_remove_conflicting_framebuffers(NULL, "dcdrmfb", false); + ret = drm_framebuffer_init(dev, &phytium_fb->base, &viv_fb_funcs); if (ret) { diff --git a/drivers/gpu/drm/phytium/phytium_fb.h b/drivers/gpu/drm/phytium/phytium_fb.h index 054b0ab15a00b2c32b8fa36566f42dd087ac1672..eb7903f3a10a4f04b36c0f39221a0a065ca20752 100644 --- a/drivers/gpu/drm/phytium/phytium_fb.h +++ b/drivers/gpu/drm/phytium/phytium_fb.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_FB_H__ diff --git a/drivers/gpu/drm/phytium/phytium_fbdev.c b/drivers/gpu/drm/phytium/phytium_fbdev.c index dd0c2920813200782ad3a1e7ea39fcd17ea14e3a..a74b2d08180f126ae99b23f274243cea3a7fc2f8 100644 --- a/drivers/gpu/drm/phytium/phytium_fbdev.c +++ b/drivers/gpu/drm/phytium/phytium_fbdev.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/phytium_fbdev.h b/drivers/gpu/drm/phytium/phytium_fbdev.h index 81070502c8e07a210f50bf4f7b0a967afd388633..ff63ba84d7728c76635193db762b627ba4a0ac42 100644 --- a/drivers/gpu/drm/phytium/phytium_fbdev.h +++ b/drivers/gpu/drm/phytium/phytium_fbdev.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef _PHYTIUM_FBDEV_H diff --git a/drivers/gpu/drm/phytium/phytium_gem.c b/drivers/gpu/drm/phytium/phytium_gem.c index cc51b0f96d22d737e90b6f680324cfd637c7be54..03a3070a3a564d9bb97c71cd52a0c2520a08f4cf 100644 --- a/drivers/gpu/drm/phytium/phytium_gem.c +++ b/drivers/gpu/drm/phytium/phytium_gem.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/phytium_gem.h b/drivers/gpu/drm/phytium/phytium_gem.h index cd34f4a4539f97ef698b3a293863be6df23740fb..50fb4f4f7b6b6f80a77958671d0dc1bf677332b3 100644 --- a/drivers/gpu/drm/phytium/phytium_gem.h +++ b/drivers/gpu/drm/phytium/phytium_gem.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_GEM_H__ diff --git a/drivers/gpu/drm/phytium/phytium_panel.c b/drivers/gpu/drm/phytium/phytium_panel.c index 16783b24a4d374bdfaac23275ce1a36269544058..efb839ae02ea78a3092f5d098b13299da8217169 100644 --- a/drivers/gpu/drm/phytium/phytium_panel.c +++ b/drivers/gpu/drm/phytium/phytium_panel.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/phytium_panel.h b/drivers/gpu/drm/phytium/phytium_panel.h index 91760e26dcf18636b5ddea494b178daf7e383d35..ff4d760d8400766e932fe7657ed82412f9665e83 100644 --- a/drivers/gpu/drm/phytium/phytium_panel.h +++ b/drivers/gpu/drm/phytium/phytium_panel.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_PANEL_H__ diff --git a/drivers/gpu/drm/phytium/phytium_pci.c b/drivers/gpu/drm/phytium/phytium_pci.c index 22e4fd79b2d6667e8e83ef33a532ebe8380af825..51c4397d609e180589cda1f7c85b581027b1af73 100644 --- a/drivers/gpu/drm/phytium/phytium_pci.c +++ b/drivers/gpu/drm/phytium/phytium_pci.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/phytium_pci.h b/drivers/gpu/drm/phytium/phytium_pci.h index ad116dfcb5e97921f06c2c5cf157f547106b4993..7ac37971759c812d67f9e22768745394d6ad020a 100644 --- a/drivers/gpu/drm/phytium/phytium_pci.h +++ b/drivers/gpu/drm/phytium/phytium_pci.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_PCI_H__ diff --git a/drivers/gpu/drm/phytium/phytium_plane.c b/drivers/gpu/drm/phytium/phytium_plane.c index 950db0487bc7003dc46a9f72fb45f62c6a7d5693..813944676d3cec312230508d8e6709f2b6bb52a6 100644 --- a/drivers/gpu/drm/phytium/phytium_plane.c +++ b/drivers/gpu/drm/phytium/phytium_plane.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/phytium_plane.h b/drivers/gpu/drm/phytium/phytium_plane.h index ee8786ced54ca0a4ec20b8d7c9b8ebc651f80d3f..25b6bba6c87d3b815e6c30b6f4e553dde33b851e 100644 --- a/drivers/gpu/drm/phytium/phytium_plane.h +++ b/drivers/gpu/drm/phytium/phytium_plane.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_PLANE_H__ diff --git a/drivers/gpu/drm/phytium/phytium_platform.c b/drivers/gpu/drm/phytium/phytium_platform.c index 27815ecc9c500733d725a55a5b9f42bb62b1bbba..c2c80d69a9cf02ba70932c45ec71a3c1932285e0 100644 --- a/drivers/gpu/drm/phytium/phytium_platform.c +++ b/drivers/gpu/drm/phytium/phytium_platform.c @@ -2,10 +2,11 @@ /* * Phytium display engine DRM driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include +#include #include #include #include @@ -19,13 +20,29 @@ int phytium_platform_carveout_mem_init(struct platform_device *pdev, struct phytium_display_private *priv) { - struct resource *res; + struct device_node *np; + struct resource res; + struct resource *pres; int ret = 0; - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (res) { - priv->pool_size = resource_size(res); - priv->pool_phys_addr = res->start; + if (pdev->dev.of_node) { + np = of_parse_phandle(pdev->dev.of_node, "memory-region", 0); + if(!np) + goto next; + ret = of_address_to_resource(np, 0, &res); + if(ret) + DRM_ERROR("No memory address assigned to the region\n"); + else { + priv->pool_size = resource_size(&res); + priv->pool_phys_addr = res.start; + } + } + +next: + pres = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (pres) { + priv->pool_size = resource_size(pres); + priv->pool_phys_addr = pres->start; } if ((priv->pool_phys_addr != 0) && (priv->pool_size != 0)) { diff --git a/drivers/gpu/drm/phytium/phytium_platform.h b/drivers/gpu/drm/phytium/phytium_platform.h index e752f79130db5e4c4a1d525c79992b12aecff580..b754ef0a137a3a21a45c62c9aa313b0c6aee18d1 100644 --- a/drivers/gpu/drm/phytium/phytium_platform.h +++ b/drivers/gpu/drm/phytium/phytium_platform.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_PLATFORM_H__ diff --git a/drivers/gpu/drm/phytium/phytium_reg.h b/drivers/gpu/drm/phytium/phytium_reg.h index 28735acee149ac650956fb8dabf2c20d39969bc5..4dca6c02312792035be8bc57d1f68ebd0420011d 100644 --- a/drivers/gpu/drm/phytium/phytium_reg.h +++ b/drivers/gpu/drm/phytium/phytium_reg.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_REG_H__ diff --git a/drivers/gpu/drm/phytium/px210_dc.c b/drivers/gpu/drm/phytium/px210_dc.c index 5c55f223ef573125e703356fb673082c51b6b396..84fd44a130f07910e324365c911744a203bcf6d5 100644 --- a/drivers/gpu/drm/phytium/px210_dc.c +++ b/drivers/gpu/drm/phytium/px210_dc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/gpu/drm/phytium/px210_dc.h b/drivers/gpu/drm/phytium/px210_dc.h index acb2dd6cb5c9039a8dead8296f6a77f695d3f98f..ef2208bf4f3019e464854831581ac5321aba2a0d 100644 --- a/drivers/gpu/drm/phytium/px210_dc.h +++ b/drivers/gpu/drm/phytium/px210_dc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PX210_DC_H__ diff --git a/drivers/gpu/drm/phytium/px210_dp.c b/drivers/gpu/drm/phytium/px210_dp.c index d7bd04eac2a84714ece2694d94c04c37e3e39667..7c655563132a83c0b615ee12d1768d1b702f5056 100644 --- a/drivers/gpu/drm/phytium/px210_dp.c +++ b/drivers/gpu/drm/phytium/px210_dp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include "phytium_display_drv.h" diff --git a/drivers/gpu/drm/phytium/px210_dp.h b/drivers/gpu/drm/phytium/px210_dp.h index 4ad65397f1aa23a40e5591981563dcfd7baae527..07e40265f02c894f5e789250c29ec37622679ef8 100644 --- a/drivers/gpu/drm/phytium/px210_dp.h +++ b/drivers/gpu/drm/phytium/px210_dp.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PX210_DP_H__ diff --git a/drivers/gpu/drm/phytium/px210_reg.h b/drivers/gpu/drm/phytium/px210_reg.h index 5556b3ee5c1db894844687520371979380c20e70..dbe1e537fc4a9db8e0aa5bbfc6686751a5e0bd6b 100644 --- a/drivers/gpu/drm/phytium/px210_reg.h +++ b/drivers/gpu/drm/phytium/px210_reg.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium display drm driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PX210_REG_H__ diff --git a/drivers/hwmon/tacho-phytium.c b/drivers/hwmon/tacho-phytium.c index cbfbe0b8250f548463c1ffa159621fb58f8b74d2..c89251f3595a3a3146832e735d6ef06ebd932d46 100644 --- a/drivers/hwmon/tacho-phytium.c +++ b/drivers/hwmon/tacho-phytium.c @@ -2,7 +2,7 @@ /* * Hwmon driver for Phytium tachometer. * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/hwspinlock/phytium_hwspinlock.c b/drivers/hwspinlock/phytium_hwspinlock.c index cea34c51afe3d7f8136869665dd260e99ca38498..e3af7347ee867cc7db95f766c877939cd16fce47 100644 --- a/drivers/hwspinlock/phytium_hwspinlock.c +++ b/drivers/hwspinlock/phytium_hwspinlock.c @@ -2,7 +2,7 @@ /* * Phytium hardware spinlock driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/i2c/busses/i2c-phytium-common.c b/drivers/i2c/busses/i2c-phytium-common.c index 5c3ee375846c2fe6778b00ef911c404198d7d6d6..d5f1ce24695fa0cc09425db28ec50479851b95e3 100644 --- a/drivers/i2c/busses/i2c-phytium-common.c +++ b/drivers/i2c/busses/i2c-phytium-common.c @@ -4,7 +4,7 @@ * * Based on the TI DAVINCI I2C adapter driver. * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include #include diff --git a/drivers/i2c/busses/i2c-phytium-core.h b/drivers/i2c/busses/i2c-phytium-core.h index de07ae71870bbc68b68efbae2ef29d4ce9b42f4f..726a4f9f4f17285c1a60be38f047d4419df5c24c 100644 --- a/drivers/i2c/busses/i2c-phytium-core.h +++ b/drivers/i2c/busses/i2c-phytium-core.h @@ -2,7 +2,7 @@ /* * Phytium I2C adapter driver. * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/i2c/busses/i2c-phytium-master.c b/drivers/i2c/busses/i2c-phytium-master.c index 9cab525020ab4985b64ae36d568634ef13faaffc..b478e5a53b2f629f517986760181416acb4dd5e8 100644 --- a/drivers/i2c/busses/i2c-phytium-master.c +++ b/drivers/i2c/busses/i2c-phytium-master.c @@ -2,7 +2,7 @@ /* * Phytium I2C adapter driver. * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include #include diff --git a/drivers/i2c/busses/i2c-phytium-pci.c b/drivers/i2c/busses/i2c-phytium-pci.c index b0482b82b6ac148785e111aae245b5f40e66376c..3ef199b1ab850624d2f5b79a3399ce5288ac8f1a 100644 --- a/drivers/i2c/busses/i2c-phytium-pci.c +++ b/drivers/i2c/busses/i2c-phytium-pci.c @@ -2,7 +2,7 @@ /* * PCI driver for Phytium I2C adapter. * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/i2c/busses/i2c-phytium-platform.c b/drivers/i2c/busses/i2c-phytium-platform.c index cb13c287a788e9e830a15265150b376f6bed7005..d9160c428c2485add1e5e169dc223ef4eb27625b 100644 --- a/drivers/i2c/busses/i2c-phytium-platform.c +++ b/drivers/i2c/busses/i2c-phytium-platform.c @@ -2,7 +2,7 @@ /* * Phytium I2C adapter driver. * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/i2c/busses/i2c-phytium-slave.c b/drivers/i2c/busses/i2c-phytium-slave.c index a9409f55c6522e15b1127cf793e89dd5d97b2c3f..e6d25ca1b6a5b5291db65b3e82be2b8c4632f14d 100644 --- a/drivers/i2c/busses/i2c-phytium-slave.c +++ b/drivers/i2c/busses/i2c-phytium-slave.c @@ -2,7 +2,7 @@ /* * Phytium I2C adapter driver (slave only). * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/iio/adc/phytium-adc.c b/drivers/iio/adc/phytium-adc.c index b9d8923c9179dcf24c4295e078ffec78a319d932..b9b044c2a8a19ee4040da56b8fbb6c71ff634695 100755 --- a/drivers/iio/adc/phytium-adc.c +++ b/drivers/iio/adc/phytium-adc.c @@ -2,7 +2,7 @@ /* * Phytium ADC device driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/input/keyboard/phytium-keypad.c b/drivers/input/keyboard/phytium-keypad.c index e5ae4a27c587c827a08a5c084ae80ef23910f2da..f34a9cf140728e92e09d3d31f33c5eaffd6c60d3 100644 --- a/drivers/input/keyboard/phytium-keypad.c +++ b/drivers/input/keyboard/phytium-keypad.c @@ -2,7 +2,7 @@ /* * Driver for the Phytium keypad port. * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/input/serio/phytium-ps2.c b/drivers/input/serio/phytium-ps2.c index d08433d954d704ed79f8067d242de564dd47d703..902dd7a04f0bd602c201bb338c840a018fa6501b 100644 --- a/drivers/input/serio/phytium-ps2.c +++ b/drivers/input/serio/phytium-ps2.c @@ -2,7 +2,7 @@ /* * Phytium PS/2 keyboard controller driver. * - * Copyright (C) 2021-2023, Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/irqchip/irq-phytium-ixic.c b/drivers/irqchip/irq-phytium-ixic.c index 7862df80fb46cf14f388438f7fb29fb75bdf1461..9fee4c6dc874eaeaeecc87b0d9f94facdbe50640 100755 --- a/drivers/irqchip/irq-phytium-ixic.c +++ b/drivers/irqchip/irq-phytium-ixic.c @@ -2,7 +2,7 @@ /* * Driver for Phytium PCIe legacy INTx interrupt controller * - * Copyright (c) 2020-2023, Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/mailbox/phytium-mailbox.c b/drivers/mailbox/phytium-mailbox.c index 21549e25b0560f5ccea3c855b16042280b598f40..c2754f766a209c70af2f4b3b9ff5780eda2d31e4 100644 --- a/drivers/mailbox/phytium-mailbox.c +++ b/drivers/mailbox/phytium-mailbox.c @@ -2,7 +2,7 @@ /* * Phytium SoC mailbox driver * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.c b/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.c index b0324a6d0d85771a7f170dcb924adcfa6402c120..f37db30301214e40259ff1097cfea5468724b36b 100644 --- a/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.c +++ b/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.c @@ -2,7 +2,7 @@ /* * Driver for Phytium JPEG Encoder Engine * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include "phytium_jpeg_reg.h" diff --git a/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.h b/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.h index 1c2b55b651f81b091ea638717cdf9161b7d41348..27e32b2d3c435cc9c77250c1fbc36200cd2d5fa1 100644 --- a/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.h +++ b/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef _PHYTIUM_JPEG_CORE_H diff --git a/drivers/media/platform/phytium-jpeg/phytium_jpeg_reg.h b/drivers/media/platform/phytium-jpeg/phytium_jpeg_reg.h index 3567badf9eb50139e995beaa52ea9f540db782bb..b0a27e2b7e89b027d1293daa024fa7f13f748f5c 100644 --- a/drivers/media/platform/phytium-jpeg/phytium_jpeg_reg.h +++ b/drivers/media/platform/phytium-jpeg/phytium_jpeg_reg.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef _PHYTIUM_JPEG_REG_H diff --git a/drivers/mfd/phytium_px210_i2s_lsd.c b/drivers/mfd/phytium_px210_i2s_lsd.c index a76b5d7708f19ed3c2cd6c54b202be6fc52284de..ad57c59fb44ae38109c574e55edce7eb633abead 100644 --- a/drivers/mfd/phytium_px210_i2s_lsd.c +++ b/drivers/mfd/phytium_px210_i2s_lsd.c @@ -2,7 +2,7 @@ /* * Phytium I2S LSD MFD driver over PCI bus * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/mfd/phytium_px210_i2s_mmd.c b/drivers/mfd/phytium_px210_i2s_mmd.c index 4020686d4ce2e847988246bb3adb3a27dfe5b2ab..c225741bbb9ceb59e4dbf2a7135e723b6915862f 100644 --- a/drivers/mfd/phytium_px210_i2s_mmd.c +++ b/drivers/mfd/phytium_px210_i2s_mmd.c @@ -2,7 +2,7 @@ /* * Phytium I2S MMD MFD driver over PCI bus * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/mmc/host/phytium-mci-pci.c b/drivers/mmc/host/phytium-mci-pci.c index b397a25700d819f55c1bc08e286e78eed67cabea..bd193bbd0ccd3b5251ae4f1c6db812d8a47356e6 100644 --- a/drivers/mmc/host/phytium-mci-pci.c +++ b/drivers/mmc/host/phytium-mci-pci.c @@ -2,7 +2,7 @@ /* * Phytium Multimedia Card Interface PCI driver * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. * */ diff --git a/drivers/mmc/host/phytium-mci-plat.c b/drivers/mmc/host/phytium-mci-plat.c index 33064b16b94b79879cec48b49e092165df1f2a3d..212c86da7bb6e9cc6135bf0e380856924956ad6f 100644 --- a/drivers/mmc/host/phytium-mci-plat.c +++ b/drivers/mmc/host/phytium-mci-plat.c @@ -2,7 +2,7 @@ /* * Phytium Multimedia Card Interface PCI driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/mmc/host/phytium-mci.c b/drivers/mmc/host/phytium-mci.c index 796c8d6207d6f32f75971593e9475312dd3f0725..cedc39cc1ab439af8f562bc5ba676354e8d41505 100644 --- a/drivers/mmc/host/phytium-mci.c +++ b/drivers/mmc/host/phytium-mci.c @@ -2,7 +2,7 @@ /* * Driver for Phytium Multimedia Card Interface * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -658,6 +658,8 @@ phytium_mci_start_data(struct phytium_mci_host *host, struct mmc_request *mrq, phytium_mci_data_sg_write_2_fifo(host, data); spin_lock_irqsave(&host->lock, flags); + mod_timer(&host->timeout_timer, + jiffies + msecs_to_jiffies(MMC_REQ_TIMEOUT_MS)); sdr_set_bits(host->base + MCI_INT_MASK, cmd_ints_mask | data_ints_mask); if (host->is_use_dma && host->adtc_type == BLOCK_RW_ADTC) { sdr_set_bits(host->base + MCI_DMAC_INT_ENA, dmac_ints_mask); @@ -673,9 +675,6 @@ phytium_mci_start_data(struct phytium_mci_host *host, struct mmc_request *mrq, wmb(); /* drain writebuffer */ writel(rawcmd, host->base + MCI_CMD); spin_unlock_irqrestore(&host->lock, flags); - - mod_timer(&host->timeout_timer, - jiffies + msecs_to_jiffies(MMC_REQ_TIMEOUT_MS)); } static void phytium_mci_track_cmd_data(struct phytium_mci_host *host, @@ -797,13 +796,12 @@ static void phytium_mci_start_command(struct phytium_mci_host *host, } spin_lock_irqsave(&host->lock, flags); + mod_timer(&host->timeout_timer, + jiffies + msecs_to_jiffies(MMC_REQ_TIMEOUT_MS)); sdr_set_bits(host->base + MCI_INT_MASK, cmd_ints_mask); writel(cmd->arg, host->base + MCI_CMDARG); writel(rawcmd, host->base + MCI_CMD); spin_unlock_irqrestore(&host->lock, flags); - - mod_timer(&host->timeout_timer, - jiffies + msecs_to_jiffies(MMC_REQ_TIMEOUT_MS)); } static void diff --git a/drivers/mmc/host/phytium-mci.h b/drivers/mmc/host/phytium-mci.h index 5423597ecb97b13bc85d0486ee2323debbb66363..c35e6f3b3a859872f9c0702ff715004163c21f91 100644 --- a/drivers/mmc/host/phytium-mci.h +++ b/drivers/mmc/host/phytium-mci.h @@ -2,7 +2,7 @@ /* * Driver for Phytium Multimedia Card Interface * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_MCI_H diff --git a/drivers/mmc/host/phytium-sdci.c b/drivers/mmc/host/phytium-sdci.c index 929162b8d5bf8ad31e6817a73bd73f9c79dc08f2..b4ca402c1da550dc782ccf41fb014494b46ebc65 100755 --- a/drivers/mmc/host/phytium-sdci.c +++ b/drivers/mmc/host/phytium-sdci.c @@ -2,7 +2,7 @@ /* * Phytium SD Card Interface dirver * - * Copyright (c) 2019-2023, Phytium Technology Co.,Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/mmc/host/phytium-sdci.h b/drivers/mmc/host/phytium-sdci.h index be0e9aa65e2e6a0501888b409c5a94855109c2c5..d53f8b5e0edbef507a4e702ce2afbda9594b66b4 100755 --- a/drivers/mmc/host/phytium-sdci.h +++ b/drivers/mmc/host/phytium-sdci.h @@ -2,7 +2,7 @@ /* * Phytium SD Card Interface driver * - * Copyright (c) 2019-2023, Phytium Technology Co.,Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. */ /*---------------------------------------------------------------------------*/ diff --git a/drivers/mtd/nand/raw/phytium_nand.c b/drivers/mtd/nand/raw/phytium_nand.c index 68728e7ed498c26695ea99c5b55c0a66e379840d..1c8e27d7151c97ba8864a57af60195ce6a870b47 100644 --- a/drivers/mtd/nand/raw/phytium_nand.c +++ b/drivers/mtd/nand/raw/phytium_nand.c @@ -2,7 +2,7 @@ /* * Core driver for Phytium NAND flash controller * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/mtd/nand/raw/phytium_nand.h b/drivers/mtd/nand/raw/phytium_nand.h index 963d555a2aca009c7904b1d362d7b833483b507f..1f773653ff97f62438038c326c6649670069c06e 100644 --- a/drivers/mtd/nand/raw/phytium_nand.h +++ b/drivers/mtd/nand/raw/phytium_nand.h @@ -2,7 +2,7 @@ /* * Phytium NAND flash controller driver * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #ifndef PHYTIUM_NAND_H #define PHYTIUM_NAND_H diff --git a/drivers/mtd/nand/raw/phytium_nand_pci.c b/drivers/mtd/nand/raw/phytium_nand_pci.c index 6ce76dd15161a183bbad882ff7a1c333ecdb5095..a8f054d669cc60765e2a0887030185f3d36bc6d6 100644 --- a/drivers/mtd/nand/raw/phytium_nand_pci.c +++ b/drivers/mtd/nand/raw/phytium_nand_pci.c @@ -2,7 +2,7 @@ /* * PCI driver for Phytium NAND flash controller * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include #include diff --git a/drivers/mtd/nand/raw/phytium_nand_plat.c b/drivers/mtd/nand/raw/phytium_nand_plat.c index b3fde07b4aeb18b16db35fcd061716ff6c8c8d9f..65504785f33ba1b441e5fa06302a016f7be7d009 100644 --- a/drivers/mtd/nand/raw/phytium_nand_plat.c +++ b/drivers/mtd/nand/raw/phytium_nand_plat.c @@ -2,7 +2,7 @@ /* * Core driver for Phytium NAND flash controller * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/mtd/spi-nor/controllers/Kconfig b/drivers/mtd/spi-nor/controllers/Kconfig index 5bfc72f7103f9521123525fd46c734e9b008323a..5c0e0ec2e6d1f1002cf3f2f421d222e73a790cf8 100644 --- a/drivers/mtd/spi-nor/controllers/Kconfig +++ b/drivers/mtd/spi-nor/controllers/Kconfig @@ -62,12 +62,3 @@ config SPI_INTEL_SPI_PLATFORM To compile this driver as a module, choose M here: the module will be called intel-spi-platform. - -config SPI_PHYTIUM_QUADSPI - tristate "Phytium Quad SPI Controller" - depends on ARCH_PHYTIUM || ARM - depends on OF && HAS_IOMEM - help - This enables support for the Quad SPI controller in master mode. - This driver does not support generic SPI. The implementation only - supports SPI NOR. diff --git a/drivers/mtd/spi-nor/controllers/Makefile b/drivers/mtd/spi-nor/controllers/Makefile index a83cf25ceacc35db513fcff463da7bf9a6ce4936..e7abba491d98329fbeb565e70f6ea75299102143 100644 --- a/drivers/mtd/spi-nor/controllers/Makefile +++ b/drivers/mtd/spi-nor/controllers/Makefile @@ -5,4 +5,3 @@ obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o -obj-$(CONFIG_SPI_PHYTIUM_QUADSPI) += phytium-quadspi.o diff --git a/drivers/mtd/spi-nor/controllers/phytium-quadspi.c b/drivers/mtd/spi-nor/controllers/phytium-quadspi.c deleted file mode 100644 index 67937d8b69905af21e89ca7756b196798232615a..0000000000000000000000000000000000000000 --- a/drivers/mtd/spi-nor/controllers/phytium-quadspi.c +++ /dev/null @@ -1,1024 +0,0 @@ -/* - * Phytium SPI core controller driver. - * - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define QSPI_FLASH_CAP_REG 0x000 -#define QSPI_RD_CFG_REG 0x004 -#define QSPI_WR_CFG_REG 0x008 -#define QSPI_FLUSH_REG 0x00C -#define QSPI_CMD_PORT_REG 0x010 -#define QSPI_ADDR_PORT_REG 0x014 -#define QSPI_HD_PORT_REG 0x018 -#define QSPI_LD_PORT_REG 0x01C -#define QSPI_FUN_SET_REG 0x020 -#define QSPI_WIP_REG 0x024 -#define QSPI_WP_REG 0x028 -#define QSPI_MODE_REG 0x02C - -#define QSPI_FLASH_CAP_NUM_SHIFT 3 -#define QSPI_FLASH_CAP_NUM_MASK (0x3 << QSPI_FLASH_CAP_NUM_SHIFT) -#define QSPI_FLASH_CAP_CAP_SHIFT 0 -#define QSPI_FLASH_CAP_CAP_MASK (0x7 << QSPI_FLASH_CAP_CAP_SHIFT) - -#define QSPI_RD_CFG_RD_CMD_SHIFT 24 -#define QSPI_RD_CFG_RD_CMD_MASK (0xFF << QSPI_RD_CFG_RD_CMD_SHIFT) -#define QSPI_RD_CFG_RD_THROUGH_SHIFT 23 -#define QSPI_RD_CFG_RD_THROUGH_MASK (0x01 << QSPI_RD_CFG_RD_THROUGH_SHIFT) -#define QSPI_RD_CFG_RD_TRANSFER_SHIFT 20 -#define QSPI_RD_CFG_RD_TRANSFER_MASK (0x07 << QSPI_RD_CFG_RD_TRANSFER_SHIFT) -#define QSPI_RD_CFG_RD_ADDR_SEL_SHIFT 19 -#define QSPI_RD_CFG_RD_ADDR_SEL_MASK (0x1 << QSPI_RD_CFG_RD_ADDR_SEL_SHIFT) -#define QSPI_RD_CFG_RD_LATENCY_SHIFT 18 -#define QSPI_RD_CFG_RD_LATENCY_MASK (0x1 << QSPI_RD_CFG_RD_LATENCY_SHIFT) -#define QSPI_RD_CFG_MODE_BYTE_SHIFT 17 -#define QSPI_RD_CFG_MODE_BYTE_MASK (0x1 << QSPI_RD_CFG_MODE_BYTE_SHIFT) -#define QSPI_RD_CFG_CMD_SIGN_SHIFT 9 -#define QSPI_RD_CFG_CMD_SIGN_MASK (0xFF << QSPI_RD_CFG_CMD_SIGN_SHIFT) -#define QSPI_RD_CFG_DUMMY_SHIFT 4 -#define QSPI_RD_CFG_DUMMY_MASK (0x1F << QSPI_RD_CFG_DUMMY_SHIFT) -#define QSPI_RD_CFG_D_BUFFER_SHIFT 3 -#define QSPI_RD_CFG_D_BUFFER_MASK (0x1 << QSPI_RD_CFG_D_BUFFER_SHIFT) -#define QSPI_RD_CFG_RD_SCK_SEL_SHIFT 0 -#define QSPI_RD_CFG_RD_SCK_SEL_MASK (0x3 << QSPI_RD_CFG_RD_SCK_SEL_SHIFT) - -#define QSPI_WR_CFG_WR_CMD_SHIFT 24 -#define QSPI_WR_CFG_WR_CMD_MASK (0xFF << QSPI_WR_CFG_WR_CMD_SHIFT) -#define QSPI_WR_CFG_WR_WAIT_SHIFT 9 -#define QSPI_WR_CFG_WR_WAIT_MASK (0x01 << QSPI_WR_CFG_WR_WAIT_SHIFT) -#define QSPI_WR_CFG_WR_THROUGH_SHIFT 8 -#define QSPI_WR_CFG_WR_THROUGH_MAS (0x01 << QSPI_WR_CFG_WR_THROUGH_SHIFT) -#define QSPI_WR_CFG_WR_TRANSFER_SHIFT 5 -#define QSPI_WR_CFG_WR_TRANSFER_MASK (0X7 << QSPI_WR_CFG_WR_TRANSFER_SHIFT) -#define QSPI_WR_CFG_WR_ADDR_SEL_SHIFT 4 -#define QSPI_WR_CFG_WR_ADDR_SEL_MASK (0x1 << QSPI_WR_CFG_WR_ADDR_SEL_SHIFT) -#define QSPI_WR_CFG_WR_MODE_SHIFT 3 -#define QSPI_WR_CFG_WR_MODE (0x01 << QSPI_WR_CFG_WR_MODE_SHIFT) -#define QSPI_WR_CFG_WR_SCK_SEL_SHIFT 0 -#define QSPI_WR_CFG_WR_SCK_SEL_MASK (0x7 << QSPI_WR_CFG_WR_SCK_SEL_SHIFT) - -#define QSPI_FLUSH_EN (0x1 << 0) - -#define QSPI_CMD_PORT_CMD_SHIFT 24 -#define QSPI_CMD_PORT_CMD_MASK (0xFF << QSPI_CMD_PORT_CMD_SHIFT) -#define QSPI_CMD_PORT_WAIT_SHIFT 22 -#define QSPI_CMD_PORT_WAIT_MASK (0x1 << QSPI_CMD_PORT_WAIT_SHIFT) -#define QSPI_CMD_PORT_THROUGH_SHIFT 21 -#define QSPI_CMD_PORT_THROUGH_MASK (0x1 << QSPI_CMD_PORT_THROUGH_SHIFT) -#define QSPI_CMD_PORT_CS_SHIFT 19 -#define QSPI_CMD_PORT_CS_MASK (0x3 << QSPI_CMD_PORT_CS_SHIFT) -#define QSPI_CMD_PORT_TRANSFER_SHIFT 16 -#define QSPI_CMD_PORT_TRANSFER_MASK (0x7 << QSPI_CMD_PORT_TRANSFER_SHIFT) -#define QSPI_CMD_PORT_CMD_ADDR_SHIFT 15 -#define QSPI_CMD_PORT_CMD_ADDR_MASK (0x1 << QSPI_CMD_PORT_CMD_ADDR_SHIFT) -#define QSPI_CMD_PORT_LATENCY_SHIFT 14 -#define QSPI_CMD_PORT_LATENCY_MASK (0x1 << QSPI_CMD_PORT_LATENCY_SHIFT) -#define QSPI_CMD_PORT_DATA_TRANSFER_SHIFT 13 -#define QSPI_CMD_PORT_DATA_TRANSFER_MASK (0x1 << 13) -#define QSPI_CMD_PORT_SEL_SHIFT 12 -#define QSPI_CMD_PORT_SEL_MASK (0x1 << QSPI_CMD_PORT_SEL_SHIFT) -#define QSPI_CMD_PORT_DUMMY_SHIFT 7 -#define QSPI_CMD_PORT_DUMMY_MASK (0x1F << QSPI_CMD_PORT_DUMMY_SHIFT) -#define QSPI_CMD_PORT_DUMMY(x) (((x) << QSPI_CMD_PORT_DUMMY_SHIFT) & QSPI_CMD_PORT_DUMMY_MASK) -#define QSPI_CMD_PORT_P_BUFFER_SHIFT 6 -#define QSPI_CMD_PORT_P_BUFFER_MASK (0x1 << QSPI_CMD_PORT_P_BUFFER_SHIFT) -#define QSPI_CMD_PORT_RW_NUM_SHIFT 3 -#define QSPI_CMD_PORT_RW_NUM_MASK (0x7 << QSPI_CMD_PORT_RW_NUM_SHIFT) -#define QSPI_CMD_PORT_SCK_SEL_SHIFT 0 -#define QSPI_CMD_PORT_SCK_SEL_MASK (0x7 << QSPI_CMD_PORT_SCK_SEL_SHIFT) - -#define QSPI_FUN_SET_HOLD_SHIFT 24 -#define QSPI_FUN_SET_HOLD_MASK (0xFF << QSPI_FUN_SET_HOLD_SHIFT) -#define QSPI_FUN_SET_SETUP_SHIFT 16 -#define QSPI_FUN_SET_SETUP_MASK (0xFF << QSPI_FUN_SET_SETUP_SHIFT) -#define QSPI_FUN_SET_DELAY_SHIFT 0 -#define QSPI_FUN_SET_DELAY_MASK (0xFFFF << QSPI_FUN_SET_DELAY_SHIFT) - -#define QSPI_WIP_W_CMD_SHIFT 24 -#define QSPI_WIP_W_CMD_MASK (0xFF << QSPI_WIP_W_CMD_SHIFT) -#define QSPI_WIP_W_TRANSFER_SHIFT 3 -#define QSPI_WIP_W_TRANSFER_MASK (0x3 << QSPI_WIP_W_TRANSFER_SHIFT) -#define QSPI_WIP_W_SCK_SEL_SHIFT 0 -#define QSPI_WIP_W_SCK_SEL_MASK (0x7 << QSPI_WIP_W_SCK_SEL_SHIFT) - -#define QSPI_WP_EN_SHIFT 17 -#define QSPI_WP_EN_MASK (0x1 << QSPI_WP_EN_SHIFT) -#define QSPI_WP_IO2_SHIFT 16 -#define QSPI_WP_IO2_MASK (0x1 << QSPI_WP_IO2_SHIFT) -#define QSPI_WP_HOLD_SHIFT 8 -#define QSPI_WP_HOLD_MASK (0xFF << QSPI_WP_HOLD_SHIFT) -#define QSPI_WP_SETUP_SHIFT 0 -#define QSPI_WP_SETUP_MASK (0xFF << QSPI_WP_SETUP_SHIFT) - -#define QSPI_MODE_VALID_SHIFT 8 -#define QSPI_MODE_VALID_MASK (0xFF << QSPI_MODE_VALID_SHIFT) -#define QSPI_MODE_SHIFT 0 -#define QSPI_MODE_MASK (0xFF << QSPI_MODE_SHIFT) - -#define FSIZE_VAL(size) (__fls(size) - 1) - -#define PHYTIUM_MAX_MMAP_S SZ_512M -#define PHYTIUM_MAX_NORCHIP 4 - -#define PHYTIUM_QSPI_FIFO_SZ 32 -#define PHYTIUM_QSPI_FIFO_TIMEOUT_US 50000 -#define PHYTIUM_QSPI_BUSY_TIMEOUT_US 100000 - -#define PHYTIUM_SCK_SEL 0x05 -#define PHYTIUM_CMD_SCK_SEL 0x07 - -#define PHYTIUM_FMODE_MM 0x01 -#define PHYTIUM_FMODE_IN 0x02 - -/* - * the codes of the different commands - */ -#define CMD_WRDI 0x04 -#define CMD_RDID 0x9F -#define CMD_RDSR 0x05 -#define CMD_WREN 0x06 -#define CMD_RDAR 0x65 -#define CMD_P4E 0x20 -#define CMD_4P4E 0x21 -#define CMD_BE 0x60 -#define CMD_4BE 0xC7 -#define CMD_READ 0x03 -#define CMD_FAST_READ 0x0B -#define CMD_QOR 0x6B -#define CMD_QIOR 0xEB -#define CMD_DDRFR 0x0D -#define CMD_DDRQIOQ 0xED -#define CMD_PP 0x02 -#define CMD_QPP 0x32 -#define CMD_SE 0xD8 -#define CMD_4FAST_READ 0x0C -#define CMD_4READ 0x13 -#define CMD_4QOR 0x6C -#define CMD_4QIOR 0xEC -#define CMD_4DDRFR 0x0E -#define CMD_4DDRQIOR 0xEE -#define CMD_4PP 0x12 -#define CMD_4QPP 0x34 -#define CMD_4SE 0xDC - -#define PHYTIUM_QSPI_1_1_1 0 -#define PHYTIUM_QSPI_1_1_2 1 -#define PHYTIUM_QSPI_1_1_4 2 -#define PHYTIUM_QSPI_1_2_2 3 -#define PHYTIUM_QSPI_1_4_4 4 -#define PHYTIUM_QSPI_2_2_2 5 -#define PHYTIUM_QSPI_4_4_4 6 - -struct phytium_qspi_flash { - struct spi_nor nor; - struct phytium_qspi *qspi; - u32 cs; - u32 fsize; - u32 presc; - u32 clk_div; - u32 read_mode; - bool registered; - u32 prefetch_limit; - u32 addr_width; - u32 read_cmd; -}; - -struct phytium_qspi { - struct device *dev; - void __iomem *io_base; - void __iomem *mm_base; - resource_size_t mm_size; - u32 nor_num; - struct clk *clk; - u32 clk_rate; - struct phytium_qspi_flash flash[PHYTIUM_MAX_NORCHIP]; - - spinlock_t spinlock; - - /* - * to protect device configuration, could be different between - * 2 flash access (bk1, bk2) - */ - struct mutex lock; -}; - -/* Need to enable p_buffer */ -static int memcpy_from_ftreg(struct phytium_qspi *qspi, u_char *buf, size_t len) -{ - int i; - u32 val = 0; - - if (!qspi || !buf) - return -EINVAL; - - for (i = 0; i < len; i++) { - if (0 == i % 4) - val = readl_relaxed(qspi->io_base + QSPI_LD_PORT_REG); - - buf[i] = (u_char) (val >> (i % 4) * 8) & 0xFF; - } - - return 0; -} - -/* Not to enable p_buffer */ -static int memcpy_to_ftreg(struct phytium_qspi *qspi, const u8 *buf, size_t len) -{ - u32 val = 0; - - if (!qspi || !buf || (len >= 8)) - return -EINVAL; - - if (1 == len) { - val = buf[0]; - } else if (2 == len) { - val = buf[1]; - val = (val << 8) + buf[0]; - } else if (3 == len) { - val = buf[2]; - val = (val << 8) + buf[1]; - val = (val << 8) + buf[0]; - } else if (4 == len) { - val = buf[3]; - val = (val << 8) + buf[2]; - val = (val << 8) + buf[1]; - val = (val << 8) + buf[0]; - } - - writel_relaxed(val, qspi->io_base + QSPI_LD_PORT_REG); - - return 0; -} - -static int phytium_qspi_wait_cmd(struct phytium_qspi *qspi, - struct phytium_qspi_flash *flash) -{ - u32 cmd = 0; - u32 cnt = 0; - - cmd |= CMD_RDSR << QSPI_CMD_PORT_CMD_SHIFT; - cmd |= BIT(QSPI_CMD_PORT_DATA_TRANSFER_SHIFT); - cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT; - - writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG); - - cnt = PHYTIUM_QSPI_BUSY_TIMEOUT_US / 10; - while (readl_relaxed(qspi->io_base + QSPI_LD_PORT_REG) & 0x01) { - udelay(10); - cnt--; - if (!cnt) { - dev_err(qspi->dev, "wait command process timeout\n"); - break; - } - } - - return !cnt; -} - -static int phytium_qspi_cmd_enable(struct phytium_qspi *qspi) -{ - u32 val = 0; - - writel_relaxed(val, qspi->io_base + QSPI_LD_PORT_REG); - - return 0; -} - -static int phytium_qspi_write_enable(struct phytium_qspi *qspi, - struct phytium_qspi_flash *flash) -{ - u32 cmd = 0; - - cmd = CMD_WREN << QSPI_CMD_PORT_CMD_SHIFT; - cmd |= PHYTIUM_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT; - cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT; - - writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG); - phytium_qspi_cmd_enable(qspi); - - return 0; -} - -static int phytium_qspi_write_disable(struct phytium_qspi *qspi, - struct phytium_qspi_flash *flash) -{ - u32 cmd = 0; - - cmd = CMD_WRDI << QSPI_CMD_PORT_CMD_SHIFT; - cmd |= PHYTIUM_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT; - cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT; - - writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG); - phytium_qspi_cmd_enable(qspi); - - return 0; -} - -static int phytium_qspi_read_flash_id(struct phytium_qspi *qspi, - struct phytium_qspi_flash *flash, u8 opcode, u8 *buf, int len) -{ - u32 cmd = 0; - unsigned long iflags; - - cmd = opcode << QSPI_CMD_PORT_CMD_SHIFT; - cmd |= BIT(QSPI_CMD_PORT_DATA_TRANSFER_SHIFT); - cmd |= BIT(QSPI_CMD_PORT_P_BUFFER_SHIFT); - cmd |= PHYTIUM_CMD_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT; - cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT; - - writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG); - phytium_qspi_cmd_enable(qspi); - - spin_lock_irqsave(&qspi->spinlock, iflags); - memcpy_from_ftreg(qspi, buf, len); - spin_unlock_irqrestore(&qspi->spinlock, iflags); - - dev_dbg(qspi->dev, "read flash id:%x\n", *(u32 *)buf); - return 0; -} - -static int phytium_qspi_read_flash_sfdp(struct phytium_qspi *qspi, - struct phytium_qspi_flash *flash, struct spi_nor *nor, loff_t from, u8 *buf, int len) -{ - unsigned long iflags; - u32 cmd = 0; - u8 opcode = nor->read_opcode; - - cmd = opcode << QSPI_CMD_PORT_CMD_SHIFT; - cmd |= BIT(QSPI_CMD_PORT_DATA_TRANSFER_SHIFT); - cmd |= BIT(QSPI_CMD_PORT_P_BUFFER_SHIFT); - cmd |= BIT(QSPI_CMD_PORT_CMD_ADDR_SHIFT); - cmd |= PHYTIUM_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT; - cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT; - cmd |= BIT(QSPI_CMD_PORT_LATENCY_SHIFT); - cmd |= QSPI_CMD_PORT_DUMMY(nor->read_dummy - 1); - - writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG); - writel_relaxed(from, qspi->io_base + QSPI_ADDR_PORT_REG); - phytium_qspi_cmd_enable(qspi); - - spin_lock_irqsave(&qspi->spinlock, iflags); - memcpy_from_ftreg(qspi, buf, len); - spin_unlock_irqrestore(&qspi->spinlock, iflags); - - dev_dbg(qspi->dev, "read flash sfdp:0x%llx 0x%llx\n", - *(u64 *)buf, *(u64 *)(buf + 8)); - return len; -} - -static int phytium_qspi_read_flash_sr1(struct phytium_qspi *qspi, - struct phytium_qspi_flash *flash, u8 opcode, u8 *buf, int len) -{ - u32 cmd = 0; - u32 val; - - cmd = opcode << QSPI_CMD_PORT_CMD_SHIFT; - cmd |= BIT(QSPI_CMD_PORT_DATA_TRANSFER_SHIFT); - cmd |= (len << QSPI_CMD_PORT_RW_NUM_SHIFT) & QSPI_CMD_PORT_RW_NUM_MASK; - cmd |= PHYTIUM_CMD_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT; - cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT; - - writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG); - phytium_qspi_cmd_enable(qspi); - - val = readl_relaxed(qspi->io_base + QSPI_LD_PORT_REG); - buf[0] = (u8)val; - - return 0; -} - -static int phytium_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len) -{ - struct phytium_qspi_flash *flash = nor->priv; - struct device *dev = flash->qspi->dev; - struct phytium_qspi *qspi = flash->qspi; - unsigned long iflags; - u32 cmd = 0; - - dev_dbg(dev, "read_reg: cmd:%#.2x buf:%pK len:%#lx\n", opcode, buf, len); - - switch (opcode) { - case CMD_RDID: - phytium_qspi_read_flash_id(qspi, flash, opcode, buf, len); - return 0; - case CMD_RDSR: - phytium_qspi_read_flash_sr1(qspi, flash, opcode, buf, len); - return 0; - default: - break; - } - - cmd = opcode << QSPI_CMD_PORT_CMD_SHIFT; - cmd |= BIT(QSPI_CMD_PORT_DATA_TRANSFER_SHIFT); - cmd |= BIT(QSPI_CMD_PORT_P_BUFFER_SHIFT); - cmd |= PHYTIUM_CMD_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT; - cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT; - - writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG); - phytium_qspi_cmd_enable(qspi); - - spin_lock_irqsave(&qspi->spinlock, iflags); - memcpy_from_ftreg(qspi, buf, len); - spin_unlock_irqrestore(&qspi->spinlock, iflags); - - return 0; -} - -static int phytium_qspi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf, size_t len) -{ - struct phytium_qspi_flash *flash = nor->priv; - struct device *dev = flash->qspi->dev; - struct phytium_qspi *qspi = flash->qspi; - u32 cmd = 0; - - dev_dbg(dev, "write_reg: cmd:%#.2x buf:%pK len:%#lx\n", opcode, buf, len); - - switch (opcode) { - case CMD_WREN: - phytium_qspi_write_enable(qspi, flash); - return 0; - case CMD_WRDI: - phytium_qspi_write_disable(qspi, flash); - return 0; - default: - break; - } - - cmd = opcode << QSPI_CMD_PORT_CMD_SHIFT; - cmd |= PHYTIUM_CMD_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT; - cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT; - - if ((len > 8) || (NULL == buf)) { - dev_err(dev, "data length exceed. commad %x, len:%ld \n", opcode, len); - return -EINVAL; - } else if (len > 0) { - cmd |= ((len - 1) << QSPI_CMD_PORT_RW_NUM_SHIFT) & QSPI_CMD_PORT_RW_NUM_MASK; - cmd |= BIT(QSPI_CMD_PORT_DATA_TRANSFER_SHIFT); - } - - writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG); - memcpy_to_ftreg(qspi, buf, len); - - return 0; -} - -static ssize_t phytium_qspi_read_tmp(struct phytium_qspi *qspi, u32 read_cmd, loff_t from, size_t len, u_char *buf) -{ - u32 addr = (u32)from; - u64 val = 0; - - if (!qspi) - return -1; - - dev_dbg(qspi->dev, "read cmd:%x, addr:%x len:%zx\n", read_cmd, addr, len); - writel_relaxed(read_cmd, qspi->io_base + QSPI_RD_CFG_REG); - - memcpy_fromio(buf, qspi->mm_base + addr, len); - - val = *(u64 *)(buf); - dev_dbg(qspi->dev, "read val:%llx\n", val); - - return len; -} - -static ssize_t phytium_qspi_read(struct spi_nor *nor, loff_t from, size_t len, u8 *buf) -{ - struct phytium_qspi_flash *flash = nor->priv; - struct phytium_qspi *qspi = flash->qspi; - u32 cmd = nor->read_opcode; - u32 addr = (u32)from; - - addr = addr + flash->cs * flash->fsize; - - dev_dbg(qspi->dev, "read(%#.2x): buf:%pK from:%#.8x len:%#zx\n", nor->read_opcode, buf, addr, len); - - cmd = cmd << QSPI_RD_CFG_RD_CMD_SHIFT; - cmd |= BIT(QSPI_RD_CFG_D_BUFFER_SHIFT); - cmd |= flash->clk_div << QSPI_CMD_PORT_SCK_SEL_SHIFT; - - cmd &= ~QSPI_RD_CFG_RD_TRANSFER_MASK; - cmd |= (flash->addr_width << QSPI_RD_CFG_RD_TRANSFER_SHIFT); - - switch (nor->read_opcode) { - case CMD_READ: - case CMD_FAST_READ: - case CMD_QIOR: - case CMD_QOR: - cmd &= ~QSPI_RD_CFG_RD_ADDR_SEL_MASK; - break; - case CMD_4READ: - case CMD_4FAST_READ: - case CMD_4QOR: - case CMD_4QIOR: - cmd |= BIT(QSPI_RD_CFG_RD_ADDR_SEL_SHIFT); - break; - case 0x5A: - cmd &= ~QSPI_RD_CFG_RD_ADDR_SEL_MASK; - return phytium_qspi_read_flash_sfdp(qspi, flash, nor, from, buf, len); - break; - default: - break; - } - - if ((PHYTIUM_QSPI_1_1_4 == flash->addr_width) || (PHYTIUM_QSPI_1_4_4 == flash->addr_width)) { - cmd |= BIT(QSPI_RD_CFG_RD_LATENCY_SHIFT); - cmd &= ~QSPI_RD_CFG_DUMMY_MASK; - cmd |= (0x07 << QSPI_RD_CFG_DUMMY_SHIFT); - } - - dev_dbg(qspi->dev, "read(%#.2x): cmd:%#x\n", nor->read_opcode, cmd); - - if (cmd != flash->read_cmd) - flash->read_cmd = cmd; - - writel_relaxed(cmd, qspi->io_base + QSPI_RD_CFG_REG); - - memcpy_fromio(buf, qspi->mm_base + addr, len); - - return len; -} - -static ssize_t phytium_qspi_write(struct spi_nor *nor, loff_t to, size_t len, const u8 *buf) -{ - struct phytium_qspi_flash *flash = nor->priv; - struct device *dev = flash->qspi->dev; - struct phytium_qspi *qspi = flash->qspi; - u32 cmd = nor->program_opcode; - u32 addr = (u32)to; - int i; - u_char tmp[8] = {0}; - size_t mask = 0x03; - - addr = addr + flash->cs * flash->fsize; - - dev_dbg(dev, "write(%#.2x): buf:%p to:%#.8x len:%#zx\n", nor->program_opcode, buf, addr, len); - - if (addr & 0x03) { - dev_err(dev, "Addr not four-byte aligned!\n"); - return -EINVAL; - } - - cmd = cmd << QSPI_WR_CFG_WR_CMD_SHIFT; - cmd |= BIT(QSPI_WR_CFG_WR_MODE_SHIFT); - cmd |= PHYTIUM_CMD_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT; - - switch (nor->program_opcode) { - case CMD_PP: - case CMD_QPP: - cmd &= ~QSPI_WR_CFG_WR_ADDR_SEL_MASK; - break; - case CMD_4PP: - case CMD_4QPP: - cmd |= BIT(QSPI_WR_CFG_WR_ADDR_SEL_SHIFT); - break; - default: - dev_err(qspi->dev, "Not support program command:%#x\n", nor->erase_opcode); - return -EINVAL; - } - - dev_dbg(qspi->dev, "write cmd:%x\n", cmd); - - writel_relaxed(cmd, qspi->io_base + QSPI_WR_CFG_REG); - - for (i = 0; i < len/4; i++) - writel_relaxed(*(u32 *)(buf + 4*i), qspi->mm_base + addr + 4*i); - - if (len & mask) { - addr = addr + (len & ~mask); - phytium_qspi_read_tmp(qspi, flash->read_cmd, addr, 4, &tmp[0]); - memcpy(tmp, buf + (len & ~mask), len & mask); - writel_relaxed(*(u32 *)(tmp), qspi->mm_base + addr); - } - - writel_relaxed(QSPI_FLUSH_EN, qspi->io_base + QSPI_FLUSH_REG); - - phytium_qspi_wait_cmd(qspi, flash); - - return len; -} - -static int phytium_qspi_erase(struct spi_nor *nor, loff_t offs) -{ - struct phytium_qspi_flash *flash = nor->priv; - struct device *dev = flash->qspi->dev; - struct phytium_qspi *qspi = flash->qspi; - u32 cmd = nor->erase_opcode; - u32 addr = (u32)offs; - - dev_dbg(dev, "erase(%#.2x):offs:%#x\n", nor->erase_opcode, (u32)offs); - - phytium_qspi_write_enable(qspi, flash); - - cmd = cmd << QSPI_CMD_PORT_CMD_SHIFT; - cmd |= PHYTIUM_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT; - cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT; - - /* s25fl256s1 not supoort D8, DC, 20, 21 */ - switch (nor->erase_opcode) { - case CMD_SE: - cmd &= ~QSPI_CMD_PORT_SEL_MASK; - cmd |= BIT(QSPI_CMD_PORT_CMD_ADDR_SHIFT); - writel_relaxed(addr, qspi->io_base + QSPI_ADDR_PORT_REG); - break; - case CMD_4SE: - cmd |= BIT(QSPI_CMD_PORT_SEL_SHIFT); - cmd |= BIT(QSPI_CMD_PORT_CMD_ADDR_SHIFT); - writel_relaxed(addr, qspi->io_base + QSPI_ADDR_PORT_REG); - break; - case CMD_P4E: - cmd &= ~QSPI_CMD_PORT_SEL_MASK; - cmd |= BIT(QSPI_CMD_PORT_CMD_ADDR_SHIFT); - writel_relaxed(addr, qspi->io_base + QSPI_ADDR_PORT_REG); - break; - case CMD_4P4E: - cmd |= BIT(QSPI_CMD_PORT_SEL_SHIFT); - cmd |= BIT(QSPI_CMD_PORT_CMD_ADDR_SHIFT); - writel_relaxed(addr, qspi->io_base + QSPI_ADDR_PORT_REG); - break; - case CMD_BE: - cmd &= ~QSPI_CMD_PORT_SEL_MASK; - break; - case CMD_4BE: - cmd |= BIT(QSPI_CMD_PORT_SEL_SHIFT); - break; - default: - dev_err(qspi->dev, "Not support erase command:%#x\n", nor->erase_opcode); - return -EINVAL; - } - - writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG); - phytium_qspi_cmd_enable(qspi); - phytium_qspi_wait_cmd(qspi, flash); - - return 0; -} - -static int phytium_qspi_prep(struct spi_nor *nor) -{ - struct phytium_qspi_flash *flash = nor->priv; - struct phytium_qspi *qspi = flash->qspi; - - mutex_lock(&qspi->lock); - return 0; -} - -static void phytium_qspi_unprep(struct spi_nor *nor) -{ - struct phytium_qspi_flash *flash = nor->priv; - struct phytium_qspi *qspi = flash->qspi; - - mutex_unlock(&qspi->lock); -} - -static int phytium_qspi_get_flash_size(struct phytium_qspi *qspi, u32 size) -{ - int ret = 0; - u32 value; - - switch (size) { - case SZ_4M: - value = 0; - break; - case SZ_8M: - value = 1; - break; - case SZ_16M: - value = 2; - break; - case SZ_32M: - value = 3; - break; - case SZ_64M: - value = 4; - break; - case SZ_128M: - value = 5; - break; - case SZ_256M: - value = 6; - break; - case SZ_512M: - value = 7; - break; - default: - value = 0; - ret = -EINVAL; - return ret; - } - - return value; -} - -static const struct spi_nor_controller_ops phytium_controller_ops = { - .prepare = phytium_qspi_prep, - .unprepare = phytium_qspi_unprep, - .read_reg = phytium_qspi_read_reg, - .write_reg = phytium_qspi_write_reg, - .read = phytium_qspi_read, - .write = phytium_qspi_write, - .erase = phytium_qspi_erase, -}; - -static int phytium_qspi_flash_setup(struct phytium_qspi *qspi, struct fwnode_handle *np) -{ - struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | SNOR_HWCAPS_PP, }; - u32 width, presc; - u32 cs_num = 0; - u32 max_rate = 0; - u32 clk_div = 0; - u32 flash_cap = 0; - u32 addr_width = PHYTIUM_QSPI_1_1_1; - struct phytium_qspi_flash *flash; - struct mtd_info *mtd; - int ret; - - fwnode_property_read_u32(np, "reg", &cs_num); - if (cs_num >= PHYTIUM_MAX_NORCHIP) - return -EINVAL; - - fwnode_property_read_u32(np, "spi-max-frequency", &max_rate); - if (!max_rate) - return -EINVAL; - - fwnode_property_read_u32(np, "spi-clk-div", &clk_div); - if (!clk_div) - clk_div = PHYTIUM_SCK_SEL; - - if (clk_div < 4) - return -EINVAL; - - presc = DIV_ROUND_UP(qspi->clk_rate, max_rate) - 1; - - fwnode_property_read_u32(np, "spi-rx-bus-width", &width); - if (!width) - width = 1; - - if (width == 4) { - hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; - addr_width = PHYTIUM_QSPI_1_1_4; - } else if (width == 2) { - hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; - addr_width = PHYTIUM_QSPI_1_1_2; - } else if (width != 1) - return -EINVAL; - - flash = &qspi->flash[cs_num]; - - flash->qspi = qspi; - flash->cs = cs_num; - flash->presc = presc; - flash->clk_div = clk_div; - flash->addr_width = addr_width; - flash->nor.dev = qspi->dev; - if (qspi->dev->of_node) - spi_nor_set_flash_node(&flash->nor, qspi->dev->of_node); - flash->nor.priv = flash; - flash->nor.controller_ops = &phytium_controller_ops; - - ret = spi_nor_scan(&flash->nor, NULL, &hwcaps); - if (ret) { - dev_err(qspi->dev, "device scan failed\n"); - return ret; - } - - mtd = &flash->nor.mtd; - - flash->fsize = mtd->size; - flash->prefetch_limit = mtd->size - PHYTIUM_QSPI_FIFO_SZ; - - ret = phytium_qspi_get_flash_size(flash->qspi, mtd->size); - if (ret < 0) { - dev_err(qspi->dev, "flash size invalid\n"); - return ret; - } - - flash_cap = cs_num << QSPI_FLASH_CAP_NUM_SHIFT; - flash_cap |= ret; - writel_relaxed(flash_cap, qspi->io_base + QSPI_FLASH_CAP_REG); - - flash->read_mode = PHYTIUM_FMODE_MM; - - ret = mtd_device_register(mtd, NULL, 0); - if (ret) { - dev_err(qspi->dev, "mtd device parse failed\n"); - return ret; - } - - flash->registered = true; - - dev_dbg(qspi->dev, "read mm:%s %px cs:%d bus:%d clk-div:%d\n", - flash->read_mode == PHYTIUM_FMODE_MM ? "yes" : "no", - qspi->mm_base, cs_num, width, clk_div); - - dev_dbg(qspi->dev, "mtd->size:%llx, mtd->erasesize:%x, fsize:%x\n", - mtd->size, mtd->erasesize, flash->fsize); - - return 0; -} - -static void phytium_qspi_mtd_free(struct phytium_qspi *qspi) -{ - int i; - - for (i = 0; i < PHYTIUM_MAX_NORCHIP; i++) - if (qspi->flash[i].registered) - mtd_device_unregister(&qspi->flash[i].nor.mtd); -} - -static ssize_t clk_div_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct phytium_qspi *qspi = dev_get_drvdata(dev); - struct phytium_qspi_flash *flash = &qspi->flash[0]; - - return sprintf(buf, "Flash 0 clk-div: %d\n", flash->clk_div); -} - -static ssize_t clk_div_store(struct device *dev, - struct device_attribute *attr, const char *buf, - size_t size) -{ - struct phytium_qspi *qspi = dev_get_drvdata(dev); - struct phytium_qspi_flash *flash = &qspi->flash[0]; - long value; - char *token; - ssize_t status; - - token = strsep ((char **)&buf, " "); - if (!token) - return -EINVAL; - - status = kstrtol(token, 0, &value); - if (status) - return status; - - flash->clk_div = (u8)value; - - return size; -} -static DEVICE_ATTR_RW(clk_div); - -static struct attribute *phytium_qspi_attrs[] = { - &dev_attr_clk_div.attr, - NULL, -}; - -static struct attribute_group phytium_qspi_attr_group = { - .attrs = phytium_qspi_attrs, -}; - -static int phytium_qspi_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct fwnode_handle *flash_np; - struct phytium_qspi *qspi; - struct resource *res; - int ret; - - qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL); - if (!qspi) - return -ENOMEM; - - qspi->nor_num = device_get_child_node_count(dev); - if (!qspi->nor_num || qspi->nor_num > PHYTIUM_MAX_NORCHIP) - return -ENODEV; - - if (dev->of_node) - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi"); - else if (has_acpi_companion(dev)) { - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - } - qspi->io_base = devm_ioremap_resource(dev, res); - if (IS_ERR(qspi->io_base)) - return PTR_ERR(qspi->io_base); - - - if (dev->of_node) - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm"); - else if (has_acpi_companion(dev)) - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - - qspi->mm_base = devm_ioremap_resource(dev, res); - if (IS_ERR(qspi->mm_base)) - return PTR_ERR(qspi->mm_base); - - qspi->mm_size = resource_size(res); - - if (dev->of_node) { - qspi->clk = devm_clk_get(dev, NULL); - if (IS_ERR(qspi->clk)) - return PTR_ERR(qspi->clk); - - qspi->clk_rate = clk_get_rate(qspi->clk); - if (!qspi->clk_rate) - return -EINVAL; - - ret = clk_prepare_enable(qspi->clk); - if (ret) { - dev_err(dev, "can not enable the clock\n"); - return ret; - } - } - else if (has_acpi_companion(dev)) { /* ACPI table not pass clk rate */ - qspi->clk_rate = 50000000; - } - - qspi->dev = dev; - platform_set_drvdata(pdev, qspi); - mutex_init(&qspi->lock); - spin_lock_init(&qspi->spinlock); - - fwnode_for_each_available_child_node(dev_fwnode(dev), flash_np) { - ret = phytium_qspi_flash_setup(qspi, flash_np); - if (ret) { - dev_err(dev, "unable to setup flash chip\n"); - goto err_flash; - } - } - - ret = sysfs_create_group(&qspi->dev->kobj, &phytium_qspi_attr_group); - if (ret) { - dev_err(dev, "unable to create sysfs\n"); - goto err_flash; - } - - return 0; - -err_flash: - mutex_destroy(&qspi->lock); - phytium_qspi_mtd_free(qspi); - - clk_disable_unprepare(qspi->clk); - return ret; -} - -static int phytium_qspi_remove(struct platform_device *pdev) -{ - struct phytium_qspi *qspi = platform_get_drvdata(pdev); - - sysfs_remove_group(&qspi->dev->kobj, &phytium_qspi_attr_group); - - phytium_qspi_mtd_free(qspi); - mutex_destroy(&qspi->lock); - - clk_disable_unprepare(qspi->clk); - return 0; -} - -#ifdef CONFIG_ACPI -static const struct acpi_device_id phytium_qspi_acpi_ids[] = { - { "PHYT0011", 0 }, - { /* sentinel */ }, -}; -MODULE_DEVICE_TABLE(acpi, phytium_qspi_acpi_ids); -#endif - -static const struct of_device_id phytium_qspi_match[] = { - { .compatible = "phytium,qspi" }, - { } -}; -MODULE_DEVICE_TABLE(of, phytium_qspi_match); - -static struct platform_driver phytium_qspi_driver = { - .probe = phytium_qspi_probe, - .remove = phytium_qspi_remove, - .driver = { - .name = "phytium-quadspi", - .of_match_table = phytium_qspi_match, - .acpi_match_table = ACPI_PTR(phytium_qspi_acpi_ids), - }, -}; -module_platform_driver(phytium_qspi_driver); - -MODULE_AUTHOR("Mingshuai Zhu "); -MODULE_AUTHOR("Shaojun Yang "); -MODULE_DESCRIPTION("Phytium QuadSPI driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/net/can/phytium/phytium_can.c b/drivers/net/can/phytium/phytium_can.c index c761c77ac7555b2bd625fce7d3dff14e61368fee..1b2859ac106751b9bb80293d0199cf7be30c3ca5 100644 --- a/drivers/net/can/phytium/phytium_can.c +++ b/drivers/net/can/phytium/phytium_can.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* CAN bus driver for Phytium CAN controller * - * Copyright (C) 2021-2023, Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/net/can/phytium/phytium_can.h b/drivers/net/can/phytium/phytium_can.h index 802bb36a131160d960585987b245c9320b49b725..52bddeddc5cfb13b5bf7a96fcd16f00cdc118848 100644 --- a/drivers/net/can/phytium/phytium_can.h +++ b/drivers/net/can/phytium/phytium_can.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium CAN controller driver * - * Copyright (C) 2021-2023, Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #ifndef _PHYTIUM_CAN_H_ diff --git a/drivers/net/can/phytium/phytium_can_pci.c b/drivers/net/can/phytium/phytium_can_pci.c index 5113926e088b97419bc20cd98c2f1702e064db45..a41833b7e8af67555142c6b2df54281e6983ccb4 100644 --- a/drivers/net/can/phytium/phytium_can_pci.c +++ b/drivers/net/can/phytium/phytium_can_pci.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Platform CAN bus driver for Phytium CAN controller * - * Copyright (C) 2021-2023, Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/net/can/phytium/phytium_can_platform.c b/drivers/net/can/phytium/phytium_can_platform.c index 697f69d625c7173cba1eff9e85c290132c3c8e7c..35a747ad76d008c1eef11cb29b6379b6e34e79de 100644 --- a/drivers/net/can/phytium/phytium_can_platform.c +++ b/drivers/net/can/phytium/phytium_can_platform.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Platform CAN bus driver for Phytium CAN controller * - * Copyright (C) 2021-2023, Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -145,7 +145,15 @@ static int phytium_can_plat_probe(struct platform_device *pdev) platform_set_drvdata(pdev, cdev->net); - pm_runtime_enable(cdev->dev); + if (!pm_runtime_enabled(cdev->dev)) + pm_runtime_enable(cdev->dev); + ret = pm_runtime_get_sync(cdev->dev); + if (ret < 0) { + netdev_err(cdev->net, "%s: pm_runtime_get failed(%d)\n", + __func__, ret); + goto out_runtime_disable; + } + ret = phytium_can_register(cdev); if (ret) goto out_runtime_disable; diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 17d92bbafea4aef6a34992fb7f8b52822903e843..a82071da9c8f098af69d2617f9d6f4b0556e7293 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -1087,7 +1087,7 @@ static int macb_phylink_connect(struct macb *bp) struct net_device *dev = bp->dev; struct phy_device *phydev; struct macb_platform_data *pdata = dev_get_platdata(&bp->pdev->dev); - int ret; + int ret = 0; if (pdata && pdata->phytium_macb_pdata.properties) { phylink_start(bp->phylink); @@ -1106,7 +1106,8 @@ static int macb_phylink_connect(struct macb *bp) phydev->force_mode = bp->force_phy_mode; /* attach the mac to the phy */ - ret = phylink_connect_phy(bp->phylink, phydev); + if (phylink_expects_phy(bp->phylink)) + ret = phylink_connect_phy(bp->phylink, phydev); } if (ret) { @@ -1318,6 +1319,10 @@ static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc) } #endif addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr)); +#ifdef CONFIG_MACB_USE_HWSTAMP + if (bp->hw_dma_cap & HW_DMA_CAP_PTP) + addr &= ~GEM_BIT(DMA_RXVALID); +#endif return addr; } @@ -2397,7 +2402,6 @@ static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev) bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) || skb_is_nonlinear(*skb); int padlen = ETH_ZLEN - (*skb)->len; - int headroom = skb_headroom(*skb); int tailroom = skb_tailroom(*skb); struct sk_buff *nskb; u32 fcs; @@ -2411,9 +2415,6 @@ static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev) /* FCS could be appeded to tailroom. */ if (tailroom >= ETH_FCS_LEN) goto add_fcs; - /* FCS could be appeded by moving data to headroom. */ - else if (!cloned && headroom + tailroom >= ETH_FCS_LEN) - padlen = 0; /* No room for FCS, need to reallocate skb. */ else padlen = ETH_FCS_LEN; @@ -2422,10 +2423,7 @@ static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev) padlen += ETH_FCS_LEN; } - if (!cloned && headroom + tailroom >= padlen) { - (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len); - skb_set_tail_pointer(*skb, (*skb)->len); - } else { + if (cloned || tailroom < padlen) { nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC); if (!nskb) return -ENOMEM; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-phytium.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-phytium.c index 0dbf6eef7df5af29186cb78af9e271fff18bbb2c..a56d9a19303a375339bec5acee1ddd31d80d131b 100755 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-phytium.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-phytium.c @@ -2,7 +2,7 @@ /* * Phytium SWMAC specific glue layer * - * Copyright (c) 2022-2023, Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 40824860743e3169eb104d15834351d446b9cb39..fa460f43014c687abbd114215e7e31e496df2c70 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -934,6 +934,25 @@ void phylink_destroy(struct phylink *pl) } EXPORT_SYMBOL_GPL(phylink_destroy); +/** + * phylink_expects_phy() - Determine if phylink expects a phy to be attached + * @pl: a pointer to a &struct phylink returned from phylink_create() + * + * When using fixed-link mode, or in-band mode with 1000base-X or 2500base-X, + * no PHY is needed. + * + * Returns true if phylink will be expecting a PHY. + */ +bool phylink_expects_phy(struct phylink *pl) +{ + if (pl->cfg_link_an_mode == MLO_AN_FIXED || + (pl->cfg_link_an_mode == MLO_AN_INBAND && + phy_interface_mode_is_8023z(pl->link_config.interface))) + return false; + return true; +} +EXPORT_SYMBOL_GPL(phylink_expects_phy); + static void phylink_phy_change(struct phy_device *phydev, bool up) { struct phylink *pl = phydev->phylink; diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig index 18450437d5d5ae8265291a4685d5b269a1985214..0fec52ff94ac8fe0c37e5be977fce01ab0e8d1b4 100644 --- a/drivers/of/Kconfig +++ b/drivers/of/Kconfig @@ -100,4 +100,11 @@ config OF_DMA_DEFAULT_COHERENT # arches should select this if DMA is coherent by default for OF devices bool +config OF_CONFIGFS + bool "Device Tree Overlay ConfigFS interface" + select CONFIGFS_FS + select OF_OVERLAY + help + Enable a simple user-space driven DT overlay interface. + endif # OF diff --git a/drivers/of/Makefile b/drivers/of/Makefile index 6e1e5212f05895ee3e67bd5b10f0f25f4fefb92a..3222259b039329ba752ad8e0784dacbc8defc388 100644 --- a/drivers/of/Makefile +++ b/drivers/of/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-y = base.o device.o platform.o property.o obj-$(CONFIG_OF_KOBJ) += kobj.o +obj-$(CONFIG_OF_CONFIGFS) += configfs.o obj-$(CONFIG_OF_DYNAMIC) += dynamic.o obj-$(CONFIG_OF_FLATTREE) += fdt.o obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c new file mode 100644 index 0000000000000000000000000000000000000000..ac04301dabe134ee007d733766b07d1abb600b50 --- /dev/null +++ b/drivers/of/configfs.c @@ -0,0 +1,277 @@ +/* + * Configfs entries for device-tree + * + * Copyright (C) 2013 - Pantelis Antoniou + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "of_private.h" + +struct cfs_overlay_item { + struct config_item item; + + char path[PATH_MAX]; + + const struct firmware *fw; + struct device_node *overlay; + int ov_id; + + void *dtbo; + int dtbo_size; +}; + +static inline struct cfs_overlay_item *to_cfs_overlay_item( + struct config_item *item) +{ + return item ? container_of(item, struct cfs_overlay_item, item) : NULL; +} + +static ssize_t cfs_overlay_item_path_show(struct config_item *item, + char *page) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + return sprintf(page, "%s\n", overlay->path); +} + +static ssize_t cfs_overlay_item_path_store(struct config_item *item, + const char *page, size_t count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + const char *p = page; + char *s; + int err; + + /* if it's set do not allow changes */ + if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) + return -EPERM; + + /* copy to path buffer (and make sure it's always zero terminated */ + count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p); + overlay->path[sizeof(overlay->path) - 1] = '\0'; + + /* strip trailing newlines */ + s = overlay->path + strlen(overlay->path); + while (s > overlay->path && *--s == '\n') + *s = '\0'; + + pr_debug("%s: path is '%s'\n", __func__, overlay->path); + + err = request_firmware(&overlay->fw, overlay->path, NULL); + if (err != 0) + goto out_err; + + err = of_overlay_fdt_apply((void *)overlay->fw->data, + (u32)overlay->fw->size, &overlay->ov_id); + if (err != 0) + goto out_err; + + return count; + +out_err: + + release_firmware(overlay->fw); + overlay->fw = NULL; + + overlay->path[0] = '\0'; + return err; +} + +static ssize_t cfs_overlay_item_status_show(struct config_item *item, + char *page) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + return sprintf(page, "%s\n", + overlay->ov_id > 0 ? "applied" : "unapplied"); +} + +CONFIGFS_ATTR(cfs_overlay_item_, path); +CONFIGFS_ATTR_RO(cfs_overlay_item_, status); + +static struct configfs_attribute *cfs_overlay_attrs[] = { + &cfs_overlay_item_attr_path, + &cfs_overlay_item_attr_status, + NULL, +}; + +ssize_t cfs_overlay_item_dtbo_read(struct config_item *item, + void *buf, size_t max_count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + pr_debug("%s: buf=%p max_count=%zu\n", __func__, + buf, max_count); + + if (overlay->dtbo == NULL) + return 0; + + /* copy if buffer provided */ + if (buf != NULL) { + /* the buffer must be large enough */ + if (overlay->dtbo_size > max_count) + return -ENOSPC; + + memcpy(buf, overlay->dtbo, overlay->dtbo_size); + } + + return overlay->dtbo_size; +} + +ssize_t cfs_overlay_item_dtbo_write(struct config_item *item, + const void *buf, size_t count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + int err; + + /* if it's set do not allow changes */ + if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) + return -EPERM; + + /* copy the contents */ + overlay->dtbo = kmemdup(buf, count, GFP_KERNEL); + if (overlay->dtbo == NULL) + return -ENOMEM; + + overlay->dtbo_size = count; + + err = of_overlay_fdt_apply(overlay->dtbo, overlay->dtbo_size, + &overlay->ov_id); + if (err != 0) + goto out_err; + + return count; + +out_err: + kfree(overlay->dtbo); + overlay->dtbo = NULL; + overlay->dtbo_size = 0; + overlay->ov_id = 0; + + return err; +} + +CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M); + +static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = { + &cfs_overlay_item_attr_dtbo, + NULL, +}; + +static void cfs_overlay_release(struct config_item *item) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + if (overlay->ov_id > 0) + of_overlay_remove(&overlay->ov_id); + if (overlay->fw) + release_firmware(overlay->fw); + /* kfree with NULL is safe */ + kfree(overlay->dtbo); + kfree(overlay); +} + +static struct configfs_item_operations cfs_overlay_item_ops = { + .release = cfs_overlay_release, +}; + +static struct config_item_type cfs_overlay_type = { + .ct_item_ops = &cfs_overlay_item_ops, + .ct_attrs = cfs_overlay_attrs, + .ct_bin_attrs = cfs_overlay_bin_attrs, + .ct_owner = THIS_MODULE, +}; + +static struct config_item *cfs_overlay_group_make_item( + struct config_group *group, const char *name) +{ + struct cfs_overlay_item *overlay; + + overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); + if (!overlay) + return ERR_PTR(-ENOMEM); + + config_item_init_type_name(&overlay->item, name, &cfs_overlay_type); + return &overlay->item; +} + +static void cfs_overlay_group_drop_item(struct config_group *group, + struct config_item *item) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + config_item_put(&overlay->item); +} + +static struct configfs_group_operations overlays_ops = { + .make_item = cfs_overlay_group_make_item, + .drop_item = cfs_overlay_group_drop_item, +}; + +static struct config_item_type overlays_type = { + .ct_group_ops = &overlays_ops, + .ct_owner = THIS_MODULE, +}; + +static struct configfs_group_operations of_cfs_ops = { + /* empty - we don't allow anything to be created */ +}; + +static struct config_item_type of_cfs_type = { + .ct_group_ops = &of_cfs_ops, + .ct_owner = THIS_MODULE, +}; + +struct config_group of_cfs_overlay_group; + +static struct configfs_subsystem of_cfs_subsys = { + .su_group = { + .cg_item = { + .ci_namebuf = "device-tree", + .ci_type = &of_cfs_type, + }, + }, + .su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex), +}; + +static int __init of_cfs_init(void) +{ + int ret; + + pr_info("%s\n", __func__); + + config_group_init(&of_cfs_subsys.su_group); + config_group_init_type_name(&of_cfs_overlay_group, "overlays", + &overlays_type); + configfs_add_default_group(&of_cfs_overlay_group, + &of_cfs_subsys.su_group); + + ret = configfs_register_subsystem(&of_cfs_subsys); + if (ret != 0) { + pr_err("%s: failed to register subsys\n", __func__); + goto out; + } + pr_info("%s: OK\n", __func__); +out: + return ret; +} +late_initcall(of_cfs_init); diff --git a/drivers/pci/controller/pcie-phytium-ep.c b/drivers/pci/controller/pcie-phytium-ep.c index 5f66810e84f42bfef7350f3f9136427339bef31d..816ed10a66bf00613f36c8abab038d14ade5166b 100644 --- a/drivers/pci/controller/pcie-phytium-ep.c +++ b/drivers/pci/controller/pcie-phytium-ep.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Phytium pd2008 pcie endpoint driver * - * Copyright (c) 2021 Phytium Limited. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. * * Author: * Yang Xun diff --git a/drivers/pci/controller/pcie-phytium-ep.h b/drivers/pci/controller/pcie-phytium-ep.h index 10b6a81da2acae2bac1281d8b1f045664b703f42..d53cc010585a421c5c74a43a24aedec9d8d26b27 100644 --- a/drivers/pci/controller/pcie-phytium-ep.h +++ b/drivers/pci/controller/pcie-phytium-ep.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium pd2008 pcie endpoint driver * - * Copyright (c) 2021 Phytium Limited. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. * * Author: * Yang Xun diff --git a/drivers/pci/controller/pcie-phytium-register.h b/drivers/pci/controller/pcie-phytium-register.h index fb006bbf8414541476c84f0f65e7ce4c1d4d162e..9ef1ea4a8b9711bf8bb4f17750d25c8801fb64b5 100644 --- a/drivers/pci/controller/pcie-phytium-register.h +++ b/drivers/pci/controller/pcie-phytium-register.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Phytium Pd2008 pcie endpoint driver * - * Copyright (c) 2021 Phytium Limited. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. * * Author: * Yang Xun diff --git a/drivers/pwm/pwm-phytium.c b/drivers/pwm/pwm-phytium.c index d4cc94dde663eb0e71b7a26c1a249f148cd7ef12..1eaf292952c8c9636bcb5304263603abd6ec130d 100644 --- a/drivers/pwm/pwm-phytium.c +++ b/drivers/pwm/pwm-phytium.c @@ -2,7 +2,7 @@ /* * Phytium PWM driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/remoteproc/homo_remoteproc.c b/drivers/remoteproc/homo_remoteproc.c index 056cabdd73b59a4c703394190ce5c77e16db0f28..71f54cb79a5a912cb67128ebddbf4f716bc6543c 100644 --- a/drivers/remoteproc/homo_remoteproc.c +++ b/drivers/remoteproc/homo_remoteproc.c @@ -1,7 +1,7 @@ /* * Homogeneous Remote Processor Control Driver * - * Copyright (c) 2022-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. * Author: Shaojun Yang * * This program is free software; you can redistribute it and/or modify it under the terms diff --git a/drivers/spi/spi-phytium-pci.c b/drivers/spi/spi-phytium-pci.c index 4b83bc1b5d4204712291780a44b8e8bcf5079955..5bc68634277f3e7036faca9b1b4153e932332141 100644 --- a/drivers/spi/spi-phytium-pci.c +++ b/drivers/spi/spi-phytium-pci.c @@ -2,7 +2,7 @@ /* * Phytium SPI core controller PCI driver. * - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/spi/spi-phytium-plat.c b/drivers/spi/spi-phytium-plat.c index 51805f1b0c0f7f161af91c2d67ba6504998d7244..57593cd0e85bd027c16ecea871396c029e24bae3 100644 --- a/drivers/spi/spi-phytium-plat.c +++ b/drivers/spi/spi-phytium-plat.c @@ -2,7 +2,7 @@ /* * Phytium SPI core controller platform driver. * - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. */ #include #include diff --git a/drivers/spi/spi-phytium-qspi.c b/drivers/spi/spi-phytium-qspi.c index e909a8505d8646637a8d244162438310b2b15c58..8695b627c85c82d1f0430a171c0044171230a734 100755 --- a/drivers/spi/spi-phytium-qspi.c +++ b/drivers/spi/spi-phytium-qspi.c @@ -2,13 +2,14 @@ /* * Phytium Quad SPI controller driver. * - * Copyright (c) 2022-2023, Phytium Technology Co., Ltd. + * Copyright (c) 2022-2024 Phytium Technology Co., Ltd. */ #include #include #include #include +#include #include #include #include @@ -168,6 +169,10 @@ struct phytium_qspi { struct phytium_qspi_flash flash[PHYTIUM_QSPI_MAX_NORCHIP]; u8 fnum; bool nodirmap; + + u32 wr_cfg_reg; + u32 rd_cfg_reg; + u32 flash_cap; }; static bool phytium_qspi_check_buswidth(u8 width) @@ -281,6 +286,29 @@ static int phytium_qspi_flash_capacity_encode(u32 size, u32 *cap) return ret; } +static void phytium_qspi_clear_wr(struct phytium_qspi *qspi, + struct phytium_qspi_flash *flash) +{ + u32 cmd = 0; + u32 state = 0; + int ret = 0; + + cmd |= 0x05 << QSPI_CMD_PORT_CMD_SHIFT; + cmd |= BIT(QSPI_CMD_PORT_TRANSFER_SHIFT); + cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT; + + writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG); + readl_relaxed(qspi->io_base + QSPI_LD_PORT_REG); + + ret = readl_poll_timeout(qspi->io_base + QSPI_LD_PORT_REG, + state, !(state & 0x01), 10, 100000); + if (ret) + dev_err(qspi->dev, "wait device timeout\n"); + + /* clear wr_cfg */ + writel_relaxed(0x0, qspi->io_base + QSPI_WR_CFG_REG); +} + static int phytium_qspi_write_port(struct phytium_qspi *qspi, const u8 *buf, const size_t len) { @@ -468,6 +496,7 @@ static int phytium_qspi_dirmap_create(struct spi_mem_dirmap_desc *desc) cmd |= flash->clk_div & QSPI_RD_CFG_RD_SCK_SEL_MASK; writel_relaxed(cmd, qspi->io_base + QSPI_RD_CFG_REG); + qspi->rd_cfg_reg = cmd; dev_dbg(qspi->dev, "Create read dirmap and setup RD_CFG_REG [%#x].\n", cmd); } else if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) { @@ -484,10 +513,7 @@ static int phytium_qspi_dirmap_create(struct spi_mem_dirmap_desc *desc) cmd |= QSPI_WR_CFG_WR_MODE_MASK; cmd |= flash->clk_div & QSPI_WR_CFG_WR_SCK_SEL_MASK; - - writel_relaxed(cmd, qspi->io_base + QSPI_WR_CFG_REG); - - dev_dbg(qspi->dev, "Create write dirmap and setup WR_CFG_REG [%#x].\n", cmd); + qspi->wr_cfg_reg = cmd; } else { ret = -EINVAL; } @@ -524,6 +550,9 @@ static ssize_t phytium_qspi_dirmap_write(struct spi_mem_dirmap_desc *desc, size_t mask = 0x03; u_char tmp[4] = {0}; + /* set wr_cfg for drimap write */ + writel_relaxed(qspi->wr_cfg_reg, qspi->io_base + QSPI_WR_CFG_REG); + if (offs & 0x03) { dev_err(qspi->dev, "Addr not four-byte aligned!\n"); return -EINVAL; @@ -541,6 +570,8 @@ static ssize_t phytium_qspi_dirmap_write(struct spi_mem_dirmap_desc *desc, //write cache data to flash writel_relaxed(QSPI_FLUSH_EN, qspi->io_base + QSPI_FLUSH_REG); + phytium_qspi_clear_wr(qspi, flash); + return len; } @@ -614,7 +645,6 @@ static int phytium_qspi_probe(struct platform_device *pdev) struct resource *res; struct phytium_qspi *qspi; int i, ret; - u32 flash_cap; struct spi_mem *mem; struct spi_nor *nor; @@ -719,15 +749,15 @@ static int phytium_qspi_probe(struct platform_device *pdev) } ret = phytium_qspi_flash_capacity_encode(qspi->flash[0].size, - &flash_cap); + &qspi->flash_cap); if (ret) { dev_err(dev, "Flash size is invalid.\n"); goto probe_setup_failed; } - flash_cap |= qspi->fnum << QSPI_FLASH_CAP_NUM_SHIFT; + qspi->flash_cap |= qspi->fnum << QSPI_FLASH_CAP_NUM_SHIFT; - writel_relaxed(flash_cap, qspi->io_base + QSPI_FLASH_CAP_REG); + writel_relaxed(qspi->flash_cap, qspi->io_base + QSPI_FLASH_CAP_REG); } return 0; @@ -771,6 +801,11 @@ static int __maybe_unused phytium_qspi_suspend(struct device *dev) static int __maybe_unused phytium_qspi_resume(struct device *dev) { + struct phytium_qspi *qspi = dev_get_drvdata(dev); + + /* set rd_cfg reg and flash_capacity reg after resume */ + writel_relaxed(qspi->rd_cfg_reg, qspi->io_base + QSPI_RD_CFG_REG); + writel_relaxed(qspi->flash_cap, qspi->io_base + QSPI_FLASH_CAP_REG); return pm_runtime_force_resume(dev); } diff --git a/drivers/spi/spi-phytium.c b/drivers/spi/spi-phytium.c index a6f849c5cf1ae1e8cf5a908fb3b6e46c20f4b854..4fae2cd2cac1c9b56a0fb56490c4d62b001f613f 100644 --- a/drivers/spi/spi-phytium.c +++ b/drivers/spi/spi-phytium.c @@ -2,7 +2,7 @@ /* * Phytium SPI core controller driver. * - * Copyright (c) 2019-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2019-2024 Phytium Technology Co., Ltd. */ #include #include @@ -415,6 +415,8 @@ int phytium_spi_add_host(struct device *dev, struct phytium_spi *fts) fts->dma_addr = (dma_addr_t)(fts->paddr + DR); snprintf(fts->name, sizeof(fts->name), "phytium_spi%d", fts->bus_num); + spi_hw_init(dev, fts); + ret = request_irq(fts->irq, phytium_spi_irq, IRQF_SHARED, fts->name, master); if (ret < 0) { dev_err(dev, "can not get IRQ\n"); @@ -436,9 +438,6 @@ int phytium_spi_add_host(struct device *dev, struct phytium_spi *fts) master->flags = SPI_MASTER_GPIO_SS; master->cs_gpios = fts->cs; - spi_hw_init(dev, fts); - - if (fts->dma_ops && fts->dma_ops->dma_init) { ret = fts->dma_ops->dma_init(dev, fts); if (ret) { diff --git a/drivers/tty/serial/phytium-uart.c b/drivers/tty/serial/phytium-uart.c index 084bf9e1f964d7f2e93d5ee5b7978d6c3bb919a8..928126888c926357f17ee1982f03817beed36ca8 100644 --- a/drivers/tty/serial/phytium-uart.c +++ b/drivers/tty/serial/phytium-uart.c @@ -2,7 +2,7 @@ /* * Driver for Phytium PCI UART controller * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/drivers/w1/masters/phytium_w1.c b/drivers/w1/masters/phytium_w1.c index 77badce5c22a3e07fd9bc50a5b4759a99e5738d3..32e41a816637dcb1e51cf00a7a0f77fe3126ec55 100644 --- a/drivers/w1/masters/phytium_w1.c +++ b/drivers/w1/masters/phytium_w1.c @@ -2,7 +2,7 @@ /* * drivers/w1/masters/phytium_w1m.c * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/include/linux/phylink.h b/include/linux/phylink.h index d81a714cfbbdb16dd73711c4f10f3c1445c0f249..5ae0d98ea9cfa4e84dde44a38afb9ddd3859766c 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -436,6 +436,7 @@ struct phylink *phylink_create(struct phylink_config *, struct fwnode_handle *, const struct phylink_mac_ops *mac_ops); void phylink_set_pcs(struct phylink *, struct phylink_pcs *pcs); void phylink_destroy(struct phylink *); +bool phylink_expects_phy(struct phylink *pl); int phylink_connect_phy(struct phylink *, struct phy_device *); int phylink_of_phy_connect(struct phylink *, struct device_node *, u32 flags); diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst index 50d580d77ae920b9c96d52639ec3b229082707db..079b833080110d7383ba5b68abb2120d9eef06b2 100644 --- a/scripts/Makefile.dtbinst +++ b/scripts/Makefile.dtbinst @@ -18,9 +18,10 @@ include scripts/Kbuild.include include $(src)/Makefile dtbs := $(addprefix $(dst)/, $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-))) +dtbos := $(addprefix $(dst)/, $(dtbo-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-))) subdirs := $(addprefix $(obj)/, $(subdir-y) $(subdir-m)) -__dtbs_install: $(dtbs) $(subdirs) +__dtbs_install: $(dtbs) $(dtbos) $(subdirs) @: quiet_cmd_dtb_install = INSTALL $@ @@ -29,6 +30,9 @@ quiet_cmd_dtb_install = INSTALL $@ $(dst)/%.dtb: $(obj)/%.dtb $(call cmd,dtb_install) +$(dst)/%.dtbo: $(obj)/%.dtbo + $(call cmd,dtb_install) + PHONY += $(subdirs) $(subdirs): $(Q)$(MAKE) $(dtbinst)=$@ dst=$(patsubst $(obj)/%,$(dst)/%,$@) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 94133708889d7f0357f6b3c59a3f65f61c61b3b4..11a36fc16af4db186aa9f56ab88b9bf6fd27b3d8 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -281,6 +281,7 @@ DTC_FLAGS += -Wno-interrupt_provider ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),) DTC_FLAGS += -Wno-unit_address_vs_reg \ -Wno-unit_address_format \ + -Wno-gpios_property \ -Wno-avoid_unnecessary_addr_size \ -Wno-alias_paths \ -Wno-graph_child_address \ @@ -341,6 +342,18 @@ endef $(obj)/%.dt.yaml: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE $(call if_changed_rule,dtc,yaml) +quiet_cmd_dtco = DTCO $@ +cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \ + $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ + $(DTC) -@ -H epapr -O dtb -o $@ -b 0 \ + -i $(dir $<) $(DTC_FLAGS) \ + -Wno-interrupts_property \ + -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) + +$(obj)/%.dtbo: $(src)/%.dtso FORCE + $(call if_changed_dep,dtco) + dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) # Bzip2 diff --git a/sound/pci/hda/hda_phytium.c b/sound/pci/hda/hda_phytium.c index 69bfe699d2358ecf9c75bd58e8417b0b00fd774f..aead6f079e728ab33de2b228bf156d539f297973 100644 --- a/sound/pci/hda/hda_phytium.c +++ b/sound/pci/hda/hda_phytium.c @@ -2,7 +2,7 @@ /* * Implementation of primary ALSA driver code for Phytium HD Audio. * - * Copyright (c) 2018-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2018-2024 Phytium Technology Co., Ltd. */ #include diff --git a/sound/pci/hda/hda_phytium.h b/sound/pci/hda/hda_phytium.h index edca12ec6fa7e36baed78f455367e73d1bfaa497..ec1f3e7f7b9cfa52ca5af33a376214efd2fb7947 100644 --- a/sound/pci/hda/hda_phytium.h +++ b/sound/pci/hda/hda_phytium.h @@ -2,7 +2,7 @@ /* * Implementation of primary ALSA driver code base for Phytium HD Audio. * - * Copyright (c) 2018-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2018-2024 Phytium Technology Co., Ltd. */ #ifndef __SOUND_HDA_PHYTIUM_H__ #define __SOUND_HDA_PHYTIUM_H__ diff --git a/sound/soc/codecs/es8388.c b/sound/soc/codecs/es8388.c index 2824b630668664bc3c05add878ca13e9bcb611e3..fbb3f8399ccd636cba8f22e2c4057dd064f6f2a1 100644 --- a/sound/soc/codecs/es8388.c +++ b/sound/soc/codecs/es8388.c @@ -2,7 +2,7 @@ /* * es8388.c -- ES8388 ALSA SoC Audio driver * - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. * Author: Yiqun Zhang * * This program is free software; you can redistribute it and/or modify diff --git a/sound/soc/phytium/local.h b/sound/soc/phytium/local.h index 3076a9588c5c89d7f859ffbc0d46261742795cb8..887facdd72524e406c1b8e3ea4a222133b7445d9 100644 --- a/sound/soc/phytium/local.h +++ b/sound/soc/phytium/local.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. */ #ifndef __PHYTIUM_I2S_LOCAL_H diff --git a/sound/soc/phytium/phytium_i2s.c b/sound/soc/phytium/phytium_i2s.c index 2d028d36b5eb8610609ff540240bc0f72108dfaf..725aafdd64e2741c089a2b62b2e5b6be143781ce 100755 --- a/sound/soc/phytium/phytium_i2s.c +++ b/sound/soc/phytium/phytium_i2s.c @@ -2,7 +2,7 @@ /* * Phytium I2S ASoC driver * - * Copyright (c) 2020-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2020-2024 Phytium Technology Co., Ltd. * * Derived from sound/soc/dwc/dwc-i2s.c * Copyright (C) 2010 ST Microelectronics @@ -1095,23 +1095,22 @@ static int stream_direction(struct azx *chip, unsigned char index) } -void snd_i2s_stream_init(struct i2sc_bus *bus, struct i2s_stream *azx_dev, +void snd_i2s_stream_init(struct i2sc_bus *bus, struct i2s_stream *stream, int idx, int direction, int tag) { - azx_dev->bus = bus; - azx_dev->sd_addr = bus->remap_addr; + stream->bus = bus; + stream->sd_addr = bus->remap_addr; if (idx == 0) - azx_dev->sd_int_sta_mask = 1 << idx; + stream->sd_int_sta_mask = 1 << idx; else - azx_dev->sd_int_sta_mask = 1 << 8; + stream->sd_int_sta_mask = 1 << 8; - azx_dev->index = idx; - azx_dev->direction = direction; - azx_dev->stream_tag = tag; - - list_add_tail(&azx_dev->list, &bus->stream_list); + stream->index = idx; + stream->direction = direction; + stream->stream_tag = tag; + list_add_tail(&stream->list, &bus->stream_list); } int azx_i2s_init_streams(struct azx *chip) @@ -1338,7 +1337,6 @@ static int phytium_i2s_probe(struct platform_device *pdev) err = i2s_phytium_create(pdev, card_num, &chip, i2s); if (err < 0) return err; - i2s = container_of(chip, struct i2s_phytium, chip); schedule_probe = !chip->disabled; dev_set_drvdata(&pdev->dev, i2s); diff --git a/sound/soc/phytium/pmdk_dp.c b/sound/soc/phytium/pmdk_dp.c index ec045e9a4dc1b13381719a447251fde7d387753f..ce56634aef2259e34ca74fe6c67012b4e003eef2 100755 --- a/sound/soc/phytium/pmdk_dp.c +++ b/sound/soc/phytium/pmdk_dp.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include @@ -31,27 +31,6 @@ static const struct snd_soc_dapm_route pmdk_dp_audio_map[] = { {"DP", NULL, "TX"}, }; -static struct snd_soc_jack_pin dp0_pins[] = { - { - .pin = "HDMI/DP,pcm=0", - .mask = SND_JACK_LINEOUT, - }, -}; - -static struct snd_soc_jack_pin dp1_pins[] = { - { - .pin = "HDMI/DP,pcm=1", - .mask = SND_JACK_LINEOUT, - }, -}; - -static struct snd_soc_jack_pin dp2_pins[] = { - { - .pin = "HDMI/DP,pcm=2", - .mask = SND_JACK_LINEOUT, - }, -}; - #define SMDK_DAI_FMT (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | \ SND_SOC_DAIFMT_CBS_CFS) @@ -63,9 +42,8 @@ static int pmdk_dp0_init(struct snd_soc_pcm_runtime *runtime) int ret; ret = snd_soc_card_jack_new(card, "HDMI/DP,pcm=0", - SND_JACK_LINEOUT, - &priv->jack0, dp0_pins, - ARRAY_SIZE(dp0_pins)); + SND_JACK_LINEOUT, &priv->jack0, NULL, 0); + if (ret) { dev_err(card->dev, "Jack creation failed %d\n", ret); return ret; @@ -82,9 +60,7 @@ static int pmdk_dp1_init(struct snd_soc_pcm_runtime *runtime) int ret; ret = snd_soc_card_jack_new(card, "HDMI/DP,pcm=1", - SND_JACK_LINEOUT, - &priv->jack1, dp1_pins, - ARRAY_SIZE(dp1_pins)); + SND_JACK_LINEOUT, &priv->jack1, NULL, 0); if (ret) { dev_err(card->dev, "Jack creation failed %d\n", ret); @@ -102,9 +78,8 @@ static int pmdk_dp2_init(struct snd_soc_pcm_runtime *runtime) int ret; ret = snd_soc_card_jack_new(card, "HDMI/DP,pcm=2", - SND_JACK_LINEOUT, - &priv->jack2, dp2_pins, - ARRAY_SIZE(dp2_pins)); + SND_JACK_LINEOUT, &priv->jack2, NULL, 0); + if (ret) { dev_err(card->dev, "Jack creation failed %d\n", ret); return ret; diff --git a/sound/soc/phytium/pmdk_es8336.c b/sound/soc/phytium/pmdk_es8336.c index f27404373a266bdaa0dd8833cb3bc13f5ae6bb59..77d2e272c90a2d521f9fc17c70cdf1aff9cb919e 100644 --- a/sound/soc/phytium/pmdk_es8336.c +++ b/sound/soc/phytium/pmdk_es8336.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include diff --git a/sound/soc/phytium/pmdk_es8388.c b/sound/soc/phytium/pmdk_es8388.c index 81b61c1323d8d814e08a179a057b2759eb0f7def..57e17313c91655ab4439f6bf9938b7169c73e39e 100644 --- a/sound/soc/phytium/pmdk_es8388.c +++ b/sound/soc/phytium/pmdk_es8388.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2021-2023 Phytium Technology Co., Ltd. + * Copyright (c) 2021-2024 Phytium Technology Co., Ltd. */ #include