From 50ce43317ac6b23883a262b1b641742817eb5ac5 Mon Sep 17 00:00:00 2001 From: 1576988680 <1576988680@qq.com> Date: Thu, 17 Jun 2021 17:24:38 +0800 Subject: [PATCH] update file --- .../bsp/drivers/GD32E10x_Firmware/board.patch | 40 +- .../drivers/GD32E10x_Firmware/driver.patch | 4030 +++++------ .../drivers/GD32E10x_Firmware/patch.sha256 | 4 +- .../bsp/drivers/GD32F30x_Firmware/board.patch | 40 +- .../drivers/GD32F30x_Firmware/driver.patch | 5982 ++++++++--------- .../drivers/GD32VF103_Firmware/board.patch | 70 +- .../drivers/GD32VF103_Firmware/driver.patch | 3050 ++++----- 7 files changed, 6608 insertions(+), 6608 deletions(-) diff --git a/targets/bsp/drivers/GD32E10x_Firmware/board.patch b/targets/bsp/drivers/GD32E10x_Firmware/board.patch index 90c06a1..15fee9b 100644 --- a/targets/bsp/drivers/GD32E10x_Firmware/board.patch +++ b/targets/bsp/drivers/GD32E10x_Firmware/board.patch @@ -3,24 +3,24 @@ index bae9f71..5f81975 --- a/Inc/gd32e10x.h +++ b/Inc/gd32e10x.h @@ -203,8 +203,8 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) - #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) - #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) --#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) --#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) -+#define GD_BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -+#define GET_BITS(regval, start, end) (((regval) & GD_BITS((start),(end))) >> (start)) - - /* main flash and SRAM memory map */ - #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ + #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) + #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) + #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +-#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +-#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) ++#define GD_BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) ++#define GET_BITS(regval, start, end) (((regval) & GD_BITS((start),(end))) >> (start)) + + /* main flash and SRAM memory map */ + #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ @@ -247,10 +247,6 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - #define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ - #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ - --/* define marco USE_STDPERIPH_DRIVER */ --#if !defined USE_STDPERIPH_DRIVER --#define USE_STDPERIPH_DRIVER --#endif - #ifdef USE_STDPERIPH_DRIVER - #include "gd32e10x_libopt.h" - #endif /* USE_STDPERIPH_DRIVER */ + #define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ + #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ + +-/* define marco USE_STDPERIPH_DRIVER */ +-#if !defined USE_STDPERIPH_DRIVER +-#define USE_STDPERIPH_DRIVER +-#endif + #ifdef USE_STDPERIPH_DRIVER + #include "gd32e10x_libopt.h" + #endif /* USE_STDPERIPH_DRIVER */ diff --git a/targets/bsp/drivers/GD32E10x_Firmware/driver.patch b/targets/bsp/drivers/GD32E10x_Firmware/driver.patch index bdab98e..3515f93 100644 --- a/targets/bsp/drivers/GD32E10x_Firmware/driver.patch +++ b/targets/bsp/drivers/GD32E10x_Firmware/driver.patch @@ -3,2222 +3,2222 @@ index bae9f71..565db4d --- a/GD32E10x_Firmware_Library/Firmware/CMSIS/GD/GD32E10x/Include/gd32e10x.h +++ b/GD32E10x_Firmware_Library/Firmware/CMSIS/GD/GD32E10x/Include/gd32e10x.h @@ -203,8 +203,8 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) - #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) - #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) --#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) --#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) -+#define GD_BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -+#define GET_BITS(regval, start, end) (((regval) & GD_BITS((start),(end))) >> (start)) - - /* main flash and SRAM memory map */ - #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ + #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) + #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) + #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +-#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +-#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) ++#define GD_BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) ++#define GET_BITS(regval, start, end) (((regval) & GD_BITS((start),(end))) >> (start)) + + /* main flash and SRAM memory map */ + #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_adc.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_adc.h index c3d0bf4..75a2d7c --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_adc.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_adc.h @@ -75,7 +75,7 @@ OF SUCH DAMAGE. - #define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ - - /* ADC_CTL0 */ --#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -+#define ADC_CTL0_WDCHSEL GD_BITS(0,4) /*!< analog watchdog channel select bits */ - #define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ - #define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ - #define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ + #define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ + + /* ADC_CTL0 */ +-#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ ++#define ADC_CTL0_WDCHSEL GD_BITS(0,4) /*!< analog watchdog channel select bits */ + #define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ + #define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ + #define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ @@ -84,8 +84,8 @@ OF SUCH DAMAGE. - #define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ - #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ - #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ --#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ --#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ -+#define ADC_CTL0_DISNUM GD_BITS(13,15) /*!< discontinuous mode channel count */ -+#define ADC_CTL0_SYNCM GD_BITS(16,19) /*!< sync mode selection */ - #define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ - #define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ - + #define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ + #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ + #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +-#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +-#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ ++#define ADC_CTL0_DISNUM GD_BITS(13,15) /*!< discontinuous mode channel count */ ++#define ADC_CTL0_SYNCM GD_BITS(16,19) /*!< sync mode selection */ + #define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ + #define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ + @@ -96,47 +96,47 @@ OF SUCH DAMAGE. - #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ - #define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ - #define ADC_CTL1_DAL BIT(11) /*!< data alignment */ --#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ -+#define ADC_CTL1_ETSIC GD_BITS(12,14) /*!< external trigger select for inserted channel */ - #define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ --#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ -+#define ADC_CTL1_ETSRC GD_BITS(17,19) /*!< external trigger select for regular channel */ - #define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ - #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ - #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ - #define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ - - /* ADC_SAMPTx x=0..1 */ --#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */ -+#define ADC_SAMPTX_SPTN GD_BITS(0,2) /*!< channel n sample time selection */ - - /* ADC_IOFFx x=0..3 */ --#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ -+#define ADC_IOFFX_IOFF GD_BITS(0,11) /*!< data offset for inserted channel x */ - - /* ADC_WDHT */ --#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ -+#define ADC_WDHT_WDHT GD_BITS(0,11) /*!< analog watchdog high threshold */ - - /* ADC_WDLT */ --#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ -+#define ADC_WDLT_WDLT GD_BITS(0,11) /*!< analog watchdog low threshold */ - - /* ADC_RSQx x=0..2 */ --#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */ --#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ -+#define ADC_RSQX_RSQN GD_BITS(0,4) /*!< nth conversion in regular sequence */ -+#define ADC_RSQ0_RL GD_BITS(20,23) /*!< regular channel sequence length */ - - /* ADC_ISQ */ --#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */ --#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ -+#define ADC_ISQ_ISQN GD_BITS(0,4) /*!< nth conversion in inserted sequence */ -+#define ADC_ISQ_IL GD_BITS(20,21) /*!< inserted sequence length */ - - /* ADC_IDATAx x=0..3 */ --#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */ -+#define ADC_IDATAX_IDATAN GD_BITS(0,15) /*!< inserted data n */ - - /* ADC_RDATA */ --#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ --#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ -+#define ADC_RDATA_RDATA GD_BITS(0,15) /*!< regular data */ -+#define ADC_RDATA_ADC1RDTR GD_BITS(16,31) /*!< ADC1 regular channel data */ - - /* ADC_OVSAMPCTL */ - #define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ --#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ --#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ -+#define ADC_OVSAMPCTL_OVSR GD_BITS(2,4) /*!< oversampling ratio */ -+#define ADC_OVSAMPCTL_OVSS GD_BITS(5,8) /*!< oversampling shift */ - #define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ --#define ADC_OVSAMPCTL_DRES BITS(12,13) /*!< ADC resolution */ -+#define ADC_OVSAMPCTL_DRES GD_BITS(12,13) /*!< ADC resolution */ - - /* constants definitions */ - /* adc_stat register value */ + #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ + #define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ + #define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +-#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ ++#define ADC_CTL1_ETSIC GD_BITS(12,14) /*!< external trigger select for inserted channel */ + #define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ +-#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ ++#define ADC_CTL1_ETSRC GD_BITS(17,19) /*!< external trigger select for regular channel */ + #define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ + #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ + #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ + #define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ + + /* ADC_SAMPTx x=0..1 */ +-#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */ ++#define ADC_SAMPTX_SPTN GD_BITS(0,2) /*!< channel n sample time selection */ + + /* ADC_IOFFx x=0..3 */ +-#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ ++#define ADC_IOFFX_IOFF GD_BITS(0,11) /*!< data offset for inserted channel x */ + + /* ADC_WDHT */ +-#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ ++#define ADC_WDHT_WDHT GD_BITS(0,11) /*!< analog watchdog high threshold */ + + /* ADC_WDLT */ +-#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ ++#define ADC_WDLT_WDLT GD_BITS(0,11) /*!< analog watchdog low threshold */ + + /* ADC_RSQx x=0..2 */ +-#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */ +-#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ ++#define ADC_RSQX_RSQN GD_BITS(0,4) /*!< nth conversion in regular sequence */ ++#define ADC_RSQ0_RL GD_BITS(20,23) /*!< regular channel sequence length */ + + /* ADC_ISQ */ +-#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */ +-#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ ++#define ADC_ISQ_ISQN GD_BITS(0,4) /*!< nth conversion in inserted sequence */ ++#define ADC_ISQ_IL GD_BITS(20,21) /*!< inserted sequence length */ + + /* ADC_IDATAx x=0..3 */ +-#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */ ++#define ADC_IDATAX_IDATAN GD_BITS(0,15) /*!< inserted data n */ + + /* ADC_RDATA */ +-#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ +-#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ ++#define ADC_RDATA_RDATA GD_BITS(0,15) /*!< regular data */ ++#define ADC_RDATA_ADC1RDTR GD_BITS(16,31) /*!< ADC1 regular channel data */ + + /* ADC_OVSAMPCTL */ + #define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ +-#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ +-#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ ++#define ADC_OVSAMPCTL_OVSR GD_BITS(2,4) /*!< oversampling ratio */ ++#define ADC_OVSAMPCTL_OVSS GD_BITS(5,8) /*!< oversampling shift */ + #define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ +-#define ADC_OVSAMPCTL_DRES BITS(12,13) /*!< ADC resolution */ ++#define ADC_OVSAMPCTL_DRES GD_BITS(12,13) /*!< ADC resolution */ + + /* constants definitions */ + /* adc_stat register value */ @@ -147,7 +147,7 @@ OF SUCH DAMAGE. - #define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ - - /* adc_ctl0 register value */ --#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ -+#define CTL0_DISNUM(regval) (GD_BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ - - /* scan mode */ - #define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ + #define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ + + /* adc_ctl0 register value */ +-#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ ++#define CTL0_DISNUM(regval) (GD_BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ + + /* scan mode */ + #define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ @@ -156,7 +156,7 @@ OF SUCH DAMAGE. - #define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ - - /* ADC sync mode */ --#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ -+#define CTL0_SYNCM(regval) (GD_BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ - #define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ - #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ - #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ + #define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ + + /* ADC sync mode */ +-#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ ++#define CTL0_SYNCM(regval) (GD_BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ + #define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ + #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ + #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ @@ -176,7 +176,7 @@ OF SUCH DAMAGE. - #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ - - /* external trigger select for regular channel */ --#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ -+#define CTL1_ETSRC(regval) (GD_BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ - #define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ - #define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ - #define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ + #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + + /* external trigger select for regular channel */ +-#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ ++#define CTL1_ETSRC(regval) (GD_BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ + #define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ + #define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ + #define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ @@ -188,7 +188,7 @@ OF SUCH DAMAGE. - #define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ - - /* external trigger mode for inserted channel */ --#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ -+#define CTL1_ETSIC(regval) (GD_BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ - #define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< timer 0 TRGO event select */ - #define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< timer 0 CC3 event select */ - #define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< timer 1 TRGO event select */ + #define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ + + /* external trigger mode for inserted channel */ +-#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ ++#define CTL1_ETSIC(regval) (GD_BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ + #define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< timer 0 TRGO event select */ + #define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< timer 0 CC3 event select */ + #define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< timer 1 TRGO event select */ @@ -200,7 +200,7 @@ OF SUCH DAMAGE. - #define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ - - /* adc_samptx register value */ --#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ -+#define SAMPTX_SPT(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ - #define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ - #define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ - #define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ + #define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ + + /* adc_samptx register value */ +-#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ ++#define SAMPTX_SPT(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ + #define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ + #define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ + #define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ @@ -211,30 +211,30 @@ OF SUCH DAMAGE. - #define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ - - /* adc_ioffx register value */ --#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ -+#define IOFFX_IOFF(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ - - /* adc_wdht register value */ --#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ -+#define WDHT_WDHT(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ - - /* adc_wdlt register value */ --#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ -+#define WDLT_WDLT(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ - - /* adc_rsqx register value */ --#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ -+#define RSQ0_RL(regval) (GD_BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ - - /* adc_isq register value */ --#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ -+#define ISQ_IL(regval) (GD_BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ - - /* adc_ovsampctl register value */ - /* ADC resolution */ --#define OVSAMPCTL_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ -+#define OVSAMPCTL_DRES(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ - #define ADC_RESOLUTION_12B OVSAMPCTL_DRES(0) /*!< 12-bit ADC resolution */ - #define ADC_RESOLUTION_10B OVSAMPCTL_DRES(1) /*!< 10-bit ADC resolution */ - #define ADC_RESOLUTION_8B OVSAMPCTL_DRES(2) /*!< 8-bit ADC resolution */ - #define ADC_RESOLUTION_6B OVSAMPCTL_DRES(3) /*!< 6-bit ADC resolution */ - - /* oversampling shift */ --#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ -+#define OVSAMPCTL_OVSS(regval) (GD_BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ - #define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ - #define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ - #define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ + #define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ + + /* adc_ioffx register value */ +-#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ ++#define IOFFX_IOFF(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ + + /* adc_wdht register value */ +-#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ ++#define WDHT_WDHT(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ + + /* adc_wdlt register value */ +-#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ ++#define WDLT_WDLT(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ + + /* adc_rsqx register value */ +-#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ ++#define RSQ0_RL(regval) (GD_BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ + + /* adc_isq register value */ +-#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ ++#define ISQ_IL(regval) (GD_BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ + + /* adc_ovsampctl register value */ + /* ADC resolution */ +-#define OVSAMPCTL_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ ++#define OVSAMPCTL_DRES(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ + #define ADC_RESOLUTION_12B OVSAMPCTL_DRES(0) /*!< 12-bit ADC resolution */ + #define ADC_RESOLUTION_10B OVSAMPCTL_DRES(1) /*!< 10-bit ADC resolution */ + #define ADC_RESOLUTION_8B OVSAMPCTL_DRES(2) /*!< 8-bit ADC resolution */ + #define ADC_RESOLUTION_6B OVSAMPCTL_DRES(3) /*!< 6-bit ADC resolution */ + + /* oversampling shift */ +-#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ ++#define OVSAMPCTL_OVSS(regval) (GD_BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ + #define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ + #define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ + #define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ @@ -246,7 +246,7 @@ OF SUCH DAMAGE. - #define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ - - /* oversampling ratio */ --#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ -+#define OVSAMPCTL_OVSR(regval) (GD_BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ - #define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ - #define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ - #define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ + #define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ + + /* oversampling ratio */ +-#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ ++#define OVSAMPCTL_OVSR(regval) (GD_BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ + #define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ + #define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ + #define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_bkp.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_bkp.h index 2d8f481..39e8ae9 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_bkp.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_bkp.h @@ -91,10 +91,10 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* BKP_DATA */ --#define BKP_DATA BITS(0,15) /*!< backup data */ -+#define BKP_DATA GD_BITS(0,15) /*!< backup data */ - - /* BKP_OCTL */ --#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ -+#define BKP_OCTL_RCCV GD_BITS(0,6) /*!< RTC clock calibration value */ - #define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ - #define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ - #define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ + + /* bits definitions */ + /* BKP_DATA */ +-#define BKP_DATA BITS(0,15) /*!< backup data */ ++#define BKP_DATA GD_BITS(0,15) /*!< backup data */ + + /* BKP_OCTL */ +-#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ ++#define BKP_OCTL_RCCV GD_BITS(0,6) /*!< RTC clock calibration value */ + #define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ + #define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ + #define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ @@ -168,7 +168,7 @@ typedef enum - #define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) - - /* RTC clock calibration value */ --#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -+#define OCTL_RCCV(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) - - /* RTC output selection */ - #define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ + #define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) + + /* RTC clock calibration value */ +-#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) ++#define OCTL_RCCV(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) + + /* RTC output selection */ + #define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_can.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_can.h index 777418a..13a64e1 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_can.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_can.h @@ -194,7 +194,7 @@ OF SUCH DAMAGE. - #define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ - #define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ - #define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ --#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ -+#define CAN_TSTAT_NUM GD_BITS(24,25) /*!< mailbox number */ - #define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ - #define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ - #define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ + #define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ + #define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ + #define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ +-#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ ++#define CAN_TSTAT_NUM GD_BITS(24,25) /*!< mailbox number */ + #define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ + #define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ + #define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ @@ -203,13 +203,13 @@ OF SUCH DAMAGE. - #define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ - - /* CAN_RFIFO0 */ --#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ -+#define CAN_RFIFO0_RFL0 GD_BITS(0,1) /*!< receive FIFO0 length */ - #define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ - #define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ - #define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ - - /* CAN_RFIFO1 */ --#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ -+#define CAN_RFIFO1_RFL1 GD_BITS(0,1) /*!< receive FIFO1 length */ - #define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ - #define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ - #define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ + #define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ + + /* CAN_RFIFO0 */ +-#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ ++#define CAN_RFIFO0_RFL0 GD_BITS(0,1) /*!< receive FIFO0 length */ + #define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ + #define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ + #define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ + + /* CAN_RFIFO1 */ +-#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ ++#define CAN_RFIFO1_RFL1 GD_BITS(0,1) /*!< receive FIFO1 length */ + #define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ + #define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ + #define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ @@ -234,17 +234,17 @@ OF SUCH DAMAGE. - #define CAN_ERR_WERR BIT(0) /*!< warning error */ - #define CAN_ERR_PERR BIT(1) /*!< passive error */ - #define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ --#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ --#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ --#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ -+#define CAN_ERR_ERRN GD_BITS(4,6) /*!< error number */ -+#define CAN_ERR_TECNT GD_BITS(16,23) /*!< transmit error count */ -+#define CAN_ERR_RECNT GD_BITS(24,31) /*!< receive error count */ - - /* CAN_BT */ --#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ --#define CAN_BT_BS1_6_4 BITS(10,12) /*!< bit segment 1 [6:4] */ --#define CAN_BT_BS2_4_3 BITS(13,14) /*!< bit segment 2 [4:3] */ --#define CAN_BT_BS1_3_0 BITS(16,19) /*!< bit segment 1 [3:0] */ --#define CAN_BT_BS2_2_0 BITS(20,22) /*!< bit segment 2 [2:0]*/ --#define CAN_BT_SJW BITS(24,28) /*!< resynchronization jump width */ -+#define CAN_BT_BAUDPSC GD_BITS(0,9) /*!< baudrate prescaler */ -+#define CAN_BT_BS1_6_4 GD_BITS(10,12) /*!< bit segment 1 [6:4] */ -+#define CAN_BT_BS2_4_3 GD_BITS(13,14) /*!< bit segment 2 [4:3] */ -+#define CAN_BT_BS1_3_0 GD_BITS(16,19) /*!< bit segment 1 [3:0] */ -+#define CAN_BT_BS2_2_0 GD_BITS(20,22) /*!< bit segment 2 [2:0]*/ -+#define CAN_BT_SJW GD_BITS(24,28) /*!< resynchronization jump width */ - #define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ - #define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ - + #define CAN_ERR_WERR BIT(0) /*!< warning error */ + #define CAN_ERR_PERR BIT(1) /*!< passive error */ + #define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ +-#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ +-#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ +-#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ ++#define CAN_ERR_ERRN GD_BITS(4,6) /*!< error number */ ++#define CAN_ERR_TECNT GD_BITS(16,23) /*!< transmit error count */ ++#define CAN_ERR_RECNT GD_BITS(24,31) /*!< receive error count */ + + /* CAN_BT */ +-#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ +-#define CAN_BT_BS1_6_4 BITS(10,12) /*!< bit segment 1 [6:4] */ +-#define CAN_BT_BS2_4_3 BITS(13,14) /*!< bit segment 2 [4:3] */ +-#define CAN_BT_BS1_3_0 BITS(16,19) /*!< bit segment 1 [3:0] */ +-#define CAN_BT_BS2_2_0 BITS(20,22) /*!< bit segment 2 [2:0]*/ +-#define CAN_BT_SJW BITS(24,28) /*!< resynchronization jump width */ ++#define CAN_BT_BAUDPSC GD_BITS(0,9) /*!< baudrate prescaler */ ++#define CAN_BT_BS1_6_4 GD_BITS(10,12) /*!< bit segment 1 [6:4] */ ++#define CAN_BT_BS2_4_3 GD_BITS(13,14) /*!< bit segment 2 [4:3] */ ++#define CAN_BT_BS1_3_0 GD_BITS(16,19) /*!< bit segment 1 [3:0] */ ++#define CAN_BT_BS2_2_0 GD_BITS(20,22) /*!< bit segment 2 [2:0]*/ ++#define CAN_BT_SJW GD_BITS(24,28) /*!< resynchronization jump width */ + #define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ + #define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ + @@ -257,75 +257,75 @@ OF SUCH DAMAGE. - #define CAN_FDCTL_ESIMOD BIT(6) /*!< error state indicator mode */ - - /* CAN_FDSTAT */ --#define CAN_FDSTAT_TDCV BITS(0,6) /*!< transmitter delay compensation value */ -+#define CAN_FDSTAT_TDCV GD_BITS(0,6) /*!< transmitter delay compensation value */ - #define CAN_FDSTAT_PRE BIT(16) /*!< protocol exception event */ - - /* CAN_FDTDC */ --#define CAN_FDTDC_TDCF BITS(0,6) /*!< transmitter delay compensation filter */ --#define CAN_FDTDC_TDCO BITS(8,14) /*!< transmitter delay compensation offset */ -+#define CAN_FDTDC_TDCF GD_BITS(0,6) /*!< transmitter delay compensation filter */ -+#define CAN_FDTDC_TDCO GD_BITS(8,14) /*!< transmitter delay compensation offset */ - - /* CAN_DBT */ --#define CAN_DBT_DBAUDPSC BITS(0,9) /*!< baud rate prescaler */ --#define CAN_DBT_DBS1 BITS(16,19) /*!< bit segment 1 */ --#define CAN_DBT_DBS2 BITS(20,22) /*!< bit segment 2 */ --#define CAN_DBT_DSJW BITS(24,26) /*!< resynchronization jump width */ -+#define CAN_DBT_DBAUDPSC GD_BITS(0,9) /*!< baud rate prescaler */ -+#define CAN_DBT_DBS1 GD_BITS(16,19) /*!< bit segment 1 */ -+#define CAN_DBT_DBS2 GD_BITS(20,22) /*!< bit segment 2 */ -+#define CAN_DBT_DSJW GD_BITS(24,26) /*!< resynchronization jump width */ - - /* CAN_TMIx */ - #define CAN_TMI_TEN BIT(0) /*!< transmit enable */ - #define CAN_TMI_FT BIT(1) /*!< frame type */ - #define CAN_TMI_FF BIT(2) /*!< frame format */ --#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ --#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ -+#define CAN_TMI_EFID GD_BITS(3,31) /*!< the frame identifier */ -+#define CAN_TMI_SFID GD_BITS(21,31) /*!< the frame identifier */ - - /* CAN_TMPx */ --#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ -+#define CAN_TMP_DLENC GD_BITS(0,3) /*!< data length code */ - #define CAN_TMP_ESI BIT(4) /*!< error status indicator */ - #define CAN_TMP_BRS BIT(5) /*!< bit rate of data switch */ - #define CAN_TMP_FDF BIT(7) /*!< CAN FD frame flag */ - #define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ --#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ -+#define CAN_TMP_TS GD_BITS(16,31) /*!< time stamp */ - - /* CAN_TMDATA0x */ --#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ --#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ --#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ --#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ -+#define CAN_TMDATA0_DB0 GD_BITS(0,7) /*!< transmit data byte 0 */ -+#define CAN_TMDATA0_DB1 GD_BITS(8,15) /*!< transmit data byte 1 */ -+#define CAN_TMDATA0_DB2 GD_BITS(16,23) /*!< transmit data byte 2 */ -+#define CAN_TMDATA0_DB3 GD_BITS(24,31) /*!< transmit data byte 3 */ - - /* CAN_TMDATA1x */ --#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ --#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ --#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ --#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ -+#define CAN_TMDATA1_DB4 GD_BITS(0,7) /*!< transmit data byte 4 */ -+#define CAN_TMDATA1_DB5 GD_BITS(8,15) /*!< transmit data byte 5 */ -+#define CAN_TMDATA1_DB6 GD_BITS(16,23) /*!< transmit data byte 6 */ -+#define CAN_TMDATA1_DB7 GD_BITS(24,31) /*!< transmit data byte 7 */ - - /* CAN_RFIFOMIx */ - #define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ - #define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ --#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ --#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ -+#define CAN_RFIFOMI_EFID GD_BITS(3,31) /*!< the frame identifier */ -+#define CAN_RFIFOMI_SFID GD_BITS(21,31) /*!< the frame identifier */ - - /* CAN_RFIFOMPx */ --#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ -+#define CAN_RFIFOMP_DLENC GD_BITS(0,3) /*!< receive data length code */ - #define CAN_RFIFOMP_ESI BIT(4) /*!< error status indicator */ - #define CAN_RFIFOMP_BRS BIT(5) /*!< bit rate of data switch */ - #define CAN_RFIFOMP_FDF BIT(7) /*!< CAN FD frame flag */ --#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ --#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ -+#define CAN_RFIFOMP_FI GD_BITS(8,15) /*!< filter index */ -+#define CAN_RFIFOMP_TS GD_BITS(16,31) /*!< time stamp */ - - /* CAN_RFIFOMDATA0x */ --#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ --#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ --#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ --#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ -+#define CAN_RFIFOMDATA0_DB0 GD_BITS(0,7) /*!< receive data byte 0 */ -+#define CAN_RFIFOMDATA0_DB1 GD_BITS(8,15) /*!< receive data byte 1 */ -+#define CAN_RFIFOMDATA0_DB2 GD_BITS(16,23) /*!< receive data byte 2 */ -+#define CAN_RFIFOMDATA0_DB3 GD_BITS(24,31) /*!< receive data byte 3 */ - - /* CAN_RFIFOMDATA1x */ --#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ --#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ --#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ --#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ -+#define CAN_RFIFOMDATA1_DB4 GD_BITS(0,7) /*!< receive data byte 4 */ -+#define CAN_RFIFOMDATA1_DB5 GD_BITS(8,15) /*!< receive data byte 5 */ -+#define CAN_RFIFOMDATA1_DB6 GD_BITS(16,23) /*!< receive data byte 6 */ -+#define CAN_RFIFOMDATA1_DB7 GD_BITS(24,31) /*!< receive data byte 7 */ - - /* CAN_FCTL */ - #define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ --#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ -+#define CAN_FCTL_HBC1F GD_BITS(8,13) /*!< header bank of CAN1 filter */ - - /* CAN_FMCFG */ - #define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ + #define CAN_FDCTL_ESIMOD BIT(6) /*!< error state indicator mode */ + + /* CAN_FDSTAT */ +-#define CAN_FDSTAT_TDCV BITS(0,6) /*!< transmitter delay compensation value */ ++#define CAN_FDSTAT_TDCV GD_BITS(0,6) /*!< transmitter delay compensation value */ + #define CAN_FDSTAT_PRE BIT(16) /*!< protocol exception event */ + + /* CAN_FDTDC */ +-#define CAN_FDTDC_TDCF BITS(0,6) /*!< transmitter delay compensation filter */ +-#define CAN_FDTDC_TDCO BITS(8,14) /*!< transmitter delay compensation offset */ ++#define CAN_FDTDC_TDCF GD_BITS(0,6) /*!< transmitter delay compensation filter */ ++#define CAN_FDTDC_TDCO GD_BITS(8,14) /*!< transmitter delay compensation offset */ + + /* CAN_DBT */ +-#define CAN_DBT_DBAUDPSC BITS(0,9) /*!< baud rate prescaler */ +-#define CAN_DBT_DBS1 BITS(16,19) /*!< bit segment 1 */ +-#define CAN_DBT_DBS2 BITS(20,22) /*!< bit segment 2 */ +-#define CAN_DBT_DSJW BITS(24,26) /*!< resynchronization jump width */ ++#define CAN_DBT_DBAUDPSC GD_BITS(0,9) /*!< baud rate prescaler */ ++#define CAN_DBT_DBS1 GD_BITS(16,19) /*!< bit segment 1 */ ++#define CAN_DBT_DBS2 GD_BITS(20,22) /*!< bit segment 2 */ ++#define CAN_DBT_DSJW GD_BITS(24,26) /*!< resynchronization jump width */ + + /* CAN_TMIx */ + #define CAN_TMI_TEN BIT(0) /*!< transmit enable */ + #define CAN_TMI_FT BIT(1) /*!< frame type */ + #define CAN_TMI_FF BIT(2) /*!< frame format */ +-#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ +-#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ ++#define CAN_TMI_EFID GD_BITS(3,31) /*!< the frame identifier */ ++#define CAN_TMI_SFID GD_BITS(21,31) /*!< the frame identifier */ + + /* CAN_TMPx */ +-#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ ++#define CAN_TMP_DLENC GD_BITS(0,3) /*!< data length code */ + #define CAN_TMP_ESI BIT(4) /*!< error status indicator */ + #define CAN_TMP_BRS BIT(5) /*!< bit rate of data switch */ + #define CAN_TMP_FDF BIT(7) /*!< CAN FD frame flag */ + #define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ +-#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ ++#define CAN_TMP_TS GD_BITS(16,31) /*!< time stamp */ + + /* CAN_TMDATA0x */ +-#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ +-#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ +-#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ +-#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ ++#define CAN_TMDATA0_DB0 GD_BITS(0,7) /*!< transmit data byte 0 */ ++#define CAN_TMDATA0_DB1 GD_BITS(8,15) /*!< transmit data byte 1 */ ++#define CAN_TMDATA0_DB2 GD_BITS(16,23) /*!< transmit data byte 2 */ ++#define CAN_TMDATA0_DB3 GD_BITS(24,31) /*!< transmit data byte 3 */ + + /* CAN_TMDATA1x */ +-#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ +-#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ +-#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ +-#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ ++#define CAN_TMDATA1_DB4 GD_BITS(0,7) /*!< transmit data byte 4 */ ++#define CAN_TMDATA1_DB5 GD_BITS(8,15) /*!< transmit data byte 5 */ ++#define CAN_TMDATA1_DB6 GD_BITS(16,23) /*!< transmit data byte 6 */ ++#define CAN_TMDATA1_DB7 GD_BITS(24,31) /*!< transmit data byte 7 */ + + /* CAN_RFIFOMIx */ + #define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ + #define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ +-#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ +-#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ ++#define CAN_RFIFOMI_EFID GD_BITS(3,31) /*!< the frame identifier */ ++#define CAN_RFIFOMI_SFID GD_BITS(21,31) /*!< the frame identifier */ + + /* CAN_RFIFOMPx */ +-#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ ++#define CAN_RFIFOMP_DLENC GD_BITS(0,3) /*!< receive data length code */ + #define CAN_RFIFOMP_ESI BIT(4) /*!< error status indicator */ + #define CAN_RFIFOMP_BRS BIT(5) /*!< bit rate of data switch */ + #define CAN_RFIFOMP_FDF BIT(7) /*!< CAN FD frame flag */ +-#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ +-#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ ++#define CAN_RFIFOMP_FI GD_BITS(8,15) /*!< filter index */ ++#define CAN_RFIFOMP_TS GD_BITS(16,31) /*!< time stamp */ + + /* CAN_RFIFOMDATA0x */ +-#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ +-#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ +-#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ +-#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ ++#define CAN_RFIFOMDATA0_DB0 GD_BITS(0,7) /*!< receive data byte 0 */ ++#define CAN_RFIFOMDATA0_DB1 GD_BITS(8,15) /*!< receive data byte 1 */ ++#define CAN_RFIFOMDATA0_DB2 GD_BITS(16,23) /*!< receive data byte 2 */ ++#define CAN_RFIFOMDATA0_DB3 GD_BITS(24,31) /*!< receive data byte 3 */ + + /* CAN_RFIFOMDATA1x */ +-#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ +-#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ +-#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ +-#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ ++#define CAN_RFIFOMDATA1_DB4 GD_BITS(0,7) /*!< receive data byte 4 */ ++#define CAN_RFIFOMDATA1_DB5 GD_BITS(8,15) /*!< receive data byte 5 */ ++#define CAN_RFIFOMDATA1_DB6 GD_BITS(16,23) /*!< receive data byte 6 */ ++#define CAN_RFIFOMDATA1_DB7 GD_BITS(24,31) /*!< receive data byte 7 */ + + /* CAN_FCTL */ + #define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ +-#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ ++#define CAN_FCTL_HBC1F GD_BITS(8,13) /*!< header bank of CAN1 filter */ + + /* CAN_FMCFG */ + #define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ @@ -524,64 +524,64 @@ typedef enum - }can_struct_type_enum; - - /* CAN baudrate prescaler*/ --#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) -+#define BT_BAUDPSC(regval) (GD_BITS(0,9) & ((uint32_t)(regval) << 0)) - - /* CAN bit segment 1*/ --#define BT_BS1(regval) ((BITS(16,19) & ((uint32_t)(regval) << 16)) | (BITS(10,12) & ((uint32_t)(regval) << 6))) --#define BT_DBS1(regval) ((BITS(16,19) & ((uint32_t)(regval) << 16))) -+#define BT_BS1(regval) ((GD_BITS(16,19) & ((uint32_t)(regval) << 16)) | (GD_BITS(10,12) & ((uint32_t)(regval) << 6))) -+#define BT_DBS1(regval) ((GD_BITS(16,19) & ((uint32_t)(regval) << 16))) - - /* CAN bit segment 2*/ --#define BT_BS2(regval) ((BITS(20,22) & ((uint32_t)(regval) << 20)) | (BITS(13,14) & ((uint32_t)(regval) << 10))) --#define BT_DBS2(regval) ((BITS(20,22)) & ((uint32_t)(regval) << 20)) -+#define BT_BS2(regval) ((GD_BITS(20,22) & ((uint32_t)(regval) << 20)) | (GD_BITS(13,14) & ((uint32_t)(regval) << 10))) -+#define BT_DBS2(regval) ((GD_BITS(20,22)) & ((uint32_t)(regval) << 20)) - - /* CAN resynchronization jump width*/ --#define BT_SJW(regval) (BITS(24,28) & ((uint32_t)(regval) << 24)) --#define BT_DSJW(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) -+#define BT_SJW(regval) (GD_BITS(24,28) & ((uint32_t)(regval) << 24)) -+#define BT_DSJW(regval) (GD_BITS(24,26) & ((uint32_t)(regval) << 24)) - --#define FDTDC_TDCF(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) --#define FDTDC_TDCO(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) -+#define FDTDC_TDCF(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) -+#define FDTDC_TDCO(regval) (GD_BITS(8,14) & ((uint32_t)(regval) << 8)) - - /* CAN communication mode*/ --#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) -+#define BT_MODE(regval) (GD_BITS(30,31) & ((uint32_t)(regval) << 30)) - - /* CAN FDATA high 16 bits */ --#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) -+#define FDATA_MASK_HIGH(regval) (GD_BITS(16,31) & ((uint32_t)(regval) << 16)) - - /* CAN FDATA low 16 bits */ --#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -+#define FDATA_MASK_LOW(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) - - /* CAN1 filter start bank_number*/ --#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) -+#define FCTL_HBC1F(regval) (GD_BITS(8,13) & ((uint32_t)(regval) << 8)) - - /* CAN transmit mailbox extended identifier*/ --#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) -+#define TMI_EFID(regval) (GD_BITS(3,31) & ((uint32_t)(regval) << 3)) - - /* CAN transmit mailbox standard identifier*/ --#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) -+#define TMI_SFID(regval) (GD_BITS(21,31) & ((uint32_t)(regval) << 21)) - - /* transmit data byte 0 */ --#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) -+#define TMDATA0_DB0(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) - - /* transmit data byte 1 */ --#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) -+#define TMDATA0_DB1(regval) (GD_BITS(8,15) & ((uint32_t)(regval) << 8)) - - /* transmit data byte 2 */ --#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -+#define TMDATA0_DB2(regval) (GD_BITS(16,23) & ((uint32_t)(regval) << 16)) - - /* transmit data byte 3 */ --#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) -+#define TMDATA0_DB3(regval) (GD_BITS(24,31) & ((uint32_t)(regval) << 24)) - - /* transmit data byte 4 */ --#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) -+#define TMDATA1_DB4(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) - - /* transmit data byte 5 */ --#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) -+#define TMDATA1_DB5(regval) (GD_BITS(8,15) & ((uint32_t)(regval) << 8)) - - /* transmit data byte 6 */ --#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -+#define TMDATA1_DB6(regval) (GD_BITS(16,23) & ((uint32_t)(regval) << 16)) - - /* transmit data byte 7 */ --#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) -+#define TMDATA1_DB7(regval) (GD_BITS(24,31) & ((uint32_t)(regval) << 24)) - - /* receive mailbox extended identifier*/ - #define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) + }can_struct_type_enum; + + /* CAN baudrate prescaler*/ +-#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) ++#define BT_BAUDPSC(regval) (GD_BITS(0,9) & ((uint32_t)(regval) << 0)) + + /* CAN bit segment 1*/ +-#define BT_BS1(regval) ((BITS(16,19) & ((uint32_t)(regval) << 16)) | (BITS(10,12) & ((uint32_t)(regval) << 6))) +-#define BT_DBS1(regval) ((BITS(16,19) & ((uint32_t)(regval) << 16))) ++#define BT_BS1(regval) ((GD_BITS(16,19) & ((uint32_t)(regval) << 16)) | (GD_BITS(10,12) & ((uint32_t)(regval) << 6))) ++#define BT_DBS1(regval) ((GD_BITS(16,19) & ((uint32_t)(regval) << 16))) + + /* CAN bit segment 2*/ +-#define BT_BS2(regval) ((BITS(20,22) & ((uint32_t)(regval) << 20)) | (BITS(13,14) & ((uint32_t)(regval) << 10))) +-#define BT_DBS2(regval) ((BITS(20,22)) & ((uint32_t)(regval) << 20)) ++#define BT_BS2(regval) ((GD_BITS(20,22) & ((uint32_t)(regval) << 20)) | (GD_BITS(13,14) & ((uint32_t)(regval) << 10))) ++#define BT_DBS2(regval) ((GD_BITS(20,22)) & ((uint32_t)(regval) << 20)) + + /* CAN resynchronization jump width*/ +-#define BT_SJW(regval) (BITS(24,28) & ((uint32_t)(regval) << 24)) +-#define BT_DSJW(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) ++#define BT_SJW(regval) (GD_BITS(24,28) & ((uint32_t)(regval) << 24)) ++#define BT_DSJW(regval) (GD_BITS(24,26) & ((uint32_t)(regval) << 24)) + +-#define FDTDC_TDCF(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) +-#define FDTDC_TDCO(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) ++#define FDTDC_TDCF(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) ++#define FDTDC_TDCO(regval) (GD_BITS(8,14) & ((uint32_t)(regval) << 8)) + + /* CAN communication mode*/ +-#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) ++#define BT_MODE(regval) (GD_BITS(30,31) & ((uint32_t)(regval) << 30)) + + /* CAN FDATA high 16 bits */ +-#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) ++#define FDATA_MASK_HIGH(regval) (GD_BITS(16,31) & ((uint32_t)(regval) << 16)) + + /* CAN FDATA low 16 bits */ +-#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) ++#define FDATA_MASK_LOW(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) + + /* CAN1 filter start bank_number*/ +-#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) ++#define FCTL_HBC1F(regval) (GD_BITS(8,13) & ((uint32_t)(regval) << 8)) + + /* CAN transmit mailbox extended identifier*/ +-#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) ++#define TMI_EFID(regval) (GD_BITS(3,31) & ((uint32_t)(regval) << 3)) + + /* CAN transmit mailbox standard identifier*/ +-#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) ++#define TMI_SFID(regval) (GD_BITS(21,31) & ((uint32_t)(regval) << 21)) + + /* transmit data byte 0 */ +-#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) ++#define TMDATA0_DB0(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) + + /* transmit data byte 1 */ +-#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) ++#define TMDATA0_DB1(regval) (GD_BITS(8,15) & ((uint32_t)(regval) << 8)) + + /* transmit data byte 2 */ +-#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) ++#define TMDATA0_DB2(regval) (GD_BITS(16,23) & ((uint32_t)(regval) << 16)) + + /* transmit data byte 3 */ +-#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) ++#define TMDATA0_DB3(regval) (GD_BITS(24,31) & ((uint32_t)(regval) << 24)) + + /* transmit data byte 4 */ +-#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) ++#define TMDATA1_DB4(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) + + /* transmit data byte 5 */ +-#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) ++#define TMDATA1_DB5(regval) (GD_BITS(8,15) & ((uint32_t)(regval) << 8)) + + /* transmit data byte 6 */ +-#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) ++#define TMDATA1_DB6(regval) (GD_BITS(16,23) & ((uint32_t)(regval) << 16)) + + /* transmit data byte 7 */ +-#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) ++#define TMDATA1_DB7(regval) (GD_BITS(24,31) & ((uint32_t)(regval) << 24)) + + /* receive mailbox extended identifier*/ + #define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) @@ -629,7 +629,7 @@ typedef enum - #define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24, 31) - - /* CAN errors */ --#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -+#define ERR_ERRN(regval) (GD_BITS(4,6) & ((uint32_t)(regval) << 4)) - #define CAN_ERRN_0 ERR_ERRN(0) /* no error */ - #define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ - #define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ + #define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24, 31) + + /* CAN errors */ +-#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) ++#define ERR_ERRN(regval) (GD_BITS(4,6) & ((uint32_t)(regval) << 4)) + #define CAN_ERRN_0 ERR_ERRN(0) /* no error */ + #define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ + #define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_crc.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_crc.h index 048f18d..d5d76a6 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_crc.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_crc.h @@ -49,10 +49,10 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* CRC_DATA */ --#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ -+#define CRC_DATA_DATA GD_BITS(0,31) /*!< CRC calculation result bits */ - - /* CRC_FDATA */ --#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ -+#define CRC_FDATA_FDATA GD_BITS(0,7) /*!< CRC free data bits */ - - /* CRC_CTL */ - #define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ + + /* bits definitions */ + /* CRC_DATA */ +-#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ ++#define CRC_DATA_DATA GD_BITS(0,31) /*!< CRC calculation result bits */ + + /* CRC_FDATA */ +-#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ ++#define CRC_FDATA_FDATA GD_BITS(0,7) /*!< CRC free data bits */ + + /* CRC_CTL */ + #define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_ctc.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_ctc.h index dd1559a..4126e00 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_ctc.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_ctc.h @@ -57,13 +57,13 @@ OF SUCH DAMAGE. - #define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ - #define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ - #define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ --#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ -+#define CTC_CTL0_TRIMVALUE GD_BITS(8,13) /*!< IRC48M trim value */ - - /* CTC_CTL1 */ --#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ --#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ --#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ --#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ -+#define CTC_CTL1_RLVALUE GD_BITS(0,15) /*!< CTC counter reload value */ -+#define CTC_CTL1_CKLIM GD_BITS(16,23) /*!< clock trim base limit value */ -+#define CTC_CTL1_REFPSC GD_BITS(24,26) /*!< reference signal source prescaler */ -+#define CTC_CTL1_REFSEL GD_BITS(28,29) /*!< reference signal source selection */ - #define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ - - /* CTC_STAT */ + #define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ + #define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ + #define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ +-#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ ++#define CTC_CTL0_TRIMVALUE GD_BITS(8,13) /*!< IRC48M trim value */ + + /* CTC_CTL1 */ +-#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ +-#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ +-#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ +-#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ ++#define CTC_CTL1_RLVALUE GD_BITS(0,15) /*!< CTC counter reload value */ ++#define CTC_CTL1_CKLIM GD_BITS(16,23) /*!< clock trim base limit value */ ++#define CTC_CTL1_REFPSC GD_BITS(24,26) /*!< reference signal source prescaler */ ++#define CTC_CTL1_REFSEL GD_BITS(28,29) /*!< reference signal source selection */ + #define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ + + /* CTC_STAT */ @@ -75,7 +75,7 @@ OF SUCH DAMAGE. - #define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ - #define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ - #define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ --#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ -+#define CTC_STAT_REFCAP GD_BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ - - /* CTC_INTC */ - #define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ + #define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ + #define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ + #define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ +-#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ ++#define CTC_STAT_REFCAP GD_BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ + + /* CTC_INTC */ + #define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ @@ -93,13 +93,13 @@ OF SUCH DAMAGE. - #define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ - - /* reference signal source selection definitions */ --#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -+#define CTL1_REFSEL(regval) (GD_BITS(28,29) & ((uint32_t)(regval) << 28)) - #define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ - #define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is selected */ - #define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBFS_SOF is selected */ - - /* reference signal source prescaler definitions */ --#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) -+#define CTL1_REFPSC(regval) (GD_BITS(24,26) & ((uint32_t)(regval) << 24)) - #define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ - #define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ - #define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ + #define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ + + /* reference signal source selection definitions */ +-#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) ++#define CTL1_REFSEL(regval) (GD_BITS(28,29) & ((uint32_t)(regval) << 28)) + #define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ + #define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is selected */ + #define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBFS_SOF is selected */ + + /* reference signal source prescaler definitions */ +-#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) ++#define CTL1_REFPSC(regval) (GD_BITS(24,26) & ((uint32_t)(regval) << 24)) + #define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ + #define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ + #define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_dac.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_dac.h index 6c1e301..14bec95 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_dac.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_dac.h @@ -64,16 +64,16 @@ OF SUCH DAMAGE. - #define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ - #define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ - #define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ --#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ --#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ --#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ -+#define DAC_CTL_DTSEL0 GD_BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ -+#define DAC_CTL_DWM0 GD_BITS(6,7) /*!< DAC0 noise wave mode */ -+#define DAC_CTL_DWBW0 GD_BITS(8,11) /*!< DAC0 noise wave bit width */ - #define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ - #define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ - #define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ - #define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ --#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ --#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ --#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ -+#define DAC_CTL_DTSEL1 GD_BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ -+#define DAC_CTL_DWM1 GD_BITS(22,23) /*!< DAC1 noise wave mode */ -+#define DAC_CTL_DWBW1 GD_BITS(24,27) /*!< DAC1 noise wave bit width */ - #define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ - - /* DAC_SWT */ + #define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ + #define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ + #define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +-#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +-#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +-#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ ++#define DAC_CTL_DTSEL0 GD_BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ ++#define DAC_CTL_DWM0 GD_BITS(6,7) /*!< DAC0 noise wave mode */ ++#define DAC_CTL_DWBW0 GD_BITS(8,11) /*!< DAC0 noise wave bit width */ + #define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ + #define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ + #define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ + #define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +-#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +-#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +-#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ ++#define DAC_CTL_DTSEL1 GD_BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ ++#define DAC_CTL_DWM1 GD_BITS(22,23) /*!< DAC1 noise wave mode */ ++#define DAC_CTL_DWBW1 GD_BITS(24,27) /*!< DAC1 noise wave bit width */ + #define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ + + /* DAC_SWT */ @@ -81,44 +81,44 @@ OF SUCH DAMAGE. - #define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ - - /* DAC0_R12DH */ --#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ -+#define DAC0_R12DH_DAC0_DH GD_BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ - - /* DAC0_L12DH */ --#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ -+#define DAC0_L12DH_DAC0_DH GD_BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ - - /* DAC0_R8DH */ --#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ -+#define DAC0_R8DH_DAC0_DH GD_BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ - - /* DAC1_R12DH */ --#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ -+#define DAC1_R12DH_DAC1_DH GD_BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ - - /* DAC1_L12DH */ --#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ -+#define DAC1_L12DH_DAC1_DH GD_BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ - - /* DAC1_R8DH */ --#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ -+#define DAC1_R8DH_DAC1_DH GD_BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ - - /* DACC_R12DH */ --#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ --#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ -+#define DACC_R12DH_DAC0_DH GD_BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ -+#define DACC_R12DH_DAC1_DH GD_BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ - - /* DACC_L12DH */ --#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ --#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ -+#define DACC_L12DH_DAC0_DH GD_BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ -+#define DACC_L12DH_DAC1_DH GD_BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ - - /* DACC_R8DH */ --#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ --#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ -+#define DACC_R8DH_DAC0_DH GD_BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ -+#define DACC_R8DH_DAC1_DH GD_BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ - - /* DAC0_DO */ --#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ -+#define DAC0_DO_DAC0_DO GD_BITS(0,11) /*!< DAC0 12-bit output data bits */ - - /* DAC1_DO */ --#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ -+#define DAC1_DO_DAC1_DO GD_BITS(0,11) /*!< DAC1 12-bit output data bits */ - - /* constants definitions */ - /* DAC trigger source */ --#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -+#define CTL_DTSEL(regval) (GD_BITS(3,5) & ((uint32_t)(regval) << 3)) - #define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ - #define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ - #define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ + #define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ + + /* DAC0_R12DH */ +-#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ ++#define DAC0_R12DH_DAC0_DH GD_BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ + + /* DAC0_L12DH */ +-#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ ++#define DAC0_L12DH_DAC0_DH GD_BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ + + /* DAC0_R8DH */ +-#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ ++#define DAC0_R8DH_DAC0_DH GD_BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ + + /* DAC1_R12DH */ +-#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ ++#define DAC1_R12DH_DAC1_DH GD_BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ + + /* DAC1_L12DH */ +-#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ ++#define DAC1_L12DH_DAC1_DH GD_BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ + + /* DAC1_R8DH */ +-#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ ++#define DAC1_R8DH_DAC1_DH GD_BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ + + /* DACC_R12DH */ +-#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +-#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ ++#define DACC_R12DH_DAC0_DH GD_BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ ++#define DACC_R12DH_DAC1_DH GD_BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ + + /* DACC_L12DH */ +-#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +-#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ ++#define DACC_L12DH_DAC0_DH GD_BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ ++#define DACC_L12DH_DAC1_DH GD_BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ + + /* DACC_R8DH */ +-#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +-#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ ++#define DACC_R8DH_DAC0_DH GD_BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ ++#define DACC_R8DH_DAC1_DH GD_BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ + + /* DAC0_DO */ +-#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ ++#define DAC0_DO_DAC0_DO GD_BITS(0,11) /*!< DAC0 12-bit output data bits */ + + /* DAC1_DO */ +-#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ ++#define DAC1_DO_DAC1_DO GD_BITS(0,11) /*!< DAC1 12-bit output data bits */ + + /* constants definitions */ + /* DAC trigger source */ +-#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) ++#define CTL_DTSEL(regval) (GD_BITS(3,5) & ((uint32_t)(regval) << 3)) + #define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ + #define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ + #define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ @@ -129,13 +129,13 @@ OF SUCH DAMAGE. - #define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ - - /* DAC noise wave mode */ --#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -+#define CTL_DWM(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6)) - #define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ - #define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ - #define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ - - /* DAC noise wave bit width */ --#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -+#define DWBW(regval) (GD_BITS(8,11) & ((uint32_t)(regval) << 8)) - #define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ - #define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ - #define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ + #define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ + + /* DAC noise wave mode */ +-#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) ++#define CTL_DWM(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6)) + #define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ + #define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ + #define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ + + /* DAC noise wave bit width */ +-#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) ++#define DWBW(regval) (GD_BITS(8,11) & ((uint32_t)(regval) << 8)) + #define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ + #define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ + #define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ @@ -164,7 +164,7 @@ OF SUCH DAMAGE. - #define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ - - /* DAC data alignment */ --#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -+#define DATA_ALIGN(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) - #define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */ - #define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */ - #define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */ + #define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + + /* DAC data alignment */ +-#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) ++#define DATA_ALIGN(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) + #define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */ + #define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */ + #define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_dbg.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_dbg.h index a3eae25..598aec7 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_dbg.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_dbg.h @@ -48,14 +48,14 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* DBG_ID */ --#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ -+#define DBG_ID_ID_CODE GD_BITS(0,31) /*!< DBG ID code values */ - - /* DBG_CTL */ - #define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ - #define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ - #define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ - #define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ --#define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ -+#define DBG_CTL_TRACE_MODE GD_BITS(6,7) /*!< trace pin mode selection */ - #define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ - #define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ - #define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ + + /* bits definitions */ + /* DBG_ID */ +-#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ ++#define DBG_ID_ID_CODE GD_BITS(0,31) /*!< DBG ID code values */ + + /* DBG_CTL */ + #define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ + #define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ + #define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ + #define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ +-#define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ ++#define DBG_CTL_TRACE_MODE GD_BITS(6,7) /*!< trace pin mode selection */ + #define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ + #define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ + #define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ @@ -108,7 +108,7 @@ typedef enum - }dbg_periph_enum; - - /* DBG_CTL0_TRACE_MODE configurations */ --#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) -+#define CTL_TRACE_MODE(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6U)) - #define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */ - #define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ - #define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ + }dbg_periph_enum; + + /* DBG_CTL0_TRACE_MODE configurations */ +-#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) ++#define CTL_TRACE_MODE(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6U)) + #define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */ + #define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ + #define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_dma.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_dma.h index c727bd7..ca169e9 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_dma.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_dma.h @@ -97,19 +97,19 @@ OF SUCH DAMAGE. - #define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ - #define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ - #define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ --#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ --#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ --#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ -+#define DMA_CHXCTL_PWIDTH GD_BITS(8,9) /*!< transfer data width of peripheral */ -+#define DMA_CHXCTL_MWIDTH GD_BITS(10,11) /*!< transfer data width of memory */ -+#define DMA_CHXCTL_PRIO GD_BITS(12,13) /*!< priority level */ - #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ - - /* DMA_CHxCNT,x=0..6 */ --#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ -+#define DMA_CHXCNT_CNT GD_BITS(0,15) /*!< transfer counter */ - - /* DMA_CHxPADDR,x=0..6 */ --#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ -+#define DMA_CHXPADDR_PADDR GD_BITS(0,31) /*!< peripheral base address */ - - /* DMA_CHxMADDR,x=0..6 */ --#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ -+#define DMA_CHXMADDR_MADDR GD_BITS(0,31) /*!< memory base address */ - - /* constants definitions */ - /* DMA channel select */ + #define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ + #define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ + #define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ +-#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ +-#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ +-#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ ++#define DMA_CHXCTL_PWIDTH GD_BITS(8,9) /*!< transfer data width of peripheral */ ++#define DMA_CHXCTL_MWIDTH GD_BITS(10,11) /*!< transfer data width of memory */ ++#define DMA_CHXCTL_PRIO GD_BITS(12,13) /*!< priority level */ + #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ + + /* DMA_CHxCNT,x=0..6 */ +-#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ ++#define DMA_CHXCNT_CNT GD_BITS(0,15) /*!< transfer counter */ + + /* DMA_CHxPADDR,x=0..6 */ +-#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ ++#define DMA_CHXPADDR_PADDR GD_BITS(0,31) /*!< peripheral base address */ + + /* DMA_CHxMADDR,x=0..6 */ +-#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ ++#define DMA_CHXMADDR_MADDR GD_BITS(0,31) /*!< memory base address */ + + /* constants definitions */ + /* DMA channel select */ @@ -186,19 +186,19 @@ typedef struct - #define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of memory is increasing address mode */ - - /* transfer data size of peripheral */ --#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ -+#define CHCTL_PWIDTH(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ - #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */ - #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */ - #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */ - - /* transfer data size of memory */ --#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ -+#define CHCTL_MWIDTH(regval) (GD_BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ - #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */ - #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */ - #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */ - - /* channel priority level */ --#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ -+#define CHCTL_PRIO(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ - #define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ - #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ - #define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ + #define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of memory is increasing address mode */ + + /* transfer data size of peripheral */ +-#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ ++#define CHCTL_PWIDTH(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ + #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */ + #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */ + #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */ + + /* transfer data size of memory */ +-#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ ++#define CHCTL_MWIDTH(regval) (GD_BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ + #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */ + #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */ + #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */ + + /* channel priority level */ +-#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ ++#define CHCTL_PRIO(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ + #define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ + #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ + #define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_exmc.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_exmc.h index d65c088..ed2ef3c --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_exmc.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_exmc.h @@ -52,8 +52,8 @@ OF SUCH DAMAGE. - /* EXMC_SNCTL */ - #define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR region enable */ - #define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR region memory address/data multiplexing */ --#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR region memory type */ --#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR region memory data bus width */ -+#define EXMC_SNCTL_NRTP GD_BITS(2,3) /*!< NOR region memory type */ -+#define EXMC_SNCTL_NRW GD_BITS(4,5) /*!< NOR region memory data bus width */ - #define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ - #define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ - #define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ + /* EXMC_SNCTL */ + #define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR region enable */ + #define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR region memory address/data multiplexing */ +-#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR region memory type */ +-#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR region memory data bus width */ ++#define EXMC_SNCTL_NRTP GD_BITS(2,3) /*!< NOR region memory type */ ++#define EXMC_SNCTL_NRW GD_BITS(4,5) /*!< NOR region memory data bus width */ + #define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ + #define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ + #define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ @@ -63,24 +63,24 @@ OF SUCH DAMAGE. - #define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ - #define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ - #define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ --#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ -+#define EXMC_SNCTL_CPS GD_BITS(16,18) /*!< CRAM page size */ - #define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */ - - /* EXMC_SNTCFG */ --#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ --#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ --#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ --#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ --#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ --#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ --#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ -+#define EXMC_SNTCFG_ASET GD_BITS(0,3) /*!< address setup time */ -+#define EXMC_SNTCFG_AHLD GD_BITS(4,7) /*!< address hold time */ -+#define EXMC_SNTCFG_DSET GD_BITS(8,15) /*!< data setup time */ -+#define EXMC_SNTCFG_BUSLAT GD_BITS(16,19) /*!< bus latency */ -+#define EXMC_SNTCFG_CKDIV GD_BITS(20,23) /*!< synchronous clock divide ratio */ -+#define EXMC_SNTCFG_DLAT GD_BITS(24,27) /*!< data latency for NOR flash */ -+#define EXMC_SNTCFG_ASYNCMOD GD_BITS(28,29) /*!< asynchronous access mode */ - - /* EXMC_SNWTCFG */ --#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */ --#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */ --#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */ --#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ --#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ -+#define EXMC_SNWTCFG_WASET GD_BITS(0,3) /*!< address setup time */ -+#define EXMC_SNWTCFG_WAHLD GD_BITS(4,7) /*!< address hold time */ -+#define EXMC_SNWTCFG_WDSET GD_BITS(8,15) /*!< data setup time */ -+#define EXMC_SNWTCFG_WBUSLAT GD_BITS(16,19) /*!< bus latency */ -+#define EXMC_SNWTCFG_WASYNCMOD GD_BITS(28,29) /*!< asynchronous access mode */ - - /* constants definitions */ - /* EXMC NOR/SRAM timing initialize struct */ + #define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ + #define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ + #define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ +-#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ ++#define EXMC_SNCTL_CPS GD_BITS(16,18) /*!< CRAM page size */ + #define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */ + + /* EXMC_SNTCFG */ +-#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ +-#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ +-#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ +-#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ +-#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ +-#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ +-#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ ++#define EXMC_SNTCFG_ASET GD_BITS(0,3) /*!< address setup time */ ++#define EXMC_SNTCFG_AHLD GD_BITS(4,7) /*!< address hold time */ ++#define EXMC_SNTCFG_DSET GD_BITS(8,15) /*!< data setup time */ ++#define EXMC_SNTCFG_BUSLAT GD_BITS(16,19) /*!< bus latency */ ++#define EXMC_SNTCFG_CKDIV GD_BITS(20,23) /*!< synchronous clock divide ratio */ ++#define EXMC_SNTCFG_DLAT GD_BITS(24,27) /*!< data latency for NOR flash */ ++#define EXMC_SNTCFG_ASYNCMOD GD_BITS(28,29) /*!< asynchronous access mode */ + + /* EXMC_SNWTCFG */ +-#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */ +-#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */ +-#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */ +-#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ +-#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ ++#define EXMC_SNWTCFG_WASET GD_BITS(0,3) /*!< address setup time */ ++#define EXMC_SNWTCFG_WAHLD GD_BITS(4,7) /*!< address hold time */ ++#define EXMC_SNWTCFG_WDSET GD_BITS(8,15) /*!< data setup time */ ++#define EXMC_SNWTCFG_WBUSLAT GD_BITS(16,19) /*!< bus latency */ ++#define EXMC_SNWTCFG_WASYNCMOD GD_BITS(28,29) /*!< asynchronous access mode */ + + /* constants definitions */ + /* EXMC NOR/SRAM timing initialize struct */ @@ -116,7 +116,7 @@ typedef struct - }exmc_norsram_parameter_struct; - - /* CRAM page size */ --#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) -+#define SNCTL_CPS(regval) (GD_BITS(16,18) & ((uint32_t)(regval) << 16)) - #define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ - #define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ - #define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ + }exmc_norsram_parameter_struct; + + /* CRAM page size */ +-#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) ++#define SNCTL_CPS(regval) (GD_BITS(16,18) & ((uint32_t)(regval) << 16)) + #define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ + #define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ + #define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ @@ -124,25 +124,25 @@ typedef struct - #define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ - - /* NOR region memory data bus width */ --#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -+#define SNCTL_NRW(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) - #define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ - #define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ - - /* NOR region memory type */ --#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -+#define SNCTL_NRTP(regval) (GD_BITS(2,3) & ((uint32_t)(regval) << 2)) - #define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ - #define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ - #define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ - - /* asynchronous access mode */ --#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -+#define SNTCFG_ASYNCMOD(regval) (GD_BITS(28,29) & ((uint32_t)(regval) << 28)) - #define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ - #define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ - #define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ - #define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ - - /* data latency for NOR flash */ --#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -+#define SNTCFG_DLAT(regval) (GD_BITS(24,27) & ((uint32_t)(regval) << 24)) - #define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */ - #define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */ - #define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */ + #define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ + + /* NOR region memory data bus width */ +-#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) ++#define SNCTL_NRW(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) + #define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ + #define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ + + /* NOR region memory type */ +-#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) ++#define SNCTL_NRTP(regval) (GD_BITS(2,3) & ((uint32_t)(regval) << 2)) + #define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ + #define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ + #define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ + + /* asynchronous access mode */ +-#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) ++#define SNTCFG_ASYNCMOD(regval) (GD_BITS(28,29) & ((uint32_t)(regval) << 28)) + #define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ + #define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ + #define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ + #define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ + + /* data latency for NOR flash */ +-#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) ++#define SNTCFG_DLAT(regval) (GD_BITS(24,27) & ((uint32_t)(regval) << 24)) + #define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */ + #define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */ + #define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */ @@ -161,7 +161,7 @@ typedef struct - #define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */ - - /* synchronous clock divide ratio */ --#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) -+#define SNTCFG_CKDIV(regval) (GD_BITS(20,23) & ((uint32_t)(regval) << 20)) - #define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ - #define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ - #define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ + #define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */ + + /* synchronous clock divide ratio */ +-#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) ++#define SNTCFG_CKDIV(regval) (GD_BITS(20,23) & ((uint32_t)(regval) << 20)) + #define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ + #define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ + #define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_fmc.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_fmc.h index 554f260..dd55348 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_fmc.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_fmc.h @@ -65,7 +65,7 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* FMC_WS */ --#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ -+#define FMC_WS_WSCNT GD_BITS(0,2) /*!< wait state counter */ - #define FMC_WS_PFEN BIT(4) /*!< pre-fetch enable */ - #define FMC_WS_ICEN BIT(9) /*!< IBUS cache enable */ - #define FMC_WS_DCEN BIT(10) /*!< DBUS cache enable */ + + /* bits definitions */ + /* FMC_WS */ +-#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ ++#define FMC_WS_WSCNT GD_BITS(0,2) /*!< wait state counter */ + #define FMC_WS_PFEN BIT(4) /*!< pre-fetch enable */ + #define FMC_WS_ICEN BIT(9) /*!< IBUS cache enable */ + #define FMC_WS_DCEN BIT(10) /*!< DBUS cache enable */ @@ -74,10 +74,10 @@ OF SUCH DAMAGE. - #define FMC_WS_PGW BIT(15) /*!< program width to flash memory */ - - /* FMC_KEY */ --#define FMC_KEY_KEY BITS(0,31) /*!< FMC_CTL unlock key bits */ -+#define FMC_KEY_KEY GD_BITS(0,31) /*!< FMC_CTL unlock key bits */ - - /* FMC_OBKEY */ --#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ -+#define FMC_OBKEY_OBKEY GD_BITS(0,31) /*!< option bytes unlock key bits */ - - /* FMC_STAT */ - #define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ + #define FMC_WS_PGW BIT(15) /*!< program width to flash memory */ + + /* FMC_KEY */ +-#define FMC_KEY_KEY BITS(0,31) /*!< FMC_CTL unlock key bits */ ++#define FMC_KEY_KEY GD_BITS(0,31) /*!< FMC_CTL unlock key bits */ + + /* FMC_OBKEY */ +-#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ ++#define FMC_OBKEY_OBKEY GD_BITS(0,31) /*!< option bytes unlock key bits */ + + /* FMC_STAT */ + #define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ @@ -99,19 +99,19 @@ OF SUCH DAMAGE. - #define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ - - /* FMC_ADDR */ --#define FMC_ADDR_ADDR BITS(0,31) /*!< flash erase/program command address bits */ -+#define FMC_ADDR_ADDR GD_BITS(0,31) /*!< flash erase/program command address bits */ - - /* FMC_OBSTAT */ - #define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ - #define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ --#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ --#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ -+#define FMC_OBSTAT_USER GD_BITS(2,9) /*!< store USER of option bytes block after system reset */ -+#define FMC_OBSTAT_DATA GD_BITS(10,25) /*!< store DATA of option bytes block after system reset. */ - - /* FMC_WP */ --#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ -+#define FMC_WP_WP GD_BITS(0,31) /*!< store WP of option bytes block after system reset */ - - /* FMC_PID */ --#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ -+#define FMC_PID_PID GD_BITS(0,31) /*!< product ID bits */ - - /* constants definitions */ - /* define the FMC bit position and its register index offset */ + #define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ + + /* FMC_ADDR */ +-#define FMC_ADDR_ADDR BITS(0,31) /*!< flash erase/program command address bits */ ++#define FMC_ADDR_ADDR GD_BITS(0,31) /*!< flash erase/program command address bits */ + + /* FMC_OBSTAT */ + #define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ + #define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ +-#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ +-#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ ++#define FMC_OBSTAT_USER GD_BITS(2,9) /*!< store USER of option bytes block after system reset */ ++#define FMC_OBSTAT_DATA GD_BITS(10,25) /*!< store DATA of option bytes block after system reset. */ + + /* FMC_WP */ +-#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ ++#define FMC_WP_WP GD_BITS(0,31) /*!< store WP of option bytes block after system reset */ + + /* FMC_PID */ +-#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ ++#define FMC_PID_PID GD_BITS(0,31) /*!< product ID bits */ + + /* constants definitions */ + /* define the FMC bit position and its register index offset */ @@ -172,7 +172,7 @@ typedef enum - #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ - - /* FMC wait state counter */ --#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) -+#define WS_WSCNT(regval) (GD_BITS(0,2) & ((uint32_t)(regval))) - #define FMC_WAIT_STATE_0 WS_WSCNT(0) /*!< FMC 0 wait */ - #define FMC_WAIT_STATE_1 WS_WSCNT(1) /*!< FMC 1 wait */ - #define FMC_WAIT_STATE_2 WS_WSCNT(2) /*!< FMC 2 wait */ + #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ + + /* FMC wait state counter */ +-#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) ++#define WS_WSCNT(regval) (GD_BITS(0,2) & ((uint32_t)(regval))) + #define FMC_WAIT_STATE_0 WS_WSCNT(0) /*!< FMC 0 wait */ + #define FMC_WAIT_STATE_1 WS_WSCNT(1) /*!< FMC 1 wait */ + #define FMC_WAIT_STATE_2 WS_WSCNT(2) /*!< FMC 2 wait */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_fwdgt.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_fwdgt.h index 4856f09..d222c2b --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_fwdgt.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_fwdgt.h @@ -50,13 +50,13 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* FWDGT_CTL */ --#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ -+#define FWDGT_CTL_CMD GD_BITS(0,15) /*!< FWDGT command value */ - - /* FWDGT_PSC */ --#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ -+#define FWDGT_PSC_PSC GD_BITS(0,2) /*!< FWDGT prescaler divider value */ - - /* FWDGT_RLD */ --#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ -+#define FWDGT_RLD_RLD GD_BITS(0,11) /*!< FWDGT counter reload value */ - - /* FWDGT_STAT */ - #define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ + + /* bits definitions */ + /* FWDGT_CTL */ +-#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ ++#define FWDGT_CTL_CMD GD_BITS(0,15) /*!< FWDGT command value */ + + /* FWDGT_PSC */ +-#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ ++#define FWDGT_PSC_PSC GD_BITS(0,2) /*!< FWDGT prescaler divider value */ + + /* FWDGT_RLD */ +-#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ ++#define FWDGT_RLD_RLD GD_BITS(0,11) /*!< FWDGT counter reload value */ + + /* FWDGT_STAT */ + #define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ @@ -64,7 +64,7 @@ OF SUCH DAMAGE. - - /* constants definitions */ - /* psc register value */ --#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -+#define PSC_PSC(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) - #define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ - #define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ - #define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ + + /* constants definitions */ + /* psc register value */ +-#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) ++#define PSC_PSC(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) + #define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ + #define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ + #define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_gpio.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_gpio.h index 76113ad..000650f --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_gpio.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_gpio.h @@ -72,40 +72,40 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* GPIO_CTL0 */ --#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ --#define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ --#define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ --#define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ --#define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */ --#define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */ --#define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */ --#define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */ --#define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */ --#define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */ --#define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */ --#define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */ --#define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */ --#define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */ --#define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */ --#define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ -+#define GPIO_CTL0_MD0 GD_BITS(0,1) /*!< port 0 mode bits */ -+#define GPIO_CTL0_CTL0 GD_BITS(2,3) /*!< pin 0 configuration bits */ -+#define GPIO_CTL0_MD1 GD_BITS(4,5) /*!< port 1 mode bits */ -+#define GPIO_CTL0_CTL1 GD_BITS(6,7) /*!< pin 1 configuration bits */ -+#define GPIO_CTL0_MD2 GD_BITS(8,9) /*!< port 2 mode bits */ -+#define GPIO_CTL0_CTL2 GD_BITS(10,11) /*!< pin 2 configuration bits */ -+#define GPIO_CTL0_MD3 GD_BITS(12,13) /*!< port 3 mode bits */ -+#define GPIO_CTL0_CTL3 GD_BITS(14,15) /*!< pin 3 configuration bits */ -+#define GPIO_CTL0_MD4 GD_BITS(16,17) /*!< port 4 mode bits */ -+#define GPIO_CTL0_CTL4 GD_BITS(18,19) /*!< pin 4 configuration bits */ -+#define GPIO_CTL0_MD5 GD_BITS(20,21) /*!< port 5 mode bits */ -+#define GPIO_CTL0_CTL5 GD_BITS(22,23) /*!< pin 5 configuration bits */ -+#define GPIO_CTL0_MD6 GD_BITS(24,25) /*!< port 6 mode bits */ -+#define GPIO_CTL0_CTL6 GD_BITS(26,27) /*!< pin 6 configuration bits */ -+#define GPIO_CTL0_MD7 GD_BITS(28,29) /*!< port 7 mode bits */ -+#define GPIO_CTL0_CTL7 GD_BITS(30,31) /*!< pin 7 configuration bits */ - - /* GPIO_CTL1 */ --#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ --#define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ --#define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ --#define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ --#define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */ --#define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */ --#define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */ --#define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */ --#define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */ --#define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */ --#define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */ --#define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */ --#define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */ --#define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */ --#define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */ --#define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ -+#define GPIO_CTL1_MD8 GD_BITS(0,1) /*!< port 8 mode bits */ -+#define GPIO_CTL1_CTL8 GD_BITS(2,3) /*!< pin 8 configuration bits */ -+#define GPIO_CTL1_MD9 GD_BITS(4,5) /*!< port 9 mode bits */ -+#define GPIO_CTL1_CTL9 GD_BITS(6,7) /*!< pin 9 configuration bits */ -+#define GPIO_CTL1_MD10 GD_BITS(8,9) /*!< port 10 mode bits */ -+#define GPIO_CTL1_CTL10 GD_BITS(10,11) /*!< pin 10 configuration bits */ -+#define GPIO_CTL1_MD11 GD_BITS(12,13) /*!< port 11 mode bits */ -+#define GPIO_CTL1_CTL11 GD_BITS(14,15) /*!< pin 11 configuration bits */ -+#define GPIO_CTL1_MD12 GD_BITS(16,17) /*!< port 12 mode bits */ -+#define GPIO_CTL1_CTL12 GD_BITS(18,19) /*!< pin 12 configuration bits */ -+#define GPIO_CTL1_MD13 GD_BITS(20,21) /*!< port 13 mode bits */ -+#define GPIO_CTL1_CTL13 GD_BITS(22,23) /*!< pin 13 configuration bits */ -+#define GPIO_CTL1_MD14 GD_BITS(24,25) /*!< port 14 mode bits */ -+#define GPIO_CTL1_CTL14 GD_BITS(26,27) /*!< pin 14 configuration bits */ -+#define GPIO_CTL1_MD15 GD_BITS(28,29) /*!< port 15 mode bits */ -+#define GPIO_CTL1_CTL15 GD_BITS(30,31) /*!< pin 15 configuration bits */ - - /* GPIO_ISTAT */ - #define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ + + /* bits definitions */ + /* GPIO_CTL0 */ +-#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ +-#define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ +-#define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ +-#define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ +-#define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */ +-#define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */ +-#define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */ +-#define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */ +-#define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */ +-#define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */ +-#define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */ +-#define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */ +-#define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */ +-#define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */ +-#define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */ +-#define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ ++#define GPIO_CTL0_MD0 GD_BITS(0,1) /*!< port 0 mode bits */ ++#define GPIO_CTL0_CTL0 GD_BITS(2,3) /*!< pin 0 configuration bits */ ++#define GPIO_CTL0_MD1 GD_BITS(4,5) /*!< port 1 mode bits */ ++#define GPIO_CTL0_CTL1 GD_BITS(6,7) /*!< pin 1 configuration bits */ ++#define GPIO_CTL0_MD2 GD_BITS(8,9) /*!< port 2 mode bits */ ++#define GPIO_CTL0_CTL2 GD_BITS(10,11) /*!< pin 2 configuration bits */ ++#define GPIO_CTL0_MD3 GD_BITS(12,13) /*!< port 3 mode bits */ ++#define GPIO_CTL0_CTL3 GD_BITS(14,15) /*!< pin 3 configuration bits */ ++#define GPIO_CTL0_MD4 GD_BITS(16,17) /*!< port 4 mode bits */ ++#define GPIO_CTL0_CTL4 GD_BITS(18,19) /*!< pin 4 configuration bits */ ++#define GPIO_CTL0_MD5 GD_BITS(20,21) /*!< port 5 mode bits */ ++#define GPIO_CTL0_CTL5 GD_BITS(22,23) /*!< pin 5 configuration bits */ ++#define GPIO_CTL0_MD6 GD_BITS(24,25) /*!< port 6 mode bits */ ++#define GPIO_CTL0_CTL6 GD_BITS(26,27) /*!< pin 6 configuration bits */ ++#define GPIO_CTL0_MD7 GD_BITS(28,29) /*!< port 7 mode bits */ ++#define GPIO_CTL0_CTL7 GD_BITS(30,31) /*!< pin 7 configuration bits */ + + /* GPIO_CTL1 */ +-#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ +-#define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ +-#define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ +-#define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ +-#define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */ +-#define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */ +-#define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */ +-#define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */ +-#define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */ +-#define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */ +-#define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */ +-#define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */ +-#define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */ +-#define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */ +-#define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */ +-#define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ ++#define GPIO_CTL1_MD8 GD_BITS(0,1) /*!< port 8 mode bits */ ++#define GPIO_CTL1_CTL8 GD_BITS(2,3) /*!< pin 8 configuration bits */ ++#define GPIO_CTL1_MD9 GD_BITS(4,5) /*!< port 9 mode bits */ ++#define GPIO_CTL1_CTL9 GD_BITS(6,7) /*!< pin 9 configuration bits */ ++#define GPIO_CTL1_MD10 GD_BITS(8,9) /*!< port 10 mode bits */ ++#define GPIO_CTL1_CTL10 GD_BITS(10,11) /*!< pin 10 configuration bits */ ++#define GPIO_CTL1_MD11 GD_BITS(12,13) /*!< port 11 mode bits */ ++#define GPIO_CTL1_CTL11 GD_BITS(14,15) /*!< pin 11 configuration bits */ ++#define GPIO_CTL1_MD12 GD_BITS(16,17) /*!< port 12 mode bits */ ++#define GPIO_CTL1_CTL12 GD_BITS(18,19) /*!< pin 12 configuration bits */ ++#define GPIO_CTL1_MD13 GD_BITS(20,21) /*!< port 13 mode bits */ ++#define GPIO_CTL1_CTL13 GD_BITS(22,23) /*!< pin 13 configuration bits */ ++#define GPIO_CTL1_MD14 GD_BITS(24,25) /*!< port 14 mode bits */ ++#define GPIO_CTL1_CTL14 GD_BITS(26,27) /*!< pin 14 configuration bits */ ++#define GPIO_CTL1_MD15 GD_BITS(28,29) /*!< port 15 mode bits */ ++#define GPIO_CTL1_CTL15 GD_BITS(30,31) /*!< pin 15 configuration bits */ + + /* GPIO_ISTAT */ + #define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ @@ -233,8 +233,8 @@ OF SUCH DAMAGE. - #define GPIO_SPD_SPD15 BIT(15) /*!< pin 15 set very high output speed when MDx is 0b11 */ - - /* AFIO_EC */ --#define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */ --#define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */ -+#define AFIO_EC_PIN GD_BITS(0,3) /*!< event output pin selection */ -+#define AFIO_EC_PORT GD_BITS(4,6) /*!< event output port selection */ - #define AFIO_EC_EOE BIT(7) /*!< event output enable */ - - /* AFIO_PCF0 */ + #define GPIO_SPD_SPD15 BIT(15) /*!< pin 15 set very high output speed when MDx is 0b11 */ + + /* AFIO_EC */ +-#define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */ +-#define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */ ++#define AFIO_EC_PIN GD_BITS(0,3) /*!< event output pin selection */ ++#define AFIO_EC_PORT GD_BITS(4,6) /*!< event output port selection */ + #define AFIO_EC_EOE BIT(7) /*!< event output enable */ + + /* AFIO_PCF0 */ @@ -243,12 +243,12 @@ OF SUCH DAMAGE. - #define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ - #define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ - #define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ --#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ --#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ --#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ --#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ -+#define AFIO_PCF0_USART2_REMAP GD_BITS(4,5) /*!< USART2 remapping */ -+#define AFIO_PCF0_TIMER0_REMAP GD_BITS(6,7) /*!< TIMER0 remapping */ -+#define AFIO_PCF0_TIMER1_REMAP GD_BITS(8,9) /*!< TIMER1 remapping */ -+#define AFIO_PCF0_TIMER2_REMAP GD_BITS(10,11) /*!< TIMER2 remapping */ - #define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ --#define AFIO_PCF0_CAN0_REMAP BITS(13,14) /*!< CAN0 remapping */ -+#define AFIO_PCF0_CAN0_REMAP GD_BITS(13,14) /*!< CAN0 remapping */ - #define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ - #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ - #define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */ + #define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ + #define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ + #define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ +-#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ +-#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ +-#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ +-#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ ++#define AFIO_PCF0_USART2_REMAP GD_BITS(4,5) /*!< USART2 remapping */ ++#define AFIO_PCF0_TIMER0_REMAP GD_BITS(6,7) /*!< TIMER0 remapping */ ++#define AFIO_PCF0_TIMER1_REMAP GD_BITS(8,9) /*!< TIMER1 remapping */ ++#define AFIO_PCF0_TIMER2_REMAP GD_BITS(10,11) /*!< TIMER2 remapping */ + #define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ +-#define AFIO_PCF0_CAN0_REMAP BITS(13,14) /*!< CAN0 remapping */ ++#define AFIO_PCF0_CAN0_REMAP GD_BITS(13,14) /*!< CAN0 remapping */ + #define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ + #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ + #define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */ @@ -256,38 +256,38 @@ OF SUCH DAMAGE. - #define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */ - #define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */ - #define AFIO_PCF0_CAN1_REMAP BIT(22) /*!< CAN1 remapping */ --#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ -+#define AFIO_PCF0_SWJ_CFG GD_BITS(24,26) /*!< serial wire JTAG configuration */ - #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ - #define AFIO_PCF0_TIMER1ITR0_REMAP BIT(29) /*!< TIMER1 internal trigger 0 remapping */ - - /* AFIO_EXTISS0 */ --#define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */ --#define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */ --#define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */ --#define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */ -+#define AFIO_EXTI0_SS GD_BITS(0,3) /*!< EXTI 0 sources selection */ -+#define AFIO_EXTI1_SS GD_BITS(4,7) /*!< EXTI 1 sources selection */ -+#define AFIO_EXTI2_SS GD_BITS(8,11) /*!< EXTI 2 sources selection */ -+#define AFIO_EXTI3_SS GD_BITS(12,15) /*!< EXTI 3 sources selection */ - - /* AFIO_EXTISS1 */ --#define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */ --#define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */ --#define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */ --#define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */ -+#define AFIO_EXTI4_SS GD_BITS(0,3) /*!< EXTI 4 sources selection */ -+#define AFIO_EXTI5_SS GD_BITS(4,7) /*!< EXTI 5 sources selection */ -+#define AFIO_EXTI6_SS GD_BITS(8,11) /*!< EXTI 6 sources selection */ -+#define AFIO_EXTI7_SS GD_BITS(12,15) /*!< EXTI 7 sources selection */ - - /* AFIO_EXTISS2 */ --#define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */ --#define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */ --#define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */ --#define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */ -+#define AFIO_EXTI8_SS GD_BITS(0,3) /*!< EXTI 8 sources selection */ -+#define AFIO_EXTI9_SS GD_BITS(4,7) /*!< EXTI 9 sources selection */ -+#define AFIO_EXTI10_SS GD_BITS(8,11) /*!< EXTI 10 sources selection */ -+#define AFIO_EXTI11_SS GD_BITS(12,15) /*!< EXTI 11 sources selection */ - - /* AFIO_EXTISS3 */ --#define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */ --#define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */ --#define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */ --#define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */ -+#define AFIO_EXTI12_SS GD_BITS(0,3) /*!< EXTI 12 sources selection */ -+#define AFIO_EXTI13_SS GD_BITS(4,7) /*!< EXTI 13 sources selection */ -+#define AFIO_EXTI14_SS GD_BITS(8,11) /*!< EXTI 14 sources selection */ -+#define AFIO_EXTI15_SS GD_BITS(12,15) /*!< EXTI 15 sources selection */ - - /* AFIO_PCF1 */ - #define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */ - #define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ --#define AFIO_PCF1_CTC_REMAP BITS(11,12) /*!< CTC remapping */ -+#define AFIO_PCF1_CTC_REMAP GD_BITS(11,12) /*!< CTC remapping */ - - /* AFIO_CPSCTL */ - #define AFIO_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ + #define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */ + #define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */ + #define AFIO_PCF0_CAN1_REMAP BIT(22) /*!< CAN1 remapping */ +-#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ ++#define AFIO_PCF0_SWJ_CFG GD_BITS(24,26) /*!< serial wire JTAG configuration */ + #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ + #define AFIO_PCF0_TIMER1ITR0_REMAP BIT(29) /*!< TIMER1 internal trigger 0 remapping */ + + /* AFIO_EXTISS0 */ +-#define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */ +-#define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */ +-#define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */ +-#define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */ ++#define AFIO_EXTI0_SS GD_BITS(0,3) /*!< EXTI 0 sources selection */ ++#define AFIO_EXTI1_SS GD_BITS(4,7) /*!< EXTI 1 sources selection */ ++#define AFIO_EXTI2_SS GD_BITS(8,11) /*!< EXTI 2 sources selection */ ++#define AFIO_EXTI3_SS GD_BITS(12,15) /*!< EXTI 3 sources selection */ + + /* AFIO_EXTISS1 */ +-#define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */ +-#define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */ +-#define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */ +-#define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */ ++#define AFIO_EXTI4_SS GD_BITS(0,3) /*!< EXTI 4 sources selection */ ++#define AFIO_EXTI5_SS GD_BITS(4,7) /*!< EXTI 5 sources selection */ ++#define AFIO_EXTI6_SS GD_BITS(8,11) /*!< EXTI 6 sources selection */ ++#define AFIO_EXTI7_SS GD_BITS(12,15) /*!< EXTI 7 sources selection */ + + /* AFIO_EXTISS2 */ +-#define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */ +-#define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */ +-#define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */ +-#define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */ ++#define AFIO_EXTI8_SS GD_BITS(0,3) /*!< EXTI 8 sources selection */ ++#define AFIO_EXTI9_SS GD_BITS(4,7) /*!< EXTI 9 sources selection */ ++#define AFIO_EXTI10_SS GD_BITS(8,11) /*!< EXTI 10 sources selection */ ++#define AFIO_EXTI11_SS GD_BITS(12,15) /*!< EXTI 11 sources selection */ + + /* AFIO_EXTISS3 */ +-#define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */ +-#define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */ +-#define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */ +-#define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */ ++#define AFIO_EXTI12_SS GD_BITS(0,3) /*!< EXTI 12 sources selection */ ++#define AFIO_EXTI13_SS GD_BITS(4,7) /*!< EXTI 13 sources selection */ ++#define AFIO_EXTI14_SS GD_BITS(8,11) /*!< EXTI 14 sources selection */ ++#define AFIO_EXTI15_SS GD_BITS(12,15) /*!< EXTI 15 sources selection */ + + /* AFIO_PCF1 */ + #define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */ + #define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ +-#define AFIO_PCF1_CTC_REMAP BITS(11,12) /*!< CTC remapping */ ++#define AFIO_PCF1_CTC_REMAP GD_BITS(11,12) /*!< CTC remapping */ + + /* AFIO_CPSCTL */ + #define AFIO_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ @@ -383,16 +383,16 @@ typedef FlagStatus bit_status; - #define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ - #define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ - #define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ --#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ -+#define GPIO_PIN_ALL GD_BITS(0,15) /*!< GPIO pin all */ - - /* AFIO remap */ --#define PCF0_USART2_REMAP(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< USART2 remapping */ --#define PCF0_TIMER0_REMAP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< TIMER0 remapping */ --#define PCF0_TIMER1_REMAP(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< TIMER1 remapping */ --#define PCF0_TIMER2_REMAP(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< TIMER2 remapping */ --#define PCF0_CAN_REMAP(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< CAN remapping */ --#define PCF0_SWJ_CFG(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) /*!< serial wire JTAG configuration */ --#define PCF1_CTC_REMAP(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< CTC remapping */ -+#define PCF0_USART2_REMAP(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< USART2 remapping */ -+#define PCF0_TIMER0_REMAP(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< TIMER0 remapping */ -+#define PCF0_TIMER1_REMAP(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< TIMER1 remapping */ -+#define PCF0_TIMER2_REMAP(regval) (GD_BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< TIMER2 remapping */ -+#define PCF0_CAN_REMAP(regval) (GD_BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< CAN remapping */ -+#define PCF0_SWJ_CFG(regval) (GD_BITS(24,26) & ((uint32_t)(regval) << 24)) /*!< serial wire JTAG configuration */ -+#define PCF1_CTC_REMAP(regval) (GD_BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< CTC remapping */ - - /* GPIO remap definitions */ - #define GPIO_SPI0_REMAP AFIO_PCF0_SPI0_REMAP /*!< SPI0 remapping */ + #define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ + #define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ + #define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +-#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ ++#define GPIO_PIN_ALL GD_BITS(0,15) /*!< GPIO pin all */ + + /* AFIO remap */ +-#define PCF0_USART2_REMAP(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< USART2 remapping */ +-#define PCF0_TIMER0_REMAP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< TIMER0 remapping */ +-#define PCF0_TIMER1_REMAP(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< TIMER1 remapping */ +-#define PCF0_TIMER2_REMAP(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< TIMER2 remapping */ +-#define PCF0_CAN_REMAP(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< CAN remapping */ +-#define PCF0_SWJ_CFG(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) /*!< serial wire JTAG configuration */ +-#define PCF1_CTC_REMAP(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< CTC remapping */ ++#define PCF0_USART2_REMAP(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< USART2 remapping */ ++#define PCF0_TIMER0_REMAP(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< TIMER0 remapping */ ++#define PCF0_TIMER1_REMAP(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< TIMER1 remapping */ ++#define PCF0_TIMER2_REMAP(regval) (GD_BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< TIMER2 remapping */ ++#define PCF0_CAN_REMAP(regval) (GD_BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< CAN remapping */ ++#define PCF0_SWJ_CFG(regval) (GD_BITS(24,26) & ((uint32_t)(regval) << 24)) /*!< serial wire JTAG configuration */ ++#define PCF1_CTC_REMAP(regval) (GD_BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< CTC remapping */ + + /* GPIO remap definitions */ + #define GPIO_SPI0_REMAP AFIO_PCF0_SPI0_REMAP /*!< SPI0 remapping */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_i2c.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_i2c.h index e35d4f7..92b78b4 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_i2c.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_i2c.h @@ -75,7 +75,7 @@ OF SUCH DAMAGE. - #define I2C_CTL0_SRESET BIT(15) /*!< software reset */ - - /* I2Cx_CTL1 */ --#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ -+#define I2C_CTL1_I2CCLK GD_BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ - #define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ - #define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ - #define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ + #define I2C_CTL0_SRESET BIT(15) /*!< software reset */ + + /* I2Cx_CTL1 */ +-#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ ++#define I2C_CTL1_I2CCLK GD_BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ + #define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ + #define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ + #define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ @@ -84,16 +84,16 @@ OF SUCH DAMAGE. - - /* I2Cx_SADDR0 */ - #define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ --#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ --#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -+#define I2C_SADDR0_ADDRESS GD_BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -+#define I2C_SADDR0_ADDRESS_H GD_BITS(8,9) /*!< highest two bits of a 10-bit address */ - #define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ - - /* I2Cx_SADDR1 */ - #define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ --#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ -+#define I2C_SADDR1_ADDRESS2 GD_BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ - - /* I2Cx_DATA */ --#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ -+#define I2C_DATA_TRB GD_BITS(0,7) /*!< 8-bit data register */ - - /* I2Cx_STAT0 */ - #define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ + + /* I2Cx_SADDR0 */ + #define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +-#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +-#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ ++#define I2C_SADDR0_ADDRESS GD_BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ ++#define I2C_SADDR0_ADDRESS_H GD_BITS(8,9) /*!< highest two bits of a 10-bit address */ + #define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ + + /* I2Cx_SADDR1 */ + #define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +-#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ ++#define I2C_SADDR1_ADDRESS2 GD_BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ + + /* I2Cx_DATA */ +-#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ ++#define I2C_DATA_TRB GD_BITS(0,7) /*!< 8-bit data register */ + + /* I2Cx_STAT0 */ + #define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ @@ -119,15 +119,15 @@ OF SUCH DAMAGE. - #define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ - #define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ - #define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ --#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ -+#define I2C_STAT1_PECV GD_BITS(8,15) /*!< packet error checking value */ - - /* I2Cx_CKCFG */ --#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ -+#define I2C_CKCFG_CLKC GD_BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ - #define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ - #define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ - - /* I2Cx_RT */ --#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ -+#define I2C_RT_RISETIME GD_BITS(0,5) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ - - /* I2Cx_SAMCS */ - #define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ + #define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ + #define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ + #define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +-#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ ++#define I2C_STAT1_PECV GD_BITS(8,15) /*!< packet error checking value */ + + /* I2Cx_CKCFG */ +-#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ ++#define I2C_CKCFG_CLKC GD_BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ + #define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ + #define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ + + /* I2Cx_RT */ +-#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ ++#define I2C_RT_RISETIME GD_BITS(0,5) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ + + /* I2Cx_SAMCS */ + #define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ @@ -302,7 +302,7 @@ typedef enum - #define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */ - - /* transmit I2C data */ --#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) -+#define DATA_TRANS(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) - - /* receive I2C data */ - #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) + #define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */ + + /* transmit I2C data */ +-#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) ++#define DATA_TRANS(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) + + /* receive I2C data */ + #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_pmu.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_pmu.h index a231273..c6f7154 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_pmu.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_pmu.h @@ -53,9 +53,9 @@ OF SUCH DAMAGE. - #define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ - #define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ - #define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ --#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ -+#define PMU_CTL_LVDT GD_BITS(5,7) /*!< low voltage detector threshold */ - #define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ --#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ -+#define PMU_CTL_LDOVS GD_BITS(14,15) /*!< LDO output voltage select */ - - /* PMU_CS */ - #define PMU_CS_WUF BIT(0) /*!< wakeup flag */ + #define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ + #define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ + #define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +-#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ ++#define PMU_CTL_LVDT GD_BITS(5,7) /*!< low voltage detector threshold */ + #define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ +-#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ ++#define PMU_CTL_LDOVS GD_BITS(14,15) /*!< LDO output voltage select */ + + /* PMU_CS */ + #define PMU_CS_WUF BIT(0) /*!< wakeup flag */ @@ -65,7 +65,7 @@ OF SUCH DAMAGE. - - /* constants definitions */ - /* PMU low voltage detector threshold definitions */ --#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) -+#define CTL_LVDT(regval) (GD_BITS(5,7)&((uint32_t)(regval)<<5)) - #define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ - #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ - #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ + + /* constants definitions */ + /* PMU low voltage detector threshold definitions */ +-#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) ++#define CTL_LVDT(regval) (GD_BITS(5,7)&((uint32_t)(regval)<<5)) + #define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ + #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ + #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ @@ -76,7 +76,7 @@ OF SUCH DAMAGE. - #define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ - - /* PMU LDO output voltage select definitions */ --#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) -+#define CTL_LDOVS(regval) (GD_BITS(14,15)&((uint32_t)(regval)<<14)) - #define PMU_LDOVS_NORMAL CTL_LDOVS(1) /*!< LDO output voltage select normal mode */ - #define PMU_LDOVS_LOW CTL_LDOVS(3) /*!< LDO output voltage select low mode */ - + #define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ + + /* PMU LDO output voltage select definitions */ +-#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) ++#define CTL_LDOVS(regval) (GD_BITS(14,15)&((uint32_t)(regval)<<14)) + #define PMU_LDOVS_NORMAL CTL_LDOVS(1) /*!< LDO output voltage select normal mode */ + #define PMU_LDOVS_LOW CTL_LDOVS(3) /*!< LDO output voltage select low mode */ + diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_rcu.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_rcu.h index ccca8d2..fbbcac9 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_rcu.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_rcu.h @@ -65,8 +65,8 @@ OF SUCH DAMAGE. - /* RCU_CTL */ - #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ - #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ --#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ --#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -+#define RCU_CTL_IRC8MADJ GD_BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -+#define RCU_CTL_IRC8MCALIB GD_BITS(8,15) /*!< high speed internal oscillator calibration value register */ - #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ - #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ - #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ + /* RCU_CTL */ + #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ + #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +-#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +-#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ ++#define RCU_CTL_IRC8MADJ GD_BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ ++#define RCU_CTL_IRC8MCALIB GD_BITS(8,15) /*!< high speed internal oscillator calibration value register */ + #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ + #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ + #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ @@ -79,17 +79,17 @@ OF SUCH DAMAGE. - #define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ - - /* RCU_CFG0 */ --#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ --#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ --#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ --#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ --#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ --#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ -+#define RCU_CFG0_SCS GD_BITS(0,1) /*!< system clock switch */ -+#define RCU_CFG0_SCSS GD_BITS(2,3) /*!< system clock switch status */ -+#define RCU_CFG0_AHBPSC GD_BITS(4,7) /*!< AHB prescaler selection */ -+#define RCU_CFG0_APB1PSC GD_BITS(8,10) /*!< APB1 prescaler selection */ -+#define RCU_CFG0_APB2PSC GD_BITS(11,13) /*!< APB2 prescaler selection */ -+#define RCU_CFG0_ADCPSC GD_BITS(14,15) /*!< ADC prescaler selection */ - #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ - #define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ --#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ --#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ --#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ -+#define RCU_CFG0_PLLMF GD_BITS(18,21) /*!< PLL clock multiplication factor */ -+#define RCU_CFG0_USBFSPSC GD_BITS(22,23) /*!< USBFS clock prescaler selection */ -+#define RCU_CFG0_CKOUT0SEL GD_BITS(24,27) /*!< CKOUT0 clock source selection */ - #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ - #define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ - #define RCU_CFG0_USBFSPSC_2 BIT(31) /*!< bit 2 of USBFSPSC */ + #define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ + + /* RCU_CFG0 */ +-#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +-#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +-#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +-#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +-#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +-#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ ++#define RCU_CFG0_SCS GD_BITS(0,1) /*!< system clock switch */ ++#define RCU_CFG0_SCSS GD_BITS(2,3) /*!< system clock switch status */ ++#define RCU_CFG0_AHBPSC GD_BITS(4,7) /*!< AHB prescaler selection */ ++#define RCU_CFG0_APB1PSC GD_BITS(8,10) /*!< APB1 prescaler selection */ ++#define RCU_CFG0_APB2PSC GD_BITS(11,13) /*!< APB2 prescaler selection */ ++#define RCU_CFG0_ADCPSC GD_BITS(14,15) /*!< ADC prescaler selection */ + #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ + #define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ +-#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +-#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ +-#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ ++#define RCU_CFG0_PLLMF GD_BITS(18,21) /*!< PLL clock multiplication factor */ ++#define RCU_CFG0_USBFSPSC GD_BITS(22,23) /*!< USBFS clock prescaler selection */ ++#define RCU_CFG0_CKOUT0SEL GD_BITS(24,27) /*!< CKOUT0 clock source selection */ + #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ + #define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ + #define RCU_CFG0_USBFSPSC_2 BIT(31) /*!< bit 2 of USBFSPSC */ @@ -217,8 +217,8 @@ OF SUCH DAMAGE. - #define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ - #define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ - #define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ --#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ --#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ -+#define RCU_BDCTL_LXTALDRI GD_BITS(3,4) /*!< LXTAL drive capability */ -+#define RCU_BDCTL_RTCSRC GD_BITS(8,9) /*!< RTC clock entry selection */ - #define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ - #define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ - + #define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ + #define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ + #define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +-#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ +-#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ ++#define RCU_BDCTL_LXTALDRI GD_BITS(3,4) /*!< LXTAL drive capability */ ++#define RCU_BDCTL_RTCSRC GD_BITS(8,9) /*!< RTC clock entry selection */ + #define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ + #define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + @@ -237,10 +237,10 @@ OF SUCH DAMAGE. - #define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ - - /* RCU_CFG1 */ --#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ --#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ --#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ --#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ -+#define RCU_CFG1_PREDV0 GD_BITS(0,3) /*!< PREDV0 division factor */ -+#define RCU_CFG1_PREDV1 GD_BITS(4,7) /*!< PREDV1 division factor */ -+#define RCU_CFG1_PLL1MF GD_BITS(8,11) /*!< PLL1 clock multiplication factor */ -+#define RCU_CFG1_PLL2MF GD_BITS(12,15) /*!< PLL2 clock multiplication factor */ - #define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ - #define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ - #define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ + #define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ + + /* RCU_CFG1 */ +-#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ +-#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ +-#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ +-#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ ++#define RCU_CFG1_PREDV0 GD_BITS(0,3) /*!< PREDV0 division factor */ ++#define RCU_CFG1_PREDV1 GD_BITS(4,7) /*!< PREDV1 division factor */ ++#define RCU_CFG1_PLL1MF GD_BITS(8,11) /*!< PLL1 clock multiplication factor */ ++#define RCU_CFG1_PLL2MF GD_BITS(12,15) /*!< PLL2 clock multiplication factor */ + #define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ + #define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ + #define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ @@ -248,13 +248,13 @@ OF SUCH DAMAGE. - #define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ - - /* RCU_DSV */ --#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ -+#define RCU_DSV_DSLPVS GD_BITS(0,1) /*!< deep-sleep mode voltage select */ - - /* RCU_ADDCTL */ - #define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */ - #define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ - #define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ --#define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ -+#define RCU_ADDCTL_IRC48MCAL GD_BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ - - /* RCU_ADDINT */ - #define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ + #define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ + + /* RCU_DSV */ +-#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ ++#define RCU_DSV_DSLPVS GD_BITS(0,1) /*!< deep-sleep mode voltage select */ + + /* RCU_ADDCTL */ + #define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */ + #define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ + #define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ +-#define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ ++#define RCU_ADDCTL_IRC48MCAL GD_BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ + + /* RCU_ADDINT */ + #define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ @@ -507,19 +507,19 @@ typedef enum - - /* RCU_CFG0 register bit define */ - /* system clock source select */ --#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -+#define CFG0_SCS(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) - #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ - #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ - #define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ - - /* system clock source select status */ --#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -+#define CFG0_SCSS(regval) (GD_BITS(2,3) & ((uint32_t)(regval) << 2)) - #define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ - #define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ - #define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ - - /* AHB prescaler selection */ --#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -+#define CFG0_AHBPSC(regval) (GD_BITS(4,7) & ((uint32_t)(regval) << 4)) - #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ - #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ - #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ + + /* RCU_CFG0 register bit define */ + /* system clock source select */ +-#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) ++#define CFG0_SCS(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) + #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ + #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ + #define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ + + /* system clock source select status */ +-#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) ++#define CFG0_SCSS(regval) (GD_BITS(2,3) & ((uint32_t)(regval) << 2)) + #define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ + #define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ + #define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ + + /* AHB prescaler selection */ +-#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) ++#define CFG0_AHBPSC(regval) (GD_BITS(4,7) & ((uint32_t)(regval) << 4)) + #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ + #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ + #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ @@ -531,7 +531,7 @@ typedef enum - #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ - - /* APB1 prescaler selection */ --#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) -+#define CFG0_APB1PSC(regval) (GD_BITS(8,10) & ((uint32_t)(regval) << 8)) - #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ - #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ - #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ + #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + + /* APB1 prescaler selection */ +-#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) ++#define CFG0_APB1PSC(regval) (GD_BITS(8,10) & ((uint32_t)(regval) << 8)) + #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ + #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ + #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ @@ -539,7 +539,7 @@ typedef enum - #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ - - /* APB2 prescaler selection */ --#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) -+#define CFG0_APB2PSC(regval) (GD_BITS(11,13) & ((uint32_t)(regval) << 11)) - #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ - #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ - #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ + #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + + /* APB2 prescaler selection */ +-#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) ++#define CFG0_APB2PSC(regval) (GD_BITS(11,13) & ((uint32_t)(regval) << 11)) + #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ + #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ + #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ @@ -565,7 +565,7 @@ typedef enum - /* PLL clock multiplication factor */ - #define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ - --#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) -+#define CFG0_PLLMF(regval) (GD_BITS(18,21) & ((uint32_t)(regval) << 18)) - #define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ - #define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ - #define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ + /* PLL clock multiplication factor */ + #define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ + +-#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) ++#define CFG0_PLLMF(regval) (GD_BITS(18,21) & ((uint32_t)(regval) << 18)) + #define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ + #define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ + #define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ @@ -600,7 +600,7 @@ typedef enum - #define USBPSC_2 RCU_CFG0_USBFSPSC_2 - - /* USBD/USBFS prescaler select */ --#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) -+#define CFG0_USBPSC(regval) (GD_BITS(22,23) & ((uint32_t)(regval) << 22)) - #define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBFS prescaler select CK_PLL/1.5 */ - #define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBFS prescaler select CK_PLL/1 */ - #define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBFS prescaler select CK_PLL/2.5 */ + #define USBPSC_2 RCU_CFG0_USBFSPSC_2 + + /* USBD/USBFS prescaler select */ +-#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) ++#define CFG0_USBPSC(regval) (GD_BITS(22,23) & ((uint32_t)(regval) << 22)) + #define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBFS prescaler select CK_PLL/1.5 */ + #define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBFS prescaler select CK_PLL/1 */ + #define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBFS prescaler select CK_PLL/2.5 */ @@ -610,7 +610,7 @@ typedef enum - #define RCU_CKUSB_CKPLL_DIV4 (USBPSC_2 |CFG0_USBPSC(2)) /*!< USBFS prescaler select CK_PLL/4 */ - - /* CKOUT0 Clock source selection */ --#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -+#define CFG0_CKOUT0SEL(regval) (GD_BITS(24,27) & ((uint32_t)(regval) << 24)) - #define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ - #define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ - #define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ + #define RCU_CKUSB_CKPLL_DIV4 (USBPSC_2 |CFG0_USBPSC(2)) /*!< USBFS prescaler select CK_PLL/4 */ + + /* CKOUT0 Clock source selection */ +-#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) ++#define CFG0_CKOUT0SEL(regval) (GD_BITS(24,27) & ((uint32_t)(regval) << 24)) + #define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ + #define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ + #define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ @@ -623,21 +623,21 @@ typedef enum - #define RCU_CKOUT0SRC_IRC48M_DIV8 CFG0_CKOUT0SEL(13) /*!< IRC48M/8 clock selected */ - - /* LXTAL drive capability */ --#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) -+#define BDCTL_LXTALDRI(regval) (GD_BITS(3,4) & ((uint32_t)(regval) << 3)) - #define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ - #define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ - #define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ - #define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ - - /* RTC clock entry selection */ --#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -+#define BDCTL_RTCSRC(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) - #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ - #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ - #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ - #define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ - - /* PREDV0 division factor */ --#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -+#define CFG1_PREDV0(regval) (GD_BITS(0,3) & ((uint32_t)(regval) << 0)) - #define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ - #define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ - #define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ + #define RCU_CKOUT0SRC_IRC48M_DIV8 CFG0_CKOUT0SEL(13) /*!< IRC48M/8 clock selected */ + + /* LXTAL drive capability */ +-#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) ++#define BDCTL_LXTALDRI(regval) (GD_BITS(3,4) & ((uint32_t)(regval) << 3)) + #define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ + #define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ + #define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ + #define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ + + /* RTC clock entry selection */ +-#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) ++#define BDCTL_RTCSRC(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) + #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ + #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ + #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ + #define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ + + /* PREDV0 division factor */ +-#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) ++#define CFG1_PREDV0(regval) (GD_BITS(0,3) & ((uint32_t)(regval) << 0)) + #define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ + #define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ + #define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ @@ -656,7 +656,7 @@ typedef enum - #define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ - - /* PREDV1 division factor */ --#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -+#define CFG1_PREDV1(regval) (GD_BITS(4,7) & ((uint32_t)(regval) << 4)) - #define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ - #define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ - #define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ + #define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ + + /* PREDV1 division factor */ +-#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) ++#define CFG1_PREDV1(regval) (GD_BITS(4,7) & ((uint32_t)(regval) << 4)) + #define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ + #define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ + #define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ @@ -675,7 +675,7 @@ typedef enum - #define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ - - /* PLL1 clock multiplication factor */ --#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -+#define CFG1_PLL1MF(regval) (GD_BITS(8,11) & ((uint32_t)(regval) << 8)) - #define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ - #define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ - #define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ + #define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ + + /* PLL1 clock multiplication factor */ +-#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) ++#define CFG1_PLL1MF(regval) (GD_BITS(8,11) & ((uint32_t)(regval) << 8)) + #define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ + #define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ + #define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ @@ -687,7 +687,7 @@ typedef enum - #define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ - - /* PLL2 clock multiplication factor */ --#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) -+#define CFG1_PLL2MF(regval) (GD_BITS(12,15) & ((uint32_t)(regval) << 12)) - #define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ - #define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ - #define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ + #define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ + + /* PLL2 clock multiplication factor */ +-#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) ++#define CFG1_PLL2MF(regval) (GD_BITS(12,15) & ((uint32_t)(regval) << 12)) + #define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ + #define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ + #define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ @@ -715,7 +715,7 @@ typedef enum - #define RCU_PLLPRESRC_IRC48M RCU_CFG1_PLLPRESEL /*!< CK_PLL selected as PREDV0 input source clock */ - - /* deep-sleep mode voltage */ --#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -+#define DSV_DSLPVS(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) - #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ - #define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ - #define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ + #define RCU_PLLPRESRC_IRC48M RCU_CFG1_PLLPRESEL /*!< CK_PLL selected as PREDV0 input source clock */ + + /* deep-sleep mode voltage */ +-#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) ++#define DSV_DSLPVS(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) + #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ + #define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ + #define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_rtc.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_rtc.h index 4516e62..d634e22 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_rtc.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_rtc.h @@ -69,28 +69,28 @@ OF SUCH DAMAGE. - #define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ - - /* RTC_PSCH */ --#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */ -+#define RTC_PSCH_PSC GD_BITS(0,3) /*!< prescaler high value */ - - /* RTC_PSCL */ --#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */ -+#define RTC_PSCL_PSC GD_BITS(0,15) /*!< prescaler low value */ - - /* RTC_DIVH */ --#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */ -+#define RTC_DIVH_DIV GD_BITS(0,3) /*!< divider high value */ - - /* RTC_DIVL */ --#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */ -+#define RTC_DIVL_DIV GD_BITS(0,15) /*!< divider low value */ - - /* RTC_CNTH */ --#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */ -+#define RTC_CNTH_CNT GD_BITS(0,15) /*!< counter high value */ - - /* RTC_CNTL */ --#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */ -+#define RTC_CNTL_CNT GD_BITS(0,15) /*!< counter low value */ - - /* RTC_ALRMH */ --#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */ -+#define RTC_ALRMH_ALRM GD_BITS(0,15) /*!< alarm high value */ - - /* RTC_ALRML */ --#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */ -+#define RTC_ALRML_ALRM GD_BITS(0,15) /*!< alarm low value */ - - /* constants definitions */ - /* RTC interrupt enable or disable definitions */ + #define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ + + /* RTC_PSCH */ +-#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */ ++#define RTC_PSCH_PSC GD_BITS(0,3) /*!< prescaler high value */ + + /* RTC_PSCL */ +-#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */ ++#define RTC_PSCL_PSC GD_BITS(0,15) /*!< prescaler low value */ + + /* RTC_DIVH */ +-#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */ ++#define RTC_DIVH_DIV GD_BITS(0,3) /*!< divider high value */ + + /* RTC_DIVL */ +-#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */ ++#define RTC_DIVL_DIV GD_BITS(0,15) /*!< divider low value */ + + /* RTC_CNTH */ +-#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */ ++#define RTC_CNTH_CNT GD_BITS(0,15) /*!< counter high value */ + + /* RTC_CNTL */ +-#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */ ++#define RTC_CNTL_CNT GD_BITS(0,15) /*!< counter low value */ + + /* RTC_ALRMH */ +-#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */ ++#define RTC_ALRMH_ALRM GD_BITS(0,15) /*!< alarm high value */ + + /* RTC_ALRML */ +-#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */ ++#define RTC_ALRML_ALRM GD_BITS(0,15) /*!< alarm low value */ + + /* constants definitions */ + /* RTC interrupt enable or disable definitions */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_spi.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_spi.h index eb6cb55..0e61c70 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_spi.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_spi.h @@ -61,7 +61,7 @@ OF SUCH DAMAGE. - #define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ - #define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ - #define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ --#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ -+#define SPI_CTL0_PSC GD_BITS(3,5) /*!< master clock prescaler selection */ - #define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ - #define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ - #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ + #define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ + #define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ + #define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +-#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ ++#define SPI_CTL0_PSC GD_BITS(3,5) /*!< master clock prescaler selection */ + #define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ + #define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ + #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ @@ -95,29 +95,29 @@ OF SUCH DAMAGE. - #define SPI_STAT_FERR BIT(8) /*!< format error bit */ - - /* SPI_DATA */ --#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ -+#define SPI_DATA_DATA GD_BITS(0,15) /*!< data transfer register */ - - /* SPI_CRCPOLY */ --#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ -+#define SPI_CRCPOLY_CRCPOLY GD_BITS(0,15) /*!< CRC polynomial value */ - - /* SPI_RCRC */ --#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ -+#define SPI_RCRC_RCRC GD_BITS(0,15) /*!< RX CRC value */ - - /* SPI_TCRC */ --#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ -+#define SPI_TCRC_TCRC GD_BITS(0,15) /*!< TX CRC value */ - - /* SPI_I2SCTL */ - #define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ --#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ -+#define SPI_I2SCTL_DTLEN GD_BITS(1,2) /*!< data length */ - #define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ --#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ -+#define SPI_I2SCTL_I2SSTD GD_BITS(4,5) /*!< I2S standard selection */ - #define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ --#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ -+#define SPI_I2SCTL_I2SOPMOD GD_BITS(8,9) /*!< I2S operation mode */ - #define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ - #define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ - - /* SPI_I2SPSC */ --#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ -+#define SPI_I2SPSC_DIV GD_BITS(0,7) /*!< dividing factor for the prescaler */ - #define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ - #define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ - + #define SPI_STAT_FERR BIT(8) /*!< format error bit */ + + /* SPI_DATA */ +-#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ ++#define SPI_DATA_DATA GD_BITS(0,15) /*!< data transfer register */ + + /* SPI_CRCPOLY */ +-#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ ++#define SPI_CRCPOLY_CRCPOLY GD_BITS(0,15) /*!< CRC polynomial value */ + + /* SPI_RCRC */ +-#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ ++#define SPI_RCRC_RCRC GD_BITS(0,15) /*!< RX CRC value */ + + /* SPI_TCRC */ +-#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ ++#define SPI_TCRC_TCRC GD_BITS(0,15) /*!< TX CRC value */ + + /* SPI_I2SCTL */ + #define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +-#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ ++#define SPI_I2SCTL_DTLEN GD_BITS(1,2) /*!< data length */ + #define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +-#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ ++#define SPI_I2SCTL_I2SSTD GD_BITS(4,5) /*!< I2S standard selection */ + #define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +-#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ ++#define SPI_I2SCTL_I2SOPMOD GD_BITS(8,9) /*!< I2S operation mode */ + #define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ + #define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + + /* SPI_I2SPSC */ +-#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ ++#define SPI_I2SPSC_DIV GD_BITS(0,7) /*!< dividing factor for the prescaler */ + #define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ + #define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + @@ -172,7 +172,7 @@ typedef struct - #define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ - - /* SPI clock prescale factor */ --#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -+#define CTL0_PSC(regval) (GD_BITS(3,5) & ((uint32_t)(regval) << 3)) - #define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ - #define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ - #define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ + #define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + + /* SPI clock prescale factor */ +-#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) ++#define CTL0_PSC(regval) (GD_BITS(3,5) & ((uint32_t)(regval) << 3)) + #define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ + #define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ + #define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ @@ -194,7 +194,7 @@ typedef struct - #define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ - - /* I2S frame format */ --#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) -+#define I2SCTL_DTLEN(regval) (GD_BITS(1,2) & ((uint32_t)(regval) << 1)) - #define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ - #define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ - #define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ + #define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + + /* I2S frame format */ +-#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) ++#define I2SCTL_DTLEN(regval) (GD_BITS(1,2) & ((uint32_t)(regval) << 1)) + #define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ + #define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ + #define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ @@ -205,14 +205,14 @@ typedef struct - #define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ - - /* I2S operation mode */ --#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -+#define I2SCTL_I2SOPMOD(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) - #define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ - #define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ - #define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ - #define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ - - /* I2S standard */ --#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -+#define I2SCTL_I2SSTD(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) - #define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ - #define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ - #define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ + #define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + + /* I2S operation mode */ +-#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) ++#define I2SCTL_I2SOPMOD(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) + #define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ + #define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ + #define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ + #define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + + /* I2S standard */ +-#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) ++#define I2SCTL_I2SSTD(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) + #define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ + #define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ + #define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_timer.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_timer.h index d61efbb..c89d182 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_timer.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_timer.h @@ -85,15 +85,15 @@ OF SUCH DAMAGE. - #define TIMER_CTL0_UPS BIT(2) /*!< update source */ - #define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ - #define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ --#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ -+#define TIMER_CTL0_CAM GD_BITS(5,6) /*!< center-aligned mode selection */ - #define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ --#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ -+#define TIMER_CTL0_CKDIV GD_BITS(8,9) /*!< clock division */ - - /* TIMER_CTL1 */ - #define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ - #define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ - #define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ --#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ -+#define TIMER_CTL1_MMC GD_BITS(4,6) /*!< master mode control */ - #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ - #define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ - #define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ + #define TIMER_CTL0_UPS BIT(2) /*!< update source */ + #define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ + #define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +-#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ ++#define TIMER_CTL0_CAM GD_BITS(5,6) /*!< center-aligned mode selection */ + #define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +-#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ ++#define TIMER_CTL0_CKDIV GD_BITS(8,9) /*!< clock division */ + + /* TIMER_CTL1 */ + #define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ + #define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ + #define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +-#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ ++#define TIMER_CTL1_MMC GD_BITS(4,6) /*!< master mode control */ + #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ + #define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ + #define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ @@ -104,11 +104,11 @@ OF SUCH DAMAGE. - #define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ - - /* TIMER_SMCFG */ --#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ --#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ -+#define TIMER_SMCFG_SMC GD_BITS(0,2) /*!< slave mode control */ -+#define TIMER_SMCFG_TRGS GD_BITS(4,6) /*!< trigger selection */ - #define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ --#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ --#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ -+#define TIMER_SMCFG_ETFC GD_BITS(8,11) /*!< external trigger filter control */ -+#define TIMER_SMCFG_ETPSC GD_BITS(12,13) /*!< external trigger prescaler */ - #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ - #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - + #define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ + + /* TIMER_SMCFG */ +-#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +-#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ ++#define TIMER_SMCFG_SMC GD_BITS(0,2) /*!< slave mode control */ ++#define TIMER_SMCFG_TRGS GD_BITS(4,6) /*!< trigger selection */ + #define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +-#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +-#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ ++#define TIMER_SMCFG_ETFC GD_BITS(8,11) /*!< external trigger filter control */ ++#define TIMER_SMCFG_ETPSC GD_BITS(12,13) /*!< external trigger prescaler */ + #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ + #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ + @@ -155,39 +155,39 @@ OF SUCH DAMAGE. - - /* TIMER_CHCTL0 */ - /* output compare mode */ --#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ -+#define TIMER_CHCTL0_CH0MS GD_BITS(0,1) /*!< channel 0 mode selection */ - #define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ - #define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ --#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ -+#define TIMER_CHCTL0_CH0COMCTL GD_BITS(4,6) /*!< channel 0 output compare control */ - #define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ --#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ -+#define TIMER_CHCTL0_CH1MS GD_BITS(8,9) /*!< channel 1 mode selection */ - #define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ - #define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ --#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ -+#define TIMER_CHCTL0_CH1COMCTL GD_BITS(12,14) /*!< channel 1 output compare control */ - #define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ - /* input capture mode */ --#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ --#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ --#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ --#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ -+#define TIMER_CHCTL0_CH0CAPPSC GD_BITS(2,3) /*!< channel 0 input capture prescaler */ -+#define TIMER_CHCTL0_CH0CAPFLT GD_BITS(4,7) /*!< channel 0 input capture filter control */ -+#define TIMER_CHCTL0_CH1CAPPSC GD_BITS(10,11) /*!< channel 1 input capture prescaler */ -+#define TIMER_CHCTL0_CH1CAPFLT GD_BITS(12,15) /*!< channel 1 input capture filter control */ - - /* TIMER_CHCTL1 */ - /* output compare mode */ --#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ -+#define TIMER_CHCTL1_CH2MS GD_BITS(0,1) /*!< channel 2 mode selection */ - #define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ - #define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ --#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ -+#define TIMER_CHCTL1_CH2COMCTL GD_BITS(4,6) /*!< channel 2 output compare control */ - #define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ --#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ -+#define TIMER_CHCTL1_CH3MS GD_BITS(8,9) /*!< channel 3 mode selection */ - #define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ - #define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ --#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ -+#define TIMER_CHCTL1_CH3COMCTL GD_BITS(12,14) /*!< channel 3 output compare control */ - #define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ - /* input capture mode */ --#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ --#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ --#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ --#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ -+#define TIMER_CHCTL1_CH2CAPPSC GD_BITS(2,3) /*!< channel 2 input capture prescaler */ -+#define TIMER_CHCTL1_CH2CAPFLT GD_BITS(4,7) /*!< channel 2 input capture filter control */ -+#define TIMER_CHCTL1_CH3CAPPSC GD_BITS(10,11) /*!< channel 3 input capture prescaler */ -+#define TIMER_CHCTL1_CH3CAPFLT GD_BITS(12,15) /*!< channel 3 input capture filter control */ - - /* TIMER_CHCTL2 */ - #define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ + + /* TIMER_CHCTL0 */ + /* output compare mode */ +-#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ ++#define TIMER_CHCTL0_CH0MS GD_BITS(0,1) /*!< channel 0 mode selection */ + #define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ + #define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +-#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ ++#define TIMER_CHCTL0_CH0COMCTL GD_BITS(4,6) /*!< channel 0 output compare control */ + #define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +-#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ ++#define TIMER_CHCTL0_CH1MS GD_BITS(8,9) /*!< channel 1 mode selection */ + #define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ + #define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +-#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ ++#define TIMER_CHCTL0_CH1COMCTL GD_BITS(12,14) /*!< channel 1 output compare control */ + #define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ + /* input capture mode */ +-#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +-#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +-#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +-#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ ++#define TIMER_CHCTL0_CH0CAPPSC GD_BITS(2,3) /*!< channel 0 input capture prescaler */ ++#define TIMER_CHCTL0_CH0CAPFLT GD_BITS(4,7) /*!< channel 0 input capture filter control */ ++#define TIMER_CHCTL0_CH1CAPPSC GD_BITS(10,11) /*!< channel 1 input capture prescaler */ ++#define TIMER_CHCTL0_CH1CAPFLT GD_BITS(12,15) /*!< channel 1 input capture filter control */ + + /* TIMER_CHCTL1 */ + /* output compare mode */ +-#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ ++#define TIMER_CHCTL1_CH2MS GD_BITS(0,1) /*!< channel 2 mode selection */ + #define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ + #define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +-#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ ++#define TIMER_CHCTL1_CH2COMCTL GD_BITS(4,6) /*!< channel 2 output compare control */ + #define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +-#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ ++#define TIMER_CHCTL1_CH3MS GD_BITS(8,9) /*!< channel 3 mode selection */ + #define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ + #define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +-#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ ++#define TIMER_CHCTL1_CH3COMCTL GD_BITS(12,14) /*!< channel 3 output compare control */ + #define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ + /* input capture mode */ +-#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +-#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +-#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +-#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ ++#define TIMER_CHCTL1_CH2CAPPSC GD_BITS(2,3) /*!< channel 2 input capture prescaler */ ++#define TIMER_CHCTL1_CH2CAPFLT GD_BITS(4,7) /*!< channel 2 input capture filter control */ ++#define TIMER_CHCTL1_CH3CAPPSC GD_BITS(10,11) /*!< channel 3 input capture prescaler */ ++#define TIMER_CHCTL1_CH3CAPFLT GD_BITS(12,15) /*!< channel 3 input capture filter control */ + + /* TIMER_CHCTL2 */ + #define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ @@ -206,32 +206,32 @@ OF SUCH DAMAGE. - #define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ - - /* TIMER_CNT */ --#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ -+#define TIMER_CNT_CNT GD_BITS(0,15) /*!< 16 bit timer counter */ - - /* TIMER_PSC */ --#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ -+#define TIMER_PSC_PSC GD_BITS(0,15) /*!< prescaler value of the counter clock */ - - /* TIMER_CAR */ --#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ -+#define TIMER_CAR_CARL GD_BITS(0,15) /*!< 16 bit counter auto reload value */ - - /* TIMER_CREP */ --#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ -+#define TIMER_CREP_CREP GD_BITS(0,7) /*!< counter repetition value */ - - /* TIMER_CH0CV */ --#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ -+#define TIMER_CH0CV_CH0VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ - - /* TIMER_CH1CV */ --#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ -+#define TIMER_CH1CV_CH1VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ - - /* TIMER_CH2CV */ --#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ -+#define TIMER_CH2CV_CH2VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ - - /* TIMER_CH3CV */ --#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ -+#define TIMER_CH3CV_CH3VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ - - /* TIMER_CCHP */ --#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ --#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ -+#define TIMER_CCHP_DTCFG GD_BITS(0,7) /*!< dead time configure */ -+#define TIMER_CCHP_PROT GD_BITS(8,9) /*!< complementary register protect control */ - #define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ - #define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ - #define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ + #define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ + + /* TIMER_CNT */ +-#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ ++#define TIMER_CNT_CNT GD_BITS(0,15) /*!< 16 bit timer counter */ + + /* TIMER_PSC */ +-#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ ++#define TIMER_PSC_PSC GD_BITS(0,15) /*!< prescaler value of the counter clock */ + + /* TIMER_CAR */ +-#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ ++#define TIMER_CAR_CARL GD_BITS(0,15) /*!< 16 bit counter auto reload value */ + + /* TIMER_CREP */ +-#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ ++#define TIMER_CREP_CREP GD_BITS(0,7) /*!< counter repetition value */ + + /* TIMER_CH0CV */ +-#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ ++#define TIMER_CH0CV_CH0VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ + + /* TIMER_CH1CV */ +-#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ ++#define TIMER_CH1CV_CH1VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ + + /* TIMER_CH2CV */ +-#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ ++#define TIMER_CH2CV_CH2VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ + + /* TIMER_CH3CV */ +-#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ ++#define TIMER_CH3CV_CH3VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ + + /* TIMER_CCHP */ +-#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +-#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ ++#define TIMER_CCHP_DTCFG GD_BITS(0,7) /*!< dead time configure */ ++#define TIMER_CCHP_PROT GD_BITS(8,9) /*!< complementary register protect control */ + #define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ + #define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ + #define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ @@ -240,11 +240,11 @@ OF SUCH DAMAGE. - #define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ - - /* TIMER_DMACFG */ --#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ --#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ -+#define TIMER_DMACFG_DMATA GD_BITS(0,4) /*!< DMA transfer access start address */ -+#define TIMER_DMACFG_DMATC GD_BITS(8,12) /*!< DMA transfer count */ - - /* TIMER_DMATB */ --#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ -+#define TIMER_DMATB_DMATB GD_BITS(0,15) /*!< DMA transfer buffer address */ - - /* TIMER_CFG */ - #define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ + #define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + + /* TIMER_DMACFG */ +-#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ +-#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ ++#define TIMER_DMACFG_DMATA GD_BITS(0,4) /*!< DMA transfer access start address */ ++#define TIMER_DMACFG_DMATC GD_BITS(8,12) /*!< DMA transfer count */ + + /* TIMER_DMATB */ +-#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ ++#define TIMER_DMATB_DMATB GD_BITS(0,15) /*!< DMA transfer buffer address */ + + /* TIMER_CFG */ + #define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ @@ -342,7 +342,7 @@ typedef struct - #define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ - - /* DMA access base address */ --#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) -+#define DMACFG_DMATA(regval) (GD_BITS(0, 4) & ((uint32_t)(regval) << 0U)) - #define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ - #define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ - #define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ + #define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ + + /* DMA access base address */ +-#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) ++#define DMACFG_DMATA(regval) (GD_BITS(0, 4) & ((uint32_t)(regval) << 0U)) + #define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ + #define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ + #define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ @@ -364,7 +364,7 @@ typedef struct - #define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ - - /* DMA access burst length */ --#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) -+#define DMACFG_DMATC(regval) (GD_BITS(8, 12) & ((uint32_t)(regval) << 8U)) - #define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ - #define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ - #define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ + #define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ + + /* DMA access burst length */ +-#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) ++#define DMACFG_DMATC(regval) (GD_BITS(8, 12) & ((uint32_t)(regval) << 8U)) + #define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ + #define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ + #define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ @@ -395,7 +395,7 @@ typedef struct - #define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ - - /* center-aligned mode selection */ --#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) -+#define CTL0_CAM(regval) ((uint16_t)(GD_BITS(5, 6) & ((uint32_t)(regval) << 5U))) - #define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ - #define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ - #define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ + #define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ + + /* center-aligned mode selection */ +-#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) ++#define CTL0_CAM(regval) ((uint16_t)(GD_BITS(5, 6) & ((uint32_t)(regval) << 5U))) + #define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ + #define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ + #define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ @@ -410,7 +410,7 @@ typedef struct - #define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ - - /* specify division ratio between TIMER clock and dead-time and sampling clock */ --#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -+#define CTL0_CKDIV(regval) ((uint16_t)(GD_BITS(8, 9) & ((uint32_t)(regval) << 8U))) - #define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ - #define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ - #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ + #define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ + + /* specify division ratio between TIMER clock and dead-time and sampling clock */ +-#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) ++#define CTL0_CKDIV(regval) ((uint16_t)(GD_BITS(8, 9) & ((uint32_t)(regval) << 8U))) + #define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ + #define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ + #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ @@ -441,7 +441,7 @@ typedef struct - #define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ - - /* complementary register protect control */ --#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -+#define CCHP_PROT(regval) ((uint16_t)(GD_BITS(8, 9) & ((uint32_t)(regval) << 8U))) - #define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ - #define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ - #define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ + #define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ + + /* complementary register protect control */ +-#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) ++#define CCHP_PROT(regval) ((uint16_t)(GD_BITS(8, 9) & ((uint32_t)(regval) << 8U))) + #define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ + #define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ + #define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ @@ -524,7 +524,7 @@ typedef struct - #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ - - /* trigger selection */ --#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -+#define SMCFG_TRGSEL(regval) (GD_BITS(4, 6) & ((uint32_t)(regval) << 4U)) - #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ - #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ - #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ + #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + + /* trigger selection */ +-#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) ++#define SMCFG_TRGSEL(regval) (GD_BITS(4, 6) & ((uint32_t)(regval) << 4U)) + #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ + #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ + #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ @@ -535,7 +535,7 @@ typedef struct - #define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */ - - /* master mode control */ --#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -+#define CTL1_MMC(regval) (GD_BITS(4, 6) & ((uint32_t)(regval) << 4U)) - #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ - #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ - #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ + #define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */ + + /* master mode control */ +-#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) ++#define CTL1_MMC(regval) (GD_BITS(4, 6) & ((uint32_t)(regval) << 4U)) + #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ + #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ + #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ @@ -546,7 +546,7 @@ typedef struct - #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ - - /* slave mode control */ --#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) -+#define SMCFG_SMC(regval) (GD_BITS(0, 2) & ((uint32_t)(regval) << 0U)) - #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ - #define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ - #define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ + #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + + /* slave mode control */ +-#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) ++#define SMCFG_SMC(regval) (GD_BITS(0, 2) & ((uint32_t)(regval) << 0U)) + #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ + #define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ + #define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ @@ -561,7 +561,7 @@ typedef struct - #define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ - - /* external trigger prescaler */ --#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) -+#define SMCFG_ETPSC(regval) (GD_BITS(12, 13) & ((uint32_t)(regval) << 12U)) - #define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ - #define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ - #define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ + #define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ + + /* external trigger prescaler */ +-#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) ++#define SMCFG_ETPSC(regval) (GD_BITS(12, 13) & ((uint32_t)(regval) << 12U)) + #define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ + #define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ + #define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_usart.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_usart.h index ef236ed..e3fd80d --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_usart.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_usart.h @@ -73,11 +73,11 @@ OF SUCH DAMAGE. - #define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ - - /* USARTx_DATA */ --#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ -+#define USART_DATA_DATA GD_BITS(0,8) /*!< transmit or read data value */ - - /* USARTx_BAUD */ --#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ --#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ -+#define USART_BAUD_FRADIV GD_BITS(0,3) /*!< fraction part of baud-rate divider */ -+#define USART_BAUD_INTDIV GD_BITS(4,15) /*!< integer part of baud-rate divider */ - - /* USARTx_CTL0 */ - #define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ + #define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ + + /* USARTx_DATA */ +-#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ ++#define USART_DATA_DATA GD_BITS(0,8) /*!< transmit or read data value */ + + /* USARTx_BAUD */ +-#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +-#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ ++#define USART_BAUD_FRADIV GD_BITS(0,3) /*!< fraction part of baud-rate divider */ ++#define USART_BAUD_INTDIV GD_BITS(4,15) /*!< integer part of baud-rate divider */ + + /* USARTx_CTL0 */ + #define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ @@ -96,14 +96,14 @@ OF SUCH DAMAGE. - #define USART_CTL0_UEN BIT(13) /*!< USART enable */ - - /* USARTx_CTL1 */ --#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ -+#define USART_CTL1_ADDR GD_BITS(0,3) /*!< address of USART */ - #define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ - #define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ - #define USART_CTL1_CLEN BIT(8) /*!< CK length */ - #define USART_CTL1_CPH BIT(9) /*!< CK phase */ - #define USART_CTL1_CPL BIT(10) /*!< CK polarity */ - #define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ --#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ -+#define USART_CTL1_STB GD_BITS(12,13) /*!< STOP bits length */ - #define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ - - /* USARTx_CTL2 */ + #define USART_CTL0_UEN BIT(13) /*!< USART enable */ + + /* USARTx_CTL1 */ +-#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ ++#define USART_CTL1_ADDR GD_BITS(0,3) /*!< address of USART */ + #define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ + #define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ + #define USART_CTL1_CLEN BIT(8) /*!< CK length */ + #define USART_CTL1_CPH BIT(9) /*!< CK phase */ + #define USART_CTL1_CPL BIT(10) /*!< CK polarity */ + #define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ +-#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ ++#define USART_CTL1_STB GD_BITS(12,13) /*!< STOP bits length */ + #define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ + + /* USARTx_CTL2 */ @@ -120,12 +120,12 @@ OF SUCH DAMAGE. - #define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ - - /* USARTx_GP */ --#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ --#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ -+#define USART_GP_PSC GD_BITS(0,7) /*!< prescaler value for dividing the system clock */ -+#define USART_GP_GUAT GD_BITS(8,15) /*!< guard time value in smartcard mode */ - - /* USARTx_CTL3 */ - #define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ --#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ -+#define USART_CTL3_SCRTNUM GD_BITS(1,3) /*!< smartcard auto-retry number */ - #define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ - #define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ - #define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ + #define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ + + /* USARTx_GP */ +-#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +-#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ ++#define USART_GP_PSC GD_BITS(0,7) /*!< prescaler value for dividing the system clock */ ++#define USART_GP_GUAT GD_BITS(8,15) /*!< guard time value in smartcard mode */ + + /* USARTx_CTL3 */ + #define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ +-#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ ++#define USART_CTL3_SCRTNUM GD_BITS(1,3) /*!< smartcard auto-retry number */ + #define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ + #define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ + #define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ @@ -134,8 +134,8 @@ OF SUCH DAMAGE. - #define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ - - /* USARTx_RT */ --#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ --#define USART_RT_BL BITS(24,31) /*!< block length */ -+#define USART_RT_RT GD_BITS(0,23) /*!< receiver timeout threshold */ -+#define USART_RT_BL GD_BITS(24,31) /*!< block length */ - - /* USARTx_STAT1 */ - #define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ + #define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ + + /* USARTx_RT */ +-#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ +-#define USART_RT_BL BITS(24,31) /*!< block length */ ++#define USART_RT_RT GD_BITS(0,23) /*!< receiver timeout threshold */ ++#define USART_RT_BL GD_BITS(24,31) /*!< block length */ + + /* USARTx_STAT1 */ + #define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ @@ -253,7 +253,7 @@ typedef enum - #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ - - /* USART parity bits definitions */ --#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -+#define CTL0_PM(regval) (GD_BITS(9,10) & ((uint32_t)(regval) << 9)) - #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ - #define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ - #define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + + /* USART parity bits definitions */ +-#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) ++#define CTL0_PM(regval) (GD_BITS(9,10) & ((uint32_t)(regval) << 9)) + #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ + #define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ + #define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ @@ -269,7 +269,7 @@ typedef enum - #define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ - - /* USART stop bits definitions */ --#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -+#define CTL1_STB(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) - #define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ - #define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ - #define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ + #define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + + /* USART stop bits definitions */ +-#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) ++#define CTL1_STB(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) + #define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ + #define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ + #define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_wwdgt.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_wwdgt.h index d332614..8d13b3f --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_wwdgt.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Include/gd32e10x_wwdgt.h @@ -49,19 +49,19 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* WWDGT_CTL */ --#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ -+#define WWDGT_CTL_CNT GD_BITS(0,6) /*!< WWDGT counter value */ - #define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ - - /* WWDGT_CFG */ --#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ --#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ -+#define WWDGT_CFG_WIN GD_BITS(0,6) /*!< WWDGT counter window value */ -+#define WWDGT_CFG_PSC GD_BITS(7,8) /*!< WWDGT prescaler divider value */ - #define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ - - /* WWDGT_STAT */ - #define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ - - /* constants definitions */ --#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ -+#define CFG_PSC(regval) (GD_BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ - #define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ - #define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ - #define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ + + /* bits definitions */ + /* WWDGT_CTL */ +-#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ ++#define WWDGT_CTL_CNT GD_BITS(0,6) /*!< WWDGT counter value */ + #define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + + /* WWDGT_CFG */ +-#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +-#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ ++#define WWDGT_CFG_WIN GD_BITS(0,6) /*!< WWDGT counter window value */ ++#define WWDGT_CFG_PSC GD_BITS(7,8) /*!< WWDGT prescaler divider value */ + #define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ + + /* WWDGT_STAT */ + #define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ + + /* constants definitions */ +-#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ ++#define CFG_PSC(regval) (GD_BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ + #define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ + #define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ + #define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Source/gd32e10x_fwdgt.c b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Source/gd32e10x_fwdgt.c index 173f35f..96fdc9c --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Source/gd32e10x_fwdgt.c +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Source/gd32e10x_fwdgt.c @@ -37,9 +37,9 @@ OF SUCH DAMAGE. - #include "gd32e10x_fwdgt.h" - - /* write value to FWDGT_CTL_CMD bit field */ --#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -+#define CTL_CMD(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) - /* write value to FWDGT_RLD_RLD bit field */ --#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) -+#define RLD_RLD(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) - - /*! - \brief enable write access to FWDGT_PSC and FWDGT_RLD + #include "gd32e10x_fwdgt.h" + + /* write value to FWDGT_CTL_CMD bit field */ +-#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) ++#define CTL_CMD(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) + /* write value to FWDGT_RLD_RLD bit field */ +-#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) ++#define RLD_RLD(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) + + /*! + \brief enable write access to FWDGT_PSC and FWDGT_RLD diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Source/gd32e10x_rcu.c b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Source/gd32e10x_rcu.c index cbbfb58..c7c0572 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Source/gd32e10x_rcu.c +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Source/gd32e10x_rcu.c @@ -547,7 +547,7 @@ void rcu_adc_clock_config(uint32_t adc_psc) - case RCU_CKADC_CKAHB_DIV5: - case RCU_CKADC_CKAHB_DIV7: - case RCU_CKADC_CKAHB_DIV9: -- adc_psc &= ~BITS(2,3); -+ adc_psc &= ~GD_BITS(2,3); - reg0 |= (adc_psc << RCU_ADC_PSC_OFFSET); - reg1 |= RCU_CFG1_ADCPSC_3; - break; + case RCU_CKADC_CKAHB_DIV5: + case RCU_CKADC_CKAHB_DIV7: + case RCU_CKADC_CKAHB_DIV9: +- adc_psc &= ~BITS(2,3); ++ adc_psc &= ~GD_BITS(2,3); + reg0 |= (adc_psc << RCU_ADC_PSC_OFFSET); + reg1 |= RCU_CFG1_ADCPSC_3; + break; diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Source/gd32e10x_wwdgt.c b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Source/gd32e10x_wwdgt.c index b67aa5a..05a2aee --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Source/gd32e10x_wwdgt.c +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_standard_peripheral/Source/gd32e10x_wwdgt.c @@ -37,9 +37,9 @@ OF SUCH DAMAGE. - #include "gd32e10x_wwdgt.h" - - /* write value to WWDGT_CTL_CNT bit field */ --#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -+#define CTL_CNT(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) - /* write value to WWDGT_CFG_WIN bit field */ --#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -+#define CFG_WIN(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) - - /*! - \brief reset the window watchdog timer configuration + #include "gd32e10x_wwdgt.h" + + /* write value to WWDGT_CTL_CNT bit field */ +-#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) ++#define CTL_CNT(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) + /* write value to WWDGT_CFG_WIN bit field */ +-#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) ++#define CFG_WIN(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) + + /*! + \brief reset the window watchdog timer configuration diff --git a/GD32E10x_Firmware_Library/Firmware/GD32E10x_usbfs_driver/Include/usb_regs.h b/GD32E10x_Firmware_Library/Firmware/GD32E10x_usbfs_driver/Include/usb_regs.h index 2d0f067..4dce601 --- a/GD32E10x_Firmware_Library/Firmware/GD32E10x_usbfs_driver/Include/usb_regs.h +++ b/GD32E10x_Firmware_Library/Firmware/GD32E10x_usbfs_driver/Include/usb_regs.h @@ -141,13 +141,13 @@ OF SUCH DAMAGE. - /* global USB control and status register bits definitions */ - #define GUSBCS_FDM BIT(30) /*!< force device mode */ - #define GUSBCS_FHM BIT(29) /*!< force host mode */ --#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ -+#define GUSBCS_UTT GD_BITS(10, 13) /*!< USB turnaround time */ - #define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ - #define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ --#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ -+#define GUSBCS_TOC GD_BITS(0, 2) /*!< timeout calibration */ - - /* global reset control register bits definitions */ --#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ -+#define GRSTCTL_TXFNUM GD_BITS(6, 10) /*!< tx FIFO number */ - #define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ - #define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ - #define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ + /* global USB control and status register bits definitions */ + #define GUSBCS_FDM BIT(30) /*!< force device mode */ + #define GUSBCS_FHM BIT(29) /*!< force host mode */ +-#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ ++#define GUSBCS_UTT GD_BITS(10, 13) /*!< USB turnaround time */ + #define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ + #define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ +-#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ ++#define GUSBCS_TOC GD_BITS(0, 2) /*!< timeout calibration */ + + /* global reset control register bits definitions */ +-#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ ++#define GRSTCTL_TXFNUM GD_BITS(6, 10) /*!< tx FIFO number */ + #define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ + #define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ + #define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ @@ -210,29 +210,29 @@ OF SUCH DAMAGE. - #define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ - - /* global receive status read and pop register bits definitions */ --#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ --#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ --#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ --#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ --#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ -+#define GRSTATRP_RPCKST GD_BITS(17, 20) /*!< received packet status */ -+#define GRSTATRP_DPID GD_BITS(15, 16) /*!< data PID */ -+#define GRSTATRP_BCOUNT GD_BITS(4, 14) /*!< byte count */ -+#define GRSTATRP_CNUM GD_BITS(0, 3) /*!< channel number */ -+#define GRSTATRP_EPNUM GD_BITS(0, 3) /*!< endpoint number */ - - /* global receive FIFO length register bits definitions */ --#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ -+#define GRFLEN_RXFD GD_BITS(0, 15) /*!< rx FIFO depth */ - - /* host non-periodic transmit FIFO length register bits definitions */ --#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ --#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ -+#define HNPTFLEN_HNPTXFD GD_BITS(16, 31) /*!< non-periodic Tx FIFO depth */ -+#define HNPTFLEN_HNPTXRSAR GD_BITS(0, 15) /*!< non-periodic Tx RAM start address */ - - /* IN endpoint 0 transmit FIFO length register bits definitions */ --#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ --#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ -+#define DIEP0TFLEN_IEP0TXFD GD_BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ -+#define DIEP0TFLEN_IEP0TXRSAR GD_BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ - - /* host non-periodic transmit FIFO/queue status register bits definitions */ --#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ --#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ --#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ --#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ --#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ -+#define HNPTFQSTAT_NPTXRQTOP GD_BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ -+#define HNPTFQSTAT_NPTXRQS GD_BITS(16, 23) /*!< non-periodic Tx request queue space */ -+#define HNPTFQSTAT_NPTXFS GD_BITS(0, 15) /*!< non-periodic Tx FIFO space */ -+#define HNPTFQSTAT_CNUM GD_BITS(27, 30) /*!< channel number */ -+#define HNPTFQSTAT_TYPE GD_BITS(25, 26) /*!< token type */ - #define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - - /* global core configuration register bits definitions */ + #define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ + + /* global receive status read and pop register bits definitions */ +-#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ +-#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ +-#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ +-#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ +-#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ ++#define GRSTATRP_RPCKST GD_BITS(17, 20) /*!< received packet status */ ++#define GRSTATRP_DPID GD_BITS(15, 16) /*!< data PID */ ++#define GRSTATRP_BCOUNT GD_BITS(4, 14) /*!< byte count */ ++#define GRSTATRP_CNUM GD_BITS(0, 3) /*!< channel number */ ++#define GRSTATRP_EPNUM GD_BITS(0, 3) /*!< endpoint number */ + + /* global receive FIFO length register bits definitions */ +-#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ ++#define GRFLEN_RXFD GD_BITS(0, 15) /*!< rx FIFO depth */ + + /* host non-periodic transmit FIFO length register bits definitions */ +-#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ +-#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ ++#define HNPTFLEN_HNPTXFD GD_BITS(16, 31) /*!< non-periodic Tx FIFO depth */ ++#define HNPTFLEN_HNPTXRSAR GD_BITS(0, 15) /*!< non-periodic Tx RAM start address */ + + /* IN endpoint 0 transmit FIFO length register bits definitions */ +-#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ +-#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ ++#define DIEP0TFLEN_IEP0TXFD GD_BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ ++#define DIEP0TFLEN_IEP0TXRSAR GD_BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ + + /* host non-periodic transmit FIFO/queue status register bits definitions */ +-#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ +-#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ +-#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ +-#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ +-#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ ++#define HNPTFQSTAT_NPTXRQTOP GD_BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ ++#define HNPTFQSTAT_NPTXRQS GD_BITS(16, 23) /*!< non-periodic Tx request queue space */ ++#define HNPTFQSTAT_NPTXFS GD_BITS(0, 15) /*!< non-periodic Tx FIFO space */ ++#define HNPTFQSTAT_CNUM GD_BITS(27, 30) /*!< channel number */ ++#define HNPTFQSTAT_TYPE GD_BITS(25, 26) /*!< token type */ + #define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + + /* global core configuration register bits definitions */ @@ -243,44 +243,44 @@ OF SUCH DAMAGE. - #define GCCFG_PWRON BIT(16) /*!< power on */ - - /* core ID register bits definitions */ --#define CID_CID BITS(0, 31) /*!< core ID */ -+#define CID_CID GD_BITS(0, 31) /*!< core ID */ - - /* host periodic transmit FIFO length register bits definitions */ --#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ --#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ -+#define HPTFLEN_HPTXFD GD_BITS(16, 31) /*!< host periodic Tx FIFO depth */ -+#define HPTFLEN_HPTXFSAR GD_BITS(0, 15) /*!< host periodic Tx RAM start address */ - - /* device IN endpoint transmit FIFO length register bits definitions */ --#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ --#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ -+#define DIEPTFLEN_IEPTXFD GD_BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ -+#define DIEPTFLEN_IEPTXRSAR GD_BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ - - /* host control register bits definitions */ --#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ -+#define HCTL_CLKSEL GD_BITS(0, 1) /*!< clock select for USB clock */ - - /* host frame interval register bits definitions */ --#define HFT_FRI BITS(0, 15) /*!< frame interval */ -+#define HFT_FRI GD_BITS(0, 15) /*!< frame interval */ - - /* host frame information remaining register bits definitions */ --#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ --#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ -+#define HFINFR_FRT GD_BITS(16, 31) /*!< frame remaining time */ -+#define HFINFR_FRNUM GD_BITS(0, 15) /*!< frame number */ - - /* host periodic transmit FIFO/queue status register bits definitions */ --#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ --#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ --#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ --#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ --#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ -+#define HPTFQSTAT_PTXREQT GD_BITS(24, 31) /*!< top entry of the periodic Tx request queue */ -+#define HPTFQSTAT_PTXREQS GD_BITS(16, 23) /*!< periodic Tx request queue space */ -+#define HPTFQSTAT_PTXFS GD_BITS(0, 15) /*!< periodic Tx FIFO space */ -+#define HPTFQSTAT_CNUM GD_BITS(27, 30) /*!< channel number */ -+#define HPTFQSTAT_TYPE GD_BITS(25, 26) /*!< token type */ - #define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - - /* host all channels interrupt register bits definitions */ --#define HACHINT_HACHINT BITS(0, 7) /*!< host all channel interrupts */ -+#define HACHINT_HACHINT GD_BITS(0, 7) /*!< host all channel interrupts */ - - /* host all channels interrupt enable register bits definitions */ --#define HACHINTEN_CINTEN BITS(0, 7) /*!< channel interrupt enable */ -+#define HACHINTEN_CINTEN GD_BITS(0, 7) /*!< channel interrupt enable */ - - /* host port control and status register bits definitions */ --#define HPCS_PS BITS(17, 18) /*!< port speed */ -+#define HPCS_PS GD_BITS(17, 18) /*!< port speed */ - #define HPCS_PP BIT(12) /*!< port power */ --#define HPCS_PLST BITS(10, 11) /*!< port line status */ -+#define HPCS_PLST GD_BITS(10, 11) /*!< port line status */ - #define HPCS_PRST BIT(8) /*!< port reset */ - #define HPCS_PSP BIT(7) /*!< port suspend */ - #define HPCS_PREM BIT(6) /*!< port resume */ + #define GCCFG_PWRON BIT(16) /*!< power on */ + + /* core ID register bits definitions */ +-#define CID_CID BITS(0, 31) /*!< core ID */ ++#define CID_CID GD_BITS(0, 31) /*!< core ID */ + + /* host periodic transmit FIFO length register bits definitions */ +-#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ +-#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ ++#define HPTFLEN_HPTXFD GD_BITS(16, 31) /*!< host periodic Tx FIFO depth */ ++#define HPTFLEN_HPTXFSAR GD_BITS(0, 15) /*!< host periodic Tx RAM start address */ + + /* device IN endpoint transmit FIFO length register bits definitions */ +-#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ +-#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ ++#define DIEPTFLEN_IEPTXFD GD_BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ ++#define DIEPTFLEN_IEPTXRSAR GD_BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ + + /* host control register bits definitions */ +-#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ ++#define HCTL_CLKSEL GD_BITS(0, 1) /*!< clock select for USB clock */ + + /* host frame interval register bits definitions */ +-#define HFT_FRI BITS(0, 15) /*!< frame interval */ ++#define HFT_FRI GD_BITS(0, 15) /*!< frame interval */ + + /* host frame information remaining register bits definitions */ +-#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ +-#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ ++#define HFINFR_FRT GD_BITS(16, 31) /*!< frame remaining time */ ++#define HFINFR_FRNUM GD_BITS(0, 15) /*!< frame number */ + + /* host periodic transmit FIFO/queue status register bits definitions */ +-#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ +-#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ +-#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ +-#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ +-#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ ++#define HPTFQSTAT_PTXREQT GD_BITS(24, 31) /*!< top entry of the periodic Tx request queue */ ++#define HPTFQSTAT_PTXREQS GD_BITS(16, 23) /*!< periodic Tx request queue space */ ++#define HPTFQSTAT_PTXFS GD_BITS(0, 15) /*!< periodic Tx FIFO space */ ++#define HPTFQSTAT_CNUM GD_BITS(27, 30) /*!< channel number */ ++#define HPTFQSTAT_TYPE GD_BITS(25, 26) /*!< token type */ + #define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + + /* host all channels interrupt register bits definitions */ +-#define HACHINT_HACHINT BITS(0, 7) /*!< host all channel interrupts */ ++#define HACHINT_HACHINT GD_BITS(0, 7) /*!< host all channel interrupts */ + + /* host all channels interrupt enable register bits definitions */ +-#define HACHINTEN_CINTEN BITS(0, 7) /*!< channel interrupt enable */ ++#define HACHINTEN_CINTEN GD_BITS(0, 7) /*!< channel interrupt enable */ + + /* host port control and status register bits definitions */ +-#define HPCS_PS BITS(17, 18) /*!< port speed */ ++#define HPCS_PS GD_BITS(17, 18) /*!< port speed */ + #define HPCS_PP BIT(12) /*!< port power */ +-#define HPCS_PLST BITS(10, 11) /*!< port line status */ ++#define HPCS_PLST GD_BITS(10, 11) /*!< port line status */ + #define HPCS_PRST BIT(8) /*!< port reset */ + #define HPCS_PSP BIT(7) /*!< port suspend */ + #define HPCS_PREM BIT(6) /*!< port resume */ @@ -293,13 +293,13 @@ OF SUCH DAMAGE. - #define HCHCTL_CEN BIT(31) /*!< channel enable */ - #define HCHCTL_CDIS BIT(30) /*!< channel disable */ - #define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ --#define HCHCTL_DAR BITS(22, 28) /*!< device address */ --#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ --#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -+#define HCHCTL_DAR GD_BITS(22, 28) /*!< device address */ -+#define HCHCTL_MPC GD_BITS(20, 21) /*!< multiple packet count */ -+#define HCHCTL_EPTYPE GD_BITS(18, 19) /*!< endpoint type */ - #define HCHCTL_LSD BIT(17) /*!< low-speed device */ - #define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ --#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ --#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ -+#define HCHCTL_EPNUM GD_BITS(11, 14) /*!< endpoint number */ -+#define HCHCTL_MPL GD_BITS(0, 10) /*!< maximum packet length */ - - /* host channel-x interrupt flag register bits definitions */ - #define HCHINTF_DTER BIT(10) /*!< data toggle error */ + #define HCHCTL_CEN BIT(31) /*!< channel enable */ + #define HCHCTL_CDIS BIT(30) /*!< channel disable */ + #define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ +-#define HCHCTL_DAR BITS(22, 28) /*!< device address */ +-#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ +-#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ ++#define HCHCTL_DAR GD_BITS(22, 28) /*!< device address */ ++#define HCHCTL_MPC GD_BITS(20, 21) /*!< multiple packet count */ ++#define HCHCTL_EPTYPE GD_BITS(18, 19) /*!< endpoint type */ + #define HCHCTL_LSD BIT(17) /*!< low-speed device */ + #define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ +-#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ +-#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ ++#define HCHCTL_EPNUM GD_BITS(11, 14) /*!< endpoint number */ ++#define HCHCTL_MPL GD_BITS(0, 10) /*!< maximum packet length */ + + /* host channel-x interrupt flag register bits definitions */ + #define HCHINTF_DTER BIT(10) /*!< data toggle error */ @@ -326,16 +326,16 @@ OF SUCH DAMAGE. - #define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ - - /* host channel-x transfer length register bits definitions */ --#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ --#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ --#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ -+#define HCHLEN_DPID GD_BITS(29, 30) /*!< data PID */ -+#define HCHLEN_PCNT GD_BITS(19, 28) /*!< packet count */ -+#define HCHLEN_TLEN GD_BITS(0, 18) /*!< transfer length */ - - /* device control and status registers */ - /* device configuration registers bits definitions */ --#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ --#define DCFG_DAR BITS(4, 10) /*!< device address */ -+#define DCFG_EOPFT GD_BITS(11, 12) /*!< end of periodic frame time */ -+#define DCFG_DAR GD_BITS(4, 10) /*!< device address */ - #define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ --#define DCFG_DS BITS(0, 1) /*!< device speed */ -+#define DCFG_DS GD_BITS(0, 1) /*!< device speed */ - - /* device control registers bits definitions */ - #define DCTL_POIF BIT(11) /*!< power-on initialization finished */ + #define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ + + /* host channel-x transfer length register bits definitions */ +-#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ +-#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ +-#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ ++#define HCHLEN_DPID GD_BITS(29, 30) /*!< data PID */ ++#define HCHLEN_PCNT GD_BITS(19, 28) /*!< packet count */ ++#define HCHLEN_TLEN GD_BITS(0, 18) /*!< transfer length */ + + /* device control and status registers */ + /* device configuration registers bits definitions */ +-#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ +-#define DCFG_DAR BITS(4, 10) /*!< device address */ ++#define DCFG_EOPFT GD_BITS(11, 12) /*!< end of periodic frame time */ ++#define DCFG_DAR GD_BITS(4, 10) /*!< device address */ + #define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ +-#define DCFG_DS BITS(0, 1) /*!< device speed */ ++#define DCFG_DS GD_BITS(0, 1) /*!< device speed */ + + /* device control registers bits definitions */ + #define DCTL_POIF BIT(11) /*!< power-on initialization finished */ @@ -349,8 +349,8 @@ OF SUCH DAMAGE. - #define DCTL_RWKUP BIT(0) /*!< remote wakeup */ - - /* device status registers bits definitions */ --#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ --#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ -+#define DSTAT_FNRSOF GD_BITS(8, 21) /*!< the frame number of the received SOF. */ -+#define DSTAT_ES GD_BITS(1, 2) /*!< enumerated speed */ - #define DSTAT_SPST BIT(0) /*!< suspend status */ - - /* device IN endpoint common interrupt enable registers bits definitions */ + #define DCTL_RWKUP BIT(0) /*!< remote wakeup */ + + /* device status registers bits definitions */ +-#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ +-#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ ++#define DSTAT_FNRSOF GD_BITS(8, 21) /*!< the frame number of the received SOF. */ ++#define DSTAT_ES GD_BITS(1, 2) /*!< enumerated speed */ + #define DSTAT_SPST BIT(0) /*!< suspend status */ + + /* device IN endpoint common interrupt enable registers bits definitions */ @@ -368,34 +368,34 @@ OF SUCH DAMAGE. - #define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - - /* device all endpoints interrupt registers bits definitions */ --#define DAEPINT_OEPITB BITS(16, 19) /*!< device all OUT endpoint interrupt bits */ --#define DAEPINT_IEPITB BITS(0, 3) /*!< device all IN endpoint interrupt bits */ -+#define DAEPINT_OEPITB GD_BITS(16, 19) /*!< device all OUT endpoint interrupt bits */ -+#define DAEPINT_IEPITB GD_BITS(0, 3) /*!< device all IN endpoint interrupt bits */ - - /* device all endpoints interrupt enable registers bits definitions */ --#define DAEPINTEN_OEPIE BITS(16, 19) /*!< OUT endpoint interrupt enable */ --#define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ -+#define DAEPINTEN_OEPIE GD_BITS(16, 19) /*!< OUT endpoint interrupt enable */ -+#define DAEPINTEN_IEPIE GD_BITS(0, 3) /*!< IN endpoint interrupt enable */ - - /* device Vbus discharge time registers bits definitions */ --#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ -+#define DVBUSDT_DVBUSDT GD_BITS(0, 15) /*!< device VBUS discharge time */ - - /* device Vbus pulsing time registers bits definitions */ --#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ -+#define DVBUSPT_DVBUSPT GD_BITS(0, 11) /*!< device VBUS pulsing time */ - - /* device IN endpoint FIFO empty interrupt enable register bits definitions */ --#define DIEPFEINTEN_IEPTXFEIE BITS(0, 3) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ -+#define DIEPFEINTEN_IEPTXFEIE GD_BITS(0, 3) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ - - /* device endpoint 0 control register bits definitions */ - #define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ - #define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ - #define DEP0CTL_SNAK BIT(27) /*!< set NAK */ - #define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ --#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -+#define DIEP0CTL_TXFNUM GD_BITS(22, 25) /*!< tx FIFO number */ - #define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ - #define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ --#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -+#define DEP0CTL_EPTYPE GD_BITS(18, 19) /*!< endpoint type */ - #define DEP0CTL_NAKS BIT(17) /*!< NAK status */ - #define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ --#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ -+#define DEP0CTL_MPL GD_BITS(0, 1) /*!< maximum packet length */ - - /* device endpoint x control register bits definitions */ - #define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ + #define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + + /* device all endpoints interrupt registers bits definitions */ +-#define DAEPINT_OEPITB BITS(16, 19) /*!< device all OUT endpoint interrupt bits */ +-#define DAEPINT_IEPITB BITS(0, 3) /*!< device all IN endpoint interrupt bits */ ++#define DAEPINT_OEPITB GD_BITS(16, 19) /*!< device all OUT endpoint interrupt bits */ ++#define DAEPINT_IEPITB GD_BITS(0, 3) /*!< device all IN endpoint interrupt bits */ + + /* device all endpoints interrupt enable registers bits definitions */ +-#define DAEPINTEN_OEPIE BITS(16, 19) /*!< OUT endpoint interrupt enable */ +-#define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ ++#define DAEPINTEN_OEPIE GD_BITS(16, 19) /*!< OUT endpoint interrupt enable */ ++#define DAEPINTEN_IEPIE GD_BITS(0, 3) /*!< IN endpoint interrupt enable */ + + /* device Vbus discharge time registers bits definitions */ +-#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ ++#define DVBUSDT_DVBUSDT GD_BITS(0, 15) /*!< device VBUS discharge time */ + + /* device Vbus pulsing time registers bits definitions */ +-#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ ++#define DVBUSPT_DVBUSPT GD_BITS(0, 11) /*!< device VBUS pulsing time */ + + /* device IN endpoint FIFO empty interrupt enable register bits definitions */ +-#define DIEPFEINTEN_IEPTXFEIE BITS(0, 3) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ ++#define DIEPFEINTEN_IEPTXFEIE GD_BITS(0, 3) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ + + /* device endpoint 0 control register bits definitions */ + #define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ + #define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ + #define DEP0CTL_SNAK BIT(27) /*!< set NAK */ + #define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ +-#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ ++#define DIEP0CTL_TXFNUM GD_BITS(22, 25) /*!< tx FIFO number */ + #define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ + #define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ +-#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ ++#define DEP0CTL_EPTYPE GD_BITS(18, 19) /*!< endpoint type */ + #define DEP0CTL_NAKS BIT(17) /*!< NAK status */ + #define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ +-#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ ++#define DEP0CTL_MPL GD_BITS(0, 1) /*!< maximum packet length */ + + /* device endpoint x control register bits definitions */ + #define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ @@ -406,15 +406,15 @@ OF SUCH DAMAGE. - #define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ - #define DEPCTL_SNAK BIT(27) /*!< set NAK */ - #define DEPCTL_CNAK BIT(26) /*!< clear NAK */ --#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -+#define DIEPCTL_TXFNUM GD_BITS(22, 25) /*!< tx FIFO number */ - #define DEPCTL_STALL BIT(21) /*!< STALL handshake */ - #define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ --#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -+#define DEPCTL_EPTYPE GD_BITS(18, 19) /*!< endpoint type */ - #define DEPCTL_NAKS BIT(17) /*!< NAK status */ - #define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ - #define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ - #define DEPCTL_EPACT BIT(15) /*!< endpoint active */ --#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ -+#define DEPCTL_MPL GD_BITS(0, 10) /*!< maximum packet length */ - - /* device IN endpoint-x interrupt flag register bits definitions */ - #define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */ + #define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ + #define DEPCTL_SNAK BIT(27) /*!< set NAK */ + #define DEPCTL_CNAK BIT(26) /*!< clear NAK */ +-#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ ++#define DIEPCTL_TXFNUM GD_BITS(22, 25) /*!< tx FIFO number */ + #define DEPCTL_STALL BIT(21) /*!< STALL handshake */ + #define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ +-#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ ++#define DEPCTL_EPTYPE GD_BITS(18, 19) /*!< endpoint type */ + #define DEPCTL_NAKS BIT(17) /*!< NAK status */ + #define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ + #define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ + #define DEPCTL_EPACT BIT(15) /*!< endpoint active */ +-#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ ++#define DEPCTL_MPL GD_BITS(0, 10) /*!< maximum packet length */ + + /* device IN endpoint-x interrupt flag register bits definitions */ + #define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */ @@ -432,22 +432,22 @@ OF SUCH DAMAGE. - #define DOEPINTF_TF BIT(0) /*!< transfer finished */ - - /* device IN endpoint 0 transfer length register bits definitions */ --#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ --#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ -+#define DIEP0LEN_PCNT GD_BITS(19, 20) /*!< packet count */ -+#define DIEP0LEN_TLEN GD_BITS(0, 6) /*!< transfer length */ - - /* device OUT endpoint 0 transfer length register bits definitions */ --#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ -+#define DOEP0LEN_STPCNT GD_BITS(29, 30) /*!< SETUP packet count */ - #define DOEP0LEN_PCNT BIT(19) /*!< packet count */ --#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ -+#define DOEP0LEN_TLEN GD_BITS(0, 6) /*!< transfer length */ - - /* device OUT endpoint-x transfer length register bits definitions */ --#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ --#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ --#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ --#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ -+#define DOEPLEN_RXDPID GD_BITS(29, 30) /*!< received data PID */ -+#define DOEPLEN_STPCNT GD_BITS(29, 30) /*!< SETUP packet count */ -+#define DEPLEN_PCNT GD_BITS(19, 28) /*!< packet count */ -+#define DEPLEN_TLEN GD_BITS(0, 18) /*!< transfer length */ - - /* device IN endpoint-x transmit FIFO status register bits definitions */ --#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint¡¯s Tx FIFO space remaining */ -+#define DIEPTFSTAT_IEPTFS GD_BITS(0, 15) /*!< IN endpoint¡¯s Tx FIFO space remaining */ - - /* USB power and clock registers bits definition */ - #define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ + #define DOEPINTF_TF BIT(0) /*!< transfer finished */ + + /* device IN endpoint 0 transfer length register bits definitions */ +-#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ +-#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ ++#define DIEP0LEN_PCNT GD_BITS(19, 20) /*!< packet count */ ++#define DIEP0LEN_TLEN GD_BITS(0, 6) /*!< transfer length */ + + /* device OUT endpoint 0 transfer length register bits definitions */ +-#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ ++#define DOEP0LEN_STPCNT GD_BITS(29, 30) /*!< SETUP packet count */ + #define DOEP0LEN_PCNT BIT(19) /*!< packet count */ +-#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ ++#define DOEP0LEN_TLEN GD_BITS(0, 6) /*!< transfer length */ + + /* device OUT endpoint-x transfer length register bits definitions */ +-#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ +-#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ +-#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ +-#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ ++#define DOEPLEN_RXDPID GD_BITS(29, 30) /*!< received data PID */ ++#define DOEPLEN_STPCNT GD_BITS(29, 30) /*!< SETUP packet count */ ++#define DEPLEN_PCNT GD_BITS(19, 28) /*!< packet count */ ++#define DEPLEN_TLEN GD_BITS(0, 18) /*!< transfer length */ + + /* device IN endpoint-x transmit FIFO status register bits definitions */ +-#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint¡¯s Tx FIFO space remaining */ ++#define DIEPTFSTAT_IEPTFS GD_BITS(0, 15) /*!< IN endpoint¡¯s Tx FIFO space remaining */ + + /* USB power and clock registers bits definition */ + #define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ diff --git a/targets/bsp/drivers/GD32E10x_Firmware/patch.sha256 b/targets/bsp/drivers/GD32E10x_Firmware/patch.sha256 index 837fa1c..131df19 100644 --- a/targets/bsp/drivers/GD32E10x_Firmware/patch.sha256 +++ b/targets/bsp/drivers/GD32E10x_Firmware/patch.sha256 @@ -1,2 +1,2 @@ -e84515ca3968021dea8611d61df653ac3a00f4b6b447aca1f277e1eb564022e1 driver.patch -a5b6bdef6f7c819e8600e0665eb7f3015b928d56b9cfb8dc8b4a0cea79fed91f board.patch +b1264eaee86793db44c830574b6b035271e1553271ade1133e019f002190d538 driver.patch +2bc98c16777861b7179ee2c6fa297d8216eddc21b3e380f8cb9e613452963539 board.patch diff --git a/targets/bsp/drivers/GD32F30x_Firmware/board.patch b/targets/bsp/drivers/GD32F30x_Firmware/board.patch index d2ab64d..d2e150d 100644 --- a/targets/bsp/drivers/GD32F30x_Firmware/board.patch +++ b/targets/bsp/drivers/GD32F30x_Firmware/board.patch @@ -5,24 +5,24 @@ index ec748a4..d83824a --- a/Inc/gd32f30x.h +++ b/Inc/gd32f30x.h @@ -295,8 +295,8 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) - #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) - #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) --#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) --#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) -+#define GD_BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -+#define GET_BITS(regval, start, end) (((regval) & GD_BITS((start),(end))) >> (start)) - - /* main flash and SRAM memory map */ - #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ + #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) + #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) + #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +-#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +-#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) ++#define GD_BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) ++#define GET_BITS(regval, start, end) (((regval) & GD_BITS((start),(end))) >> (start)) + + /* main flash and SRAM memory map */ + #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ @@ -342,10 +342,6 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - #define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */ - #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ - --/* define marco USE_STDPERIPH_DRIVER */ --#if !defined USE_STDPERIPH_DRIVER --#define USE_STDPERIPH_DRIVER --#endif - #ifdef USE_STDPERIPH_DRIVER - #include "gd32f30x_libopt.h" - #endif /* USE_STDPERIPH_DRIVER */ + #define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */ + #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ + +-/* define marco USE_STDPERIPH_DRIVER */ +-#if !defined USE_STDPERIPH_DRIVER +-#define USE_STDPERIPH_DRIVER +-#endif + #ifdef USE_STDPERIPH_DRIVER + #include "gd32f30x_libopt.h" + #endif /* USE_STDPERIPH_DRIVER */ diff --git a/targets/bsp/drivers/GD32F30x_Firmware/driver.patch b/targets/bsp/drivers/GD32F30x_Firmware/driver.patch index d510a16..9999164 100644 --- a/targets/bsp/drivers/GD32F30x_Firmware/driver.patch +++ b/targets/bsp/drivers/GD32F30x_Firmware/driver.patch @@ -5,16 +5,16 @@ index ec748a4..88db524 --- a/GD32F30x_Firmware_Library/Firmware/CMSIS/GD/GD32F30x/Include/gd32f30x.h +++ b/GD32F30x_Firmware_Library/Firmware/CMSIS/GD/GD32F30x/Include/gd32f30x.h @@ -295,8 +295,8 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) - #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) - #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) --#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) --#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) -+#define GD_BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -+#define GET_BITS(regval, start, end) (((regval) & GD_BITS((start),(end))) >> (start)) - - /* main flash and SRAM memory map */ - #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ + #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) + #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) + #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +-#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +-#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) ++#define GD_BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) ++#define GET_BITS(regval, start, end) (((regval) & GD_BITS((start),(end))) >> (start)) + + /* main flash and SRAM memory map */ + #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h old mode 100644 new mode 100755 @@ -22,185 +22,185 @@ index 7b0be2e..7f9be32 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h @@ -79,7 +79,7 @@ OF SUCH DAMAGE. - #define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ - - /* ADC_CTL0 */ --#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -+#define ADC_CTL0_WDCHSEL GD_BITS(0,4) /*!< analog watchdog channel select bits */ - #define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ - #define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ - #define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ + #define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ + + /* ADC_CTL0 */ +-#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ ++#define ADC_CTL0_WDCHSEL GD_BITS(0,4) /*!< analog watchdog channel select bits */ + #define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ + #define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ + #define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ @@ -88,11 +88,11 @@ OF SUCH DAMAGE. - #define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ - #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ - #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ --#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ --#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ -+#define ADC_CTL0_DISNUM GD_BITS(13,15) /*!< discontinuous mode channel count */ -+#define ADC_CTL0_SYNCM GD_BITS(16,19) /*!< sync mode selection */ - #define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ - #define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ --#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ -+#define ADC_CTL0_DRES GD_BITS(24,25) /*!< ADC data resolution */ - - /* ADC_CTL1 */ - #define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ + #define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ + #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ + #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +-#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +-#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ ++#define ADC_CTL0_DISNUM GD_BITS(13,15) /*!< discontinuous mode channel count */ ++#define ADC_CTL0_SYNCM GD_BITS(16,19) /*!< sync mode selection */ + #define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ + #define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ +-#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ ++#define ADC_CTL0_DRES GD_BITS(24,25) /*!< ADC data resolution */ + + /* ADC_CTL1 */ + #define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ @@ -101,47 +101,47 @@ OF SUCH DAMAGE. - #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ - #define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ - #define ADC_CTL1_DAL BIT(11) /*!< data alignment */ --#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ -+#define ADC_CTL1_ETSIC GD_BITS(12,14) /*!< external trigger select for inserted channel */ - #define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ --#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ -+#define ADC_CTL1_ETSRC GD_BITS(17,19) /*!< external trigger select for regular channel */ - #define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ - #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ - #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ - #define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ - - /* ADC_SAMPTx x=0..1 */ --#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */ -+#define ADC_SAMPTX_SPTN GD_BITS(0,2) /*!< channel x sample time selection */ - - /* ADC_IOFFx x=0..3 */ --#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ -+#define ADC_IOFFX_IOFF GD_BITS(0,11) /*!< data offset for inserted channel x */ - - /* ADC_WDHT */ --#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ -+#define ADC_WDHT_WDHT GD_BITS(0,11) /*!< analog watchdog high threshold */ - - /* ADC_WDLT */ --#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ -+#define ADC_WDLT_WDLT GD_BITS(0,11) /*!< analog watchdog low threshold */ - - /* ADC_RSQx */ --#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */ --#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ -+#define ADC_RSQX_RSQN GD_BITS(0,4) /*!< x conversion in regular sequence */ -+#define ADC_RSQ0_RL GD_BITS(20,23) /*!< regular channel sequence length */ - - /* ADC_ISQ */ --#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */ --#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ -+#define ADC_ISQ_ISQN GD_BITS(0,4) /*!< x conversion in regular sequence */ -+#define ADC_ISQ_IL GD_BITS(20,21) /*!< inserted sequence length */ - - /* ADC_IDATAx x=0..3*/ --#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ -+#define ADC_IDATAX_IDATAN GD_BITS(0,15) /*!< inserted data x */ - - /* ADC_RDATA */ --#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ --#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ -+#define ADC_RDATA_RDATA GD_BITS(0,15) /*!< regular data */ -+#define ADC_RDATA_ADC1RDTR GD_BITS(16,31) /*!< ADC1 regular channel data */ - - /* ADC_OVSAMPCTL */ - #define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ --#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ --#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ -+#define ADC_OVSAMPCTL_OVSR GD_BITS(2,4) /*!< oversampling ratio */ -+#define ADC_OVSAMPCTL_OVSS GD_BITS(5,8) /*!< oversampling shift */ - #define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ --#define ADC_OVSAMPCTL_DRES BITS(12,13) /*!< oversampling shift */ -+#define ADC_OVSAMPCTL_DRES GD_BITS(12,13) /*!< oversampling shift */ - - - /* constants definitions */ + #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ + #define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ + #define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +-#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ ++#define ADC_CTL1_ETSIC GD_BITS(12,14) /*!< external trigger select for inserted channel */ + #define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ +-#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ ++#define ADC_CTL1_ETSRC GD_BITS(17,19) /*!< external trigger select for regular channel */ + #define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ + #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ + #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ + #define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ + + /* ADC_SAMPTx x=0..1 */ +-#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */ ++#define ADC_SAMPTX_SPTN GD_BITS(0,2) /*!< channel x sample time selection */ + + /* ADC_IOFFx x=0..3 */ +-#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ ++#define ADC_IOFFX_IOFF GD_BITS(0,11) /*!< data offset for inserted channel x */ + + /* ADC_WDHT */ +-#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ ++#define ADC_WDHT_WDHT GD_BITS(0,11) /*!< analog watchdog high threshold */ + + /* ADC_WDLT */ +-#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ ++#define ADC_WDLT_WDLT GD_BITS(0,11) /*!< analog watchdog low threshold */ + + /* ADC_RSQx */ +-#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */ +-#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ ++#define ADC_RSQX_RSQN GD_BITS(0,4) /*!< x conversion in regular sequence */ ++#define ADC_RSQ0_RL GD_BITS(20,23) /*!< regular channel sequence length */ + + /* ADC_ISQ */ +-#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */ +-#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ ++#define ADC_ISQ_ISQN GD_BITS(0,4) /*!< x conversion in regular sequence */ ++#define ADC_ISQ_IL GD_BITS(20,21) /*!< inserted sequence length */ + + /* ADC_IDATAx x=0..3*/ +-#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ ++#define ADC_IDATAX_IDATAN GD_BITS(0,15) /*!< inserted data x */ + + /* ADC_RDATA */ +-#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ +-#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ ++#define ADC_RDATA_RDATA GD_BITS(0,15) /*!< regular data */ ++#define ADC_RDATA_ADC1RDTR GD_BITS(16,31) /*!< ADC1 regular channel data */ + + /* ADC_OVSAMPCTL */ + #define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ +-#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ +-#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ ++#define ADC_OVSAMPCTL_OVSR GD_BITS(2,4) /*!< oversampling ratio */ ++#define ADC_OVSAMPCTL_OVSS GD_BITS(5,8) /*!< oversampling shift */ + #define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ +-#define ADC_OVSAMPCTL_DRES BITS(12,13) /*!< oversampling shift */ ++#define ADC_OVSAMPCTL_DRES GD_BITS(12,13) /*!< oversampling shift */ + + + /* constants definitions */ @@ -153,7 +153,7 @@ OF SUCH DAMAGE. - #define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ - - /* adc_ctl0 register value */ --#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ -+#define CTL0_DISNUM(regval) (GD_BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ - - /* ADC special function definitions */ - #define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ + #define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ + + /* adc_ctl0 register value */ +-#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ ++#define CTL0_DISNUM(regval) (GD_BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ + + /* ADC special function definitions */ + #define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ @@ -161,7 +161,7 @@ OF SUCH DAMAGE. - #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ - - /* ADC synchronization mode */ --#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ -+#define CTL0_SYNCM(regval) (GD_BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ - #define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ - #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ - #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ + #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + + /* ADC synchronization mode */ +-#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ ++#define CTL0_SYNCM(regval) (GD_BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ + #define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ + #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ + #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ @@ -178,7 +178,7 @@ OF SUCH DAMAGE. - #define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ - - /* ADC external trigger select for regular channel */ --#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ -+#define CTL1_ETSRC(regval) (GD_BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ - #define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ - #define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ - #define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ + #define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ + + /* ADC external trigger select for regular channel */ +-#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ ++#define CTL1_ETSRC(regval) (GD_BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ + #define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ + #define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ + #define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ @@ -198,7 +198,7 @@ OF SUCH DAMAGE. - #define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< timer 4 CC2 event select */ - - /* ADC external trigger select for inserted channel */ --#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ -+#define CTL1_ETSIC(regval) (GD_BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ - #define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< timer 0 TRGO event select */ - #define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< timer 0 CC3 event select */ - #define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< timer 1 TRGO event select */ + #define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< timer 4 CC2 event select */ + + /* ADC external trigger select for inserted channel */ +-#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ ++#define CTL1_ETSIC(regval) (GD_BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ + #define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< timer 0 TRGO event select */ + #define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< timer 0 CC3 event select */ + #define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< timer 1 TRGO event select */ @@ -218,7 +218,7 @@ OF SUCH DAMAGE. - #define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< timer 4 CC3 event select */ - - /* ADC channel sample time */ --#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ -+#define SAMPTX_SPT(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ - #define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ - #define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ - #define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ + #define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< timer 4 CC3 event select */ + + /* ADC channel sample time */ +-#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ ++#define SAMPTX_SPT(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ + #define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ + #define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ + #define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ @@ -229,30 +229,30 @@ OF SUCH DAMAGE. - #define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ - - /* adc_ioffx register value */ --#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ -+#define IOFFX_IOFF(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ - - /* adc_wdht register value */ --#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ -+#define WDHT_WDHT(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ - - /* adc_wdlt register value */ --#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ -+#define WDLT_WDLT(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ - - /* adc_rsqx register value */ --#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ -+#define RSQ0_RL(regval) (GD_BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ - - /* adc_isq register value */ --#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ -+#define ISQ_IL(regval) (GD_BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ - - /* adc_ovsampctl register value */ - /* ADC resolution */ --#define OVSAMPCTL_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ -+#define OVSAMPCTL_DRES(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ - #define ADC_RESOLUTION_12B OVSAMPCTL_DRES(0) /*!< 12-bit ADC resolution */ - #define ADC_RESOLUTION_10B OVSAMPCTL_DRES(1) /*!< 10-bit ADC resolution */ - #define ADC_RESOLUTION_8B OVSAMPCTL_DRES(2) /*!< 8-bit ADC resolution */ - #define ADC_RESOLUTION_6B OVSAMPCTL_DRES(3) /*!< 6-bit ADC resolution */ - - /* oversampling shift */ --#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ -+#define OVSAMPCTL_OVSS(regval) (GD_BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ - #define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ - #define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ - #define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ + #define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ + + /* adc_ioffx register value */ +-#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ ++#define IOFFX_IOFF(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ + + /* adc_wdht register value */ +-#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ ++#define WDHT_WDHT(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ + + /* adc_wdlt register value */ +-#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ ++#define WDLT_WDLT(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ + + /* adc_rsqx register value */ +-#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ ++#define RSQ0_RL(regval) (GD_BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ + + /* adc_isq register value */ +-#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ ++#define ISQ_IL(regval) (GD_BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ + + /* adc_ovsampctl register value */ + /* ADC resolution */ +-#define OVSAMPCTL_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ ++#define OVSAMPCTL_DRES(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ + #define ADC_RESOLUTION_12B OVSAMPCTL_DRES(0) /*!< 12-bit ADC resolution */ + #define ADC_RESOLUTION_10B OVSAMPCTL_DRES(1) /*!< 10-bit ADC resolution */ + #define ADC_RESOLUTION_8B OVSAMPCTL_DRES(2) /*!< 8-bit ADC resolution */ + #define ADC_RESOLUTION_6B OVSAMPCTL_DRES(3) /*!< 6-bit ADC resolution */ + + /* oversampling shift */ +-#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ ++#define OVSAMPCTL_OVSS(regval) (GD_BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ + #define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ + #define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ + #define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ @@ -264,7 +264,7 @@ OF SUCH DAMAGE. - #define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ - - /* oversampling ratio */ --#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ -+#define OVSAMPCTL_OVSR(regval) (GD_BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ - #define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ - #define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ - #define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ + #define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ + + /* oversampling ratio */ +-#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ ++#define OVSAMPCTL_OVSR(regval) (GD_BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ + #define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ + #define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ + #define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h old mode 100644 new mode 100755 @@ -208,27 +208,27 @@ index a249c7d..e86e398 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h @@ -92,10 +92,10 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* BKP_DATA */ --#define BKP_DATA BITS(0,15) /*!< backup data */ -+#define BKP_DATA GD_BITS(0,15) /*!< backup data */ - - /* BKP_OCTL */ --#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ -+#define BKP_OCTL_RCCV GD_BITS(0,6) /*!< RTC clock calibration value */ - #define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ - #define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ - #define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ + + /* bits definitions */ + /* BKP_DATA */ +-#define BKP_DATA BITS(0,15) /*!< backup data */ ++#define BKP_DATA GD_BITS(0,15) /*!< backup data */ + + /* BKP_OCTL */ +-#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ ++#define BKP_OCTL_RCCV GD_BITS(0,6) /*!< RTC clock calibration value */ + #define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ + #define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ + #define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ @@ -122,7 +122,7 @@ OF SUCH DAMAGE. - #define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) - - /* RTC clock calibration value */ --#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -+#define OCTL_RCCV(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) - - /* RTC output selection */ - #define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ + #define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) + + /* RTC clock calibration value */ +-#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) ++#define OCTL_RCCV(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) + + /* RTC output selection */ + #define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_can.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_can.h old mode 100644 new mode 100755 @@ -236,218 +236,218 @@ index 1cdb401..284536c --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_can.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_can.h @@ -192,7 +192,7 @@ OF SUCH DAMAGE. - #define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ - #define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ - #define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ --#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ -+#define CAN_TSTAT_NUM GD_BITS(24,25) /*!< mailbox number */ - #define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ - #define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ - #define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ + #define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ + #define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ + #define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ +-#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ ++#define CAN_TSTAT_NUM GD_BITS(24,25) /*!< mailbox number */ + #define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ + #define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ + #define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ @@ -201,13 +201,13 @@ OF SUCH DAMAGE. - #define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ - - /* CAN_RFIFO0 */ --#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ -+#define CAN_RFIFO0_RFL0 GD_BITS(0,1) /*!< receive FIFO0 length */ - #define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ - #define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ - #define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ - - /* CAN_RFIFO1 */ --#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ -+#define CAN_RFIFO1_RFL1 GD_BITS(0,1) /*!< receive FIFO1 length */ - #define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ - #define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ - #define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ + #define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ + + /* CAN_RFIFO0 */ +-#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ ++#define CAN_RFIFO0_RFL0 GD_BITS(0,1) /*!< receive FIFO0 length */ + #define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ + #define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ + #define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ + + /* CAN_RFIFO1 */ +-#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ ++#define CAN_RFIFO1_RFL1 GD_BITS(0,1) /*!< receive FIFO1 length */ + #define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ + #define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ + #define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ @@ -232,15 +232,15 @@ OF SUCH DAMAGE. - #define CAN_ERR_WERR BIT(0) /*!< warning error */ - #define CAN_ERR_PERR BIT(1) /*!< passive error */ - #define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ --#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ --#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ --#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ -+#define CAN_ERR_ERRN GD_BITS(4,6) /*!< error number */ -+#define CAN_ERR_TECNT GD_BITS(16,23) /*!< transmit error count */ -+#define CAN_ERR_RECNT GD_BITS(24,31) /*!< receive error count */ - - /* CAN_BT */ --#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ --#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ --#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ --#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ -+#define CAN_BT_BAUDPSC GD_BITS(0,9) /*!< baudrate prescaler */ -+#define CAN_BT_BS1 GD_BITS(16,19) /*!< bit segment 1 */ -+#define CAN_BT_BS2 GD_BITS(20,22) /*!< bit segment 2 */ -+#define CAN_BT_SJW GD_BITS(24,25) /*!< resynchronization jump width */ - #define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ - #define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ - + #define CAN_ERR_WERR BIT(0) /*!< warning error */ + #define CAN_ERR_PERR BIT(1) /*!< passive error */ + #define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ +-#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ +-#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ +-#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ ++#define CAN_ERR_ERRN GD_BITS(4,6) /*!< error number */ ++#define CAN_ERR_TECNT GD_BITS(16,23) /*!< transmit error count */ ++#define CAN_ERR_RECNT GD_BITS(24,31) /*!< receive error count */ + + /* CAN_BT */ +-#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ +-#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ +-#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ +-#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ ++#define CAN_BT_BAUDPSC GD_BITS(0,9) /*!< baudrate prescaler */ ++#define CAN_BT_BS1 GD_BITS(16,19) /*!< bit segment 1 */ ++#define CAN_BT_BS2 GD_BITS(20,22) /*!< bit segment 2 */ ++#define CAN_BT_SJW GD_BITS(24,25) /*!< resynchronization jump width */ + #define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ + #define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ + @@ -248,52 +248,52 @@ OF SUCH DAMAGE. - #define CAN_TMI_TEN BIT(0) /*!< transmit enable */ - #define CAN_TMI_FT BIT(1) /*!< frame type */ - #define CAN_TMI_FF BIT(2) /*!< frame format */ --#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ --#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ -+#define CAN_TMI_EFID GD_BITS(3,31) /*!< the frame identifier */ -+#define CAN_TMI_SFID GD_BITS(21,31) /*!< the frame identifier */ - - /* CAN_TMPx */ --#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ -+#define CAN_TMP_DLENC GD_BITS(0,3) /*!< data length code */ - #define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ --#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ -+#define CAN_TMP_TS GD_BITS(16,31) /*!< time stamp */ - - /* CAN_TMDATA0x */ --#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ --#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ --#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ --#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ -+#define CAN_TMDATA0_DB0 GD_BITS(0,7) /*!< transmit data byte 0 */ -+#define CAN_TMDATA0_DB1 GD_BITS(8,15) /*!< transmit data byte 1 */ -+#define CAN_TMDATA0_DB2 GD_BITS(16,23) /*!< transmit data byte 2 */ -+#define CAN_TMDATA0_DB3 GD_BITS(24,31) /*!< transmit data byte 3 */ - - /* CAN_TMDATA1x */ --#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ --#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ --#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ --#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ -+#define CAN_TMDATA1_DB4 GD_BITS(0,7) /*!< transmit data byte 4 */ -+#define CAN_TMDATA1_DB5 GD_BITS(8,15) /*!< transmit data byte 5 */ -+#define CAN_TMDATA1_DB6 GD_BITS(16,23) /*!< transmit data byte 6 */ -+#define CAN_TMDATA1_DB7 GD_BITS(24,31) /*!< transmit data byte 7 */ - - /* CAN_RFIFOMIx */ - #define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ - #define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ --#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ --#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ -+#define CAN_RFIFOMI_EFID GD_BITS(3,31) /*!< the frame identifier */ -+#define CAN_RFIFOMI_SFID GD_BITS(21,31) /*!< the frame identifier */ - - /* CAN_RFIFOMPx */ --#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ --#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ --#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ -+#define CAN_RFIFOMP_DLENC GD_BITS(0,3) /*!< receive data length code */ -+#define CAN_RFIFOMP_FI GD_BITS(8,15) /*!< filter index */ -+#define CAN_RFIFOMP_TS GD_BITS(16,31) /*!< time stamp */ - - /* CAN_RFIFOMDATA0x */ --#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ --#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ --#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ --#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ -+#define CAN_RFIFOMDATA0_DB0 GD_BITS(0,7) /*!< receive data byte 0 */ -+#define CAN_RFIFOMDATA0_DB1 GD_BITS(8,15) /*!< receive data byte 1 */ -+#define CAN_RFIFOMDATA0_DB2 GD_BITS(16,23) /*!< receive data byte 2 */ -+#define CAN_RFIFOMDATA0_DB3 GD_BITS(24,31) /*!< receive data byte 3 */ - - /* CAN_RFIFOMDATA1x */ --#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ --#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ --#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ --#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ -+#define CAN_RFIFOMDATA1_DB4 GD_BITS(0,7) /*!< receive data byte 4 */ -+#define CAN_RFIFOMDATA1_DB5 GD_BITS(8,15) /*!< receive data byte 5 */ -+#define CAN_RFIFOMDATA1_DB6 GD_BITS(16,23) /*!< receive data byte 6 */ -+#define CAN_RFIFOMDATA1_DB7 GD_BITS(24,31) /*!< receive data byte 7 */ - - /* CAN_FCTL */ - #define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ --#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ -+#define CAN_FCTL_HBC1F GD_BITS(8,13) /*!< header bank of CAN1 filter */ - - /* CAN_FMCFG */ - #define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ + #define CAN_TMI_TEN BIT(0) /*!< transmit enable */ + #define CAN_TMI_FT BIT(1) /*!< frame type */ + #define CAN_TMI_FF BIT(2) /*!< frame format */ +-#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ +-#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ ++#define CAN_TMI_EFID GD_BITS(3,31) /*!< the frame identifier */ ++#define CAN_TMI_SFID GD_BITS(21,31) /*!< the frame identifier */ + + /* CAN_TMPx */ +-#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ ++#define CAN_TMP_DLENC GD_BITS(0,3) /*!< data length code */ + #define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ +-#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ ++#define CAN_TMP_TS GD_BITS(16,31) /*!< time stamp */ + + /* CAN_TMDATA0x */ +-#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ +-#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ +-#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ +-#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ ++#define CAN_TMDATA0_DB0 GD_BITS(0,7) /*!< transmit data byte 0 */ ++#define CAN_TMDATA0_DB1 GD_BITS(8,15) /*!< transmit data byte 1 */ ++#define CAN_TMDATA0_DB2 GD_BITS(16,23) /*!< transmit data byte 2 */ ++#define CAN_TMDATA0_DB3 GD_BITS(24,31) /*!< transmit data byte 3 */ + + /* CAN_TMDATA1x */ +-#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ +-#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ +-#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ +-#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ ++#define CAN_TMDATA1_DB4 GD_BITS(0,7) /*!< transmit data byte 4 */ ++#define CAN_TMDATA1_DB5 GD_BITS(8,15) /*!< transmit data byte 5 */ ++#define CAN_TMDATA1_DB6 GD_BITS(16,23) /*!< transmit data byte 6 */ ++#define CAN_TMDATA1_DB7 GD_BITS(24,31) /*!< transmit data byte 7 */ + + /* CAN_RFIFOMIx */ + #define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ + #define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ +-#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ +-#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ ++#define CAN_RFIFOMI_EFID GD_BITS(3,31) /*!< the frame identifier */ ++#define CAN_RFIFOMI_SFID GD_BITS(21,31) /*!< the frame identifier */ + + /* CAN_RFIFOMPx */ +-#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ +-#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ +-#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ ++#define CAN_RFIFOMP_DLENC GD_BITS(0,3) /*!< receive data length code */ ++#define CAN_RFIFOMP_FI GD_BITS(8,15) /*!< filter index */ ++#define CAN_RFIFOMP_TS GD_BITS(16,31) /*!< time stamp */ + + /* CAN_RFIFOMDATA0x */ +-#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ +-#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ +-#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ +-#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ ++#define CAN_RFIFOMDATA0_DB0 GD_BITS(0,7) /*!< receive data byte 0 */ ++#define CAN_RFIFOMDATA0_DB1 GD_BITS(8,15) /*!< receive data byte 1 */ ++#define CAN_RFIFOMDATA0_DB2 GD_BITS(16,23) /*!< receive data byte 2 */ ++#define CAN_RFIFOMDATA0_DB3 GD_BITS(24,31) /*!< receive data byte 3 */ + + /* CAN_RFIFOMDATA1x */ +-#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ +-#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ +-#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ +-#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ ++#define CAN_RFIFOMDATA1_DB4 GD_BITS(0,7) /*!< receive data byte 4 */ ++#define CAN_RFIFOMDATA1_DB5 GD_BITS(8,15) /*!< receive data byte 5 */ ++#define CAN_RFIFOMDATA1_DB6 GD_BITS(16,23) /*!< receive data byte 6 */ ++#define CAN_RFIFOMDATA1_DB7 GD_BITS(24,31) /*!< receive data byte 7 */ + + /* CAN_FCTL */ + #define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ +-#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ ++#define CAN_FCTL_HBC1F GD_BITS(8,13) /*!< header bank of CAN1 filter */ + + /* CAN_FMCFG */ + #define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ @@ -482,58 +482,58 @@ typedef enum - }can_struct_type_enum; - - /* CAN baudrate prescaler*/ --#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) -+#define BT_BAUDPSC(regval) (GD_BITS(0,9) & ((uint32_t)(regval) << 0)) - - /* CAN bit segment 1*/ --#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) -+#define BT_BS1(regval) (GD_BITS(16,19) & ((uint32_t)(regval) << 16)) - - /* CAN bit segment 2*/ --#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) -+#define BT_BS2(regval) (GD_BITS(20,22) & ((uint32_t)(regval) << 20)) - - /* CAN resynchronization jump width*/ --#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) -+#define BT_SJW(regval) (GD_BITS(24,25) & ((uint32_t)(regval) << 24)) - - /* CAN communication mode*/ --#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) -+#define BT_MODE(regval) (GD_BITS(30,31) & ((uint32_t)(regval) << 30)) - - /* CAN FDATA high 16 bits */ --#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) -+#define FDATA_MASK_HIGH(regval) (GD_BITS(16,31) & ((uint32_t)(regval) << 16)) - - /* CAN FDATA low 16 bits */ --#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -+#define FDATA_MASK_LOW(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) - - /* CAN1 filter start bank_number*/ --#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) -+#define FCTL_HBC1F(regval) (GD_BITS(8,13) & ((uint32_t)(regval) << 8)) - - /* CAN transmit mailbox extended identifier*/ --#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) -+#define TMI_EFID(regval) (GD_BITS(3,31) & ((uint32_t)(regval) << 3)) - - /* CAN transmit mailbox standard identifier*/ --#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) -+#define TMI_SFID(regval) (GD_BITS(21,31) & ((uint32_t)(regval) << 21)) - - /* transmit data byte 0 */ --#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) -+#define TMDATA0_DB0(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) - - /* transmit data byte 1 */ --#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) -+#define TMDATA0_DB1(regval) (GD_BITS(8,15) & ((uint32_t)(regval) << 8)) - - /* transmit data byte 2 */ --#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -+#define TMDATA0_DB2(regval) (GD_BITS(16,23) & ((uint32_t)(regval) << 16)) - - /* transmit data byte 3 */ --#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) -+#define TMDATA0_DB3(regval) (GD_BITS(24,31) & ((uint32_t)(regval) << 24)) - - /* transmit data byte 4 */ --#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) -+#define TMDATA1_DB4(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) - - /* transmit data byte 5 */ --#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) -+#define TMDATA1_DB5(regval) (GD_BITS(8,15) & ((uint32_t)(regval) << 8)) - - /* transmit data byte 6 */ --#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -+#define TMDATA1_DB6(regval) (GD_BITS(16,23) & ((uint32_t)(regval) << 16)) - - /* transmit data byte 7 */ --#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) -+#define TMDATA1_DB7(regval) (GD_BITS(24,31) & ((uint32_t)(regval) << 24)) - - /* receive mailbox extended identifier*/ - #define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) + }can_struct_type_enum; + + /* CAN baudrate prescaler*/ +-#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) ++#define BT_BAUDPSC(regval) (GD_BITS(0,9) & ((uint32_t)(regval) << 0)) + + /* CAN bit segment 1*/ +-#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) ++#define BT_BS1(regval) (GD_BITS(16,19) & ((uint32_t)(regval) << 16)) + + /* CAN bit segment 2*/ +-#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) ++#define BT_BS2(regval) (GD_BITS(20,22) & ((uint32_t)(regval) << 20)) + + /* CAN resynchronization jump width*/ +-#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) ++#define BT_SJW(regval) (GD_BITS(24,25) & ((uint32_t)(regval) << 24)) + + /* CAN communication mode*/ +-#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) ++#define BT_MODE(regval) (GD_BITS(30,31) & ((uint32_t)(regval) << 30)) + + /* CAN FDATA high 16 bits */ +-#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) ++#define FDATA_MASK_HIGH(regval) (GD_BITS(16,31) & ((uint32_t)(regval) << 16)) + + /* CAN FDATA low 16 bits */ +-#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) ++#define FDATA_MASK_LOW(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) + + /* CAN1 filter start bank_number*/ +-#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) ++#define FCTL_HBC1F(regval) (GD_BITS(8,13) & ((uint32_t)(regval) << 8)) + + /* CAN transmit mailbox extended identifier*/ +-#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) ++#define TMI_EFID(regval) (GD_BITS(3,31) & ((uint32_t)(regval) << 3)) + + /* CAN transmit mailbox standard identifier*/ +-#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) ++#define TMI_SFID(regval) (GD_BITS(21,31) & ((uint32_t)(regval) << 21)) + + /* transmit data byte 0 */ +-#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) ++#define TMDATA0_DB0(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) + + /* transmit data byte 1 */ +-#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) ++#define TMDATA0_DB1(regval) (GD_BITS(8,15) & ((uint32_t)(regval) << 8)) + + /* transmit data byte 2 */ +-#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) ++#define TMDATA0_DB2(regval) (GD_BITS(16,23) & ((uint32_t)(regval) << 16)) + + /* transmit data byte 3 */ +-#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) ++#define TMDATA0_DB3(regval) (GD_BITS(24,31) & ((uint32_t)(regval) << 24)) + + /* transmit data byte 4 */ +-#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) ++#define TMDATA1_DB4(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) + + /* transmit data byte 5 */ +-#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) ++#define TMDATA1_DB5(regval) (GD_BITS(8,15) & ((uint32_t)(regval) << 8)) + + /* transmit data byte 6 */ +-#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) ++#define TMDATA1_DB6(regval) (GD_BITS(16,23) & ((uint32_t)(regval) << 16)) + + /* transmit data byte 7 */ +-#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) ++#define TMDATA1_DB7(regval) (GD_BITS(24,31) & ((uint32_t)(regval) << 24)) + + /* receive mailbox extended identifier*/ + #define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) @@ -581,7 +581,7 @@ typedef enum - #define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) - - /* CAN errors */ --#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -+#define ERR_ERRN(regval) (GD_BITS(4,6) & ((uint32_t)(regval) << 4)) - #define CAN_ERRN_0 ERR_ERRN(0U) /* no error */ - #define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ - #define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ + #define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) + + /* CAN errors */ +-#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) ++#define ERR_ERRN(regval) (GD_BITS(4,6) & ((uint32_t)(regval) << 4)) + #define CAN_ERRN_0 ERR_ERRN(0U) /* no error */ + #define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ + #define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h old mode 100644 new mode 100755 @@ -455,18 +455,18 @@ index a92db6a..3d67f60 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h @@ -50,10 +50,10 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* CRC_DATA */ --#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ -+#define CRC_DATA_DATA GD_BITS(0,31) /*!< CRC calculation result bits */ - - /* CRC_FDATA */ --#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ -+#define CRC_FDATA_FDATA GD_BITS(0,7) /*!< CRC free data bits */ - - /* CRC_CTL */ - #define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ + + /* bits definitions */ + /* CRC_DATA */ +-#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ ++#define CRC_DATA_DATA GD_BITS(0,31) /*!< CRC calculation result bits */ + + /* CRC_FDATA */ +-#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ ++#define CRC_FDATA_FDATA GD_BITS(0,7) /*!< CRC free data bits */ + + /* CRC_CTL */ + #define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h old mode 100644 new mode 100755 @@ -474,49 +474,49 @@ index 2bda49f..c81fc58 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h @@ -58,13 +58,13 @@ OF SUCH DAMAGE. - #define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ - #define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ - #define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ --#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ -+#define CTC_CTL0_TRIMVALUE GD_BITS(8,13) /*!< IRC48M trim value */ - - /* CTC_CTL1 */ --#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ --#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ --#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ --#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ -+#define CTC_CTL1_RLVALUE GD_BITS(0,15) /*!< CTC counter reload value */ -+#define CTC_CTL1_CKLIM GD_BITS(16,23) /*!< clock trim base limit value */ -+#define CTC_CTL1_REFPSC GD_BITS(24,26) /*!< reference signal source prescaler */ -+#define CTC_CTL1_REFSEL GD_BITS(28,29) /*!< reference signal source selection */ - #define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ - - /* CTC_STAT */ + #define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ + #define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ + #define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ +-#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ ++#define CTC_CTL0_TRIMVALUE GD_BITS(8,13) /*!< IRC48M trim value */ + + /* CTC_CTL1 */ +-#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ +-#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ +-#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ +-#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ ++#define CTC_CTL1_RLVALUE GD_BITS(0,15) /*!< CTC counter reload value */ ++#define CTC_CTL1_CKLIM GD_BITS(16,23) /*!< clock trim base limit value */ ++#define CTC_CTL1_REFPSC GD_BITS(24,26) /*!< reference signal source prescaler */ ++#define CTC_CTL1_REFSEL GD_BITS(28,29) /*!< reference signal source selection */ + #define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ + + /* CTC_STAT */ @@ -76,7 +76,7 @@ OF SUCH DAMAGE. - #define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ - #define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ - #define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ --#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ -+#define CTC_STAT_REFCAP GD_BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ - - /* CTC_INTC */ - #define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ + #define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ + #define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ + #define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ +-#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ ++#define CTC_STAT_REFCAP GD_BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ + + /* CTC_INTC */ + #define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ @@ -94,13 +94,13 @@ OF SUCH DAMAGE. - #define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ - - /* reference signal source selection definitions */ --#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -+#define CTL1_REFSEL(regval) (GD_BITS(28,29) & ((uint32_t)(regval) << 28)) - #define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ - #define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is selected */ - #define CTC_REFSOURCE_USB_SOF CTL1_REFSEL(2) /*!< USBD_SOF or USBFS_SOF is selected */ - - /* reference signal source prescaler definitions */ --#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) -+#define CTL1_REFPSC(regval) (GD_BITS(24,26) & ((uint32_t)(regval) << 24)) - #define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ - #define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ - #define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ + #define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ + + /* reference signal source selection definitions */ +-#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) ++#define CTL1_REFSEL(regval) (GD_BITS(28,29) & ((uint32_t)(regval) << 28)) + #define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ + #define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is selected */ + #define CTC_REFSOURCE_USB_SOF CTL1_REFSEL(2) /*!< USBD_SOF or USBFS_SOF is selected */ + + /* reference signal source prescaler definitions */ +-#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) ++#define CTL1_REFPSC(regval) (GD_BITS(24,26) & ((uint32_t)(regval) << 24)) + #define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ + #define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ + #define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h old mode 100644 new mode 100755 @@ -524,113 +524,113 @@ index 8563095..365004d --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h @@ -65,16 +65,16 @@ OF SUCH DAMAGE. - #define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ - #define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ - #define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ --#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ --#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ --#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ -+#define DAC_CTL_DTSEL0 GD_BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ -+#define DAC_CTL_DWM0 GD_BITS(6,7) /*!< DAC0 noise wave mode */ -+#define DAC_CTL_DWBW0 GD_BITS(8,11) /*!< DAC0 noise wave bit width */ - #define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ - #define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ - #define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ - #define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ --#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ --#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ --#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ -+#define DAC_CTL_DTSEL1 GD_BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ -+#define DAC_CTL_DWM1 GD_BITS(22,23) /*!< DAC1 noise wave mode */ -+#define DAC_CTL_DWBW1 GD_BITS(24,27) /*!< DAC1 noise wave bit width */ - #define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ - - /* DAC_SWT */ + #define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ + #define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ + #define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +-#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +-#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +-#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ ++#define DAC_CTL_DTSEL0 GD_BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ ++#define DAC_CTL_DWM0 GD_BITS(6,7) /*!< DAC0 noise wave mode */ ++#define DAC_CTL_DWBW0 GD_BITS(8,11) /*!< DAC0 noise wave bit width */ + #define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ + #define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ + #define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ + #define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +-#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +-#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +-#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ ++#define DAC_CTL_DTSEL1 GD_BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ ++#define DAC_CTL_DWM1 GD_BITS(22,23) /*!< DAC1 noise wave mode */ ++#define DAC_CTL_DWBW1 GD_BITS(24,27) /*!< DAC1 noise wave bit width */ + #define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ + + /* DAC_SWT */ @@ -82,44 +82,44 @@ OF SUCH DAMAGE. - #define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ - - /* DAC0_R12DH */ --#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ -+#define DAC0_R12DH_DAC0_DH GD_BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ - - /* DAC0_L12DH */ --#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ -+#define DAC0_L12DH_DAC0_DH GD_BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ - - /* DAC0_R8DH */ --#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ -+#define DAC0_R8DH_DAC0_DH GD_BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ - - /* DAC1_R12DH */ --#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ -+#define DAC1_R12DH_DAC1_DH GD_BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ - - /* DAC1_L12DH */ --#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ -+#define DAC1_L12DH_DAC1_DH GD_BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ - - /* DAC1_R8DH */ --#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ -+#define DAC1_R8DH_DAC1_DH GD_BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ - - /* DACC_R12DH */ --#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ --#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ -+#define DACC_R12DH_DAC0_DH GD_BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ -+#define DACC_R12DH_DAC1_DH GD_BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ - - /* DACC_L12DH */ --#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ --#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ -+#define DACC_L12DH_DAC0_DH GD_BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ -+#define DACC_L12DH_DAC1_DH GD_BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ - - /* DACC_R8DH */ --#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ --#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ -+#define DACC_R8DH_DAC0_DH GD_BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ -+#define DACC_R8DH_DAC1_DH GD_BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ - - /* DAC0_DO */ --#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ -+#define DAC0_DO_DAC0_DO GD_BITS(0,11) /*!< DAC0 12-bit output data bits */ - - /* DAC1_DO */ --#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ -+#define DAC1_DO_DAC1_DO GD_BITS(0,11) /*!< DAC1 12-bit output data bits */ - - /* constants definitions */ - /* DAC trigger source */ --#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -+#define CTL_DTSEL(regval) (GD_BITS(3,5) & ((uint32_t)(regval) << 3)) - #define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ - #if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - #define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ + #define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ + + /* DAC0_R12DH */ +-#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ ++#define DAC0_R12DH_DAC0_DH GD_BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ + + /* DAC0_L12DH */ +-#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ ++#define DAC0_L12DH_DAC0_DH GD_BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ + + /* DAC0_R8DH */ +-#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ ++#define DAC0_R8DH_DAC0_DH GD_BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ + + /* DAC1_R12DH */ +-#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ ++#define DAC1_R12DH_DAC1_DH GD_BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ + + /* DAC1_L12DH */ +-#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ ++#define DAC1_L12DH_DAC1_DH GD_BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ + + /* DAC1_R8DH */ +-#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ ++#define DAC1_R8DH_DAC1_DH GD_BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ + + /* DACC_R12DH */ +-#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +-#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ ++#define DACC_R12DH_DAC0_DH GD_BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ ++#define DACC_R12DH_DAC1_DH GD_BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ + + /* DACC_L12DH */ +-#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +-#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ ++#define DACC_L12DH_DAC0_DH GD_BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ ++#define DACC_L12DH_DAC1_DH GD_BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ + + /* DACC_R8DH */ +-#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +-#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ ++#define DACC_R8DH_DAC0_DH GD_BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ ++#define DACC_R8DH_DAC1_DH GD_BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ + + /* DAC0_DO */ +-#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ ++#define DAC0_DO_DAC0_DO GD_BITS(0,11) /*!< DAC0 12-bit output data bits */ + + /* DAC1_DO */ +-#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ ++#define DAC1_DO_DAC1_DO GD_BITS(0,11) /*!< DAC1 12-bit output data bits */ + + /* constants definitions */ + /* DAC trigger source */ +-#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) ++#define CTL_DTSEL(regval) (GD_BITS(3,5) & ((uint32_t)(regval) << 3)) + #define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ + #if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + #define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ @@ -134,13 +134,13 @@ OF SUCH DAMAGE. - #define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ - - /* DAC noise wave mode */ --#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -+#define CTL_DWM(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6)) - #define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ - #define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ - #define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ - - /* DAC noise wave bit width */ --#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -+#define DWBW(regval) (GD_BITS(8,11) & ((uint32_t)(regval) << 8)) - #define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ - #define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ - #define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ + #define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ + + /* DAC noise wave mode */ +-#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) ++#define CTL_DWM(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6)) + #define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ + #define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ + #define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ + + /* DAC noise wave bit width */ +-#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) ++#define DWBW(regval) (GD_BITS(8,11) & ((uint32_t)(regval) << 8)) + #define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ + #define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ + #define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ @@ -169,7 +169,7 @@ OF SUCH DAMAGE. - #define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ - - /* DAC data alignment */ --#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -+#define DATA_ALIGN(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) - #define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */ - #define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */ - #define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */ + #define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + + /* DAC data alignment */ +-#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) ++#define DATA_ALIGN(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) + #define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */ + #define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */ + #define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h old mode 100644 new mode 100755 @@ -638,31 +638,31 @@ index f4c616f..920fa6b --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h @@ -49,14 +49,14 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* DBG_ID */ --#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ -+#define DBG_ID_ID_CODE GD_BITS(0,31) /*!< DBG ID code values */ - - /* DBG_CTL0 */ - #define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ - #define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ - #define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ - #define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ --#define DBG_CTL0_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ -+#define DBG_CTL0_TRACE_MODE GD_BITS(6,7) /*!< trace pin mode selection */ - #define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ - #define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ - #define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ + + /* bits definitions */ + /* DBG_ID */ +-#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ ++#define DBG_ID_ID_CODE GD_BITS(0,31) /*!< DBG ID code values */ + + /* DBG_CTL0 */ + #define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ + #define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ + #define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ + #define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ +-#define DBG_CTL0_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ ++#define DBG_CTL0_TRACE_MODE GD_BITS(6,7) /*!< trace pin mode selection */ + #define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ + #define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ + #define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ @@ -126,7 +126,7 @@ typedef enum - #endif /* GD32F30X_HD */ - }dbg_periph_enum; - --#define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6)) -+#define CTL0_TRACE_MODE(regval) (GD_BITS(6,7)&((uint32_t)(regval)<<6)) - #define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */ - #define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ - #define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ + #endif /* GD32F30X_HD */ + }dbg_periph_enum; + +-#define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6)) ++#define CTL0_TRACE_MODE(regval) (GD_BITS(6,7)&((uint32_t)(regval)<<6)) + #define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */ + #define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ + #define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h old mode 100644 new mode 100755 @@ -670,54 +670,54 @@ index bda4787..ebd3d98 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h @@ -105,19 +105,19 @@ OF SUCH DAMAGE. - #define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ - #define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ - #define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ --#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ --#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ --#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ -+#define DMA_CHXCTL_PWIDTH GD_BITS(8,9) /*!< transfer data width of peripheral */ -+#define DMA_CHXCTL_MWIDTH GD_BITS(10,11) /*!< transfer data width of memory */ -+#define DMA_CHXCTL_PRIO GD_BITS(12,13) /*!< priority level */ - #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ - - /* DMA_CHxCNT,x=0..6 */ --#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ -+#define DMA_CHXCNT_CNT GD_BITS(0,15) /*!< transfer counter */ - - /* DMA_CHxPADDR,x=0..6 */ --#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ -+#define DMA_CHXPADDR_PADDR GD_BITS(0,31) /*!< peripheral base address */ - - /* DMA_CHxMADDR,x=0..6 */ --#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ -+#define DMA_CHXMADDR_MADDR GD_BITS(0,31) /*!< memory base address */ - - /* constants definitions */ - /* DMA channel select */ + #define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ + #define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ + #define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ +-#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ +-#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ +-#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ ++#define DMA_CHXCTL_PWIDTH GD_BITS(8,9) /*!< transfer data width of peripheral */ ++#define DMA_CHXCTL_MWIDTH GD_BITS(10,11) /*!< transfer data width of memory */ ++#define DMA_CHXCTL_PRIO GD_BITS(12,13) /*!< priority level */ + #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ + + /* DMA_CHxCNT,x=0..6 */ +-#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ ++#define DMA_CHXCNT_CNT GD_BITS(0,15) /*!< transfer counter */ + + /* DMA_CHxPADDR,x=0..6 */ +-#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ ++#define DMA_CHXPADDR_PADDR GD_BITS(0,31) /*!< peripheral base address */ + + /* DMA_CHxMADDR,x=0..6 */ +-#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ ++#define DMA_CHXMADDR_MADDR GD_BITS(0,31) /*!< memory base address */ + + /* constants definitions */ + /* DMA channel select */ @@ -195,19 +195,19 @@ typedef struct - #define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of memory is increasing address mode */ - - /* transfer data size of peripheral */ --#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ -+#define CHCTL_PWIDTH(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ - #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */ - #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */ - #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */ - - /* transfer data size of memory */ --#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ -+#define CHCTL_MWIDTH(regval) (GD_BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ - #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */ - #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */ - #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */ - - /* channel priority level */ --#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ -+#define CHCTL_PRIO(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ - #define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ - #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ - #define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ + #define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of memory is increasing address mode */ + + /* transfer data size of peripheral */ +-#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ ++#define CHCTL_PWIDTH(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ + #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */ + #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */ + #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */ + + /* transfer data size of memory */ +-#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ ++#define CHCTL_MWIDTH(regval) (GD_BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ + #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */ + #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */ + #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */ + + /* channel priority level */ +-#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ ++#define CHCTL_PRIO(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ + #define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ + #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ + #define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h old mode 100644 new mode 100755 @@ -725,645 +725,645 @@ index aa76ec2..feddb7e --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h @@ -186,7 +186,7 @@ OF SUCH DAMAGE. - #define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */ - #define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */ - #define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */ --#define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */ -+#define ENET_MAC_CFG_BOL GD_BITS(5,6) /*!< back-off limit */ - #define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */ - #define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */ - #define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */ + #define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */ + #define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */ + #define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */ +-#define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */ ++#define ENET_MAC_CFG_BOL GD_BITS(5,6) /*!< back-off limit */ + #define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */ + #define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */ + #define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */ @@ -195,7 +195,7 @@ OF SUCH DAMAGE. - #define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ - #define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ - #define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ --#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ -+#define ENET_MAC_CFG_IGBS GD_BITS(17,19) /*!< inter-frame gap bit selection */ - #define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ - #define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ - #define ENET_MAC_CFG_TFCD BIT(25) /*!< type frame CRC dropping */ + #define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ + #define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ + #define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ +-#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ ++#define ENET_MAC_CFG_IGBS GD_BITS(17,19) /*!< inter-frame gap bit selection */ + #define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ + #define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ + #define ENET_MAC_CFG_TFCD BIT(25) /*!< type frame CRC dropping */ @@ -207,43 +207,43 @@ OF SUCH DAMAGE. - #define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ - #define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ - #define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ --#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ -+#define ENET_MAC_FRMF_PCFRM GD_BITS(6,7) /*!< pass control frames */ - #define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ - #define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ - #define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ - #define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ - - /* ENET_MAC_HLH */ --#define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ -+#define ENET_MAC_HLH_HLH GD_BITS(0,31) /*!< hash list high */ - - /* ENET_MAC_HLL */ --#define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ -+#define ENET_MAC_HLL_HLL GD_BITS(0,31) /*!< hash list low */ - - /* ENET_MAC_PHY_CTL */ - #define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ - #define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ --#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ --#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ --#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ -+#define ENET_MAC_PHY_CTL_CLR GD_BITS(2,4) /*!< clock range */ -+#define ENET_MAC_PHY_CTL_PR GD_BITS(6,10) /*!< PHY register */ -+#define ENET_MAC_PHY_CTL_PA GD_BITS(11,15) /*!< PHY address */ - - /* ENET_MAC_PHY_DATA */ --#define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ -+#define ENET_MAC_PHY_DATA_PD GD_BITS(0,15) /*!< PHY data */ - - /* ENET_MAC_FCTL */ - #define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ - #define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ - #define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ - #define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ --#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ -+#define ENET_MAC_FCTL_PLTS GD_BITS(4,5) /*!< pause low threshold */ - #define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ --#define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ -+#define ENET_MAC_FCTL_PTM GD_BITS(16,31) /*!< pause time */ - - /* ENET_MAC_VLT */ --#define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ -+#define ENET_MAC_VLT_VLTI GD_BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ - #define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ - - /* ENET_MAC_RWFF */ --#define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ -+#define ENET_MAC_RWFF_DATA GD_BITS(0,31) /*!< wakeup frame filter register data */ - - /* ENET_MAC_WUM */ - #define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ + #define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ + #define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ + #define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ +-#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ ++#define ENET_MAC_FRMF_PCFRM GD_BITS(6,7) /*!< pass control frames */ + #define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ + #define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ + #define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ + #define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ + + /* ENET_MAC_HLH */ +-#define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ ++#define ENET_MAC_HLH_HLH GD_BITS(0,31) /*!< hash list high */ + + /* ENET_MAC_HLL */ +-#define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ ++#define ENET_MAC_HLL_HLL GD_BITS(0,31) /*!< hash list low */ + + /* ENET_MAC_PHY_CTL */ + #define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ + #define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ +-#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ +-#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ +-#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ ++#define ENET_MAC_PHY_CTL_CLR GD_BITS(2,4) /*!< clock range */ ++#define ENET_MAC_PHY_CTL_PR GD_BITS(6,10) /*!< PHY register */ ++#define ENET_MAC_PHY_CTL_PA GD_BITS(11,15) /*!< PHY address */ + + /* ENET_MAC_PHY_DATA */ +-#define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ ++#define ENET_MAC_PHY_DATA_PD GD_BITS(0,15) /*!< PHY data */ + + /* ENET_MAC_FCTL */ + #define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ + #define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ + #define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ + #define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ +-#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ ++#define ENET_MAC_FCTL_PLTS GD_BITS(4,5) /*!< pause low threshold */ + #define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ +-#define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ ++#define ENET_MAC_FCTL_PTM GD_BITS(16,31) /*!< pause time */ + + /* ENET_MAC_VLT */ +-#define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ ++#define ENET_MAC_VLT_VLTI GD_BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ + #define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ + + /* ENET_MAC_RWFF */ +-#define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ ++#define ENET_MAC_RWFF_DATA GD_BITS(0,31) /*!< wakeup frame filter register data */ + + /* ENET_MAC_WUM */ + #define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ @@ -256,14 +256,14 @@ OF SUCH DAMAGE. - - /* ENET_MAC_DBG */ - #define ENET_MAC_DBG_MRNI BIT(0) /*!< MAC receive state not idle */ --#define ENET_MAC_DBG_RXAFS BITS(1,2) /*!< Rx asynchronous FIFO status */ -+#define ENET_MAC_DBG_RXAFS GD_BITS(1,2) /*!< Rx asynchronous FIFO status */ - #define ENET_MAC_DBG_RXFW BIT(4) /*!< RxFIFO is writing */ --#define ENET_MAC_DBG_RXFRS BITS(5,6) /*!< RxFIFO read operation status */ --#define ENET_MAC_DBG_RXFS BITS(8,9) /*!< RxFIFO state */ -+#define ENET_MAC_DBG_RXFRS GD_BITS(5,6) /*!< RxFIFO read operation status */ -+#define ENET_MAC_DBG_RXFS GD_BITS(8,9) /*!< RxFIFO state */ - #define ENET_MAC_DBG_MTNI BIT(16) /*!< MAC transmit state not idle */ --#define ENET_MAC_DBG_SOMT BITS(17,18) /*!< status of mac transmitter */ -+#define ENET_MAC_DBG_SOMT GD_BITS(17,18) /*!< status of mac transmitter */ - #define ENET_MAC_DBG_PCS BIT(19) /*!< pause condition status */ --#define ENET_MAC_DBG_TXFRS BITS(20,21) /*!< TxFIFO read operation status */ -+#define ENET_MAC_DBG_TXFRS GD_BITS(20,21) /*!< TxFIFO read operation status */ - #define ENET_MAC_DBG_TXFW BIT(22) /*!< TxFIFO is writing */ - #define ENET_MAC_DBG_TXFNE BIT(24) /*!< TxFIFO not empty flag */ - #define ENET_MAC_DBG_TXFF BIT(25) /*!< TxFIFO full flag */ + + /* ENET_MAC_DBG */ + #define ENET_MAC_DBG_MRNI BIT(0) /*!< MAC receive state not idle */ +-#define ENET_MAC_DBG_RXAFS BITS(1,2) /*!< Rx asynchronous FIFO status */ ++#define ENET_MAC_DBG_RXAFS GD_BITS(1,2) /*!< Rx asynchronous FIFO status */ + #define ENET_MAC_DBG_RXFW BIT(4) /*!< RxFIFO is writing */ +-#define ENET_MAC_DBG_RXFRS BITS(5,6) /*!< RxFIFO read operation status */ +-#define ENET_MAC_DBG_RXFS BITS(8,9) /*!< RxFIFO state */ ++#define ENET_MAC_DBG_RXFRS GD_BITS(5,6) /*!< RxFIFO read operation status */ ++#define ENET_MAC_DBG_RXFS GD_BITS(8,9) /*!< RxFIFO state */ + #define ENET_MAC_DBG_MTNI BIT(16) /*!< MAC transmit state not idle */ +-#define ENET_MAC_DBG_SOMT BITS(17,18) /*!< status of mac transmitter */ ++#define ENET_MAC_DBG_SOMT GD_BITS(17,18) /*!< status of mac transmitter */ + #define ENET_MAC_DBG_PCS BIT(19) /*!< pause condition status */ +-#define ENET_MAC_DBG_TXFRS BITS(20,21) /*!< TxFIFO read operation status */ ++#define ENET_MAC_DBG_TXFRS GD_BITS(20,21) /*!< TxFIFO read operation status */ + #define ENET_MAC_DBG_TXFW BIT(22) /*!< TxFIFO is writing */ + #define ENET_MAC_DBG_TXFNE BIT(24) /*!< TxFIFO not empty flag */ + #define ENET_MAC_DBG_TXFF BIT(25) /*!< TxFIFO full flag */ @@ -280,42 +280,42 @@ OF SUCH DAMAGE. - #define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */ - - /* ENET_MAC_ADDR0H */ --#define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ -+#define ENET_MAC_ADDR0H_ADDR0H GD_BITS(0,15) /*!< MAC address0 high */ - #define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ - - /* ENET_MAC_ADDR0L */ --#define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ -+#define ENET_MAC_ADDR0L_ADDR0L GD_BITS(0,31) /*!< MAC address0 low */ - - /* ENET_MAC_ADDR1H */ --#define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ --#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ -+#define ENET_MAC_ADDR1H_ADDR1H GD_BITS(0,15) /*!< MAC address1 high */ -+#define ENET_MAC_ADDR1H_MB GD_BITS(24,29) /*!< mask byte */ - #define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ - #define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ - - /* ENET_MAC_ADDR1L */ --#define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ -+#define ENET_MAC_ADDR1L_ADDR1L GD_BITS(0,31) /*!< MAC address1 low */ - - /* ENET_MAC_ADDR2H */ --#define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ --#define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ -+#define ENET_MAC_ADDR2H_ADDR2H GD_BITS(0,15) /*!< MAC address2 high */ -+#define ENET_MAC_ADDR2H_MB GD_BITS(24,29) /*!< mask byte */ - #define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ - #define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ - - /* ENET_MAC_ADDR2L */ --#define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ -+#define ENET_MAC_ADDR2L_ADDR2L GD_BITS(0,31) /*!< MAC address2 low */ - - /* ENET_MAC_ADDR3H */ --#define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ --#define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ -+#define ENET_MAC_ADDR3H_ADDR3H GD_BITS(0,15) /*!< MAC address3 high */ -+#define ENET_MAC_ADDR3H_MB GD_BITS(24,29) /*!< mask byte */ - #define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */ - #define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */ - - /* ENET_MAC_ADDR3L */ --#define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ -+#define ENET_MAC_ADDR3L_ADDR3L GD_BITS(0,31) /*!< MAC address3 low */ - - /* ENET_MAC_FCTH */ --#define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ --#define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ -+#define ENET_MAC_FCTH_RFA GD_BITS(0,2) /*!< threshold of active flow control */ -+#define ENET_MAC_FCTH_RFD GD_BITS(4,6) /*!< threshold of deactive flow control */ - - /* ENET_MSC_CTL */ - #define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ + #define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */ + + /* ENET_MAC_ADDR0H */ +-#define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ ++#define ENET_MAC_ADDR0H_ADDR0H GD_BITS(0,15) /*!< MAC address0 high */ + #define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ + + /* ENET_MAC_ADDR0L */ +-#define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ ++#define ENET_MAC_ADDR0L_ADDR0L GD_BITS(0,31) /*!< MAC address0 low */ + + /* ENET_MAC_ADDR1H */ +-#define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ +-#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ ++#define ENET_MAC_ADDR1H_ADDR1H GD_BITS(0,15) /*!< MAC address1 high */ ++#define ENET_MAC_ADDR1H_MB GD_BITS(24,29) /*!< mask byte */ + #define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ + #define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ + + /* ENET_MAC_ADDR1L */ +-#define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ ++#define ENET_MAC_ADDR1L_ADDR1L GD_BITS(0,31) /*!< MAC address1 low */ + + /* ENET_MAC_ADDR2H */ +-#define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ +-#define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ ++#define ENET_MAC_ADDR2H_ADDR2H GD_BITS(0,15) /*!< MAC address2 high */ ++#define ENET_MAC_ADDR2H_MB GD_BITS(24,29) /*!< mask byte */ + #define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ + #define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ + + /* ENET_MAC_ADDR2L */ +-#define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ ++#define ENET_MAC_ADDR2L_ADDR2L GD_BITS(0,31) /*!< MAC address2 low */ + + /* ENET_MAC_ADDR3H */ +-#define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ +-#define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ ++#define ENET_MAC_ADDR3H_ADDR3H GD_BITS(0,15) /*!< MAC address3 high */ ++#define ENET_MAC_ADDR3H_MB GD_BITS(24,29) /*!< mask byte */ + #define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */ + #define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */ + + /* ENET_MAC_ADDR3L */ +-#define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ ++#define ENET_MAC_ADDR3L_ADDR3L GD_BITS(0,31) /*!< MAC address3 low */ + + /* ENET_MAC_FCTH */ +-#define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ +-#define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ ++#define ENET_MAC_FCTH_RFA GD_BITS(0,2) /*!< threshold of active flow control */ ++#define ENET_MAC_FCTH_RFD GD_BITS(4,6) /*!< threshold of deactive flow control */ + + /* ENET_MSC_CTL */ + #define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ @@ -346,22 +346,22 @@ OF SUCH DAMAGE. - #define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ - - /* ENET_MSC_SCCNT */ --#define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ -+#define ENET_MSC_SCCNT_SCC GD_BITS(0,31) /*!< transmitted good frames single collision counter */ - - /* ENET_MSC_MSCCNT */ --#define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ -+#define ENET_MSC_MSCCNT_MSCC GD_BITS(0,31) /*!< transmitted good frames more one single collision counter */ - - /* ENET_MSC_TGFCNT */ --#define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ -+#define ENET_MSC_TGFCNT_TGF GD_BITS(0,31) /*!< transmitted good frames counter */ - - /* ENET_MSC_RFCECNT */ --#define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ -+#define ENET_MSC_RFCECNT_RFCER GD_BITS(0,31) /*!< received frames with CRC error counter */ - - /* ENET_MSC_RFAECNT */ --#define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ -+#define ENET_MSC_RFAECNT_RFAER GD_BITS(0,31) /*!< received frames alignment error counter */ - - /* ENET_MSC_RGUFCNT */ --#define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ -+#define ENET_MSC_RGUFCNT_RGUF GD_BITS(0,31) /*!< received good unicast frames counter */ - - /* ENET_PTP_TSCTL */ - #define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */ + #define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ + + /* ENET_MSC_SCCNT */ +-#define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ ++#define ENET_MSC_SCCNT_SCC GD_BITS(0,31) /*!< transmitted good frames single collision counter */ + + /* ENET_MSC_MSCCNT */ +-#define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ ++#define ENET_MSC_MSCCNT_MSCC GD_BITS(0,31) /*!< transmitted good frames more one single collision counter */ + + /* ENET_MSC_TGFCNT */ +-#define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ ++#define ENET_MSC_TGFCNT_TGF GD_BITS(0,31) /*!< transmitted good frames counter */ + + /* ENET_MSC_RFCECNT */ +-#define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ ++#define ENET_MSC_RFCECNT_RFCER GD_BITS(0,31) /*!< received frames with CRC error counter */ + + /* ENET_MSC_RFAECNT */ +-#define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ ++#define ENET_MSC_RFAECNT_RFAER GD_BITS(0,31) /*!< received frames alignment error counter */ + + /* ENET_MSC_RGUFCNT */ +-#define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ ++#define ENET_MSC_RGUFCNT_RGUF GD_BITS(0,31) /*!< received good unicast frames counter */ + + /* ENET_PTP_TSCTL */ + #define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */ @@ -378,67 +378,67 @@ OF SUCH DAMAGE. - #define ENET_PTP_TSCTL_IP4SEN BIT(13) /*!< received IPv4 snapshot enable */ - #define ENET_PTP_TSCTL_ETMSEN BIT(14) /*!< received event type message snapshot enable */ - #define ENET_PTP_TSCTL_MNMSEN BIT(15) /*!< received master node message snapshot enable */ --#define ENET_PTP_TSCTL_CKNT BITS(16,17) /*!< clock node type for time stamp */ -+#define ENET_PTP_TSCTL_CKNT GD_BITS(16,17) /*!< clock node type for time stamp */ - #define ENET_PTP_TSCTL_MAFEN BIT(18) /*!< MAC address filter enable for PTP frame */ - - /* ENET_PTP_SSINC */ --#define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ -+#define ENET_PTP_SSINC_STMSSI GD_BITS(0,7) /*!< system time subsecond increment */ - - /* ENET_PTP_TSH */ --#define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ -+#define ENET_PTP_TSH_STMS GD_BITS(0,31) /*!< system time second */ - - /* ENET_PTP_TSL */ --#define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ -+#define ENET_PTP_TSL_STMSS GD_BITS(0,30) /*!< system time subseconds */ - #define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ - - /* ENET_PTP_TSUH */ --#define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ -+#define ENET_PTP_TSUH_TMSUS GD_BITS(0,31) /*!< timestamp update seconds */ - - /* ENET_PTP_TSUL */ --#define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ -+#define ENET_PTP_TSUL_TMSUSS GD_BITS(0,30) /*!< timestamp update subseconds */ - #define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ - - /* ENET_PTP_TSADDEND */ --#define ENET_PTP_TSADDEND_TMSA BITS(0,31) /*!< timestamp addend */ -+#define ENET_PTP_TSADDEND_TMSA GD_BITS(0,31) /*!< timestamp addend */ - - /* ENET_PTP_ETH */ --#define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ -+#define ENET_PTP_ETH_ETSH GD_BITS(0,31) /*!< expected time high */ - - /* ENET_PTP_ETL */ --#define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ -+#define ENET_PTP_ETL_ETSL GD_BITS(0,31) /*!< expected time low */ - - /* ENET_PTP_TSF */ - #define ENET_PTP_TSF_TSSCO BIT(0) /*!< timestamp second counter overflow */ - #define ENET_PTP_TSF_TTM BIT(1) /*!< target time match */ - - /* ENET_PTP_PPSCTL */ --#define ENET_PTP_PPSCTL_PPSOFC BITS(0,3) /*!< PPS output frequency configure */ -+#define ENET_PTP_PPSCTL_PPSOFC GD_BITS(0,3) /*!< PPS output frequency configure */ - - /* ENET_DMA_BCTL */ - #define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */ - #define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */ --#define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */ -+#define ENET_DMA_BCTL_DPSL GD_BITS(2,6) /*!< descriptor skip length */ - #define ENET_DMA_BCTL_DFM BIT(7) /*!< descriptor format mode */ --#define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */ --#define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ -+#define ENET_DMA_BCTL_PGBL GD_BITS(8,13) /*!< programmable burst length */ -+#define ENET_DMA_BCTL_RTPR GD_BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ - #define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */ --#define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */ -+#define ENET_DMA_BCTL_RXDP GD_BITS(17,22) /*!< RxDMA PGBL */ - #define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */ - #define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ - #define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ - #define ENET_DMA_BCTL_MB BIT(26) /*!< mixed burst */ - - /* ENET_DMA_TPEN */ --#define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ -+#define ENET_DMA_TPEN_TPE GD_BITS(0,31) /*!< transmit poll enable */ - - /* ENET_DMA_RPEN */ --#define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ -+#define ENET_DMA_RPEN_RPE GD_BITS(0,31) /*!< receive poll enable */ - - /* ENET_DMA_RDTADDR */ --#define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ -+#define ENET_DMA_RDTADDR_SRT GD_BITS(0,31) /*!< start address of receive table */ - - /* ENET_DMA_TDTADDR */ --#define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ -+#define ENET_DMA_TDTADDR_STT GD_BITS(0,31) /*!< start address of transmit table */ - - /* ENET_DMA_STAT */ - #define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ + #define ENET_PTP_TSCTL_IP4SEN BIT(13) /*!< received IPv4 snapshot enable */ + #define ENET_PTP_TSCTL_ETMSEN BIT(14) /*!< received event type message snapshot enable */ + #define ENET_PTP_TSCTL_MNMSEN BIT(15) /*!< received master node message snapshot enable */ +-#define ENET_PTP_TSCTL_CKNT BITS(16,17) /*!< clock node type for time stamp */ ++#define ENET_PTP_TSCTL_CKNT GD_BITS(16,17) /*!< clock node type for time stamp */ + #define ENET_PTP_TSCTL_MAFEN BIT(18) /*!< MAC address filter enable for PTP frame */ + + /* ENET_PTP_SSINC */ +-#define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ ++#define ENET_PTP_SSINC_STMSSI GD_BITS(0,7) /*!< system time subsecond increment */ + + /* ENET_PTP_TSH */ +-#define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ ++#define ENET_PTP_TSH_STMS GD_BITS(0,31) /*!< system time second */ + + /* ENET_PTP_TSL */ +-#define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ ++#define ENET_PTP_TSL_STMSS GD_BITS(0,30) /*!< system time subseconds */ + #define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ + + /* ENET_PTP_TSUH */ +-#define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ ++#define ENET_PTP_TSUH_TMSUS GD_BITS(0,31) /*!< timestamp update seconds */ + + /* ENET_PTP_TSUL */ +-#define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ ++#define ENET_PTP_TSUL_TMSUSS GD_BITS(0,30) /*!< timestamp update subseconds */ + #define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ + + /* ENET_PTP_TSADDEND */ +-#define ENET_PTP_TSADDEND_TMSA BITS(0,31) /*!< timestamp addend */ ++#define ENET_PTP_TSADDEND_TMSA GD_BITS(0,31) /*!< timestamp addend */ + + /* ENET_PTP_ETH */ +-#define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ ++#define ENET_PTP_ETH_ETSH GD_BITS(0,31) /*!< expected time high */ + + /* ENET_PTP_ETL */ +-#define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ ++#define ENET_PTP_ETL_ETSL GD_BITS(0,31) /*!< expected time low */ + + /* ENET_PTP_TSF */ + #define ENET_PTP_TSF_TSSCO BIT(0) /*!< timestamp second counter overflow */ + #define ENET_PTP_TSF_TTM BIT(1) /*!< target time match */ + + /* ENET_PTP_PPSCTL */ +-#define ENET_PTP_PPSCTL_PPSOFC BITS(0,3) /*!< PPS output frequency configure */ ++#define ENET_PTP_PPSCTL_PPSOFC GD_BITS(0,3) /*!< PPS output frequency configure */ + + /* ENET_DMA_BCTL */ + #define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */ + #define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */ +-#define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */ ++#define ENET_DMA_BCTL_DPSL GD_BITS(2,6) /*!< descriptor skip length */ + #define ENET_DMA_BCTL_DFM BIT(7) /*!< descriptor format mode */ +-#define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */ +-#define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ ++#define ENET_DMA_BCTL_PGBL GD_BITS(8,13) /*!< programmable burst length */ ++#define ENET_DMA_BCTL_RTPR GD_BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ + #define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */ +-#define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */ ++#define ENET_DMA_BCTL_RXDP GD_BITS(17,22) /*!< RxDMA PGBL */ + #define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */ + #define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ + #define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ + #define ENET_DMA_BCTL_MB BIT(26) /*!< mixed burst */ + + /* ENET_DMA_TPEN */ +-#define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ ++#define ENET_DMA_TPEN_TPE GD_BITS(0,31) /*!< transmit poll enable */ + + /* ENET_DMA_RPEN */ +-#define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ ++#define ENET_DMA_RPEN_RPE GD_BITS(0,31) /*!< receive poll enable */ + + /* ENET_DMA_RDTADDR */ +-#define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ ++#define ENET_DMA_RDTADDR_SRT GD_BITS(0,31) /*!< start address of receive table */ + + /* ENET_DMA_TDTADDR */ +-#define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ ++#define ENET_DMA_TDTADDR_STT GD_BITS(0,31) /*!< start address of transmit table */ + + /* ENET_DMA_STAT */ + #define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ @@ -456,9 +456,9 @@ OF SUCH DAMAGE. - #define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */ - #define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */ - #define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */ --#define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */ --#define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */ --#define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */ -+#define ENET_DMA_STAT_RP GD_BITS(17,19) /*!< receive process state */ -+#define ENET_DMA_STAT_TP GD_BITS(20,22) /*!< transmit process state */ -+#define ENET_DMA_STAT_EB GD_BITS(23,25) /*!< error bits status */ - #define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ - #define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ - #define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ + #define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */ + #define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */ + #define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */ +-#define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */ +-#define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */ +-#define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */ ++#define ENET_DMA_STAT_RP GD_BITS(17,19) /*!< receive process state */ ++#define ENET_DMA_STAT_TP GD_BITS(20,22) /*!< transmit process state */ ++#define ENET_DMA_STAT_EB GD_BITS(23,25) /*!< error bits status */ + #define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ + #define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ + #define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ @@ -466,11 +466,11 @@ OF SUCH DAMAGE. - /* ENET_DMA_CTL */ - #define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ - #define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ --#define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */ -+#define ENET_DMA_CTL_RTHC GD_BITS(3,4) /*!< receive threshold control */ - #define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */ - #define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */ - #define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */ --#define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */ -+#define ENET_DMA_CTL_TTHC GD_BITS(14,16) /*!< transmit threshold control */ - #define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */ - #define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */ - #define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ + /* ENET_DMA_CTL */ + #define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ + #define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ +-#define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */ ++#define ENET_DMA_CTL_RTHC GD_BITS(3,4) /*!< receive threshold control */ + #define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */ + #define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */ + #define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */ +-#define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */ ++#define ENET_DMA_CTL_TTHC GD_BITS(14,16) /*!< transmit threshold control */ + #define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */ + #define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */ + #define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ @@ -495,29 +495,29 @@ OF SUCH DAMAGE. - #define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ - - /* ENET_DMA_MFBOCNT */ --#define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ --#define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ -+#define ENET_DMA_MFBOCNT_MSFC GD_BITS(0,15) /*!< missed frames by the controller */ -+#define ENET_DMA_MFBOCNT_MSFA GD_BITS(17,27) /*!< missed frames by the application */ - - /* ENET_DMA_RSWDC */ --#define ENET_DMA_RSWDC_WDCFRS BITS(0,7) /*!< watchdog counter for receive status (RS) */ -+#define ENET_DMA_RSWDC_WDCFRS GD_BITS(0,7) /*!< watchdog counter for receive status (RS) */ - - /* ENET_DMA_CTDADDR */ --#define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */ -+#define ENET_DMA_CTDADDR_TDAP GD_BITS(0,31) /*!< transmit descriptor address pointer */ - - /* ENET_DMA_CRDADDR */ --#define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ -+#define ENET_DMA_CRDADDR_RDAP GD_BITS(0,31) /*!< receive descriptor address pointer */ - - /* ENET_DMA_CTBADDR */ --#define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ -+#define ENET_DMA_CTBADDR_TBAP GD_BITS(0,31) /*!< transmit buffer address pointer */ - - /* ENET_DMA_CRBADDR */ --#define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ -+#define ENET_DMA_CRBADDR_RBAP GD_BITS(0,31) /*!< receive buffer address pointer */ - - /* ENET DMA Tx descriptor TDES0 */ - #define ENET_TDES0_DB BIT(0) /*!< deferred */ - #define ENET_TDES0_UFE BIT(1) /*!< underflow error */ - #define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */ --#define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */ -+#define ENET_TDES0_COCNT GD_BITS(3,6) /*!< collision count */ - #define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */ - #define ENET_TDES0_ECO BIT(8) /*!< excessive collision */ - #define ENET_TDES0_LCO BIT(9) /*!< late collision */ + #define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ + + /* ENET_DMA_MFBOCNT */ +-#define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ +-#define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ ++#define ENET_DMA_MFBOCNT_MSFC GD_BITS(0,15) /*!< missed frames by the controller */ ++#define ENET_DMA_MFBOCNT_MSFA GD_BITS(17,27) /*!< missed frames by the application */ + + /* ENET_DMA_RSWDC */ +-#define ENET_DMA_RSWDC_WDCFRS BITS(0,7) /*!< watchdog counter for receive status (RS) */ ++#define ENET_DMA_RSWDC_WDCFRS GD_BITS(0,7) /*!< watchdog counter for receive status (RS) */ + + /* ENET_DMA_CTDADDR */ +-#define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */ ++#define ENET_DMA_CTDADDR_TDAP GD_BITS(0,31) /*!< transmit descriptor address pointer */ + + /* ENET_DMA_CRDADDR */ +-#define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ ++#define ENET_DMA_CRDADDR_RDAP GD_BITS(0,31) /*!< receive descriptor address pointer */ + + /* ENET_DMA_CTBADDR */ +-#define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ ++#define ENET_DMA_CTBADDR_TBAP GD_BITS(0,31) /*!< transmit buffer address pointer */ + + /* ENET_DMA_CRBADDR */ +-#define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ ++#define ENET_DMA_CRBADDR_RBAP GD_BITS(0,31) /*!< receive buffer address pointer */ + + /* ENET DMA Tx descriptor TDES0 */ + #define ENET_TDES0_DB BIT(0) /*!< deferred */ + #define ENET_TDES0_UFE BIT(1) /*!< underflow error */ + #define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */ +-#define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */ ++#define ENET_TDES0_COCNT GD_BITS(3,6) /*!< collision count */ + #define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */ + #define ENET_TDES0_ECO BIT(8) /*!< excessive collision */ + #define ENET_TDES0_LCO BIT(9) /*!< late collision */ @@ -531,7 +531,7 @@ OF SUCH DAMAGE. - #define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */ - #define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */ - #define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/ --#define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */ -+#define ENET_TDES0_CM GD_BITS(22,23) /*!< checksum mode */ - #define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */ - #define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */ - #define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */ + #define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */ + #define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */ + #define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/ +-#define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */ ++#define ENET_TDES0_CM GD_BITS(22,23) /*!< checksum mode */ + #define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */ + #define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */ + #define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */ @@ -541,21 +541,21 @@ OF SUCH DAMAGE. - #define ENET_TDES0_DAV BIT(31) /*!< DAV bit */ - - /* ENET DMA Tx descriptor TDES1 */ --#define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */ --#define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */ -+#define ENET_TDES1_TB1S GD_BITS(0,12) /*!< transmit buffer 1 size */ -+#define ENET_TDES1_TB2S GD_BITS(16,28) /*!< transmit buffer 2 size */ - - /* ENET DMA Tx descriptor TDES2 */ --#define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ -+#define ENET_TDES2_TB1AP GD_BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ - - /* ENET DMA Tx descriptor TDES3 */ --#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ -+#define ENET_TDES3_TB2AP GD_BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ - - #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE - /* ENET DMA Tx descriptor TDES6 */ --#define ENET_TDES6_TTSL BITS(0,31) /*!< transmit frame timestamp low 32-bit value */ -+#define ENET_TDES6_TTSL GD_BITS(0,31) /*!< transmit frame timestamp low 32-bit value */ - - /* ENET DMA Tx descriptor TDES7 */ --#define ENET_TDES7_TTSH BITS(0,31) /*!< transmit frame timestamp high 32-bit value */ -+#define ENET_TDES7_TTSH GD_BITS(0,31) /*!< transmit frame timestamp high 32-bit value */ - #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - - /* ENET DMA Rx descriptor RDES0 */ + #define ENET_TDES0_DAV BIT(31) /*!< DAV bit */ + + /* ENET DMA Tx descriptor TDES1 */ +-#define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */ +-#define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */ ++#define ENET_TDES1_TB1S GD_BITS(0,12) /*!< transmit buffer 1 size */ ++#define ENET_TDES1_TB2S GD_BITS(16,28) /*!< transmit buffer 2 size */ + + /* ENET DMA Tx descriptor TDES2 */ +-#define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ ++#define ENET_TDES2_TB1AP GD_BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ + + /* ENET DMA Tx descriptor TDES3 */ +-#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ ++#define ENET_TDES3_TB2AP GD_BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ + + #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE + /* ENET DMA Tx descriptor TDES6 */ +-#define ENET_TDES6_TTSL BITS(0,31) /*!< transmit frame timestamp low 32-bit value */ ++#define ENET_TDES6_TTSL GD_BITS(0,31) /*!< transmit frame timestamp low 32-bit value */ + + /* ENET DMA Tx descriptor TDES7 */ +-#define ENET_TDES7_TTSH BITS(0,31) /*!< transmit frame timestamp high 32-bit value */ ++#define ENET_TDES7_TTSH GD_BITS(0,31) /*!< transmit frame timestamp high 32-bit value */ + #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + + /* ENET DMA Rx descriptor RDES0 */ @@ -577,40 +577,40 @@ OF SUCH DAMAGE. - #define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */ - #define ENET_RDES0_DERR BIT(14) /*!< descriptor error */ - #define ENET_RDES0_ERRS BIT(15) /*!< error summary */ --#define ENET_RDES0_FRML BITS(16,29) /*!< frame length */ -+#define ENET_RDES0_FRML GD_BITS(16,29) /*!< frame length */ - #define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ - #define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ - - /* ENET DMA Rx descriptor RDES1 */ --#define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ -+#define ENET_RDES1_RB1S GD_BITS(0,12) /*!< receive buffer 1 size */ - #define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ - #define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ --#define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */ -+#define ENET_RDES1_RB2S GD_BITS(16,28) /*!< receive buffer 2 size */ - #define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */ - - /* ENET DMA Rx descriptor RDES2 */ --#define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ -+#define ENET_RDES2_RB1AP GD_BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ - - /* ENET DMA Rx descriptor RDES3 */ --#define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ -+#define ENET_RDES3_RB2AP GD_BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ - - #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE - /* ENET DMA Rx descriptor RDES4 */ --#define ENET_RDES4_IPPLDT BITS(0,2) /*!< IP frame payload type */ -+#define ENET_RDES4_IPPLDT GD_BITS(0,2) /*!< IP frame payload type */ - #define ENET_RDES4_IPHERR BIT(3) /*!< IP frame header error */ - #define ENET_RDES4_IPPLDERR BIT(4) /*!< IP frame payload error */ - #define ENET_RDES4_IPCKSB BIT(5) /*!< IP frame checksum bypassed */ - #define ENET_RDES4_IPF4 BIT(6) /*!< IP frame in version 4 */ - #define ENET_RDES4_IPF6 BIT(7) /*!< IP frame in version 6 */ --#define ENET_RDES4_PTPMT BITS(8,11) /*!< PTP message type */ -+#define ENET_RDES4_PTPMT GD_BITS(8,11) /*!< PTP message type */ - #define ENET_RDES4_PTPOEF BIT(12) /*!< PTP on ethernet frame */ - #define ENET_RDES4_PTPVF BIT(13) /*!< PTP version format */ - - /* ENET DMA Rx descriptor RDES6 */ --#define ENET_RDES6_RTSL BITS(0,31) /*!< receive frame timestamp low 32-bit value */ -+#define ENET_RDES6_RTSL GD_BITS(0,31) /*!< receive frame timestamp low 32-bit value */ - - /* ENET DMA Rx descriptor RDES7 */ --#define ENET_RDES7_RTSH BITS(0,31) /*!< receive frame timestamp high 32-bit value */ -+#define ENET_RDES7_RTSH GD_BITS(0,31) /*!< receive frame timestamp high 32-bit value */ - #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - - /* constants definitions */ + #define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */ + #define ENET_RDES0_DERR BIT(14) /*!< descriptor error */ + #define ENET_RDES0_ERRS BIT(15) /*!< error summary */ +-#define ENET_RDES0_FRML BITS(16,29) /*!< frame length */ ++#define ENET_RDES0_FRML GD_BITS(16,29) /*!< frame length */ + #define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ + #define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ + + /* ENET DMA Rx descriptor RDES1 */ +-#define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ ++#define ENET_RDES1_RB1S GD_BITS(0,12) /*!< receive buffer 1 size */ + #define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ + #define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ +-#define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */ ++#define ENET_RDES1_RB2S GD_BITS(16,28) /*!< receive buffer 2 size */ + #define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */ + + /* ENET DMA Rx descriptor RDES2 */ +-#define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ ++#define ENET_RDES2_RB1AP GD_BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ + + /* ENET DMA Rx descriptor RDES3 */ +-#define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ ++#define ENET_RDES3_RB2AP GD_BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ + + #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE + /* ENET DMA Rx descriptor RDES4 */ +-#define ENET_RDES4_IPPLDT BITS(0,2) /*!< IP frame payload type */ ++#define ENET_RDES4_IPPLDT GD_BITS(0,2) /*!< IP frame payload type */ + #define ENET_RDES4_IPHERR BIT(3) /*!< IP frame header error */ + #define ENET_RDES4_IPPLDERR BIT(4) /*!< IP frame payload error */ + #define ENET_RDES4_IPCKSB BIT(5) /*!< IP frame checksum bypassed */ + #define ENET_RDES4_IPF4 BIT(6) /*!< IP frame in version 4 */ + #define ENET_RDES4_IPF6 BIT(7) /*!< IP frame in version 6 */ +-#define ENET_RDES4_PTPMT BITS(8,11) /*!< PTP message type */ ++#define ENET_RDES4_PTPMT GD_BITS(8,11) /*!< PTP message type */ + #define ENET_RDES4_PTPOEF BIT(12) /*!< PTP on ethernet frame */ + #define ENET_RDES4_PTPVF BIT(13) /*!< PTP version format */ + + /* ENET DMA Rx descriptor RDES6 */ +-#define ENET_RDES6_RTSL BITS(0,31) /*!< receive frame timestamp low 32-bit value */ ++#define ENET_RDES6_RTSL GD_BITS(0,31) /*!< receive frame timestamp low 32-bit value */ + + /* ENET DMA Rx descriptor RDES7 */ +-#define ENET_RDES7_RTSH BITS(0,31) /*!< receive frame timestamp high 32-bit value */ ++#define ENET_RDES7_RTSH GD_BITS(0,31) /*!< receive frame timestamp high 32-bit value */ + #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + + /* constants definitions */ @@ -992,13 +992,13 @@ typedef struct - }enet_ptp_systime_struct; - - /* mac_cfg register value */ --#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ -+#define MAC_CFG_BOL(regval) (GD_BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ - #define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ - #define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ - #define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ - #define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ - --#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ -+#define MAC_CFG_IGBS(regval) (GD_BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ - #define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ - #define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ - #define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ + }enet_ptp_systime_struct; + + /* mac_cfg register value */ +-#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ ++#define MAC_CFG_BOL(regval) (GD_BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ + #define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ + #define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ + #define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ + #define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ + +-#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ ++#define MAC_CFG_IGBS(regval) (GD_BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ + #define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ + #define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ + #define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ @@ -1047,7 +1047,7 @@ typedef struct - #define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */ - - /* mac_frmf register value */ --#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ -+#define MAC_FRMF_PCFRM(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ - #define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */ - #define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ - #define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ + #define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */ + + /* mac_frmf register value */ +-#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ ++#define MAC_FRMF_PCFRM(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ + #define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */ + #define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ + #define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ @@ -1086,21 +1086,21 @@ typedef struct - #define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */ - - /* mac_phy_ctl register value */ --#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ -+#define MAC_PHY_CTL_CLR(regval) (GD_BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ - #define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */ - #define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-120 MHz; MDC clock= HCLK/62 */ - #define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ - #define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ - --#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ -+#define MAC_PHY_CTL_PR(regval) (GD_BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ - --#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ -+#define MAC_PHY_CTL_PA(regval) (GD_BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ - - /* mac_phy_data register value */ --#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ -+#define MAC_PHY_DATA_PD(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ - - /* mac_fctl register value */ --#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ -+#define MAC_FCTL_PLTS(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ - #define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ - #define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ - #define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ + #define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */ + + /* mac_phy_ctl register value */ +-#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ ++#define MAC_PHY_CTL_CLR(regval) (GD_BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ + #define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */ + #define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-120 MHz; MDC clock= HCLK/62 */ + #define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ + #define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ + +-#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ ++#define MAC_PHY_CTL_PR(regval) (GD_BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ + +-#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ ++#define MAC_PHY_CTL_PA(regval) (GD_BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ + + /* mac_phy_data register value */ +-#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ ++#define MAC_PHY_DATA_PD(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ + + /* mac_fctl register value */ +-#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ ++#define MAC_FCTL_PLTS(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ + #define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ + #define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ + #define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ @@ -1125,9 +1125,9 @@ typedef struct - #define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ - #define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ - --#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ -+#define MAC_FCTL_PTM(regval) (GD_BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ - /* mac_vlt register value */ --#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ -+#define MAC_VLT_VLTI(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ - - #define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ - #define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ + #define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ + #define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ + +-#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ ++#define MAC_FCTL_PTM(regval) (GD_BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ + /* mac_vlt register value */ +-#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ ++#define MAC_VLT_VLTI(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ + + #define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ + #define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ @@ -1166,10 +1166,10 @@ typedef struct - #define GET_MAC_DBG_TXFRS(regval) GET_BITS((regval),20,21) /*!< get value of ENET_MAC_DBG_TXFRS bit field */ - - /* mac_addr0h register value */ --#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ -+#define MAC_ADDR0H_ADDR0H(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ - - /* mac_addrxh register value, x = 1,2,3 */ --#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ -+#define MAC_ADDR123H_ADDR123H(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ - - #define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */ - #define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */ + #define GET_MAC_DBG_TXFRS(regval) GET_BITS((regval),20,21) /*!< get value of ENET_MAC_DBG_TXFRS bit field */ + + /* mac_addr0h register value */ +-#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ ++#define MAC_ADDR0H_ADDR0H(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ + + /* mac_addrxh register value, x = 1,2,3 */ +-#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ ++#define MAC_ADDR123H_ADDR123H(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ + + #define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */ + #define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */ @@ -1182,7 +1182,7 @@ typedef struct - #define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ - - /* mac_fcth register value */ --#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ -+#define MAC_FCTH_RFA(regval) ((GD_BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ - #define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ - #define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ - #define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ + #define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ + + /* mac_fcth register value */ +-#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ ++#define MAC_FCTH_RFA(regval) ((GD_BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ + #define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ + #define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ + #define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ @@ -1191,7 +1191,7 @@ typedef struct - #define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ - #define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ - --#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ -+#define MAC_FCTH_RFD(regval) ((GD_BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ - #define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ - #define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ - #define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ + #define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ + #define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ + +-#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ ++#define MAC_FCTH_RFD(regval) ((GD_BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ + #define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ + #define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ + #define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ @@ -1206,7 +1206,7 @@ typedef struct - #define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */ - - /* ptp_tsctl register value */ --#define PTP_TSCTL_CKNT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */ -+#define PTP_TSCTL_CKNT(regval) (GD_BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */ - - #define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */ - #define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */ + #define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */ + + /* ptp_tsctl register value */ +-#define PTP_TSCTL_CKNT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */ ++#define PTP_TSCTL_CKNT(regval) (GD_BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */ + + #define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */ + #define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */ @@ -1217,7 +1217,7 @@ typedef struct - #define ENET_PTP_FRAME_USE_MACADDRESS_FILTER ENET_PTP_TSCTL_MAFEN /*!< enable MAC address1-3 to filter the PTP frame */ - - /* ptp_ssinc register value */ --#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ -+#define PTP_SSINC_STMSSI(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ - - /* ptp_tsl register value */ - #define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ + #define ENET_PTP_FRAME_USE_MACADDRESS_FILTER ENET_PTP_TSCTL_MAFEN /*!< enable MAC address1-3 to filter the PTP frame */ + + /* ptp_ssinc register value */ +-#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ ++#define PTP_SSINC_STMSSI(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ + + /* ptp_tsl register value */ + #define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ @@ -1228,13 +1228,13 @@ typedef struct - #define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ - - /* ptp_tsul register value */ --#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ -+#define PTP_TSUL_TMSUSS(regval) (GD_BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ - - #define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ - #define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ - - /* ptp_ppsctl register value */ --#define PTP_PPSCTL_PPSOFC(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_PPSCTL_PPSOFC bit field */ -+#define PTP_PPSCTL_PPSOFC(regval) (GD_BITS(0,3) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_PPSCTL_PPSOFC bit field */ - #define ENET_PPSOFC_1HZ PTP_PPSCTL_PPSOFC(0) /*!< PPS output 1Hz frequency */ - #define ENET_PPSOFC_2HZ PTP_PPSCTL_PPSOFC(1) /*!< PPS output 2Hz frequency */ - #define ENET_PPSOFC_4HZ PTP_PPSCTL_PPSOFC(2) /*!< PPS output 4Hz frequency */ + #define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ + + /* ptp_tsul register value */ +-#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ ++#define PTP_TSUL_TMSUSS(regval) (GD_BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ + + #define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ + #define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ + + /* ptp_ppsctl register value */ +-#define PTP_PPSCTL_PPSOFC(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_PPSCTL_PPSOFC bit field */ ++#define PTP_PPSCTL_PPSOFC(regval) (GD_BITS(0,3) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_PPSCTL_PPSOFC bit field */ + #define ENET_PPSOFC_1HZ PTP_PPSCTL_PPSOFC(0) /*!< PPS output 1Hz frequency */ + #define ENET_PPSOFC_2HZ PTP_PPSCTL_PPSOFC(1) /*!< PPS output 2Hz frequency */ + #define ENET_PPSOFC_4HZ PTP_PPSCTL_PPSOFC(2) /*!< PPS output 4Hz frequency */ @@ -1253,13 +1253,13 @@ typedef struct - #define ENET_PPSOFC_32768HZ PTP_PPSCTL_PPSOFC(15) /*!< PPS output 32768Hz frequency */ - - /* dma_bctl register value */ --#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ -+#define DMA_BCTL_DPSL(regval) (GD_BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ - #define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ - - #define ENET_ENHANCED_DESCRIPTOR ENET_DMA_BCTL_DFM /*!< enhanced mode descriptor */ - #define ENET_NORMAL_DESCRIPTOR ((uint32_t)0x00000000) /*!< normal mode descriptor */ - --#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ -+#define DMA_BCTL_PGBL(regval) (GD_BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ - #define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ - #define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ - #define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ + #define ENET_PPSOFC_32768HZ PTP_PPSCTL_PPSOFC(15) /*!< PPS output 32768Hz frequency */ + + /* dma_bctl register value */ +-#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ ++#define DMA_BCTL_DPSL(regval) (GD_BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ + #define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ + + #define ENET_ENHANCED_DESCRIPTOR ENET_DMA_BCTL_DFM /*!< enhanced mode descriptor */ + #define ENET_NORMAL_DESCRIPTOR ((uint32_t)0x00000000) /*!< normal mode descriptor */ + +-#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ ++#define DMA_BCTL_PGBL(regval) (GD_BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ + #define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ + #define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ + #define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ @@ -1273,7 +1273,7 @@ typedef struct - #define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ - #define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ - --#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ -+#define DMA_BCTL_RTPR(regval) (GD_BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ - #define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ - #define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ - #define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ + #define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ + #define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ + +-#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ ++#define DMA_BCTL_RTPR(regval) (GD_BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ + #define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ + #define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ + #define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ @@ -1283,7 +1283,7 @@ typedef struct - #define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ - #define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */ - --#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ -+#define DMA_BCTL_RXDP(regval) (GD_BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ - #define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ - #define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ - #define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ + #define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ + #define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */ + +-#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ ++#define DMA_BCTL_RXDP(regval) (GD_BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ + #define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ + #define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ + #define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ @@ -1329,13 +1329,13 @@ typedef struct - #define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */ - - /* dma_ctl register value */ --#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ -+#define DMA_CTL_RTHC(regval) (GD_BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ - #define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */ - #define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */ - #define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */ - #define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */ - --#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ -+#define DMA_CTL_TTHC(regval) (GD_BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ - #define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */ - #define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */ - #define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */ + #define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */ + + /* dma_ctl register value */ +-#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ ++#define DMA_CTL_RTHC(regval) (GD_BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ + #define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */ + #define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */ + #define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */ + #define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */ + +-#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ ++#define DMA_CTL_TTHC(regval) (GD_BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ + #define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */ + #define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */ + #define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */ @@ -1376,25 +1376,25 @@ typedef struct - #define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ - - /* dma_rswdc register value */ --#define DMA_RSWDC_WDCFRS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_DMA_RSWDC_WDCFRS bit field */ -+#define DMA_RSWDC_WDCFRS(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_DMA_RSWDC_WDCFRS bit field */ - - /* dma tx descriptor tdes0 register value */ --#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ -+#define TDES0_CONT(regval) (GD_BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ - #define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ - --#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ -+#define TDES0_CM(regval) (GD_BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ - #define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ - #define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ - #define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ - #define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ - - /* dma tx descriptor tdes1 register value */ --#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ -+#define TDES1_TB1S(regval) (GD_BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ - --#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ -+#define TDES1_TB2S(regval) (GD_BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ - - /* dma rx descriptor rdes0 register value */ --#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ -+#define RDES0_FRML(regval) (GD_BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ - #define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */ - - /* dma rx descriptor rdes1 register value */ + #define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ + + /* dma_rswdc register value */ +-#define DMA_RSWDC_WDCFRS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_DMA_RSWDC_WDCFRS bit field */ ++#define DMA_RSWDC_WDCFRS(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_DMA_RSWDC_WDCFRS bit field */ + + /* dma tx descriptor tdes0 register value */ +-#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ ++#define TDES0_CONT(regval) (GD_BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ + #define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ + +-#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ ++#define TDES0_CM(regval) (GD_BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ + #define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ + #define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ + #define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ + #define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ + + /* dma tx descriptor tdes1 register value */ +-#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ ++#define TDES1_TB1S(regval) (GD_BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ + +-#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ ++#define TDES1_TB2S(regval) (GD_BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ + + /* dma rx descriptor rdes0 register value */ +-#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ ++#define RDES0_FRML(regval) (GD_BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ + #define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */ + + /* dma rx descriptor rdes1 register value */ @@ -1406,10 +1406,10 @@ typedef struct - #define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */ - - /* dma rx descriptor rdes4 register value */ --#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ -+#define RDES4_IPPLDT(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ - #define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ - --#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ -+#define RDES4_PTPMT(regval) (GD_BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ - #define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ - - /* ENET register mask value */ + #define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */ + + /* dma rx descriptor rdes4 register value */ +-#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ ++#define RDES4_IPPLDT(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ + #define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ + +-#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ ++#define RDES4_PTPMT(regval) (GD_BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ + #define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ + + /* ENET register mask value */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h old mode 100644 new mode 100755 @@ -1371,191 +1371,191 @@ index 6ef9bac..83dc834 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h @@ -84,8 +84,8 @@ OF SUCH DAMAGE. - /* EXMC_SNCTLx,x=0..3 */ - #define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ - #define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing enable */ --#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ --#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ -+#define EXMC_SNCTL_NRTP GD_BITS(2,3) /*!< NOR bank memory type */ -+#define EXMC_SNCTL_NRW GD_BITS(4,5) /*!< NOR bank memory data bus width */ - #define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ - #define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ - #define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ + /* EXMC_SNCTLx,x=0..3 */ + #define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ + #define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing enable */ +-#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ +-#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ ++#define EXMC_SNCTL_NRTP GD_BITS(2,3) /*!< NOR bank memory type */ ++#define EXMC_SNCTL_NRW GD_BITS(4,5) /*!< NOR bank memory data bus width */ + #define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ + #define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ + #define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ @@ -95,34 +95,34 @@ OF SUCH DAMAGE. - #define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ - #define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ - #define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait enable */ --#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ -+#define EXMC_SNCTL_CPS GD_BITS(16,18) /*!< CRAM page size */ - #define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write config */ - - /* EXMC_SNTCFGx,x=0..3 */ --#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */ --#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */ --#define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */ --#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ --#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ --#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */ --#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ -+#define EXMC_SNTCFG_ASET GD_BITS(0,3) /*!< asynchronous address setup time */ -+#define EXMC_SNTCFG_AHLD GD_BITS(4,7) /*!< asynchronous address hold time */ -+#define EXMC_SNTCFG_DSET GD_BITS(8,15) /*!< asynchronous data setup time */ -+#define EXMC_SNTCFG_BUSLAT GD_BITS(16,19) /*!< bus latency */ -+#define EXMC_SNTCFG_CKDIV GD_BITS(20,23) /*!< synchronous clock divide ratio */ -+#define EXMC_SNTCFG_DLAT GD_BITS(24,27) /*!< synchronous data latency for NOR flash */ -+#define EXMC_SNTCFG_ASYNCMOD GD_BITS(28,29) /*!< asynchronous access mode */ - - /* EXMC_SNWTCFGx,x=0..3 */ --#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */ --#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */ --#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */ --#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ --#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ -+#define EXMC_SNWTCFG_WASET GD_BITS(0,3) /*!< asynchronous address setup time */ -+#define EXMC_SNWTCFG_WAHLD GD_BITS(4,7) /*!< asynchronous address hold time */ -+#define EXMC_SNWTCFG_WDSET GD_BITS(8,15) /*!< asynchronous data setup time */ -+#define EXMC_SNWTCFG_WBUSLAT GD_BITS(16,19) /*!< bus latency */ -+#define EXMC_SNWTCFG_WASYNCMOD GD_BITS(28,29) /*!< asynchronous access mode */ - - /* EXMC_NPCTLx,x=1..3 */ - #define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ - #define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ - #define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ --#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ -+#define EXMC_NPCTL_NDW GD_BITS(4,5) /*!< NAND bank memory data bus width */ - #define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ --#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ --#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ --#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ -+#define EXMC_NPCTL_CTR GD_BITS(9,12) /*!< CLE to RE delay */ -+#define EXMC_NPCTL_ATR GD_BITS(13,16) /*!< ALE to RE delay */ -+#define EXMC_NPCTL_ECCSZ GD_BITS(17,19) /*!< ECC size */ - - /* EXMC_NPINTENx,x=1..3 */ - #define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ + #define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ + #define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ + #define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait enable */ +-#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ ++#define EXMC_SNCTL_CPS GD_BITS(16,18) /*!< CRAM page size */ + #define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write config */ + + /* EXMC_SNTCFGx,x=0..3 */ +-#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */ +-#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */ +-#define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */ +-#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ +-#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ +-#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */ +-#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ ++#define EXMC_SNTCFG_ASET GD_BITS(0,3) /*!< asynchronous address setup time */ ++#define EXMC_SNTCFG_AHLD GD_BITS(4,7) /*!< asynchronous address hold time */ ++#define EXMC_SNTCFG_DSET GD_BITS(8,15) /*!< asynchronous data setup time */ ++#define EXMC_SNTCFG_BUSLAT GD_BITS(16,19) /*!< bus latency */ ++#define EXMC_SNTCFG_CKDIV GD_BITS(20,23) /*!< synchronous clock divide ratio */ ++#define EXMC_SNTCFG_DLAT GD_BITS(24,27) /*!< synchronous data latency for NOR flash */ ++#define EXMC_SNTCFG_ASYNCMOD GD_BITS(28,29) /*!< asynchronous access mode */ + + /* EXMC_SNWTCFGx,x=0..3 */ +-#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */ +-#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */ +-#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */ +-#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ +-#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ ++#define EXMC_SNWTCFG_WASET GD_BITS(0,3) /*!< asynchronous address setup time */ ++#define EXMC_SNWTCFG_WAHLD GD_BITS(4,7) /*!< asynchronous address hold time */ ++#define EXMC_SNWTCFG_WDSET GD_BITS(8,15) /*!< asynchronous data setup time */ ++#define EXMC_SNWTCFG_WBUSLAT GD_BITS(16,19) /*!< bus latency */ ++#define EXMC_SNWTCFG_WASYNCMOD GD_BITS(28,29) /*!< asynchronous access mode */ + + /* EXMC_NPCTLx,x=1..3 */ + #define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ + #define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ + #define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ +-#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ ++#define EXMC_NPCTL_NDW GD_BITS(4,5) /*!< NAND bank memory data bus width */ + #define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ +-#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ +-#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ +-#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ ++#define EXMC_NPCTL_CTR GD_BITS(9,12) /*!< CLE to RE delay */ ++#define EXMC_NPCTL_ATR GD_BITS(13,16) /*!< ALE to RE delay */ ++#define EXMC_NPCTL_ECCSZ GD_BITS(17,19) /*!< ECC size */ + + /* EXMC_NPINTENx,x=1..3 */ + #define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ @@ -134,25 +134,25 @@ OF SUCH DAMAGE. - #define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ - - /* EXMC_NPCTCFGx,x=1..3 */ --#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ --#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ --#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ --#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ -+#define EXMC_NPCTCFG_COMSET GD_BITS(0,7) /*!< common memory setup time */ -+#define EXMC_NPCTCFG_COMWAIT GD_BITS(8,15) /*!< common memory wait time */ -+#define EXMC_NPCTCFG_COMHLD GD_BITS(16,23) /*!< common memory hold time */ -+#define EXMC_NPCTCFG_COMHIZ GD_BITS(24,31) /*!< common memory data bus HiZ time */ - - /* EXMC_NPATCFGx,x=1..3 */ --#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ --#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ --#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ --#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ -+#define EXMC_NPATCFG_ATTSET GD_BITS(0,7) /*!< attribute memory setup time */ -+#define EXMC_NPATCFG_ATTWAIT GD_BITS(8,15) /*!< attribute memory wait time */ -+#define EXMC_NPATCFG_ATTHLD GD_BITS(16,23) /*!< attribute memory hold time */ -+#define EXMC_NPATCFG_ATTHIZ GD_BITS(24,31) /*!< attribute memory data bus HiZ time */ - - /* EXMC_PIOTCFG3 */ --#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ --#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ --#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ --#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ -+#define EXMC_PIOTCFG3_IOSET GD_BITS(0,7) /*!< IO space setup time */ -+#define EXMC_PIOTCFG3_IOWAIT GD_BITS(8,15) /*!< IO space wait time */ -+#define EXMC_PIOTCFG3_IOHLD GD_BITS(16,23) /*!< IO space hold time */ -+#define EXMC_PIOTCFG3_IOHIZ GD_BITS(24,31) /*!< IO space data bus HiZ time */ - - /* EXMC_NECCx,x=1,2 */ --#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ -+#define EXMC_NECC_ECC GD_BITS(0,31) /*!< ECC result */ - - /* constants definitions */ - /* EXMC NOR/SRAM timing initialize struct */ + #define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ + + /* EXMC_NPCTCFGx,x=1..3 */ +-#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ +-#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ +-#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ +-#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ ++#define EXMC_NPCTCFG_COMSET GD_BITS(0,7) /*!< common memory setup time */ ++#define EXMC_NPCTCFG_COMWAIT GD_BITS(8,15) /*!< common memory wait time */ ++#define EXMC_NPCTCFG_COMHLD GD_BITS(16,23) /*!< common memory hold time */ ++#define EXMC_NPCTCFG_COMHIZ GD_BITS(24,31) /*!< common memory data bus HiZ time */ + + /* EXMC_NPATCFGx,x=1..3 */ +-#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ +-#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ +-#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ +-#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ ++#define EXMC_NPATCFG_ATTSET GD_BITS(0,7) /*!< attribute memory setup time */ ++#define EXMC_NPATCFG_ATTWAIT GD_BITS(8,15) /*!< attribute memory wait time */ ++#define EXMC_NPATCFG_ATTHLD GD_BITS(16,23) /*!< attribute memory hold time */ ++#define EXMC_NPATCFG_ATTHIZ GD_BITS(24,31) /*!< attribute memory data bus HiZ time */ + + /* EXMC_PIOTCFG3 */ +-#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ +-#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ +-#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ +-#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ ++#define EXMC_PIOTCFG3_IOSET GD_BITS(0,7) /*!< IO space setup time */ ++#define EXMC_PIOTCFG3_IOWAIT GD_BITS(8,15) /*!< IO space wait time */ ++#define EXMC_PIOTCFG3_IOHLD GD_BITS(16,23) /*!< IO space hold time */ ++#define EXMC_PIOTCFG3_IOHIZ GD_BITS(24,31) /*!< IO space data bus HiZ time */ + + /* EXMC_NECCx,x=1,2 */ +-#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ ++#define EXMC_NECC_ECC GD_BITS(0,31) /*!< ECC result */ + + /* constants definitions */ + /* EXMC NOR/SRAM timing initialize struct */ @@ -234,7 +234,7 @@ typedef struct - #define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC registers, bank = 1,2 */ - - /* CRAM page size */ --#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) -+#define SNCTL_CPS(regval) (GD_BITS(16,18) & ((uint32_t)(regval) << 16)) - #define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ - #define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ - #define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ + #define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC registers, bank = 1,2 */ + + /* CRAM page size */ +-#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) ++#define SNCTL_CPS(regval) (GD_BITS(16,18) & ((uint32_t)(regval) << 16)) + #define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ + #define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ + #define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ @@ -242,25 +242,25 @@ typedef struct - #define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ - - /* NOR bank memory data bus width */ --#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -+#define SNCTL_NRW(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) - #define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */ - #define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */ - - /* NOR bank memory type */ --#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -+#define SNCTL_NRTP(regval) (GD_BITS(2,3) & ((uint32_t)(regval) << 2)) - #define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ - #define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ - #define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ - - /* asynchronous access mode */ --#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -+#define SNTCFG_ASYNCMOD(regval) (GD_BITS(28,29) & ((uint32_t)(regval) << 28)) - #define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ - #define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ - #define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ - #define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ - - /* data latency for NOR flash */ --#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -+#define SNTCFG_DLAT(regval) (GD_BITS(24,27) & ((uint32_t)(regval) << 24)) - #define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */ - #define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */ - #define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */ + #define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ + + /* NOR bank memory data bus width */ +-#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) ++#define SNCTL_NRW(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) + #define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */ + #define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */ + + /* NOR bank memory type */ +-#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) ++#define SNCTL_NRTP(regval) (GD_BITS(2,3) & ((uint32_t)(regval) << 2)) + #define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ + #define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ + #define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ + + /* asynchronous access mode */ +-#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) ++#define SNTCFG_ASYNCMOD(regval) (GD_BITS(28,29) & ((uint32_t)(regval) << 28)) + #define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ + #define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ + #define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ + #define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ + + /* data latency for NOR flash */ +-#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) ++#define SNTCFG_DLAT(regval) (GD_BITS(24,27) & ((uint32_t)(regval) << 24)) + #define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */ + #define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */ + #define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */ @@ -279,7 +279,7 @@ typedef struct - #define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */ - - /* synchronous clock divide ratio */ --#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) -+#define SNTCFG_CKDIV(regval) (GD_BITS(20,23) & ((uint32_t)(regval) << 20)) - #define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ - #define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ - #define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ + #define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */ + + /* synchronous clock divide ratio */ +-#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) ++#define SNTCFG_CKDIV(regval) (GD_BITS(20,23) & ((uint32_t)(regval) << 20)) + #define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ + #define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ + #define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ @@ -298,7 +298,7 @@ typedef struct - #define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ - - /* ECC size */ --#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) -+#define NPCTL_ECCSZ(regval) (GD_BITS(17,19) & ((uint32_t)(regval) << 17)) - #define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* ECC size is 256 bytes */ - #define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* ECC size is 512 bytes */ - #define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* ECC size is 1024 bytes */ + #define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ + + /* ECC size */ +-#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) ++#define NPCTL_ECCSZ(regval) (GD_BITS(17,19) & ((uint32_t)(regval) << 17)) + #define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* ECC size is 256 bytes */ + #define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* ECC size is 512 bytes */ + #define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* ECC size is 1024 bytes */ @@ -307,7 +307,7 @@ typedef struct - #define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* ECC size is 8192 bytes */ - - /* ALE to RE delay */ --#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) -+#define NPCTL_ATR(regval) (GD_BITS(13,16) & ((uint32_t)(regval) << 13)) - #define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ - #define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ - #define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ + #define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* ECC size is 8192 bytes */ + + /* ALE to RE delay */ +-#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) ++#define NPCTL_ATR(regval) (GD_BITS(13,16) & ((uint32_t)(regval) << 13)) + #define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ + #define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ + #define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ @@ -326,7 +326,7 @@ typedef struct - #define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ - - /* CLE to RE delay */ --#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) -+#define NPCTL_CTR(regval) (GD_BITS(9,12) & ((uint32_t)(regval) << 9)) - #define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ - #define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ - #define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ + #define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ + + /* CLE to RE delay */ +-#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) ++#define NPCTL_CTR(regval) (GD_BITS(9,12) & ((uint32_t)(regval) << 9)) + #define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ + #define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ + #define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ @@ -345,7 +345,7 @@ typedef struct - #define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ - - /* NAND bank memory data bus width */ --#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -+#define NPCTL_NDW(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) - #define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width is 8 bits */ - #define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width is 16 bits */ - + #define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ + + /* NAND bank memory data bus width */ +-#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) ++#define NPCTL_NDW(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) + #define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width is 8 bits */ + #define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width is 16 bits */ + diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h old mode 100644 new mode 100755 @@ -1563,73 +1563,73 @@ index 5daafa9..a905eea --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h @@ -72,13 +72,13 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* FMC_WS */ --#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ -+#define FMC_WS_WSCNT GD_BITS(0,2) /*!< wait state counter */ - - /* FMC_KEY0 */ --#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */ -+#define FMC_KEY0_KEY GD_BITS(0,31) /*!< FMC_CTL0 unlock key bits */ - - /* FMC_OBKEY */ --#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ -+#define FMC_OBKEY_OBKEY GD_BITS(0,31) /*!< option bytes unlock key bits */ - - /* FMC_STAT0 */ - #define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */ + + /* bits definitions */ + /* FMC_WS */ +-#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ ++#define FMC_WS_WSCNT GD_BITS(0,2) /*!< wait state counter */ + + /* FMC_KEY0 */ +-#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */ ++#define FMC_KEY0_KEY GD_BITS(0,31) /*!< FMC_CTL0 unlock key bits */ + + /* FMC_OBKEY */ +-#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ ++#define FMC_OBKEY_OBKEY GD_BITS(0,31) /*!< option bytes unlock key bits */ + + /* FMC_STAT0 */ + #define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */ @@ -99,19 +99,19 @@ OF SUCH DAMAGE. - #define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ - - /* FMC_ADDR0 */ --#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ -+#define FMC_ADDR0_ADDR GD_BITS(0,31) /*!< Flash erase/program command address bits */ - - /* FMC_OBSTAT */ - #define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ - #define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ --#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ --#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ -+#define FMC_OBSTAT_USER GD_BITS(2,9) /*!< store USER of option bytes block after system reset */ -+#define FMC_OBSTAT_DATA GD_BITS(10,25) /*!< store DATA of option bytes block after system reset. */ - - /* FMC_WP */ --#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ -+#define FMC_WP_WP GD_BITS(0,31) /*!< store WP of option bytes block after system reset */ - - /* FMC_KEY1 */ --#define FMC_KEY1_KEY BITS(0,31) /*!< FMC_CTL1 unlock key bits */ -+#define FMC_KEY1_KEY GD_BITS(0,31) /*!< FMC_CTL1 unlock key bits */ - - /* FMC_STAT1 */ - #define FMC_STAT1_BUSY BIT(0) /*!< flash busy flag bit */ + #define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ + + /* FMC_ADDR0 */ +-#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ ++#define FMC_ADDR0_ADDR GD_BITS(0,31) /*!< Flash erase/program command address bits */ + + /* FMC_OBSTAT */ + #define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ + #define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ +-#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ +-#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ ++#define FMC_OBSTAT_USER GD_BITS(2,9) /*!< store USER of option bytes block after system reset */ ++#define FMC_OBSTAT_DATA GD_BITS(10,25) /*!< store DATA of option bytes block after system reset. */ + + /* FMC_WP */ +-#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ ++#define FMC_WP_WP GD_BITS(0,31) /*!< store WP of option bytes block after system reset */ + + /* FMC_KEY1 */ +-#define FMC_KEY1_KEY BITS(0,31) /*!< FMC_CTL1 unlock key bits */ ++#define FMC_KEY1_KEY GD_BITS(0,31) /*!< FMC_CTL1 unlock key bits */ + + /* FMC_STAT1 */ + #define FMC_STAT1_BUSY BIT(0) /*!< flash busy flag bit */ @@ -129,14 +129,14 @@ OF SUCH DAMAGE. - #define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ - - /* FMC_ADDR1 */ --#define FMC_ADDR1_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ -+#define FMC_ADDR1_ADDR GD_BITS(0,31) /*!< Flash erase/program command address bits */ - - /* FMC_WSEN */ - #define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ - #define FMC_WSEN_BPEN BIT(1) /*!< FMC bit program enable bit */ - - /* FMC_PID */ --#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ -+#define FMC_PID_PID GD_BITS(0,31) /*!< product ID bits */ - - /* constants definitions */ - /* define the FMC bit position and its register index offset */ + #define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ + + /* FMC_ADDR1 */ +-#define FMC_ADDR1_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ ++#define FMC_ADDR1_ADDR GD_BITS(0,31) /*!< Flash erase/program command address bits */ + + /* FMC_WSEN */ + #define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ + #define FMC_WSEN_BPEN BIT(1) /*!< FMC bit program enable bit */ + + /* FMC_PID */ +-#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ ++#define FMC_PID_PID GD_BITS(0,31) /*!< product ID bits */ + + /* constants definitions */ + /* define the FMC bit position and its register index offset */ @@ -205,7 +205,7 @@ typedef enum - #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ - - /* FMC wait state counter */ --#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) -+#define WS_WSCNT(regval) (GD_BITS(0,2) & ((uint32_t)(regval))) - #define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ - #define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ - #define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ + #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ + + /* FMC wait state counter */ +-#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) ++#define WS_WSCNT(regval) (GD_BITS(0,2) & ((uint32_t)(regval))) + #define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ + #define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ + #define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h old mode 100644 new mode 100755 @@ -1637,31 +1637,31 @@ index eac3ec7..a849b30 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h @@ -51,13 +51,13 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* FWDGT_CTL */ --#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ -+#define FWDGT_CTL_CMD GD_BITS(0,15) /*!< FWDGT command value */ - - /* FWDGT_PSC */ --#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ -+#define FWDGT_PSC_PSC GD_BITS(0,2) /*!< FWDGT prescaler divider value */ - - /* FWDGT_RLD */ --#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ -+#define FWDGT_RLD_RLD GD_BITS(0,11) /*!< FWDGT counter reload value */ - - /* FWDGT_STAT */ - #define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ + + /* bits definitions */ + /* FWDGT_CTL */ +-#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ ++#define FWDGT_CTL_CMD GD_BITS(0,15) /*!< FWDGT command value */ + + /* FWDGT_PSC */ +-#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ ++#define FWDGT_PSC_PSC GD_BITS(0,2) /*!< FWDGT prescaler divider value */ + + /* FWDGT_RLD */ +-#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ ++#define FWDGT_RLD_RLD GD_BITS(0,11) /*!< FWDGT counter reload value */ + + /* FWDGT_STAT */ + #define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ @@ -65,7 +65,7 @@ OF SUCH DAMAGE. - - /* constants definitions */ - /* psc register value */ --#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -+#define PSC_PSC(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) - #define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ - #define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ - #define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ + + /* constants definitions */ + /* psc register value */ +-#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) ++#define PSC_PSC(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) + #define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ + #define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ + #define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h old mode 100644 new mode 100755 @@ -1669,225 +1669,225 @@ index 19d2626..c497ba8 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h @@ -75,40 +75,40 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* GPIO_CTL0 */ --#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ --#define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ --#define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ --#define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ --#define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */ --#define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */ --#define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */ --#define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */ --#define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */ --#define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */ --#define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */ --#define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */ --#define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */ --#define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */ --#define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */ --#define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ -+#define GPIO_CTL0_MD0 GD_BITS(0,1) /*!< port 0 mode bits */ -+#define GPIO_CTL0_CTL0 GD_BITS(2,3) /*!< pin 0 configuration bits */ -+#define GPIO_CTL0_MD1 GD_BITS(4,5) /*!< port 1 mode bits */ -+#define GPIO_CTL0_CTL1 GD_BITS(6,7) /*!< pin 1 configuration bits */ -+#define GPIO_CTL0_MD2 GD_BITS(8,9) /*!< port 2 mode bits */ -+#define GPIO_CTL0_CTL2 GD_BITS(10,11) /*!< pin 2 configuration bits */ -+#define GPIO_CTL0_MD3 GD_BITS(12,13) /*!< port 3 mode bits */ -+#define GPIO_CTL0_CTL3 GD_BITS(14,15) /*!< pin 3 configuration bits */ -+#define GPIO_CTL0_MD4 GD_BITS(16,17) /*!< port 4 mode bits */ -+#define GPIO_CTL0_CTL4 GD_BITS(18,19) /*!< pin 4 configuration bits */ -+#define GPIO_CTL0_MD5 GD_BITS(20,21) /*!< port 5 mode bits */ -+#define GPIO_CTL0_CTL5 GD_BITS(22,23) /*!< pin 5 configuration bits */ -+#define GPIO_CTL0_MD6 GD_BITS(24,25) /*!< port 6 mode bits */ -+#define GPIO_CTL0_CTL6 GD_BITS(26,27) /*!< pin 6 configuration bits */ -+#define GPIO_CTL0_MD7 GD_BITS(28,29) /*!< port 7 mode bits */ -+#define GPIO_CTL0_CTL7 GD_BITS(30,31) /*!< pin 7 configuration bits */ - - /* GPIO_CTL1 */ --#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ --#define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ --#define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ --#define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ --#define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */ --#define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */ --#define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */ --#define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */ --#define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */ --#define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */ --#define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */ --#define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */ --#define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */ --#define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */ --#define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */ --#define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ -+#define GPIO_CTL1_MD8 GD_BITS(0,1) /*!< port 8 mode bits */ -+#define GPIO_CTL1_CTL8 GD_BITS(2,3) /*!< pin 8 configuration bits */ -+#define GPIO_CTL1_MD9 GD_BITS(4,5) /*!< port 9 mode bits */ -+#define GPIO_CTL1_CTL9 GD_BITS(6,7) /*!< pin 9 configuration bits */ -+#define GPIO_CTL1_MD10 GD_BITS(8,9) /*!< port 10 mode bits */ -+#define GPIO_CTL1_CTL10 GD_BITS(10,11) /*!< pin 10 configuration bits */ -+#define GPIO_CTL1_MD11 GD_BITS(12,13) /*!< port 11 mode bits */ -+#define GPIO_CTL1_CTL11 GD_BITS(14,15) /*!< pin 11 configuration bits */ -+#define GPIO_CTL1_MD12 GD_BITS(16,17) /*!< port 12 mode bits */ -+#define GPIO_CTL1_CTL12 GD_BITS(18,19) /*!< pin 12 configuration bits */ -+#define GPIO_CTL1_MD13 GD_BITS(20,21) /*!< port 13 mode bits */ -+#define GPIO_CTL1_CTL13 GD_BITS(22,23) /*!< pin 13 configuration bits */ -+#define GPIO_CTL1_MD14 GD_BITS(24,25) /*!< port 14 mode bits */ -+#define GPIO_CTL1_CTL14 GD_BITS(26,27) /*!< pin 14 configuration bits */ -+#define GPIO_CTL1_MD15 GD_BITS(28,29) /*!< port 15 mode bits */ -+#define GPIO_CTL1_CTL15 GD_BITS(30,31) /*!< pin 15 configuration bits */ - - /* GPIO_ISTAT */ - #define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ + + /* bits definitions */ + /* GPIO_CTL0 */ +-#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ +-#define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ +-#define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ +-#define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ +-#define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */ +-#define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */ +-#define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */ +-#define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */ +-#define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */ +-#define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */ +-#define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */ +-#define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */ +-#define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */ +-#define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */ +-#define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */ +-#define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ ++#define GPIO_CTL0_MD0 GD_BITS(0,1) /*!< port 0 mode bits */ ++#define GPIO_CTL0_CTL0 GD_BITS(2,3) /*!< pin 0 configuration bits */ ++#define GPIO_CTL0_MD1 GD_BITS(4,5) /*!< port 1 mode bits */ ++#define GPIO_CTL0_CTL1 GD_BITS(6,7) /*!< pin 1 configuration bits */ ++#define GPIO_CTL0_MD2 GD_BITS(8,9) /*!< port 2 mode bits */ ++#define GPIO_CTL0_CTL2 GD_BITS(10,11) /*!< pin 2 configuration bits */ ++#define GPIO_CTL0_MD3 GD_BITS(12,13) /*!< port 3 mode bits */ ++#define GPIO_CTL0_CTL3 GD_BITS(14,15) /*!< pin 3 configuration bits */ ++#define GPIO_CTL0_MD4 GD_BITS(16,17) /*!< port 4 mode bits */ ++#define GPIO_CTL0_CTL4 GD_BITS(18,19) /*!< pin 4 configuration bits */ ++#define GPIO_CTL0_MD5 GD_BITS(20,21) /*!< port 5 mode bits */ ++#define GPIO_CTL0_CTL5 GD_BITS(22,23) /*!< pin 5 configuration bits */ ++#define GPIO_CTL0_MD6 GD_BITS(24,25) /*!< port 6 mode bits */ ++#define GPIO_CTL0_CTL6 GD_BITS(26,27) /*!< pin 6 configuration bits */ ++#define GPIO_CTL0_MD7 GD_BITS(28,29) /*!< port 7 mode bits */ ++#define GPIO_CTL0_CTL7 GD_BITS(30,31) /*!< pin 7 configuration bits */ + + /* GPIO_CTL1 */ +-#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ +-#define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ +-#define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ +-#define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ +-#define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */ +-#define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */ +-#define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */ +-#define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */ +-#define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */ +-#define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */ +-#define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */ +-#define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */ +-#define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */ +-#define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */ +-#define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */ +-#define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ ++#define GPIO_CTL1_MD8 GD_BITS(0,1) /*!< port 8 mode bits */ ++#define GPIO_CTL1_CTL8 GD_BITS(2,3) /*!< pin 8 configuration bits */ ++#define GPIO_CTL1_MD9 GD_BITS(4,5) /*!< port 9 mode bits */ ++#define GPIO_CTL1_CTL9 GD_BITS(6,7) /*!< pin 9 configuration bits */ ++#define GPIO_CTL1_MD10 GD_BITS(8,9) /*!< port 10 mode bits */ ++#define GPIO_CTL1_CTL10 GD_BITS(10,11) /*!< pin 10 configuration bits */ ++#define GPIO_CTL1_MD11 GD_BITS(12,13) /*!< port 11 mode bits */ ++#define GPIO_CTL1_CTL11 GD_BITS(14,15) /*!< pin 11 configuration bits */ ++#define GPIO_CTL1_MD12 GD_BITS(16,17) /*!< port 12 mode bits */ ++#define GPIO_CTL1_CTL12 GD_BITS(18,19) /*!< pin 12 configuration bits */ ++#define GPIO_CTL1_MD13 GD_BITS(20,21) /*!< port 13 mode bits */ ++#define GPIO_CTL1_CTL13 GD_BITS(22,23) /*!< pin 13 configuration bits */ ++#define GPIO_CTL1_MD14 GD_BITS(24,25) /*!< port 14 mode bits */ ++#define GPIO_CTL1_CTL14 GD_BITS(26,27) /*!< pin 14 configuration bits */ ++#define GPIO_CTL1_MD15 GD_BITS(28,29) /*!< port 15 mode bits */ ++#define GPIO_CTL1_CTL15 GD_BITS(30,31) /*!< pin 15 configuration bits */ + + /* GPIO_ISTAT */ + #define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ @@ -236,8 +236,8 @@ OF SUCH DAMAGE. - #define GPIO_SPD_SPD15 BIT(15) /*!< pin 15 set very high output speed when MDx is 0b11 */ - - /* AFIO_EC */ --#define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */ --#define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */ -+#define AFIO_EC_PIN GD_BITS(0,3) /*!< event output pin selection */ -+#define AFIO_EC_PORT GD_BITS(4,6) /*!< event output port selection */ - #define AFIO_EC_EOE BIT(7) /*!< event output enable */ - - /* AFIO_PCF0 */ + #define GPIO_SPD_SPD15 BIT(15) /*!< pin 15 set very high output speed when MDx is 0b11 */ + + /* AFIO_EC */ +-#define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */ +-#define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */ ++#define AFIO_EC_PIN GD_BITS(0,3) /*!< event output pin selection */ ++#define AFIO_EC_PORT GD_BITS(4,6) /*!< event output port selection */ + #define AFIO_EC_EOE BIT(7) /*!< event output enable */ + + /* AFIO_PCF0 */ @@ -247,18 +247,18 @@ OF SUCH DAMAGE. - #define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ - #define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ - #define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ --#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ --#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ --#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ --#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ -+#define AFIO_PCF0_USART2_REMAP GD_BITS(4,5) /*!< USART2 remapping */ -+#define AFIO_PCF0_TIMER0_REMAP GD_BITS(6,7) /*!< TIMER0 remapping */ -+#define AFIO_PCF0_TIMER1_REMAP GD_BITS(8,9) /*!< TIMER1 remapping */ -+#define AFIO_PCF0_TIMER2_REMAP GD_BITS(10,11) /*!< TIMER2 remapping */ - #define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ --#define AFIO_PCF0_CAN0_REMAP BITS(13,14) /*!< CAN0 remapping */ -+#define AFIO_PCF0_CAN0_REMAP GD_BITS(13,14) /*!< CAN0 remapping */ - #define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ - #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ - #define AFIO_PCF0_ENET_REMAP BIT(21) /*!< ethernet MAC I/O remapping */ - #define AFIO_PCF0_CAN1_REMAP BIT(22) /*!< CAN1 remapping */ - #define AFIO_PCF0_ENET_PHY_SEL BIT(23) /*!< ethernet MII or RMII PHY selection */ --#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ -+#define AFIO_PCF0_SWJ_CFG GD_BITS(24,26) /*!< serial wire JTAG configuration */ - #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ - #define AFIO_PCF0_TIMER1ITR0_REMAP BIT(29) /*!< TIMER1 internal trigger 0 remapping */ - #define AFIO_PCF0_PTP_PPS_REMAP BIT(30) /*!< ethernet PTP PPS remapping */ + #define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ + #define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ + #define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ +-#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ +-#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ +-#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ +-#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ ++#define AFIO_PCF0_USART2_REMAP GD_BITS(4,5) /*!< USART2 remapping */ ++#define AFIO_PCF0_TIMER0_REMAP GD_BITS(6,7) /*!< TIMER0 remapping */ ++#define AFIO_PCF0_TIMER1_REMAP GD_BITS(8,9) /*!< TIMER1 remapping */ ++#define AFIO_PCF0_TIMER2_REMAP GD_BITS(10,11) /*!< TIMER2 remapping */ + #define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ +-#define AFIO_PCF0_CAN0_REMAP BITS(13,14) /*!< CAN0 remapping */ ++#define AFIO_PCF0_CAN0_REMAP GD_BITS(13,14) /*!< CAN0 remapping */ + #define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ + #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ + #define AFIO_PCF0_ENET_REMAP BIT(21) /*!< ethernet MAC I/O remapping */ + #define AFIO_PCF0_CAN1_REMAP BIT(22) /*!< CAN1 remapping */ + #define AFIO_PCF0_ENET_PHY_SEL BIT(23) /*!< ethernet MII or RMII PHY selection */ +-#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ ++#define AFIO_PCF0_SWJ_CFG GD_BITS(24,26) /*!< serial wire JTAG configuration */ + #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ + #define AFIO_PCF0_TIMER1ITR0_REMAP BIT(29) /*!< TIMER1 internal trigger 0 remapping */ + #define AFIO_PCF0_PTP_PPS_REMAP BIT(30) /*!< ethernet PTP PPS remapping */ @@ -269,45 +269,45 @@ OF SUCH DAMAGE. - #define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ - #define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ - #define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ --#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ --#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ --#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ --#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ -+#define AFIO_PCF0_USART2_REMAP GD_BITS(4,5) /*!< USART2 remapping */ -+#define AFIO_PCF0_TIMER0_REMAP GD_BITS(6,7) /*!< TIMER0 remapping */ -+#define AFIO_PCF0_TIMER1_REMAP GD_BITS(8,9) /*!< TIMER1 remapping */ -+#define AFIO_PCF0_TIMER2_REMAP GD_BITS(10,11) /*!< TIMER2 remapping */ - #define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ --#define AFIO_PCF0_CAN_REMAP BITS(13,14) /*!< CAN remapping */ -+#define AFIO_PCF0_CAN_REMAP GD_BITS(13,14) /*!< CAN remapping */ - #define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ - #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ - #define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */ - #define AFIO_PCF0_ADC0_ETRGREG_REMAP BIT(18) /*!< ADC 0 external trigger regular conversion remapping */ - #define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */ - #define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */ --#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ -+#define AFIO_PCF0_SWJ_CFG GD_BITS(24,26) /*!< serial wire JTAG configuration */ - #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ - #endif /* GD32F30X_CL */ - - /* AFIO_EXTISS0 */ --#define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */ --#define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */ --#define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */ --#define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */ -+#define AFIO_EXTI0_SS GD_BITS(0,3) /*!< EXTI 0 sources selection */ -+#define AFIO_EXTI1_SS GD_BITS(4,7) /*!< EXTI 1 sources selection */ -+#define AFIO_EXTI2_SS GD_BITS(8,11) /*!< EXTI 2 sources selection */ -+#define AFIO_EXTI3_SS GD_BITS(12,15) /*!< EXTI 3 sources selection */ - - /* AFIO_EXTISS1 */ --#define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */ --#define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */ --#define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */ --#define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */ -+#define AFIO_EXTI4_SS GD_BITS(0,3) /*!< EXTI 4 sources selection */ -+#define AFIO_EXTI5_SS GD_BITS(4,7) /*!< EXTI 5 sources selection */ -+#define AFIO_EXTI6_SS GD_BITS(8,11) /*!< EXTI 6 sources selection */ -+#define AFIO_EXTI7_SS GD_BITS(12,15) /*!< EXTI 7 sources selection */ - - /* AFIO_EXTISS2 */ --#define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */ --#define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */ --#define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */ --#define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */ -+#define AFIO_EXTI8_SS GD_BITS(0,3) /*!< EXTI 8 sources selection */ -+#define AFIO_EXTI9_SS GD_BITS(4,7) /*!< EXTI 9 sources selection */ -+#define AFIO_EXTI10_SS GD_BITS(8,11) /*!< EXTI 10 sources selection */ -+#define AFIO_EXTI11_SS GD_BITS(12,15) /*!< EXTI 11 sources selection */ - - /* AFIO_EXTISS3 */ --#define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */ --#define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */ --#define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */ --#define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */ -+#define AFIO_EXTI12_SS GD_BITS(0,3) /*!< EXTI 12 sources selection */ -+#define AFIO_EXTI13_SS GD_BITS(4,7) /*!< EXTI 13 sources selection */ -+#define AFIO_EXTI14_SS GD_BITS(8,11) /*!< EXTI 14 sources selection */ -+#define AFIO_EXTI15_SS GD_BITS(12,15) /*!< EXTI 15 sources selection */ - - /* AFIO_PCF1 */ - #define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */ + #define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ + #define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ + #define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ +-#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ +-#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ +-#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ +-#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ ++#define AFIO_PCF0_USART2_REMAP GD_BITS(4,5) /*!< USART2 remapping */ ++#define AFIO_PCF0_TIMER0_REMAP GD_BITS(6,7) /*!< TIMER0 remapping */ ++#define AFIO_PCF0_TIMER1_REMAP GD_BITS(8,9) /*!< TIMER1 remapping */ ++#define AFIO_PCF0_TIMER2_REMAP GD_BITS(10,11) /*!< TIMER2 remapping */ + #define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ +-#define AFIO_PCF0_CAN_REMAP BITS(13,14) /*!< CAN remapping */ ++#define AFIO_PCF0_CAN_REMAP GD_BITS(13,14) /*!< CAN remapping */ + #define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ + #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ + #define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */ + #define AFIO_PCF0_ADC0_ETRGREG_REMAP BIT(18) /*!< ADC 0 external trigger regular conversion remapping */ + #define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */ + #define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */ +-#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ ++#define AFIO_PCF0_SWJ_CFG GD_BITS(24,26) /*!< serial wire JTAG configuration */ + #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ + #endif /* GD32F30X_CL */ + + /* AFIO_EXTISS0 */ +-#define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */ +-#define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */ +-#define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */ +-#define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */ ++#define AFIO_EXTI0_SS GD_BITS(0,3) /*!< EXTI 0 sources selection */ ++#define AFIO_EXTI1_SS GD_BITS(4,7) /*!< EXTI 1 sources selection */ ++#define AFIO_EXTI2_SS GD_BITS(8,11) /*!< EXTI 2 sources selection */ ++#define AFIO_EXTI3_SS GD_BITS(12,15) /*!< EXTI 3 sources selection */ + + /* AFIO_EXTISS1 */ +-#define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */ +-#define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */ +-#define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */ +-#define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */ ++#define AFIO_EXTI4_SS GD_BITS(0,3) /*!< EXTI 4 sources selection */ ++#define AFIO_EXTI5_SS GD_BITS(4,7) /*!< EXTI 5 sources selection */ ++#define AFIO_EXTI6_SS GD_BITS(8,11) /*!< EXTI 6 sources selection */ ++#define AFIO_EXTI7_SS GD_BITS(12,15) /*!< EXTI 7 sources selection */ + + /* AFIO_EXTISS2 */ +-#define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */ +-#define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */ +-#define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */ +-#define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */ ++#define AFIO_EXTI8_SS GD_BITS(0,3) /*!< EXTI 8 sources selection */ ++#define AFIO_EXTI9_SS GD_BITS(4,7) /*!< EXTI 9 sources selection */ ++#define AFIO_EXTI10_SS GD_BITS(8,11) /*!< EXTI 10 sources selection */ ++#define AFIO_EXTI11_SS GD_BITS(12,15) /*!< EXTI 11 sources selection */ + + /* AFIO_EXTISS3 */ +-#define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */ +-#define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */ +-#define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */ +-#define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */ ++#define AFIO_EXTI12_SS GD_BITS(0,3) /*!< EXTI 12 sources selection */ ++#define AFIO_EXTI13_SS GD_BITS(4,7) /*!< EXTI 13 sources selection */ ++#define AFIO_EXTI14_SS GD_BITS(8,11) /*!< EXTI 14 sources selection */ ++#define AFIO_EXTI15_SS GD_BITS(12,15) /*!< EXTI 15 sources selection */ + + /* AFIO_PCF1 */ + #define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */ @@ -316,7 +316,7 @@ OF SUCH DAMAGE. - #define AFIO_PCF1_TIMER12_REMAP BIT(8) /*!< TIMER12 remapping */ - #define AFIO_PCF1_TIMER13_REMAP BIT(9) /*!< TIMER13 remapping */ - #define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ --#define AFIO_PCF1_CTC_REMAP BITS(11,12) /*!< CTC remapping */ -+#define AFIO_PCF1_CTC_REMAP GD_BITS(11,12) /*!< CTC remapping */ - - /* AFIO_CPSCTL */ - #define AFIO_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ + #define AFIO_PCF1_TIMER12_REMAP BIT(8) /*!< TIMER12 remapping */ + #define AFIO_PCF1_TIMER13_REMAP BIT(9) /*!< TIMER13 remapping */ + #define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ +-#define AFIO_PCF1_CTC_REMAP BITS(11,12) /*!< CTC remapping */ ++#define AFIO_PCF1_CTC_REMAP GD_BITS(11,12) /*!< CTC remapping */ + + /* AFIO_CPSCTL */ + #define AFIO_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ @@ -414,16 +414,16 @@ typedef FlagStatus bit_status; - #define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ - #define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ - #define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ --#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ -+#define GPIO_PIN_ALL GD_BITS(0,15) /*!< GPIO pin all */ - - /* AFIO remap mask */ --#define PCF0_USART2_REMAP(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< USART2 remapping */ --#define PCF0_TIMER0_REMAP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< TIMER0 remapping */ --#define PCF0_TIMER1_REMAP(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< TIMER1 remapping */ --#define PCF0_TIMER2_REMAP(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< TIMER2 remapping */ --#define PCF0_CAN_REMAP(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< CAN remapping */ --#define PCF0_SWJ_CFG(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) /*!< serial wire JTAG configuration */ --#define PCF1_CTC_REMAP(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< CTC remapping */ -+#define PCF0_USART2_REMAP(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< USART2 remapping */ -+#define PCF0_TIMER0_REMAP(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< TIMER0 remapping */ -+#define PCF0_TIMER1_REMAP(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< TIMER1 remapping */ -+#define PCF0_TIMER2_REMAP(regval) (GD_BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< TIMER2 remapping */ -+#define PCF0_CAN_REMAP(regval) (GD_BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< CAN remapping */ -+#define PCF0_SWJ_CFG(regval) (GD_BITS(24,26) & ((uint32_t)(regval) << 24)) /*!< serial wire JTAG configuration */ -+#define PCF1_CTC_REMAP(regval) (GD_BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< CTC remapping */ - - /* GPIO remap definitions */ - #define GPIO_SPI0_REMAP AFIO_PCF0_SPI0_REMAP /*!< SPI0 remapping */ + #define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ + #define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ + #define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +-#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ ++#define GPIO_PIN_ALL GD_BITS(0,15) /*!< GPIO pin all */ + + /* AFIO remap mask */ +-#define PCF0_USART2_REMAP(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< USART2 remapping */ +-#define PCF0_TIMER0_REMAP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< TIMER0 remapping */ +-#define PCF0_TIMER1_REMAP(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< TIMER1 remapping */ +-#define PCF0_TIMER2_REMAP(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< TIMER2 remapping */ +-#define PCF0_CAN_REMAP(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< CAN remapping */ +-#define PCF0_SWJ_CFG(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) /*!< serial wire JTAG configuration */ +-#define PCF1_CTC_REMAP(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< CTC remapping */ ++#define PCF0_USART2_REMAP(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< USART2 remapping */ ++#define PCF0_TIMER0_REMAP(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< TIMER0 remapping */ ++#define PCF0_TIMER1_REMAP(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< TIMER1 remapping */ ++#define PCF0_TIMER2_REMAP(regval) (GD_BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< TIMER2 remapping */ ++#define PCF0_CAN_REMAP(regval) (GD_BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< CAN remapping */ ++#define PCF0_SWJ_CFG(regval) (GD_BITS(24,26) & ((uint32_t)(regval) << 24)) /*!< serial wire JTAG configuration */ ++#define PCF1_CTC_REMAP(regval) (GD_BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< CTC remapping */ + + /* GPIO remap definitions */ + #define GPIO_SPI0_REMAP AFIO_PCF0_SPI0_REMAP /*!< SPI0 remapping */ @@ -495,6 +495,8 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin - void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); - /* reset GPIO pin bit */ - void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); -+/* toggle GPIO pin */ -+void gpio_bit_toggle(uint32_t gpio_periph,uint32_t pin); - /* write data to the specified GPIO pin */ - void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); - /* write data to the specified GPIO port */ + void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); + /* reset GPIO pin bit */ + void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); ++/* toggle GPIO pin */ ++void gpio_bit_toggle(uint32_t gpio_periph,uint32_t pin); + /* write data to the specified GPIO pin */ + void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); + /* write data to the specified GPIO port */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h old mode 100644 new mode 100755 @@ -1895,63 +1895,63 @@ index bb12927..fccf4e1 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h @@ -75,7 +75,7 @@ OF SUCH DAMAGE. - #define I2C_CTL0_SRESET BIT(15) /*!< software reset */ - - /* I2Cx_CTL1 */ --#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */ -+#define I2C_CTL1_I2CCLK GD_BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */ - #define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */ - #define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ - #define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ + #define I2C_CTL0_SRESET BIT(15) /*!< software reset */ + + /* I2Cx_CTL1 */ +-#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */ ++#define I2C_CTL1_I2CCLK GD_BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */ + #define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */ + #define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ + #define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ @@ -84,16 +84,16 @@ OF SUCH DAMAGE. - - /* I2Cx_SADDR0 */ - #define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ --#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ --#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -+#define I2C_SADDR0_ADDRESS GD_BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -+#define I2C_SADDR0_ADDRESS_H GD_BITS(8,9) /*!< highest two bits of a 10-bit address */ - #define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ - - /* I2Cx_SADDR1 */ - #define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ --#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ -+#define I2C_SADDR1_ADDRESS2 GD_BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ - - /* I2Cx_DATA */ --#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ -+#define I2C_DATA_TRB GD_BITS(0,7) /*!< 8-bit data register */ - - /* I2Cx_STAT0 */ - #define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ + + /* I2Cx_SADDR0 */ + #define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +-#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +-#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ ++#define I2C_SADDR0_ADDRESS GD_BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ ++#define I2C_SADDR0_ADDRESS_H GD_BITS(8,9) /*!< highest two bits of a 10-bit address */ + #define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ + + /* I2Cx_SADDR1 */ + #define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +-#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ ++#define I2C_SADDR1_ADDRESS2 GD_BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ + + /* I2Cx_DATA */ +-#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ ++#define I2C_DATA_TRB GD_BITS(0,7) /*!< 8-bit data register */ + + /* I2Cx_STAT0 */ + #define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ @@ -119,15 +119,15 @@ OF SUCH DAMAGE. - #define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ - #define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ - #define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ --#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ -+#define I2C_STAT1_PECV GD_BITS(8,15) /*!< packet error checking value */ - - /* I2Cx_CKCFG */ --#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ -+#define I2C_CKCFG_CLKC GD_BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ - #define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ - #define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ - - /* I2Cx_RT */ --#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ -+#define I2C_RT_RISETIME GD_BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ - - /* I2Cx_FMPCFG */ - #define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ + #define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ + #define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ + #define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +-#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ ++#define I2C_STAT1_PECV GD_BITS(8,15) /*!< packet error checking value */ + + /* I2Cx_CKCFG */ +-#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ ++#define I2C_CKCFG_CLKC GD_BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ + #define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ + #define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ + + /* I2Cx_RT */ +-#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ ++#define I2C_RT_RISETIME GD_BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ + + /* I2Cx_FMPCFG */ + #define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ @@ -272,7 +272,7 @@ typedef enum - #define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */ - - /* transmit I2C data */ --#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) -+#define DATA_TRANS(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) - - /* receive I2C data */ - #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) + #define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */ + + /* transmit I2C data */ +-#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) ++#define DATA_TRANS(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) + + /* receive I2C data */ + #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h old mode 100644 new mode 100755 @@ -1959,55 +1959,55 @@ index 030f696..efde2dd --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h @@ -55,14 +55,14 @@ OF SUCH DAMAGE. - #define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ - #define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ - #define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ --#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ -+#define PMU_CTL_LVDT GD_BITS(5,7) /*!< low voltage detector threshold */ - #define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ - #define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ - #define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ --#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ -+#define PMU_CTL_LDOVS GD_BITS(14,15) /*!< LDO output voltage select */ - #define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ - #define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ --#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ -+#define PMU_CTL_LDEN GD_BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ - - /* PMU_CS */ - #define PMU_CS_WUF BIT(0) /*!< wakeup flag */ + #define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ + #define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ + #define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +-#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ ++#define PMU_CTL_LVDT GD_BITS(5,7) /*!< low voltage detector threshold */ + #define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ + #define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ + #define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ +-#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ ++#define PMU_CTL_LDOVS GD_BITS(14,15) /*!< LDO output voltage select */ + #define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ + #define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ +-#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ ++#define PMU_CTL_LDEN GD_BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ + + /* PMU_CS */ + #define PMU_CS_WUF BIT(0) /*!< wakeup flag */ @@ -72,11 +72,11 @@ OF SUCH DAMAGE. - #define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ - #define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ - #define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ --#define PMU_CS_LDRF BITS(18,19) /*!< Low-driver mode ready flag */ -+#define PMU_CS_LDRF GD_BITS(18,19) /*!< Low-driver mode ready flag */ - - /* constants definitions */ - /* PMU low voltage detector threshold definitions */ --#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) -+#define CTL_LVDT(regval) (GD_BITS(5,7)&((uint32_t)(regval)<<5)) - #define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ - #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ - #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ + #define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ + #define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ + #define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ +-#define PMU_CS_LDRF BITS(18,19) /*!< Low-driver mode ready flag */ ++#define PMU_CS_LDRF GD_BITS(18,19) /*!< Low-driver mode ready flag */ + + /* constants definitions */ + /* PMU low voltage detector threshold definitions */ +-#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) ++#define CTL_LVDT(regval) (GD_BITS(5,7)&((uint32_t)(regval)<<5)) + #define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ + #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ + #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ @@ -87,7 +87,7 @@ OF SUCH DAMAGE. - #define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ - - /* PMU LDO output voltage select definitions */ --#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) -+#define CTL_LDOVS(regval) (GD_BITS(14,15)&((uint32_t)(regval)<<14)) - #define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ - #define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ - #define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ + #define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ + + /* PMU LDO output voltage select definitions */ +-#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) ++#define CTL_LDOVS(regval) (GD_BITS(14,15)&((uint32_t)(regval)<<14)) + #define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ + #define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ + #define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ @@ -108,7 +108,7 @@ OF SUCH DAMAGE. - #define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ - - /* PMU low power mode ready flag definitions */ --#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) -+#define CS_LDRF(regval) (GD_BITS(18,19)&((uint32_t)(regval)<<18)) - #define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */ - #define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ - + #define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ + + /* PMU low power mode ready flag definitions */ +-#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) ++#define CS_LDRF(regval) (GD_BITS(18,19)&((uint32_t)(regval)<<18)) + #define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */ + #define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ + diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h old mode 100644 new mode 100755 @@ -2015,250 +2015,250 @@ index 3e293c1..9ab7ade --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h @@ -86,8 +86,8 @@ OF SUCH DAMAGE. - #if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ - #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ --#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ --#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -+#define RCU_CTL_IRC8MADJ GD_BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -+#define RCU_CTL_IRC8MCALIB GD_BITS(8,15) /*!< high speed internal oscillator calibration value register */ - #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ - #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ - #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ + #if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ + #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +-#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +-#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ ++#define RCU_CTL_IRC8MADJ GD_BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ ++#define RCU_CTL_IRC8MCALIB GD_BITS(8,15) /*!< high speed internal oscillator calibration value register */ + #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ + #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ + #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ @@ -97,8 +97,8 @@ OF SUCH DAMAGE. - #elif defined(GD32F30X_CL) - #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ - #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ --#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ --#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -+#define RCU_CTL_IRC8MADJ GD_BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -+#define RCU_CTL_IRC8MCALIB GD_BITS(8,15) /*!< high speed internal oscillator calibration value register */ - #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ - #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ - #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ + #elif defined(GD32F30X_CL) + #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ + #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +-#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +-#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ ++#define RCU_CTL_IRC8MADJ GD_BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ ++#define RCU_CTL_IRC8MCALIB GD_BITS(8,15) /*!< high speed internal oscillator calibration value register */ + #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ + #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ + #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ @@ -113,33 +113,33 @@ OF SUCH DAMAGE. - - /* RCU_CFG0 */ - #if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) --#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ --#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ --#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ --#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ --#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ --#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ -+#define RCU_CFG0_SCS GD_BITS(0,1) /*!< system clock switch */ -+#define RCU_CFG0_SCSS GD_BITS(2,3) /*!< system clock switch status */ -+#define RCU_CFG0_AHBPSC GD_BITS(4,7) /*!< AHB prescaler selection */ -+#define RCU_CFG0_APB1PSC GD_BITS(8,10) /*!< APB1 prescaler selection */ -+#define RCU_CFG0_APB2PSC GD_BITS(11,13) /*!< APB2 prescaler selection */ -+#define RCU_CFG0_ADCPSC GD_BITS(14,15) /*!< ADC prescaler selection */ - #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ - #define RCU_CFG0_PREDV0 BIT(17) /*!< PREDV0 division factor */ --#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ --#define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */ --#define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CKOUT0 clock source selection */ -+#define RCU_CFG0_PLLMF GD_BITS(18,21) /*!< PLL clock multiplication factor */ -+#define RCU_CFG0_USBDPSC GD_BITS(22,23) /*!< USBD clock prescaler selection */ -+#define RCU_CFG0_CKOUT0SEL GD_BITS(24,26) /*!< CKOUT0 clock source selection */ - #define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */ - #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ - #define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ - #define RCU_CFG0_USBDPSC_2 BIT(31) /*!< bit 2 of USBDPSC */ - #elif defined(GD32F30X_CL) --#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ --#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ --#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ --#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ --#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ --#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ -+#define RCU_CFG0_SCS GD_BITS(0,1) /*!< system clock switch */ -+#define RCU_CFG0_SCSS GD_BITS(2,3) /*!< system clock switch status */ -+#define RCU_CFG0_AHBPSC GD_BITS(4,7) /*!< AHB prescaler selection */ -+#define RCU_CFG0_APB1PSC GD_BITS(8,10) /*!< APB1 prescaler selection */ -+#define RCU_CFG0_APB2PSC GD_BITS(11,13) /*!< APB2 prescaler selection */ -+#define RCU_CFG0_ADCPSC GD_BITS(14,15) /*!< ADC prescaler selection */ - #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ - #define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ --#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ --#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ --#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ -+#define RCU_CFG0_PLLMF GD_BITS(18,21) /*!< PLL clock multiplication factor */ -+#define RCU_CFG0_USBFSPSC GD_BITS(22,23) /*!< USBFS clock prescaler selection */ -+#define RCU_CFG0_CKOUT0SEL GD_BITS(24,27) /*!< CKOUT0 clock source selection */ - #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ - #define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ - #define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ + + /* RCU_CFG0 */ + #if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +-#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +-#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +-#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +-#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +-#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +-#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ ++#define RCU_CFG0_SCS GD_BITS(0,1) /*!< system clock switch */ ++#define RCU_CFG0_SCSS GD_BITS(2,3) /*!< system clock switch status */ ++#define RCU_CFG0_AHBPSC GD_BITS(4,7) /*!< AHB prescaler selection */ ++#define RCU_CFG0_APB1PSC GD_BITS(8,10) /*!< APB1 prescaler selection */ ++#define RCU_CFG0_APB2PSC GD_BITS(11,13) /*!< APB2 prescaler selection */ ++#define RCU_CFG0_ADCPSC GD_BITS(14,15) /*!< ADC prescaler selection */ + #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ + #define RCU_CFG0_PREDV0 BIT(17) /*!< PREDV0 division factor */ +-#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +-#define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */ +-#define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CKOUT0 clock source selection */ ++#define RCU_CFG0_PLLMF GD_BITS(18,21) /*!< PLL clock multiplication factor */ ++#define RCU_CFG0_USBDPSC GD_BITS(22,23) /*!< USBD clock prescaler selection */ ++#define RCU_CFG0_CKOUT0SEL GD_BITS(24,26) /*!< CKOUT0 clock source selection */ + #define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */ + #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ + #define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ + #define RCU_CFG0_USBDPSC_2 BIT(31) /*!< bit 2 of USBDPSC */ + #elif defined(GD32F30X_CL) +-#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +-#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +-#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +-#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +-#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +-#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ ++#define RCU_CFG0_SCS GD_BITS(0,1) /*!< system clock switch */ ++#define RCU_CFG0_SCSS GD_BITS(2,3) /*!< system clock switch status */ ++#define RCU_CFG0_AHBPSC GD_BITS(4,7) /*!< AHB prescaler selection */ ++#define RCU_CFG0_APB1PSC GD_BITS(8,10) /*!< APB1 prescaler selection */ ++#define RCU_CFG0_APB2PSC GD_BITS(11,13) /*!< APB2 prescaler selection */ ++#define RCU_CFG0_ADCPSC GD_BITS(14,15) /*!< ADC prescaler selection */ + #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ + #define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ +-#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +-#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ +-#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ ++#define RCU_CFG0_PLLMF GD_BITS(18,21) /*!< PLL clock multiplication factor */ ++#define RCU_CFG0_USBFSPSC GD_BITS(22,23) /*!< USBFS clock prescaler selection */ ++#define RCU_CFG0_CKOUT0SEL GD_BITS(24,27) /*!< CKOUT0 clock source selection */ + #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ + #define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ + #define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ @@ -323,8 +323,8 @@ OF SUCH DAMAGE. - #define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ - #define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ - #define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ --#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ --#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ -+#define RCU_BDCTL_LXTALDRI GD_BITS(3,4) /*!< LXTAL drive capability */ -+#define RCU_BDCTL_RTCSRC GD_BITS(8,9) /*!< RTC clock entry selection */ - #define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ - #define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ - + #define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ + #define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ + #define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +-#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ +-#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ ++#define RCU_BDCTL_LXTALDRI GD_BITS(3,4) /*!< LXTAL drive capability */ ++#define RCU_BDCTL_RTCSRC GD_BITS(8,9) /*!< RTC clock entry selection */ + #define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ + #define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + @@ -350,10 +350,10 @@ OF SUCH DAMAGE. - #define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */ - #define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ - #elif defined(GD32F30X_CL) --#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ --#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ --#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ --#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ -+#define RCU_CFG1_PREDV0 GD_BITS(0,3) /*!< PREDV0 division factor */ -+#define RCU_CFG1_PREDV1 GD_BITS(4,7) /*!< PREDV1 division factor */ -+#define RCU_CFG1_PLL1MF GD_BITS(8,11) /*!< PLL1 clock multiplication factor */ -+#define RCU_CFG1_PLL2MF GD_BITS(12,15) /*!< PLL2 clock multiplication factor */ - #define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ - #define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ - #define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ + #define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */ + #define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ + #elif defined(GD32F30X_CL) +-#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ +-#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ +-#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ +-#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ ++#define RCU_CFG1_PREDV0 GD_BITS(0,3) /*!< PREDV0 division factor */ ++#define RCU_CFG1_PREDV1 GD_BITS(4,7) /*!< PREDV1 division factor */ ++#define RCU_CFG1_PLL1MF GD_BITS(8,11) /*!< PLL1 clock multiplication factor */ ++#define RCU_CFG1_PLL2MF GD_BITS(12,15) /*!< PLL2 clock multiplication factor */ + #define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ + #define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ + #define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ @@ -363,13 +363,13 @@ OF SUCH DAMAGE. - #endif /* GD32F30X_HD and GD32F30X_XD */ - - /* RCU_DSV */ --#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ -+#define RCU_DSV_DSLPVS GD_BITS(0,2) /*!< deep-sleep mode voltage select */ - - /* RCU_ADDCTL */ - #define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */ - #define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ - #define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ --#define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ -+#define RCU_ADDCTL_IRC48MCAL GD_BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ - - /* RCU_ADDINT */ - #define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ + #endif /* GD32F30X_HD and GD32F30X_XD */ + + /* RCU_DSV */ +-#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ ++#define RCU_DSV_DSLPVS GD_BITS(0,2) /*!< deep-sleep mode voltage select */ + + /* RCU_ADDCTL */ + #define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */ + #define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ + #define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ +-#define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ ++#define RCU_ADDCTL_IRC48MCAL GD_BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ + + /* RCU_ADDINT */ + #define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ @@ -663,19 +663,19 @@ typedef enum - - /* RCU_CFG0 register bit define */ - /* system clock source select */ --#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -+#define CFG0_SCS(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) - #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ - #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ - #define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ - - /* system clock source select status */ --#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -+#define CFG0_SCSS(regval) (GD_BITS(2,3) & ((uint32_t)(regval) << 2)) - #define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ - #define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ - #define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ - - /* AHB prescaler selection */ --#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -+#define CFG0_AHBPSC(regval) (GD_BITS(4,7) & ((uint32_t)(regval) << 4)) - #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ - #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ - #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ + + /* RCU_CFG0 register bit define */ + /* system clock source select */ +-#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) ++#define CFG0_SCS(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) + #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ + #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ + #define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ + + /* system clock source select status */ +-#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) ++#define CFG0_SCSS(regval) (GD_BITS(2,3) & ((uint32_t)(regval) << 2)) + #define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ + #define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ + #define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ + + /* AHB prescaler selection */ +-#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) ++#define CFG0_AHBPSC(regval) (GD_BITS(4,7) & ((uint32_t)(regval) << 4)) + #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ + #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ + #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ @@ -687,7 +687,7 @@ typedef enum - #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ - - /* APB1 prescaler selection */ --#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) -+#define CFG0_APB1PSC(regval) (GD_BITS(8,10) & ((uint32_t)(regval) << 8)) - #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ - #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ - #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ + #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + + /* APB1 prescaler selection */ +-#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) ++#define CFG0_APB1PSC(regval) (GD_BITS(8,10) & ((uint32_t)(regval) << 8)) + #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ + #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ + #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ @@ -695,7 +695,7 @@ typedef enum - #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ - - /* APB2 prescaler selection */ --#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) -+#define CFG0_APB2PSC(regval) (GD_BITS(11,13) & ((uint32_t)(regval) << 11)) - #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ - #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ - #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ + #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + + /* APB2 prescaler selection */ +-#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) ++#define CFG0_APB2PSC(regval) (GD_BITS(11,13) & ((uint32_t)(regval) << 11)) + #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ + #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ + #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ @@ -723,7 +723,7 @@ typedef enum - #define PLLMF_5 RCU_CFG0_PLLMF_5 /* bit 5 of PLLMF */ - #define PLLMF_4_5 (PLLMF_4 | PLLMF_5) /* bit 4 and 5 of PLLMF */ - --#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) -+#define CFG0_PLLMF(regval) (GD_BITS(18,21) & ((uint32_t)(regval) << 18)) - #define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ - #define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ - #define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ + #define PLLMF_5 RCU_CFG0_PLLMF_5 /* bit 5 of PLLMF */ + #define PLLMF_4_5 (PLLMF_4 | PLLMF_5) /* bit 4 and 5 of PLLMF */ + +-#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) ++#define CFG0_PLLMF(regval) (GD_BITS(18,21) & ((uint32_t)(regval) << 18)) + #define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ + #define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ + #define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ @@ -798,7 +798,7 @@ typedef enum - #endif /* GD32F30X_HD and GD32F30X_XD */ - - /* USBD/USBFS prescaler select */ --#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) -+#define CFG0_USBPSC(regval) (GD_BITS(22,23) & ((uint32_t)(regval) << 22)) - #define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBD/USBFS prescaler select CK_PLL/1.5 */ - #define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBD/USBFS prescaler select CK_PLL/1 */ - #define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBD/USBFS prescaler select CK_PLL/2.5 */ + #endif /* GD32F30X_HD and GD32F30X_XD */ + + /* USBD/USBFS prescaler select */ +-#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) ++#define CFG0_USBPSC(regval) (GD_BITS(22,23) & ((uint32_t)(regval) << 22)) + #define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBD/USBFS prescaler select CK_PLL/1.5 */ + #define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBD/USBFS prescaler select CK_PLL/1 */ + #define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBD/USBFS prescaler select CK_PLL/2.5 */ @@ -808,7 +808,7 @@ typedef enum - #define RCU_CKUSB_CKPLL_DIV4 (USBPSC_2 |CFG0_USBPSC(2)) /*!< USBD/USBFS prescaler select CK_PLL/4 */ - - /* CKOUT0 Clock source selection */ --#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -+#define CFG0_CKOUT0SEL(regval) (GD_BITS(24,27) & ((uint32_t)(regval) << 24)) - #define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ - #define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ - #define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ + #define RCU_CKUSB_CKPLL_DIV4 (USBPSC_2 |CFG0_USBPSC(2)) /*!< USBD/USBFS prescaler select CK_PLL/4 */ + + /* CKOUT0 Clock source selection */ +-#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) ++#define CFG0_CKOUT0SEL(regval) (GD_BITS(24,27) & ((uint32_t)(regval) << 24)) + #define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ + #define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ + #define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ @@ -822,21 +822,21 @@ typedef enum - #endif /* GD32F30X_CL */ - - /* LXTAL drive capability */ --#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) -+#define BDCTL_LXTALDRI(regval) (GD_BITS(3,4) & ((uint32_t)(regval) << 3)) - #define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ - #define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ - #define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ - #define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ - - /* RTC clock entry selection */ --#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -+#define BDCTL_RTCSRC(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) - #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ - #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ - #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ - #define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ - - /* PREDV0 division factor */ --#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -+#define CFG1_PREDV0(regval) (GD_BITS(0,3) & ((uint32_t)(regval) << 0)) - #define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ - #define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ - #define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ + #endif /* GD32F30X_CL */ + + /* LXTAL drive capability */ +-#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) ++#define BDCTL_LXTALDRI(regval) (GD_BITS(3,4) & ((uint32_t)(regval) << 3)) + #define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ + #define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ + #define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ + #define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ + + /* RTC clock entry selection */ +-#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) ++#define BDCTL_RTCSRC(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) + #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ + #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ + #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ + #define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ + + /* PREDV0 division factor */ +-#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) ++#define CFG1_PREDV0(regval) (GD_BITS(0,3) & ((uint32_t)(regval) << 0)) + #define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ + #define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ + #define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ @@ -855,7 +855,7 @@ typedef enum - #define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ - - /* PREDV1 division factor */ --#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -+#define CFG1_PREDV1(regval) (GD_BITS(4,7) & ((uint32_t)(regval) << 4)) - #define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ - #define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ - #define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ + #define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ + + /* PREDV1 division factor */ +-#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) ++#define CFG1_PREDV1(regval) (GD_BITS(4,7) & ((uint32_t)(regval) << 4)) + #define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ + #define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ + #define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ @@ -874,7 +874,7 @@ typedef enum - #define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ - - /* PLL1 clock multiplication factor */ --#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -+#define CFG1_PLL1MF(regval) (GD_BITS(8,11) & ((uint32_t)(regval) << 8)) - #define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ - #define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ - #define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ + #define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ + + /* PLL1 clock multiplication factor */ +-#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) ++#define CFG1_PLL1MF(regval) (GD_BITS(8,11) & ((uint32_t)(regval) << 8)) + #define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ + #define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ + #define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ @@ -889,7 +889,7 @@ typedef enum - /* PLL2 clock multiplication factor */ - #define PLL2MF_4 RCU_CFG1_PLL2MF_4 /* bit 4 of PLL2MF */ - --#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) -+#define CFG1_PLL2MF(regval) (GD_BITS(12,15) & ((uint32_t)(regval) << 12)) - #define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ - #define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ - #define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ + /* PLL2 clock multiplication factor */ + #define PLL2MF_4 RCU_CFG1_PLL2MF_4 /* bit 4 of PLL2MF */ + +-#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) ++#define CFG1_PLL2MF(regval) (GD_BITS(12,15) & ((uint32_t)(regval) << 12)) + #define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ + #define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ + #define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ @@ -935,7 +935,7 @@ typedef enum - #define RCU_PLLPRESRC_IRC48M RCU_CFG1_PLLPRESEL /*!< CK_PLL selected as PREDV0 input source clock */ - - /* deep-sleep mode voltage */ --#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -+#define DSV_DSLPVS(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) - #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ - #define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ - #define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ + #define RCU_PLLPRESRC_IRC48M RCU_CFG1_PLLPRESEL /*!< CK_PLL selected as PREDV0 input source clock */ + + /* deep-sleep mode voltage */ +-#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) ++#define DSV_DSLPVS(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) + #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ + #define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ + #define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h old mode 100644 new mode 100755 @@ -2266,34 +2266,34 @@ index 68bc90e..e8d490a --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h @@ -71,20 +71,20 @@ OF SUCH DAMAGE. - #define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ - - /* RTC_PSC */ --#define RTC_PSCH_PSC BITS(0, 3) /*!< prescaler high value */ --#define RTC_PSCL_PSC BITS(0, 15) /*!< prescaler low value */ -+#define RTC_PSCH_PSC GD_BITS(0, 3) /*!< prescaler high value */ -+#define RTC_PSCL_PSC GD_BITS(0, 15) /*!< prescaler low value */ - - /* RTC_DIV */ --#define RTC_DIVH_DIV BITS(0, 3) /*!< divider high value */ --#define RTC_DIVL_DIV BITS(0, 15) /*!< divider low value */ -+#define RTC_DIVH_DIV GD_BITS(0, 3) /*!< divider high value */ -+#define RTC_DIVL_DIV GD_BITS(0, 15) /*!< divider low value */ - - /* RTC_CNT */ --#define RTC_CNTH_CNT BITS(0, 15) /*!< counter high value */ --#define RTC_CNTL_CNT BITS(0, 15) /*!< counter low value */ -+#define RTC_CNTH_CNT GD_BITS(0, 15) /*!< counter high value */ -+#define RTC_CNTL_CNT GD_BITS(0, 15) /*!< counter low value */ - - /* RTC_ALRM */ --#define RTC_ALRMH_ALRM BITS(0, 15) /*!< alarm high value */ --#define RTC_ALRML_ALRM BITS(0, 15) /*!< alarm low value */ -+#define RTC_ALRMH_ALRM GD_BITS(0, 15) /*!< alarm high value */ -+#define RTC_ALRML_ALRM GD_BITS(0, 15) /*!< alarm low value */ - - /* constants definitions */ - #define RTC_HIGH_VALUE 0x000F0000U /*!< RTC high value */ + #define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ + + /* RTC_PSC */ +-#define RTC_PSCH_PSC BITS(0, 3) /*!< prescaler high value */ +-#define RTC_PSCL_PSC BITS(0, 15) /*!< prescaler low value */ ++#define RTC_PSCH_PSC GD_BITS(0, 3) /*!< prescaler high value */ ++#define RTC_PSCL_PSC GD_BITS(0, 15) /*!< prescaler low value */ + + /* RTC_DIV */ +-#define RTC_DIVH_DIV BITS(0, 3) /*!< divider high value */ +-#define RTC_DIVL_DIV BITS(0, 15) /*!< divider low value */ ++#define RTC_DIVH_DIV GD_BITS(0, 3) /*!< divider high value */ ++#define RTC_DIVL_DIV GD_BITS(0, 15) /*!< divider low value */ + + /* RTC_CNT */ +-#define RTC_CNTH_CNT BITS(0, 15) /*!< counter high value */ +-#define RTC_CNTL_CNT BITS(0, 15) /*!< counter low value */ ++#define RTC_CNTH_CNT GD_BITS(0, 15) /*!< counter high value */ ++#define RTC_CNTL_CNT GD_BITS(0, 15) /*!< counter low value */ + + /* RTC_ALRM */ +-#define RTC_ALRMH_ALRM BITS(0, 15) /*!< alarm high value */ +-#define RTC_ALRML_ALRM BITS(0, 15) /*!< alarm low value */ ++#define RTC_ALRMH_ALRM GD_BITS(0, 15) /*!< alarm high value */ ++#define RTC_ALRML_ALRM GD_BITS(0, 15) /*!< alarm low value */ + + /* constants definitions */ + #define RTC_HIGH_VALUE 0x000F0000U /*!< RTC high value */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h old mode 100644 new mode 100755 @@ -2301,99 +2301,99 @@ index acc4e93..46d7a85 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h @@ -65,24 +65,24 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* SDIO_PWRCTL */ --#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */ -+#define SDIO_PWRCTL_PWRCTL GD_BITS(0,1) /*!< SDIO power control bits */ - - /* SDIO_CLKCTL */ --#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */ -+#define SDIO_CLKCTL_DIV GD_BITS(0,7) /*!< clock division */ - #define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */ - #define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */ - #define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */ --#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */ -+#define SDIO_CLKCTL_BUSMODE GD_BITS(11,12) /*!< SDIO card bus mode control bit */ - #define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */ - #define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */ - #define SDIO_CLKCTL_DIV8 BIT(31) /*!< MSB of clock division */ - - /* SDIO_CMDAGMT */ --#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */ -+#define SDIO_CMDAGMT_CMDAGMT GD_BITS(0,31) /*!< SDIO card command argument */ - - /* SDIO_CMDCTL */ --#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */ --#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */ -+#define SDIO_CMDCTL_CMDIDX GD_BITS(0,5) /*!< command index */ -+#define SDIO_CMDCTL_CMDRESP GD_BITS(6,7) /*!< command response type bits */ - #define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */ - #define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */ - #define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */ + + /* bits definitions */ + /* SDIO_PWRCTL */ +-#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */ ++#define SDIO_PWRCTL_PWRCTL GD_BITS(0,1) /*!< SDIO power control bits */ + + /* SDIO_CLKCTL */ +-#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */ ++#define SDIO_CLKCTL_DIV GD_BITS(0,7) /*!< clock division */ + #define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */ + #define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */ + #define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */ +-#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */ ++#define SDIO_CLKCTL_BUSMODE GD_BITS(11,12) /*!< SDIO card bus mode control bit */ + #define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */ + #define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */ + #define SDIO_CLKCTL_DIV8 BIT(31) /*!< MSB of clock division */ + + /* SDIO_CMDAGMT */ +-#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */ ++#define SDIO_CMDAGMT_CMDAGMT GD_BITS(0,31) /*!< SDIO card command argument */ + + /* SDIO_CMDCTL */ +-#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */ +-#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */ ++#define SDIO_CMDCTL_CMDIDX GD_BITS(0,5) /*!< command index */ ++#define SDIO_CMDCTL_CMDRESP GD_BITS(6,7) /*!< command response type bits */ + #define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */ + #define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */ + #define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */ @@ -92,17 +92,17 @@ OF SUCH DAMAGE. - #define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */ - - /* SDIO_DATATO */ --#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */ -+#define SDIO_DATATO_DATATO GD_BITS(0,31) /*!< data timeout period */ - - /* SDIO_DATALEN */ --#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */ -+#define SDIO_DATALEN_DATALEN GD_BITS(0,24) /*!< data transfer length */ - - /* SDIO_DATACTL */ - #define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */ - #define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */ - #define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */ - #define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */ --#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */ -+#define SDIO_DATACTL_BLKSZ GD_BITS(4,7) /*!< data block size */ - #define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */ - #define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */ - #define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */ + #define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */ + + /* SDIO_DATATO */ +-#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */ ++#define SDIO_DATATO_DATATO GD_BITS(0,31) /*!< data timeout period */ + + /* SDIO_DATALEN */ +-#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */ ++#define SDIO_DATALEN_DATALEN GD_BITS(0,24) /*!< data transfer length */ + + /* SDIO_DATACTL */ + #define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */ + #define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */ + #define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */ + #define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */ +-#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */ ++#define SDIO_DATACTL_BLKSZ GD_BITS(4,7) /*!< data block size */ + #define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */ + #define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */ + #define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */ @@ -176,7 +176,7 @@ OF SUCH DAMAGE. - #define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */ - - /* SDIO_FIFO */ --#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */ -+#define SDIO_FIFO_FIFODT GD_BITS(0,31) /*!< receive FIFO data or transmit FIFO data */ - - /* constants definitions */ - /* SDIO flags */ + #define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */ + + /* SDIO_FIFO */ +-#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */ ++#define SDIO_FIFO_FIFODT GD_BITS(0,31) /*!< receive FIFO data or transmit FIFO data */ + + /* constants definitions */ + /* SDIO flags */ @@ -258,12 +258,12 @@ OF SUCH DAMAGE. - #define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt flag */ - - /* SDIO power control */ --#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -+#define PWRCTL_PWRCTL(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) - #define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */ - #define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */ - - /* SDIO card bus mode control */ --#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) -+#define CLKCTL_BUSMODE(regval) (GD_BITS(11,12) & ((uint32_t)(regval) << 11)) - #define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */ - #define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */ - #define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */ + #define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt flag */ + + /* SDIO power control */ +-#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) ++#define PWRCTL_PWRCTL(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) + #define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */ + #define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */ + + /* SDIO card bus mode control */ +-#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) ++#define CLKCTL_BUSMODE(regval) (GD_BITS(11,12) & ((uint32_t)(regval) << 11)) + #define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */ + #define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */ + #define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */ @@ -281,7 +281,7 @@ OF SUCH DAMAGE. - #define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */ - - /* SDIO command response type */ --#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -+#define CMDCTL_CMDRESP(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6)) - #define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */ - #define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */ - #define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */ + #define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */ + + /* SDIO command response type */ +-#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) ++#define CMDCTL_CMDRESP(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6)) + #define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */ + #define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */ + #define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */ @@ -297,7 +297,7 @@ OF SUCH DAMAGE. - #define SDIO_RESPONSE3 (uint32_t)0x00000003U /*!< card response[31:1], plus bit 0 */ - - /* SDIO data block size */ --#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -+#define DATACTL_BLKSZ(regval) (GD_BITS(4,7) & ((uint32_t)(regval) << 4)) - #define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */ - #define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */ - #define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */ + #define SDIO_RESPONSE3 (uint32_t)0x00000003U /*!< card response[31:1], plus bit 0 */ + + /* SDIO data block size */ +-#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) ++#define DATACTL_BLKSZ(regval) (GD_BITS(4,7) & ((uint32_t)(regval) << 4)) + #define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */ + #define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */ + #define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h old mode 100644 new mode 100755 @@ -2401,87 +2401,87 @@ index 5250841..84d93e6 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h @@ -62,7 +62,7 @@ OF SUCH DAMAGE. - #define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ - #define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ - #define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ --#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ -+#define SPI_CTL0_PSC GD_BITS(3,5) /*!< master clock prescaler selection */ - #define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ - #define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ - #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ + #define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ + #define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ + #define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +-#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ ++#define SPI_CTL0_PSC GD_BITS(3,5) /*!< master clock prescaler selection */ + #define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ + #define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ + #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ @@ -96,29 +96,29 @@ OF SUCH DAMAGE. - #define SPI_STAT_FERR BIT(8) /*!< format error bit */ - - /* SPI_DATA */ --#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ -+#define SPI_DATA_DATA GD_BITS(0,15) /*!< data transfer register */ - - /* SPI_CRCPOLY */ --#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial register */ -+#define SPI_CRCPOLY_CPR GD_BITS(0,15) /*!< CRC polynomial register */ - - /* SPI_RCRC */ --#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */ -+#define SPI_RCRC_RCR GD_BITS(0,15) /*!< RX CRC register */ - - /* SPI_TCRC */ --#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC register */ -+#define SPI_TCRC_TCR GD_BITS(0,15) /*!< TX CRC register */ - - /* SPI_I2SCTL */ - #define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ --#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ -+#define SPI_I2SCTL_DTLEN GD_BITS(1,2) /*!< data length */ - #define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ --#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ -+#define SPI_I2SCTL_I2SSTD GD_BITS(4,5) /*!< I2S standard selection */ - #define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ --#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ -+#define SPI_I2SCTL_I2SOPMOD GD_BITS(8,9) /*!< I2S operation mode */ - #define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ - #define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ - - /* SPI_I2SPSC */ --#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ -+#define SPI_I2SPSC_DIV GD_BITS(0,7) /*!< dividing factor for the prescaler */ - #define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ - #define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ - + #define SPI_STAT_FERR BIT(8) /*!< format error bit */ + + /* SPI_DATA */ +-#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ ++#define SPI_DATA_DATA GD_BITS(0,15) /*!< data transfer register */ + + /* SPI_CRCPOLY */ +-#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial register */ ++#define SPI_CRCPOLY_CPR GD_BITS(0,15) /*!< CRC polynomial register */ + + /* SPI_RCRC */ +-#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */ ++#define SPI_RCRC_RCR GD_BITS(0,15) /*!< RX CRC register */ + + /* SPI_TCRC */ +-#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC register */ ++#define SPI_TCRC_TCR GD_BITS(0,15) /*!< TX CRC register */ + + /* SPI_I2SCTL */ + #define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +-#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ ++#define SPI_I2SCTL_DTLEN GD_BITS(1,2) /*!< data length */ + #define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +-#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ ++#define SPI_I2SCTL_I2SSTD GD_BITS(4,5) /*!< I2S standard selection */ + #define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +-#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ ++#define SPI_I2SCTL_I2SOPMOD GD_BITS(8,9) /*!< I2S operation mode */ + #define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ + #define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + + /* SPI_I2SPSC */ +-#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ ++#define SPI_I2SPSC_DIV GD_BITS(0,7) /*!< dividing factor for the prescaler */ + #define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ + #define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + @@ -173,7 +173,7 @@ typedef struct - #define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ - - /* SPI clock prescale factor */ --#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -+#define CTL0_PSC(regval) (GD_BITS(3,5) & ((uint32_t)(regval) << 3)) - #define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ - #define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ - #define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ + #define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + + /* SPI clock prescale factor */ +-#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) ++#define CTL0_PSC(regval) (GD_BITS(3,5) & ((uint32_t)(regval) << 3)) + #define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ + #define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ + #define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ @@ -195,7 +195,7 @@ typedef struct - #define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ - - /* I2S frame format */ --#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) -+#define I2SCTL_DTLEN(regval) (GD_BITS(1,2) & ((uint32_t)(regval) << 1)) - #define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ - #define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ - #define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ + #define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + + /* I2S frame format */ +-#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) ++#define I2SCTL_DTLEN(regval) (GD_BITS(1,2) & ((uint32_t)(regval) << 1)) + #define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ + #define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ + #define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ @@ -206,14 +206,14 @@ typedef struct - #define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ - - /* I2S operation mode */ --#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -+#define I2SCTL_I2SOPMOD(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) - #define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ - #define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ - #define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ - #define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ - - /* I2S standard */ --#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -+#define I2SCTL_I2SSTD(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) - #define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ - #define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ - #define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ + #define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + + /* I2S operation mode */ +-#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) ++#define I2SCTL_I2SOPMOD(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) + #define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ + #define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ + #define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ + #define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + + /* I2S standard */ +-#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) ++#define I2SCTL_I2SSTD(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) + #define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ + #define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ + #define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h old mode 100644 new mode 100755 @@ -2489,239 +2489,239 @@ index 5da3d45..e868a1b --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h @@ -87,15 +87,15 @@ OF SUCH DAMAGE. - #define TIMER_CTL0_UPS BIT(2) /*!< update source */ - #define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ - #define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ --#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ -+#define TIMER_CTL0_CAM GD_BITS(5,6) /*!< center-aligned mode selection */ - #define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ --#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ -+#define TIMER_CTL0_CKDIV GD_BITS(8,9) /*!< clock division */ - - /* TIMER_CTL1 */ - #define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ - #define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ - #define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ --#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ -+#define TIMER_CTL1_MMC GD_BITS(4,6) /*!< master mode control */ - #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ - #define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ - #define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ + #define TIMER_CTL0_UPS BIT(2) /*!< update source */ + #define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ + #define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +-#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ ++#define TIMER_CTL0_CAM GD_BITS(5,6) /*!< center-aligned mode selection */ + #define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +-#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ ++#define TIMER_CTL0_CKDIV GD_BITS(8,9) /*!< clock division */ + + /* TIMER_CTL1 */ + #define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ + #define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ + #define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +-#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ ++#define TIMER_CTL1_MMC GD_BITS(4,6) /*!< master mode control */ + #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ + #define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ + #define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ @@ -106,11 +106,11 @@ OF SUCH DAMAGE. - #define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ - - /* TIMER_SMCFG */ --#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ --#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ -+#define TIMER_SMCFG_SMC GD_BITS(0,2) /*!< slave mode control */ -+#define TIMER_SMCFG_TRGS GD_BITS(4,6) /*!< trigger selection */ - #define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ --#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ --#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ -+#define TIMER_SMCFG_ETFC GD_BITS(8,11) /*!< external trigger filter control */ -+#define TIMER_SMCFG_ETPSC GD_BITS(12,13) /*!< external trigger prescaler */ - #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ - #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - + #define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ + + /* TIMER_SMCFG */ +-#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +-#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ ++#define TIMER_SMCFG_SMC GD_BITS(0,2) /*!< slave mode control */ ++#define TIMER_SMCFG_TRGS GD_BITS(4,6) /*!< trigger selection */ + #define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +-#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +-#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ ++#define TIMER_SMCFG_ETFC GD_BITS(8,11) /*!< external trigger filter control */ ++#define TIMER_SMCFG_ETPSC GD_BITS(12,13) /*!< external trigger prescaler */ + #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ + #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ + @@ -157,39 +157,39 @@ OF SUCH DAMAGE. - - /* TIMER_CHCTL0 */ - /* output compare mode */ --#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ -+#define TIMER_CHCTL0_CH0MS GD_BITS(0,1) /*!< channel 0 mode selection */ - #define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ - #define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ --#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */ -+#define TIMER_CHCTL0_CH0COMCTL GD_BITS(4,6) /*!< channel 0 output compare mode */ - #define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ --#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ -+#define TIMER_CHCTL0_CH1MS GD_BITS(8,9) /*!< channel 1 mode selection */ - #define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ - #define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ --#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */ -+#define TIMER_CHCTL0_CH1COMCTL GD_BITS(12,14) /*!< channel 1 output compare mode */ - #define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ - /* input capture mode */ --#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ --#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ --#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ --#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ -+#define TIMER_CHCTL0_CH0CAPPSC GD_BITS(2,3) /*!< channel 0 input capture prescaler */ -+#define TIMER_CHCTL0_CH0CAPFLT GD_BITS(4,7) /*!< channel 0 input capture filter control */ -+#define TIMER_CHCTL0_CH1CAPPSC GD_BITS(10,11) /*!< channel 1 input capture prescaler */ -+#define TIMER_CHCTL0_CH1CAPFLT GD_BITS(12,15) /*!< channel 1 input capture filter control */ - - /* TIMER_CHCTL1 */ - /* output compare mode */ --#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ -+#define TIMER_CHCTL1_CH2MS GD_BITS(0,1) /*!< channel 2 mode selection */ - #define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ - #define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ --#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */ -+#define TIMER_CHCTL1_CH2COMCTL GD_BITS(4,6) /*!< channel 2 output compare mode */ - #define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ --#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ -+#define TIMER_CHCTL1_CH3MS GD_BITS(8,9) /*!< channel 3 mode selection */ - #define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ - #define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ --#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ -+#define TIMER_CHCTL1_CH3COMCTL GD_BITS(12,14) /*!< channel 3 output compare mode */ - #define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ - /* input capture mode */ --#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ --#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ --#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ --#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ -+#define TIMER_CHCTL1_CH2CAPPSC GD_BITS(2,3) /*!< channel 2 input capture prescaler */ -+#define TIMER_CHCTL1_CH2CAPFLT GD_BITS(4,7) /*!< channel 2 input capture filter control */ -+#define TIMER_CHCTL1_CH3CAPPSC GD_BITS(10,11) /*!< channel 3 input capture prescaler */ -+#define TIMER_CHCTL1_CH3CAPFLT GD_BITS(12,15) /*!< channel 3 input capture filter control */ - - /* TIMER_CHCTL2 */ - #define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ + + /* TIMER_CHCTL0 */ + /* output compare mode */ +-#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ ++#define TIMER_CHCTL0_CH0MS GD_BITS(0,1) /*!< channel 0 mode selection */ + #define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ + #define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +-#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */ ++#define TIMER_CHCTL0_CH0COMCTL GD_BITS(4,6) /*!< channel 0 output compare mode */ + #define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +-#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ ++#define TIMER_CHCTL0_CH1MS GD_BITS(8,9) /*!< channel 1 mode selection */ + #define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ + #define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +-#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */ ++#define TIMER_CHCTL0_CH1COMCTL GD_BITS(12,14) /*!< channel 1 output compare mode */ + #define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ + /* input capture mode */ +-#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +-#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +-#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +-#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ ++#define TIMER_CHCTL0_CH0CAPPSC GD_BITS(2,3) /*!< channel 0 input capture prescaler */ ++#define TIMER_CHCTL0_CH0CAPFLT GD_BITS(4,7) /*!< channel 0 input capture filter control */ ++#define TIMER_CHCTL0_CH1CAPPSC GD_BITS(10,11) /*!< channel 1 input capture prescaler */ ++#define TIMER_CHCTL0_CH1CAPFLT GD_BITS(12,15) /*!< channel 1 input capture filter control */ + + /* TIMER_CHCTL1 */ + /* output compare mode */ +-#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ ++#define TIMER_CHCTL1_CH2MS GD_BITS(0,1) /*!< channel 2 mode selection */ + #define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ + #define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +-#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */ ++#define TIMER_CHCTL1_CH2COMCTL GD_BITS(4,6) /*!< channel 2 output compare mode */ + #define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +-#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ ++#define TIMER_CHCTL1_CH3MS GD_BITS(8,9) /*!< channel 3 mode selection */ + #define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ + #define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +-#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ ++#define TIMER_CHCTL1_CH3COMCTL GD_BITS(12,14) /*!< channel 3 output compare mode */ + #define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ + /* input capture mode */ +-#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +-#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +-#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +-#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ ++#define TIMER_CHCTL1_CH2CAPPSC GD_BITS(2,3) /*!< channel 2 input capture prescaler */ ++#define TIMER_CHCTL1_CH2CAPFLT GD_BITS(4,7) /*!< channel 2 input capture filter control */ ++#define TIMER_CHCTL1_CH3CAPPSC GD_BITS(10,11) /*!< channel 3 input capture prescaler */ ++#define TIMER_CHCTL1_CH3CAPFLT GD_BITS(12,15) /*!< channel 3 input capture filter control */ + + /* TIMER_CHCTL2 */ + #define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ @@ -208,32 +208,32 @@ OF SUCH DAMAGE. - #define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ - - /* TIMER_CNT */ --#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ -+#define TIMER_CNT_CNT GD_BITS(0,15) /*!< 16 bit timer counter */ - - /* TIMER_PSC */ --#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ -+#define TIMER_PSC_PSC GD_BITS(0,15) /*!< prescaler value of the counter clock */ - - /* TIMER_CAR */ --#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ -+#define TIMER_CAR_CARL GD_BITS(0,15) /*!< 16 bit counter auto reload value */ - - /* TIMER_CREP */ --#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ -+#define TIMER_CREP_CREP GD_BITS(0,7) /*!< counter repetition value */ - - /* TIMER_CH0CV */ --#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ -+#define TIMER_CH0CV_CH0VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ - - /* TIMER_CH1CV */ --#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ -+#define TIMER_CH1CV_CH1VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ - - /* TIMER_CH2CV */ --#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ -+#define TIMER_CH2CV_CH2VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ - - /* TIMER_CH3CV */ --#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ -+#define TIMER_CH3CV_CH3VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ - - /* TIMER_CCHP */ --#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ --#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ -+#define TIMER_CCHP_DTCFG GD_BITS(0,7) /*!< dead time configure */ -+#define TIMER_CCHP_PROT GD_BITS(8,9) /*!< complementary register protect control */ - #define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ - #define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ - #define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ + #define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ + + /* TIMER_CNT */ +-#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ ++#define TIMER_CNT_CNT GD_BITS(0,15) /*!< 16 bit timer counter */ + + /* TIMER_PSC */ +-#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ ++#define TIMER_PSC_PSC GD_BITS(0,15) /*!< prescaler value of the counter clock */ + + /* TIMER_CAR */ +-#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ ++#define TIMER_CAR_CARL GD_BITS(0,15) /*!< 16 bit counter auto reload value */ + + /* TIMER_CREP */ +-#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ ++#define TIMER_CREP_CREP GD_BITS(0,7) /*!< counter repetition value */ + + /* TIMER_CH0CV */ +-#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ ++#define TIMER_CH0CV_CH0VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ + + /* TIMER_CH1CV */ +-#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ ++#define TIMER_CH1CV_CH1VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ + + /* TIMER_CH2CV */ +-#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ ++#define TIMER_CH2CV_CH2VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ + + /* TIMER_CH3CV */ +-#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ ++#define TIMER_CH3CV_CH3VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ + + /* TIMER_CCHP */ +-#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +-#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ ++#define TIMER_CCHP_DTCFG GD_BITS(0,7) /*!< dead time configure */ ++#define TIMER_CCHP_PROT GD_BITS(8,9) /*!< complementary register protect control */ + #define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ + #define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ + #define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ @@ -242,14 +242,14 @@ OF SUCH DAMAGE. - #define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ - - /* TIMER_DMACFG */ --#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ --#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ -+#define TIMER_DMACFG_DMATA GD_BITS(0,4) /*!< DMA transfer access start address */ -+#define TIMER_DMACFG_DMATC GD_BITS(8,12) /*!< DMA transfer count */ - - /* TIMER_DMATB */ --#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ -+#define TIMER_DMATB_DMATB GD_BITS(0,15) /*!< DMA transfer buffer address */ - - /* TIMER_IRMP */ --#define TIMER10_IRMP_ITI1_RMP BITS(0,1) /*!< TIMER10 internal trigger input 1 remap */ -+#define TIMER10_IRMP_ITI1_RMP GD_BITS(0,1) /*!< TIMER10 internal trigger input 1 remap */ - - /* TIMER_CFG */ - #define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ + #define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + + /* TIMER_DMACFG */ +-#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ +-#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ ++#define TIMER_DMACFG_DMATA GD_BITS(0,4) /*!< DMA transfer access start address */ ++#define TIMER_DMACFG_DMATC GD_BITS(8,12) /*!< DMA transfer count */ + + /* TIMER_DMATB */ +-#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ ++#define TIMER_DMATB_DMATB GD_BITS(0,15) /*!< DMA transfer buffer address */ + + /* TIMER_IRMP */ +-#define TIMER10_IRMP_ITI1_RMP BITS(0,1) /*!< TIMER10 internal trigger input 1 remap */ ++#define TIMER10_IRMP_ITI1_RMP GD_BITS(0,1) /*!< TIMER10 internal trigger input 1 remap */ + + /* TIMER_CFG */ + #define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ @@ -349,7 +349,7 @@ typedef struct - #define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */ - - /* DMA access base address */ --#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) -+#define DMACFG_DMATA(regval) (GD_BITS(0, 4) & ((uint32_t)(regval) << 0U)) - #define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ - #define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ - #define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ + #define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */ + + /* DMA access base address */ +-#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) ++#define DMACFG_DMATA(regval) (GD_BITS(0, 4) & ((uint32_t)(regval) << 0U)) + #define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ + #define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ + #define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ @@ -372,7 +372,7 @@ typedef struct - #define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */ - - /* DMA access burst length */ --#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) -+#define DMACFG_DMATC(regval) (GD_BITS(8, 12) & ((uint32_t)(regval) << 8U)) - #define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ - #define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ - #define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ + #define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */ + + /* DMA access burst length */ +-#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) ++#define DMACFG_DMATC(regval) (GD_BITS(8, 12) & ((uint32_t)(regval) << 8U)) + #define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ + #define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ + #define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ @@ -403,7 +403,7 @@ typedef struct - #define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ - - /* center-aligned mode selection */ --#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) -+#define CTL0_CAM(regval) ((uint16_t)(GD_BITS(5, 6) & ((uint32_t)(regval) << 5U))) - #define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ - #define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ - #define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ + #define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ + + /* center-aligned mode selection */ +-#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) ++#define CTL0_CAM(regval) ((uint16_t)(GD_BITS(5, 6) & ((uint32_t)(regval) << 5U))) + #define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ + #define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ + #define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ @@ -418,7 +418,7 @@ typedef struct - #define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ - - /* specify division ratio between TIMER clock and dead-time and sampling clock */ --#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -+#define CTL0_CKDIV(regval) ((uint16_t)(GD_BITS(8, 9) & ((uint32_t)(regval) << 8U))) - #define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ - #define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ - #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ + #define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ + + /* specify division ratio between TIMER clock and dead-time and sampling clock */ +-#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) ++#define CTL0_CKDIV(regval) ((uint16_t)(GD_BITS(8, 9) & ((uint32_t)(regval) << 8U))) + #define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ + #define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ + #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ @@ -448,7 +448,7 @@ typedef struct - #define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ - - /* complementary register protect control */ --#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -+#define CCHP_PROT(regval) ((uint16_t)(GD_BITS(8, 9) & ((uint32_t)(regval) << 8U))) - #define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ - #define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ - #define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ + #define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ + + /* complementary register protect control */ +-#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) ++#define CCHP_PROT(regval) ((uint16_t)(GD_BITS(8, 9) & ((uint32_t)(regval) << 8U))) + #define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ + #define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ + #define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ @@ -530,7 +530,7 @@ typedef struct - #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ - - /* trigger selection */ --#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -+#define SMCFG_TRGSEL(regval) (GD_BITS(4, 6) & ((uint32_t)(regval) << 4U)) - #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ - #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ - #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ + #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + + /* trigger selection */ +-#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) ++#define SMCFG_TRGSEL(regval) (GD_BITS(4, 6) & ((uint32_t)(regval) << 4U)) + #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ + #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ + #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ @@ -541,7 +541,7 @@ typedef struct - #define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ - - /* master mode control */ --#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -+#define CTL1_MMC(regval) (GD_BITS(4, 6) & ((uint32_t)(regval) << 4U)) - #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ - #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ - #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ + #define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ + + /* master mode control */ +-#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) ++#define CTL1_MMC(regval) (GD_BITS(4, 6) & ((uint32_t)(regval) << 4U)) + #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ + #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ + #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ @@ -552,7 +552,7 @@ typedef struct - #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ - - /* slave mode control */ --#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) -+#define SMCFG_SMC(regval) (GD_BITS(0, 2) & ((uint32_t)(regval) << 0U)) - #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ - #define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ - #define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ + #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + + /* slave mode control */ +-#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) ++#define SMCFG_SMC(regval) (GD_BITS(0, 2) & ((uint32_t)(regval) << 0U)) + #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ + #define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ + #define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ @@ -567,7 +567,7 @@ typedef struct - #define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */ - - /* external trigger prescaler */ --#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) -+#define SMCFG_ETPSC(regval) (GD_BITS(12, 13) & ((uint32_t)(regval) << 12U)) - #define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ - #define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ - #define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ + #define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */ + + /* external trigger prescaler */ +-#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) ++#define SMCFG_ETPSC(regval) (GD_BITS(12, 13) & ((uint32_t)(regval) << 12U)) + #define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ + #define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ + #define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h old mode 100644 new mode 100755 @@ -2729,82 +2729,82 @@ index d9754c6..f8a58ef --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h @@ -73,11 +73,11 @@ OF SUCH DAMAGE. - #define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ - - /* USARTx_DATA */ --#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ -+#define USART_DATA_DATA GD_BITS(0,8) /*!< transmit or read data value */ - - /* USARTx_BAUD */ --#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ --#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ -+#define USART_BAUD_FRADIV GD_BITS(0,3) /*!< fraction part of baud-rate divider */ -+#define USART_BAUD_INTDIV GD_BITS(4,15) /*!< integer part of baud-rate divider */ - - /* USARTx_CTL0 */ - #define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ + #define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ + + /* USARTx_DATA */ +-#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ ++#define USART_DATA_DATA GD_BITS(0,8) /*!< transmit or read data value */ + + /* USARTx_BAUD */ +-#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +-#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ ++#define USART_BAUD_FRADIV GD_BITS(0,3) /*!< fraction part of baud-rate divider */ ++#define USART_BAUD_INTDIV GD_BITS(4,15) /*!< integer part of baud-rate divider */ + + /* USARTx_CTL0 */ + #define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ @@ -96,14 +96,14 @@ OF SUCH DAMAGE. - #define USART_CTL0_UEN BIT(13) /*!< USART enable */ - - /* USARTx_CTL1 */ --#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ -+#define USART_CTL1_ADDR GD_BITS(0,3) /*!< address of USART */ - #define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ - #define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ - #define USART_CTL1_CLEN BIT(8) /*!< CK length */ - #define USART_CTL1_CPH BIT(9) /*!< CK phase */ - #define USART_CTL1_CPL BIT(10) /*!< CK polarity */ - #define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ --#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ -+#define USART_CTL1_STB GD_BITS(12,13) /*!< STOP bits length */ - #define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ - - /* USARTx_CTL2 */ + #define USART_CTL0_UEN BIT(13) /*!< USART enable */ + + /* USARTx_CTL1 */ +-#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ ++#define USART_CTL1_ADDR GD_BITS(0,3) /*!< address of USART */ + #define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ + #define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ + #define USART_CTL1_CLEN BIT(8) /*!< CK length */ + #define USART_CTL1_CPH BIT(9) /*!< CK phase */ + #define USART_CTL1_CPL BIT(10) /*!< CK polarity */ + #define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ +-#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ ++#define USART_CTL1_STB GD_BITS(12,13) /*!< STOP bits length */ + #define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ + + /* USARTx_CTL2 */ @@ -120,12 +120,12 @@ OF SUCH DAMAGE. - #define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ - - /* USARTx_GP */ --#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ --#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ -+#define USART_GP_PSC GD_BITS(0,7) /*!< prescaler value for dividing the system clock */ -+#define USART_GP_GUAT GD_BITS(8,15) /*!< guard time value in smartcard mode */ - - /* USARTx_CTL3 */ - #define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ --#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ -+#define USART_CTL3_SCRTNUM GD_BITS(1,3) /*!< smartcard auto-retry number */ - #define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ - #define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ - #define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ + #define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ + + /* USARTx_GP */ +-#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +-#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ ++#define USART_GP_PSC GD_BITS(0,7) /*!< prescaler value for dividing the system clock */ ++#define USART_GP_GUAT GD_BITS(8,15) /*!< guard time value in smartcard mode */ + + /* USARTx_CTL3 */ + #define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ +-#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ ++#define USART_CTL3_SCRTNUM GD_BITS(1,3) /*!< smartcard auto-retry number */ + #define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ + #define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ + #define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ @@ -134,8 +134,8 @@ OF SUCH DAMAGE. - #define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ - - /* USARTx_RT */ --#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ --#define USART_RT_BL BITS(24,31) /*!< block length */ -+#define USART_RT_RT GD_BITS(0,23) /*!< receiver timeout threshold */ -+#define USART_RT_BL GD_BITS(24,31) /*!< block length */ - - /* USARTx_STAT1 */ - #define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ + #define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ + + /* USARTx_RT */ +-#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ +-#define USART_RT_BL BITS(24,31) /*!< block length */ ++#define USART_RT_RT GD_BITS(0,23) /*!< receiver timeout threshold */ ++#define USART_RT_BL GD_BITS(24,31) /*!< block length */ + + /* USARTx_STAT1 */ + #define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ @@ -246,7 +246,7 @@ typedef enum - #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ - - /* USART parity bits definitions */ --#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -+#define CTL0_PM(regval) (GD_BITS(9,10) & ((uint32_t)(regval) << 9)) - #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ - #define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ - #define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + + /* USART parity bits definitions */ +-#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) ++#define CTL0_PM(regval) (GD_BITS(9,10) & ((uint32_t)(regval) << 9)) + #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ + #define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ + #define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ @@ -262,7 +262,7 @@ typedef enum - #define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ - - /* USART stop bits definitions */ --#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -+#define CTL1_STB(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) - #define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ - #define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ - #define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ + #define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + + /* USART stop bits definitions */ +-#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) ++#define CTL1_STB(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) + #define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ + #define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ + #define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h old mode 100644 new mode 100755 @@ -2812,29 +2812,29 @@ index ff2cbce..dff6d8b --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h @@ -51,19 +51,19 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* WWDGT_CTL */ --#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ -+#define WWDGT_CTL_CNT GD_BITS(0,6) /*!< WWDGT counter value */ - #define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ - - /* WWDGT_CFG */ --#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ --#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ -+#define WWDGT_CFG_WIN GD_BITS(0,6) /*!< WWDGT counter window value */ -+#define WWDGT_CFG_PSC GD_BITS(7,8) /*!< WWDGT prescaler divider value */ - #define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ - - /* WWDGT_STAT */ - #define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ - - /* constants definitions */ --#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ -+#define CFG_PSC(regval) (GD_BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ - #define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ - #define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ - #define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ + + /* bits definitions */ + /* WWDGT_CTL */ +-#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ ++#define WWDGT_CTL_CNT GD_BITS(0,6) /*!< WWDGT counter value */ + #define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + + /* WWDGT_CFG */ +-#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +-#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ ++#define WWDGT_CFG_WIN GD_BITS(0,6) /*!< WWDGT counter window value */ ++#define WWDGT_CFG_PSC GD_BITS(7,8) /*!< WWDGT prescaler divider value */ + #define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ + + /* WWDGT_STAT */ + #define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ + + /* constants definitions */ +-#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ ++#define CFG_PSC(regval) (GD_BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ + #define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ + #define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ + #define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c old mode 100644 new mode 100755 @@ -2842,17 +2842,17 @@ index 330cebf..9ab78c1 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c @@ -38,9 +38,9 @@ OF SUCH DAMAGE. - #include "gd32f30x_fwdgt.h" - - /* write value to FWDGT_CTL_CMD bit field */ --#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -+#define CTL_CMD(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) - /* write value to FWDGT_RLD_RLD bit field */ --#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) -+#define RLD_RLD(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) - - /*! - \brief enable write access to FWDGT_PSC and FWDGT_RLD + #include "gd32f30x_fwdgt.h" + + /* write value to FWDGT_CTL_CMD bit field */ +-#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) ++#define CTL_CMD(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) + /* write value to FWDGT_RLD_RLD bit field */ +-#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) ++#define RLD_RLD(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) + + /*! + \brief enable write access to FWDGT_PSC and FWDGT_RLD diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c old mode 100644 new mode 100755 @@ -2860,29 +2860,29 @@ index c0972f1..858a180 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c @@ -233,6 +233,23 @@ void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin) - GPIO_BC(gpio_periph) = (uint32_t)pin; - } - -+/*! -+ \brief toggle GPIO pin -+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) -+ \param[in] pin: GPIO pin -+ one or more parameters can be selected which are shown as below: -+ \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL -+ \param[out] none -+ \retval none -+*/ -+void gpio_bit_toggle(uint32_t gpio_periph,uint32_t pin) { -+ if ((GPIO_OCTL(gpio_periph)&(pin)) != pin) { -+ gpio_bit_set(gpio_periph, pin); -+ } else { -+ gpio_bit_reset(gpio_periph, pin); -+ } -+} -+ - /*! - \brief write data to the specified GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + GPIO_BC(gpio_periph) = (uint32_t)pin; + } + ++/*! ++ \brief toggle GPIO pin ++ \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) ++ \param[in] pin: GPIO pin ++ one or more parameters can be selected which are shown as below: ++ \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL ++ \param[out] none ++ \retval none ++*/ ++void gpio_bit_toggle(uint32_t gpio_periph,uint32_t pin) { ++ if ((GPIO_OCTL(gpio_periph)&(pin)) != pin) { ++ gpio_bit_set(gpio_periph, pin); ++ } else { ++ gpio_bit_reset(gpio_periph, pin); ++ } ++} ++ + /*! + \brief write data to the specified GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c old mode 100644 new mode 100755 @@ -2890,14 +2890,14 @@ index 454aaaa..7bf4416 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c @@ -597,7 +597,7 @@ void rcu_adc_clock_config(uint32_t adc_psc) - case RCU_CKADC_CKAHB_DIV6: - case RCU_CKADC_CKAHB_DIV10: - case RCU_CKADC_CKAHB_DIV20: -- adc_psc &= ~BITS(2,3); -+ adc_psc &= ~GD_BITS(2,3); - reg0 |= (adc_psc << RCU_ADC_PSC_OFFSET); - reg1 |= RCU_CFG1_ADCPSC_3; - break; + case RCU_CKADC_CKAHB_DIV6: + case RCU_CKADC_CKAHB_DIV10: + case RCU_CKADC_CKAHB_DIV20: +- adc_psc &= ~BITS(2,3); ++ adc_psc &= ~GD_BITS(2,3); + reg0 |= (adc_psc << RCU_ADC_PSC_OFFSET); + reg1 |= RCU_CFG1_ADCPSC_3; + break; diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c old mode 100644 new mode 100755 @@ -2905,17 +2905,17 @@ index 67a7def..1be3081 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c @@ -38,9 +38,9 @@ OF SUCH DAMAGE. - #include "gd32f30x_wwdgt.h" - - /* write value to WWDGT_CTL_CNT bit field */ --#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -+#define CTL_CNT(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) - /* write value to WWDGT_CFG_WIN bit field */ --#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -+#define CFG_WIN(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) - - /*! - \brief reset the window watchdog timer configuration + #include "gd32f30x_wwdgt.h" + + /* write value to WWDGT_CTL_CNT bit field */ +-#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) ++#define CTL_CNT(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) + /* write value to WWDGT_CFG_WIN bit field */ +-#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) ++#define CFG_WIN(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) + + /*! + \brief reset the window watchdog timer configuration diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_usbd_library/usbd/Include/usbd_lld_regs.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_usbd_library/usbd/Include/usbd_lld_regs.h old mode 100644 new mode 100755 @@ -2923,74 +2923,74 @@ index 6d357cf..8441895 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_usbd_library/usbd/Include/usbd_lld_regs.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_usbd_library/usbd/Include/usbd_lld_regs.h @@ -72,9 +72,9 @@ OF SUCH DAMAGE. - #define CTL_SETRST BIT(0) /*!< set USB reset */ - - #ifdef LPM_ENABLED --#define USBD_INTEN BITS(7, 15) /*!< USBD interrupt enable bits */ -+#define USBD_INTEN GD_BITS(7, 15) /*!< USBD interrupt enable bits */ - #else --#define USBD_INTEN BITS(8, 15) /*!< USBD interrupt enable bits */ -+#define USBD_INTEN GD_BITS(8, 15) /*!< USBD interrupt enable bits */ - #endif - /* USBD_INTF */ - #define INTF_STIF BIT(15) /*!< successful transfer interrupt flag (read only bit) */ + #define CTL_SETRST BIT(0) /*!< set USB reset */ + + #ifdef LPM_ENABLED +-#define USBD_INTEN BITS(7, 15) /*!< USBD interrupt enable bits */ ++#define USBD_INTEN GD_BITS(7, 15) /*!< USBD interrupt enable bits */ + #else +-#define USBD_INTEN BITS(8, 15) /*!< USBD interrupt enable bits */ ++#define USBD_INTEN GD_BITS(8, 15) /*!< USBD interrupt enable bits */ + #endif + /* USBD_INTF */ + #define INTF_STIF BIT(15) /*!< successful transfer interrupt flag (read only bit) */ @@ -87,33 +87,33 @@ OF SUCH DAMAGE. - #define INTF_ESOFIF BIT(8) /*!< expected start of frame interrupt flag(clear-only bit) */ - #define INTF_L1REQ BIT(7) /*!< LPM L1 transaction is successfully received and acknowledged */ - #define INTF_DIR BIT(4) /*!< direction of transaction (read-only bit) */ --#define INTF_EPNUM BITS(0, 3) /*!< endpoint number (read-only bit) */ -+#define INTF_EPNUM GD_BITS(0, 3) /*!< endpoint number (read-only bit) */ - - /* USBD_STAT */ - #define STAT_RXDP BIT(15) /*!< data plus line status */ - #define STAT_RXDM BIT(14) /*!< data minus line status */ - #define STAT_LOCK BIT(13) /*!< locked the USB */ --#define STAT_SOFLN BITS(11, 12) /*!< SOF lost number */ --#define STAT_FCNT BITS(0, 10) /*!< frame number count */ -+#define STAT_SOFLN GD_BITS(11, 12) /*!< SOF lost number */ -+#define STAT_FCNT GD_BITS(0, 10) /*!< frame number count */ - - /* USBD_DADDR */ - #define DADDR_USBEN BIT(7) /*!< USB module enable */ --#define DADDR_USBADDR BITS(0, 6) /*!< USB device address */ -+#define DADDR_USBADDR GD_BITS(0, 6) /*!< USB device address */ - - /* USBD_EPxCS */ - #define EPxCS_RX_ST BIT(15) /*!< endpoint reception successful transferred */ - #define EPxCS_RX_DTG BIT(14) /*!< endpoint reception data PID toggle */ --#define EPxCS_RX_STA BITS(12, 13) /*!< endpoint reception status bits */ -+#define EPxCS_RX_STA GD_BITS(12, 13) /*!< endpoint reception status bits */ - #define EPxCS_SETUP BIT(11) /*!< endpoint setup transaction completed */ --#define EPxCS_CTL BITS(9, 10) /*!< endpoint type control */ -+#define EPxCS_CTL GD_BITS(9, 10) /*!< endpoint type control */ - #define EPxCS_KCTL BIT(8) /*!< endpoint kind control */ - #define EPxCS_TX_ST BIT(7) /*!< endpoint transmission successful transfer */ - #define EPxCS_TX_DTG BIT(6) /*!< endpoint transmission data toggle */ --#define EPxCS_TX_STA BITS(4, 5) /*!< endpoint transmission transfers status bits */ --#define EPxCS_AR BITS(0, 3) /*!< endpoint address */ -+#define EPxCS_TX_STA GD_BITS(4, 5) /*!< endpoint transmission transfers status bits */ -+#define EPxCS_AR GD_BITS(0, 3) /*!< endpoint address */ - - /* USBD_LPMCS */ --#define LPMCS_BLSTAT BITS(4, 7) /*!< bLinkState value */ -+#define LPMCS_BLSTAT GD_BITS(4, 7) /*!< bLinkState value */ - #define LPMCS_REMWK BIT(3) /*!< bRemoteWake value */ - #define LPMCS_LPMACK BIT(1) /*!< LPM token acknowledge enable */ - #define LPMCS_LPMEN BIT(0) /*!< LPM support enable */ + #define INTF_ESOFIF BIT(8) /*!< expected start of frame interrupt flag(clear-only bit) */ + #define INTF_L1REQ BIT(7) /*!< LPM L1 transaction is successfully received and acknowledged */ + #define INTF_DIR BIT(4) /*!< direction of transaction (read-only bit) */ +-#define INTF_EPNUM BITS(0, 3) /*!< endpoint number (read-only bit) */ ++#define INTF_EPNUM GD_BITS(0, 3) /*!< endpoint number (read-only bit) */ + + /* USBD_STAT */ + #define STAT_RXDP BIT(15) /*!< data plus line status */ + #define STAT_RXDM BIT(14) /*!< data minus line status */ + #define STAT_LOCK BIT(13) /*!< locked the USB */ +-#define STAT_SOFLN BITS(11, 12) /*!< SOF lost number */ +-#define STAT_FCNT BITS(0, 10) /*!< frame number count */ ++#define STAT_SOFLN GD_BITS(11, 12) /*!< SOF lost number */ ++#define STAT_FCNT GD_BITS(0, 10) /*!< frame number count */ + + /* USBD_DADDR */ + #define DADDR_USBEN BIT(7) /*!< USB module enable */ +-#define DADDR_USBADDR BITS(0, 6) /*!< USB device address */ ++#define DADDR_USBADDR GD_BITS(0, 6) /*!< USB device address */ + + /* USBD_EPxCS */ + #define EPxCS_RX_ST BIT(15) /*!< endpoint reception successful transferred */ + #define EPxCS_RX_DTG BIT(14) /*!< endpoint reception data PID toggle */ +-#define EPxCS_RX_STA BITS(12, 13) /*!< endpoint reception status bits */ ++#define EPxCS_RX_STA GD_BITS(12, 13) /*!< endpoint reception status bits */ + #define EPxCS_SETUP BIT(11) /*!< endpoint setup transaction completed */ +-#define EPxCS_CTL BITS(9, 10) /*!< endpoint type control */ ++#define EPxCS_CTL GD_BITS(9, 10) /*!< endpoint type control */ + #define EPxCS_KCTL BIT(8) /*!< endpoint kind control */ + #define EPxCS_TX_ST BIT(7) /*!< endpoint transmission successful transfer */ + #define EPxCS_TX_DTG BIT(6) /*!< endpoint transmission data toggle */ +-#define EPxCS_TX_STA BITS(4, 5) /*!< endpoint transmission transfers status bits */ +-#define EPxCS_AR BITS(0, 3) /*!< endpoint address */ ++#define EPxCS_TX_STA GD_BITS(4, 5) /*!< endpoint transmission transfers status bits */ ++#define EPxCS_AR GD_BITS(0, 3) /*!< endpoint address */ + + /* USBD_LPMCS */ +-#define LPMCS_BLSTAT BITS(4, 7) /*!< bLinkState value */ ++#define LPMCS_BLSTAT GD_BITS(4, 7) /*!< bLinkState value */ + #define LPMCS_REMWK BIT(3) /*!< bRemoteWake value */ + #define LPMCS_LPMACK BIT(1) /*!< LPM token acknowledge enable */ + #define LPMCS_LPMEN BIT(0) /*!< LPM support enable */ @@ -155,10 +155,10 @@ OF SUCH DAMAGE. - - /* endpoint receive/transmission counter register bit definitions */ - #define EPRCNT_BLKSIZ BIT(15) /* reception data block size */ --#define EPRCNT_BLKNUM BITS(10, 14) /* reception data block number */ --#define EPRCNT_CNT BITS(0, 9) /* reception data count */ -+#define EPRCNT_BLKNUM GD_BITS(10, 14) /* reception data block number */ -+#define EPRCNT_CNT GD_BITS(0, 9) /* reception data count */ - --#define EPTCNT_CNT BITS(0, 9) /* transmisson data count */ -+#define EPTCNT_CNT GD_BITS(0, 9) /* transmisson data count */ - - /* interrupt flag clear bits */ - #define CLR(x) (USBD_INTF = ~INTF_##x) + + /* endpoint receive/transmission counter register bit definitions */ + #define EPRCNT_BLKSIZ BIT(15) /* reception data block size */ +-#define EPRCNT_BLKNUM BITS(10, 14) /* reception data block number */ +-#define EPRCNT_CNT BITS(0, 9) /* reception data count */ ++#define EPRCNT_BLKNUM GD_BITS(10, 14) /* reception data block number */ ++#define EPRCNT_CNT GD_BITS(0, 9) /* reception data count */ + +-#define EPTCNT_CNT BITS(0, 9) /* transmisson data count */ ++#define EPTCNT_CNT GD_BITS(0, 9) /* transmisson data count */ + + /* interrupt flag clear bits */ + #define CLR(x) (USBD_INTF = ~INTF_##x) diff --git a/GD32F30x_Firmware_Library/Firmware/GD32F30x_usbfs_library/driver/Include/drv_usb_regs.h b/GD32F30x_Firmware_Library/Firmware/GD32F30x_usbfs_library/driver/Include/drv_usb_regs.h old mode 100644 new mode 100755 @@ -2998,327 +2998,327 @@ index 5d9f262..e7eedb8 --- a/GD32F30x_Firmware_Library/Firmware/GD32F30x_usbfs_library/driver/Include/drv_usb_regs.h +++ b/GD32F30x_Firmware_Library/Firmware/GD32F30x_usbfs_library/driver/Include/drv_usb_regs.h @@ -208,7 +208,7 @@ typedef struct _usb_regs - #define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */ - #define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */ - #define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */ --#define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */ -+#define GAHBCS_BURST GD_BITS(1, 4) /*!< the AHB burst type used by DMA */ - #define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ - - /* global USB control and status register bits definitions */ + #define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */ + #define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */ + #define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */ +-#define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */ ++#define GAHBCS_BURST GD_BITS(1, 4) /*!< the AHB burst type used by DMA */ + #define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ + + /* global USB control and status register bits definitions */ @@ -216,16 +216,16 @@ typedef struct _usb_regs - #define GUSBCS_FHM BIT(29) /*!< force host mode */ - #define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */ - #define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */ --#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ -+#define GUSBCS_UTT GD_BITS(10, 13) /*!< USB turnaround time */ - #define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ - #define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ - #define GUSBCS_EMBPHY BIT(6) /*!< embedded PHY selected */ --#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ -+#define GUSBCS_TOC GD_BITS(0, 2) /*!< timeout calibration */ - - /* global reset control register bits definitions */ - #define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */ - #define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */ --#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ -+#define GRSTCTL_TXFNUM GD_BITS(6, 10) /*!< tx FIFO number */ - #define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ - #define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ - #define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ + #define GUSBCS_FHM BIT(29) /*!< force host mode */ + #define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */ + #define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */ +-#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ ++#define GUSBCS_UTT GD_BITS(10, 13) /*!< USB turnaround time */ + #define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ + #define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ + #define GUSBCS_EMBPHY BIT(6) /*!< embedded PHY selected */ +-#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ ++#define GUSBCS_TOC GD_BITS(0, 2) /*!< timeout calibration */ + + /* global reset control register bits definitions */ + #define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */ + #define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */ +-#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ ++#define GRSTCTL_TXFNUM GD_BITS(6, 10) /*!< tx FIFO number */ + #define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ + #define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ + #define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ @@ -288,30 +288,30 @@ typedef struct _usb_regs - #define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ - - /* global receive status read and pop register bits definitions */ --#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ --#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ --#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ --#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ --#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ -+#define GRSTATRP_RPCKST GD_BITS(17, 20) /*!< received packet status */ -+#define GRSTATRP_DPID GD_BITS(15, 16) /*!< data PID */ -+#define GRSTATRP_BCOUNT GD_BITS(4, 14) /*!< byte count */ -+#define GRSTATRP_CNUM GD_BITS(0, 3) /*!< channel number */ -+#define GRSTATRP_EPNUM GD_BITS(0, 3) /*!< endpoint number */ - - /* global receive FIFO length register bits definitions */ --#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ -+#define GRFLEN_RXFD GD_BITS(0, 15) /*!< rx FIFO depth */ - - /* host non-periodic transmit FIFO length register bits definitions */ --#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ --#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ -+#define HNPTFLEN_HNPTXFD GD_BITS(16, 31) /*!< non-periodic Tx FIFO depth */ -+#define HNPTFLEN_HNPTXRSAR GD_BITS(0, 15) /*!< non-periodic Tx RAM start address */ - - /* USB IN endpoint 0 transmit FIFO length register bits definitions */ --#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ --#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ -+#define DIEP0TFLEN_IEP0TXFD GD_BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ -+#define DIEP0TFLEN_IEP0TXRSAR GD_BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ - - /* host non-periodic transmit FIFO/queue status register bits definitions */ --#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ --#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ --#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ --#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ --#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ --#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ -+#define HNPTFQSTAT_NPTXRQTOP GD_BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ -+#define HNPTFQSTAT_NPTXRQS GD_BITS(16, 23) /*!< non-periodic Tx request queue space */ -+#define HNPTFQSTAT_NPTXFS GD_BITS(0, 15) /*!< non-periodic Tx FIFO space */ -+#define HNPTFQSTAT_CNUM GD_BITS(27, 30) /*!< channel number*/ -+#define HNPTFQSTAT_EPNUM GD_BITS(27, 30) /*!< endpoint number */ -+#define HNPTFQSTAT_TYPE GD_BITS(25, 26) /*!< token type */ - #define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - - /* global core configuration register bits definitions */ + #define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ + + /* global receive status read and pop register bits definitions */ +-#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ +-#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ +-#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ +-#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ +-#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ ++#define GRSTATRP_RPCKST GD_BITS(17, 20) /*!< received packet status */ ++#define GRSTATRP_DPID GD_BITS(15, 16) /*!< data PID */ ++#define GRSTATRP_BCOUNT GD_BITS(4, 14) /*!< byte count */ ++#define GRSTATRP_CNUM GD_BITS(0, 3) /*!< channel number */ ++#define GRSTATRP_EPNUM GD_BITS(0, 3) /*!< endpoint number */ + + /* global receive FIFO length register bits definitions */ +-#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ ++#define GRFLEN_RXFD GD_BITS(0, 15) /*!< rx FIFO depth */ + + /* host non-periodic transmit FIFO length register bits definitions */ +-#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ +-#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ ++#define HNPTFLEN_HNPTXFD GD_BITS(16, 31) /*!< non-periodic Tx FIFO depth */ ++#define HNPTFLEN_HNPTXRSAR GD_BITS(0, 15) /*!< non-periodic Tx RAM start address */ + + /* USB IN endpoint 0 transmit FIFO length register bits definitions */ +-#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ +-#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ ++#define DIEP0TFLEN_IEP0TXFD GD_BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ ++#define DIEP0TFLEN_IEP0TXRSAR GD_BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ + + /* host non-periodic transmit FIFO/queue status register bits definitions */ +-#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ +-#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ +-#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ +-#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ +-#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +-#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ ++#define HNPTFQSTAT_NPTXRQTOP GD_BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ ++#define HNPTFQSTAT_NPTXRQS GD_BITS(16, 23) /*!< non-periodic Tx request queue space */ ++#define HNPTFQSTAT_NPTXFS GD_BITS(0, 15) /*!< non-periodic Tx FIFO space */ ++#define HNPTFQSTAT_CNUM GD_BITS(27, 30) /*!< channel number*/ ++#define HNPTFQSTAT_EPNUM GD_BITS(27, 30) /*!< endpoint number */ ++#define HNPTFQSTAT_TYPE GD_BITS(25, 26) /*!< token type */ + #define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + + /* global core configuration register bits definitions */ @@ -322,50 +322,50 @@ typedef struct _usb_regs - #define GCCFG_PWRON BIT(16) /*!< power on */ - - /* core ID register bits definitions */ --#define CID_CID BITS(0, 31) /*!< core ID */ -+#define CID_CID GD_BITS(0, 31) /*!< core ID */ - - /* host periodic transmit FIFO length register bits definitions */ --#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ --#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ -+#define HPTFLEN_HPTXFD GD_BITS(16, 31) /*!< host periodic Tx FIFO depth */ -+#define HPTFLEN_HPTXFSAR GD_BITS(0, 15) /*!< host periodic Tx RAM start address */ - - /* device IN endpoint transmit FIFO length register bits definitions */ --#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ --#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ -+#define DIEPTFLEN_IEPTXFD GD_BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ -+#define DIEPTFLEN_IEPTXRSAR GD_BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ - - /* host control register bits definitions */ - #define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */ --#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ -+#define HCTL_CLKSEL GD_BITS(0, 1) /*!< clock select for USB clock */ - - /* host frame interval register bits definitions */ --#define HFT_FRI BITS(0, 15) /*!< frame interval */ -+#define HFT_FRI GD_BITS(0, 15) /*!< frame interval */ - - /* host frame information remaining register bits definitions */ --#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ --#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ -+#define HFINFR_FRT GD_BITS(16, 31) /*!< frame remaining time */ -+#define HFINFR_FRNUM GD_BITS(0, 15) /*!< frame number */ - - /* host periodic transmit FIFO/queue status register bits definitions */ --#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ --#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ --#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ -+#define HPTFQSTAT_PTXREQT GD_BITS(24, 31) /*!< top entry of the periodic Tx request queue */ -+#define HPTFQSTAT_PTXREQS GD_BITS(16, 23) /*!< periodic Tx request queue space */ -+#define HPTFQSTAT_PTXFS GD_BITS(0, 15) /*!< periodic Tx FIFO space */ - #define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ --#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ --#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ --#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ -+#define HPTFQSTAT_CNUM GD_BITS(27, 30) /*!< channel number */ -+#define HPTFQSTAT_EPNUM GD_BITS(27, 30) /*!< endpoint number */ -+#define HPTFQSTAT_TYPE GD_BITS(25, 26) /*!< token type */ - #define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - --#define TFQSTAT_TXFS BITS(0, 15) --#define TFQSTAT_CNUM BITS(27, 30) -+#define TFQSTAT_TXFS GD_BITS(0, 15) -+#define TFQSTAT_CNUM GD_BITS(27, 30) - - /* host all channels interrupt register bits definitions */ --#define HACHINT_HACHINT BITS(0, 11) /*!< host all channel interrupts */ -+#define HACHINT_HACHINT GD_BITS(0, 11) /*!< host all channel interrupts */ - - /* host all channels interrupt enable register bits definitions */ --#define HACHINTEN_CINTEN BITS(0, 11) /*!< channel interrupt enable */ -+#define HACHINTEN_CINTEN GD_BITS(0, 11) /*!< channel interrupt enable */ - - /* host port control and status register bits definitions */ --#define HPCS_PS BITS(17, 18) /*!< port speed */ -+#define HPCS_PS GD_BITS(17, 18) /*!< port speed */ - #define HPCS_PP BIT(12) /*!< port power */ --#define HPCS_PLST BITS(10, 11) /*!< port line status */ -+#define HPCS_PLST GD_BITS(10, 11) /*!< port line status */ - #define HPCS_PRST BIT(8) /*!< port reset */ - #define HPCS_PSP BIT(7) /*!< port suspend */ - #define HPCS_PREM BIT(6) /*!< port resume */ + #define GCCFG_PWRON BIT(16) /*!< power on */ + + /* core ID register bits definitions */ +-#define CID_CID BITS(0, 31) /*!< core ID */ ++#define CID_CID GD_BITS(0, 31) /*!< core ID */ + + /* host periodic transmit FIFO length register bits definitions */ +-#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ +-#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ ++#define HPTFLEN_HPTXFD GD_BITS(16, 31) /*!< host periodic Tx FIFO depth */ ++#define HPTFLEN_HPTXFSAR GD_BITS(0, 15) /*!< host periodic Tx RAM start address */ + + /* device IN endpoint transmit FIFO length register bits definitions */ +-#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ +-#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ ++#define DIEPTFLEN_IEPTXFD GD_BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ ++#define DIEPTFLEN_IEPTXRSAR GD_BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ + + /* host control register bits definitions */ + #define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */ +-#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ ++#define HCTL_CLKSEL GD_BITS(0, 1) /*!< clock select for USB clock */ + + /* host frame interval register bits definitions */ +-#define HFT_FRI BITS(0, 15) /*!< frame interval */ ++#define HFT_FRI GD_BITS(0, 15) /*!< frame interval */ + + /* host frame information remaining register bits definitions */ +-#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ +-#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ ++#define HFINFR_FRT GD_BITS(16, 31) /*!< frame remaining time */ ++#define HFINFR_FRNUM GD_BITS(0, 15) /*!< frame number */ + + /* host periodic transmit FIFO/queue status register bits definitions */ +-#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ +-#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ +-#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ ++#define HPTFQSTAT_PTXREQT GD_BITS(24, 31) /*!< top entry of the periodic Tx request queue */ ++#define HPTFQSTAT_PTXREQS GD_BITS(16, 23) /*!< periodic Tx request queue space */ ++#define HPTFQSTAT_PTXFS GD_BITS(0, 15) /*!< periodic Tx FIFO space */ + #define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ +-#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ +-#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +-#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ ++#define HPTFQSTAT_CNUM GD_BITS(27, 30) /*!< channel number */ ++#define HPTFQSTAT_EPNUM GD_BITS(27, 30) /*!< endpoint number */ ++#define HPTFQSTAT_TYPE GD_BITS(25, 26) /*!< token type */ + #define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +-#define TFQSTAT_TXFS BITS(0, 15) +-#define TFQSTAT_CNUM BITS(27, 30) ++#define TFQSTAT_TXFS GD_BITS(0, 15) ++#define TFQSTAT_CNUM GD_BITS(27, 30) + + /* host all channels interrupt register bits definitions */ +-#define HACHINT_HACHINT BITS(0, 11) /*!< host all channel interrupts */ ++#define HACHINT_HACHINT GD_BITS(0, 11) /*!< host all channel interrupts */ + + /* host all channels interrupt enable register bits definitions */ +-#define HACHINTEN_CINTEN BITS(0, 11) /*!< channel interrupt enable */ ++#define HACHINTEN_CINTEN GD_BITS(0, 11) /*!< channel interrupt enable */ + + /* host port control and status register bits definitions */ +-#define HPCS_PS BITS(17, 18) /*!< port speed */ ++#define HPCS_PS GD_BITS(17, 18) /*!< port speed */ + #define HPCS_PP BIT(12) /*!< port power */ +-#define HPCS_PLST BITS(10, 11) /*!< port line status */ ++#define HPCS_PLST GD_BITS(10, 11) /*!< port line status */ + #define HPCS_PRST BIT(8) /*!< port reset */ + #define HPCS_PSP BIT(7) /*!< port suspend */ + #define HPCS_PREM BIT(6) /*!< port resume */ @@ -378,20 +378,20 @@ typedef struct _usb_regs - #define HCHCTL_CEN BIT(31) /*!< channel enable */ - #define HCHCTL_CDIS BIT(30) /*!< channel disable */ - #define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ --#define HCHCTL_DAR BITS(22, 28) /*!< device address */ --#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ --#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -+#define HCHCTL_DAR GD_BITS(22, 28) /*!< device address */ -+#define HCHCTL_MPC GD_BITS(20, 21) /*!< multiple packet count */ -+#define HCHCTL_EPTYPE GD_BITS(18, 19) /*!< endpoint type */ - #define HCHCTL_LSD BIT(17) /*!< low-speed device */ - #define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ --#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ --#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ -+#define HCHCTL_EPNUM GD_BITS(11, 14) /*!< endpoint number */ -+#define HCHCTL_MPL GD_BITS(0, 10) /*!< maximum packet length */ - - /* host channel-x split transaction register bits definitions */ - #define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */ - #define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */ --#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ --#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */ --#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */ -+#define HCHSTCTL_ISOPCE GD_BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ -+#define HCHSTCTL_HADDR GD_BITS(7, 13) /*!< HUB address */ -+#define HCHSTCTL_PADDR GD_BITS(0, 6) /*!< port address */ - - /* host channel-x interrupt flag register bits definitions */ - #define HCHINTF_DTER BIT(10) /*!< data toggle error */ + #define HCHCTL_CEN BIT(31) /*!< channel enable */ + #define HCHCTL_CDIS BIT(30) /*!< channel disable */ + #define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ +-#define HCHCTL_DAR BITS(22, 28) /*!< device address */ +-#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ +-#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ ++#define HCHCTL_DAR GD_BITS(22, 28) /*!< device address */ ++#define HCHCTL_MPC GD_BITS(20, 21) /*!< multiple packet count */ ++#define HCHCTL_EPTYPE GD_BITS(18, 19) /*!< endpoint type */ + #define HCHCTL_LSD BIT(17) /*!< low-speed device */ + #define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ +-#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ +-#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ ++#define HCHCTL_EPNUM GD_BITS(11, 14) /*!< endpoint number */ ++#define HCHCTL_MPL GD_BITS(0, 10) /*!< maximum packet length */ + + /* host channel-x split transaction register bits definitions */ + #define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */ + #define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */ +-#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ +-#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */ +-#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */ ++#define HCHSTCTL_ISOPCE GD_BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ ++#define HCHSTCTL_HADDR GD_BITS(7, 13) /*!< HUB address */ ++#define HCHSTCTL_PADDR GD_BITS(0, 6) /*!< port address */ + + /* host channel-x interrupt flag register bits definitions */ + #define HCHINTF_DTER BIT(10) /*!< data toggle error */ @@ -421,12 +421,12 @@ typedef struct _usb_regs - - /* host channel-x transfer length register bits definitions */ - #define HCHLEN_PING BIT(31) /*!< PING token request */ --#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ --#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ --#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ -+#define HCHLEN_DPID GD_BITS(29, 30) /*!< data PID */ -+#define HCHLEN_PCNT GD_BITS(19, 28) /*!< packet count */ -+#define HCHLEN_TLEN GD_BITS(0, 18) /*!< transfer length */ - - /* host channel-x DMA address register bits definitions */ --#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ -+#define HCHDMAADDR_DMAADDR GD_BITS(0, 31) /*!< DMA address */ - - #define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ - + + /* host channel-x transfer length register bits definitions */ + #define HCHLEN_PING BIT(31) /*!< PING token request */ +-#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ +-#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ +-#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ ++#define HCHLEN_DPID GD_BITS(29, 30) /*!< data PID */ ++#define HCHLEN_PCNT GD_BITS(19, 28) /*!< packet count */ ++#define HCHLEN_TLEN GD_BITS(0, 18) /*!< transfer length */ + + /* host channel-x DMA address register bits definitions */ +-#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ ++#define HCHDMAADDR_DMAADDR GD_BITS(0, 31) /*!< DMA address */ + + #define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ + @@ -452,10 +452,10 @@ typedef struct _usb_regs - extern const uint32_t PIPE_DPID[2]; - - /* device configuration registers bits definitions */ --#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ --#define DCFG_DAR BITS(4, 10) /*!< device address */ -+#define DCFG_EOPFT GD_BITS(11, 12) /*!< end of periodic frame time */ -+#define DCFG_DAR GD_BITS(4, 10) /*!< device address */ - #define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ --#define DCFG_DS BITS(0, 1) /*!< device speed */ -+#define DCFG_DS GD_BITS(0, 1) /*!< device speed */ - - /* device control registers bits definitions */ - #define DCTL_POIF BIT(11) /*!< power-on initialization finished */ + extern const uint32_t PIPE_DPID[2]; + + /* device configuration registers bits definitions */ +-#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ +-#define DCFG_DAR BITS(4, 10) /*!< device address */ ++#define DCFG_EOPFT GD_BITS(11, 12) /*!< end of periodic frame time */ ++#define DCFG_DAR GD_BITS(4, 10) /*!< device address */ + #define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ +-#define DCFG_DS BITS(0, 1) /*!< device speed */ ++#define DCFG_DS GD_BITS(0, 1) /*!< device speed */ + + /* device control registers bits definitions */ + #define DCTL_POIF BIT(11) /*!< power-on initialization finished */ @@ -469,8 +469,8 @@ extern const uint32_t PIPE_DPID[2]; - #define DCTL_RWKUP BIT(0) /*!< remote wakeup */ - - /* device status registers bits definitions */ --#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ --#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ -+#define DSTAT_FNRSOF GD_BITS(8, 21) /*!< the frame number of the received SOF. */ -+#define DSTAT_ES GD_BITS(1, 2) /*!< enumerated speed */ - #define DSTAT_SPST BIT(0) /*!< suspend status */ - - /* device IN endpoint common interrupt enable registers bits definitions */ + #define DCTL_RWKUP BIT(0) /*!< remote wakeup */ + + /* device status registers bits definitions */ +-#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ +-#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ ++#define DSTAT_FNRSOF GD_BITS(8, 21) /*!< the frame number of the received SOF. */ ++#define DSTAT_ES GD_BITS(1, 2) /*!< enumerated speed */ + #define DSTAT_SPST BIT(0) /*!< suspend status */ + + /* device IN endpoint common interrupt enable registers bits definitions */ @@ -491,34 +491,34 @@ extern const uint32_t PIPE_DPID[2]; - #define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - - /* device all endpoints interrupt registers bits definitions */ --#define DAEPINT_OEPITB BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ --#define DAEPINT_IEPITB BITS(0, 5) /*!< device all IN endpoint interrupt bits */ -+#define DAEPINT_OEPITB GD_BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ -+#define DAEPINT_IEPITB GD_BITS(0, 5) /*!< device all IN endpoint interrupt bits */ - - /* device all endpoints interrupt enable registers bits definitions */ --#define DAEPINTEN_OEPIE BITS(16, 21) /*!< OUT endpoint interrupt enable */ --#define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ -+#define DAEPINTEN_OEPIE GD_BITS(16, 21) /*!< OUT endpoint interrupt enable */ -+#define DAEPINTEN_IEPIE GD_BITS(0, 3) /*!< IN endpoint interrupt enable */ - - /* device Vbus discharge time registers bits definitions */ --#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ -+#define DVBUSDT_DVBUSDT GD_BITS(0, 15) /*!< device VBUS discharge time */ - - /* device Vbus pulsing time registers bits definitions */ --#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ -+#define DVBUSPT_DVBUSPT GD_BITS(0, 11) /*!< device VBUS pulsing time */ - - /* device IN endpoint FIFO empty interrupt enable register bits definitions */ --#define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ -+#define DIEPFEINTEN_IEPTXFEIE GD_BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ - - /* device endpoint 0 control register bits definitions */ - #define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ - #define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ - #define DEP0CTL_SNAK BIT(27) /*!< set NAK */ - #define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ --#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -+#define DIEP0CTL_TXFNUM GD_BITS(22, 25) /*!< tx FIFO number */ - #define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ - #define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ --#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -+#define DEP0CTL_EPTYPE GD_BITS(18, 19) /*!< endpoint type */ - #define DEP0CTL_NAKS BIT(17) /*!< NAK status */ - #define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ --#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ -+#define DEP0CTL_MPL GD_BITS(0, 1) /*!< maximum packet length */ - - /* device endpoint x control register bits definitions */ - #define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ + #define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + + /* device all endpoints interrupt registers bits definitions */ +-#define DAEPINT_OEPITB BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ +-#define DAEPINT_IEPITB BITS(0, 5) /*!< device all IN endpoint interrupt bits */ ++#define DAEPINT_OEPITB GD_BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ ++#define DAEPINT_IEPITB GD_BITS(0, 5) /*!< device all IN endpoint interrupt bits */ + + /* device all endpoints interrupt enable registers bits definitions */ +-#define DAEPINTEN_OEPIE BITS(16, 21) /*!< OUT endpoint interrupt enable */ +-#define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ ++#define DAEPINTEN_OEPIE GD_BITS(16, 21) /*!< OUT endpoint interrupt enable */ ++#define DAEPINTEN_IEPIE GD_BITS(0, 3) /*!< IN endpoint interrupt enable */ + + /* device Vbus discharge time registers bits definitions */ +-#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ ++#define DVBUSDT_DVBUSDT GD_BITS(0, 15) /*!< device VBUS discharge time */ + + /* device Vbus pulsing time registers bits definitions */ +-#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ ++#define DVBUSPT_DVBUSPT GD_BITS(0, 11) /*!< device VBUS pulsing time */ + + /* device IN endpoint FIFO empty interrupt enable register bits definitions */ +-#define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ ++#define DIEPFEINTEN_IEPTXFEIE GD_BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ + + /* device endpoint 0 control register bits definitions */ + #define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ + #define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ + #define DEP0CTL_SNAK BIT(27) /*!< set NAK */ + #define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ +-#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ ++#define DIEP0CTL_TXFNUM GD_BITS(22, 25) /*!< tx FIFO number */ + #define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ + #define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ +-#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ ++#define DEP0CTL_EPTYPE GD_BITS(18, 19) /*!< endpoint type */ + #define DEP0CTL_NAKS BIT(17) /*!< NAK status */ + #define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ +-#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ ++#define DEP0CTL_MPL GD_BITS(0, 1) /*!< maximum packet length */ + + /* device endpoint x control register bits definitions */ + #define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ @@ -529,15 +529,15 @@ extern const uint32_t PIPE_DPID[2]; - #define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ - #define DEPCTL_SNAK BIT(27) /*!< set NAK */ - #define DEPCTL_CNAK BIT(26) /*!< clear NAK */ --#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -+#define DIEPCTL_TXFNUM GD_BITS(22, 25) /*!< tx FIFO number */ - #define DEPCTL_STALL BIT(21) /*!< STALL handshake */ - #define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ --#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -+#define DEPCTL_EPTYPE GD_BITS(18, 19) /*!< endpoint type */ - #define DEPCTL_NAKS BIT(17) /*!< NAK status */ - #define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ - #define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ - #define DEPCTL_EPACT BIT(15) /*!< endpoint active */ --#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ -+#define DEPCTL_MPL GD_BITS(0, 10) /*!< maximum packet length */ - - /* device IN endpoint-x interrupt flag register bits definitions */ - #define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */ + #define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ + #define DEPCTL_SNAK BIT(27) /*!< set NAK */ + #define DEPCTL_CNAK BIT(26) /*!< clear NAK */ +-#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ ++#define DIEPCTL_TXFNUM GD_BITS(22, 25) /*!< tx FIFO number */ + #define DEPCTL_STALL BIT(21) /*!< STALL handshake */ + #define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ +-#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ ++#define DEPCTL_EPTYPE GD_BITS(18, 19) /*!< endpoint type */ + #define DEPCTL_NAKS BIT(17) /*!< NAK status */ + #define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ + #define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ + #define DEPCTL_EPACT BIT(15) /*!< endpoint active */ +-#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ ++#define DEPCTL_MPL GD_BITS(0, 10) /*!< maximum packet length */ + + /* device IN endpoint-x interrupt flag register bits definitions */ + #define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */ @@ -557,29 +557,29 @@ extern const uint32_t PIPE_DPID[2]; - #define DOEPINTF_TF BIT(0) /*!< transfer finished */ - - /* device IN endpoint 0 transfer length register bits definitions */ --#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ --#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ -+#define DIEP0LEN_PCNT GD_BITS(19, 20) /*!< packet count */ -+#define DIEP0LEN_TLEN GD_BITS(0, 6) /*!< transfer length */ - - /* device OUT endpoint 0 transfer length register bits definitions */ --#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ -+#define DOEP0LEN_STPCNT GD_BITS(29, 30) /*!< SETUP packet count */ - #define DOEP0LEN_PCNT BIT(19) /*!< packet count */ --#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ -+#define DOEP0LEN_TLEN GD_BITS(0, 6) /*!< transfer length */ - - /* device OUT endpoint-x transfer length register bits definitions */ --#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ --#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ --#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ --#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ --#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ -+#define DOEPLEN_RXDPID GD_BITS(29, 30) /*!< received data PID */ -+#define DOEPLEN_STPCNT GD_BITS(29, 30) /*!< SETUP packet count */ -+#define DIEPLEN_MCNT GD_BITS(29, 30) /*!< multi count */ -+#define DEPLEN_PCNT GD_BITS(19, 28) /*!< packet count */ -+#define DEPLEN_TLEN GD_BITS(0, 18) /*!< transfer length */ - - /* device IN endpoint-x DMA address register bits definitions */ --#define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ -+#define DIEPDMAADDR_DMAADDR GD_BITS(0, 31) /*!< DMA address */ - - /* device OUT endpoint-x DMA address register bits definitions */ --#define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ -+#define DOEPDMAADDR_DMAADDR GD_BITS(0, 31) /*!< DMA address */ - - /* device IN endpoint-x transmit FIFO status register bits definitions */ --#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */ -+#define DIEPTFSTAT_IEPTFS GD_BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */ - - /* USB power and clock registers bits definition */ - #define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ + #define DOEPINTF_TF BIT(0) /*!< transfer finished */ + + /* device IN endpoint 0 transfer length register bits definitions */ +-#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ +-#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ ++#define DIEP0LEN_PCNT GD_BITS(19, 20) /*!< packet count */ ++#define DIEP0LEN_TLEN GD_BITS(0, 6) /*!< transfer length */ + + /* device OUT endpoint 0 transfer length register bits definitions */ +-#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ ++#define DOEP0LEN_STPCNT GD_BITS(29, 30) /*!< SETUP packet count */ + #define DOEP0LEN_PCNT BIT(19) /*!< packet count */ +-#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ ++#define DOEP0LEN_TLEN GD_BITS(0, 6) /*!< transfer length */ + + /* device OUT endpoint-x transfer length register bits definitions */ +-#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ +-#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ +-#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ +-#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ +-#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ ++#define DOEPLEN_RXDPID GD_BITS(29, 30) /*!< received data PID */ ++#define DOEPLEN_STPCNT GD_BITS(29, 30) /*!< SETUP packet count */ ++#define DIEPLEN_MCNT GD_BITS(29, 30) /*!< multi count */ ++#define DEPLEN_PCNT GD_BITS(19, 28) /*!< packet count */ ++#define DEPLEN_TLEN GD_BITS(0, 18) /*!< transfer length */ + + /* device IN endpoint-x DMA address register bits definitions */ +-#define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ ++#define DIEPDMAADDR_DMAADDR GD_BITS(0, 31) /*!< DMA address */ + + /* device OUT endpoint-x DMA address register bits definitions */ +-#define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ ++#define DOEPDMAADDR_DMAADDR GD_BITS(0, 31) /*!< DMA address */ + + /* device IN endpoint-x transmit FIFO status register bits definitions */ +-#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */ ++#define DIEPTFSTAT_IEPTFS GD_BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */ + + /* USB power and clock registers bits definition */ + #define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ diff --git a/targets/bsp/drivers/GD32VF103_Firmware/board.patch b/targets/bsp/drivers/GD32VF103_Firmware/board.patch index 9603575..61e4923 100644 --- a/targets/bsp/drivers/GD32VF103_Firmware/board.patch +++ b/targets/bsp/drivers/GD32VF103_Firmware/board.patch @@ -5,44 +5,44 @@ index d3fb610..a2a2a00 --- a/Inc/gd32vf103.h +++ b/Inc/gd32vf103.h @@ -168,7 +168,7 @@ typedef enum IRQn - CAN1_EWMC_IRQn = 85, /*!< CAN1 EWMC interrupt */ - USBFS_IRQn = 86, /*!< USBFS global interrupt */ - -- ECLIC_NUM_INTERRUPTS -+ ECLIC_NUM_INTERRUPTS - } IRQn_Type; - - /* includes */ + CAN1_EWMC_IRQn = 85, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 86, /*!< USBFS global interrupt */ + +- ECLIC_NUM_INTERRUPTS ++ ECLIC_NUM_INTERRUPTS + } IRQn_Type; + + /* includes */ @@ -177,7 +177,6 @@ typedef enum IRQn - - /* enum definitions */ - typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; --typedef enum {FALSE = 0, TRUE = !FALSE} bool; - typedef enum {RESET = 0, SET = !RESET} FlagStatus; - typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - + + /* enum definitions */ + typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; +-typedef enum {FALSE = 0, TRUE = !FALSE} bool; + typedef enum {RESET = 0, SET = !RESET} FlagStatus; + typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + @@ -186,8 +185,8 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) - #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) - #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) --#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) --#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) -+#define GD_BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -+#define GET_BITS(regval, start, end) (((regval) & GD_BITS((start),(end))) >> (start)) - - /* main flash and SRAM memory map */ - #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ + #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) + #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) + #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +-#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +-#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) ++#define GD_BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) ++#define GET_BITS(regval, start, end) (((regval) & GD_BITS((start),(end))) >> (start)) + + /* main flash and SRAM memory map */ + #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ @@ -228,10 +227,6 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - #define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ - #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ - --/* define marco USE_STDPERIPH_DRIVER */ --#if !defined USE_STDPERIPH_DRIVER --#define USE_STDPERIPH_DRIVER --#endif - #ifdef USE_STDPERIPH_DRIVER - #include "gd32vf103_libopt.h" - #endif /* USE_STDPERIPH_DRIVER */ + #define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ + #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ + +-/* define marco USE_STDPERIPH_DRIVER */ +-#if !defined USE_STDPERIPH_DRIVER +-#define USE_STDPERIPH_DRIVER +-#endif + #ifdef USE_STDPERIPH_DRIVER + #include "gd32vf103_libopt.h" + #endif /* USE_STDPERIPH_DRIVER */ diff --git a/Inc/system_gd32vf103.h b/Inc/system_gd32vf103.h old mode 100644 new mode 100755 diff --git a/targets/bsp/drivers/GD32VF103_Firmware/driver.patch b/targets/bsp/drivers/GD32VF103_Firmware/driver.patch index 260abae..a593bb7 100644 --- a/targets/bsp/drivers/GD32VF103_Firmware/driver.patch +++ b/targets/bsp/drivers/GD32VF103_Firmware/driver.patch @@ -5,186 +5,186 @@ index 8904728..ee23a4f --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h @@ -74,7 +74,7 @@ OF SUCH DAMAGE. - #define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ - - /* ADC_CTL0 */ --#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -+#define ADC_CTL0_WDCHSEL GD_BITS(0,4) /*!< analog watchdog channel select bits */ - #define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ - #define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ - #define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ + #define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ + + /* ADC_CTL0 */ +-#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ ++#define ADC_CTL0_WDCHSEL GD_BITS(0,4) /*!< analog watchdog channel select bits */ + #define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ + #define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ + #define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ @@ -83,8 +83,8 @@ OF SUCH DAMAGE. - #define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ - #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ - #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ --#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ --#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ -+#define ADC_CTL0_DISNUM GD_BITS(13,15) /*!< discontinuous mode channel count */ -+#define ADC_CTL0_SYNCM GD_BITS(16,19) /*!< sync mode selection */ - #define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ - #define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ - + #define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ + #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ + #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +-#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +-#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ ++#define ADC_CTL0_DISNUM GD_BITS(13,15) /*!< discontinuous mode channel count */ ++#define ADC_CTL0_SYNCM GD_BITS(16,19) /*!< sync mode selection */ + #define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ + #define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ + @@ -95,47 +95,47 @@ OF SUCH DAMAGE. - #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ - #define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ - #define ADC_CTL1_DAL BIT(11) /*!< data alignment */ --#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ -+#define ADC_CTL1_ETSIC GD_BITS(12,14) /*!< external trigger select for inserted channel */ - #define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ --#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ -+#define ADC_CTL1_ETSRC GD_BITS(17,19) /*!< external trigger select for regular channel */ - #define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ - #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ - #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ - #define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ - - /* ADC_SAMPTx x=0..1 */ --#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */ -+#define ADC_SAMPTX_SPTN GD_BITS(0,2) /*!< channel n sample time selection */ - - /* ADC_IOFFx x=0..3 */ --#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ -+#define ADC_IOFFX_IOFF GD_BITS(0,11) /*!< data offset for inserted channel x */ - - /* ADC_WDHT */ --#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ -+#define ADC_WDHT_WDHT GD_BITS(0,11) /*!< analog watchdog high threshold */ - - /* ADC_WDLT */ --#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ -+#define ADC_WDLT_WDLT GD_BITS(0,11) /*!< analog watchdog low threshold */ - - /* ADC_RSQx x=0..2 */ --#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */ --#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ -+#define ADC_RSQX_RSQN GD_BITS(0,4) /*!< nth conversion in regular sequence */ -+#define ADC_RSQ0_RL GD_BITS(20,23) /*!< regular channel sequence length */ - - /* ADC_ISQ */ --#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */ --#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ -+#define ADC_ISQ_ISQN GD_BITS(0,4) /*!< nth conversion in inserted sequence */ -+#define ADC_ISQ_IL GD_BITS(20,21) /*!< inserted sequence length */ - - /* ADC_IDATAx x=0..3*/ --#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */ -+#define ADC_IDATAX_IDATAN GD_BITS(0,15) /*!< inserted data n */ - - /* ADC_RDATA */ --#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ --#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ -+#define ADC_RDATA_RDATA GD_BITS(0,15) /*!< regular data */ -+#define ADC_RDATA_ADC1RDTR GD_BITS(16,31) /*!< ADC1 regular channel data */ - - /* ADC_OVSCR */ - #define ADC_OVSCR_OVSEN BIT(0) /*!< oversampling enable */ --#define ADC_OVSCR_OVSR BITS(2,4) /*!< oversampling ratio */ --#define ADC_OVSCR_OVSS BITS(5,8) /*!< oversampling shift */ -+#define ADC_OVSCR_OVSR GD_BITS(2,4) /*!< oversampling ratio */ -+#define ADC_OVSCR_OVSS GD_BITS(5,8) /*!< oversampling shift */ - #define ADC_OVSCR_TOVS BIT(9) /*!< triggered oversampling */ --#define ADC_OVSCR_DRES BITS(12,13) /*!< ADC data resolution */ -+#define ADC_OVSCR_DRES GD_BITS(12,13) /*!< ADC data resolution */ - - /* constants definitions */ - /* adc_stat register value */ + #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ + #define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ + #define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +-#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ ++#define ADC_CTL1_ETSIC GD_BITS(12,14) /*!< external trigger select for inserted channel */ + #define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ +-#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ ++#define ADC_CTL1_ETSRC GD_BITS(17,19) /*!< external trigger select for regular channel */ + #define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ + #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ + #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ + #define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ + + /* ADC_SAMPTx x=0..1 */ +-#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */ ++#define ADC_SAMPTX_SPTN GD_BITS(0,2) /*!< channel n sample time selection */ + + /* ADC_IOFFx x=0..3 */ +-#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ ++#define ADC_IOFFX_IOFF GD_BITS(0,11) /*!< data offset for inserted channel x */ + + /* ADC_WDHT */ +-#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ ++#define ADC_WDHT_WDHT GD_BITS(0,11) /*!< analog watchdog high threshold */ + + /* ADC_WDLT */ +-#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ ++#define ADC_WDLT_WDLT GD_BITS(0,11) /*!< analog watchdog low threshold */ + + /* ADC_RSQx x=0..2 */ +-#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */ +-#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ ++#define ADC_RSQX_RSQN GD_BITS(0,4) /*!< nth conversion in regular sequence */ ++#define ADC_RSQ0_RL GD_BITS(20,23) /*!< regular channel sequence length */ + + /* ADC_ISQ */ +-#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */ +-#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ ++#define ADC_ISQ_ISQN GD_BITS(0,4) /*!< nth conversion in inserted sequence */ ++#define ADC_ISQ_IL GD_BITS(20,21) /*!< inserted sequence length */ + + /* ADC_IDATAx x=0..3*/ +-#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */ ++#define ADC_IDATAX_IDATAN GD_BITS(0,15) /*!< inserted data n */ + + /* ADC_RDATA */ +-#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ +-#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ ++#define ADC_RDATA_RDATA GD_BITS(0,15) /*!< regular data */ ++#define ADC_RDATA_ADC1RDTR GD_BITS(16,31) /*!< ADC1 regular channel data */ + + /* ADC_OVSCR */ + #define ADC_OVSCR_OVSEN BIT(0) /*!< oversampling enable */ +-#define ADC_OVSCR_OVSR BITS(2,4) /*!< oversampling ratio */ +-#define ADC_OVSCR_OVSS BITS(5,8) /*!< oversampling shift */ ++#define ADC_OVSCR_OVSR GD_BITS(2,4) /*!< oversampling ratio */ ++#define ADC_OVSCR_OVSS GD_BITS(5,8) /*!< oversampling shift */ + #define ADC_OVSCR_TOVS BIT(9) /*!< triggered oversampling */ +-#define ADC_OVSCR_DRES BITS(12,13) /*!< ADC data resolution */ ++#define ADC_OVSCR_DRES GD_BITS(12,13) /*!< ADC data resolution */ + + /* constants definitions */ + /* adc_stat register value */ @@ -146,7 +146,7 @@ OF SUCH DAMAGE. - #define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ - - /* adc_ctl0 register value */ --#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ -+#define CTL0_DISNUM(regval) (GD_BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ - - /* scan mode */ - #define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ + #define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ + + /* adc_ctl0 register value */ +-#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ ++#define CTL0_DISNUM(regval) (GD_BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ + + /* scan mode */ + #define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ @@ -155,7 +155,7 @@ OF SUCH DAMAGE. - #define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ - - /* ADC sync mode */ --#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ -+#define CTL0_SYNCM(regval) (GD_BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ - #define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ - #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ - #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ + #define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ + + /* ADC sync mode */ +-#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ ++#define CTL0_SYNCM(regval) (GD_BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ + #define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ + #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ + #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ @@ -175,7 +175,7 @@ OF SUCH DAMAGE. - #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ - - /* external trigger select for regular channel */ --#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ -+#define CTL1_ETSRC(regval) (GD_BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ - /* for ADC0 and ADC1 regular channel */ - #define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ - #define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ + #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + + /* external trigger select for regular channel */ +-#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ ++#define CTL1_ETSRC(regval) (GD_BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ + /* for ADC0 and ADC1 regular channel */ + #define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ + #define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ @@ -187,7 +187,7 @@ OF SUCH DAMAGE. - #define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ - - /* external trigger mode for inserted channel */ --#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ -+#define CTL1_ETSIC(regval) (GD_BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ - /* for ADC0 and ADC1 inserted channel */ - #define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ - #define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ + #define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ + + /* external trigger mode for inserted channel */ +-#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ ++#define CTL1_ETSIC(regval) (GD_BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ + /* for ADC0 and ADC1 inserted channel */ + #define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ + #define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ @@ -199,7 +199,7 @@ OF SUCH DAMAGE. - #define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ - - /* adc_samptx register value */ --#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ -+#define SAMPTX_SPT(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ - #define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ - #define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ - #define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ + #define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ + + /* adc_samptx register value */ +-#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ ++#define SAMPTX_SPT(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ + #define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ + #define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ + #define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ @@ -210,19 +210,19 @@ OF SUCH DAMAGE. - #define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ - - /* adc_ioffx register value */ --#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ -+#define IOFFX_IOFF(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ - - /* adc_wdht register value */ --#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ -+#define WDHT_WDHT(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ - - /* adc_wdlt register value */ --#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ -+#define WDLT_WDLT(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ - - /* adc_rsqx register value */ --#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ -+#define RSQ0_RL(regval) (GD_BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ - - /* adc_isq register value */ --#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ -+#define ISQ_IL(regval) (GD_BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ - - /* ADC channel group definitions */ - #define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ + #define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ + + /* adc_ioffx register value */ +-#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ ++#define IOFFX_IOFF(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ + + /* adc_wdht register value */ +-#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ ++#define WDHT_WDHT(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ + + /* adc_wdlt register value */ +-#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ ++#define WDLT_WDLT(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ + + /* adc_rsqx register value */ +-#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ ++#define RSQ0_RL(regval) (GD_BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ + + /* adc_isq register value */ +-#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ ++#define ISQ_IL(regval) (GD_BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ + + /* ADC channel group definitions */ + #define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ @@ -268,7 +268,7 @@ OF SUCH DAMAGE. - #define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ - - /* ADC resolution definitions */ --#define OVSCR_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -+#define OVSCR_DRES(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) - #define ADC_RESOLUTION_12B OVSCR_DRES(0) /*!< 12-bit ADC resolution */ - #define ADC_RESOLUTION_10B OVSCR_DRES(1) /*!< 10-bit ADC resolution */ - #define ADC_RESOLUTION_8B OVSCR_DRES(2) /*!< 8-bit ADC resolution */ + #define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ + + /* ADC resolution definitions */ +-#define OVSCR_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) ++#define OVSCR_DRES(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) + #define ADC_RESOLUTION_12B OVSCR_DRES(0) /*!< 12-bit ADC resolution */ + #define ADC_RESOLUTION_10B OVSCR_DRES(1) /*!< 10-bit ADC resolution */ + #define ADC_RESOLUTION_8B OVSCR_DRES(2) /*!< 8-bit ADC resolution */ @@ -279,7 +279,7 @@ OF SUCH DAMAGE. - #define ADC_OVERSAMPLING_ONE_CONVERT 1 /*!< each oversampled conversion for a channel needs a trigger */ - - /* ADC oversampling shift */ --#define OVSCR_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) -+#define OVSCR_OVSS(regval) (GD_BITS(5,8) & ((uint32_t)(regval) << 5)) - #define ADC_OVERSAMPLING_SHIFT_NONE OVSCR_OVSS(0) /*!< no oversampling shift */ - #define ADC_OVERSAMPLING_SHIFT_1B OVSCR_OVSS(1) /*!< 1-bit oversampling shift */ - #define ADC_OVERSAMPLING_SHIFT_2B OVSCR_OVSS(2) /*!< 2-bit oversampling shift */ + #define ADC_OVERSAMPLING_ONE_CONVERT 1 /*!< each oversampled conversion for a channel needs a trigger */ + + /* ADC oversampling shift */ +-#define OVSCR_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) ++#define OVSCR_OVSS(regval) (GD_BITS(5,8) & ((uint32_t)(regval) << 5)) + #define ADC_OVERSAMPLING_SHIFT_NONE OVSCR_OVSS(0) /*!< no oversampling shift */ + #define ADC_OVERSAMPLING_SHIFT_1B OVSCR_OVSS(1) /*!< 1-bit oversampling shift */ + #define ADC_OVERSAMPLING_SHIFT_2B OVSCR_OVSS(2) /*!< 2-bit oversampling shift */ @@ -291,7 +291,7 @@ OF SUCH DAMAGE. - #define ADC_OVERSAMPLING_SHIFT_8B OVSCR_OVSS(8) /*!< 8-bit oversampling shift */ - - /* ADC oversampling ratio */ --#define OVSCR_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) -+#define OVSCR_OVSR(regval) (GD_BITS(2,4) & ((uint32_t)(regval) << 2)) - #define ADC_OVERSAMPLING_RATIO_MUL2 OVSCR_OVSR(0) /*!< oversampling ratio X2 */ - #define ADC_OVERSAMPLING_RATIO_MUL4 OVSCR_OVSR(1) /*!< oversampling ratio X4 */ - #define ADC_OVERSAMPLING_RATIO_MUL8 OVSCR_OVSR(2) /*!< oversampling ratio X8 */ + #define ADC_OVERSAMPLING_SHIFT_8B OVSCR_OVSS(8) /*!< 8-bit oversampling shift */ + + /* ADC oversampling ratio */ +-#define OVSCR_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) ++#define OVSCR_OVSR(regval) (GD_BITS(2,4) & ((uint32_t)(regval) << 2)) + #define ADC_OVERSAMPLING_RATIO_MUL2 OVSCR_OVSR(0) /*!< oversampling ratio X2 */ + #define ADC_OVERSAMPLING_RATIO_MUL4 OVSCR_OVSR(1) /*!< oversampling ratio X4 */ + #define ADC_OVERSAMPLING_RATIO_MUL8 OVSCR_OVSR(2) /*!< oversampling ratio X8 */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h old mode 100644 new mode 100755 @@ -192,27 +192,27 @@ index 22f6cae..e6d740a --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h @@ -90,10 +90,10 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* BKP_DATA */ --#define BKP_DATA BITS(0,15) /*!< backup data */ -+#define BKP_DATA GD_BITS(0,15) /*!< backup data */ - - /* BKP_OCTL */ --#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ -+#define BKP_OCTL_RCCV GD_BITS(0,6) /*!< RTC clock calibration value */ - #define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ - #define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ - #define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ + + /* bits definitions */ + /* BKP_DATA */ +-#define BKP_DATA BITS(0,15) /*!< backup data */ ++#define BKP_DATA GD_BITS(0,15) /*!< backup data */ + + /* BKP_OCTL */ +-#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ ++#define BKP_OCTL_RCCV GD_BITS(0,6) /*!< RTC clock calibration value */ + #define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ + #define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ + #define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ @@ -165,7 +165,7 @@ typedef enum - #define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) - - /* RTC clock calibration value */ --#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -+#define OCTL_RCCV(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) - - /* RTC output selection */ - #define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ + #define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) + + /* RTC clock calibration value */ +-#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) ++#define OCTL_RCCV(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) + + /* RTC output selection */ + #define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h old mode 100644 new mode 100755 @@ -220,218 +220,218 @@ index 1f15921..b394f8e --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_can.h @@ -191,7 +191,7 @@ OF SUCH DAMAGE. - #define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ - #define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ - #define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ --#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ -+#define CAN_TSTAT_NUM GD_BITS(24,25) /*!< mailbox number */ - #define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ - #define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ - #define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ + #define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ + #define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ + #define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ +-#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ ++#define CAN_TSTAT_NUM GD_BITS(24,25) /*!< mailbox number */ + #define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ + #define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ + #define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ @@ -200,13 +200,13 @@ OF SUCH DAMAGE. - #define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ - - /* CAN_RFIFO0 */ --#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ -+#define CAN_RFIFO0_RFL0 GD_BITS(0,1) /*!< receive FIFO0 length */ - #define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ - #define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ - #define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ - - /* CAN_RFIFO1 */ --#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ -+#define CAN_RFIFO1_RFL1 GD_BITS(0,1) /*!< receive FIFO1 length */ - #define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ - #define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ - #define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ + #define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ + + /* CAN_RFIFO0 */ +-#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ ++#define CAN_RFIFO0_RFL0 GD_BITS(0,1) /*!< receive FIFO0 length */ + #define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ + #define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ + #define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ + + /* CAN_RFIFO1 */ +-#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ ++#define CAN_RFIFO1_RFL1 GD_BITS(0,1) /*!< receive FIFO1 length */ + #define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ + #define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ + #define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ @@ -231,15 +231,15 @@ OF SUCH DAMAGE. - #define CAN_ERR_WERR BIT(0) /*!< warning error */ - #define CAN_ERR_PERR BIT(1) /*!< passive error */ - #define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ --#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ --#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ --#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ -+#define CAN_ERR_ERRN GD_BITS(4,6) /*!< error number */ -+#define CAN_ERR_TECNT GD_BITS(16,23) /*!< transmit error count */ -+#define CAN_ERR_RECNT GD_BITS(24,31) /*!< receive error count */ - - /* CAN_BT */ --#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ --#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ --#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ --#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ -+#define CAN_BT_BAUDPSC GD_BITS(0,9) /*!< baudrate prescaler */ -+#define CAN_BT_BS1 GD_BITS(16,19) /*!< bit segment 1 */ -+#define CAN_BT_BS2 GD_BITS(20,22) /*!< bit segment 2 */ -+#define CAN_BT_SJW GD_BITS(24,25) /*!< resynchronization jump width */ - #define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ - #define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ - + #define CAN_ERR_WERR BIT(0) /*!< warning error */ + #define CAN_ERR_PERR BIT(1) /*!< passive error */ + #define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ +-#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ +-#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ +-#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ ++#define CAN_ERR_ERRN GD_BITS(4,6) /*!< error number */ ++#define CAN_ERR_TECNT GD_BITS(16,23) /*!< transmit error count */ ++#define CAN_ERR_RECNT GD_BITS(24,31) /*!< receive error count */ + + /* CAN_BT */ +-#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ +-#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ +-#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ +-#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ ++#define CAN_BT_BAUDPSC GD_BITS(0,9) /*!< baudrate prescaler */ ++#define CAN_BT_BS1 GD_BITS(16,19) /*!< bit segment 1 */ ++#define CAN_BT_BS2 GD_BITS(20,22) /*!< bit segment 2 */ ++#define CAN_BT_SJW GD_BITS(24,25) /*!< resynchronization jump width */ + #define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ + #define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ + @@ -247,52 +247,52 @@ OF SUCH DAMAGE. - #define CAN_TMI_TEN BIT(0) /*!< transmit enable */ - #define CAN_TMI_FT BIT(1) /*!< frame type */ - #define CAN_TMI_FF BIT(2) /*!< frame format */ --#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ --#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ -+#define CAN_TMI_EFID GD_BITS(3,31) /*!< the frame identifier */ -+#define CAN_TMI_SFID GD_BITS(21,31) /*!< the frame identifier */ - - /* CAN_TMPx */ --#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ -+#define CAN_TMP_DLENC GD_BITS(0,3) /*!< data length code */ - #define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ --#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ -+#define CAN_TMP_TS GD_BITS(16,31) /*!< time stamp */ - - /* CAN_TMDATA0x */ --#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ --#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ --#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ --#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ -+#define CAN_TMDATA0_DB0 GD_BITS(0,7) /*!< transmit data byte 0 */ -+#define CAN_TMDATA0_DB1 GD_BITS(8,15) /*!< transmit data byte 1 */ -+#define CAN_TMDATA0_DB2 GD_BITS(16,23) /*!< transmit data byte 2 */ -+#define CAN_TMDATA0_DB3 GD_BITS(24,31) /*!< transmit data byte 3 */ - - /* CAN_TMDATA1x */ --#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ --#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ --#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ --#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ -+#define CAN_TMDATA1_DB4 GD_BITS(0,7) /*!< transmit data byte 4 */ -+#define CAN_TMDATA1_DB5 GD_BITS(8,15) /*!< transmit data byte 5 */ -+#define CAN_TMDATA1_DB6 GD_BITS(16,23) /*!< transmit data byte 6 */ -+#define CAN_TMDATA1_DB7 GD_BITS(24,31) /*!< transmit data byte 7 */ - - /* CAN_RFIFOMIx */ - #define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ - #define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ --#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ --#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ -+#define CAN_RFIFOMI_EFID GD_BITS(3,31) /*!< the frame identifier */ -+#define CAN_RFIFOMI_SFID GD_BITS(21,31) /*!< the frame identifier */ - - /* CAN_RFIFOMPx */ --#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ --#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ --#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ -+#define CAN_RFIFOMP_DLENC GD_BITS(0,3) /*!< receive data length code */ -+#define CAN_RFIFOMP_FI GD_BITS(8,15) /*!< filter index */ -+#define CAN_RFIFOMP_TS GD_BITS(16,31) /*!< time stamp */ - - /* CAN_RFIFOMDATA0x */ --#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ --#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ --#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ --#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ -+#define CAN_RFIFOMDATA0_DB0 GD_BITS(0,7) /*!< receive data byte 0 */ -+#define CAN_RFIFOMDATA0_DB1 GD_BITS(8,15) /*!< receive data byte 1 */ -+#define CAN_RFIFOMDATA0_DB2 GD_BITS(16,23) /*!< receive data byte 2 */ -+#define CAN_RFIFOMDATA0_DB3 GD_BITS(24,31) /*!< receive data byte 3 */ - - /* CAN_RFIFOMDATA1x */ --#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ --#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ --#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ --#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ -+#define CAN_RFIFOMDATA1_DB4 GD_BITS(0,7) /*!< receive data byte 4 */ -+#define CAN_RFIFOMDATA1_DB5 GD_BITS(8,15) /*!< receive data byte 5 */ -+#define CAN_RFIFOMDATA1_DB6 GD_BITS(16,23) /*!< receive data byte 6 */ -+#define CAN_RFIFOMDATA1_DB7 GD_BITS(24,31) /*!< receive data byte 7 */ - - /* CAN_FCTL */ - #define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ --#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ -+#define CAN_FCTL_HBC1F GD_BITS(8,13) /*!< header bank of CAN1 filter */ - - /* CAN_FMCFG */ - #define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ + #define CAN_TMI_TEN BIT(0) /*!< transmit enable */ + #define CAN_TMI_FT BIT(1) /*!< frame type */ + #define CAN_TMI_FF BIT(2) /*!< frame format */ +-#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ +-#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ ++#define CAN_TMI_EFID GD_BITS(3,31) /*!< the frame identifier */ ++#define CAN_TMI_SFID GD_BITS(21,31) /*!< the frame identifier */ + + /* CAN_TMPx */ +-#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ ++#define CAN_TMP_DLENC GD_BITS(0,3) /*!< data length code */ + #define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ +-#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ ++#define CAN_TMP_TS GD_BITS(16,31) /*!< time stamp */ + + /* CAN_TMDATA0x */ +-#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ +-#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ +-#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ +-#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ ++#define CAN_TMDATA0_DB0 GD_BITS(0,7) /*!< transmit data byte 0 */ ++#define CAN_TMDATA0_DB1 GD_BITS(8,15) /*!< transmit data byte 1 */ ++#define CAN_TMDATA0_DB2 GD_BITS(16,23) /*!< transmit data byte 2 */ ++#define CAN_TMDATA0_DB3 GD_BITS(24,31) /*!< transmit data byte 3 */ + + /* CAN_TMDATA1x */ +-#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ +-#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ +-#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ +-#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ ++#define CAN_TMDATA1_DB4 GD_BITS(0,7) /*!< transmit data byte 4 */ ++#define CAN_TMDATA1_DB5 GD_BITS(8,15) /*!< transmit data byte 5 */ ++#define CAN_TMDATA1_DB6 GD_BITS(16,23) /*!< transmit data byte 6 */ ++#define CAN_TMDATA1_DB7 GD_BITS(24,31) /*!< transmit data byte 7 */ + + /* CAN_RFIFOMIx */ + #define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ + #define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ +-#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ +-#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ ++#define CAN_RFIFOMI_EFID GD_BITS(3,31) /*!< the frame identifier */ ++#define CAN_RFIFOMI_SFID GD_BITS(21,31) /*!< the frame identifier */ + + /* CAN_RFIFOMPx */ +-#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ +-#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ +-#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ ++#define CAN_RFIFOMP_DLENC GD_BITS(0,3) /*!< receive data length code */ ++#define CAN_RFIFOMP_FI GD_BITS(8,15) /*!< filter index */ ++#define CAN_RFIFOMP_TS GD_BITS(16,31) /*!< time stamp */ + + /* CAN_RFIFOMDATA0x */ +-#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ +-#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ +-#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ +-#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ ++#define CAN_RFIFOMDATA0_DB0 GD_BITS(0,7) /*!< receive data byte 0 */ ++#define CAN_RFIFOMDATA0_DB1 GD_BITS(8,15) /*!< receive data byte 1 */ ++#define CAN_RFIFOMDATA0_DB2 GD_BITS(16,23) /*!< receive data byte 2 */ ++#define CAN_RFIFOMDATA0_DB3 GD_BITS(24,31) /*!< receive data byte 3 */ + + /* CAN_RFIFOMDATA1x */ +-#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ +-#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ +-#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ +-#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ ++#define CAN_RFIFOMDATA1_DB4 GD_BITS(0,7) /*!< receive data byte 4 */ ++#define CAN_RFIFOMDATA1_DB5 GD_BITS(8,15) /*!< receive data byte 5 */ ++#define CAN_RFIFOMDATA1_DB6 GD_BITS(16,23) /*!< receive data byte 6 */ ++#define CAN_RFIFOMDATA1_DB7 GD_BITS(24,31) /*!< receive data byte 7 */ + + /* CAN_FCTL */ + #define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ +-#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ ++#define CAN_FCTL_HBC1F GD_BITS(8,13) /*!< header bank of CAN1 filter */ + + /* CAN_FMCFG */ + #define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ @@ -481,58 +481,58 @@ typedef enum - }can_struct_type_enum; - - /* CAN baudrate prescaler*/ --#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) -+#define BT_BAUDPSC(regval) (GD_BITS(0,9) & ((uint32_t)(regval) << 0)) - - /* CAN bit segment 1*/ --#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) -+#define BT_BS1(regval) (GD_BITS(16,19) & ((uint32_t)(regval) << 16)) - - /* CAN bit segment 2*/ --#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) -+#define BT_BS2(regval) (GD_BITS(20,22) & ((uint32_t)(regval) << 20)) - - /* CAN resynchronization jump width*/ --#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) -+#define BT_SJW(regval) (GD_BITS(24,25) & ((uint32_t)(regval) << 24)) - - /* CAN communication mode*/ --#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) -+#define BT_MODE(regval) (GD_BITS(30,31) & ((uint32_t)(regval) << 30)) - - /* CAN FDATA high 16 bits */ --#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) -+#define FDATA_MASK_HIGH(regval) (GD_BITS(16,31) & ((uint32_t)(regval) << 16)) - - /* CAN FDATA low 16 bits */ --#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -+#define FDATA_MASK_LOW(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) - - /* CAN1 filter start bank_number*/ --#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) -+#define FCTL_HBC1F(regval) (GD_BITS(8,13) & ((uint32_t)(regval) << 8)) - - /* CAN transmit mailbox extended identifier*/ --#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) -+#define TMI_EFID(regval) (GD_BITS(3,31) & ((uint32_t)(regval) << 3)) - - /* CAN transmit mailbox standard identifier*/ --#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) -+#define TMI_SFID(regval) (GD_BITS(21,31) & ((uint32_t)(regval) << 21)) - - /* transmit data byte 0 */ --#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) -+#define TMDATA0_DB0(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) - - /* transmit data byte 1 */ --#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) -+#define TMDATA0_DB1(regval) (GD_BITS(8,15) & ((uint32_t)(regval) << 8)) - - /* transmit data byte 2 */ --#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -+#define TMDATA0_DB2(regval) (GD_BITS(16,23) & ((uint32_t)(regval) << 16)) - - /* transmit data byte 3 */ --#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) -+#define TMDATA0_DB3(regval) (GD_BITS(24,31) & ((uint32_t)(regval) << 24)) - - /* transmit data byte 4 */ --#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) -+#define TMDATA1_DB4(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) - - /* transmit data byte 5 */ --#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) -+#define TMDATA1_DB5(regval) (GD_BITS(8,15) & ((uint32_t)(regval) << 8)) - - /* transmit data byte 6 */ --#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -+#define TMDATA1_DB6(regval) (GD_BITS(16,23) & ((uint32_t)(regval) << 16)) - - /* transmit data byte 7 */ --#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) -+#define TMDATA1_DB7(regval) (GD_BITS(24,31) & ((uint32_t)(regval) << 24)) - - /* receive mailbox extended identifier*/ - #define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) + }can_struct_type_enum; + + /* CAN baudrate prescaler*/ +-#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) ++#define BT_BAUDPSC(regval) (GD_BITS(0,9) & ((uint32_t)(regval) << 0)) + + /* CAN bit segment 1*/ +-#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) ++#define BT_BS1(regval) (GD_BITS(16,19) & ((uint32_t)(regval) << 16)) + + /* CAN bit segment 2*/ +-#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) ++#define BT_BS2(regval) (GD_BITS(20,22) & ((uint32_t)(regval) << 20)) + + /* CAN resynchronization jump width*/ +-#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) ++#define BT_SJW(regval) (GD_BITS(24,25) & ((uint32_t)(regval) << 24)) + + /* CAN communication mode*/ +-#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) ++#define BT_MODE(regval) (GD_BITS(30,31) & ((uint32_t)(regval) << 30)) + + /* CAN FDATA high 16 bits */ +-#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) ++#define FDATA_MASK_HIGH(regval) (GD_BITS(16,31) & ((uint32_t)(regval) << 16)) + + /* CAN FDATA low 16 bits */ +-#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) ++#define FDATA_MASK_LOW(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) + + /* CAN1 filter start bank_number*/ +-#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) ++#define FCTL_HBC1F(regval) (GD_BITS(8,13) & ((uint32_t)(regval) << 8)) + + /* CAN transmit mailbox extended identifier*/ +-#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) ++#define TMI_EFID(regval) (GD_BITS(3,31) & ((uint32_t)(regval) << 3)) + + /* CAN transmit mailbox standard identifier*/ +-#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) ++#define TMI_SFID(regval) (GD_BITS(21,31) & ((uint32_t)(regval) << 21)) + + /* transmit data byte 0 */ +-#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) ++#define TMDATA0_DB0(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) + + /* transmit data byte 1 */ +-#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) ++#define TMDATA0_DB1(regval) (GD_BITS(8,15) & ((uint32_t)(regval) << 8)) + + /* transmit data byte 2 */ +-#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) ++#define TMDATA0_DB2(regval) (GD_BITS(16,23) & ((uint32_t)(regval) << 16)) + + /* transmit data byte 3 */ +-#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) ++#define TMDATA0_DB3(regval) (GD_BITS(24,31) & ((uint32_t)(regval) << 24)) + + /* transmit data byte 4 */ +-#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) ++#define TMDATA1_DB4(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) + + /* transmit data byte 5 */ +-#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) ++#define TMDATA1_DB5(regval) (GD_BITS(8,15) & ((uint32_t)(regval) << 8)) + + /* transmit data byte 6 */ +-#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) ++#define TMDATA1_DB6(regval) (GD_BITS(16,23) & ((uint32_t)(regval) << 16)) + + /* transmit data byte 7 */ +-#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) ++#define TMDATA1_DB7(regval) (GD_BITS(24,31) & ((uint32_t)(regval) << 24)) + + /* receive mailbox extended identifier*/ + #define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) @@ -580,7 +580,7 @@ typedef enum - #define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) - - /* CAN errors */ --#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -+#define ERR_ERRN(regval) (GD_BITS(4,6) & ((uint32_t)(regval) << 4)) - #define CAN_ERRN_0 ERR_ERRN(0U) /* no error */ - #define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ - #define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ + #define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) + + /* CAN errors */ +-#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) ++#define ERR_ERRN(regval) (GD_BITS(4,6) & ((uint32_t)(regval) << 4)) + #define CAN_ERRN_0 ERR_ERRN(0U) /* no error */ + #define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ + #define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h old mode 100644 new mode 100755 @@ -439,18 +439,18 @@ index d73a7d3..a217490 --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h @@ -48,10 +48,10 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* CRC_DATA */ --#define CRC_DATA_DATA BITS(0, 31) /*!< CRC calculation result bits */ -+#define CRC_DATA_DATA GD_BITS(0, 31) /*!< CRC calculation result bits */ - - /* CRC_FDATA */ --#define CRC_FDATA_FDATA BITS(0, 7) /*!< CRC free data bits */ -+#define CRC_FDATA_FDATA GD_BITS(0, 7) /*!< CRC free data bits */ - - /* CRC_CTL */ - #define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ + + /* bits definitions */ + /* CRC_DATA */ +-#define CRC_DATA_DATA BITS(0, 31) /*!< CRC calculation result bits */ ++#define CRC_DATA_DATA GD_BITS(0, 31) /*!< CRC calculation result bits */ + + /* CRC_FDATA */ +-#define CRC_FDATA_FDATA BITS(0, 7) /*!< CRC free data bits */ ++#define CRC_FDATA_FDATA GD_BITS(0, 7) /*!< CRC free data bits */ + + /* CRC_CTL */ + #define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h old mode 100644 new mode 100755 @@ -458,113 +458,113 @@ index 87bec12..3c28fe2 --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h @@ -63,16 +63,16 @@ OF SUCH DAMAGE. - #define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ - #define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ - #define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ --#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ --#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ --#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ -+#define DAC_CTL_DTSEL0 GD_BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ -+#define DAC_CTL_DWM0 GD_BITS(6,7) /*!< DAC0 noise wave mode */ -+#define DAC_CTL_DWBW0 GD_BITS(8,11) /*!< DAC0 noise wave bit width */ - #define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ - #define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ - #define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ - #define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ --#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ --#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ --#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ -+#define DAC_CTL_DTSEL1 GD_BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ -+#define DAC_CTL_DWM1 GD_BITS(22,23) /*!< DAC1 noise wave mode */ -+#define DAC_CTL_DWBW1 GD_BITS(24,27) /*!< DAC1 noise wave bit width */ - #define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ - - /* DAC_SWT */ + #define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ + #define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ + #define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +-#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +-#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +-#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ ++#define DAC_CTL_DTSEL0 GD_BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ ++#define DAC_CTL_DWM0 GD_BITS(6,7) /*!< DAC0 noise wave mode */ ++#define DAC_CTL_DWBW0 GD_BITS(8,11) /*!< DAC0 noise wave bit width */ + #define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ + #define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ + #define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ + #define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +-#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +-#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +-#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ ++#define DAC_CTL_DTSEL1 GD_BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ ++#define DAC_CTL_DWM1 GD_BITS(22,23) /*!< DAC1 noise wave mode */ ++#define DAC_CTL_DWBW1 GD_BITS(24,27) /*!< DAC1 noise wave bit width */ + #define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ + + /* DAC_SWT */ @@ -80,44 +80,44 @@ OF SUCH DAMAGE. - #define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ - - /* DAC0_R12DH */ --#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ -+#define DAC0_R12DH_DAC0_DH GD_BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ - - /* DAC0_L12DH */ --#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ -+#define DAC0_L12DH_DAC0_DH GD_BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ - - /* DAC0_R8DH */ --#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ -+#define DAC0_R8DH_DAC0_DH GD_BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ - - /* DAC1_R12DH */ --#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ -+#define DAC1_R12DH_DAC1_DH GD_BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ - - /* DAC1_L12DH */ --#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ -+#define DAC1_L12DH_DAC1_DH GD_BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ - - /* DAC1_R8DH */ --#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ -+#define DAC1_R8DH_DAC1_DH GD_BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ - - /* DACC_R12DH */ --#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ --#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ -+#define DACC_R12DH_DAC0_DH GD_BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ -+#define DACC_R12DH_DAC1_DH GD_BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ - - /* DACC_L12DH */ --#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ --#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ -+#define DACC_L12DH_DAC0_DH GD_BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ -+#define DACC_L12DH_DAC1_DH GD_BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ - - /* DACC_R8DH */ --#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ --#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ -+#define DACC_R8DH_DAC0_DH GD_BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ -+#define DACC_R8DH_DAC1_DH GD_BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ - - /* DAC0_DO */ --#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ -+#define DAC0_DO_DAC0_DO GD_BITS(0,11) /*!< DAC0 12-bit output data bits */ - - /* DAC1_DO */ --#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ -+#define DAC1_DO_DAC1_DO GD_BITS(0,11) /*!< DAC1 12-bit output data bits */ - - /* constants definitions */ - /* DAC trigger source */ --#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -+#define CTL_DTSEL(regval) (GD_BITS(3,5) & ((uint32_t)(regval) << 3)) - #define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ - #define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ - #define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ + #define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ + + /* DAC0_R12DH */ +-#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ ++#define DAC0_R12DH_DAC0_DH GD_BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ + + /* DAC0_L12DH */ +-#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ ++#define DAC0_L12DH_DAC0_DH GD_BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ + + /* DAC0_R8DH */ +-#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ ++#define DAC0_R8DH_DAC0_DH GD_BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ + + /* DAC1_R12DH */ +-#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ ++#define DAC1_R12DH_DAC1_DH GD_BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ + + /* DAC1_L12DH */ +-#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ ++#define DAC1_L12DH_DAC1_DH GD_BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ + + /* DAC1_R8DH */ +-#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ ++#define DAC1_R8DH_DAC1_DH GD_BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ + + /* DACC_R12DH */ +-#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +-#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ ++#define DACC_R12DH_DAC0_DH GD_BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ ++#define DACC_R12DH_DAC1_DH GD_BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ + + /* DACC_L12DH */ +-#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +-#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ ++#define DACC_L12DH_DAC0_DH GD_BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ ++#define DACC_L12DH_DAC1_DH GD_BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ + + /* DACC_R8DH */ +-#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +-#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ ++#define DACC_R8DH_DAC0_DH GD_BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ ++#define DACC_R8DH_DAC1_DH GD_BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ + + /* DAC0_DO */ +-#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ ++#define DAC0_DO_DAC0_DO GD_BITS(0,11) /*!< DAC0 12-bit output data bits */ + + /* DAC1_DO */ +-#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ ++#define DAC1_DO_DAC1_DO GD_BITS(0,11) /*!< DAC1 12-bit output data bits */ + + /* constants definitions */ + /* DAC trigger source */ +-#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) ++#define CTL_DTSEL(regval) (GD_BITS(3,5) & ((uint32_t)(regval) << 3)) + #define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ + #define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ + #define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ @@ -128,13 +128,13 @@ OF SUCH DAMAGE. - #define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ - - /* DAC noise wave mode */ --#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -+#define CTL_DWM(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6)) - #define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ - #define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ - #define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ - - /* DAC noise wave bit width */ --#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -+#define DWBW(regval) (GD_BITS(8,11) & ((uint32_t)(regval) << 8)) - #define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ - #define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ - #define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ + #define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ + + /* DAC noise wave mode */ +-#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) ++#define CTL_DWM(regval) (GD_BITS(6,7) & ((uint32_t)(regval) << 6)) + #define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ + #define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ + #define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ + + /* DAC noise wave bit width */ +-#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) ++#define DWBW(regval) (GD_BITS(8,11) & ((uint32_t)(regval) << 8)) + #define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ + #define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ + #define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ @@ -163,7 +163,7 @@ OF SUCH DAMAGE. - #define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ - - /* DAC data alignment */ --#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -+#define DATA_ALIGN(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) - #define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ - #define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ - #define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ + #define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + + /* DAC data alignment */ +-#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) ++#define DATA_ALIGN(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) + #define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ + #define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ + #define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h old mode 100644 new mode 100755 @@ -572,14 +572,14 @@ index 885e9aa..bffbc16 --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h @@ -47,7 +47,7 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* DBG_ID */ --#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ -+#define DBG_ID_ID_CODE GD_BITS(0,31) /*!< DBG ID code values */ - - /* DBG_CTL */ - #define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ + + /* bits definitions */ + /* DBG_ID */ +-#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ ++#define DBG_ID_ID_CODE GD_BITS(0,31) /*!< DBG ID code values */ + + /* DBG_CTL */ + #define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h old mode 100644 new mode 100755 @@ -587,54 +587,54 @@ index 1120123..9d9e2b1 --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h @@ -104,19 +104,19 @@ OF SUCH DAMAGE. - #define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ - #define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ - #define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ --#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ --#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ --#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ -+#define DMA_CHXCTL_PWIDTH GD_BITS(8,9) /*!< transfer data width of peripheral */ -+#define DMA_CHXCTL_MWIDTH GD_BITS(10,11) /*!< transfer data width of memory */ -+#define DMA_CHXCTL_PRIO GD_BITS(12,13) /*!< priority level */ - #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ - - /* DMA_CHxCNT, x=0..6 */ --#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ -+#define DMA_CHXCNT_CNT GD_BITS(0,15) /*!< transfer counter */ - - /* DMA_CHxPADDR, x=0..6 */ --#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ -+#define DMA_CHXPADDR_PADDR GD_BITS(0,31) /*!< peripheral base address */ - - /* DMA_CHxMADDR, x=0..6 */ --#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ -+#define DMA_CHXMADDR_MADDR GD_BITS(0,31) /*!< memory base address */ - - /* constants definitions */ - /* DMA channel select */ + #define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ + #define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ + #define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ +-#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ +-#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ +-#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ ++#define DMA_CHXCTL_PWIDTH GD_BITS(8,9) /*!< transfer data width of peripheral */ ++#define DMA_CHXCTL_MWIDTH GD_BITS(10,11) /*!< transfer data width of memory */ ++#define DMA_CHXCTL_PRIO GD_BITS(12,13) /*!< priority level */ + #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ + + /* DMA_CHxCNT, x=0..6 */ +-#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ ++#define DMA_CHXCNT_CNT GD_BITS(0,15) /*!< transfer counter */ + + /* DMA_CHxPADDR, x=0..6 */ +-#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ ++#define DMA_CHXPADDR_PADDR GD_BITS(0,31) /*!< peripheral base address */ + + /* DMA_CHxMADDR, x=0..6 */ +-#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ ++#define DMA_CHXMADDR_MADDR GD_BITS(0,31) /*!< memory base address */ + + /* constants definitions */ + /* DMA channel select */ @@ -194,19 +194,19 @@ typedef struct - #define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of memory is increasing address mode */ - - /* transfer data size of peripheral */ --#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ -+#define CHCTL_PWIDTH(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ - #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ - #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ - #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ - - /* transfer data size of memory */ --#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ -+#define CHCTL_MWIDTH(regval) (GD_BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ - #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ - #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ - #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ - - /* channel priority level */ --#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ -+#define CHCTL_PRIO(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ - #define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ - #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ - #define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ + #define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of memory is increasing address mode */ + + /* transfer data size of peripheral */ +-#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ ++#define CHCTL_PWIDTH(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ + #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ + #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ + #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ + + /* transfer data size of memory */ +-#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ ++#define CHCTL_MWIDTH(regval) (GD_BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ + #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ + #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ + #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ + + /* channel priority level */ +-#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ ++#define CHCTL_PRIO(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ + #define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ + #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ + #define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h old mode 100644 new mode 100755 @@ -642,46 +642,46 @@ index 39ed7c2..35a9bbf --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h @@ -52,8 +52,8 @@ OF SUCH DAMAGE. - /* EXMC_SNCTLx, x=0 */ - #define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ - #define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ --#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ --#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ -+#define EXMC_SNCTL_NRTP GD_BITS(2,3) /*!< NOR bank memory type */ -+#define EXMC_SNCTL_NRW GD_BITS(4,5) /*!< NOR bank memory data bus width */ - #define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ - #define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ - #define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ + /* EXMC_SNCTLx, x=0 */ + #define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ + #define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ +-#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ +-#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ ++#define EXMC_SNCTL_NRTP GD_BITS(2,3) /*!< NOR bank memory type */ ++#define EXMC_SNCTL_NRW GD_BITS(4,5) /*!< NOR bank memory data bus width */ + #define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ + #define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ + #define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ @@ -61,10 +61,10 @@ OF SUCH DAMAGE. - #define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ - - /* EXMC_SNTCFGx, x=0 */ --#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ --#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ --#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ --#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ -+#define EXMC_SNTCFG_ASET GD_BITS(0,3) /*!< address setup time */ -+#define EXMC_SNTCFG_AHLD GD_BITS(4,7) /*!< address hold time */ -+#define EXMC_SNTCFG_DSET GD_BITS(8,15) /*!< data setup time */ -+#define EXMC_SNTCFG_BUSLAT GD_BITS(16,19) /*!< bus latency */ - - /* constants definitions */ - /* EXMC NOR/SRAM timing initialize struct */ + #define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ + + /* EXMC_SNTCFGx, x=0 */ +-#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ +-#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ +-#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ +-#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ ++#define EXMC_SNTCFG_ASET GD_BITS(0,3) /*!< address setup time */ ++#define EXMC_SNTCFG_AHLD GD_BITS(4,7) /*!< address hold time */ ++#define EXMC_SNTCFG_DSET GD_BITS(8,15) /*!< data setup time */ ++#define EXMC_SNTCFG_BUSLAT GD_BITS(16,19) /*!< bus latency */ + + /* constants definitions */ + /* EXMC NOR/SRAM timing initialize struct */ @@ -95,12 +95,12 @@ typedef struct - #define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ - - /* NOR bank memory data bus width */ --#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -+#define SNCTL_NRW(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) - #define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ - #define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ - - /* NOR bank memory type */ --#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -+#define SNCTL_NRTP(regval) (GD_BITS(2,3) & ((uint32_t)(regval) << 2)) - #define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ - #define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ - #define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ + #define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ + + /* NOR bank memory data bus width */ +-#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) ++#define SNCTL_NRW(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) + #define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ + #define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ + + /* NOR bank memory type */ +-#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) ++#define SNCTL_NRTP(regval) (GD_BITS(2,3) & ((uint32_t)(regval) << 2)) + #define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ + #define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ + #define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h old mode 100644 new mode 100755 @@ -689,59 +689,59 @@ index 0ba1144..9c61087 --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h @@ -64,13 +64,13 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* FMC_WS */ --#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ -+#define FMC_WS_WSCNT GD_BITS(0,2) /*!< wait state counter */ - - /* FMC_KEY */ --#define FMC_KEY_KEY BITS(0,31) /*!< FMC_CTL unlock key bits */ -+#define FMC_KEY_KEY GD_BITS(0,31) /*!< FMC_CTL unlock key bits */ - - /* FMC_OBKEY */ --#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ -+#define FMC_OBKEY_OBKEY GD_BITS(0,31) /*!< option bytes unlock key bits */ - - /* FMC_STAT */ - #define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ + + /* bits definitions */ + /* FMC_WS */ +-#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ ++#define FMC_WS_WSCNT GD_BITS(0,2) /*!< wait state counter */ + + /* FMC_KEY */ +-#define FMC_KEY_KEY BITS(0,31) /*!< FMC_CTL unlock key bits */ ++#define FMC_KEY_KEY GD_BITS(0,31) /*!< FMC_CTL unlock key bits */ + + /* FMC_OBKEY */ +-#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ ++#define FMC_OBKEY_OBKEY GD_BITS(0,31) /*!< option bytes unlock key bits */ + + /* FMC_STAT */ + #define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ @@ -91,22 +91,22 @@ OF SUCH DAMAGE. - #define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ - - /* FMC_ADDR */ --#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ -+#define FMC_ADDR0_ADDR GD_BITS(0,31) /*!< Flash erase/program command address bits */ - - /* FMC_OBSTAT */ - #define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ - #define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ --#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ --#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ -+#define FMC_OBSTAT_USER GD_BITS(2,9) /*!< store USER of option bytes block after system reset */ -+#define FMC_OBSTAT_DATA GD_BITS(10,25) /*!< store DATA of option bytes block after system reset. */ - - /* FMC_WP */ --#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ -+#define FMC_WP_WP GD_BITS(0,31) /*!< store WP of option bytes block after system reset */ - - /* FMC_WSEN */ - #define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ - - /* FMC_PID */ --#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ -+#define FMC_PID_PID GD_BITS(0,31) /*!< product ID bits */ - - /* constants definitions */ - /* define the FMC bit position and its register index offset */ + #define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ + + /* FMC_ADDR */ +-#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ ++#define FMC_ADDR0_ADDR GD_BITS(0,31) /*!< Flash erase/program command address bits */ + + /* FMC_OBSTAT */ + #define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ + #define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ +-#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ +-#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ ++#define FMC_OBSTAT_USER GD_BITS(2,9) /*!< store USER of option bytes block after system reset */ ++#define FMC_OBSTAT_DATA GD_BITS(10,25) /*!< store DATA of option bytes block after system reset. */ + + /* FMC_WP */ +-#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ ++#define FMC_WP_WP GD_BITS(0,31) /*!< store WP of option bytes block after system reset */ + + /* FMC_WSEN */ + #define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ + + /* FMC_PID */ +-#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ ++#define FMC_PID_PID GD_BITS(0,31) /*!< product ID bits */ + + /* constants definitions */ + /* define the FMC bit position and its register index offset */ @@ -163,7 +163,7 @@ typedef enum - #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ - - /* FMC wait state counter */ --#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) -+#define WS_WSCNT(regval) (GD_BITS(0,2) & ((uint32_t)(regval))) - #define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ - #define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ - #define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ + #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ + + /* FMC wait state counter */ +-#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) ++#define WS_WSCNT(regval) (GD_BITS(0,2) & ((uint32_t)(regval))) + #define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ + #define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ + #define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h old mode 100644 new mode 100755 @@ -749,31 +749,31 @@ index 824f8d4..803c5a7 --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h @@ -49,13 +49,13 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* FWDGT_CTL */ --#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ -+#define FWDGT_CTL_CMD GD_BITS(0,15) /*!< FWDGT command value */ - - /* FWDGT_PSC */ --#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ -+#define FWDGT_PSC_PSC GD_BITS(0,2) /*!< FWDGT prescaler divider value */ - - /* FWDGT_RLD */ --#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ -+#define FWDGT_RLD_RLD GD_BITS(0,11) /*!< FWDGT counter reload value */ - - /* FWDGT_STAT */ - #define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ + + /* bits definitions */ + /* FWDGT_CTL */ +-#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ ++#define FWDGT_CTL_CMD GD_BITS(0,15) /*!< FWDGT command value */ + + /* FWDGT_PSC */ +-#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ ++#define FWDGT_PSC_PSC GD_BITS(0,2) /*!< FWDGT prescaler divider value */ + + /* FWDGT_RLD */ +-#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ ++#define FWDGT_RLD_RLD GD_BITS(0,11) /*!< FWDGT counter reload value */ + + /* FWDGT_STAT */ + #define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ @@ -63,7 +63,7 @@ OF SUCH DAMAGE. - - /* constants definitions */ - /* psc register value */ --#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -+#define PSC_PSC(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) - #define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ - #define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ - #define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ + + /* constants definitions */ + /* psc register value */ +-#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) ++#define PSC_PSC(regval) (GD_BITS(0,2) & ((uint32_t)(regval) << 0)) + #define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ + #define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ + #define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h old mode 100644 new mode 100755 @@ -781,162 +781,162 @@ index 07d3b4c..59227e8 --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h @@ -70,40 +70,40 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* GPIO_CTL0 */ --#define GPIO_CTL0_MD0 BITS(0, 1) /*!< port 0 mode bits */ --#define GPIO_CTL0_CTL0 BITS(2, 3) /*!< pin 0 configuration bits */ --#define GPIO_CTL0_MD1 BITS(4, 5) /*!< port 1 mode bits */ --#define GPIO_CTL0_CTL1 BITS(6, 7) /*!< pin 1 configuration bits */ --#define GPIO_CTL0_MD2 BITS(8, 9) /*!< port 2 mode bits */ --#define GPIO_CTL0_CTL2 BITS(10, 11) /*!< pin 2 configuration bits */ --#define GPIO_CTL0_MD3 BITS(12, 13) /*!< port 3 mode bits */ --#define GPIO_CTL0_CTL3 BITS(14, 15) /*!< pin 3 configuration bits */ --#define GPIO_CTL0_MD4 BITS(16, 17) /*!< port 4 mode bits */ --#define GPIO_CTL0_CTL4 BITS(18, 19) /*!< pin 4 configuration bits */ --#define GPIO_CTL0_MD5 BITS(20, 21) /*!< port 5 mode bits */ --#define GPIO_CTL0_CTL5 BITS(22, 23) /*!< pin 5 configuration bits */ --#define GPIO_CTL0_MD6 BITS(24, 25) /*!< port 6 mode bits */ --#define GPIO_CTL0_CTL6 BITS(26, 27) /*!< pin 6 configuration bits */ --#define GPIO_CTL0_MD7 BITS(28, 29) /*!< port 7 mode bits */ --#define GPIO_CTL0_CTL7 BITS(30, 31) /*!< pin 7 configuration bits */ -+#define GPIO_CTL0_MD0 GD_BITS(0, 1) /*!< port 0 mode bits */ -+#define GPIO_CTL0_CTL0 GD_BITS(2, 3) /*!< pin 0 configuration bits */ -+#define GPIO_CTL0_MD1 GD_BITS(4, 5) /*!< port 1 mode bits */ -+#define GPIO_CTL0_CTL1 GD_BITS(6, 7) /*!< pin 1 configuration bits */ -+#define GPIO_CTL0_MD2 GD_BITS(8, 9) /*!< port 2 mode bits */ -+#define GPIO_CTL0_CTL2 GD_BITS(10, 11) /*!< pin 2 configuration bits */ -+#define GPIO_CTL0_MD3 GD_BITS(12, 13) /*!< port 3 mode bits */ -+#define GPIO_CTL0_CTL3 GD_BITS(14, 15) /*!< pin 3 configuration bits */ -+#define GPIO_CTL0_MD4 GD_BITS(16, 17) /*!< port 4 mode bits */ -+#define GPIO_CTL0_CTL4 GD_BITS(18, 19) /*!< pin 4 configuration bits */ -+#define GPIO_CTL0_MD5 GD_BITS(20, 21) /*!< port 5 mode bits */ -+#define GPIO_CTL0_CTL5 GD_BITS(22, 23) /*!< pin 5 configuration bits */ -+#define GPIO_CTL0_MD6 GD_BITS(24, 25) /*!< port 6 mode bits */ -+#define GPIO_CTL0_CTL6 GD_BITS(26, 27) /*!< pin 6 configuration bits */ -+#define GPIO_CTL0_MD7 GD_BITS(28, 29) /*!< port 7 mode bits */ -+#define GPIO_CTL0_CTL7 GD_BITS(30, 31) /*!< pin 7 configuration bits */ - - /* GPIO_CTL1 */ --#define GPIO_CTL1_MD8 BITS(0, 1) /*!< port 8 mode bits */ --#define GPIO_CTL1_CTL8 BITS(2, 3) /*!< pin 8 configuration bits */ --#define GPIO_CTL1_MD9 BITS(4, 5) /*!< port 9 mode bits */ --#define GPIO_CTL1_CTL9 BITS(6, 7) /*!< pin 9 configuration bits */ --#define GPIO_CTL1_MD10 BITS(8, 9) /*!< port 10 mode bits */ --#define GPIO_CTL1_CTL10 BITS(10, 11) /*!< pin 10 configuration bits */ --#define GPIO_CTL1_MD11 BITS(12, 13) /*!< port 11 mode bits */ --#define GPIO_CTL1_CTL11 BITS(14, 15) /*!< pin 11 configuration bits */ --#define GPIO_CTL1_MD12 BITS(16, 17) /*!< port 12 mode bits */ --#define GPIO_CTL1_CTL12 BITS(18, 19) /*!< pin 12 configuration bits */ --#define GPIO_CTL1_MD13 BITS(20, 21) /*!< port 13 mode bits */ --#define GPIO_CTL1_CTL13 BITS(22, 23) /*!< pin 13 configuration bits */ --#define GPIO_CTL1_MD14 BITS(24, 25) /*!< port 14 mode bits */ --#define GPIO_CTL1_CTL14 BITS(26, 27) /*!< pin 14 configuration bits */ --#define GPIO_CTL1_MD15 BITS(28, 29) /*!< port 15 mode bits */ --#define GPIO_CTL1_CTL15 BITS(30, 31) /*!< pin 15 configuration bits */ -+#define GPIO_CTL1_MD8 GD_BITS(0, 1) /*!< port 8 mode bits */ -+#define GPIO_CTL1_CTL8 GD_BITS(2, 3) /*!< pin 8 configuration bits */ -+#define GPIO_CTL1_MD9 GD_BITS(4, 5) /*!< port 9 mode bits */ -+#define GPIO_CTL1_CTL9 GD_BITS(6, 7) /*!< pin 9 configuration bits */ -+#define GPIO_CTL1_MD10 GD_BITS(8, 9) /*!< port 10 mode bits */ -+#define GPIO_CTL1_CTL10 GD_BITS(10, 11) /*!< pin 10 configuration bits */ -+#define GPIO_CTL1_MD11 GD_BITS(12, 13) /*!< port 11 mode bits */ -+#define GPIO_CTL1_CTL11 GD_BITS(14, 15) /*!< pin 11 configuration bits */ -+#define GPIO_CTL1_MD12 GD_BITS(16, 17) /*!< port 12 mode bits */ -+#define GPIO_CTL1_CTL12 GD_BITS(18, 19) /*!< pin 12 configuration bits */ -+#define GPIO_CTL1_MD13 GD_BITS(20, 21) /*!< port 13 mode bits */ -+#define GPIO_CTL1_CTL13 GD_BITS(22, 23) /*!< pin 13 configuration bits */ -+#define GPIO_CTL1_MD14 GD_BITS(24, 25) /*!< port 14 mode bits */ -+#define GPIO_CTL1_CTL14 GD_BITS(26, 27) /*!< pin 14 configuration bits */ -+#define GPIO_CTL1_MD15 GD_BITS(28, 29) /*!< port 15 mode bits */ -+#define GPIO_CTL1_CTL15 GD_BITS(30, 31) /*!< pin 15 configuration bits */ - - /* GPIO_ISTAT */ - #define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ + + /* bits definitions */ + /* GPIO_CTL0 */ +-#define GPIO_CTL0_MD0 BITS(0, 1) /*!< port 0 mode bits */ +-#define GPIO_CTL0_CTL0 BITS(2, 3) /*!< pin 0 configuration bits */ +-#define GPIO_CTL0_MD1 BITS(4, 5) /*!< port 1 mode bits */ +-#define GPIO_CTL0_CTL1 BITS(6, 7) /*!< pin 1 configuration bits */ +-#define GPIO_CTL0_MD2 BITS(8, 9) /*!< port 2 mode bits */ +-#define GPIO_CTL0_CTL2 BITS(10, 11) /*!< pin 2 configuration bits */ +-#define GPIO_CTL0_MD3 BITS(12, 13) /*!< port 3 mode bits */ +-#define GPIO_CTL0_CTL3 BITS(14, 15) /*!< pin 3 configuration bits */ +-#define GPIO_CTL0_MD4 BITS(16, 17) /*!< port 4 mode bits */ +-#define GPIO_CTL0_CTL4 BITS(18, 19) /*!< pin 4 configuration bits */ +-#define GPIO_CTL0_MD5 BITS(20, 21) /*!< port 5 mode bits */ +-#define GPIO_CTL0_CTL5 BITS(22, 23) /*!< pin 5 configuration bits */ +-#define GPIO_CTL0_MD6 BITS(24, 25) /*!< port 6 mode bits */ +-#define GPIO_CTL0_CTL6 BITS(26, 27) /*!< pin 6 configuration bits */ +-#define GPIO_CTL0_MD7 BITS(28, 29) /*!< port 7 mode bits */ +-#define GPIO_CTL0_CTL7 BITS(30, 31) /*!< pin 7 configuration bits */ ++#define GPIO_CTL0_MD0 GD_BITS(0, 1) /*!< port 0 mode bits */ ++#define GPIO_CTL0_CTL0 GD_BITS(2, 3) /*!< pin 0 configuration bits */ ++#define GPIO_CTL0_MD1 GD_BITS(4, 5) /*!< port 1 mode bits */ ++#define GPIO_CTL0_CTL1 GD_BITS(6, 7) /*!< pin 1 configuration bits */ ++#define GPIO_CTL0_MD2 GD_BITS(8, 9) /*!< port 2 mode bits */ ++#define GPIO_CTL0_CTL2 GD_BITS(10, 11) /*!< pin 2 configuration bits */ ++#define GPIO_CTL0_MD3 GD_BITS(12, 13) /*!< port 3 mode bits */ ++#define GPIO_CTL0_CTL3 GD_BITS(14, 15) /*!< pin 3 configuration bits */ ++#define GPIO_CTL0_MD4 GD_BITS(16, 17) /*!< port 4 mode bits */ ++#define GPIO_CTL0_CTL4 GD_BITS(18, 19) /*!< pin 4 configuration bits */ ++#define GPIO_CTL0_MD5 GD_BITS(20, 21) /*!< port 5 mode bits */ ++#define GPIO_CTL0_CTL5 GD_BITS(22, 23) /*!< pin 5 configuration bits */ ++#define GPIO_CTL0_MD6 GD_BITS(24, 25) /*!< port 6 mode bits */ ++#define GPIO_CTL0_CTL6 GD_BITS(26, 27) /*!< pin 6 configuration bits */ ++#define GPIO_CTL0_MD7 GD_BITS(28, 29) /*!< port 7 mode bits */ ++#define GPIO_CTL0_CTL7 GD_BITS(30, 31) /*!< pin 7 configuration bits */ + + /* GPIO_CTL1 */ +-#define GPIO_CTL1_MD8 BITS(0, 1) /*!< port 8 mode bits */ +-#define GPIO_CTL1_CTL8 BITS(2, 3) /*!< pin 8 configuration bits */ +-#define GPIO_CTL1_MD9 BITS(4, 5) /*!< port 9 mode bits */ +-#define GPIO_CTL1_CTL9 BITS(6, 7) /*!< pin 9 configuration bits */ +-#define GPIO_CTL1_MD10 BITS(8, 9) /*!< port 10 mode bits */ +-#define GPIO_CTL1_CTL10 BITS(10, 11) /*!< pin 10 configuration bits */ +-#define GPIO_CTL1_MD11 BITS(12, 13) /*!< port 11 mode bits */ +-#define GPIO_CTL1_CTL11 BITS(14, 15) /*!< pin 11 configuration bits */ +-#define GPIO_CTL1_MD12 BITS(16, 17) /*!< port 12 mode bits */ +-#define GPIO_CTL1_CTL12 BITS(18, 19) /*!< pin 12 configuration bits */ +-#define GPIO_CTL1_MD13 BITS(20, 21) /*!< port 13 mode bits */ +-#define GPIO_CTL1_CTL13 BITS(22, 23) /*!< pin 13 configuration bits */ +-#define GPIO_CTL1_MD14 BITS(24, 25) /*!< port 14 mode bits */ +-#define GPIO_CTL1_CTL14 BITS(26, 27) /*!< pin 14 configuration bits */ +-#define GPIO_CTL1_MD15 BITS(28, 29) /*!< port 15 mode bits */ +-#define GPIO_CTL1_CTL15 BITS(30, 31) /*!< pin 15 configuration bits */ ++#define GPIO_CTL1_MD8 GD_BITS(0, 1) /*!< port 8 mode bits */ ++#define GPIO_CTL1_CTL8 GD_BITS(2, 3) /*!< pin 8 configuration bits */ ++#define GPIO_CTL1_MD9 GD_BITS(4, 5) /*!< port 9 mode bits */ ++#define GPIO_CTL1_CTL9 GD_BITS(6, 7) /*!< pin 9 configuration bits */ ++#define GPIO_CTL1_MD10 GD_BITS(8, 9) /*!< port 10 mode bits */ ++#define GPIO_CTL1_CTL10 GD_BITS(10, 11) /*!< pin 10 configuration bits */ ++#define GPIO_CTL1_MD11 GD_BITS(12, 13) /*!< port 11 mode bits */ ++#define GPIO_CTL1_CTL11 GD_BITS(14, 15) /*!< pin 11 configuration bits */ ++#define GPIO_CTL1_MD12 GD_BITS(16, 17) /*!< port 12 mode bits */ ++#define GPIO_CTL1_CTL12 GD_BITS(18, 19) /*!< pin 12 configuration bits */ ++#define GPIO_CTL1_MD13 GD_BITS(20, 21) /*!< port 13 mode bits */ ++#define GPIO_CTL1_CTL13 GD_BITS(22, 23) /*!< pin 13 configuration bits */ ++#define GPIO_CTL1_MD14 GD_BITS(24, 25) /*!< port 14 mode bits */ ++#define GPIO_CTL1_CTL14 GD_BITS(26, 27) /*!< pin 14 configuration bits */ ++#define GPIO_CTL1_MD15 GD_BITS(28, 29) /*!< port 15 mode bits */ ++#define GPIO_CTL1_CTL15 GD_BITS(30, 31) /*!< pin 15 configuration bits */ + + /* GPIO_ISTAT */ + #define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ @@ -213,8 +213,8 @@ OF SUCH DAMAGE. - #define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ - - /* AFIO_EC */ --#define AFIO_EC_PIN BITS(0, 3) /*!< event output pin selection */ --#define AFIO_EC_PORT BITS(4, 6) /*!< event output port selection */ -+#define AFIO_EC_PIN GD_BITS(0, 3) /*!< event output pin selection */ -+#define AFIO_EC_PORT GD_BITS(4, 6) /*!< event output port selection */ - #define AFIO_EC_EOE BIT(7) /*!< event output enable */ - - /* AFIO_PCF0 */ + #define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ + + /* AFIO_EC */ +-#define AFIO_EC_PIN BITS(0, 3) /*!< event output pin selection */ +-#define AFIO_EC_PORT BITS(4, 6) /*!< event output port selection */ ++#define AFIO_EC_PIN GD_BITS(0, 3) /*!< event output pin selection */ ++#define AFIO_EC_PORT GD_BITS(4, 6) /*!< event output port selection */ + #define AFIO_EC_EOE BIT(7) /*!< event output enable */ + + /* AFIO_PCF0 */ @@ -222,41 +222,41 @@ OF SUCH DAMAGE. - #define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ - #define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ - #define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ --#define AFIO_PCF0_USART2_REMAP BITS(4, 5) /*!< USART2 remapping */ --#define AFIO_PCF0_TIMER0_REMAP BITS(6, 7) /*!< TIMER0 remapping */ --#define AFIO_PCF0_TIMER1_REMAP BITS(8, 9) /*!< TIMER1 remapping */ --#define AFIO_PCF0_TIMER2_REMAP BITS(10, 11) /*!< TIMER2 remapping */ -+#define AFIO_PCF0_USART2_REMAP GD_BITS(4, 5) /*!< USART2 remapping */ -+#define AFIO_PCF0_TIMER0_REMAP GD_BITS(6, 7) /*!< TIMER0 remapping */ -+#define AFIO_PCF0_TIMER1_REMAP GD_BITS(8, 9) /*!< TIMER1 remapping */ -+#define AFIO_PCF0_TIMER2_REMAP GD_BITS(10, 11) /*!< TIMER2 remapping */ - #define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ --#define AFIO_PCF0_CAN_REMAP BITS(13, 14) /*!< CAN remapping */ -+#define AFIO_PCF0_CAN_REMAP GD_BITS(13, 14) /*!< CAN remapping */ - #define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ - #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER3 channel3 internal remapping */ --#define AFIO_PCF0_SWJ_CFG BITS(24, 26) /*!< serial wire JTAG configuration */ -+#define AFIO_PCF0_SWJ_CFG GD_BITS(24, 26) /*!< serial wire JTAG configuration */ - #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ - #define AFIO_PCF0_TIMER1_ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */ - - /* AFIO_EXTISS0 */ --#define AFIO_EXTI0_SS BITS(0, 3) /*!< EXTI 0 sources selection */ --#define AFIO_EXTI1_SS BITS(4, 7) /*!< EXTI 1 sources selection */ --#define AFIO_EXTI2_SS BITS(8, 11) /*!< EXTI 2 sources selection */ --#define AFIO_EXTI3_SS BITS(12, 15) /*!< EXTI 3 sources selection */ -+#define AFIO_EXTI0_SS GD_BITS(0, 3) /*!< EXTI 0 sources selection */ -+#define AFIO_EXTI1_SS GD_BITS(4, 7) /*!< EXTI 1 sources selection */ -+#define AFIO_EXTI2_SS GD_BITS(8, 11) /*!< EXTI 2 sources selection */ -+#define AFIO_EXTI3_SS GD_BITS(12, 15) /*!< EXTI 3 sources selection */ - - /* AFIO_EXTISS1 */ --#define AFIO_EXTI4_SS BITS(0, 3) /*!< EXTI 4 sources selection */ --#define AFIO_EXTI5_SS BITS(4, 7) /*!< EXTI 5 sources selection */ --#define AFIO_EXTI6_SS BITS(8, 11) /*!< EXTI 6 sources selection */ --#define AFIO_EXTI7_SS BITS(12, 15) /*!< EXTI 7 sources selection */ -+#define AFIO_EXTI4_SS GD_BITS(0, 3) /*!< EXTI 4 sources selection */ -+#define AFIO_EXTI5_SS GD_BITS(4, 7) /*!< EXTI 5 sources selection */ -+#define AFIO_EXTI6_SS GD_BITS(8, 11) /*!< EXTI 6 sources selection */ -+#define AFIO_EXTI7_SS GD_BITS(12, 15) /*!< EXTI 7 sources selection */ - - /* AFIO_EXTISS2 */ --#define AFIO_EXTI8_SS BITS(0, 3) /*!< EXTI 8 sources selection */ --#define AFIO_EXTI9_SS BITS(4, 7) /*!< EXTI 9 sources selection */ --#define AFIO_EXTI10_SS BITS(8, 11) /*!< EXTI 10 sources selection */ --#define AFIO_EXTI11_SS BITS(12, 15) /*!< EXTI 11 sources selection */ -+#define AFIO_EXTI8_SS GD_BITS(0, 3) /*!< EXTI 8 sources selection */ -+#define AFIO_EXTI9_SS GD_BITS(4, 7) /*!< EXTI 9 sources selection */ -+#define AFIO_EXTI10_SS GD_BITS(8, 11) /*!< EXTI 10 sources selection */ -+#define AFIO_EXTI11_SS GD_BITS(12, 15) /*!< EXTI 11 sources selection */ - - /* AFIO_EXTISS3 */ --#define AFIO_EXTI12_SS BITS(0, 3) /*!< EXTI 12 sources selection */ --#define AFIO_EXTI13_SS BITS(4, 7) /*!< EXTI 13 sources selection */ --#define AFIO_EXTI14_SS BITS(8, 11) /*!< EXTI 14 sources selection */ --#define AFIO_EXTI15_SS BITS(12, 15) /*!< EXTI 15 sources selection */ -+#define AFIO_EXTI12_SS GD_BITS(0, 3) /*!< EXTI 12 sources selection */ -+#define AFIO_EXTI13_SS GD_BITS(4, 7) /*!< EXTI 13 sources selection */ -+#define AFIO_EXTI14_SS GD_BITS(8, 11) /*!< EXTI 14 sources selection */ -+#define AFIO_EXTI15_SS GD_BITS(12, 15) /*!< EXTI 15 sources selection */ - - /* AFIO_PCF1 */ - #define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ + #define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ + #define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ + #define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ +-#define AFIO_PCF0_USART2_REMAP BITS(4, 5) /*!< USART2 remapping */ +-#define AFIO_PCF0_TIMER0_REMAP BITS(6, 7) /*!< TIMER0 remapping */ +-#define AFIO_PCF0_TIMER1_REMAP BITS(8, 9) /*!< TIMER1 remapping */ +-#define AFIO_PCF0_TIMER2_REMAP BITS(10, 11) /*!< TIMER2 remapping */ ++#define AFIO_PCF0_USART2_REMAP GD_BITS(4, 5) /*!< USART2 remapping */ ++#define AFIO_PCF0_TIMER0_REMAP GD_BITS(6, 7) /*!< TIMER0 remapping */ ++#define AFIO_PCF0_TIMER1_REMAP GD_BITS(8, 9) /*!< TIMER1 remapping */ ++#define AFIO_PCF0_TIMER2_REMAP GD_BITS(10, 11) /*!< TIMER2 remapping */ + #define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ +-#define AFIO_PCF0_CAN_REMAP BITS(13, 14) /*!< CAN remapping */ ++#define AFIO_PCF0_CAN_REMAP GD_BITS(13, 14) /*!< CAN remapping */ + #define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ + #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER3 channel3 internal remapping */ +-#define AFIO_PCF0_SWJ_CFG BITS(24, 26) /*!< serial wire JTAG configuration */ ++#define AFIO_PCF0_SWJ_CFG GD_BITS(24, 26) /*!< serial wire JTAG configuration */ + #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ + #define AFIO_PCF0_TIMER1_ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */ + + /* AFIO_EXTISS0 */ +-#define AFIO_EXTI0_SS BITS(0, 3) /*!< EXTI 0 sources selection */ +-#define AFIO_EXTI1_SS BITS(4, 7) /*!< EXTI 1 sources selection */ +-#define AFIO_EXTI2_SS BITS(8, 11) /*!< EXTI 2 sources selection */ +-#define AFIO_EXTI3_SS BITS(12, 15) /*!< EXTI 3 sources selection */ ++#define AFIO_EXTI0_SS GD_BITS(0, 3) /*!< EXTI 0 sources selection */ ++#define AFIO_EXTI1_SS GD_BITS(4, 7) /*!< EXTI 1 sources selection */ ++#define AFIO_EXTI2_SS GD_BITS(8, 11) /*!< EXTI 2 sources selection */ ++#define AFIO_EXTI3_SS GD_BITS(12, 15) /*!< EXTI 3 sources selection */ + + /* AFIO_EXTISS1 */ +-#define AFIO_EXTI4_SS BITS(0, 3) /*!< EXTI 4 sources selection */ +-#define AFIO_EXTI5_SS BITS(4, 7) /*!< EXTI 5 sources selection */ +-#define AFIO_EXTI6_SS BITS(8, 11) /*!< EXTI 6 sources selection */ +-#define AFIO_EXTI7_SS BITS(12, 15) /*!< EXTI 7 sources selection */ ++#define AFIO_EXTI4_SS GD_BITS(0, 3) /*!< EXTI 4 sources selection */ ++#define AFIO_EXTI5_SS GD_BITS(4, 7) /*!< EXTI 5 sources selection */ ++#define AFIO_EXTI6_SS GD_BITS(8, 11) /*!< EXTI 6 sources selection */ ++#define AFIO_EXTI7_SS GD_BITS(12, 15) /*!< EXTI 7 sources selection */ + + /* AFIO_EXTISS2 */ +-#define AFIO_EXTI8_SS BITS(0, 3) /*!< EXTI 8 sources selection */ +-#define AFIO_EXTI9_SS BITS(4, 7) /*!< EXTI 9 sources selection */ +-#define AFIO_EXTI10_SS BITS(8, 11) /*!< EXTI 10 sources selection */ +-#define AFIO_EXTI11_SS BITS(12, 15) /*!< EXTI 11 sources selection */ ++#define AFIO_EXTI8_SS GD_BITS(0, 3) /*!< EXTI 8 sources selection */ ++#define AFIO_EXTI9_SS GD_BITS(4, 7) /*!< EXTI 9 sources selection */ ++#define AFIO_EXTI10_SS GD_BITS(8, 11) /*!< EXTI 10 sources selection */ ++#define AFIO_EXTI11_SS GD_BITS(12, 15) /*!< EXTI 11 sources selection */ + + /* AFIO_EXTISS3 */ +-#define AFIO_EXTI12_SS BITS(0, 3) /*!< EXTI 12 sources selection */ +-#define AFIO_EXTI13_SS BITS(4, 7) /*!< EXTI 13 sources selection */ +-#define AFIO_EXTI14_SS BITS(8, 11) /*!< EXTI 14 sources selection */ +-#define AFIO_EXTI15_SS BITS(12, 15) /*!< EXTI 15 sources selection */ ++#define AFIO_EXTI12_SS GD_BITS(0, 3) /*!< EXTI 12 sources selection */ ++#define AFIO_EXTI13_SS GD_BITS(4, 7) /*!< EXTI 13 sources selection */ ++#define AFIO_EXTI14_SS GD_BITS(8, 11) /*!< EXTI 14 sources selection */ ++#define AFIO_EXTI15_SS GD_BITS(12, 15) /*!< EXTI 15 sources selection */ + + /* AFIO_PCF1 */ + #define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ @@ -350,7 +350,7 @@ typedef FlagStatus bit_status; - #define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ - #define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ - #define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ --#define GPIO_PIN_ALL BITS(0, 15) /*!< GPIO pin all */ -+#define GPIO_PIN_ALL GD_BITS(0, 15) /*!< GPIO pin all */ - - /* GPIO remap definitions */ - #define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */ + #define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ + #define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ + #define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +-#define GPIO_PIN_ALL BITS(0, 15) /*!< GPIO pin all */ ++#define GPIO_PIN_ALL GD_BITS(0, 15) /*!< GPIO pin all */ + + /* GPIO remap definitions */ + #define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h old mode 100644 new mode 100755 @@ -944,63 +944,63 @@ index deb37a8..b2dc3ad --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h @@ -71,7 +71,7 @@ OF SUCH DAMAGE. - #define I2C_CTL0_SRESET BIT(15) /*!< software reset */ - - /* I2Cx_CTL1 */ --#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ -+#define I2C_CTL1_I2CCLK GD_BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ - #define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ - #define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ - #define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ + #define I2C_CTL0_SRESET BIT(15) /*!< software reset */ + + /* I2Cx_CTL1 */ +-#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ ++#define I2C_CTL1_I2CCLK GD_BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ + #define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ + #define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ + #define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ @@ -80,16 +80,16 @@ OF SUCH DAMAGE. - - /* I2Cx_SADDR0 */ - #define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ --#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ --#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -+#define I2C_SADDR0_ADDRESS GD_BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -+#define I2C_SADDR0_ADDRESS_H GD_BITS(8,9) /*!< highest two bits of a 10-bit address */ - #define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ - - /* I2Cx_SADDR1 */ - #define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ --#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ -+#define I2C_SADDR1_ADDRESS2 GD_BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ - - /* I2Cx_DATA */ --#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ -+#define I2C_DATA_TRB GD_BITS(0,7) /*!< 8-bit data register */ - - /* I2Cx_STAT0 */ - #define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ + + /* I2Cx_SADDR0 */ + #define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +-#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +-#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ ++#define I2C_SADDR0_ADDRESS GD_BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ ++#define I2C_SADDR0_ADDRESS_H GD_BITS(8,9) /*!< highest two bits of a 10-bit address */ + #define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ + + /* I2Cx_SADDR1 */ + #define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +-#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ ++#define I2C_SADDR1_ADDRESS2 GD_BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ + + /* I2Cx_DATA */ +-#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ ++#define I2C_DATA_TRB GD_BITS(0,7) /*!< 8-bit data register */ + + /* I2Cx_STAT0 */ + #define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ @@ -115,15 +115,15 @@ OF SUCH DAMAGE. - #define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ - #define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ - #define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ --#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ -+#define I2C_STAT1_PECV GD_BITS(8,15) /*!< packet error checking value */ - - /* I2Cx_CKCFG */ --#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ -+#define I2C_CKCFG_CLKC GD_BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ - #define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ - #define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ - - /* I2Cx_RT */ --#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ -+#define I2C_RT_RISETIME GD_BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ - - /* I2Cx_FMPCFG */ - #define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ + #define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ + #define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ + #define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +-#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ ++#define I2C_STAT1_PECV GD_BITS(8,15) /*!< packet error checking value */ + + /* I2Cx_CKCFG */ +-#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ ++#define I2C_CKCFG_CLKC GD_BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ + #define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ + #define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ + + /* I2Cx_RT */ +-#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ ++#define I2C_RT_RISETIME GD_BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ + + /* I2Cx_FMPCFG */ + #define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ @@ -261,7 +261,7 @@ typedef enum { - #define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ - - /* transmit I2C data */ --#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) -+#define DATA_TRANS(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) - - /* receive I2C data */ - #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) + #define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ + + /* transmit I2C data */ +-#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) ++#define DATA_TRANS(regval) (GD_BITS(0,7) & ((uint32_t)(regval) << 0)) + + /* receive I2C data */ + #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h old mode 100644 new mode 100755 @@ -1008,23 +1008,23 @@ index 59d014a..37ff29f --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h @@ -52,7 +52,7 @@ OF SUCH DAMAGE. - #define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ - #define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ - #define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ --#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ -+#define PMU_CTL_LVDT GD_BITS(5,7) /*!< low voltage detector threshold */ - #define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ - - /* PMU_CS */ + #define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ + #define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ + #define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +-#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ ++#define PMU_CTL_LVDT GD_BITS(5,7) /*!< low voltage detector threshold */ + #define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ + + /* PMU_CS */ @@ -63,7 +63,7 @@ OF SUCH DAMAGE. - - /* constants definitions */ - /* PMU low voltage detector threshold definitions */ --#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5)) -+#define CTL_LVDT(regval) (GD_BITS(5,7)&((uint32_t)(regval) << 5)) - #define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */ - #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ - #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ + + /* constants definitions */ + /* PMU low voltage detector threshold definitions */ +-#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5)) ++#define CTL_LVDT(regval) (GD_BITS(5,7)&((uint32_t)(regval) << 5)) + #define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */ + #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ + #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h old mode 100644 new mode 100755 @@ -1032,194 +1032,194 @@ index 3045a75..eeff357 --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h @@ -62,8 +62,8 @@ OF SUCH DAMAGE. - /* RCU_CTL */ - #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ - #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ --#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ --#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -+#define RCU_CTL_IRC8MADJ GD_BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -+#define RCU_CTL_IRC8MCALIB GD_BITS(8,15) /*!< high speed internal oscillator calibration value register */ - #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ - #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ - #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ + /* RCU_CTL */ + #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ + #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +-#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +-#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ ++#define RCU_CTL_IRC8MADJ GD_BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ ++#define RCU_CTL_IRC8MCALIB GD_BITS(8,15) /*!< high speed internal oscillator calibration value register */ + #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ + #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ + #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ @@ -76,17 +76,17 @@ OF SUCH DAMAGE. - #define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ - - --#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ --#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ --#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ --#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ --#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ --#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ -+#define RCU_CFG0_SCS GD_BITS(0,1) /*!< system clock switch */ -+#define RCU_CFG0_SCSS GD_BITS(2,3) /*!< system clock switch status */ -+#define RCU_CFG0_AHBPSC GD_BITS(4,7) /*!< AHB prescaler selection */ -+#define RCU_CFG0_APB1PSC GD_BITS(8,10) /*!< APB1 prescaler selection */ -+#define RCU_CFG0_APB2PSC GD_BITS(11,13) /*!< APB2 prescaler selection */ -+#define RCU_CFG0_ADCPSC GD_BITS(14,15) /*!< ADC prescaler selection */ - #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ - #define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ --#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ --#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ --#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ -+#define RCU_CFG0_PLLMF GD_BITS(18,21) /*!< PLL clock multiplication factor */ -+#define RCU_CFG0_USBFSPSC GD_BITS(22,23) /*!< USBFS clock prescaler selection */ -+#define RCU_CFG0_CKOUT0SEL GD_BITS(24,27) /*!< CKOUT0 clock source selection */ - #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ - #define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ - + #define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ + + +-#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +-#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +-#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +-#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +-#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +-#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ ++#define RCU_CFG0_SCS GD_BITS(0,1) /*!< system clock switch */ ++#define RCU_CFG0_SCSS GD_BITS(2,3) /*!< system clock switch status */ ++#define RCU_CFG0_AHBPSC GD_BITS(4,7) /*!< AHB prescaler selection */ ++#define RCU_CFG0_APB1PSC GD_BITS(8,10) /*!< APB1 prescaler selection */ ++#define RCU_CFG0_APB2PSC GD_BITS(11,13) /*!< APB2 prescaler selection */ ++#define RCU_CFG0_ADCPSC GD_BITS(14,15) /*!< ADC prescaler selection */ + #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ + #define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ +-#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +-#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ +-#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ ++#define RCU_CFG0_PLLMF GD_BITS(18,21) /*!< PLL clock multiplication factor */ ++#define RCU_CFG0_USBFSPSC GD_BITS(22,23) /*!< USBFS clock prescaler selection */ ++#define RCU_CFG0_CKOUT0SEL GD_BITS(24,27) /*!< CKOUT0 clock source selection */ + #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ + #define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ + @@ -199,7 +199,7 @@ OF SUCH DAMAGE. - #define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ - #define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ - #define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ --#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ -+#define RCU_BDCTL_RTCSRC GD_BITS(8,9) /*!< RTC clock entry selection */ - #define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ - #define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ - + #define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ + #define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ + #define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +-#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ ++#define RCU_BDCTL_RTCSRC GD_BITS(8,9) /*!< RTC clock entry selection */ + #define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ + #define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + @@ -218,16 +218,16 @@ OF SUCH DAMAGE. - #define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ - - /* RCU_CFG1 */ --#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ --#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ --#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ --#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ -+#define RCU_CFG1_PREDV0 GD_BITS(0,3) /*!< PREDV0 division factor */ -+#define RCU_CFG1_PREDV1 GD_BITS(4,7) /*!< PREDV1 division factor */ -+#define RCU_CFG1_PLL1MF GD_BITS(8,11) /*!< PLL1 clock multiplication factor */ -+#define RCU_CFG1_PLL2MF GD_BITS(12,15) /*!< PLL2 clock multiplication factor */ - #define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ - #define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ - #define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ - - /* RCU_DSV */ --#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ -+#define RCU_DSV_DSLPVS GD_BITS(0,1) /*!< deep-sleep mode voltage select */ - - /* constants definitions */ - /* define the peripheral clock enable bit position and its register index offset */ + #define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ + + /* RCU_CFG1 */ +-#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ +-#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ +-#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ +-#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ ++#define RCU_CFG1_PREDV0 GD_BITS(0,3) /*!< PREDV0 division factor */ ++#define RCU_CFG1_PREDV1 GD_BITS(4,7) /*!< PREDV1 division factor */ ++#define RCU_CFG1_PLL1MF GD_BITS(8,11) /*!< PLL1 clock multiplication factor */ ++#define RCU_CFG1_PLL2MF GD_BITS(12,15) /*!< PLL2 clock multiplication factor */ + #define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ + #define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ + #define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ + + /* RCU_DSV */ +-#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ ++#define RCU_DSV_DSLPVS GD_BITS(0,1) /*!< deep-sleep mode voltage select */ + + /* constants definitions */ + /* define the peripheral clock enable bit position and its register index offset */ @@ -423,19 +423,19 @@ typedef enum { - - /* RCU_CFG0 register bit define */ - /* system clock source select */ --#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -+#define CFG0_SCS(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) - #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ - #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ - #define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ - - /* system clock source select status */ --#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -+#define CFG0_SCSS(regval) (GD_BITS(2,3) & ((uint32_t)(regval) << 2)) - #define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ - #define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ - #define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ - - /* AHB prescaler selection */ --#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -+#define CFG0_AHBPSC(regval) (GD_BITS(4,7) & ((uint32_t)(regval) << 4)) - #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ - #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ - #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ + + /* RCU_CFG0 register bit define */ + /* system clock source select */ +-#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) ++#define CFG0_SCS(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) + #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ + #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ + #define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ + + /* system clock source select status */ +-#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) ++#define CFG0_SCSS(regval) (GD_BITS(2,3) & ((uint32_t)(regval) << 2)) + #define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ + #define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ + #define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ + + /* AHB prescaler selection */ +-#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) ++#define CFG0_AHBPSC(regval) (GD_BITS(4,7) & ((uint32_t)(regval) << 4)) + #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ + #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ + #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ @@ -447,7 +447,7 @@ typedef enum { - #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ - - /* APB1 prescaler selection */ --#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) -+#define CFG0_APB1PSC(regval) (GD_BITS(8,10) & ((uint32_t)(regval) << 8)) - #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ - #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ - #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ + #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + + /* APB1 prescaler selection */ +-#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) ++#define CFG0_APB1PSC(regval) (GD_BITS(8,10) & ((uint32_t)(regval) << 8)) + #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ + #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ + #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ @@ -455,7 +455,7 @@ typedef enum { - #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ - - /* APB2 prescaler selection */ --#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) -+#define CFG0_APB2PSC(regval) (GD_BITS(11,13) & ((uint32_t)(regval) << 11)) - #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ - #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ - #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ + #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + + /* APB2 prescaler selection */ +-#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) ++#define CFG0_APB2PSC(regval) (GD_BITS(11,13) & ((uint32_t)(regval) << 11)) + #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ + #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ + #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ @@ -477,7 +477,7 @@ typedef enum { - /* PLL clock multiplication factor */ - #define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ - --#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) -+#define CFG0_PLLMF(regval) (GD_BITS(18,21) & ((uint32_t)(regval) << 18)) - #define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ - #define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ - #define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ + /* PLL clock multiplication factor */ + #define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ + +-#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) ++#define CFG0_PLLMF(regval) (GD_BITS(18,21) & ((uint32_t)(regval) << 18)) + #define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ + #define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ + #define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ @@ -511,14 +511,14 @@ typedef enum { - #define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ - - /* USBFS prescaler select */ --#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) -+#define CFG0_USBPSC(regval) (GD_BITS(22,23) & ((uint32_t)(regval) << 22)) - #define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBFS prescaler select CK_PLL/1.5 */ - #define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBFS prescaler select CK_PLL/1 */ - #define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBFS prescaler select CK_PLL/2.5 */ - #define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBFS prescaler select CK_PLL/2 */ - - /* CKOUT0 clock source selection */ --#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -+#define CFG0_CKOUT0SEL(regval) (GD_BITS(24,27) & ((uint32_t)(regval) << 24)) - #define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ - #define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ - #define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ + #define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ + + /* USBFS prescaler select */ +-#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) ++#define CFG0_USBPSC(regval) (GD_BITS(22,23) & ((uint32_t)(regval) << 22)) + #define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBFS prescaler select CK_PLL/1.5 */ + #define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBFS prescaler select CK_PLL/1 */ + #define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBFS prescaler select CK_PLL/2.5 */ + #define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBFS prescaler select CK_PLL/2 */ + + /* CKOUT0 clock source selection */ +-#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) ++#define CFG0_CKOUT0SEL(regval) (GD_BITS(24,27) & ((uint32_t)(regval) << 24)) + #define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ + #define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ + #define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ @@ -530,14 +530,14 @@ typedef enum { - #define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ - - /* RTC clock entry selection */ --#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -+#define BDCTL_RTCSRC(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) - #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ - #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ - #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ - #define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ - - /* PREDV0 division factor */ --#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -+#define CFG1_PREDV0(regval) (GD_BITS(0,3) & ((uint32_t)(regval) << 0)) - #define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ - #define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ - #define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ + #define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ + + /* RTC clock entry selection */ +-#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) ++#define BDCTL_RTCSRC(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) + #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ + #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ + #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ + #define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ + + /* PREDV0 division factor */ +-#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) ++#define CFG1_PREDV0(regval) (GD_BITS(0,3) & ((uint32_t)(regval) << 0)) + #define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ + #define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ + #define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ @@ -556,7 +556,7 @@ typedef enum { - #define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ - - /* PREDV1 division factor */ --#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -+#define CFG1_PREDV1(regval) (GD_BITS(4,7) & ((uint32_t)(regval) << 4)) - #define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ - #define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ - #define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ + #define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ + + /* PREDV1 division factor */ +-#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) ++#define CFG1_PREDV1(regval) (GD_BITS(4,7) & ((uint32_t)(regval) << 4)) + #define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ + #define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ + #define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ @@ -575,7 +575,7 @@ typedef enum { - #define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ - - /* PLL1 clock multiplication factor */ --#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -+#define CFG1_PLL1MF(regval) (GD_BITS(8,11) & ((uint32_t)(regval) << 8)) - #define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ - #define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ - #define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ + #define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ + + /* PLL1 clock multiplication factor */ +-#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) ++#define CFG1_PLL1MF(regval) (GD_BITS(8,11) & ((uint32_t)(regval) << 8)) + #define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ + #define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ + #define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ @@ -588,7 +588,7 @@ typedef enum { - #define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ - - /* PLL2 clock multiplication factor */ --#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) -+#define CFG1_PLL2MF(regval) (GD_BITS(12,15) & ((uint32_t)(regval) << 12)) - #define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ - #define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ - #define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ + #define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ + + /* PLL2 clock multiplication factor */ +-#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) ++#define CFG1_PLL2MF(regval) (GD_BITS(12,15) & ((uint32_t)(regval) << 12)) + #define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ + #define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ + #define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ @@ -615,7 +615,7 @@ typedef enum { - - - /* deep-sleep mode voltage */ --#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -+#define DSV_DSLPVS(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) - #define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ - #define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */ - #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ + + + /* deep-sleep mode voltage */ +-#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) ++#define DSV_DSLPVS(regval) (GD_BITS(0,1) & ((uint32_t)(regval) << 0)) + #define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ + #define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */ + #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h old mode 100644 new mode 100755 @@ -1227,42 +1227,42 @@ index 8b05aa5..5ed3650 --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h @@ -68,28 +68,28 @@ OF SUCH DAMAGE. - #define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ - - /* RTC_PSCH */ --#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */ -+#define RTC_PSCH_PSC GD_BITS(0,3) /*!< prescaler high value */ - - /* RTC_PSCL */ --#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */ -+#define RTC_PSCL_PSC GD_BITS(0,15) /*!< prescaler low value */ - - /* RTC_DIVH */ --#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */ -+#define RTC_DIVH_DIV GD_BITS(0,3) /*!< divider high value */ - - /* RTC_DIVL */ --#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */ -+#define RTC_DIVL_DIV GD_BITS(0,15) /*!< divider low value */ - - /* RTC_CNTH */ --#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */ -+#define RTC_CNTH_CNT GD_BITS(0,15) /*!< counter high value */ - - /* RTC_CNTL */ --#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */ -+#define RTC_CNTL_CNT GD_BITS(0,15) /*!< counter low value */ - - /* RTC_ALRMH */ --#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */ -+#define RTC_ALRMH_ALRM GD_BITS(0,15) /*!< alarm high value */ - - /* RTC_ALRML */ --#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */ -+#define RTC_ALRML_ALRM GD_BITS(0,15) /*!< alarm low value */ - - /* constants definitions */ - /* RTC interrupt enable or disable definitions */ + #define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ + + /* RTC_PSCH */ +-#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */ ++#define RTC_PSCH_PSC GD_BITS(0,3) /*!< prescaler high value */ + + /* RTC_PSCL */ +-#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */ ++#define RTC_PSCL_PSC GD_BITS(0,15) /*!< prescaler low value */ + + /* RTC_DIVH */ +-#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */ ++#define RTC_DIVH_DIV GD_BITS(0,3) /*!< divider high value */ + + /* RTC_DIVL */ +-#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */ ++#define RTC_DIVL_DIV GD_BITS(0,15) /*!< divider low value */ + + /* RTC_CNTH */ +-#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */ ++#define RTC_CNTH_CNT GD_BITS(0,15) /*!< counter high value */ + + /* RTC_CNTL */ +-#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */ ++#define RTC_CNTL_CNT GD_BITS(0,15) /*!< counter low value */ + + /* RTC_ALRMH */ +-#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */ ++#define RTC_ALRMH_ALRM GD_BITS(0,15) /*!< alarm high value */ + + /* RTC_ALRML */ +-#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */ ++#define RTC_ALRML_ALRM GD_BITS(0,15) /*!< alarm low value */ + + /* constants definitions */ + /* RTC interrupt enable or disable definitions */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h old mode 100644 new mode 100755 @@ -1270,87 +1270,87 @@ index 417e4c6..9c1b855 --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h @@ -59,7 +59,7 @@ OF SUCH DAMAGE. - #define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ - #define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ - #define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ --#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ -+#define SPI_CTL0_PSC GD_BITS(3,5) /*!< master clock prescaler selection */ - #define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ - #define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ - #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ + #define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ + #define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ + #define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +-#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ ++#define SPI_CTL0_PSC GD_BITS(3,5) /*!< master clock prescaler selection */ + #define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ + #define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ + #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ @@ -93,29 +93,29 @@ OF SUCH DAMAGE. - #define SPI_STAT_FERR BIT(8) /*!< format error bit */ - - /* SPI_DATA */ --#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ -+#define SPI_DATA_DATA GD_BITS(0,15) /*!< data transfer register */ - - /* SPI_CRCPOLY */ --#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ -+#define SPI_CRCPOLY_CRCPOLY GD_BITS(0,15) /*!< CRC polynomial value */ - - /* SPI_RCRC */ --#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ -+#define SPI_RCRC_RCRC GD_BITS(0,15) /*!< RX CRC value */ - - /* SPI_TCRC */ --#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ -+#define SPI_TCRC_TCRC GD_BITS(0,15) /*!< TX CRC value */ - - /* SPI_I2SCTL */ - #define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ --#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ -+#define SPI_I2SCTL_DTLEN GD_BITS(1,2) /*!< data length */ - #define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ --#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ -+#define SPI_I2SCTL_I2SSTD GD_BITS(4,5) /*!< I2S standard selection */ - #define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ --#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ -+#define SPI_I2SCTL_I2SOPMOD GD_BITS(8,9) /*!< I2S operation mode */ - #define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ - #define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ - - /* SPI_I2SPSC */ --#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ -+#define SPI_I2SPSC_DIV GD_BITS(0,7) /*!< dividing factor for the prescaler */ - #define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ - #define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ - + #define SPI_STAT_FERR BIT(8) /*!< format error bit */ + + /* SPI_DATA */ +-#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ ++#define SPI_DATA_DATA GD_BITS(0,15) /*!< data transfer register */ + + /* SPI_CRCPOLY */ +-#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ ++#define SPI_CRCPOLY_CRCPOLY GD_BITS(0,15) /*!< CRC polynomial value */ + + /* SPI_RCRC */ +-#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ ++#define SPI_RCRC_RCRC GD_BITS(0,15) /*!< RX CRC value */ + + /* SPI_TCRC */ +-#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ ++#define SPI_TCRC_TCRC GD_BITS(0,15) /*!< TX CRC value */ + + /* SPI_I2SCTL */ + #define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +-#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ ++#define SPI_I2SCTL_DTLEN GD_BITS(1,2) /*!< data length */ + #define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +-#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ ++#define SPI_I2SCTL_I2SSTD GD_BITS(4,5) /*!< I2S standard selection */ + #define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +-#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ ++#define SPI_I2SCTL_I2SOPMOD GD_BITS(8,9) /*!< I2S operation mode */ + #define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ + #define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + + /* SPI_I2SPSC */ +-#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ ++#define SPI_I2SPSC_DIV GD_BITS(0,7) /*!< dividing factor for the prescaler */ + #define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ + #define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + @@ -165,7 +165,7 @@ typedef struct - #define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ - - /* SPI clock prescale factor */ --#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -+#define CTL0_PSC(regval) (GD_BITS(3,5) & ((uint32_t)(regval) << 3)) - #define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ - #define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ - #define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ + #define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + + /* SPI clock prescale factor */ +-#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) ++#define CTL0_PSC(regval) (GD_BITS(3,5) & ((uint32_t)(regval) << 3)) + #define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ + #define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ + #define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ @@ -187,7 +187,7 @@ typedef struct - #define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ - - /* I2S frame format */ --#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) -+#define I2SCTL_DTLEN(regval) (GD_BITS(1,2) & ((uint32_t)(regval) << 1)) - #define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ - #define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ - #define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ + #define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + + /* I2S frame format */ +-#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) ++#define I2SCTL_DTLEN(regval) (GD_BITS(1,2) & ((uint32_t)(regval) << 1)) + #define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ + #define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ + #define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ @@ -198,14 +198,14 @@ typedef struct - #define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ - - /* I2S operation mode */ --#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -+#define I2SCTL_I2SOPMOD(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) - #define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ - #define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ - #define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ - #define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ - - /* I2S standard */ --#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -+#define I2SCTL_I2SSTD(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) - #define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ - #define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ - #define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ + #define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + + /* I2S operation mode */ +-#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) ++#define I2SCTL_I2SOPMOD(regval) (GD_BITS(8,9) & ((uint32_t)(regval) << 8)) + #define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ + #define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ + #define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ + #define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + + /* I2S standard */ +-#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) ++#define I2SCTL_I2SSTD(regval) (GD_BITS(4,5) & ((uint32_t)(regval) << 4)) + #define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ + #define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ + #define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h old mode 100644 new mode 100755 @@ -1358,235 +1358,235 @@ index 7e0b51d..a4a394d --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h @@ -76,15 +76,15 @@ OF SUCH DAMAGE. - #define TIMER_CTL0_UPS BIT(2) /*!< update source */ - #define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ - #define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ --#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ -+#define TIMER_CTL0_CAM GD_BITS(5,6) /*!< center-aligned mode selection */ - #define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ --#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ -+#define TIMER_CTL0_CKDIV GD_BITS(8,9) /*!< clock division */ - - /* TIMER_CTL1 */ - #define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ - #define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ - #define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ --#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ -+#define TIMER_CTL1_MMC GD_BITS(4,6) /*!< master mode control */ - #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ - #define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ - #define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ + #define TIMER_CTL0_UPS BIT(2) /*!< update source */ + #define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ + #define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +-#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ ++#define TIMER_CTL0_CAM GD_BITS(5,6) /*!< center-aligned mode selection */ + #define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +-#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ ++#define TIMER_CTL0_CKDIV GD_BITS(8,9) /*!< clock division */ + + /* TIMER_CTL1 */ + #define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ + #define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ + #define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +-#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ ++#define TIMER_CTL1_MMC GD_BITS(4,6) /*!< master mode control */ + #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ + #define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ + #define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ @@ -95,11 +95,11 @@ OF SUCH DAMAGE. - #define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ - - /* TIMER_SMCFG */ --#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ --#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ -+#define TIMER_SMCFG_SMC GD_BITS(0,2) /*!< slave mode control */ -+#define TIMER_SMCFG_TRGS GD_BITS(4,6) /*!< trigger selection */ - #define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ --#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ --#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ -+#define TIMER_SMCFG_ETFC GD_BITS(8,11) /*!< external trigger filter control */ -+#define TIMER_SMCFG_ETPSC GD_BITS(12,13) /*!< external trigger prescaler */ - #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ - #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - + #define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ + + /* TIMER_SMCFG */ +-#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +-#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ ++#define TIMER_SMCFG_SMC GD_BITS(0,2) /*!< slave mode control */ ++#define TIMER_SMCFG_TRGS GD_BITS(4,6) /*!< trigger selection */ + #define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +-#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +-#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ ++#define TIMER_SMCFG_ETFC GD_BITS(8,11) /*!< external trigger filter control */ ++#define TIMER_SMCFG_ETPSC GD_BITS(12,13) /*!< external trigger prescaler */ + #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ + #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ + @@ -146,39 +146,39 @@ OF SUCH DAMAGE. - - /* TIMER_CHCTL0 */ - /* output compare mode */ --#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ -+#define TIMER_CHCTL0_CH0MS GD_BITS(0,1) /*!< channel 0 mode selection */ - #define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ - #define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ --#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ -+#define TIMER_CHCTL0_CH0COMCTL GD_BITS(4,6) /*!< channel 0 output compare control */ - #define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ --#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ -+#define TIMER_CHCTL0_CH1MS GD_BITS(8,9) /*!< channel 1 mode selection */ - #define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ - #define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ --#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ -+#define TIMER_CHCTL0_CH1COMCTL GD_BITS(12,14) /*!< channel 1 output compare control */ - #define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ - /* input capture mode */ --#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ --#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ --#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ --#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ -+#define TIMER_CHCTL0_CH0CAPPSC GD_BITS(2,3) /*!< channel 0 input capture prescaler */ -+#define TIMER_CHCTL0_CH0CAPFLT GD_BITS(4,7) /*!< channel 0 input capture filter control */ -+#define TIMER_CHCTL0_CH1CAPPSC GD_BITS(10,11) /*!< channel 1 input capture prescaler */ -+#define TIMER_CHCTL0_CH1CAPFLT GD_BITS(12,15) /*!< channel 1 input capture filter control */ - - /* TIMER_CHCTL1 */ - /* output compare mode */ --#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ -+#define TIMER_CHCTL1_CH2MS GD_BITS(0,1) /*!< channel 2 mode selection */ - #define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ - #define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ --#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ -+#define TIMER_CHCTL1_CH2COMCTL GD_BITS(4,6) /*!< channel 2 output compare control */ - #define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ --#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ -+#define TIMER_CHCTL1_CH3MS GD_BITS(8,9) /*!< channel 3 mode selection */ - #define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ - #define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ --#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ -+#define TIMER_CHCTL1_CH3COMCTL GD_BITS(12,14) /*!< channel 3 output compare control */ - #define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ - /* input capture mode */ --#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ --#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ --#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ --#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ -+#define TIMER_CHCTL1_CH2CAPPSC GD_BITS(2,3) /*!< channel 2 input capture prescaler */ -+#define TIMER_CHCTL1_CH2CAPFLT GD_BITS(4,7) /*!< channel 2 input capture filter control */ -+#define TIMER_CHCTL1_CH3CAPPSC GD_BITS(10,11) /*!< channel 3 input capture prescaler */ -+#define TIMER_CHCTL1_CH3CAPFLT GD_BITS(12,15) /*!< channel 3 input capture filter control */ - - /* TIMER_CHCTL2 */ - #define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ + + /* TIMER_CHCTL0 */ + /* output compare mode */ +-#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ ++#define TIMER_CHCTL0_CH0MS GD_BITS(0,1) /*!< channel 0 mode selection */ + #define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ + #define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +-#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ ++#define TIMER_CHCTL0_CH0COMCTL GD_BITS(4,6) /*!< channel 0 output compare control */ + #define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +-#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ ++#define TIMER_CHCTL0_CH1MS GD_BITS(8,9) /*!< channel 1 mode selection */ + #define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ + #define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +-#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ ++#define TIMER_CHCTL0_CH1COMCTL GD_BITS(12,14) /*!< channel 1 output compare control */ + #define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ + /* input capture mode */ +-#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +-#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +-#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +-#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ ++#define TIMER_CHCTL0_CH0CAPPSC GD_BITS(2,3) /*!< channel 0 input capture prescaler */ ++#define TIMER_CHCTL0_CH0CAPFLT GD_BITS(4,7) /*!< channel 0 input capture filter control */ ++#define TIMER_CHCTL0_CH1CAPPSC GD_BITS(10,11) /*!< channel 1 input capture prescaler */ ++#define TIMER_CHCTL0_CH1CAPFLT GD_BITS(12,15) /*!< channel 1 input capture filter control */ + + /* TIMER_CHCTL1 */ + /* output compare mode */ +-#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ ++#define TIMER_CHCTL1_CH2MS GD_BITS(0,1) /*!< channel 2 mode selection */ + #define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ + #define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +-#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ ++#define TIMER_CHCTL1_CH2COMCTL GD_BITS(4,6) /*!< channel 2 output compare control */ + #define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +-#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ ++#define TIMER_CHCTL1_CH3MS GD_BITS(8,9) /*!< channel 3 mode selection */ + #define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ + #define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +-#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ ++#define TIMER_CHCTL1_CH3COMCTL GD_BITS(12,14) /*!< channel 3 output compare control */ + #define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ + /* input capture mode */ +-#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +-#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +-#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +-#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ ++#define TIMER_CHCTL1_CH2CAPPSC GD_BITS(2,3) /*!< channel 2 input capture prescaler */ ++#define TIMER_CHCTL1_CH2CAPFLT GD_BITS(4,7) /*!< channel 2 input capture filter control */ ++#define TIMER_CHCTL1_CH3CAPPSC GD_BITS(10,11) /*!< channel 3 input capture prescaler */ ++#define TIMER_CHCTL1_CH3CAPFLT GD_BITS(12,15) /*!< channel 3 input capture filter control */ + + /* TIMER_CHCTL2 */ + #define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ @@ -197,32 +197,32 @@ OF SUCH DAMAGE. - #define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ - - /* TIMER_CNT */ --#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ -+#define TIMER_CNT_CNT GD_BITS(0,15) /*!< 16 bit timer counter */ - - /* TIMER_PSC */ --#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ -+#define TIMER_PSC_PSC GD_BITS(0,15) /*!< prescaler value of the counter clock */ - - /* TIMER_CAR */ --#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ -+#define TIMER_CAR_CARL GD_BITS(0,15) /*!< 16 bit counter auto reload value */ - - /* TIMER_CREP */ --#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ -+#define TIMER_CREP_CREP GD_BITS(0,7) /*!< counter repetition value */ - - /* TIMER_CH0CV */ --#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ -+#define TIMER_CH0CV_CH0VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ - - /* TIMER_CH1CV */ --#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ -+#define TIMER_CH1CV_CH1VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ - - /* TIMER_CH2CV */ --#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ -+#define TIMER_CH2CV_CH2VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ - - /* TIMER_CH3CV */ --#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ -+#define TIMER_CH3CV_CH3VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ - - /* TIMER_CCHP */ --#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ --#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ -+#define TIMER_CCHP_DTCFG GD_BITS(0,7) /*!< dead time configure */ -+#define TIMER_CCHP_PROT GD_BITS(8,9) /*!< complementary register protect control */ - #define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ - #define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ - #define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ + #define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ + + /* TIMER_CNT */ +-#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ ++#define TIMER_CNT_CNT GD_BITS(0,15) /*!< 16 bit timer counter */ + + /* TIMER_PSC */ +-#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ ++#define TIMER_PSC_PSC GD_BITS(0,15) /*!< prescaler value of the counter clock */ + + /* TIMER_CAR */ +-#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ ++#define TIMER_CAR_CARL GD_BITS(0,15) /*!< 16 bit counter auto reload value */ + + /* TIMER_CREP */ +-#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ ++#define TIMER_CREP_CREP GD_BITS(0,7) /*!< counter repetition value */ + + /* TIMER_CH0CV */ +-#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ ++#define TIMER_CH0CV_CH0VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ + + /* TIMER_CH1CV */ +-#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ ++#define TIMER_CH1CV_CH1VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ + + /* TIMER_CH2CV */ +-#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ ++#define TIMER_CH2CV_CH2VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ + + /* TIMER_CH3CV */ +-#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ ++#define TIMER_CH3CV_CH3VAL GD_BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ + + /* TIMER_CCHP */ +-#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +-#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ ++#define TIMER_CCHP_DTCFG GD_BITS(0,7) /*!< dead time configure */ ++#define TIMER_CCHP_PROT GD_BITS(8,9) /*!< complementary register protect control */ + #define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ + #define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ + #define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ @@ -231,11 +231,11 @@ OF SUCH DAMAGE. - #define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ - - /* TIMER_DMACFG */ --#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ --#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ -+#define TIMER_DMACFG_DMATA GD_BITS(0,4) /*!< DMA transfer access start address */ -+#define TIMER_DMACFG_DMATC GD_BITS(8,12) /*!< DMA transfer count */ - - /* TIMER_DMATB */ --#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ -+#define TIMER_DMATB_DMATB GD_BITS(0,15) /*!< DMA transfer buffer address */ - - /* constants definitions */ - /* TIMER init parameter struct definitions */ + #define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + + /* TIMER_DMACFG */ +-#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ +-#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ ++#define TIMER_DMACFG_DMATA GD_BITS(0,4) /*!< DMA transfer access start address */ ++#define TIMER_DMACFG_DMATC GD_BITS(8,12) /*!< DMA transfer count */ + + /* TIMER_DMATB */ +-#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ ++#define TIMER_DMATB_DMATB GD_BITS(0,15) /*!< DMA transfer buffer address */ + + /* constants definitions */ + /* TIMER init parameter struct definitions */ @@ -329,7 +329,7 @@ typedef struct - #define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ - - /* DMA access base address */ --#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) -+#define DMACFG_DMATA(regval) (GD_BITS(0, 4) & ((uint32_t)(regval) << 0U)) - #define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ - #define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ - #define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ + #define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ + + /* DMA access base address */ +-#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) ++#define DMACFG_DMATA(regval) (GD_BITS(0, 4) & ((uint32_t)(regval) << 0U)) + #define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ + #define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ + #define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ @@ -351,7 +351,7 @@ typedef struct - #define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ - - /* DMA access burst length */ --#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) -+#define DMACFG_DMATC(regval) (GD_BITS(8, 12) & ((uint32_t)(regval) << 8U)) - #define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ - #define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ - #define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ + #define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ + + /* DMA access burst length */ +-#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) ++#define DMACFG_DMATC(regval) (GD_BITS(8, 12) & ((uint32_t)(regval) << 8U)) + #define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ + #define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ + #define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ @@ -382,7 +382,7 @@ typedef struct - #define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ - - /* center-aligned mode selection */ --#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) -+#define CTL0_CAM(regval) ((uint16_t)(GD_BITS(5, 6) & ((uint32_t)(regval) << 5U))) - #define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ - #define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ - #define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ + #define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ + + /* center-aligned mode selection */ +-#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) ++#define CTL0_CAM(regval) ((uint16_t)(GD_BITS(5, 6) & ((uint32_t)(regval) << 5U))) + #define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ + #define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ + #define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ @@ -397,7 +397,7 @@ typedef struct - #define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ - - /* specify division ratio between TIMER clock and dead-time and sampling clock */ --#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -+#define CTL0_CKDIV(regval) ((uint16_t)(GD_BITS(8, 9) & ((uint32_t)(regval) << 8U))) - #define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ - #define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ - #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ + #define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ + + /* specify division ratio between TIMER clock and dead-time and sampling clock */ +-#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) ++#define CTL0_CKDIV(regval) ((uint16_t)(GD_BITS(8, 9) & ((uint32_t)(regval) << 8U))) + #define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ + #define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ + #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ @@ -428,7 +428,7 @@ typedef struct - #define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ - - /* complementary register protect control */ --#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -+#define CCHP_PROT(regval) ((uint16_t)(GD_BITS(8, 9) & ((uint32_t)(regval) << 8U))) - #define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ - #define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ - #define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ + #define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ + + /* complementary register protect control */ +-#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) ++#define CCHP_PROT(regval) ((uint16_t)(GD_BITS(8, 9) & ((uint32_t)(regval) << 8U))) + #define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ + #define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ + #define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ @@ -511,7 +511,7 @@ typedef struct - #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ - - /* trigger selection */ --#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -+#define SMCFG_TRGSEL(regval) (GD_BITS(4, 6) & ((uint32_t)(regval) << 4U)) - #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ - #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ - #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ + #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + + /* trigger selection */ +-#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) ++#define SMCFG_TRGSEL(regval) (GD_BITS(4, 6) & ((uint32_t)(regval) << 4U)) + #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ + #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ + #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ @@ -522,7 +522,7 @@ typedef struct - #define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */ - - /* master mode control */ --#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -+#define CTL1_MMC(regval) (GD_BITS(4, 6) & ((uint32_t)(regval) << 4U)) - #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ - #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ - #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ + #define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */ + + /* master mode control */ +-#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) ++#define CTL1_MMC(regval) (GD_BITS(4, 6) & ((uint32_t)(regval) << 4U)) + #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ + #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ + #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ @@ -533,7 +533,7 @@ typedef struct - #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ - - /* slave mode control */ --#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) -+#define SMCFG_SMC(regval) (GD_BITS(0, 2) & ((uint32_t)(regval) << 0U)) - #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ - #define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ - #define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ + #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + + /* slave mode control */ +-#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) ++#define SMCFG_SMC(regval) (GD_BITS(0, 2) & ((uint32_t)(regval) << 0U)) + #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ + #define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ + #define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ @@ -548,7 +548,7 @@ typedef struct - #define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ - - /* external trigger prescaler */ --#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) -+#define SMCFG_ETPSC(regval) (GD_BITS(12, 13) & ((uint32_t)(regval) << 12U)) - #define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ - #define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ - #define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ + #define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ + + /* external trigger prescaler */ +-#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) ++#define SMCFG_ETPSC(regval) (GD_BITS(12, 13) & ((uint32_t)(regval) << 12U)) + #define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ + #define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ + #define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h old mode 100644 new mode 100755 @@ -1594,66 +1594,66 @@ index bbf5462..276d91c --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h @@ -69,11 +69,11 @@ OF SUCH DAMAGE. - #define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ - - /* USARTx_DATA */ --#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ -+#define USART_DATA_DATA GD_BITS(0,8) /*!< transmit or read data value */ - - /* USARTx_BAUD */ --#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ --#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ -+#define USART_BAUD_FRADIV GD_BITS(0,3) /*!< fraction part of baud-rate divider */ -+#define USART_BAUD_INTDIV GD_BITS(4,15) /*!< integer part of baud-rate divider */ - - /* USARTx_CTL0 */ - #define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ + #define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ + + /* USARTx_DATA */ +-#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ ++#define USART_DATA_DATA GD_BITS(0,8) /*!< transmit or read data value */ + + /* USARTx_BAUD */ +-#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +-#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ ++#define USART_BAUD_FRADIV GD_BITS(0,3) /*!< fraction part of baud-rate divider */ ++#define USART_BAUD_INTDIV GD_BITS(4,15) /*!< integer part of baud-rate divider */ + + /* USARTx_CTL0 */ + #define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ @@ -92,14 +92,14 @@ OF SUCH DAMAGE. - #define USART_CTL0_UEN BIT(13) /*!< USART enable */ - - /* USARTx_CTL1 */ --#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ -+#define USART_CTL1_ADDR GD_BITS(0,3) /*!< address of USART */ - #define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ - #define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ - #define USART_CTL1_CLEN BIT(8) /*!< CK length */ - #define USART_CTL1_CPH BIT(9) /*!< CK phase */ - #define USART_CTL1_CPL BIT(10) /*!< CK polarity */ - #define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ --#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ -+#define USART_CTL1_STB GD_BITS(12,13) /*!< STOP bits length */ - #define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ - - /* USARTx_CTL2 */ + #define USART_CTL0_UEN BIT(13) /*!< USART enable */ + + /* USARTx_CTL1 */ +-#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ ++#define USART_CTL1_ADDR GD_BITS(0,3) /*!< address of USART */ + #define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ + #define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ + #define USART_CTL1_CLEN BIT(8) /*!< CK length */ + #define USART_CTL1_CPH BIT(9) /*!< CK phase */ + #define USART_CTL1_CPL BIT(10) /*!< CK polarity */ + #define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ +-#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ ++#define USART_CTL1_STB GD_BITS(12,13) /*!< STOP bits length */ + #define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ + + /* USARTx_CTL2 */ @@ -116,8 +116,8 @@ OF SUCH DAMAGE. - #define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ - - /* USARTx_GP */ --#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ --#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ -+#define USART_GP_PSC GD_BITS(0,7) /*!< prescaler value for dividing the system clock */ -+#define USART_GP_GUAT GD_BITS(8,15) /*!< guard time value in smartcard mode */ - - /* constants definitions */ - /* define the USART bit position and its register index offset */ + #define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ + + /* USARTx_GP */ +-#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +-#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ ++#define USART_GP_PSC GD_BITS(0,7) /*!< prescaler value for dividing the system clock */ ++#define USART_GP_GUAT GD_BITS(8,15) /*!< guard time value in smartcard mode */ + + /* constants definitions */ + /* define the USART bit position and its register index offset */ @@ -197,7 +197,7 @@ typedef enum - #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ - - /* USART parity bits definitions */ --#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -+#define CTL0_PM(regval) (GD_BITS(9,10) & ((uint32_t)(regval) << 9)) - #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ - #define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ - #define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + + /* USART parity bits definitions */ +-#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) ++#define CTL0_PM(regval) (GD_BITS(9,10) & ((uint32_t)(regval) << 9)) + #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ + #define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ + #define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ @@ -213,7 +213,7 @@ typedef enum - #define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ - - /* USART stop bits definitions */ --#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -+#define CTL1_STB(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) - #define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ - #define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ - #define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ + #define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + + /* USART stop bits definitions */ +-#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) ++#define CTL1_STB(regval) (GD_BITS(12,13) & ((uint32_t)(regval) << 12)) + #define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ + #define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ + #define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h old mode 100644 new mode 100755 @@ -1661,29 +1661,29 @@ index a6ce3ea..722d59e --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h @@ -48,19 +48,19 @@ OF SUCH DAMAGE. - - /* bits definitions */ - /* WWDGT_CTL */ --#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ -+#define WWDGT_CTL_CNT GD_BITS(0,6) /*!< WWDGT counter value */ - #define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ - - /* WWDGT_CFG */ --#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ --#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ -+#define WWDGT_CFG_WIN GD_BITS(0,6) /*!< WWDGT counter window value */ -+#define WWDGT_CFG_PSC GD_BITS(7,8) /*!< WWDGT prescaler divider value */ - #define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ - - /* WWDGT_STAT */ - #define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ - - /* constants definitions */ --#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ -+#define CFG_PSC(regval) (GD_BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ - #define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ - #define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ - #define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ + + /* bits definitions */ + /* WWDGT_CTL */ +-#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ ++#define WWDGT_CTL_CNT GD_BITS(0,6) /*!< WWDGT counter value */ + #define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + + /* WWDGT_CFG */ +-#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +-#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ ++#define WWDGT_CFG_WIN GD_BITS(0,6) /*!< WWDGT counter window value */ ++#define WWDGT_CFG_PSC GD_BITS(7,8) /*!< WWDGT prescaler divider value */ + #define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ + + /* WWDGT_STAT */ + #define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ + + /* constants definitions */ +-#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ ++#define CFG_PSC(regval) (GD_BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ + #define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ + #define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ + #define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c old mode 100644 new mode 100755 @@ -1691,17 +1691,17 @@ index 918e972..7093ad8 --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c @@ -36,9 +36,9 @@ OF SUCH DAMAGE. - #include "gd32vf103_fwdgt.h" - - /* write value to FWDGT_CTL_CMD bit field */ --#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -+#define CTL_CMD(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) - /* write value to FWDGT_RLD_RLD bit field */ --#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) -+#define RLD_RLD(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) - - /*! - \brief enable write access to FWDGT_PSC and FWDGT_RLD + #include "gd32vf103_fwdgt.h" + + /* write value to FWDGT_CTL_CMD bit field */ +-#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) ++#define CTL_CMD(regval) (GD_BITS(0,15) & ((uint32_t)(regval) << 0)) + /* write value to FWDGT_RLD_RLD bit field */ +-#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) ++#define RLD_RLD(regval) (GD_BITS(0,11) & ((uint32_t)(regval) << 0)) + + /*! + \brief enable write access to FWDGT_PSC and FWDGT_RLD diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c old mode 100644 new mode 100755 @@ -1709,17 +1709,17 @@ index 90e2c3e..197270c --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c @@ -36,9 +36,9 @@ OF SUCH DAMAGE. - #include "gd32vf103_wwdgt.h" - - /* write value to WWDGT_CTL_CNT bit field */ --#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -+#define CTL_CNT(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) - /* write value to WWDGT_CFG_WIN bit field */ --#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -+#define CFG_WIN(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) - - /*! - \brief reset the window watchdog timer configuration + #include "gd32vf103_wwdgt.h" + + /* write value to WWDGT_CTL_CNT bit field */ +-#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) ++#define CTL_CNT(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) + /* write value to WWDGT_CFG_WIN bit field */ +-#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) ++#define CFG_WIN(regval) (GD_BITS(0,6) & ((uint32_t)(regval) << 0)) + + /*! + \brief reset the window watchdog timer configuration diff --git a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/gd32vf103.h b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/gd32vf103.h old mode 100644 new mode 100755 @@ -1727,28 +1727,28 @@ index d3fb610..c2ba19b --- a/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/gd32vf103.h +++ b/GD32VF103_Firmware_Library/Firmware/GD32VF103_standard_peripheral/gd32vf103.h @@ -186,8 +186,8 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) - #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) - #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) --#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) --#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) -+#define GD_BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -+#define GET_BITS(regval, start, end) (((regval) & GD_BITS((start),(end))) >> (start)) - - /* main flash and SRAM memory map */ - #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ + #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) + #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) + #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +-#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +-#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) ++#define GD_BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) ++#define GET_BITS(regval, start, end) (((regval) & GD_BITS((start),(end))) >> (start)) + + /* main flash and SRAM memory map */ + #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ diff --git a/GD32VF103_Firmware_Library/Firmware/RISCV/drivers/n200_func.h b/GD32VF103_Firmware_Library/Firmware/RISCV/drivers/n200_func.h index ce5c92c..6de28a5 100644 --- a/GD32VF103_Firmware_Library/Firmware/RISCV/drivers/n200_func.h +++ b/GD32VF103_Firmware_Library/Firmware/RISCV/drivers/n200_func.h @@ -7,6 +7,7 @@ - #include - #include "n200_timer.h" - #include "n200_eclic.h" -+#include "los_typedef.h" - - #define ECLIC_GROUP_LEVEL0_PRIO4 0 - #define ECLIC_GROUP_LEVEL1_PRIO3 1 + #include + #include "n200_timer.h" + #include "n200_eclic.h" ++#include "los_typedef.h" + + #define ECLIC_GROUP_LEVEL0_PRIO4 0 + #define ECLIC_GROUP_LEVEL1_PRIO3 1 diff --git a/GD32VF103_Firmware_Library/Firmware/RISCV/stubs/sbrk.c b/GD32VF103_Firmware_Library/Firmware/RISCV/stubs/sbrk.c old mode 100644 new mode 100755 -- Gitee